Tests
dashboard | hierarchy | modlist | groups | tests | asserts
Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
97.79 97.04 93.25 97.88 100.00 99.02 98.04 99.30


Total test records in report: 484
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html
T273 /workspace/coverage/default/38.rom_ctrl_max_throughput_chk.2579417141 Feb 04 12:48:13 PM PST 24 Feb 04 12:48:19 PM PST 24 361396367 ps
T274 /workspace/coverage/default/41.rom_ctrl_max_throughput_chk.3282401989 Feb 04 12:48:18 PM PST 24 Feb 04 12:48:38 PM PST 24 2226204736 ps
T275 /workspace/coverage/default/27.rom_ctrl_max_throughput_chk.1143364767 Feb 04 12:47:35 PM PST 24 Feb 04 12:47:54 PM PST 24 4487304386 ps
T276 /workspace/coverage/default/21.rom_ctrl_stress_all_with_rand_reset.593568886 Feb 04 12:47:29 PM PST 24 Feb 04 01:02:20 PM PST 24 96766118771 ps
T277 /workspace/coverage/default/0.rom_ctrl_kmac_err_chk.4252166537 Feb 04 12:47:04 PM PST 24 Feb 04 12:47:15 PM PST 24 2071983652 ps
T278 /workspace/coverage/default/35.rom_ctrl_kmac_err_chk.2789025584 Feb 04 12:47:54 PM PST 24 Feb 04 12:48:04 PM PST 24 333930174 ps
T279 /workspace/coverage/default/20.rom_ctrl_smoke.3422229614 Feb 04 12:47:33 PM PST 24 Feb 04 12:47:47 PM PST 24 187570809 ps
T280 /workspace/coverage/default/40.rom_ctrl_alert_test.3797532988 Feb 04 12:48:06 PM PST 24 Feb 04 12:48:24 PM PST 24 40535784906 ps
T281 /workspace/coverage/default/31.rom_ctrl_kmac_err_chk.2709529901 Feb 04 12:47:54 PM PST 24 Feb 04 12:48:29 PM PST 24 17152243184 ps
T282 /workspace/coverage/default/33.rom_ctrl_stress_all_with_rand_reset.3092497618 Feb 04 12:47:46 PM PST 24 Feb 04 01:16:13 PM PST 24 47253672835 ps
T283 /workspace/coverage/default/12.rom_ctrl_max_throughput_chk.4068417307 Feb 04 12:47:35 PM PST 24 Feb 04 12:47:49 PM PST 24 2167259817 ps
T284 /workspace/coverage/default/17.rom_ctrl_stress_all_with_rand_reset.2054672681 Feb 04 12:47:32 PM PST 24 Feb 04 12:59:41 PM PST 24 16376111821 ps
T285 /workspace/coverage/default/38.rom_ctrl_smoke.1332039960 Feb 04 12:48:12 PM PST 24 Feb 04 12:48:38 PM PST 24 10383167698 ps
T286 /workspace/coverage/default/47.rom_ctrl_alert_test.1373934401 Feb 04 12:48:09 PM PST 24 Feb 04 12:48:22 PM PST 24 1409214487 ps
T287 /workspace/coverage/default/48.rom_ctrl_kmac_err_chk.1919760571 Feb 04 12:48:19 PM PST 24 Feb 04 12:48:31 PM PST 24 172394986 ps
T288 /workspace/coverage/default/23.rom_ctrl_corrupt_sig_fatal_chk.1230187892 Feb 04 12:47:35 PM PST 24 Feb 04 12:52:02 PM PST 24 38450430975 ps
T289 /workspace/coverage/default/33.rom_ctrl_kmac_err_chk.20903708 Feb 04 12:47:43 PM PST 24 Feb 04 12:48:18 PM PST 24 22620348951 ps
T290 /workspace/coverage/default/29.rom_ctrl_stress_all.3887525054 Feb 04 12:47:48 PM PST 24 Feb 04 12:48:06 PM PST 24 4133465039 ps
T291 /workspace/coverage/default/2.rom_ctrl_stress_all_with_rand_reset.782637501 Feb 04 12:47:05 PM PST 24 Feb 04 02:05:20 PM PST 24 72710738153 ps
T292 /workspace/coverage/default/21.rom_ctrl_kmac_err_chk.4008164741 Feb 04 12:47:29 PM PST 24 Feb 04 12:47:54 PM PST 24 6495808454 ps
T293 /workspace/coverage/default/41.rom_ctrl_stress_all_with_rand_reset.1007683773 Feb 04 12:48:10 PM PST 24 Feb 04 02:06:26 PM PST 24 122201190637 ps
T294 /workspace/coverage/default/23.rom_ctrl_stress_all.283503293 Feb 04 12:47:32 PM PST 24 Feb 04 12:49:26 PM PST 24 57394004667 ps
T295 /workspace/coverage/default/14.rom_ctrl_alert_test.950826171 Feb 04 12:47:31 PM PST 24 Feb 04 12:47:47 PM PST 24 18675856006 ps
T296 /workspace/coverage/default/45.rom_ctrl_corrupt_sig_fatal_chk.2322083214 Feb 04 12:48:19 PM PST 24 Feb 04 12:53:23 PM PST 24 554486666519 ps
T297 /workspace/coverage/default/3.rom_ctrl_stress_all.823066690 Feb 04 12:47:08 PM PST 24 Feb 04 12:47:56 PM PST 24 4139140631 ps
T298 /workspace/coverage/default/37.rom_ctrl_stress_all.593935113 Feb 04 12:48:10 PM PST 24 Feb 04 12:48:37 PM PST 24 1218899729 ps
T299 /workspace/coverage/default/20.rom_ctrl_alert_test.3465356935 Feb 04 12:47:29 PM PST 24 Feb 04 12:47:43 PM PST 24 600569959 ps
T300 /workspace/coverage/default/22.rom_ctrl_max_throughput_chk.1877267817 Feb 04 12:47:32 PM PST 24 Feb 04 12:47:48 PM PST 24 4975637290 ps
T301 /workspace/coverage/default/2.rom_ctrl_corrupt_sig_fatal_chk.1776697020 Feb 04 12:47:05 PM PST 24 Feb 04 12:50:36 PM PST 24 113186763105 ps
T302 /workspace/coverage/default/2.rom_ctrl_kmac_err_chk.3189115373 Feb 04 12:47:05 PM PST 24 Feb 04 12:47:29 PM PST 24 2151475063 ps
T303 /workspace/coverage/default/36.rom_ctrl_alert_test.3648896397 Feb 04 12:48:09 PM PST 24 Feb 04 12:48:23 PM PST 24 9811526820 ps
T304 /workspace/coverage/default/35.rom_ctrl_smoke.1406966318 Feb 04 12:47:46 PM PST 24 Feb 04 12:48:05 PM PST 24 18123864354 ps
T305 /workspace/coverage/default/34.rom_ctrl_smoke.3751534347 Feb 04 12:47:48 PM PST 24 Feb 04 12:48:03 PM PST 24 1430081915 ps
T306 /workspace/coverage/default/19.rom_ctrl_max_throughput_chk.85061100 Feb 04 12:47:34 PM PST 24 Feb 04 12:47:54 PM PST 24 2241869602 ps
T307 /workspace/coverage/default/14.rom_ctrl_max_throughput_chk.612574314 Feb 04 12:47:35 PM PST 24 Feb 04 12:47:59 PM PST 24 7545920212 ps
T308 /workspace/coverage/default/37.rom_ctrl_smoke.3902327920 Feb 04 12:48:06 PM PST 24 Feb 04 12:48:43 PM PST 24 4474798560 ps
T309 /workspace/coverage/default/12.rom_ctrl_kmac_err_chk.4222198962 Feb 04 12:47:32 PM PST 24 Feb 04 12:48:00 PM PST 24 2305126192 ps
T310 /workspace/coverage/default/2.rom_ctrl_alert_test.238497121 Feb 04 12:47:09 PM PST 24 Feb 04 12:47:24 PM PST 24 1190590983 ps
T311 /workspace/coverage/default/23.rom_ctrl_smoke.2149490660 Feb 04 12:47:26 PM PST 24 Feb 04 12:48:05 PM PST 24 8241790883 ps
T312 /workspace/coverage/default/37.rom_ctrl_corrupt_sig_fatal_chk.3812059768 Feb 04 12:48:03 PM PST 24 Feb 04 12:50:30 PM PST 24 49335160941 ps
T313 /workspace/coverage/default/21.rom_ctrl_corrupt_sig_fatal_chk.3044275536 Feb 04 12:47:28 PM PST 24 Feb 04 12:49:31 PM PST 24 2054503122 ps
T314 /workspace/coverage/default/15.rom_ctrl_corrupt_sig_fatal_chk.2270000327 Feb 04 12:47:29 PM PST 24 Feb 04 12:52:15 PM PST 24 46608074348 ps
T315 /workspace/coverage/default/3.rom_ctrl_corrupt_sig_fatal_chk.1863240793 Feb 04 12:47:09 PM PST 24 Feb 04 12:53:59 PM PST 24 80606369616 ps
T316 /workspace/coverage/default/44.rom_ctrl_corrupt_sig_fatal_chk.1130185304 Feb 04 12:48:10 PM PST 24 Feb 04 12:52:12 PM PST 24 23906002896 ps
T317 /workspace/coverage/default/41.rom_ctrl_kmac_err_chk.1827796020 Feb 04 12:48:07 PM PST 24 Feb 04 12:48:23 PM PST 24 2640209235 ps
T318 /workspace/coverage/default/6.rom_ctrl_max_throughput_chk.3580543645 Feb 04 12:47:23 PM PST 24 Feb 04 12:47:35 PM PST 24 1947077788 ps
T117 /workspace/coverage/default/35.rom_ctrl_stress_all_with_rand_reset.235436282 Feb 04 12:47:51 PM PST 24 Feb 04 01:36:43 PM PST 24 102226596100 ps
T319 /workspace/coverage/default/25.rom_ctrl_stress_all_with_rand_reset.2324063703 Feb 04 12:47:42 PM PST 24 Feb 04 02:30:37 PM PST 24 336367200124 ps
T320 /workspace/coverage/default/34.rom_ctrl_max_throughput_chk.2458119564 Feb 04 12:47:49 PM PST 24 Feb 04 12:48:00 PM PST 24 6061276944 ps
T321 /workspace/coverage/default/28.rom_ctrl_kmac_err_chk.1015133725 Feb 04 12:47:46 PM PST 24 Feb 04 12:48:16 PM PST 24 13199614059 ps
T322 /workspace/coverage/default/22.rom_ctrl_corrupt_sig_fatal_chk.1915366491 Feb 04 12:47:31 PM PST 24 Feb 04 12:50:54 PM PST 24 5114462654 ps
T323 /workspace/coverage/default/6.rom_ctrl_kmac_err_chk.2155369742 Feb 04 12:47:23 PM PST 24 Feb 04 12:47:43 PM PST 24 1129697872 ps
T324 /workspace/coverage/default/18.rom_ctrl_alert_test.2394996573 Feb 04 12:47:42 PM PST 24 Feb 04 12:47:48 PM PST 24 90184794 ps
T325 /workspace/coverage/default/49.rom_ctrl_smoke.4133475438 Feb 04 12:48:31 PM PST 24 Feb 04 12:49:10 PM PST 24 4203637736 ps
T326 /workspace/coverage/default/9.rom_ctrl_corrupt_sig_fatal_chk.3538870642 Feb 04 12:47:22 PM PST 24 Feb 04 12:48:45 PM PST 24 7810316594 ps
T327 /workspace/coverage/default/28.rom_ctrl_corrupt_sig_fatal_chk.2276823320 Feb 04 12:47:46 PM PST 24 Feb 04 12:49:39 PM PST 24 5517125077 ps
T328 /workspace/coverage/default/33.rom_ctrl_corrupt_sig_fatal_chk.1769383773 Feb 04 12:47:46 PM PST 24 Feb 04 12:51:19 PM PST 24 92090063562 ps
T329 /workspace/coverage/default/34.rom_ctrl_kmac_err_chk.1255004400 Feb 04 12:47:42 PM PST 24 Feb 04 12:48:15 PM PST 24 3741239656 ps
T330 /workspace/coverage/default/23.rom_ctrl_kmac_err_chk.3618906277 Feb 04 12:47:31 PM PST 24 Feb 04 12:47:44 PM PST 24 692637888 ps
T331 /workspace/coverage/default/8.rom_ctrl_kmac_err_chk.528552077 Feb 04 12:47:24 PM PST 24 Feb 04 12:47:52 PM PST 24 5301284670 ps
T332 /workspace/coverage/default/10.rom_ctrl_max_throughput_chk.1707849901 Feb 04 12:47:22 PM PST 24 Feb 04 12:47:32 PM PST 24 131122026 ps
T333 /workspace/coverage/default/38.rom_ctrl_alert_test.871155501 Feb 04 12:48:18 PM PST 24 Feb 04 12:48:26 PM PST 24 692708445 ps
T334 /workspace/coverage/default/30.rom_ctrl_stress_all_with_rand_reset.112205183 Feb 04 12:47:51 PM PST 24 Feb 04 02:36:15 PM PST 24 23225563924 ps
T335 /workspace/coverage/default/3.rom_ctrl_alert_test.93026699 Feb 04 12:47:13 PM PST 24 Feb 04 12:47:26 PM PST 24 2553320808 ps
T336 /workspace/coverage/default/16.rom_ctrl_smoke.574682873 Feb 04 12:47:31 PM PST 24 Feb 04 12:47:58 PM PST 24 6933582308 ps
T337 /workspace/coverage/default/23.rom_ctrl_alert_test.3754400378 Feb 04 12:47:33 PM PST 24 Feb 04 12:47:41 PM PST 24 110121208 ps
T338 /workspace/coverage/default/4.rom_ctrl_smoke.3700100807 Feb 04 12:47:09 PM PST 24 Feb 04 12:47:37 PM PST 24 9804648993 ps
T339 /workspace/coverage/default/39.rom_ctrl_corrupt_sig_fatal_chk.4037843123 Feb 04 12:48:07 PM PST 24 Feb 04 12:51:08 PM PST 24 30733235513 ps
T340 /workspace/coverage/default/7.rom_ctrl_stress_all_with_rand_reset.1799995621 Feb 04 12:47:30 PM PST 24 Feb 04 12:56:24 PM PST 24 13037903866 ps
T341 /workspace/coverage/default/20.rom_ctrl_max_throughput_chk.3508769417 Feb 04 12:47:35 PM PST 24 Feb 04 12:47:57 PM PST 24 3922666813 ps
T342 /workspace/coverage/default/18.rom_ctrl_max_throughput_chk.2144665096 Feb 04 12:47:42 PM PST 24 Feb 04 12:48:00 PM PST 24 6790792371 ps
T343 /workspace/coverage/default/42.rom_ctrl_max_throughput_chk.3383834670 Feb 04 12:48:04 PM PST 24 Feb 04 12:48:22 PM PST 24 1475631969 ps
T344 /workspace/coverage/default/18.rom_ctrl_stress_all.2825225022 Feb 04 12:47:33 PM PST 24 Feb 04 12:48:11 PM PST 24 7904752791 ps
T345 /workspace/coverage/default/18.rom_ctrl_kmac_err_chk.3120137684 Feb 04 12:47:22 PM PST 24 Feb 04 12:47:49 PM PST 24 8892404736 ps
T346 /workspace/coverage/default/42.rom_ctrl_smoke.851412387 Feb 04 12:48:07 PM PST 24 Feb 04 12:48:40 PM PST 24 3569404266 ps
T347 /workspace/coverage/default/20.rom_ctrl_stress_all_with_rand_reset.2650732611 Feb 04 12:47:31 PM PST 24 Feb 04 02:07:59 PM PST 24 131078776481 ps
T348 /workspace/coverage/default/22.rom_ctrl_alert_test.3033116526 Feb 04 12:47:37 PM PST 24 Feb 04 12:48:01 PM PST 24 16550286751 ps
T349 /workspace/coverage/default/11.rom_ctrl_smoke.4081881412 Feb 04 12:47:20 PM PST 24 Feb 04 12:48:00 PM PST 24 8267657121 ps
T350 /workspace/coverage/default/44.rom_ctrl_max_throughput_chk.1071053467 Feb 04 12:48:13 PM PST 24 Feb 04 12:48:21 PM PST 24 177820094 ps
T351 /workspace/coverage/default/36.rom_ctrl_smoke.1575395235 Feb 04 12:47:49 PM PST 24 Feb 04 12:48:00 PM PST 24 192932400 ps
T352 /workspace/coverage/default/29.rom_ctrl_max_throughput_chk.450779133 Feb 04 12:47:46 PM PST 24 Feb 04 12:47:53 PM PST 24 338853769 ps
T353 /workspace/coverage/default/36.rom_ctrl_corrupt_sig_fatal_chk.2369498586 Feb 04 12:48:09 PM PST 24 Feb 04 12:51:08 PM PST 24 5902195026 ps
T46 /workspace/coverage/default/1.rom_ctrl_sec_cm.2231743210 Feb 04 12:47:13 PM PST 24 Feb 04 12:48:08 PM PST 24 2652950646 ps
T354 /workspace/coverage/default/20.rom_ctrl_kmac_err_chk.3872485789 Feb 04 12:47:31 PM PST 24 Feb 04 12:47:45 PM PST 24 335094416 ps
T355 /workspace/coverage/default/7.rom_ctrl_kmac_err_chk.2622678335 Feb 04 12:47:23 PM PST 24 Feb 04 12:47:36 PM PST 24 1189480260 ps
T356 /workspace/coverage/default/10.rom_ctrl_kmac_err_chk.2803541793 Feb 04 12:47:20 PM PST 24 Feb 04 12:47:52 PM PST 24 5545786181 ps
T357 /workspace/coverage/default/12.rom_ctrl_corrupt_sig_fatal_chk.485141554 Feb 04 12:47:25 PM PST 24 Feb 04 12:52:28 PM PST 24 86963986531 ps
T358 /workspace/coverage/default/49.rom_ctrl_corrupt_sig_fatal_chk.1069282538 Feb 04 12:48:31 PM PST 24 Feb 04 12:50:28 PM PST 24 3639932310 ps
T359 /workspace/coverage/default/21.rom_ctrl_max_throughput_chk.4192095137 Feb 04 12:47:29 PM PST 24 Feb 04 12:47:46 PM PST 24 9583850023 ps
T360 /workspace/coverage/default/29.rom_ctrl_alert_test.1618441197 Feb 04 12:47:52 PM PST 24 Feb 04 12:47:59 PM PST 24 1697456611 ps
T361 /workspace/coverage/default/9.rom_ctrl_kmac_err_chk.1083496823 Feb 04 12:47:29 PM PST 24 Feb 04 12:47:56 PM PST 24 1896129320 ps
T362 /workspace/coverage/default/25.rom_ctrl_smoke.4069023738 Feb 04 12:47:34 PM PST 24 Feb 04 12:48:13 PM PST 24 6104471982 ps
T363 /workspace/coverage/default/48.rom_ctrl_smoke.548529425 Feb 04 12:48:20 PM PST 24 Feb 04 12:48:52 PM PST 24 2384231003 ps
T364 /workspace/coverage/default/32.rom_ctrl_max_throughput_chk.1919533292 Feb 04 12:47:46 PM PST 24 Feb 04 12:48:00 PM PST 24 3585881029 ps
T365 /workspace/coverage/default/35.rom_ctrl_alert_test.3496142505 Feb 04 12:47:52 PM PST 24 Feb 04 12:48:03 PM PST 24 4452483108 ps
T366 /workspace/coverage/default/11.rom_ctrl_max_throughput_chk.831800271 Feb 04 12:47:18 PM PST 24 Feb 04 12:47:34 PM PST 24 3095890213 ps
T367 /workspace/coverage/default/17.rom_ctrl_max_throughput_chk.4213737023 Feb 04 12:47:32 PM PST 24 Feb 04 12:47:41 PM PST 24 392306592 ps
T368 /workspace/coverage/default/19.rom_ctrl_corrupt_sig_fatal_chk.4049006540 Feb 04 12:47:35 PM PST 24 Feb 04 12:50:13 PM PST 24 13371599377 ps
T369 /workspace/coverage/default/25.rom_ctrl_stress_all.1673375774 Feb 04 12:47:32 PM PST 24 Feb 04 12:48:16 PM PST 24 18838095166 ps
T370 /workspace/coverage/default/15.rom_ctrl_kmac_err_chk.654187323 Feb 04 12:47:32 PM PST 24 Feb 04 12:47:59 PM PST 24 31484818177 ps
T371 /workspace/coverage/default/10.rom_ctrl_alert_test.592973185 Feb 04 12:47:30 PM PST 24 Feb 04 12:47:47 PM PST 24 2661503349 ps
T372 /workspace/coverage/default/13.rom_ctrl_alert_test.1747047952 Feb 04 12:47:29 PM PST 24 Feb 04 12:47:47 PM PST 24 1624102036 ps
T373 /workspace/coverage/default/45.rom_ctrl_kmac_err_chk.931137727 Feb 04 12:48:24 PM PST 24 Feb 04 12:48:51 PM PST 24 2556433778 ps
T51 /workspace/coverage/default/3.rom_ctrl_sec_cm.1932637006 Feb 04 12:47:10 PM PST 24 Feb 04 12:49:02 PM PST 24 9007217682 ps
T374 /workspace/coverage/default/15.rom_ctrl_stress_all.2249043148 Feb 04 12:47:29 PM PST 24 Feb 04 12:48:22 PM PST 24 5568097062 ps
T375 /workspace/coverage/default/43.rom_ctrl_corrupt_sig_fatal_chk.1385390209 Feb 04 12:48:11 PM PST 24 Feb 04 12:54:26 PM PST 24 67244722782 ps
T376 /workspace/coverage/default/9.rom_ctrl_smoke.1820157678 Feb 04 12:47:24 PM PST 24 Feb 04 12:48:01 PM PST 24 4434778613 ps
T377 /workspace/coverage/default/45.rom_ctrl_max_throughput_chk.94464916 Feb 04 12:48:09 PM PST 24 Feb 04 12:48:25 PM PST 24 6686803892 ps
T378 /workspace/coverage/default/46.rom_ctrl_max_throughput_chk.2534778130 Feb 04 12:48:30 PM PST 24 Feb 04 12:48:44 PM PST 24 2827529371 ps
T379 /workspace/coverage/default/25.rom_ctrl_max_throughput_chk.3119994076 Feb 04 12:47:43 PM PST 24 Feb 04 12:47:50 PM PST 24 98706439 ps
T380 /workspace/coverage/default/16.rom_ctrl_max_throughput_chk.4002379390 Feb 04 12:47:31 PM PST 24 Feb 04 12:47:40 PM PST 24 389652999 ps
T381 /workspace/coverage/default/19.rom_ctrl_alert_test.3383832383 Feb 04 12:47:32 PM PST 24 Feb 04 12:47:45 PM PST 24 9318805567 ps
T52 /workspace/coverage/default/2.rom_ctrl_sec_cm.387661230 Feb 04 12:47:09 PM PST 24 Feb 04 12:48:55 PM PST 24 4566147584 ps
T382 /workspace/coverage/default/31.rom_ctrl_smoke.776225053 Feb 04 12:47:48 PM PST 24 Feb 04 12:48:24 PM PST 24 4055238628 ps
T94 /workspace/coverage/default/37.rom_ctrl_max_throughput_chk.212921860 Feb 04 12:48:12 PM PST 24 Feb 04 12:48:27 PM PST 24 5943280806 ps
T95 /workspace/coverage/default/40.rom_ctrl_corrupt_sig_fatal_chk.4067707626 Feb 04 12:48:12 PM PST 24 Feb 04 12:52:30 PM PST 24 31483402740 ps
T96 /workspace/coverage/default/48.rom_ctrl_stress_all_with_rand_reset.3476015933 Feb 04 12:48:32 PM PST 24 Feb 04 01:10:57 PM PST 24 34353640151 ps
T97 /workspace/coverage/default/31.rom_ctrl_alert_test.580195629 Feb 04 12:47:41 PM PST 24 Feb 04 12:47:54 PM PST 24 3433563784 ps
T98 /workspace/coverage/default/28.rom_ctrl_smoke.2900545158 Feb 04 12:47:41 PM PST 24 Feb 04 12:48:21 PM PST 24 13527422444 ps
T99 /workspace/coverage/default/27.rom_ctrl_alert_test.2315687974 Feb 04 12:47:44 PM PST 24 Feb 04 12:48:00 PM PST 24 1963342552 ps
T100 /workspace/coverage/default/45.rom_ctrl_stress_all.2622641852 Feb 04 12:48:15 PM PST 24 Feb 04 12:48:35 PM PST 24 651481972 ps
T101 /workspace/coverage/default/1.rom_ctrl_stress_all_with_rand_reset.3811150069 Feb 04 12:47:10 PM PST 24 Feb 04 01:58:44 PM PST 24 178854627204 ps
T102 /workspace/coverage/default/5.rom_ctrl_max_throughput_chk.1070379364 Feb 04 12:47:13 PM PST 24 Feb 04 12:47:28 PM PST 24 4567036742 ps
T103 /workspace/coverage/default/11.rom_ctrl_corrupt_sig_fatal_chk.4287642910 Feb 04 12:47:32 PM PST 24 Feb 04 12:52:12 PM PST 24 105768158496 ps
T383 /workspace/coverage/default/19.rom_ctrl_kmac_err_chk.3516859109 Feb 04 12:47:30 PM PST 24 Feb 04 12:47:59 PM PST 24 6495156158 ps
T384 /workspace/coverage/default/49.rom_ctrl_stress_all.914104447 Feb 04 12:48:17 PM PST 24 Feb 04 12:48:35 PM PST 24 12018958104 ps
T385 /workspace/coverage/default/43.rom_ctrl_max_throughput_chk.1325383383 Feb 04 12:48:20 PM PST 24 Feb 04 12:48:28 PM PST 24 444186580 ps
T386 /workspace/coverage/default/14.rom_ctrl_smoke.22301301 Feb 04 12:47:22 PM PST 24 Feb 04 12:47:36 PM PST 24 369899011 ps
T387 /workspace/coverage/default/4.rom_ctrl_kmac_err_chk.3320483076 Feb 04 12:47:13 PM PST 24 Feb 04 12:47:31 PM PST 24 3766233121 ps
T388 /workspace/coverage/default/34.rom_ctrl_alert_test.2145007492 Feb 04 12:47:54 PM PST 24 Feb 04 12:48:02 PM PST 24 1746586355 ps
T389 /workspace/coverage/default/7.rom_ctrl_smoke.3258161756 Feb 04 12:47:30 PM PST 24 Feb 04 12:47:57 PM PST 24 6843072953 ps
T390 /workspace/coverage/default/4.rom_ctrl_max_throughput_chk.2511431875 Feb 04 12:47:07 PM PST 24 Feb 04 12:47:25 PM PST 24 7270477889 ps
T391 /workspace/coverage/default/30.rom_ctrl_smoke.3970666287 Feb 04 12:47:51 PM PST 24 Feb 04 12:48:06 PM PST 24 2644003044 ps
T392 /workspace/coverage/default/44.rom_ctrl_stress_all.3920720233 Feb 04 12:48:15 PM PST 24 Feb 04 12:48:42 PM PST 24 21218471376 ps
T393 /workspace/coverage/default/44.rom_ctrl_kmac_err_chk.552411210 Feb 04 12:48:18 PM PST 24 Feb 04 12:48:52 PM PST 24 7543408569 ps
T394 /workspace/coverage/default/39.rom_ctrl_smoke.654365434 Feb 04 12:48:07 PM PST 24 Feb 04 12:48:31 PM PST 24 1635964185 ps
T395 /workspace/coverage/default/29.rom_ctrl_corrupt_sig_fatal_chk.3930500918 Feb 04 12:47:48 PM PST 24 Feb 04 12:50:32 PM PST 24 13818642319 ps
T396 /workspace/coverage/default/1.rom_ctrl_alert_test.3881775240 Feb 04 12:47:11 PM PST 24 Feb 04 12:47:23 PM PST 24 3046119779 ps
T397 /workspace/coverage/default/6.rom_ctrl_stress_all_with_rand_reset.1165169837 Feb 04 12:47:30 PM PST 24 Feb 04 01:21:41 PM PST 24 27567877786 ps
T398 /workspace/coverage/default/44.rom_ctrl_smoke.311567550 Feb 04 12:48:20 PM PST 24 Feb 04 12:48:50 PM PST 24 13101425632 ps
T399 /workspace/coverage/default/20.rom_ctrl_stress_all.1920958945 Feb 04 12:47:30 PM PST 24 Feb 04 12:48:07 PM PST 24 632797175 ps
T400 /workspace/coverage/default/17.rom_ctrl_stress_all.348556630 Feb 04 12:47:32 PM PST 24 Feb 04 12:47:55 PM PST 24 2019419866 ps
T401 /workspace/coverage/default/47.rom_ctrl_kmac_err_chk.2707601830 Feb 04 12:48:29 PM PST 24 Feb 04 12:48:59 PM PST 24 2732517021 ps
T402 /workspace/coverage/default/36.rom_ctrl_max_throughput_chk.1483891413 Feb 04 12:48:12 PM PST 24 Feb 04 12:48:25 PM PST 24 4512548394 ps
T403 /workspace/coverage/default/47.rom_ctrl_smoke.2307884348 Feb 04 12:48:22 PM PST 24 Feb 04 12:48:34 PM PST 24 192198316 ps
T404 /workspace/coverage/default/20.rom_ctrl_corrupt_sig_fatal_chk.1565421885 Feb 04 12:47:35 PM PST 24 Feb 04 12:52:54 PM PST 24 111669552605 ps
T405 /workspace/coverage/default/8.rom_ctrl_alert_test.1357492624 Feb 04 12:47:25 PM PST 24 Feb 04 12:47:38 PM PST 24 1176491379 ps
T406 /workspace/coverage/default/32.rom_ctrl_stress_all_with_rand_reset.2810106329 Feb 04 12:47:51 PM PST 24 Feb 04 01:12:07 PM PST 24 26644957321 ps
T407 /workspace/coverage/default/40.rom_ctrl_max_throughput_chk.1226736018 Feb 04 12:48:12 PM PST 24 Feb 04 12:48:30 PM PST 24 7610617932 ps
T408 /workspace/coverage/default/5.rom_ctrl_smoke.3521238154 Feb 04 12:47:08 PM PST 24 Feb 04 12:47:27 PM PST 24 4147776885 ps
T409 /workspace/coverage/default/28.rom_ctrl_stress_all.1554223955 Feb 04 12:47:50 PM PST 24 Feb 04 12:48:10 PM PST 24 2319296480 ps
T410 /workspace/coverage/default/27.rom_ctrl_stress_all.3970417516 Feb 04 12:47:29 PM PST 24 Feb 04 12:48:45 PM PST 24 8546405789 ps
T411 /workspace/coverage/default/41.rom_ctrl_alert_test.343913563 Feb 04 12:48:16 PM PST 24 Feb 04 12:48:22 PM PST 24 439247126 ps
T412 /workspace/coverage/default/44.rom_ctrl_stress_all_with_rand_reset.732778434 Feb 04 12:48:11 PM PST 24 Feb 04 01:13:01 PM PST 24 42070742560 ps
T413 /workspace/coverage/default/30.rom_ctrl_kmac_err_chk.171635382 Feb 04 12:47:45 PM PST 24 Feb 04 12:48:09 PM PST 24 2364862274 ps
T414 /workspace/coverage/default/45.rom_ctrl_stress_all_with_rand_reset.3877502567 Feb 04 12:48:22 PM PST 24 Feb 04 01:56:50 PM PST 24 110134656059 ps
T415 /workspace/coverage/default/15.rom_ctrl_stress_all_with_rand_reset.409200646 Feb 04 12:47:32 PM PST 24 Feb 04 12:57:53 PM PST 24 16231476386 ps
T416 /workspace/coverage/default/22.rom_ctrl_smoke.885581035 Feb 04 12:47:32 PM PST 24 Feb 04 12:48:02 PM PST 24 5718946573 ps
T417 /workspace/coverage/default/38.rom_ctrl_kmac_err_chk.2829837314 Feb 04 12:48:12 PM PST 24 Feb 04 12:48:30 PM PST 24 8803942583 ps
T418 /workspace/coverage/default/46.rom_ctrl_kmac_err_chk.953794706 Feb 04 12:48:22 PM PST 24 Feb 04 12:48:53 PM PST 24 12079072697 ps
T419 /workspace/coverage/default/27.rom_ctrl_smoke.1934649729 Feb 04 12:47:32 PM PST 24 Feb 04 12:47:58 PM PST 24 7896053025 ps
T420 /workspace/coverage/default/31.rom_ctrl_max_throughput_chk.549124072 Feb 04 12:47:49 PM PST 24 Feb 04 12:48:03 PM PST 24 6035740312 ps
T421 /workspace/coverage/default/9.rom_ctrl_alert_test.661154850 Feb 04 12:47:31 PM PST 24 Feb 04 12:47:40 PM PST 24 128808857 ps
T422 /workspace/coverage/default/1.rom_ctrl_max_throughput_chk.1595473960 Feb 04 12:47:07 PM PST 24 Feb 04 12:47:15 PM PST 24 292133684 ps
T423 /workspace/coverage/default/27.rom_ctrl_stress_all_with_rand_reset.3049583951 Feb 04 12:47:31 PM PST 24 Feb 04 01:36:54 PM PST 24 58747767965 ps
T424 /workspace/coverage/default/46.rom_ctrl_smoke.770757594 Feb 04 12:48:24 PM PST 24 Feb 04 12:48:48 PM PST 24 8301459233 ps
T425 /workspace/coverage/default/26.rom_ctrl_smoke.2334807710 Feb 04 12:47:42 PM PST 24 Feb 04 12:48:04 PM PST 24 11007270198 ps
T426 /workspace/coverage/default/24.rom_ctrl_corrupt_sig_fatal_chk.3295839313 Feb 04 12:47:33 PM PST 24 Feb 04 12:53:09 PM PST 24 126391898451 ps
T427 /workspace/coverage/default/48.rom_ctrl_corrupt_sig_fatal_chk.1605903205 Feb 04 12:48:32 PM PST 24 Feb 04 12:51:21 PM PST 24 43935587536 ps
T428 /workspace/coverage/default/23.rom_ctrl_stress_all_with_rand_reset.728058399 Feb 04 12:47:32 PM PST 24 Feb 04 01:04:49 PM PST 24 13685416391 ps
T429 /workspace/coverage/default/43.rom_ctrl_kmac_err_chk.3971107022 Feb 04 12:48:12 PM PST 24 Feb 04 12:48:23 PM PST 24 666502668 ps
T430 /workspace/coverage/default/33.rom_ctrl_max_throughput_chk.3473227646 Feb 04 12:47:48 PM PST 24 Feb 04 12:47:57 PM PST 24 1534336109 ps
T431 /workspace/coverage/default/13.rom_ctrl_kmac_err_chk.1154176841 Feb 04 12:47:33 PM PST 24 Feb 04 12:48:02 PM PST 24 2778958544 ps
T432 /workspace/coverage/default/44.rom_ctrl_alert_test.3692215396 Feb 04 12:48:14 PM PST 24 Feb 04 12:48:20 PM PST 24 85547250 ps
T122 /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_intg_err.901506470 Feb 04 12:37:58 PM PST 24 Feb 04 12:38:43 PM PST 24 4330517122 ps
T90 /workspace/coverage/cover_reg_top/0.rom_ctrl_passthru_mem_tl_intg_err.1425710308 Feb 04 12:37:47 PM PST 24 Feb 04 12:42:32 PM PST 24 108778253590 ps
T433 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_bit_bash.2469529095 Feb 04 12:37:56 PM PST 24 Feb 04 12:38:14 PM PST 24 6150657609 ps
T434 /workspace/coverage/cover_reg_top/12.rom_ctrl_same_csr_outstanding.2836775969 Feb 04 12:38:17 PM PST 24 Feb 04 12:38:31 PM PST 24 2534589585 ps
T125 /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_intg_err.280530679 Feb 04 12:37:57 PM PST 24 Feb 04 12:39:12 PM PST 24 825531975 ps
T91 /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_rw.1478331834 Feb 04 12:38:04 PM PST 24 Feb 04 12:38:10 PM PST 24 85434533 ps
T435 /workspace/coverage/cover_reg_top/13.rom_ctrl_same_csr_outstanding.1401079346 Feb 04 12:38:14 PM PST 24 Feb 04 12:38:28 PM PST 24 1122588535 ps
T436 /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_errors.507021373 Feb 04 12:38:04 PM PST 24 Feb 04 12:38:23 PM PST 24 2122688396 ps
T437 /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_intg_err.1864697501 Feb 04 12:38:13 PM PST 24 Feb 04 12:39:26 PM PST 24 3824505544 ps
T438 /workspace/coverage/cover_reg_top/17.rom_ctrl_same_csr_outstanding.2613625354 Feb 04 12:38:20 PM PST 24 Feb 04 12:38:30 PM PST 24 1262866972 ps
T439 /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_intg_err.4066371130 Feb 04 12:38:12 PM PST 24 Feb 04 12:38:52 PM PST 24 3302829342 ps
T440 /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_walk.1304284125 Feb 04 12:37:47 PM PST 24 Feb 04 12:37:57 PM PST 24 333219664 ps
T441 /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_partial_access.2647672956 Feb 04 12:37:49 PM PST 24 Feb 04 12:37:58 PM PST 24 489572874 ps
T442 /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_partial_access.3711073117 Feb 04 12:37:56 PM PST 24 Feb 04 12:38:04 PM PST 24 333552160 ps
T443 /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_mem_rw_with_rand_reset.3411988077 Feb 04 12:38:12 PM PST 24 Feb 04 12:38:30 PM PST 24 8676776760 ps
T444 /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_mem_rw_with_rand_reset.689835916 Feb 04 12:37:57 PM PST 24 Feb 04 12:38:09 PM PST 24 645379100 ps
T445 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_bit_bash.552861746 Feb 04 12:37:52 PM PST 24 Feb 04 12:38:07 PM PST 24 3955862254 ps
T93 /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_rw.2302626596 Feb 04 12:38:11 PM PST 24 Feb 04 12:38:28 PM PST 24 1915478736 ps
T446 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_mem_rw_with_rand_reset.1886490914 Feb 04 12:37:46 PM PST 24 Feb 04 12:37:56 PM PST 24 463560172 ps
T447 /workspace/coverage/cover_reg_top/5.rom_ctrl_same_csr_outstanding.4283590264 Feb 04 12:38:05 PM PST 24 Feb 04 12:38:18 PM PST 24 984879268 ps
T123 /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_intg_err.2821354735 Feb 04 12:38:19 PM PST 24 Feb 04 12:39:04 PM PST 24 5358418445 ps
T448 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_bit_bash.4080278790 Feb 04 12:37:47 PM PST 24 Feb 04 12:37:57 PM PST 24 86694273 ps
T449 /workspace/coverage/cover_reg_top/7.rom_ctrl_passthru_mem_tl_intg_err.1191110385 Feb 04 12:38:02 PM PST 24 Feb 04 12:43:00 PM PST 24 35042396589 ps
T92 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_hw_reset.3933702850 Feb 04 12:37:57 PM PST 24 Feb 04 12:38:13 PM PST 24 3155739112 ps
T450 /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_mem_rw_with_rand_reset.1557747658 Feb 04 12:38:04 PM PST 24 Feb 04 12:38:20 PM PST 24 6865481618 ps
T451 /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_intg_err.1636356632 Feb 04 12:38:01 PM PST 24 Feb 04 12:39:18 PM PST 24 1323435531 ps
T452 /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_rw.728493565 Feb 04 12:37:58 PM PST 24 Feb 04 12:38:17 PM PST 24 1917127704 ps
T453 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_mem_rw_with_rand_reset.1405056305 Feb 04 12:38:02 PM PST 24 Feb 04 12:38:19 PM PST 24 1921591438 ps
T454 /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_rw.2795428073 Feb 04 12:38:17 PM PST 24 Feb 04 12:38:24 PM PST 24 184296423 ps
T455 /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_rw.2802651055 Feb 04 12:38:16 PM PST 24 Feb 04 12:38:35 PM PST 24 11825104891 ps
T456 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_bit_bash.3416883004 Feb 04 12:37:55 PM PST 24 Feb 04 12:38:04 PM PST 24 135753872 ps
T457 /workspace/coverage/cover_reg_top/1.rom_ctrl_same_csr_outstanding.4008008796 Feb 04 12:37:49 PM PST 24 Feb 04 12:38:09 PM PST 24 17874417204 ps
T458 /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_intg_err.163272740 Feb 04 12:37:50 PM PST 24 Feb 04 12:38:35 PM PST 24 618262017 ps
T459 /workspace/coverage/cover_reg_top/14.rom_ctrl_passthru_mem_tl_intg_err.1299588625 Feb 04 12:38:14 PM PST 24 Feb 04 12:39:06 PM PST 24 2009479748 ps
T460 /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_mem_rw_with_rand_reset.1501044643 Feb 04 12:38:18 PM PST 24 Feb 04 12:38:27 PM PST 24 3246244922 ps
T461 /workspace/coverage/cover_reg_top/17.rom_ctrl_passthru_mem_tl_intg_err.657685465 Feb 04 12:38:13 PM PST 24 Feb 04 12:39:34 PM PST 24 3798075882 ps
T462 /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_rw.1663330507 Feb 04 12:38:08 PM PST 24 Feb 04 12:38:18 PM PST 24 431903065 ps
T463 /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_intg_err.3682770656 Feb 04 12:38:20 PM PST 24 Feb 04 12:39:30 PM PST 24 473969678 ps
T464 /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_intg_err.4098319331 Feb 04 12:37:58 PM PST 24 Feb 04 12:39:20 PM PST 24 6425050844 ps
T465 /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_mem_rw_with_rand_reset.3469307029 Feb 04 12:38:13 PM PST 24 Feb 04 12:38:19 PM PST 24 94470130 ps
T466 /workspace/coverage/cover_reg_top/14.rom_ctrl_same_csr_outstanding.2411251427 Feb 04 12:38:19 PM PST 24 Feb 04 12:38:32 PM PST 24 2211908470 ps
T467 /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_errors.3299842176 Feb 04 12:37:57 PM PST 24 Feb 04 12:38:16 PM PST 24 6403870001 ps
T468 /workspace/coverage/cover_reg_top/15.rom_ctrl_passthru_mem_tl_intg_err.4073766041 Feb 04 12:38:12 PM PST 24 Feb 04 12:40:22 PM PST 24 32180633049 ps
T469 /workspace/coverage/cover_reg_top/18.rom_ctrl_passthru_mem_tl_intg_err.2239720183 Feb 04 12:38:12 PM PST 24 Feb 04 12:43:44 PM PST 24 86430356548 ps
T470 /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_errors.1790245279 Feb 04 12:37:42 PM PST 24 Feb 04 12:38:03 PM PST 24 3858179444 ps
T119 /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_intg_err.1312154598 Feb 04 12:38:16 PM PST 24 Feb 04 12:38:59 PM PST 24 3494664200 ps
T471 /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_errors.654476105 Feb 04 12:38:10 PM PST 24 Feb 04 12:38:29 PM PST 24 1781202003 ps
T472 /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_rw.2370056881 Feb 04 12:38:11 PM PST 24 Feb 04 12:38:26 PM PST 24 1613051249 ps
T473 /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_intg_err.803559780 Feb 04 12:37:53 PM PST 24 Feb 04 12:38:46 PM PST 24 8954698091 ps
T474 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_rw.1631675807 Feb 04 12:37:41 PM PST 24 Feb 04 12:37:56 PM PST 24 1662963826 ps
T475 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_hw_reset.1089472936 Feb 04 12:37:56 PM PST 24 Feb 04 12:38:07 PM PST 24 90256453 ps
T476 /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_errors.3978526663 Feb 04 12:38:09 PM PST 24 Feb 04 12:38:28 PM PST 24 3082057896 ps
T477 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_mem_rw_with_rand_reset.674984330 Feb 04 12:37:53 PM PST 24 Feb 04 12:38:03 PM PST 24 200818605 ps
T478 /workspace/coverage/cover_reg_top/19.rom_ctrl_passthru_mem_tl_intg_err.1685163193 Feb 04 12:38:13 PM PST 24 Feb 04 12:40:58 PM PST 24 79344837984 ps
T479 /workspace/coverage/cover_reg_top/11.rom_ctrl_passthru_mem_tl_intg_err.2574298131 Feb 04 12:37:59 PM PST 24 Feb 04 12:41:21 PM PST 24 86652413188 ps
T480 /workspace/coverage/cover_reg_top/9.rom_ctrl_passthru_mem_tl_intg_err.214679227 Feb 04 12:38:08 PM PST 24 Feb 04 12:40:53 PM PST 24 17459896818 ps
T481 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_mem_rw_with_rand_reset.982346135 Feb 04 12:37:54 PM PST 24 Feb 04 12:38:13 PM PST 24 7418948758 ps
T482 /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_rw.877197584 Feb 04 12:38:14 PM PST 24 Feb 04 12:38:30 PM PST 24 2006135494 ps
T483 /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_walk.521586304 Feb 04 12:37:57 PM PST 24 Feb 04 12:38:05 PM PST 24 85637830 ps
T484 /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_errors.2309028982 Feb 04 12:38:14 PM PST 24 Feb 04 12:38:29 PM PST 24 980352279 ps

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_passthru_mem_tl_intg_err.240509808
Short name T25
Test name
Test status
Simulation time 19926912871 ps
CPU time 122.66 seconds
Started Feb 04 12:37:53 PM PST 24
Finished Feb 04 12:40:01 PM PST 24
Peak memory 211552 kb
Host smart-f4886c04-3faf-49aa-97ad-95fec168a543
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=240509808 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_pas
sthru_mem_tl_intg_err.240509808
Directory /workspace/2.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/default/21.rom_ctrl_stress_all.723113963
Short name T5
Test name
Test status
Simulation time 6399551713 ps
CPU time 64.06 seconds
Started Feb 04 12:47:30 PM PST 24
Finished Feb 04 12:48:39 PM PST 24
Peak memory 215556 kb
Host smart-4e5836bd-41ba-4adb-8056-378526529e49
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=723113963 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 21.rom_ctrl_stress_all.723113963
Directory /workspace/21.rom_ctrl_stress_all/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_same_csr_outstanding.3071183905
Short name T23
Test name
Test status
Simulation time 346737706 ps
CPU time 4.19 seconds
Started Feb 04 12:38:08 PM PST 24
Finished Feb 04 12:38:15 PM PST 24
Peak memory 210480 kb
Host smart-586ede8b-e210-442b-aafa-fa57ebb08eae
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3071183905 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_c
trl_same_csr_outstanding.3071183905
Directory /workspace/6.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_errors.580238213
Short name T29
Test name
Test status
Simulation time 5097912332 ps
CPU time 15.93 seconds
Started Feb 04 12:38:00 PM PST 24
Finished Feb 04 12:38:19 PM PST 24
Peak memory 218792 kb
Host smart-ac7f421b-374c-4ab3-8d1a-929054a6312c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=580238213 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_tl_errors.580238213
Directory /workspace/4.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_intg_err.3813829421
Short name T67
Test name
Test status
Simulation time 7331931672 ps
CPU time 74.67 seconds
Started Feb 04 12:38:00 PM PST 24
Finished Feb 04 12:39:18 PM PST 24
Peak memory 218720 kb
Host smart-81ef37ee-8b75-41ef-aeb2-212e87e59e17
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3813829421 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_tl_in
tg_err.3813829421
Directory /workspace/1.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/42.rom_ctrl_corrupt_sig_fatal_chk.2199739241
Short name T36
Test name
Test status
Simulation time 43150854076 ps
CPU time 470.62 seconds
Started Feb 04 12:48:02 PM PST 24
Finished Feb 04 12:55:59 PM PST 24
Peak memory 237016 kb
Host smart-298c5a9f-f906-42c4-96a8-7d647e3777c7
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2199739241 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_
corrupt_sig_fatal_chk.2199739241
Directory /workspace/42.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/42.rom_ctrl_stress_all_with_rand_reset.2847253340
Short name T14
Test name
Test status
Simulation time 75855748566 ps
CPU time 1234.85 seconds
Started Feb 04 12:48:11 PM PST 24
Finished Feb 04 01:08:47 PM PST 24
Peak memory 235148 kb
Host smart-ba66e913-0284-492d-a5c9-2f08c7926ce4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2847253340 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_stress_all_with_rand_reset.2847253340
Directory /workspace/42.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_intg_err.901506470
Short name T122
Test name
Test status
Simulation time 4330517122 ps
CPU time 41.66 seconds
Started Feb 04 12:37:58 PM PST 24
Finished Feb 04 12:38:43 PM PST 24
Peak memory 218716 kb
Host smart-222ab8bc-9ddb-4689-bebe-488e1a4b2684
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=901506470 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_tl_int
g_err.901506470
Directory /workspace/2.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/4.rom_ctrl_sec_cm.4043119156
Short name T44
Test name
Test status
Simulation time 2238846190 ps
CPU time 64.6 seconds
Started Feb 04 12:47:11 PM PST 24
Finished Feb 04 12:48:17 PM PST 24
Peak memory 235964 kb
Host smart-e1cf9b59-6594-41ba-9404-c60a8156a35f
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4043119156 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_sec_cm.4043119156
Directory /workspace/4.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_errors.2146726423
Short name T75
Test name
Test status
Simulation time 9956245111 ps
CPU time 18.03 seconds
Started Feb 04 12:38:20 PM PST 24
Finished Feb 04 12:38:39 PM PST 24
Peak memory 218784 kb
Host smart-fc13d77c-8c0a-4e0a-a272-8cd447530ece
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2146726423 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_tl_errors.2146726423
Directory /workspace/14.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_errors.3291970906
Short name T64
Test name
Test status
Simulation time 4718155888 ps
CPU time 12.89 seconds
Started Feb 04 12:38:09 PM PST 24
Finished Feb 04 12:38:24 PM PST 24
Peak memory 218840 kb
Host smart-97f67420-bb16-411f-ada0-d1eebed064e0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3291970906 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_tl_errors.3291970906
Directory /workspace/10.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/default/47.rom_ctrl_stress_all_with_rand_reset.2481568932
Short name T17
Test name
Test status
Simulation time 121769392547 ps
CPU time 1288.26 seconds
Started Feb 04 12:48:19 PM PST 24
Finished Feb 04 01:09:50 PM PST 24
Peak memory 235172 kb
Host smart-f557346e-e33d-4545-89f2-989cd62f6757
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2481568932 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_stress_all_with_rand_reset.2481568932
Directory /workspace/47.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.rom_ctrl_kmac_err_chk.205281587
Short name T214
Test name
Test status
Simulation time 172207012 ps
CPU time 9.61 seconds
Started Feb 04 12:47:04 PM PST 24
Finished Feb 04 12:47:14 PM PST 24
Peak memory 210508 kb
Host smart-52ddbbf2-d0f1-4e29-b212-e1df5f26ca3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=205281587 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_kmac_err_chk.205281587
Directory /workspace/1.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/11.rom_ctrl_kmac_err_chk.690554035
Short name T244
Test name
Test status
Simulation time 4906950133 ps
CPU time 23.5 seconds
Started Feb 04 12:47:26 PM PST 24
Finished Feb 04 12:47:51 PM PST 24
Peak memory 210896 kb
Host smart-d1705c9a-f155-45a7-8ba5-6cae30feef78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=690554035 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_kmac_err_chk.690554035
Directory /workspace/11.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/42.rom_ctrl_kmac_err_chk.15406927
Short name T38
Test name
Test status
Simulation time 2339235282 ps
CPU time 23.55 seconds
Started Feb 04 12:48:12 PM PST 24
Finished Feb 04 12:48:37 PM PST 24
Peak memory 210740 kb
Host smart-c755024e-6294-41d5-9d35-43081328361b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=15406927 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_kmac_err_chk.15406927
Directory /workspace/42.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_intg_err.1404612149
Short name T76
Test name
Test status
Simulation time 2177975721 ps
CPU time 74.13 seconds
Started Feb 04 12:38:17 PM PST 24
Finished Feb 04 12:39:34 PM PST 24
Peak memory 218748 kb
Host smart-5fcfec73-b4ad-4a51-b389-6c4968471a5d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1404612149 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_tl_i
ntg_err.1404612149
Directory /workspace/15.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_intg_err.1023260833
Short name T120
Test name
Test status
Simulation time 150852066 ps
CPU time 37.41 seconds
Started Feb 04 12:38:19 PM PST 24
Finished Feb 04 12:38:58 PM PST 24
Peak memory 218692 kb
Host smart-ef0839b4-bfe3-462b-80ab-01803c6d00a0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1023260833 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_tl_i
ntg_err.1023260833
Directory /workspace/18.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/0.rom_ctrl_alert_test.4120698427
Short name T163
Test name
Test status
Simulation time 1575802526 ps
CPU time 13.11 seconds
Started Feb 04 12:47:05 PM PST 24
Finished Feb 04 12:47:19 PM PST 24
Peak memory 210456 kb
Host smart-79e15f75-18ea-463d-bf35-a0729ff80426
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4120698427 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_alert_test.4120698427
Directory /workspace/0.rom_ctrl_alert_test/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_mem_rw_with_rand_reset.798679869
Short name T147
Test name
Test status
Simulation time 3909483834 ps
CPU time 10.61 seconds
Started Feb 04 12:38:01 PM PST 24
Finished Feb 04 12:38:14 PM PST 24
Peak memory 218760 kb
Host smart-36232d6c-e9a7-4e3c-9d4f-c4d807fe3a3d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=798679869 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 11.rom_ctrl_csr_mem_rw_with_rand_reset.798679869
Directory /workspace/11.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/default/0.rom_ctrl_sec_cm.4205591200
Short name T45
Test name
Test status
Simulation time 523024083 ps
CPU time 107.09 seconds
Started Feb 04 12:47:08 PM PST 24
Finished Feb 04 12:48:59 PM PST 24
Peak memory 235904 kb
Host smart-521b650a-c9e2-4b1a-be06-65c4125acae6
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4205591200 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_sec_cm.4205591200
Directory /workspace/0.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/35.rom_ctrl_stress_all_with_rand_reset.235436282
Short name T117
Test name
Test status
Simulation time 102226596100 ps
CPU time 2930.75 seconds
Started Feb 04 12:47:51 PM PST 24
Finished Feb 04 01:36:43 PM PST 24
Peak memory 236480 kb
Host smart-5c6a55f8-ea42-45b4-a615-5d2228e17044
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=235436282 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_stress_all_with_rand_reset.235436282
Directory /workspace/35.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.rom_ctrl_stress_all_with_rand_reset.882908131
Short name T116
Test name
Test status
Simulation time 295809452814 ps
CPU time 8087.94 seconds
Started Feb 04 12:48:11 PM PST 24
Finished Feb 04 03:03:00 PM PST 24
Peak memory 239340 kb
Host smart-99802537-5943-41db-a2b9-95e0aae7ddbf
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=882908131 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_stress_all_with_rand_reset.882908131
Directory /workspace/40.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_passthru_mem_tl_intg_err.1425710308
Short name T90
Test name
Test status
Simulation time 108778253590 ps
CPU time 278.42 seconds
Started Feb 04 12:37:47 PM PST 24
Finished Feb 04 12:42:32 PM PST 24
Peak memory 210592 kb
Host smart-f25c6751-b2b8-4041-9829-ec786127b0ad
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1425710308 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_pa
ssthru_mem_tl_intg_err.1425710308
Directory /workspace/0.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/default/37.rom_ctrl_max_throughput_chk.212921860
Short name T94
Test name
Test status
Simulation time 5943280806 ps
CPU time 14.15 seconds
Started Feb 04 12:48:12 PM PST 24
Finished Feb 04 12:48:27 PM PST 24
Peak memory 210548 kb
Host smart-d0e03e32-8d81-471e-b903-e66b3ab90d6e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=212921860 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_max_throughput_chk.212921860
Directory /workspace/37.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_aliasing.538911087
Short name T140
Test name
Test status
Simulation time 2947456117 ps
CPU time 12.44 seconds
Started Feb 04 12:37:56 PM PST 24
Finished Feb 04 12:38:12 PM PST 24
Peak memory 210564 kb
Host smart-b70b3323-ca13-4013-9f26-b0c3741e5830
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=538911087 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_alias
ing.538911087
Directory /workspace/0.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_bit_bash.2632801154
Short name T109
Test name
Test status
Simulation time 1580283852 ps
CPU time 14.43 seconds
Started Feb 04 12:37:52 PM PST 24
Finished Feb 04 12:38:11 PM PST 24
Peak memory 210648 kb
Host smart-4b4c3381-417f-44c8-9e33-6d2e2ff8c412
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2632801154 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_bit_
bash.2632801154
Directory /workspace/0.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_hw_reset.1430154745
Short name T26
Test name
Test status
Simulation time 1515071610 ps
CPU time 14.07 seconds
Started Feb 04 12:37:51 PM PST 24
Finished Feb 04 12:38:09 PM PST 24
Peak memory 216496 kb
Host smart-5a63ebae-b076-49a7-985d-da8940f1a614
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1430154745 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_hw_r
eset.1430154745
Directory /workspace/0.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_mem_rw_with_rand_reset.1886490914
Short name T446
Test name
Test status
Simulation time 463560172 ps
CPU time 4.18 seconds
Started Feb 04 12:37:46 PM PST 24
Finished Feb 04 12:37:56 PM PST 24
Peak memory 218508 kb
Host smart-32624936-ad1d-4fd3-94ff-445ee97f590e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1886490914 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 0.rom_ctrl_csr_mem_rw_with_rand_reset.1886490914
Directory /workspace/0.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_rw.1631675807
Short name T474
Test name
Test status
Simulation time 1662963826 ps
CPU time 7.91 seconds
Started Feb 04 12:37:41 PM PST 24
Finished Feb 04 12:37:56 PM PST 24
Peak memory 216268 kb
Host smart-035f1ad0-2569-4ed2-b7fa-4f2e62a7bc8b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1631675807 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_rw.1631675807
Directory /workspace/0.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_partial_access.1939512985
Short name T31
Test name
Test status
Simulation time 88422614 ps
CPU time 4.16 seconds
Started Feb 04 12:37:51 PM PST 24
Finished Feb 04 12:38:00 PM PST 24
Peak memory 210420 kb
Host smart-4a6fe980-e8a6-41a9-b288-31d766dc5c65
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1939512985 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctr
l_mem_partial_access.1939512985
Directory /workspace/0.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_walk.1304284125
Short name T440
Test name
Test status
Simulation time 333219664 ps
CPU time 4.03 seconds
Started Feb 04 12:37:47 PM PST 24
Finished Feb 04 12:37:57 PM PST 24
Peak memory 210416 kb
Host smart-4d78cfb9-6d55-4bfd-a6fa-1be06402d9d1
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1304284125 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_mem_walk
.1304284125
Directory /workspace/0.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_same_csr_outstanding.2904249661
Short name T149
Test name
Test status
Simulation time 1985564234 ps
CPU time 16.04 seconds
Started Feb 04 12:37:54 PM PST 24
Finished Feb 04 12:38:14 PM PST 24
Peak memory 210456 kb
Host smart-9000f820-f485-4960-88f3-ea5169933f7c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2904249661 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_c
trl_same_csr_outstanding.2904249661
Directory /workspace/0.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_errors.1790245279
Short name T470
Test name
Test status
Simulation time 3858179444 ps
CPU time 13.88 seconds
Started Feb 04 12:37:42 PM PST 24
Finished Feb 04 12:38:03 PM PST 24
Peak memory 218768 kb
Host smart-c1df6445-b2c5-46dd-92dc-46851ea9c525
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1790245279 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_tl_errors.1790245279
Directory /workspace/0.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_intg_err.163272740
Short name T458
Test name
Test status
Simulation time 618262017 ps
CPU time 39.87 seconds
Started Feb 04 12:37:50 PM PST 24
Finished Feb 04 12:38:35 PM PST 24
Peak memory 218468 kb
Host smart-6a4cae46-a610-45b4-8622-24165d3cf4c2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=163272740 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_tl_int
g_err.163272740
Directory /workspace/0.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_aliasing.4062717097
Short name T70
Test name
Test status
Simulation time 1249368326 ps
CPU time 8.35 seconds
Started Feb 04 12:37:57 PM PST 24
Finished Feb 04 12:38:09 PM PST 24
Peak memory 215636 kb
Host smart-cf52820c-c09d-4e1c-8279-8d7140e52163
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4062717097 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_alia
sing.4062717097
Directory /workspace/1.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_bit_bash.4080278790
Short name T448
Test name
Test status
Simulation time 86694273 ps
CPU time 4.34 seconds
Started Feb 04 12:37:47 PM PST 24
Finished Feb 04 12:37:57 PM PST 24
Peak memory 215632 kb
Host smart-1ee54abd-4f22-4cf5-aef8-ae5c81e4130b
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4080278790 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_bit_
bash.4080278790
Directory /workspace/1.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_hw_reset.1252176774
Short name T146
Test name
Test status
Simulation time 1064614010 ps
CPU time 5.79 seconds
Started Feb 04 12:37:51 PM PST 24
Finished Feb 04 12:38:01 PM PST 24
Peak memory 217032 kb
Host smart-3557aa3d-ddcd-4cce-9243-83874df48b7d
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1252176774 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_hw_r
eset.1252176774
Directory /workspace/1.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_mem_rw_with_rand_reset.982346135
Short name T481
Test name
Test status
Simulation time 7418948758 ps
CPU time 14.41 seconds
Started Feb 04 12:37:54 PM PST 24
Finished Feb 04 12:38:13 PM PST 24
Peak memory 218760 kb
Host smart-28f38e97-d59c-4157-966d-d26ea5444df6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=982346135 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 1.rom_ctrl_csr_mem_rw_with_rand_reset.982346135
Directory /workspace/1.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_rw.3443155488
Short name T134
Test name
Test status
Simulation time 3884723295 ps
CPU time 14.57 seconds
Started Feb 04 12:37:54 PM PST 24
Finished Feb 04 12:38:13 PM PST 24
Peak memory 217004 kb
Host smart-0c4c5ea6-5eda-44e2-8498-426746b8063f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3443155488 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_rw.3443155488
Directory /workspace/1.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_partial_access.3711073117
Short name T442
Test name
Test status
Simulation time 333552160 ps
CPU time 4.37 seconds
Started Feb 04 12:37:56 PM PST 24
Finished Feb 04 12:38:04 PM PST 24
Peak memory 210420 kb
Host smart-9b9b6669-b676-4bdd-b5e5-5641b6c12d2a
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3711073117 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctr
l_mem_partial_access.3711073117
Directory /workspace/1.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_walk.964346998
Short name T132
Test name
Test status
Simulation time 3429228527 ps
CPU time 9.59 seconds
Started Feb 04 12:37:57 PM PST 24
Finished Feb 04 12:38:10 PM PST 24
Peak memory 210652 kb
Host smart-fd7ef9d9-643b-470d-bb58-5b38e7047351
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=964346998 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_mem_walk.
964346998
Directory /workspace/1.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_passthru_mem_tl_intg_err.1828925002
Short name T30
Test name
Test status
Simulation time 24922063578 ps
CPU time 236.86 seconds
Started Feb 04 12:37:47 PM PST 24
Finished Feb 04 12:41:50 PM PST 24
Peak memory 210496 kb
Host smart-88e16643-07ee-4f1b-8088-1292c0e18c67
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1828925002 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_pa
ssthru_mem_tl_intg_err.1828925002
Directory /workspace/1.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_same_csr_outstanding.4008008796
Short name T457
Test name
Test status
Simulation time 17874417204 ps
CPU time 15.14 seconds
Started Feb 04 12:37:49 PM PST 24
Finished Feb 04 12:38:09 PM PST 24
Peak memory 210516 kb
Host smart-72599e8a-d53a-4e5a-81f5-9d90a44b511e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4008008796 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_c
trl_same_csr_outstanding.4008008796
Directory /workspace/1.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_errors.2892007866
Short name T150
Test name
Test status
Simulation time 742633701 ps
CPU time 12.39 seconds
Started Feb 04 12:37:49 PM PST 24
Finished Feb 04 12:38:06 PM PST 24
Peak memory 218656 kb
Host smart-9154af42-6e70-416c-918c-ea784d1f27f4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2892007866 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_tl_errors.2892007866
Directory /workspace/1.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_mem_rw_with_rand_reset.224746689
Short name T144
Test name
Test status
Simulation time 8178021200 ps
CPU time 15.69 seconds
Started Feb 04 12:38:08 PM PST 24
Finished Feb 04 12:38:27 PM PST 24
Peak memory 218784 kb
Host smart-ea7db316-c029-4436-9e41-40e16e46edcd
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=224746689 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 10.rom_ctrl_csr_mem_rw_with_rand_reset.224746689
Directory /workspace/10.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_rw.1478331834
Short name T91
Test name
Test status
Simulation time 85434533 ps
CPU time 4.24 seconds
Started Feb 04 12:38:04 PM PST 24
Finished Feb 04 12:38:10 PM PST 24
Peak memory 216040 kb
Host smart-2e2a857b-e507-4235-a9a5-4e90f6181670
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1478331834 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_csr_rw.1478331834
Directory /workspace/10.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_passthru_mem_tl_intg_err.471811060
Short name T69
Test name
Test status
Simulation time 165403140770 ps
CPU time 321.15 seconds
Started Feb 04 12:38:00 PM PST 24
Finished Feb 04 12:43:24 PM PST 24
Peak memory 210548 kb
Host smart-c27316fc-e8f0-44ab-b30f-103c059171a3
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=471811060 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_pa
ssthru_mem_tl_intg_err.471811060
Directory /workspace/10.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_same_csr_outstanding.2271240188
Short name T139
Test name
Test status
Simulation time 7148910706 ps
CPU time 11.94 seconds
Started Feb 04 12:38:05 PM PST 24
Finished Feb 04 12:38:19 PM PST 24
Peak memory 210504 kb
Host smart-d18db871-322e-463b-81de-4a564ff76dbd
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2271240188 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_
ctrl_same_csr_outstanding.2271240188
Directory /workspace/10.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_intg_err.4098319331
Short name T464
Test name
Test status
Simulation time 6425050844 ps
CPU time 78.82 seconds
Started Feb 04 12:37:58 PM PST 24
Finished Feb 04 12:39:20 PM PST 24
Peak memory 210964 kb
Host smart-43f27252-c481-4899-82db-ac0a286c3cc4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4098319331 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_tl_i
ntg_err.4098319331
Directory /workspace/10.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_rw.3766033580
Short name T143
Test name
Test status
Simulation time 2033931643 ps
CPU time 15.04 seconds
Started Feb 04 12:37:58 PM PST 24
Finished Feb 04 12:38:16 PM PST 24
Peak memory 210548 kb
Host smart-f92da21c-ec60-490d-b731-adf11b3da1ec
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3766033580 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_csr_rw.3766033580
Directory /workspace/11.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_passthru_mem_tl_intg_err.2574298131
Short name T479
Test name
Test status
Simulation time 86652413188 ps
CPU time 198.66 seconds
Started Feb 04 12:37:59 PM PST 24
Finished Feb 04 12:41:21 PM PST 24
Peak memory 218728 kb
Host smart-2d715a10-bdd5-46bc-b41f-03c95ada35b4
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2574298131 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_p
assthru_mem_tl_intg_err.2574298131
Directory /workspace/11.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_same_csr_outstanding.665629674
Short name T112
Test name
Test status
Simulation time 678899889 ps
CPU time 8.45 seconds
Started Feb 04 12:38:00 PM PST 24
Finished Feb 04 12:38:11 PM PST 24
Peak memory 210488 kb
Host smart-55ea5c1f-c133-4a73-bf6e-9e0287725d5c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=665629674 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_c
trl_same_csr_outstanding.665629674
Directory /workspace/11.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_errors.586825700
Short name T115
Test name
Test status
Simulation time 88344319 ps
CPU time 7.46 seconds
Started Feb 04 12:38:01 PM PST 24
Finished Feb 04 12:38:11 PM PST 24
Peak memory 218692 kb
Host smart-c147bca7-c42a-4a8f-8ffa-1b1360388f48
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=586825700 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_tl_errors.586825700
Directory /workspace/11.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_intg_err.2948998102
Short name T68
Test name
Test status
Simulation time 210959227 ps
CPU time 37.51 seconds
Started Feb 04 12:38:09 PM PST 24
Finished Feb 04 12:38:49 PM PST 24
Peak memory 217800 kb
Host smart-a738e8ab-4a45-4e55-bffb-033860b9122c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2948998102 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_tl_i
ntg_err.2948998102
Directory /workspace/11.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_mem_rw_with_rand_reset.2266960505
Short name T135
Test name
Test status
Simulation time 2033108505 ps
CPU time 15.81 seconds
Started Feb 04 12:38:20 PM PST 24
Finished Feb 04 12:38:38 PM PST 24
Peak memory 218724 kb
Host smart-cfa9e666-add9-48d7-b0c3-2b67ca04962c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2266960505 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 12.rom_ctrl_csr_mem_rw_with_rand_reset.2266960505
Directory /workspace/12.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_rw.2302626596
Short name T93
Test name
Test status
Simulation time 1915478736 ps
CPU time 15.29 seconds
Started Feb 04 12:38:11 PM PST 24
Finished Feb 04 12:38:28 PM PST 24
Peak memory 210484 kb
Host smart-1a97dc55-f9ef-4b75-a34c-97820f82a4d5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2302626596 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_csr_rw.2302626596
Directory /workspace/12.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_passthru_mem_tl_intg_err.1548599173
Short name T84
Test name
Test status
Simulation time 1878477155 ps
CPU time 62.98 seconds
Started Feb 04 12:38:09 PM PST 24
Finished Feb 04 12:39:14 PM PST 24
Peak memory 210476 kb
Host smart-5d137aa2-9d94-4e5a-9fdf-456af3cad992
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1548599173 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_p
assthru_mem_tl_intg_err.1548599173
Directory /workspace/12.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_same_csr_outstanding.2836775969
Short name T434
Test name
Test status
Simulation time 2534589585 ps
CPU time 11.57 seconds
Started Feb 04 12:38:17 PM PST 24
Finished Feb 04 12:38:31 PM PST 24
Peak memory 217312 kb
Host smart-9f50f072-a673-4495-981a-befb831546ee
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2836775969 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_
ctrl_same_csr_outstanding.2836775969
Directory /workspace/12.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_errors.2784770997
Short name T85
Test name
Test status
Simulation time 761835908 ps
CPU time 10.73 seconds
Started Feb 04 12:38:09 PM PST 24
Finished Feb 04 12:38:22 PM PST 24
Peak memory 218812 kb
Host smart-09cb816c-2b02-4fb6-8fb4-f8e569a5ea46
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2784770997 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_tl_errors.2784770997
Directory /workspace/12.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_intg_err.3682770656
Short name T463
Test name
Test status
Simulation time 473969678 ps
CPU time 68.82 seconds
Started Feb 04 12:38:20 PM PST 24
Finished Feb 04 12:39:30 PM PST 24
Peak memory 217876 kb
Host smart-2f6fb45c-2178-41c8-9e1f-1ef01a7913f2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3682770656 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_tl_i
ntg_err.3682770656
Directory /workspace/12.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_mem_rw_with_rand_reset.1501044643
Short name T460
Test name
Test status
Simulation time 3246244922 ps
CPU time 7.3 seconds
Started Feb 04 12:38:18 PM PST 24
Finished Feb 04 12:38:27 PM PST 24
Peak memory 218764 kb
Host smart-6dc2ced1-d573-4def-ac12-157fb162b856
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1501044643 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 13.rom_ctrl_csr_mem_rw_with_rand_reset.1501044643
Directory /workspace/13.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_rw.3300606578
Short name T28
Test name
Test status
Simulation time 3442562162 ps
CPU time 14.9 seconds
Started Feb 04 12:38:14 PM PST 24
Finished Feb 04 12:38:31 PM PST 24
Peak memory 210472 kb
Host smart-8e6b20a1-a624-4b0c-ab7c-1de229585e9b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3300606578 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_csr_rw.3300606578
Directory /workspace/13.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_same_csr_outstanding.1401079346
Short name T435
Test name
Test status
Simulation time 1122588535 ps
CPU time 12.23 seconds
Started Feb 04 12:38:14 PM PST 24
Finished Feb 04 12:38:28 PM PST 24
Peak memory 210468 kb
Host smart-025012c0-1f6f-4038-9be8-8b1a2dd4a254
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1401079346 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_
ctrl_same_csr_outstanding.1401079346
Directory /workspace/13.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_errors.3757449627
Short name T154
Test name
Test status
Simulation time 1675107367 ps
CPU time 16.01 seconds
Started Feb 04 12:38:21 PM PST 24
Finished Feb 04 12:38:39 PM PST 24
Peak memory 218728 kb
Host smart-051bad8e-4171-4291-9148-30940760737b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3757449627 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_tl_errors.3757449627
Directory /workspace/13.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_intg_err.4066371130
Short name T439
Test name
Test status
Simulation time 3302829342 ps
CPU time 37.64 seconds
Started Feb 04 12:38:12 PM PST 24
Finished Feb 04 12:38:52 PM PST 24
Peak memory 218796 kb
Host smart-c6e424c0-7620-4594-90cd-fcaf3c0cc48f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4066371130 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_tl_i
ntg_err.4066371130
Directory /workspace/13.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_mem_rw_with_rand_reset.3469307029
Short name T465
Test name
Test status
Simulation time 94470130 ps
CPU time 5.13 seconds
Started Feb 04 12:38:13 PM PST 24
Finished Feb 04 12:38:19 PM PST 24
Peak memory 218712 kb
Host smart-6656a552-94ea-4033-ac99-6fc5c747b6f7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3469307029 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 14.rom_ctrl_csr_mem_rw_with_rand_reset.3469307029
Directory /workspace/14.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_rw.2802651055
Short name T455
Test name
Test status
Simulation time 11825104891 ps
CPU time 15.92 seconds
Started Feb 04 12:38:16 PM PST 24
Finished Feb 04 12:38:35 PM PST 24
Peak memory 210612 kb
Host smart-85ea06c4-a733-434c-9be2-027e4b4657ed
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2802651055 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_csr_rw.2802651055
Directory /workspace/14.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_passthru_mem_tl_intg_err.1299588625
Short name T459
Test name
Test status
Simulation time 2009479748 ps
CPU time 49.64 seconds
Started Feb 04 12:38:14 PM PST 24
Finished Feb 04 12:39:06 PM PST 24
Peak memory 210648 kb
Host smart-d7630a52-4acf-45ce-8acb-fdcb0f788f19
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1299588625 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_p
assthru_mem_tl_intg_err.1299588625
Directory /workspace/14.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_same_csr_outstanding.2411251427
Short name T466
Test name
Test status
Simulation time 2211908470 ps
CPU time 11.38 seconds
Started Feb 04 12:38:19 PM PST 24
Finished Feb 04 12:38:32 PM PST 24
Peak memory 210584 kb
Host smart-a7b4f521-47bd-4b18-8654-9e59dd0bb4c2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2411251427 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_
ctrl_same_csr_outstanding.2411251427
Directory /workspace/14.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_intg_err.1312154598
Short name T119
Test name
Test status
Simulation time 3494664200 ps
CPU time 40.68 seconds
Started Feb 04 12:38:16 PM PST 24
Finished Feb 04 12:38:59 PM PST 24
Peak memory 218672 kb
Host smart-15c9fa63-d52c-4be5-9b21-1dd5372fd7a0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1312154598 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_tl_i
ntg_err.1312154598
Directory /workspace/14.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_mem_rw_with_rand_reset.4220028006
Short name T127
Test name
Test status
Simulation time 4071708293 ps
CPU time 17.89 seconds
Started Feb 04 12:38:19 PM PST 24
Finished Feb 04 12:38:38 PM PST 24
Peak memory 218764 kb
Host smart-7ee512f1-33fe-4053-8ec6-81999724392d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4220028006 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 15.rom_ctrl_csr_mem_rw_with_rand_reset.4220028006
Directory /workspace/15.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_rw.877197584
Short name T482
Test name
Test status
Simulation time 2006135494 ps
CPU time 14.73 seconds
Started Feb 04 12:38:14 PM PST 24
Finished Feb 04 12:38:30 PM PST 24
Peak memory 210476 kb
Host smart-d70d3ea7-435e-42cf-961e-22eb6e2ccc35
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=877197584 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_csr_rw.877197584
Directory /workspace/15.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_passthru_mem_tl_intg_err.4073766041
Short name T468
Test name
Test status
Simulation time 32180633049 ps
CPU time 128.5 seconds
Started Feb 04 12:38:12 PM PST 24
Finished Feb 04 12:40:22 PM PST 24
Peak memory 210656 kb
Host smart-bb4976db-dcf6-4709-900d-cc2850678f8b
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4073766041 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_p
assthru_mem_tl_intg_err.4073766041
Directory /workspace/15.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_same_csr_outstanding.1903349822
Short name T157
Test name
Test status
Simulation time 295428185 ps
CPU time 6.12 seconds
Started Feb 04 12:38:17 PM PST 24
Finished Feb 04 12:38:25 PM PST 24
Peak memory 210460 kb
Host smart-758c581a-f50f-407b-aeb6-611d6784aa59
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1903349822 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_
ctrl_same_csr_outstanding.1903349822
Directory /workspace/15.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_errors.3460924854
Short name T65
Test name
Test status
Simulation time 1262566895 ps
CPU time 13.97 seconds
Started Feb 04 12:38:14 PM PST 24
Finished Feb 04 12:38:30 PM PST 24
Peak memory 218696 kb
Host smart-3700ad6c-f1e2-456f-9339-1eacdf763555
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3460924854 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_tl_errors.3460924854
Directory /workspace/15.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_mem_rw_with_rand_reset.1055687476
Short name T32
Test name
Test status
Simulation time 711598812 ps
CPU time 9.04 seconds
Started Feb 04 12:38:21 PM PST 24
Finished Feb 04 12:38:32 PM PST 24
Peak memory 213184 kb
Host smart-4af7ee39-a560-4b55-9846-a8788829327f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1055687476 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 16.rom_ctrl_csr_mem_rw_with_rand_reset.1055687476
Directory /workspace/16.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_rw.1393842971
Short name T148
Test name
Test status
Simulation time 1424259781 ps
CPU time 9 seconds
Started Feb 04 12:38:14 PM PST 24
Finished Feb 04 12:38:24 PM PST 24
Peak memory 216748 kb
Host smart-d4eb324b-7df5-4116-b402-306b18d6c83a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1393842971 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_csr_rw.1393842971
Directory /workspace/16.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_passthru_mem_tl_intg_err.630807229
Short name T81
Test name
Test status
Simulation time 1900309085 ps
CPU time 94.86 seconds
Started Feb 04 12:38:15 PM PST 24
Finished Feb 04 12:39:52 PM PST 24
Peak memory 218660 kb
Host smart-05d3217a-c47d-4ad5-9ba3-c9375b37356c
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=630807229 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_pa
ssthru_mem_tl_intg_err.630807229
Directory /workspace/16.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_same_csr_outstanding.549826962
Short name T110
Test name
Test status
Simulation time 1539885318 ps
CPU time 9.22 seconds
Started Feb 04 12:38:20 PM PST 24
Finished Feb 04 12:38:31 PM PST 24
Peak memory 217500 kb
Host smart-9e38cb67-3dc3-4e8a-be36-dda8895a2d21
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=549826962 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_c
trl_same_csr_outstanding.549826962
Directory /workspace/16.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_errors.3978526663
Short name T476
Test name
Test status
Simulation time 3082057896 ps
CPU time 15.72 seconds
Started Feb 04 12:38:09 PM PST 24
Finished Feb 04 12:38:28 PM PST 24
Peak memory 218720 kb
Host smart-ac6d5108-5654-40df-8094-8bcb784107c5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3978526663 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_tl_errors.3978526663
Directory /workspace/16.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_intg_err.1864697501
Short name T437
Test name
Test status
Simulation time 3824505544 ps
CPU time 71.36 seconds
Started Feb 04 12:38:13 PM PST 24
Finished Feb 04 12:39:26 PM PST 24
Peak memory 218644 kb
Host smart-756f53a2-f1b8-4d9b-8bd6-124dbdeb2ce1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1864697501 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_tl_i
ntg_err.1864697501
Directory /workspace/16.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_mem_rw_with_rand_reset.3411988077
Short name T443
Test name
Test status
Simulation time 8676776760 ps
CPU time 15.82 seconds
Started Feb 04 12:38:12 PM PST 24
Finished Feb 04 12:38:30 PM PST 24
Peak memory 218712 kb
Host smart-351a0fa2-25df-4907-8aed-877640e7562d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3411988077 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 17.rom_ctrl_csr_mem_rw_with_rand_reset.3411988077
Directory /workspace/17.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_rw.2826299751
Short name T89
Test name
Test status
Simulation time 461060329 ps
CPU time 7.17 seconds
Started Feb 04 12:38:13 PM PST 24
Finished Feb 04 12:38:21 PM PST 24
Peak memory 210544 kb
Host smart-543367f2-a6c0-4950-a93a-048e0af7b1ce
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2826299751 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_csr_rw.2826299751
Directory /workspace/17.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_passthru_mem_tl_intg_err.657685465
Short name T461
Test name
Test status
Simulation time 3798075882 ps
CPU time 78.6 seconds
Started Feb 04 12:38:13 PM PST 24
Finished Feb 04 12:39:34 PM PST 24
Peak memory 218220 kb
Host smart-65158357-b20a-4035-938b-075a3de4befe
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=657685465 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_pa
ssthru_mem_tl_intg_err.657685465
Directory /workspace/17.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_same_csr_outstanding.2613625354
Short name T438
Test name
Test status
Simulation time 1262866972 ps
CPU time 7.97 seconds
Started Feb 04 12:38:20 PM PST 24
Finished Feb 04 12:38:30 PM PST 24
Peak memory 210484 kb
Host smart-c310d956-94e8-4cb5-9553-bc19ce0adc78
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2613625354 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_
ctrl_same_csr_outstanding.2613625354
Directory /workspace/17.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_errors.654476105
Short name T471
Test name
Test status
Simulation time 1781202003 ps
CPU time 17.54 seconds
Started Feb 04 12:38:10 PM PST 24
Finished Feb 04 12:38:29 PM PST 24
Peak memory 218724 kb
Host smart-85dc3b84-b7df-47e4-9040-8e14b4d3b20c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=654476105 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_tl_errors.654476105
Directory /workspace/17.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_intg_err.2821354735
Short name T123
Test name
Test status
Simulation time 5358418445 ps
CPU time 43.4 seconds
Started Feb 04 12:38:19 PM PST 24
Finished Feb 04 12:39:04 PM PST 24
Peak memory 218780 kb
Host smart-2b0bf73e-9775-43f8-a781-6360996a85dd
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2821354735 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_tl_i
ntg_err.2821354735
Directory /workspace/17.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_mem_rw_with_rand_reset.3129176768
Short name T153
Test name
Test status
Simulation time 943371271 ps
CPU time 7.39 seconds
Started Feb 04 12:38:18 PM PST 24
Finished Feb 04 12:38:27 PM PST 24
Peak memory 218512 kb
Host smart-c303e066-1cf3-4e1b-851f-0761e3d71406
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3129176768 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 18.rom_ctrl_csr_mem_rw_with_rand_reset.3129176768
Directory /workspace/18.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_rw.3532126133
Short name T73
Test name
Test status
Simulation time 505262008 ps
CPU time 5.95 seconds
Started Feb 04 12:38:21 PM PST 24
Finished Feb 04 12:38:29 PM PST 24
Peak memory 216004 kb
Host smart-13edae41-ffeb-4afb-9e31-21c8c910bd4d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3532126133 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_csr_rw.3532126133
Directory /workspace/18.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_passthru_mem_tl_intg_err.2239720183
Short name T469
Test name
Test status
Simulation time 86430356548 ps
CPU time 329.71 seconds
Started Feb 04 12:38:12 PM PST 24
Finished Feb 04 12:43:44 PM PST 24
Peak memory 210468 kb
Host smart-d3340dc3-b229-4eba-ae56-f5c4044f4d23
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2239720183 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_p
assthru_mem_tl_intg_err.2239720183
Directory /workspace/18.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_same_csr_outstanding.1020522270
Short name T155
Test name
Test status
Simulation time 270893581 ps
CPU time 5.16 seconds
Started Feb 04 12:38:14 PM PST 24
Finished Feb 04 12:38:21 PM PST 24
Peak memory 210312 kb
Host smart-21360bda-bf97-4c2a-b35b-0cbb9b996f06
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1020522270 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_
ctrl_same_csr_outstanding.1020522270
Directory /workspace/18.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_errors.2309028982
Short name T484
Test name
Test status
Simulation time 980352279 ps
CPU time 13.25 seconds
Started Feb 04 12:38:14 PM PST 24
Finished Feb 04 12:38:29 PM PST 24
Peak memory 218896 kb
Host smart-09e5e931-16ab-4b47-a9cc-b8ccffe12ee2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2309028982 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_tl_errors.2309028982
Directory /workspace/18.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_mem_rw_with_rand_reset.396195417
Short name T66
Test name
Test status
Simulation time 1566531670 ps
CPU time 13.44 seconds
Started Feb 04 12:38:10 PM PST 24
Finished Feb 04 12:38:25 PM PST 24
Peak memory 218616 kb
Host smart-cff3373e-e3ee-4b2c-ae3f-91b3dc18d43f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=396195417 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 19.rom_ctrl_csr_mem_rw_with_rand_reset.396195417
Directory /workspace/19.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_rw.2795428073
Short name T454
Test name
Test status
Simulation time 184296423 ps
CPU time 5.12 seconds
Started Feb 04 12:38:17 PM PST 24
Finished Feb 04 12:38:24 PM PST 24
Peak memory 216044 kb
Host smart-41ab0d8c-7da4-45a5-a591-8ca53b678f1d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2795428073 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_csr_rw.2795428073
Directory /workspace/19.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_passthru_mem_tl_intg_err.1685163193
Short name T478
Test name
Test status
Simulation time 79344837984 ps
CPU time 163.48 seconds
Started Feb 04 12:38:13 PM PST 24
Finished Feb 04 12:40:58 PM PST 24
Peak memory 210716 kb
Host smart-1676ad56-9909-4578-99a6-0d8cae18ddfb
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1685163193 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_p
assthru_mem_tl_intg_err.1685163193
Directory /workspace/19.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_same_csr_outstanding.1764454345
Short name T158
Test name
Test status
Simulation time 400855245 ps
CPU time 6.04 seconds
Started Feb 04 12:38:16 PM PST 24
Finished Feb 04 12:38:25 PM PST 24
Peak memory 210544 kb
Host smart-7783013f-51d6-4a3e-8f4b-33f93f1f4a22
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1764454345 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_
ctrl_same_csr_outstanding.1764454345
Directory /workspace/19.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_errors.3284326169
Short name T48
Test name
Test status
Simulation time 3460502104 ps
CPU time 15.98 seconds
Started Feb 04 12:38:19 PM PST 24
Finished Feb 04 12:38:36 PM PST 24
Peak memory 218788 kb
Host smart-5eccbbc4-b7b4-4b9e-86f8-5843898b3c16
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3284326169 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_tl_errors.3284326169
Directory /workspace/19.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_intg_err.3249372570
Short name T50
Test name
Test status
Simulation time 1671761150 ps
CPU time 45.29 seconds
Started Feb 04 12:38:15 PM PST 24
Finished Feb 04 12:39:02 PM PST 24
Peak memory 218660 kb
Host smart-9280c624-cb4e-4de9-827d-651c1c6b7f3c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3249372570 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_tl_i
ntg_err.3249372570
Directory /workspace/19.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_aliasing.3881321858
Short name T24
Test name
Test status
Simulation time 5252488764 ps
CPU time 12.12 seconds
Started Feb 04 12:37:48 PM PST 24
Finished Feb 04 12:38:06 PM PST 24
Peak memory 210548 kb
Host smart-cec5e864-e32a-404a-9fca-884cb09b78a3
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3881321858 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_alia
sing.3881321858
Directory /workspace/2.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_bit_bash.552861746
Short name T445
Test name
Test status
Simulation time 3955862254 ps
CPU time 10.22 seconds
Started Feb 04 12:37:52 PM PST 24
Finished Feb 04 12:38:07 PM PST 24
Peak memory 210540 kb
Host smart-8fe87997-475e-4edc-94f8-881dd974ec3c
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=552861746 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_bit_b
ash.552861746
Directory /workspace/2.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_hw_reset.2752038634
Short name T136
Test name
Test status
Simulation time 92166066 ps
CPU time 5.57 seconds
Started Feb 04 12:37:46 PM PST 24
Finished Feb 04 12:37:58 PM PST 24
Peak memory 210464 kb
Host smart-129103a4-2d5d-4aa9-96b9-8f91f3414098
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2752038634 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_hw_r
eset.2752038634
Directory /workspace/2.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_mem_rw_with_rand_reset.674984330
Short name T477
Test name
Test status
Simulation time 200818605 ps
CPU time 5.01 seconds
Started Feb 04 12:37:53 PM PST 24
Finished Feb 04 12:38:03 PM PST 24
Peak memory 218712 kb
Host smart-4ec965ba-559d-49ad-b316-9c075eb2b8c0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=674984330 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 2.rom_ctrl_csr_mem_rw_with_rand_reset.674984330
Directory /workspace/2.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_rw.570148214
Short name T106
Test name
Test status
Simulation time 561690678 ps
CPU time 7.55 seconds
Started Feb 04 12:37:46 PM PST 24
Finished Feb 04 12:38:00 PM PST 24
Peak memory 210468 kb
Host smart-52ba0759-26e8-4fac-ae84-0413669adafa
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=570148214 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_rw.570148214
Directory /workspace/2.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_partial_access.2744530461
Short name T142
Test name
Test status
Simulation time 504796592 ps
CPU time 7.27 seconds
Started Feb 04 12:37:54 PM PST 24
Finished Feb 04 12:38:06 PM PST 24
Peak memory 210400 kb
Host smart-0a4cf67d-5577-49be-b860-ce7d9480134e
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2744530461 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctr
l_mem_partial_access.2744530461
Directory /workspace/2.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_walk.4146885452
Short name T145
Test name
Test status
Simulation time 2485266576 ps
CPU time 11.4 seconds
Started Feb 04 12:37:50 PM PST 24
Finished Feb 04 12:38:06 PM PST 24
Peak memory 210476 kb
Host smart-30478a6a-cc0d-4bbc-bac6-622b147f36d2
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4146885452 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_mem_walk
.4146885452
Directory /workspace/2.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_same_csr_outstanding.2844686376
Short name T86
Test name
Test status
Simulation time 1858333242 ps
CPU time 14.85 seconds
Started Feb 04 12:37:48 PM PST 24
Finished Feb 04 12:38:08 PM PST 24
Peak memory 210480 kb
Host smart-f286ea45-e675-4c7f-adec-5e18b29e4403
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2844686376 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_c
trl_same_csr_outstanding.2844686376
Directory /workspace/2.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_errors.3715431831
Short name T141
Test name
Test status
Simulation time 785845431 ps
CPU time 13.55 seconds
Started Feb 04 12:37:55 PM PST 24
Finished Feb 04 12:38:12 PM PST 24
Peak memory 218696 kb
Host smart-60bf207f-fcf0-4c7e-87a8-de12df9a20ca
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3715431831 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_tl_errors.3715431831
Directory /workspace/2.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_aliasing.3423230141
Short name T133
Test name
Test status
Simulation time 300984273 ps
CPU time 6.08 seconds
Started Feb 04 12:37:58 PM PST 24
Finished Feb 04 12:38:07 PM PST 24
Peak memory 210448 kb
Host smart-f2729d1d-7c68-4fb5-9a7c-e3afb589c115
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3423230141 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_alia
sing.3423230141
Directory /workspace/3.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_bit_bash.3416883004
Short name T456
Test name
Test status
Simulation time 135753872 ps
CPU time 5.22 seconds
Started Feb 04 12:37:55 PM PST 24
Finished Feb 04 12:38:04 PM PST 24
Peak memory 215468 kb
Host smart-e29c7db7-784f-429d-80ba-9fcb6b243855
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3416883004 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_bit_
bash.3416883004
Directory /workspace/3.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_hw_reset.3933702850
Short name T92
Test name
Test status
Simulation time 3155739112 ps
CPU time 12.48 seconds
Started Feb 04 12:37:57 PM PST 24
Finished Feb 04 12:38:13 PM PST 24
Peak memory 210468 kb
Host smart-88bedd33-3348-4065-b897-1e2042e2bf3b
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3933702850 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_hw_r
eset.3933702850
Directory /workspace/3.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_mem_rw_with_rand_reset.1298340950
Short name T126
Test name
Test status
Simulation time 7647638552 ps
CPU time 15.06 seconds
Started Feb 04 12:37:53 PM PST 24
Finished Feb 04 12:38:12 PM PST 24
Peak memory 218816 kb
Host smart-8eedcb29-c7bb-4a8a-9636-917a406bc876
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1298340950 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 3.rom_ctrl_csr_mem_rw_with_rand_reset.1298340950
Directory /workspace/3.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_rw.3756537631
Short name T72
Test name
Test status
Simulation time 602957029 ps
CPU time 7.87 seconds
Started Feb 04 12:37:53 PM PST 24
Finished Feb 04 12:38:06 PM PST 24
Peak memory 216760 kb
Host smart-2df50743-186d-4197-afb9-4f905c1b5d54
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3756537631 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_rw.3756537631
Directory /workspace/3.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_partial_access.2108374502
Short name T137
Test name
Test status
Simulation time 347540753 ps
CPU time 3.96 seconds
Started Feb 04 12:37:47 PM PST 24
Finished Feb 04 12:37:57 PM PST 24
Peak memory 210392 kb
Host smart-02170675-77e8-47d2-b455-8c03ed6a42e4
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2108374502 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctr
l_mem_partial_access.2108374502
Directory /workspace/3.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_walk.521586304
Short name T483
Test name
Test status
Simulation time 85637830 ps
CPU time 4.33 seconds
Started Feb 04 12:37:57 PM PST 24
Finished Feb 04 12:38:05 PM PST 24
Peak memory 210344 kb
Host smart-c223de86-be9d-4239-8af3-85afb4a70b7f
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=521586304 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_mem_walk.
521586304
Directory /workspace/3.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_passthru_mem_tl_intg_err.2607494561
Short name T83
Test name
Test status
Simulation time 91634198915 ps
CPU time 346.34 seconds
Started Feb 04 12:37:51 PM PST 24
Finished Feb 04 12:43:42 PM PST 24
Peak memory 210548 kb
Host smart-37b24950-51df-42f5-a3d7-53748dcb7e3a
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2607494561 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_pa
ssthru_mem_tl_intg_err.2607494561
Directory /workspace/3.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_same_csr_outstanding.1398265578
Short name T130
Test name
Test status
Simulation time 2737255810 ps
CPU time 13.99 seconds
Started Feb 04 12:37:58 PM PST 24
Finished Feb 04 12:38:15 PM PST 24
Peak memory 217700 kb
Host smart-588a62d1-d83a-4e8e-9419-7ad6e103322e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1398265578 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_c
trl_same_csr_outstanding.1398265578
Directory /workspace/3.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_errors.3299842176
Short name T467
Test name
Test status
Simulation time 6403870001 ps
CPU time 15.73 seconds
Started Feb 04 12:37:57 PM PST 24
Finished Feb 04 12:38:16 PM PST 24
Peak memory 218752 kb
Host smart-7e942ff5-de21-48ce-b599-478d0aeba971
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3299842176 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_tl_errors.3299842176
Directory /workspace/3.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_intg_err.803559780
Short name T473
Test name
Test status
Simulation time 8954698091 ps
CPU time 48.23 seconds
Started Feb 04 12:37:53 PM PST 24
Finished Feb 04 12:38:46 PM PST 24
Peak memory 211044 kb
Host smart-858869e5-0ea5-4370-98ec-9978070974be
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=803559780 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_tl_int
g_err.803559780
Directory /workspace/3.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_aliasing.3514230339
Short name T131
Test name
Test status
Simulation time 333278191 ps
CPU time 4.18 seconds
Started Feb 04 12:37:51 PM PST 24
Finished Feb 04 12:38:00 PM PST 24
Peak memory 216176 kb
Host smart-d482f04b-88ae-429a-abb6-d3d1fb5b63a3
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3514230339 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_alia
sing.3514230339
Directory /workspace/4.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_bit_bash.2469529095
Short name T433
Test name
Test status
Simulation time 6150657609 ps
CPU time 13.64 seconds
Started Feb 04 12:37:56 PM PST 24
Finished Feb 04 12:38:14 PM PST 24
Peak memory 210520 kb
Host smart-83a91b71-f8c5-416a-8df4-270a39cc0af6
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2469529095 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_bit_
bash.2469529095
Directory /workspace/4.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_hw_reset.1089472936
Short name T475
Test name
Test status
Simulation time 90256453 ps
CPU time 7.41 seconds
Started Feb 04 12:37:56 PM PST 24
Finished Feb 04 12:38:07 PM PST 24
Peak memory 210504 kb
Host smart-7d823aba-3dcf-48c2-a27e-9aba13d6fc4c
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1089472936 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_hw_r
eset.1089472936
Directory /workspace/4.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_mem_rw_with_rand_reset.1405056305
Short name T453
Test name
Test status
Simulation time 1921591438 ps
CPU time 14.94 seconds
Started Feb 04 12:38:02 PM PST 24
Finished Feb 04 12:38:19 PM PST 24
Peak memory 218764 kb
Host smart-1f7aa5f4-b1da-437c-bc33-fe7109c73a55
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1405056305 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 4.rom_ctrl_csr_mem_rw_with_rand_reset.1405056305
Directory /workspace/4.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_rw.1923866870
Short name T105
Test name
Test status
Simulation time 4086010630 ps
CPU time 10.03 seconds
Started Feb 04 12:37:53 PM PST 24
Finished Feb 04 12:38:07 PM PST 24
Peak memory 210552 kb
Host smart-01b46fd8-b5f1-4e93-877a-47fcdcfed633
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1923866870 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_rw.1923866870
Directory /workspace/4.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_partial_access.2647672956
Short name T441
Test name
Test status
Simulation time 489572874 ps
CPU time 4.04 seconds
Started Feb 04 12:37:49 PM PST 24
Finished Feb 04 12:37:58 PM PST 24
Peak memory 210356 kb
Host smart-ec7f56ce-3ed4-4b54-ae27-10472341655d
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2647672956 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctr
l_mem_partial_access.2647672956
Directory /workspace/4.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_walk.888883568
Short name T71
Test name
Test status
Simulation time 2744126136 ps
CPU time 8.92 seconds
Started Feb 04 12:37:56 PM PST 24
Finished Feb 04 12:38:09 PM PST 24
Peak memory 210512 kb
Host smart-164142c0-f961-4e32-af3f-bf2091fe70b0
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=888883568 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_mem_walk.
888883568
Directory /workspace/4.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_passthru_mem_tl_intg_err.3568706044
Short name T80
Test name
Test status
Simulation time 45812875126 ps
CPU time 340.27 seconds
Started Feb 04 12:37:49 PM PST 24
Finished Feb 04 12:43:34 PM PST 24
Peak memory 210596 kb
Host smart-e408941b-44e0-47cc-b340-2178f8e14b33
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3568706044 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_pa
ssthru_mem_tl_intg_err.3568706044
Directory /workspace/4.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_same_csr_outstanding.2201858821
Short name T138
Test name
Test status
Simulation time 400806219 ps
CPU time 6.13 seconds
Started Feb 04 12:37:51 PM PST 24
Finished Feb 04 12:38:02 PM PST 24
Peak memory 217320 kb
Host smart-2c7d5106-c9fd-4271-bdf3-c362f3a835d9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2201858821 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_c
trl_same_csr_outstanding.2201858821
Directory /workspace/4.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_intg_err.2150063638
Short name T124
Test name
Test status
Simulation time 1356411206 ps
CPU time 43.23 seconds
Started Feb 04 12:37:53 PM PST 24
Finished Feb 04 12:38:41 PM PST 24
Peak memory 218648 kb
Host smart-da3cd1ab-8eaa-445a-a055-a74b04699ea7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2150063638 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_tl_in
tg_err.2150063638
Directory /workspace/4.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_mem_rw_with_rand_reset.2300101543
Short name T129
Test name
Test status
Simulation time 1275686468 ps
CPU time 11.12 seconds
Started Feb 04 12:38:08 PM PST 24
Finished Feb 04 12:38:22 PM PST 24
Peak memory 218724 kb
Host smart-a498a4f5-ca90-45cb-8f52-37898d3a9682
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2300101543 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 5.rom_ctrl_csr_mem_rw_with_rand_reset.2300101543
Directory /workspace/5.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_rw.728493565
Short name T452
Test name
Test status
Simulation time 1917127704 ps
CPU time 15.5 seconds
Started Feb 04 12:37:58 PM PST 24
Finished Feb 04 12:38:17 PM PST 24
Peak memory 210488 kb
Host smart-5edc8c43-b730-4e7a-a509-80cec3f47a9c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=728493565 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_csr_rw.728493565
Directory /workspace/5.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_passthru_mem_tl_intg_err.3015893998
Short name T47
Test name
Test status
Simulation time 3601131182 ps
CPU time 51.2 seconds
Started Feb 04 12:38:01 PM PST 24
Finished Feb 04 12:38:55 PM PST 24
Peak memory 210620 kb
Host smart-bb2af96d-3e04-427d-990f-4edd95295d29
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3015893998 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_pa
ssthru_mem_tl_intg_err.3015893998
Directory /workspace/5.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_same_csr_outstanding.4283590264
Short name T447
Test name
Test status
Simulation time 984879268 ps
CPU time 10.1 seconds
Started Feb 04 12:38:05 PM PST 24
Finished Feb 04 12:38:18 PM PST 24
Peak memory 210436 kb
Host smart-788789a1-04be-4ece-afe2-0033a439baf9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4283590264 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_c
trl_same_csr_outstanding.4283590264
Directory /workspace/5.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_errors.507021373
Short name T436
Test name
Test status
Simulation time 2122688396 ps
CPU time 16.54 seconds
Started Feb 04 12:38:04 PM PST 24
Finished Feb 04 12:38:23 PM PST 24
Peak memory 218408 kb
Host smart-0c81389d-b57a-40ec-a899-e6bf36a66517
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=507021373 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_tl_errors.507021373
Directory /workspace/5.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_intg_err.280530679
Short name T125
Test name
Test status
Simulation time 825531975 ps
CPU time 71.69 seconds
Started Feb 04 12:37:57 PM PST 24
Finished Feb 04 12:39:12 PM PST 24
Peak memory 218740 kb
Host smart-d3b67e8e-21fc-40e8-829c-aad320eda694
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=280530679 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_tl_int
g_err.280530679
Directory /workspace/5.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_mem_rw_with_rand_reset.689835916
Short name T444
Test name
Test status
Simulation time 645379100 ps
CPU time 8.26 seconds
Started Feb 04 12:37:57 PM PST 24
Finished Feb 04 12:38:09 PM PST 24
Peak memory 218712 kb
Host smart-4ec2dde8-475c-4f87-8136-7fd5b25280d5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=689835916 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 6.rom_ctrl_csr_mem_rw_with_rand_reset.689835916
Directory /workspace/6.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_rw.1663330507
Short name T462
Test name
Test status
Simulation time 431903065 ps
CPU time 6.9 seconds
Started Feb 04 12:38:08 PM PST 24
Finished Feb 04 12:38:18 PM PST 24
Peak memory 210424 kb
Host smart-3aac465e-4fff-4284-8088-87b9c52f8b4a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1663330507 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_csr_rw.1663330507
Directory /workspace/6.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_passthru_mem_tl_intg_err.482356621
Short name T79
Test name
Test status
Simulation time 21000728184 ps
CPU time 219.02 seconds
Started Feb 04 12:37:57 PM PST 24
Finished Feb 04 12:41:40 PM PST 24
Peak memory 210644 kb
Host smart-6524d549-da93-42bf-abc9-c00deb194219
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=482356621 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_pas
sthru_mem_tl_intg_err.482356621
Directory /workspace/6.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_errors.1738544100
Short name T156
Test name
Test status
Simulation time 7798900940 ps
CPU time 11.43 seconds
Started Feb 04 12:37:58 PM PST 24
Finished Feb 04 12:38:13 PM PST 24
Peak memory 218752 kb
Host smart-7e545710-56e5-44f2-a6a1-ad6c21d454e0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1738544100 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_tl_errors.1738544100
Directory /workspace/6.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_intg_err.1861688996
Short name T118
Test name
Test status
Simulation time 7071043499 ps
CPU time 72.68 seconds
Started Feb 04 12:38:01 PM PST 24
Finished Feb 04 12:39:16 PM PST 24
Peak memory 210760 kb
Host smart-95439c02-1970-4925-9713-359cf529f6f2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1861688996 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_tl_in
tg_err.1861688996
Directory /workspace/6.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_mem_rw_with_rand_reset.3416102477
Short name T128
Test name
Test status
Simulation time 99642798 ps
CPU time 5.02 seconds
Started Feb 04 12:38:03 PM PST 24
Finished Feb 04 12:38:10 PM PST 24
Peak memory 212780 kb
Host smart-ec4283a4-0b57-422e-8818-f3e8b3042f09
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3416102477 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 7.rom_ctrl_csr_mem_rw_with_rand_reset.3416102477
Directory /workspace/7.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_rw.2588941869
Short name T27
Test name
Test status
Simulation time 6313901453 ps
CPU time 12.81 seconds
Started Feb 04 12:38:09 PM PST 24
Finished Feb 04 12:38:24 PM PST 24
Peak memory 210636 kb
Host smart-95c2cb96-9a0d-4023-80b0-f5a14348c7d7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2588941869 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_csr_rw.2588941869
Directory /workspace/7.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_passthru_mem_tl_intg_err.1191110385
Short name T449
Test name
Test status
Simulation time 35042396589 ps
CPU time 295.86 seconds
Started Feb 04 12:38:02 PM PST 24
Finished Feb 04 12:43:00 PM PST 24
Peak memory 210524 kb
Host smart-f7d28a00-8dfa-48f5-abda-4a3ea72cac94
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1191110385 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_pa
ssthru_mem_tl_intg_err.1191110385
Directory /workspace/7.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_same_csr_outstanding.1365792921
Short name T111
Test name
Test status
Simulation time 740461368 ps
CPU time 6.57 seconds
Started Feb 04 12:38:01 PM PST 24
Finished Feb 04 12:38:10 PM PST 24
Peak memory 216384 kb
Host smart-9e6012b6-33a2-499d-8c6a-e5918323980d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1365792921 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_c
trl_same_csr_outstanding.1365792921
Directory /workspace/7.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_errors.2089705882
Short name T151
Test name
Test status
Simulation time 2464438580 ps
CPU time 11.88 seconds
Started Feb 04 12:37:58 PM PST 24
Finished Feb 04 12:38:13 PM PST 24
Peak memory 218744 kb
Host smart-091c51a3-976c-442a-a4d8-f8669bc34298
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2089705882 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_tl_errors.2089705882
Directory /workspace/7.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_intg_err.1542182459
Short name T78
Test name
Test status
Simulation time 5574033706 ps
CPU time 74.21 seconds
Started Feb 04 12:37:58 PM PST 24
Finished Feb 04 12:39:15 PM PST 24
Peak memory 218716 kb
Host smart-ba2d9945-a59f-4570-a2f5-c9479af646e8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1542182459 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_tl_in
tg_err.1542182459
Directory /workspace/7.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_mem_rw_with_rand_reset.2333626046
Short name T49
Test name
Test status
Simulation time 1123119637 ps
CPU time 10.92 seconds
Started Feb 04 12:38:04 PM PST 24
Finished Feb 04 12:38:17 PM PST 24
Peak memory 218396 kb
Host smart-56edcba9-d01e-4583-bd2f-f7398ea686db
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2333626046 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 8.rom_ctrl_csr_mem_rw_with_rand_reset.2333626046
Directory /workspace/8.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_rw.2370056881
Short name T472
Test name
Test status
Simulation time 1613051249 ps
CPU time 13.03 seconds
Started Feb 04 12:38:11 PM PST 24
Finished Feb 04 12:38:26 PM PST 24
Peak memory 216876 kb
Host smart-02edf4da-abd9-4b34-9d67-e247e71fa558
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2370056881 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_csr_rw.2370056881
Directory /workspace/8.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_passthru_mem_tl_intg_err.514860543
Short name T82
Test name
Test status
Simulation time 43072407777 ps
CPU time 368.99 seconds
Started Feb 04 12:37:56 PM PST 24
Finished Feb 04 12:44:09 PM PST 24
Peak memory 218520 kb
Host smart-c31084c9-9396-426e-9c85-37eee53e6fef
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=514860543 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_pas
sthru_mem_tl_intg_err.514860543
Directory /workspace/8.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_same_csr_outstanding.3456862671
Short name T104
Test name
Test status
Simulation time 246384083 ps
CPU time 4.17 seconds
Started Feb 04 12:38:05 PM PST 24
Finished Feb 04 12:38:12 PM PST 24
Peak memory 210432 kb
Host smart-3adfe1e2-d968-418e-ab40-d5278a735c0a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3456862671 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_c
trl_same_csr_outstanding.3456862671
Directory /workspace/8.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_errors.105978920
Short name T74
Test name
Test status
Simulation time 2917956901 ps
CPU time 12.72 seconds
Started Feb 04 12:37:58 PM PST 24
Finished Feb 04 12:38:14 PM PST 24
Peak memory 218792 kb
Host smart-ae1834e8-a123-497a-9aaa-fcad2dc020c3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=105978920 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_tl_errors.105978920
Directory /workspace/8.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_intg_err.4178372806
Short name T121
Test name
Test status
Simulation time 2013358278 ps
CPU time 78.35 seconds
Started Feb 04 12:38:08 PM PST 24
Finished Feb 04 12:39:29 PM PST 24
Peak memory 218588 kb
Host smart-3765849b-11da-45a4-a78c-37bb7797cf70
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4178372806 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_tl_in
tg_err.4178372806
Directory /workspace/8.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_mem_rw_with_rand_reset.1557747658
Short name T450
Test name
Test status
Simulation time 6865481618 ps
CPU time 14.31 seconds
Started Feb 04 12:38:04 PM PST 24
Finished Feb 04 12:38:20 PM PST 24
Peak memory 218704 kb
Host smart-05dc4604-74ba-4f2a-a28c-c9eb940d26b7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1557747658 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 9.rom_ctrl_csr_mem_rw_with_rand_reset.1557747658
Directory /workspace/9.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_rw.914722070
Short name T88
Test name
Test status
Simulation time 4429719182 ps
CPU time 10.55 seconds
Started Feb 04 12:38:05 PM PST 24
Finished Feb 04 12:38:18 PM PST 24
Peak memory 210508 kb
Host smart-15b284d8-024a-4fca-83b9-210edaad0b54
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=914722070 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_csr_rw.914722070
Directory /workspace/9.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_passthru_mem_tl_intg_err.214679227
Short name T480
Test name
Test status
Simulation time 17459896818 ps
CPU time 162.42 seconds
Started Feb 04 12:38:08 PM PST 24
Finished Feb 04 12:40:53 PM PST 24
Peak memory 210552 kb
Host smart-f23aa172-e3c6-4bd0-81de-4bf63992005f
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=214679227 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_pas
sthru_mem_tl_intg_err.214679227
Directory /workspace/9.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_same_csr_outstanding.3101890751
Short name T152
Test name
Test status
Simulation time 320498248 ps
CPU time 4.25 seconds
Started Feb 04 12:38:08 PM PST 24
Finished Feb 04 12:38:15 PM PST 24
Peak memory 216172 kb
Host smart-efe643e1-6642-4843-aa0b-97f80cec64f3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3101890751 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_c
trl_same_csr_outstanding.3101890751
Directory /workspace/9.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_errors.2521090268
Short name T77
Test name
Test status
Simulation time 5391877123 ps
CPU time 12.85 seconds
Started Feb 04 12:38:11 PM PST 24
Finished Feb 04 12:38:25 PM PST 24
Peak memory 218724 kb
Host smart-62539a5d-77fe-44e7-a1b1-d3ccb0d95165
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2521090268 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_tl_errors.2521090268
Directory /workspace/9.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_intg_err.1636356632
Short name T451
Test name
Test status
Simulation time 1323435531 ps
CPU time 74.35 seconds
Started Feb 04 12:38:01 PM PST 24
Finished Feb 04 12:39:18 PM PST 24
Peak memory 218628 kb
Host smart-e6aa01d9-6e46-405a-a772-bcf17fcf28c9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1636356632 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_tl_in
tg_err.1636356632
Directory /workspace/9.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/0.rom_ctrl_corrupt_sig_fatal_chk.2779310243
Short name T60
Test name
Test status
Simulation time 66012071708 ps
CPU time 308.06 seconds
Started Feb 04 12:47:07 PM PST 24
Finished Feb 04 12:52:17 PM PST 24
Peak memory 227028 kb
Host smart-ec08b696-a220-4705-9a50-66c568638b3f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2779310243 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_c
orrupt_sig_fatal_chk.2779310243
Directory /workspace/0.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/0.rom_ctrl_kmac_err_chk.4252166537
Short name T277
Test name
Test status
Simulation time 2071983652 ps
CPU time 9.68 seconds
Started Feb 04 12:47:04 PM PST 24
Finished Feb 04 12:47:15 PM PST 24
Peak memory 210756 kb
Host smart-2c8281da-af3f-4e23-aedb-5da9173a0773
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4252166537 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_kmac_err_chk.4252166537
Directory /workspace/0.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/0.rom_ctrl_max_throughput_chk.772178171
Short name T182
Test name
Test status
Simulation time 2149455437 ps
CPU time 13.53 seconds
Started Feb 04 12:47:07 PM PST 24
Finished Feb 04 12:47:23 PM PST 24
Peak memory 210724 kb
Host smart-2e55d8aa-8d31-49bb-b3e3-70bdb74856c8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=772178171 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_max_throughput_chk.772178171
Directory /workspace/0.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/0.rom_ctrl_smoke.3471281234
Short name T204
Test name
Test status
Simulation time 5262723731 ps
CPU time 21.43 seconds
Started Feb 04 12:47:03 PM PST 24
Finished Feb 04 12:47:25 PM PST 24
Peak memory 212424 kb
Host smart-d6c858ef-aab1-4453-a15e-c323ca43bb21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3471281234 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_smoke.3471281234
Directory /workspace/0.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/0.rom_ctrl_stress_all.2914043210
Short name T181
Test name
Test status
Simulation time 37106829895 ps
CPU time 55.78 seconds
Started Feb 04 12:47:10 PM PST 24
Finished Feb 04 12:48:08 PM PST 24
Peak memory 215796 kb
Host smart-bbc9b72c-6eee-485d-b91d-f5428e7108d4
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2914043210 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 0.rom_ctrl_stress_all.2914043210
Directory /workspace/0.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/1.rom_ctrl_alert_test.3881775240
Short name T396
Test name
Test status
Simulation time 3046119779 ps
CPU time 10.08 seconds
Started Feb 04 12:47:11 PM PST 24
Finished Feb 04 12:47:23 PM PST 24
Peak memory 210520 kb
Host smart-1b2c6730-fb73-4278-a4aa-488a4976fae9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3881775240 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_alert_test.3881775240
Directory /workspace/1.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/1.rom_ctrl_corrupt_sig_fatal_chk.2152379907
Short name T53
Test name
Test status
Simulation time 1068821228 ps
CPU time 75.74 seconds
Started Feb 04 12:47:08 PM PST 24
Finished Feb 04 12:48:27 PM PST 24
Peak memory 231872 kb
Host smart-524f2236-bc80-4848-8b72-878088925e72
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2152379907 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_c
orrupt_sig_fatal_chk.2152379907
Directory /workspace/1.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/1.rom_ctrl_max_throughput_chk.1595473960
Short name T422
Test name
Test status
Simulation time 292133684 ps
CPU time 5.54 seconds
Started Feb 04 12:47:07 PM PST 24
Finished Feb 04 12:47:15 PM PST 24
Peak memory 210452 kb
Host smart-77062575-b4bc-449f-b4de-1f2aec6097ea
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1595473960 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_max_throughput_chk.1595473960
Directory /workspace/1.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/1.rom_ctrl_sec_cm.2231743210
Short name T46
Test name
Test status
Simulation time 2652950646 ps
CPU time 54.33 seconds
Started Feb 04 12:47:13 PM PST 24
Finished Feb 04 12:48:08 PM PST 24
Peak memory 234388 kb
Host smart-9665415c-30d5-4ed2-a79b-ab9c18ea1305
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2231743210 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_sec_cm.2231743210
Directory /workspace/1.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/1.rom_ctrl_smoke.1123158875
Short name T228
Test name
Test status
Simulation time 5289291541 ps
CPU time 17.98 seconds
Started Feb 04 12:47:08 PM PST 24
Finished Feb 04 12:47:29 PM PST 24
Peak memory 212276 kb
Host smart-84e1486b-4b55-495d-a87f-21435562e13b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1123158875 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_smoke.1123158875
Directory /workspace/1.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/1.rom_ctrl_stress_all.3236836796
Short name T222
Test name
Test status
Simulation time 475644907 ps
CPU time 16.73 seconds
Started Feb 04 12:47:10 PM PST 24
Finished Feb 04 12:47:29 PM PST 24
Peak memory 214136 kb
Host smart-e3cbbb7a-41cf-4a58-af74-ab115cc89672
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3236836796 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 1.rom_ctrl_stress_all.3236836796
Directory /workspace/1.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/1.rom_ctrl_stress_all_with_rand_reset.3811150069
Short name T101
Test name
Test status
Simulation time 178854627204 ps
CPU time 4290.84 seconds
Started Feb 04 12:47:10 PM PST 24
Finished Feb 04 01:58:44 PM PST 24
Peak memory 239008 kb
Host smart-73b103fd-a08a-4feb-8606-b4e05b4871f9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3811150069 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_stress_all_with_rand_reset.3811150069
Directory /workspace/1.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.rom_ctrl_alert_test.592973185
Short name T371
Test name
Test status
Simulation time 2661503349 ps
CPU time 12.14 seconds
Started Feb 04 12:47:30 PM PST 24
Finished Feb 04 12:47:47 PM PST 24
Peak memory 209600 kb
Host smart-06303c49-a526-4f9d-ae95-57e229c6316a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=592973185 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_alert_test.592973185
Directory /workspace/10.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/10.rom_ctrl_corrupt_sig_fatal_chk.1184306137
Short name T238
Test name
Test status
Simulation time 69066368708 ps
CPU time 264.07 seconds
Started Feb 04 12:47:31 PM PST 24
Finished Feb 04 12:51:59 PM PST 24
Peak memory 227504 kb
Host smart-171bc73f-55b3-407b-a040-61dd73e46628
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1184306137 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_
corrupt_sig_fatal_chk.1184306137
Directory /workspace/10.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/10.rom_ctrl_kmac_err_chk.2803541793
Short name T356
Test name
Test status
Simulation time 5545786181 ps
CPU time 25.83 seconds
Started Feb 04 12:47:20 PM PST 24
Finished Feb 04 12:47:52 PM PST 24
Peak memory 211008 kb
Host smart-1c45ee7f-c08d-4568-adfe-114285cb9fe7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2803541793 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_kmac_err_chk.2803541793
Directory /workspace/10.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/10.rom_ctrl_max_throughput_chk.1707849901
Short name T332
Test name
Test status
Simulation time 131122026 ps
CPU time 5.57 seconds
Started Feb 04 12:47:22 PM PST 24
Finished Feb 04 12:47:32 PM PST 24
Peak memory 210436 kb
Host smart-66244b5f-cdf5-4e63-9846-9dbdc4b398f4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1707849901 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_max_throughput_chk.1707849901
Directory /workspace/10.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/10.rom_ctrl_smoke.3556192101
Short name T223
Test name
Test status
Simulation time 3422223941 ps
CPU time 20 seconds
Started Feb 04 12:47:20 PM PST 24
Finished Feb 04 12:47:46 PM PST 24
Peak memory 212276 kb
Host smart-365ab92c-8e63-4785-916d-70def4625ae4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3556192101 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_smoke.3556192101
Directory /workspace/10.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/10.rom_ctrl_stress_all.2400440359
Short name T193
Test name
Test status
Simulation time 11399666842 ps
CPU time 29 seconds
Started Feb 04 12:47:28 PM PST 24
Finished Feb 04 12:48:00 PM PST 24
Peak memory 213412 kb
Host smart-8c436285-0742-4267-83a9-ac6ad08506dc
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2400440359 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 10.rom_ctrl_stress_all.2400440359
Directory /workspace/10.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/10.rom_ctrl_stress_all_with_rand_reset.2794655554
Short name T266
Test name
Test status
Simulation time 32742988814 ps
CPU time 1979.09 seconds
Started Feb 04 12:47:30 PM PST 24
Finished Feb 04 01:20:34 PM PST 24
Peak memory 234040 kb
Host smart-8768fa18-0d62-4441-a7ec-6d98e1385da9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2794655554 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_stress_all_with_rand_reset.2794655554
Directory /workspace/10.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/11.rom_ctrl_alert_test.2197594617
Short name T10
Test name
Test status
Simulation time 2735281257 ps
CPU time 7.24 seconds
Started Feb 04 12:47:25 PM PST 24
Finished Feb 04 12:47:34 PM PST 24
Peak memory 210620 kb
Host smart-b74d5e3a-cbc6-4b59-9640-43807faa83bc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2197594617 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_alert_test.2197594617
Directory /workspace/11.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/11.rom_ctrl_corrupt_sig_fatal_chk.4287642910
Short name T103
Test name
Test status
Simulation time 105768158496 ps
CPU time 275.72 seconds
Started Feb 04 12:47:32 PM PST 24
Finished Feb 04 12:52:12 PM PST 24
Peak memory 238172 kb
Host smart-92e5824a-9f42-4bff-b9fe-89f81e48d13e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4287642910 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_
corrupt_sig_fatal_chk.4287642910
Directory /workspace/11.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/11.rom_ctrl_max_throughput_chk.831800271
Short name T366
Test name
Test status
Simulation time 3095890213 ps
CPU time 9.95 seconds
Started Feb 04 12:47:18 PM PST 24
Finished Feb 04 12:47:34 PM PST 24
Peak memory 210508 kb
Host smart-6b046ad4-9c9c-4709-ab65-a4badc48d640
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=831800271 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_max_throughput_chk.831800271
Directory /workspace/11.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/11.rom_ctrl_smoke.4081881412
Short name T349
Test name
Test status
Simulation time 8267657121 ps
CPU time 33.36 seconds
Started Feb 04 12:47:20 PM PST 24
Finished Feb 04 12:48:00 PM PST 24
Peak memory 212980 kb
Host smart-5552dcb0-672e-49ed-897e-b45dac03cc1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4081881412 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_smoke.4081881412
Directory /workspace/11.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/11.rom_ctrl_stress_all.2314009583
Short name T192
Test name
Test status
Simulation time 39299818699 ps
CPU time 103.72 seconds
Started Feb 04 12:47:30 PM PST 24
Finished Feb 04 12:49:19 PM PST 24
Peak memory 218028 kb
Host smart-fe5e74a3-4ad3-4130-95f2-ae4dbca8b942
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2314009583 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 11.rom_ctrl_stress_all.2314009583
Directory /workspace/11.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/12.rom_ctrl_alert_test.2672163463
Short name T219
Test name
Test status
Simulation time 4880369045 ps
CPU time 12.3 seconds
Started Feb 04 12:47:32 PM PST 24
Finished Feb 04 12:47:49 PM PST 24
Peak memory 210416 kb
Host smart-e45f3ecf-7998-4f08-b74c-df0def3384f5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2672163463 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_alert_test.2672163463
Directory /workspace/12.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/12.rom_ctrl_corrupt_sig_fatal_chk.485141554
Short name T357
Test name
Test status
Simulation time 86963986531 ps
CPU time 301.51 seconds
Started Feb 04 12:47:25 PM PST 24
Finished Feb 04 12:52:28 PM PST 24
Peak memory 212820 kb
Host smart-fc5a752d-0f24-4a0b-9075-90ca56f60a45
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=485141554 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_c
orrupt_sig_fatal_chk.485141554
Directory /workspace/12.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/12.rom_ctrl_kmac_err_chk.4222198962
Short name T309
Test name
Test status
Simulation time 2305126192 ps
CPU time 23.52 seconds
Started Feb 04 12:47:32 PM PST 24
Finished Feb 04 12:48:00 PM PST 24
Peak memory 210520 kb
Host smart-479f0974-521a-4c6a-9985-21b52aca9feb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4222198962 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_kmac_err_chk.4222198962
Directory /workspace/12.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/12.rom_ctrl_max_throughput_chk.4068417307
Short name T283
Test name
Test status
Simulation time 2167259817 ps
CPU time 11.82 seconds
Started Feb 04 12:47:35 PM PST 24
Finished Feb 04 12:47:49 PM PST 24
Peak memory 210540 kb
Host smart-73994437-8f75-4333-8da7-bb5afc0fd937
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4068417307 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_max_throughput_chk.4068417307
Directory /workspace/12.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/12.rom_ctrl_smoke.50286970
Short name T172
Test name
Test status
Simulation time 1913300083 ps
CPU time 22.69 seconds
Started Feb 04 12:47:19 PM PST 24
Finished Feb 04 12:47:48 PM PST 24
Peak memory 211720 kb
Host smart-f51e6aab-be78-44ff-a36b-6ff2cfeaa05c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=50286970 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_smoke.50286970
Directory /workspace/12.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/12.rom_ctrl_stress_all.2214860518
Short name T256
Test name
Test status
Simulation time 1091015217 ps
CPU time 16.6 seconds
Started Feb 04 12:47:31 PM PST 24
Finished Feb 04 12:47:52 PM PST 24
Peak memory 213540 kb
Host smart-a8a9a75d-75cb-4d39-b6fa-a9d97b94ac0a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2214860518 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 12.rom_ctrl_stress_all.2214860518
Directory /workspace/12.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/13.rom_ctrl_alert_test.1747047952
Short name T372
Test name
Test status
Simulation time 1624102036 ps
CPU time 13.2 seconds
Started Feb 04 12:47:29 PM PST 24
Finished Feb 04 12:47:47 PM PST 24
Peak memory 210376 kb
Host smart-c0c60430-aed0-42a2-8508-02a14e4b81a9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1747047952 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_alert_test.1747047952
Directory /workspace/13.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/13.rom_ctrl_corrupt_sig_fatal_chk.4058917898
Short name T171
Test name
Test status
Simulation time 38384206965 ps
CPU time 186.76 seconds
Started Feb 04 12:47:30 PM PST 24
Finished Feb 04 12:50:42 PM PST 24
Peak memory 227804 kb
Host smart-4cb0083d-9486-4434-b939-570fb1fc19bc
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4058917898 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_
corrupt_sig_fatal_chk.4058917898
Directory /workspace/13.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/13.rom_ctrl_kmac_err_chk.1154176841
Short name T431
Test name
Test status
Simulation time 2778958544 ps
CPU time 25.6 seconds
Started Feb 04 12:47:33 PM PST 24
Finished Feb 04 12:48:02 PM PST 24
Peak memory 210716 kb
Host smart-ca2b7566-6605-49f8-bcce-765e77f2987b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1154176841 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_kmac_err_chk.1154176841
Directory /workspace/13.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/13.rom_ctrl_max_throughput_chk.3879397936
Short name T221
Test name
Test status
Simulation time 6968888446 ps
CPU time 14.68 seconds
Started Feb 04 12:47:31 PM PST 24
Finished Feb 04 12:47:50 PM PST 24
Peak memory 210484 kb
Host smart-e1380131-5eea-4a42-a343-6e9fbc5871f3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3879397936 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_max_throughput_chk.3879397936
Directory /workspace/13.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/13.rom_ctrl_smoke.2901509570
Short name T215
Test name
Test status
Simulation time 3190524062 ps
CPU time 31.55 seconds
Started Feb 04 12:47:31 PM PST 24
Finished Feb 04 12:48:06 PM PST 24
Peak memory 212188 kb
Host smart-a24e7503-3b63-4959-bac3-baf9fe57e8d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2901509570 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_smoke.2901509570
Directory /workspace/13.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/13.rom_ctrl_stress_all.2116112935
Short name T201
Test name
Test status
Simulation time 7549093702 ps
CPU time 67.24 seconds
Started Feb 04 12:47:33 PM PST 24
Finished Feb 04 12:48:44 PM PST 24
Peak memory 216144 kb
Host smart-33eb900e-1f80-4ce4-bdc2-ae2401d7c4f1
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2116112935 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 13.rom_ctrl_stress_all.2116112935
Directory /workspace/13.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/13.rom_ctrl_stress_all_with_rand_reset.1780955784
Short name T258
Test name
Test status
Simulation time 92126139243 ps
CPU time 5128.53 seconds
Started Feb 04 12:47:34 PM PST 24
Finished Feb 04 02:13:06 PM PST 24
Peak memory 235164 kb
Host smart-e4f81e77-9899-4196-a06f-8b1048007de4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1780955784 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_stress_all_with_rand_reset.1780955784
Directory /workspace/13.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/14.rom_ctrl_alert_test.950826171
Short name T295
Test name
Test status
Simulation time 18675856006 ps
CPU time 12.23 seconds
Started Feb 04 12:47:31 PM PST 24
Finished Feb 04 12:47:47 PM PST 24
Peak memory 210480 kb
Host smart-6b29ba32-3e09-4527-ae58-984ee59e90ea
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=950826171 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_alert_test.950826171
Directory /workspace/14.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/14.rom_ctrl_corrupt_sig_fatal_chk.1877257819
Short name T59
Test name
Test status
Simulation time 107460786213 ps
CPU time 320.21 seconds
Started Feb 04 12:47:22 PM PST 24
Finished Feb 04 12:52:46 PM PST 24
Peak memory 234096 kb
Host smart-e2535fae-6717-4617-a841-218196608aed
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1877257819 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_
corrupt_sig_fatal_chk.1877257819
Directory /workspace/14.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/14.rom_ctrl_kmac_err_chk.2261456045
Short name T209
Test name
Test status
Simulation time 177355199 ps
CPU time 9.28 seconds
Started Feb 04 12:47:29 PM PST 24
Finished Feb 04 12:47:43 PM PST 24
Peak memory 210620 kb
Host smart-305e3ef0-5eb9-46e8-bbe0-d5a9a3e1faa4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2261456045 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_kmac_err_chk.2261456045
Directory /workspace/14.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/14.rom_ctrl_max_throughput_chk.612574314
Short name T307
Test name
Test status
Simulation time 7545920212 ps
CPU time 17.12 seconds
Started Feb 04 12:47:35 PM PST 24
Finished Feb 04 12:47:59 PM PST 24
Peak memory 210032 kb
Host smart-c11ae8d0-2f3f-4731-ba18-3b5943a0d712
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=612574314 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_max_throughput_chk.612574314
Directory /workspace/14.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/14.rom_ctrl_smoke.22301301
Short name T386
Test name
Test status
Simulation time 369899011 ps
CPU time 10.21 seconds
Started Feb 04 12:47:22 PM PST 24
Finished Feb 04 12:47:36 PM PST 24
Peak memory 212288 kb
Host smart-c328cb71-37d5-4b35-99cd-9def7719272e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=22301301 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_smoke.22301301
Directory /workspace/14.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/14.rom_ctrl_stress_all.1358831387
Short name T253
Test name
Test status
Simulation time 14830035727 ps
CPU time 16.94 seconds
Started Feb 04 12:47:32 PM PST 24
Finished Feb 04 12:47:53 PM PST 24
Peak memory 210420 kb
Host smart-2d1be836-670b-497d-8c49-e2e12ec1f2a2
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1358831387 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 14.rom_ctrl_stress_all.1358831387
Directory /workspace/14.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/14.rom_ctrl_stress_all_with_rand_reset.1339736214
Short name T239
Test name
Test status
Simulation time 46640645725 ps
CPU time 1731.72 seconds
Started Feb 04 12:47:29 PM PST 24
Finished Feb 04 01:16:26 PM PST 24
Peak memory 233544 kb
Host smart-68013891-1d4d-490e-8a10-2dc45a959a09
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1339736214 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_stress_all_with_rand_reset.1339736214
Directory /workspace/14.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/15.rom_ctrl_alert_test.1446214038
Short name T259
Test name
Test status
Simulation time 5966926566 ps
CPU time 13.32 seconds
Started Feb 04 12:47:23 PM PST 24
Finished Feb 04 12:47:40 PM PST 24
Peak memory 210472 kb
Host smart-6a998ab9-aaf9-49d9-aefc-9e7f8ba8e31a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1446214038 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_alert_test.1446214038
Directory /workspace/15.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/15.rom_ctrl_corrupt_sig_fatal_chk.2270000327
Short name T314
Test name
Test status
Simulation time 46608074348 ps
CPU time 281.1 seconds
Started Feb 04 12:47:29 PM PST 24
Finished Feb 04 12:52:15 PM PST 24
Peak memory 236056 kb
Host smart-8ffa6e99-3674-4ff4-996a-c417372d566a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2270000327 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_
corrupt_sig_fatal_chk.2270000327
Directory /workspace/15.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/15.rom_ctrl_kmac_err_chk.654187323
Short name T370
Test name
Test status
Simulation time 31484818177 ps
CPU time 23.04 seconds
Started Feb 04 12:47:32 PM PST 24
Finished Feb 04 12:47:59 PM PST 24
Peak memory 210948 kb
Host smart-887465bc-d801-4c07-8340-77ac9c4bf325
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=654187323 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_kmac_err_chk.654187323
Directory /workspace/15.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/15.rom_ctrl_max_throughput_chk.3020446391
Short name T113
Test name
Test status
Simulation time 8567759473 ps
CPU time 15.53 seconds
Started Feb 04 12:47:23 PM PST 24
Finished Feb 04 12:47:42 PM PST 24
Peak memory 210436 kb
Host smart-05d9b26b-b48a-4dcc-94f9-0b680e61d8b5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3020446391 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_max_throughput_chk.3020446391
Directory /workspace/15.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/15.rom_ctrl_smoke.3377791038
Short name T183
Test name
Test status
Simulation time 8963115329 ps
CPU time 18.11 seconds
Started Feb 04 12:47:18 PM PST 24
Finished Feb 04 12:47:43 PM PST 24
Peak memory 213072 kb
Host smart-d810a870-41c7-4f01-9575-77c59975cf1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3377791038 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_smoke.3377791038
Directory /workspace/15.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/15.rom_ctrl_stress_all.2249043148
Short name T374
Test name
Test status
Simulation time 5568097062 ps
CPU time 47.52 seconds
Started Feb 04 12:47:29 PM PST 24
Finished Feb 04 12:48:22 PM PST 24
Peak memory 215884 kb
Host smart-6644025e-e4be-4cbe-b4e7-e9d1b905106e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2249043148 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 15.rom_ctrl_stress_all.2249043148
Directory /workspace/15.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/15.rom_ctrl_stress_all_with_rand_reset.409200646
Short name T415
Test name
Test status
Simulation time 16231476386 ps
CPU time 616.24 seconds
Started Feb 04 12:47:32 PM PST 24
Finished Feb 04 12:57:53 PM PST 24
Peak memory 235060 kb
Host smart-86d2480d-a848-4fe0-9c73-0fa2e1d914ed
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=409200646 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_stress_all_with_rand_reset.409200646
Directory /workspace/15.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/16.rom_ctrl_alert_test.2733955281
Short name T246
Test name
Test status
Simulation time 333415917 ps
CPU time 4.26 seconds
Started Feb 04 12:47:29 PM PST 24
Finished Feb 04 12:47:38 PM PST 24
Peak memory 210544 kb
Host smart-80eae9d2-ce87-4def-83aa-2dc857550118
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2733955281 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_alert_test.2733955281
Directory /workspace/16.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/16.rom_ctrl_corrupt_sig_fatal_chk.64144918
Short name T9
Test name
Test status
Simulation time 9933909558 ps
CPU time 135.02 seconds
Started Feb 04 12:47:33 PM PST 24
Finished Feb 04 12:49:51 PM PST 24
Peak memory 211640 kb
Host smart-faa44821-810b-4cbc-a145-6ea11706c073
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64144918 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_
sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_co
rrupt_sig_fatal_chk.64144918
Directory /workspace/16.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/16.rom_ctrl_kmac_err_chk.1679739303
Short name T41
Test name
Test status
Simulation time 4083349087 ps
CPU time 33.52 seconds
Started Feb 04 12:47:31 PM PST 24
Finished Feb 04 12:48:09 PM PST 24
Peak memory 210620 kb
Host smart-d8abf26f-d2f8-4eaa-b294-687bc8af5f0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1679739303 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_kmac_err_chk.1679739303
Directory /workspace/16.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/16.rom_ctrl_max_throughput_chk.4002379390
Short name T380
Test name
Test status
Simulation time 389652999 ps
CPU time 5.4 seconds
Started Feb 04 12:47:31 PM PST 24
Finished Feb 04 12:47:40 PM PST 24
Peak memory 210356 kb
Host smart-c524b3e2-1476-44ae-9ed6-2aa605fce3ac
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4002379390 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_max_throughput_chk.4002379390
Directory /workspace/16.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/16.rom_ctrl_smoke.574682873
Short name T336
Test name
Test status
Simulation time 6933582308 ps
CPU time 22.67 seconds
Started Feb 04 12:47:31 PM PST 24
Finished Feb 04 12:47:58 PM PST 24
Peak memory 213960 kb
Host smart-87edccad-b2f1-4284-a5a8-815588f917e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=574682873 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_smoke.574682873
Directory /workspace/16.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/16.rom_ctrl_stress_all.2451853414
Short name T226
Test name
Test status
Simulation time 13042589395 ps
CPU time 24.23 seconds
Started Feb 04 12:47:36 PM PST 24
Finished Feb 04 12:48:07 PM PST 24
Peak memory 213212 kb
Host smart-3a15b49a-5013-4120-a732-cc6a877efccf
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2451853414 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 16.rom_ctrl_stress_all.2451853414
Directory /workspace/16.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/16.rom_ctrl_stress_all_with_rand_reset.1668168721
Short name T11
Test name
Test status
Simulation time 66958275857 ps
CPU time 6586.52 seconds
Started Feb 04 12:47:46 PM PST 24
Finished Feb 04 02:37:35 PM PST 24
Peak memory 235600 kb
Host smart-d9a73297-8c43-42b0-93b9-3e1493bd4475
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1668168721 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_stress_all_with_rand_reset.1668168721
Directory /workspace/16.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/17.rom_ctrl_alert_test.341122509
Short name T54
Test name
Test status
Simulation time 17590908106 ps
CPU time 11.38 seconds
Started Feb 04 12:47:45 PM PST 24
Finished Feb 04 12:47:57 PM PST 24
Peak memory 210500 kb
Host smart-62db08bb-8e79-4257-aeb5-c4454c2b0cda
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=341122509 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_alert_test.341122509
Directory /workspace/17.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/17.rom_ctrl_corrupt_sig_fatal_chk.2300620643
Short name T199
Test name
Test status
Simulation time 3491711779 ps
CPU time 97.21 seconds
Started Feb 04 12:47:35 PM PST 24
Finished Feb 04 12:49:19 PM PST 24
Peak memory 234004 kb
Host smart-6ce6ab52-2d25-485b-a7a8-da9bf8f7f896
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2300620643 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_
corrupt_sig_fatal_chk.2300620643
Directory /workspace/17.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/17.rom_ctrl_kmac_err_chk.1176324426
Short name T58
Test name
Test status
Simulation time 8162993405 ps
CPU time 25.37 seconds
Started Feb 04 12:47:33 PM PST 24
Finished Feb 04 12:48:02 PM PST 24
Peak memory 210516 kb
Host smart-6d236f04-70be-4dca-996d-ee3327f694a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1176324426 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_kmac_err_chk.1176324426
Directory /workspace/17.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/17.rom_ctrl_max_throughput_chk.4213737023
Short name T367
Test name
Test status
Simulation time 392306592 ps
CPU time 5.69 seconds
Started Feb 04 12:47:32 PM PST 24
Finished Feb 04 12:47:41 PM PST 24
Peak memory 210424 kb
Host smart-f9e72ba6-16ed-4649-af1f-53cf88d73709
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4213737023 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_max_throughput_chk.4213737023
Directory /workspace/17.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/17.rom_ctrl_smoke.3940572870
Short name T87
Test name
Test status
Simulation time 20778259471 ps
CPU time 33.1 seconds
Started Feb 04 12:47:30 PM PST 24
Finished Feb 04 12:48:08 PM PST 24
Peak memory 212576 kb
Host smart-eb089aeb-3e11-4e2b-94ef-d81c837076d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3940572870 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_smoke.3940572870
Directory /workspace/17.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/17.rom_ctrl_stress_all.348556630
Short name T400
Test name
Test status
Simulation time 2019419866 ps
CPU time 18.51 seconds
Started Feb 04 12:47:32 PM PST 24
Finished Feb 04 12:47:55 PM PST 24
Peak memory 210232 kb
Host smart-e6a95658-fc84-42c1-9d9a-6c712a0f4c94
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=348556630 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 17.rom_ctrl_stress_all.348556630
Directory /workspace/17.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/17.rom_ctrl_stress_all_with_rand_reset.2054672681
Short name T284
Test name
Test status
Simulation time 16376111821 ps
CPU time 725.17 seconds
Started Feb 04 12:47:32 PM PST 24
Finished Feb 04 12:59:41 PM PST 24
Peak memory 222444 kb
Host smart-98303a89-d590-4723-8d40-b21c9d98f9ba
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2054672681 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_stress_all_with_rand_reset.2054672681
Directory /workspace/17.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/18.rom_ctrl_alert_test.2394996573
Short name T324
Test name
Test status
Simulation time 90184794 ps
CPU time 4.21 seconds
Started Feb 04 12:47:42 PM PST 24
Finished Feb 04 12:47:48 PM PST 24
Peak memory 210220 kb
Host smart-ee498d68-da15-4777-af5b-18b15c01fe94
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2394996573 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_alert_test.2394996573
Directory /workspace/18.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/18.rom_ctrl_corrupt_sig_fatal_chk.1260137546
Short name T211
Test name
Test status
Simulation time 60261105645 ps
CPU time 512.01 seconds
Started Feb 04 12:47:34 PM PST 24
Finished Feb 04 12:56:09 PM PST 24
Peak memory 235984 kb
Host smart-7a7be230-05a4-4d7e-8982-d8e7850a8f1a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1260137546 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_
corrupt_sig_fatal_chk.1260137546
Directory /workspace/18.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/18.rom_ctrl_kmac_err_chk.3120137684
Short name T345
Test name
Test status
Simulation time 8892404736 ps
CPU time 22.95 seconds
Started Feb 04 12:47:22 PM PST 24
Finished Feb 04 12:47:49 PM PST 24
Peak memory 210920 kb
Host smart-f032a2ea-8310-4867-9e5f-c3a8ecf90027
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3120137684 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_kmac_err_chk.3120137684
Directory /workspace/18.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/18.rom_ctrl_max_throughput_chk.2144665096
Short name T342
Test name
Test status
Simulation time 6790792371 ps
CPU time 15.71 seconds
Started Feb 04 12:47:42 PM PST 24
Finished Feb 04 12:48:00 PM PST 24
Peak memory 210372 kb
Host smart-c18382d7-eb1a-4d70-a6fc-70fd585d9223
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2144665096 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_max_throughput_chk.2144665096
Directory /workspace/18.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/18.rom_ctrl_smoke.3531060939
Short name T194
Test name
Test status
Simulation time 504879020 ps
CPU time 14.91 seconds
Started Feb 04 12:47:24 PM PST 24
Finished Feb 04 12:47:42 PM PST 24
Peak memory 212296 kb
Host smart-c463adbf-20cb-441a-bc42-1224beb6ca4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3531060939 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_smoke.3531060939
Directory /workspace/18.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/18.rom_ctrl_stress_all.2825225022
Short name T344
Test name
Test status
Simulation time 7904752791 ps
CPU time 33.9 seconds
Started Feb 04 12:47:33 PM PST 24
Finished Feb 04 12:48:11 PM PST 24
Peak memory 214276 kb
Host smart-f6471261-a6bd-40ed-b991-9320e6ced292
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2825225022 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 18.rom_ctrl_stress_all.2825225022
Directory /workspace/18.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/18.rom_ctrl_stress_all_with_rand_reset.3611165952
Short name T189
Test name
Test status
Simulation time 132984867719 ps
CPU time 2472.08 seconds
Started Feb 04 12:47:23 PM PST 24
Finished Feb 04 01:28:39 PM PST 24
Peak memory 251648 kb
Host smart-86ca6e93-db07-4300-8b2f-a4d62741aa02
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3611165952 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_stress_all_with_rand_reset.3611165952
Directory /workspace/18.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/19.rom_ctrl_alert_test.3383832383
Short name T381
Test name
Test status
Simulation time 9318805567 ps
CPU time 8.33 seconds
Started Feb 04 12:47:32 PM PST 24
Finished Feb 04 12:47:45 PM PST 24
Peak memory 210512 kb
Host smart-1069a2dd-5e64-4663-9622-683a71996769
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3383832383 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_alert_test.3383832383
Directory /workspace/19.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/19.rom_ctrl_corrupt_sig_fatal_chk.4049006540
Short name T368
Test name
Test status
Simulation time 13371599377 ps
CPU time 156.03 seconds
Started Feb 04 12:47:35 PM PST 24
Finished Feb 04 12:50:13 PM PST 24
Peak memory 232040 kb
Host smart-9803cc50-80d1-4224-aeb3-2efd94771d69
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4049006540 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_
corrupt_sig_fatal_chk.4049006540
Directory /workspace/19.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/19.rom_ctrl_kmac_err_chk.3516859109
Short name T383
Test name
Test status
Simulation time 6495156158 ps
CPU time 24.23 seconds
Started Feb 04 12:47:30 PM PST 24
Finished Feb 04 12:47:59 PM PST 24
Peak memory 211248 kb
Host smart-a6e8e992-f47f-460d-8892-d61d6cf8d068
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3516859109 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_kmac_err_chk.3516859109
Directory /workspace/19.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/19.rom_ctrl_max_throughput_chk.85061100
Short name T306
Test name
Test status
Simulation time 2241869602 ps
CPU time 16.88 seconds
Started Feb 04 12:47:34 PM PST 24
Finished Feb 04 12:47:54 PM PST 24
Peak memory 210488 kb
Host smart-fe014954-56fe-49c3-a40e-79f284c157dc
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=85061100 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_max_throughput_chk.85061100
Directory /workspace/19.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/19.rom_ctrl_smoke.4155967378
Short name T184
Test name
Test status
Simulation time 6284419319 ps
CPU time 22.9 seconds
Started Feb 04 12:47:42 PM PST 24
Finished Feb 04 12:48:07 PM PST 24
Peak memory 212912 kb
Host smart-9bf03314-0643-4043-af9d-29f24663ef3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4155967378 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_smoke.4155967378
Directory /workspace/19.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/19.rom_ctrl_stress_all.147247331
Short name T55
Test name
Test status
Simulation time 14309691702 ps
CPU time 39.21 seconds
Started Feb 04 12:47:42 PM PST 24
Finished Feb 04 12:48:23 PM PST 24
Peak memory 215192 kb
Host smart-df4fd8c9-28d8-4b95-a9d1-822eb148adf0
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=147247331 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 19.rom_ctrl_stress_all.147247331
Directory /workspace/19.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/19.rom_ctrl_stress_all_with_rand_reset.899663645
Short name T15
Test name
Test status
Simulation time 75776271109 ps
CPU time 731.78 seconds
Started Feb 04 12:47:31 PM PST 24
Finished Feb 04 12:59:47 PM PST 24
Peak memory 233956 kb
Host smart-fceded79-1d22-47b0-93de-4b7c04308ad1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=899663645 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_stress_all_with_rand_reset.899663645
Directory /workspace/19.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.rom_ctrl_alert_test.238497121
Short name T310
Test name
Test status
Simulation time 1190590983 ps
CPU time 11.69 seconds
Started Feb 04 12:47:09 PM PST 24
Finished Feb 04 12:47:24 PM PST 24
Peak memory 210572 kb
Host smart-2671c7b0-e60c-40bc-b238-87c1fd013760
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=238497121 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_alert_test.238497121
Directory /workspace/2.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/2.rom_ctrl_corrupt_sig_fatal_chk.1776697020
Short name T301
Test name
Test status
Simulation time 113186763105 ps
CPU time 209.48 seconds
Started Feb 04 12:47:05 PM PST 24
Finished Feb 04 12:50:36 PM PST 24
Peak memory 236024 kb
Host smart-b849dd01-d55d-4ad0-bbe5-ea3f075256f9
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1776697020 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_c
orrupt_sig_fatal_chk.1776697020
Directory /workspace/2.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/2.rom_ctrl_kmac_err_chk.3189115373
Short name T302
Test name
Test status
Simulation time 2151475063 ps
CPU time 21.86 seconds
Started Feb 04 12:47:05 PM PST 24
Finished Feb 04 12:47:29 PM PST 24
Peak memory 210660 kb
Host smart-714da284-09c9-485f-bbb2-3e9045989bf2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3189115373 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_kmac_err_chk.3189115373
Directory /workspace/2.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/2.rom_ctrl_max_throughput_chk.2887325337
Short name T179
Test name
Test status
Simulation time 671221789 ps
CPU time 7.32 seconds
Started Feb 04 12:47:12 PM PST 24
Finished Feb 04 12:47:20 PM PST 24
Peak memory 210380 kb
Host smart-6bd04086-5ed5-4267-95ca-cc52ca264aee
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2887325337 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_max_throughput_chk.2887325337
Directory /workspace/2.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/2.rom_ctrl_sec_cm.387661230
Short name T52
Test name
Test status
Simulation time 4566147584 ps
CPU time 102.88 seconds
Started Feb 04 12:47:09 PM PST 24
Finished Feb 04 12:48:55 PM PST 24
Peak memory 238964 kb
Host smart-a9bce959-5cef-4540-93c5-bd2147890034
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=387661230 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_sec_cm.387661230
Directory /workspace/2.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/2.rom_ctrl_smoke.464149448
Short name T207
Test name
Test status
Simulation time 840129078 ps
CPU time 17.69 seconds
Started Feb 04 12:47:04 PM PST 24
Finished Feb 04 12:47:23 PM PST 24
Peak memory 212444 kb
Host smart-3a235134-7370-4dec-8608-eed39ed41858
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=464149448 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_smoke.464149448
Directory /workspace/2.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/2.rom_ctrl_stress_all.1723400505
Short name T21
Test name
Test status
Simulation time 8651107789 ps
CPU time 102.09 seconds
Started Feb 04 12:47:05 PM PST 24
Finished Feb 04 12:48:48 PM PST 24
Peak memory 215712 kb
Host smart-11eab1f1-7a34-4a54-a3cd-dae276dbd8d3
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1723400505 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 2.rom_ctrl_stress_all.1723400505
Directory /workspace/2.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/2.rom_ctrl_stress_all_with_rand_reset.782637501
Short name T291
Test name
Test status
Simulation time 72710738153 ps
CPU time 4693.15 seconds
Started Feb 04 12:47:05 PM PST 24
Finished Feb 04 02:05:20 PM PST 24
Peak memory 235216 kb
Host smart-cb76955e-4589-46bc-9464-233d3706e3d9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=782637501 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_stress_all_with_rand_reset.782637501
Directory /workspace/2.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.rom_ctrl_alert_test.3465356935
Short name T299
Test name
Test status
Simulation time 600569959 ps
CPU time 8.04 seconds
Started Feb 04 12:47:29 PM PST 24
Finished Feb 04 12:47:43 PM PST 24
Peak memory 210404 kb
Host smart-f0484983-3674-4688-a5d3-253f0f899394
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3465356935 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_alert_test.3465356935
Directory /workspace/20.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/20.rom_ctrl_corrupt_sig_fatal_chk.1565421885
Short name T404
Test name
Test status
Simulation time 111669552605 ps
CPU time 312.6 seconds
Started Feb 04 12:47:35 PM PST 24
Finished Feb 04 12:52:54 PM PST 24
Peak memory 226900 kb
Host smart-3f736f9b-f51e-45d4-9961-f70d4453bd5c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1565421885 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_
corrupt_sig_fatal_chk.1565421885
Directory /workspace/20.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/20.rom_ctrl_kmac_err_chk.3872485789
Short name T354
Test name
Test status
Simulation time 335094416 ps
CPU time 9.61 seconds
Started Feb 04 12:47:31 PM PST 24
Finished Feb 04 12:47:45 PM PST 24
Peak memory 210612 kb
Host smart-bac2be3e-b789-4bbc-86e2-2510a18673bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3872485789 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_kmac_err_chk.3872485789
Directory /workspace/20.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/20.rom_ctrl_max_throughput_chk.3508769417
Short name T341
Test name
Test status
Simulation time 3922666813 ps
CPU time 15.6 seconds
Started Feb 04 12:47:35 PM PST 24
Finished Feb 04 12:47:57 PM PST 24
Peak memory 210392 kb
Host smart-e077ac5e-b99c-4ae4-a36a-c99622895ff1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3508769417 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_max_throughput_chk.3508769417
Directory /workspace/20.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/20.rom_ctrl_smoke.3422229614
Short name T279
Test name
Test status
Simulation time 187570809 ps
CPU time 10.43 seconds
Started Feb 04 12:47:33 PM PST 24
Finished Feb 04 12:47:47 PM PST 24
Peak memory 212004 kb
Host smart-f1686189-94d6-42dc-872b-ffb918c5db9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3422229614 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_smoke.3422229614
Directory /workspace/20.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/20.rom_ctrl_stress_all.1920958945
Short name T399
Test name
Test status
Simulation time 632797175 ps
CPU time 32.53 seconds
Started Feb 04 12:47:30 PM PST 24
Finished Feb 04 12:48:07 PM PST 24
Peak memory 215724 kb
Host smart-43d31e97-99f2-4c0a-9bcd-469eef4d98c2
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1920958945 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 20.rom_ctrl_stress_all.1920958945
Directory /workspace/20.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/20.rom_ctrl_stress_all_with_rand_reset.2650732611
Short name T347
Test name
Test status
Simulation time 131078776481 ps
CPU time 4823.2 seconds
Started Feb 04 12:47:31 PM PST 24
Finished Feb 04 02:07:59 PM PST 24
Peak memory 259804 kb
Host smart-9099ba2d-746a-4ea7-9915-c0ff0f8b5ea8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2650732611 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_stress_all_with_rand_reset.2650732611
Directory /workspace/20.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/21.rom_ctrl_alert_test.4212833764
Short name T242
Test name
Test status
Simulation time 3570931043 ps
CPU time 13.84 seconds
Started Feb 04 12:47:33 PM PST 24
Finished Feb 04 12:47:50 PM PST 24
Peak memory 210524 kb
Host smart-3fde0a3d-5684-4ed0-a4b0-a1da386c0dc2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4212833764 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_alert_test.4212833764
Directory /workspace/21.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/21.rom_ctrl_corrupt_sig_fatal_chk.3044275536
Short name T313
Test name
Test status
Simulation time 2054503122 ps
CPU time 119.73 seconds
Started Feb 04 12:47:28 PM PST 24
Finished Feb 04 12:49:31 PM PST 24
Peak memory 236884 kb
Host smart-0f788d10-20bc-4c30-9867-d285e7a92019
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3044275536 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_
corrupt_sig_fatal_chk.3044275536
Directory /workspace/21.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/21.rom_ctrl_kmac_err_chk.4008164741
Short name T292
Test name
Test status
Simulation time 6495808454 ps
CPU time 20.34 seconds
Started Feb 04 12:47:29 PM PST 24
Finished Feb 04 12:47:54 PM PST 24
Peak memory 211260 kb
Host smart-d2c2ca07-2d22-40e9-9426-090b0bfa277f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4008164741 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_kmac_err_chk.4008164741
Directory /workspace/21.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/21.rom_ctrl_max_throughput_chk.4192095137
Short name T359
Test name
Test status
Simulation time 9583850023 ps
CPU time 13.52 seconds
Started Feb 04 12:47:29 PM PST 24
Finished Feb 04 12:47:46 PM PST 24
Peak memory 210600 kb
Host smart-99bd8b7c-2c32-439b-8ae1-99c4fc232c8a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4192095137 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_max_throughput_chk.4192095137
Directory /workspace/21.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/21.rom_ctrl_smoke.1184490529
Short name T247
Test name
Test status
Simulation time 4143571460 ps
CPU time 21.28 seconds
Started Feb 04 12:47:32 PM PST 24
Finished Feb 04 12:47:57 PM PST 24
Peak memory 211936 kb
Host smart-1471092e-4d2b-4210-b188-ba76a712d2fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1184490529 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_smoke.1184490529
Directory /workspace/21.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/21.rom_ctrl_stress_all_with_rand_reset.593568886
Short name T276
Test name
Test status
Simulation time 96766118771 ps
CPU time 885.78 seconds
Started Feb 04 12:47:29 PM PST 24
Finished Feb 04 01:02:20 PM PST 24
Peak memory 227108 kb
Host smart-20518b8d-436d-4ca7-85f7-25d66b7fd652
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=593568886 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_stress_all_with_rand_reset.593568886
Directory /workspace/21.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/22.rom_ctrl_alert_test.3033116526
Short name T348
Test name
Test status
Simulation time 16550286751 ps
CPU time 17.29 seconds
Started Feb 04 12:47:37 PM PST 24
Finished Feb 04 12:48:01 PM PST 24
Peak memory 210428 kb
Host smart-caf93c2d-d352-4ab0-a6e2-ac938cb9bfd1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3033116526 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_alert_test.3033116526
Directory /workspace/22.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/22.rom_ctrl_corrupt_sig_fatal_chk.1915366491
Short name T322
Test name
Test status
Simulation time 5114462654 ps
CPU time 198.45 seconds
Started Feb 04 12:47:31 PM PST 24
Finished Feb 04 12:50:54 PM PST 24
Peak memory 235976 kb
Host smart-ecb8fe85-6456-4378-949b-e1dbd2453fde
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1915366491 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_
corrupt_sig_fatal_chk.1915366491
Directory /workspace/22.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/22.rom_ctrl_kmac_err_chk.4184617900
Short name T231
Test name
Test status
Simulation time 65687514797 ps
CPU time 32.68 seconds
Started Feb 04 12:47:26 PM PST 24
Finished Feb 04 12:48:00 PM PST 24
Peak memory 210964 kb
Host smart-4ce465a4-20e8-4a18-b89c-5009c223da21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4184617900 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_kmac_err_chk.4184617900
Directory /workspace/22.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/22.rom_ctrl_max_throughput_chk.1877267817
Short name T300
Test name
Test status
Simulation time 4975637290 ps
CPU time 12.47 seconds
Started Feb 04 12:47:32 PM PST 24
Finished Feb 04 12:47:48 PM PST 24
Peak memory 210488 kb
Host smart-44c445fd-1796-43be-9f59-5b00651be91f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1877267817 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_max_throughput_chk.1877267817
Directory /workspace/22.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/22.rom_ctrl_smoke.885581035
Short name T416
Test name
Test status
Simulation time 5718946573 ps
CPU time 26.35 seconds
Started Feb 04 12:47:32 PM PST 24
Finished Feb 04 12:48:02 PM PST 24
Peak memory 212392 kb
Host smart-e848287c-2001-4d36-9f74-8ec291df46ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=885581035 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_smoke.885581035
Directory /workspace/22.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/22.rom_ctrl_stress_all.1762147602
Short name T56
Test name
Test status
Simulation time 38311728275 ps
CPU time 29.61 seconds
Started Feb 04 12:47:33 PM PST 24
Finished Feb 04 12:48:06 PM PST 24
Peak memory 214108 kb
Host smart-81d1aea0-20d9-425c-b2b2-5f8e3048c8c4
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1762147602 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 22.rom_ctrl_stress_all.1762147602
Directory /workspace/22.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/22.rom_ctrl_stress_all_with_rand_reset.280007627
Short name T12
Test name
Test status
Simulation time 175602550842 ps
CPU time 1904.61 seconds
Started Feb 04 12:47:22 PM PST 24
Finished Feb 04 01:19:11 PM PST 24
Peak memory 235232 kb
Host smart-c9da2c4b-3514-4a00-9858-4e3d228e869a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=280007627 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_stress_all_with_rand_reset.280007627
Directory /workspace/22.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/23.rom_ctrl_alert_test.3754400378
Short name T337
Test name
Test status
Simulation time 110121208 ps
CPU time 4.19 seconds
Started Feb 04 12:47:33 PM PST 24
Finished Feb 04 12:47:41 PM PST 24
Peak memory 210404 kb
Host smart-34020fc8-80c3-4704-bc1d-bae5be4aeeb3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3754400378 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_alert_test.3754400378
Directory /workspace/23.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/23.rom_ctrl_corrupt_sig_fatal_chk.1230187892
Short name T288
Test name
Test status
Simulation time 38450430975 ps
CPU time 259.99 seconds
Started Feb 04 12:47:35 PM PST 24
Finished Feb 04 12:52:02 PM PST 24
Peak memory 210780 kb
Host smart-b4a28029-8ae9-4fb5-8ac5-135496770884
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1230187892 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_
corrupt_sig_fatal_chk.1230187892
Directory /workspace/23.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/23.rom_ctrl_kmac_err_chk.3618906277
Short name T330
Test name
Test status
Simulation time 692637888 ps
CPU time 9.14 seconds
Started Feb 04 12:47:31 PM PST 24
Finished Feb 04 12:47:44 PM PST 24
Peak memory 210616 kb
Host smart-ddde05f1-4b7a-4a6b-af20-0ab2e222cde1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3618906277 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_kmac_err_chk.3618906277
Directory /workspace/23.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/23.rom_ctrl_max_throughput_chk.4140059487
Short name T167
Test name
Test status
Simulation time 2120836453 ps
CPU time 17.93 seconds
Started Feb 04 12:47:31 PM PST 24
Finished Feb 04 12:47:53 PM PST 24
Peak memory 210356 kb
Host smart-e3a7a6b0-9b2d-41b1-8c4f-7607aa45787f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4140059487 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_max_throughput_chk.4140059487
Directory /workspace/23.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/23.rom_ctrl_smoke.2149490660
Short name T311
Test name
Test status
Simulation time 8241790883 ps
CPU time 37.51 seconds
Started Feb 04 12:47:26 PM PST 24
Finished Feb 04 12:48:05 PM PST 24
Peak memory 213004 kb
Host smart-3a2358b8-1973-40b2-ab3f-fd3f153b57b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2149490660 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_smoke.2149490660
Directory /workspace/23.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/23.rom_ctrl_stress_all.283503293
Short name T294
Test name
Test status
Simulation time 57394004667 ps
CPU time 110.83 seconds
Started Feb 04 12:47:32 PM PST 24
Finished Feb 04 12:49:26 PM PST 24
Peak memory 218688 kb
Host smart-6c48e920-641b-4715-b0ed-821f7ad4b883
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=283503293 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 23.rom_ctrl_stress_all.283503293
Directory /workspace/23.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/23.rom_ctrl_stress_all_with_rand_reset.728058399
Short name T428
Test name
Test status
Simulation time 13685416391 ps
CPU time 1032.77 seconds
Started Feb 04 12:47:32 PM PST 24
Finished Feb 04 01:04:49 PM PST 24
Peak memory 232564 kb
Host smart-7a44c13a-1ab2-4a3e-a7a6-230ac4377b2a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=728058399 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_stress_all_with_rand_reset.728058399
Directory /workspace/23.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/24.rom_ctrl_alert_test.752179033
Short name T249
Test name
Test status
Simulation time 9113331534 ps
CPU time 13.64 seconds
Started Feb 04 12:47:34 PM PST 24
Finished Feb 04 12:47:51 PM PST 24
Peak memory 210464 kb
Host smart-c296017f-4938-4786-9855-4308a726eabd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=752179033 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_alert_test.752179033
Directory /workspace/24.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/24.rom_ctrl_corrupt_sig_fatal_chk.3295839313
Short name T426
Test name
Test status
Simulation time 126391898451 ps
CPU time 332.5 seconds
Started Feb 04 12:47:33 PM PST 24
Finished Feb 04 12:53:09 PM PST 24
Peak memory 227816 kb
Host smart-3d4977ce-0a07-46e3-ac57-3c3070d6b6b2
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3295839313 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_
corrupt_sig_fatal_chk.3295839313
Directory /workspace/24.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/24.rom_ctrl_kmac_err_chk.892984453
Short name T33
Test name
Test status
Simulation time 723594634 ps
CPU time 9.3 seconds
Started Feb 04 12:47:46 PM PST 24
Finished Feb 04 12:47:57 PM PST 24
Peak memory 210624 kb
Host smart-9c5436f9-20bb-4dff-9661-cec081ae218d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=892984453 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_kmac_err_chk.892984453
Directory /workspace/24.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/24.rom_ctrl_max_throughput_chk.2741206016
Short name T218
Test name
Test status
Simulation time 1459040675 ps
CPU time 14.07 seconds
Started Feb 04 12:47:35 PM PST 24
Finished Feb 04 12:47:51 PM PST 24
Peak memory 210396 kb
Host smart-0e5188c8-7731-4842-abba-45de8216cce7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2741206016 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_max_throughput_chk.2741206016
Directory /workspace/24.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/24.rom_ctrl_smoke.2314519181
Short name T236
Test name
Test status
Simulation time 3530344205 ps
CPU time 30.26 seconds
Started Feb 04 12:47:46 PM PST 24
Finished Feb 04 12:48:18 PM PST 24
Peak memory 211928 kb
Host smart-8c190325-71a1-4a04-9150-3095100ceced
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2314519181 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_smoke.2314519181
Directory /workspace/24.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/24.rom_ctrl_stress_all.3767078924
Short name T57
Test name
Test status
Simulation time 213406708 ps
CPU time 10.57 seconds
Started Feb 04 12:47:32 PM PST 24
Finished Feb 04 12:47:47 PM PST 24
Peak memory 213572 kb
Host smart-816cf147-282e-4c40-9ac1-961af7f4e183
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3767078924 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 24.rom_ctrl_stress_all.3767078924
Directory /workspace/24.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/25.rom_ctrl_alert_test.911746108
Short name T160
Test name
Test status
Simulation time 4091970453 ps
CPU time 8.58 seconds
Started Feb 04 12:47:35 PM PST 24
Finished Feb 04 12:47:46 PM PST 24
Peak memory 210496 kb
Host smart-0c0099b0-c9fe-4b96-bad3-677fdc22ee35
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=911746108 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_alert_test.911746108
Directory /workspace/25.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/25.rom_ctrl_corrupt_sig_fatal_chk.1686654541
Short name T216
Test name
Test status
Simulation time 31557693139 ps
CPU time 160.55 seconds
Started Feb 04 12:47:34 PM PST 24
Finished Feb 04 12:50:18 PM PST 24
Peak memory 211080 kb
Host smart-bbb0d44c-f247-4e2a-af58-a29aad3d52b1
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1686654541 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_
corrupt_sig_fatal_chk.1686654541
Directory /workspace/25.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/25.rom_ctrl_kmac_err_chk.2332600021
Short name T229
Test name
Test status
Simulation time 4442088991 ps
CPU time 19.92 seconds
Started Feb 04 12:47:42 PM PST 24
Finished Feb 04 12:48:04 PM PST 24
Peak memory 210880 kb
Host smart-331b6aca-00c9-40f7-91ec-03b7439de48b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2332600021 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_kmac_err_chk.2332600021
Directory /workspace/25.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/25.rom_ctrl_max_throughput_chk.3119994076
Short name T379
Test name
Test status
Simulation time 98706439 ps
CPU time 5.41 seconds
Started Feb 04 12:47:43 PM PST 24
Finished Feb 04 12:47:50 PM PST 24
Peak memory 210276 kb
Host smart-4883e2b4-6b99-4fd6-97be-cb8e7d8a3720
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3119994076 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_max_throughput_chk.3119994076
Directory /workspace/25.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/25.rom_ctrl_smoke.4069023738
Short name T362
Test name
Test status
Simulation time 6104471982 ps
CPU time 36.32 seconds
Started Feb 04 12:47:34 PM PST 24
Finished Feb 04 12:48:13 PM PST 24
Peak memory 212436 kb
Host smart-c7b6e0b4-4ca3-49ac-913e-8642edaabc94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4069023738 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_smoke.4069023738
Directory /workspace/25.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/25.rom_ctrl_stress_all.1673375774
Short name T369
Test name
Test status
Simulation time 18838095166 ps
CPU time 39.62 seconds
Started Feb 04 12:47:32 PM PST 24
Finished Feb 04 12:48:16 PM PST 24
Peak memory 215660 kb
Host smart-ec6f8049-1219-4f40-bcb6-c27cc587ec94
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1673375774 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 25.rom_ctrl_stress_all.1673375774
Directory /workspace/25.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/25.rom_ctrl_stress_all_with_rand_reset.2324063703
Short name T319
Test name
Test status
Simulation time 336367200124 ps
CPU time 6172.33 seconds
Started Feb 04 12:47:42 PM PST 24
Finished Feb 04 02:30:37 PM PST 24
Peak memory 230760 kb
Host smart-fa27cd6d-5994-447f-951b-94d2ce05d5de
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2324063703 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_stress_all_with_rand_reset.2324063703
Directory /workspace/25.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/26.rom_ctrl_alert_test.3938158668
Short name T63
Test name
Test status
Simulation time 719842091 ps
CPU time 7.89 seconds
Started Feb 04 12:47:42 PM PST 24
Finished Feb 04 12:47:52 PM PST 24
Peak memory 210292 kb
Host smart-20a4de35-dd64-4a68-a797-2c575b964ce4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3938158668 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_alert_test.3938158668
Directory /workspace/26.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/26.rom_ctrl_corrupt_sig_fatal_chk.3812064138
Short name T232
Test name
Test status
Simulation time 46183510454 ps
CPU time 221.19 seconds
Started Feb 04 12:47:27 PM PST 24
Finished Feb 04 12:51:10 PM PST 24
Peak memory 231948 kb
Host smart-1c6b6004-81a5-4516-8c3d-1cdd4176f25b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3812064138 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_
corrupt_sig_fatal_chk.3812064138
Directory /workspace/26.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/26.rom_ctrl_kmac_err_chk.3561825545
Short name T187
Test name
Test status
Simulation time 5805229721 ps
CPU time 18.27 seconds
Started Feb 04 12:47:30 PM PST 24
Finished Feb 04 12:47:53 PM PST 24
Peak memory 210992 kb
Host smart-f92bc2be-d3bd-424e-8740-7b1dd67836c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3561825545 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_kmac_err_chk.3561825545
Directory /workspace/26.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/26.rom_ctrl_max_throughput_chk.1239290298
Short name T265
Test name
Test status
Simulation time 3631359217 ps
CPU time 16.06 seconds
Started Feb 04 12:47:29 PM PST 24
Finished Feb 04 12:47:51 PM PST 24
Peak memory 210488 kb
Host smart-ec63bdbd-9a1f-49b4-8437-c0db3fe1619a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1239290298 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_max_throughput_chk.1239290298
Directory /workspace/26.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/26.rom_ctrl_smoke.2334807710
Short name T425
Test name
Test status
Simulation time 11007270198 ps
CPU time 19.5 seconds
Started Feb 04 12:47:42 PM PST 24
Finished Feb 04 12:48:04 PM PST 24
Peak memory 212556 kb
Host smart-8adf385d-b54a-418c-9414-15a1fcbad58f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2334807710 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_smoke.2334807710
Directory /workspace/26.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/26.rom_ctrl_stress_all.982335505
Short name T212
Test name
Test status
Simulation time 32106863675 ps
CPU time 77.99 seconds
Started Feb 04 12:47:34 PM PST 24
Finished Feb 04 12:48:55 PM PST 24
Peak memory 218664 kb
Host smart-9c8dab0f-b56b-4195-b4b2-99444a16903c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=982335505 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 26.rom_ctrl_stress_all.982335505
Directory /workspace/26.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/26.rom_ctrl_stress_all_with_rand_reset.604818033
Short name T230
Test name
Test status
Simulation time 74959172769 ps
CPU time 753.03 seconds
Started Feb 04 12:47:35 PM PST 24
Finished Feb 04 01:00:10 PM PST 24
Peak memory 227640 kb
Host smart-ce6c3109-3510-4097-a314-e76dd09ff887
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=604818033 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_stress_all_with_rand_reset.604818033
Directory /workspace/26.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/27.rom_ctrl_alert_test.2315687974
Short name T99
Test name
Test status
Simulation time 1963342552 ps
CPU time 15.55 seconds
Started Feb 04 12:47:44 PM PST 24
Finished Feb 04 12:48:00 PM PST 24
Peak memory 210564 kb
Host smart-a2cbfe27-b984-4226-8721-0ffcfff6ec78
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2315687974 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_alert_test.2315687974
Directory /workspace/27.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/27.rom_ctrl_corrupt_sig_fatal_chk.3681731919
Short name T198
Test name
Test status
Simulation time 42950047101 ps
CPU time 224.32 seconds
Started Feb 04 12:47:35 PM PST 24
Finished Feb 04 12:51:25 PM PST 24
Peak memory 236964 kb
Host smart-ba3cd879-b9bb-4207-b93d-a8c89415b348
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3681731919 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_
corrupt_sig_fatal_chk.3681731919
Directory /workspace/27.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/27.rom_ctrl_kmac_err_chk.1500441636
Short name T270
Test name
Test status
Simulation time 575604748 ps
CPU time 13.43 seconds
Started Feb 04 12:47:35 PM PST 24
Finished Feb 04 12:47:51 PM PST 24
Peak memory 210556 kb
Host smart-5e019cf4-c15a-4e17-8de3-a87b7237df5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1500441636 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_kmac_err_chk.1500441636
Directory /workspace/27.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/27.rom_ctrl_max_throughput_chk.1143364767
Short name T275
Test name
Test status
Simulation time 4487304386 ps
CPU time 12.3 seconds
Started Feb 04 12:47:35 PM PST 24
Finished Feb 04 12:47:54 PM PST 24
Peak memory 210388 kb
Host smart-273ccfe1-b6d5-40b7-a640-af91742ae476
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1143364767 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_max_throughput_chk.1143364767
Directory /workspace/27.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/27.rom_ctrl_smoke.1934649729
Short name T419
Test name
Test status
Simulation time 7896053025 ps
CPU time 21.93 seconds
Started Feb 04 12:47:32 PM PST 24
Finished Feb 04 12:47:58 PM PST 24
Peak memory 212356 kb
Host smart-bb2745dc-9eac-478c-8656-8e99a7d753bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1934649729 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_smoke.1934649729
Directory /workspace/27.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/27.rom_ctrl_stress_all.3970417516
Short name T410
Test name
Test status
Simulation time 8546405789 ps
CPU time 70.45 seconds
Started Feb 04 12:47:29 PM PST 24
Finished Feb 04 12:48:45 PM PST 24
Peak memory 215576 kb
Host smart-6781d6f7-26c5-4815-8b18-cfdb309de642
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3970417516 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 27.rom_ctrl_stress_all.3970417516
Directory /workspace/27.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/27.rom_ctrl_stress_all_with_rand_reset.3049583951
Short name T423
Test name
Test status
Simulation time 58747767965 ps
CPU time 2958.65 seconds
Started Feb 04 12:47:31 PM PST 24
Finished Feb 04 01:36:54 PM PST 24
Peak memory 228312 kb
Host smart-2e29adba-6ff3-4d46-b8b7-28ff59bb5bd3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3049583951 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_stress_all_with_rand_reset.3049583951
Directory /workspace/27.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/28.rom_ctrl_alert_test.1148038502
Short name T166
Test name
Test status
Simulation time 8564565950 ps
CPU time 12.54 seconds
Started Feb 04 12:47:50 PM PST 24
Finished Feb 04 12:48:03 PM PST 24
Peak memory 210572 kb
Host smart-ffa52c9e-ec6a-45da-85b6-ab88671f39ab
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1148038502 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_alert_test.1148038502
Directory /workspace/28.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/28.rom_ctrl_corrupt_sig_fatal_chk.2276823320
Short name T327
Test name
Test status
Simulation time 5517125077 ps
CPU time 111.2 seconds
Started Feb 04 12:47:46 PM PST 24
Finished Feb 04 12:49:39 PM PST 24
Peak memory 211140 kb
Host smart-c7d540b8-58bf-4760-bb59-975561481df8
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2276823320 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_
corrupt_sig_fatal_chk.2276823320
Directory /workspace/28.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/28.rom_ctrl_kmac_err_chk.1015133725
Short name T321
Test name
Test status
Simulation time 13199614059 ps
CPU time 28.83 seconds
Started Feb 04 12:47:46 PM PST 24
Finished Feb 04 12:48:16 PM PST 24
Peak memory 211204 kb
Host smart-87d1f5c1-4241-422b-9a36-1fb869d62abd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1015133725 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_kmac_err_chk.1015133725
Directory /workspace/28.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/28.rom_ctrl_max_throughput_chk.225231531
Short name T168
Test name
Test status
Simulation time 1922109583 ps
CPU time 16.21 seconds
Started Feb 04 12:47:39 PM PST 24
Finished Feb 04 12:48:00 PM PST 24
Peak memory 210380 kb
Host smart-0a98eed5-a9b4-427c-934d-073f32a62b26
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=225231531 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_max_throughput_chk.225231531
Directory /workspace/28.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/28.rom_ctrl_smoke.2900545158
Short name T98
Test name
Test status
Simulation time 13527422444 ps
CPU time 37.28 seconds
Started Feb 04 12:47:41 PM PST 24
Finished Feb 04 12:48:21 PM PST 24
Peak memory 212668 kb
Host smart-2e15be60-50ab-4662-b8eb-d31f71831ddc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2900545158 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_smoke.2900545158
Directory /workspace/28.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/28.rom_ctrl_stress_all.1554223955
Short name T409
Test name
Test status
Simulation time 2319296480 ps
CPU time 19.59 seconds
Started Feb 04 12:47:50 PM PST 24
Finished Feb 04 12:48:10 PM PST 24
Peak memory 211212 kb
Host smart-3c40cb33-7094-4233-8bce-834745b38b9a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1554223955 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 28.rom_ctrl_stress_all.1554223955
Directory /workspace/28.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/28.rom_ctrl_stress_all_with_rand_reset.1269881875
Short name T188
Test name
Test status
Simulation time 115886969329 ps
CPU time 1365.26 seconds
Started Feb 04 12:47:43 PM PST 24
Finished Feb 04 01:10:30 PM PST 24
Peak memory 235308 kb
Host smart-158f5b1f-8f8b-459b-bfcf-2bc77a6450bf
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1269881875 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_stress_all_with_rand_reset.1269881875
Directory /workspace/28.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/29.rom_ctrl_alert_test.1618441197
Short name T360
Test name
Test status
Simulation time 1697456611 ps
CPU time 6.83 seconds
Started Feb 04 12:47:52 PM PST 24
Finished Feb 04 12:47:59 PM PST 24
Peak memory 210304 kb
Host smart-27a6a0f5-81d3-4274-baef-e6d2fb7184f3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1618441197 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_alert_test.1618441197
Directory /workspace/29.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/29.rom_ctrl_corrupt_sig_fatal_chk.3930500918
Short name T395
Test name
Test status
Simulation time 13818642319 ps
CPU time 162.8 seconds
Started Feb 04 12:47:48 PM PST 24
Finished Feb 04 12:50:32 PM PST 24
Peak memory 227592 kb
Host smart-1a165461-5dee-4003-b2a8-c1540ad0b16a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3930500918 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_
corrupt_sig_fatal_chk.3930500918
Directory /workspace/29.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/29.rom_ctrl_kmac_err_chk.4129780248
Short name T39
Test name
Test status
Simulation time 11690101867 ps
CPU time 21.29 seconds
Started Feb 04 12:47:45 PM PST 24
Finished Feb 04 12:48:07 PM PST 24
Peak memory 211052 kb
Host smart-206ad11e-157d-46cf-b6cf-03f482e2098d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4129780248 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_kmac_err_chk.4129780248
Directory /workspace/29.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/29.rom_ctrl_max_throughput_chk.450779133
Short name T352
Test name
Test status
Simulation time 338853769 ps
CPU time 5.51 seconds
Started Feb 04 12:47:46 PM PST 24
Finished Feb 04 12:47:53 PM PST 24
Peak memory 210520 kb
Host smart-0538aa11-496f-467b-8890-b3eb6d4af92b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=450779133 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_max_throughput_chk.450779133
Directory /workspace/29.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/29.rom_ctrl_smoke.2094404284
Short name T178
Test name
Test status
Simulation time 3129880627 ps
CPU time 19.12 seconds
Started Feb 04 12:47:49 PM PST 24
Finished Feb 04 12:48:09 PM PST 24
Peak memory 212052 kb
Host smart-ca742b90-f8fa-4c05-9b49-9e46e7b25b4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2094404284 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_smoke.2094404284
Directory /workspace/29.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/29.rom_ctrl_stress_all.3887525054
Short name T290
Test name
Test status
Simulation time 4133465039 ps
CPU time 16.37 seconds
Started Feb 04 12:47:48 PM PST 24
Finished Feb 04 12:48:06 PM PST 24
Peak memory 213604 kb
Host smart-8abc19b0-5210-48b1-beca-5b65d6efe42b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3887525054 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 29.rom_ctrl_stress_all.3887525054
Directory /workspace/29.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/29.rom_ctrl_stress_all_with_rand_reset.3932706627
Short name T13
Test name
Test status
Simulation time 22842196801 ps
CPU time 1945.19 seconds
Started Feb 04 12:47:51 PM PST 24
Finished Feb 04 01:20:17 PM PST 24
Peak memory 226044 kb
Host smart-93a46a56-ddfd-4dc9-82ea-bd0a5363ad64
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3932706627 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_stress_all_with_rand_reset.3932706627
Directory /workspace/29.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.rom_ctrl_alert_test.93026699
Short name T335
Test name
Test status
Simulation time 2553320808 ps
CPU time 10.18 seconds
Started Feb 04 12:47:13 PM PST 24
Finished Feb 04 12:47:26 PM PST 24
Peak memory 210532 kb
Host smart-379b7895-1959-4d94-96b7-f6b9b02e9dbf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=93026699 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_alert_test.93026699
Directory /workspace/3.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/3.rom_ctrl_corrupt_sig_fatal_chk.1863240793
Short name T315
Test name
Test status
Simulation time 80606369616 ps
CPU time 407.26 seconds
Started Feb 04 12:47:09 PM PST 24
Finished Feb 04 12:53:59 PM PST 24
Peak memory 237112 kb
Host smart-3754cd00-f7d2-401a-99bd-d60f417cfd77
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1863240793 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_c
orrupt_sig_fatal_chk.1863240793
Directory /workspace/3.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/3.rom_ctrl_kmac_err_chk.4287854294
Short name T251
Test name
Test status
Simulation time 1573165423 ps
CPU time 19.13 seconds
Started Feb 04 12:47:09 PM PST 24
Finished Feb 04 12:47:31 PM PST 24
Peak memory 210764 kb
Host smart-10dbcbec-ed6b-4e30-8a97-e287c309ffcf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4287854294 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_kmac_err_chk.4287854294
Directory /workspace/3.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/3.rom_ctrl_max_throughput_chk.1103225563
Short name T261
Test name
Test status
Simulation time 2830812085 ps
CPU time 9.59 seconds
Started Feb 04 12:47:12 PM PST 24
Finished Feb 04 12:47:23 PM PST 24
Peak memory 210568 kb
Host smart-5277d90d-b6fa-4b5a-95e9-859fb9a2a941
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1103225563 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_max_throughput_chk.1103225563
Directory /workspace/3.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/3.rom_ctrl_sec_cm.1932637006
Short name T51
Test name
Test status
Simulation time 9007217682 ps
CPU time 109.47 seconds
Started Feb 04 12:47:10 PM PST 24
Finished Feb 04 12:49:02 PM PST 24
Peak memory 233928 kb
Host smart-d73c8ead-fc03-4fe1-a432-37b47e770cf9
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1932637006 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_sec_cm.1932637006
Directory /workspace/3.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/3.rom_ctrl_smoke.180995740
Short name T227
Test name
Test status
Simulation time 1566625584 ps
CPU time 23.95 seconds
Started Feb 04 12:47:07 PM PST 24
Finished Feb 04 12:47:34 PM PST 24
Peak memory 211788 kb
Host smart-bb285046-4a93-40df-8a5c-d3c9f5409e62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=180995740 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_smoke.180995740
Directory /workspace/3.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/3.rom_ctrl_stress_all.823066690
Short name T297
Test name
Test status
Simulation time 4139140631 ps
CPU time 45.55 seconds
Started Feb 04 12:47:08 PM PST 24
Finished Feb 04 12:47:56 PM PST 24
Peak memory 211728 kb
Host smart-65fe9913-7281-4c17-a3b0-24f3a0121db2
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=823066690 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 3.rom_ctrl_stress_all.823066690
Directory /workspace/3.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/30.rom_ctrl_alert_test.2147875282
Short name T243
Test name
Test status
Simulation time 29980884971 ps
CPU time 15.39 seconds
Started Feb 04 12:47:44 PM PST 24
Finished Feb 04 12:48:00 PM PST 24
Peak memory 210492 kb
Host smart-7c882ed8-96fa-4451-83be-7dedb2b6d1a4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2147875282 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_alert_test.2147875282
Directory /workspace/30.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/30.rom_ctrl_corrupt_sig_fatal_chk.3687830101
Short name T42
Test name
Test status
Simulation time 130968386879 ps
CPU time 318 seconds
Started Feb 04 12:47:47 PM PST 24
Finished Feb 04 12:53:07 PM PST 24
Peak memory 223940 kb
Host smart-bf5513a6-ee7b-4ab2-b6a8-cad70efcac61
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3687830101 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_
corrupt_sig_fatal_chk.3687830101
Directory /workspace/30.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/30.rom_ctrl_kmac_err_chk.171635382
Short name T413
Test name
Test status
Simulation time 2364862274 ps
CPU time 23.47 seconds
Started Feb 04 12:47:45 PM PST 24
Finished Feb 04 12:48:09 PM PST 24
Peak memory 210524 kb
Host smart-3c910058-ad22-40bf-8ae2-6968394f801a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=171635382 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_kmac_err_chk.171635382
Directory /workspace/30.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/30.rom_ctrl_max_throughput_chk.3213701001
Short name T235
Test name
Test status
Simulation time 5355431522 ps
CPU time 12.93 seconds
Started Feb 04 12:47:45 PM PST 24
Finished Feb 04 12:47:59 PM PST 24
Peak memory 210476 kb
Host smart-3a1906d2-1ad5-41f0-a9cc-80f6699c460b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3213701001 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_max_throughput_chk.3213701001
Directory /workspace/30.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/30.rom_ctrl_smoke.3970666287
Short name T391
Test name
Test status
Simulation time 2644003044 ps
CPU time 13.43 seconds
Started Feb 04 12:47:51 PM PST 24
Finished Feb 04 12:48:06 PM PST 24
Peak memory 211400 kb
Host smart-370b50ef-323b-4e0c-a7cc-a05dacfb776f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3970666287 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_smoke.3970666287
Directory /workspace/30.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/30.rom_ctrl_stress_all.982193713
Short name T165
Test name
Test status
Simulation time 13914184163 ps
CPU time 35.12 seconds
Started Feb 04 12:47:51 PM PST 24
Finished Feb 04 12:48:27 PM PST 24
Peak memory 212644 kb
Host smart-abb1557b-a0d3-4df9-bbff-109fdce02ee0
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=982193713 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 30.rom_ctrl_stress_all.982193713
Directory /workspace/30.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/30.rom_ctrl_stress_all_with_rand_reset.112205183
Short name T334
Test name
Test status
Simulation time 23225563924 ps
CPU time 6502.54 seconds
Started Feb 04 12:47:51 PM PST 24
Finished Feb 04 02:36:15 PM PST 24
Peak memory 235144 kb
Host smart-438f9d4e-338f-46aa-aa8e-1e58397bfa57
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=112205183 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_stress_all_with_rand_reset.112205183
Directory /workspace/30.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.rom_ctrl_alert_test.580195629
Short name T97
Test name
Test status
Simulation time 3433563784 ps
CPU time 10.07 seconds
Started Feb 04 12:47:41 PM PST 24
Finished Feb 04 12:47:54 PM PST 24
Peak memory 210592 kb
Host smart-1df8f96a-e14d-4fb1-9219-90431c171266
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=580195629 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_alert_test.580195629
Directory /workspace/31.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/31.rom_ctrl_corrupt_sig_fatal_chk.2137033503
Short name T61
Test name
Test status
Simulation time 37513244139 ps
CPU time 170.27 seconds
Started Feb 04 12:47:43 PM PST 24
Finished Feb 04 12:50:35 PM PST 24
Peak memory 236984 kb
Host smart-6b627d3f-fe62-4ac4-bc34-631b1afe1f5d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2137033503 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_
corrupt_sig_fatal_chk.2137033503
Directory /workspace/31.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/31.rom_ctrl_kmac_err_chk.2709529901
Short name T281
Test name
Test status
Simulation time 17152243184 ps
CPU time 33.68 seconds
Started Feb 04 12:47:54 PM PST 24
Finished Feb 04 12:48:29 PM PST 24
Peak memory 211304 kb
Host smart-02568fb3-e6bf-4b9a-a2b6-dfab9491f7f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2709529901 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_kmac_err_chk.2709529901
Directory /workspace/31.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/31.rom_ctrl_max_throughput_chk.549124072
Short name T420
Test name
Test status
Simulation time 6035740312 ps
CPU time 13.09 seconds
Started Feb 04 12:47:49 PM PST 24
Finished Feb 04 12:48:03 PM PST 24
Peak memory 210520 kb
Host smart-17ee6f8c-7ae0-4355-984e-8e23d3b68952
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=549124072 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_max_throughput_chk.549124072
Directory /workspace/31.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/31.rom_ctrl_smoke.776225053
Short name T382
Test name
Test status
Simulation time 4055238628 ps
CPU time 34.92 seconds
Started Feb 04 12:47:48 PM PST 24
Finished Feb 04 12:48:24 PM PST 24
Peak memory 211920 kb
Host smart-dbf19997-d839-4329-801c-8ec5520a93cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=776225053 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_smoke.776225053
Directory /workspace/31.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/31.rom_ctrl_stress_all.1303535489
Short name T267
Test name
Test status
Simulation time 10763545398 ps
CPU time 93.16 seconds
Started Feb 04 12:47:47 PM PST 24
Finished Feb 04 12:49:22 PM PST 24
Peak memory 218804 kb
Host smart-2a915b1f-d974-4564-8b1c-639f61f33d22
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1303535489 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 31.rom_ctrl_stress_all.1303535489
Directory /workspace/31.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/32.rom_ctrl_alert_test.3105837655
Short name T202
Test name
Test status
Simulation time 553032885 ps
CPU time 4.39 seconds
Started Feb 04 12:47:47 PM PST 24
Finished Feb 04 12:47:53 PM PST 24
Peak memory 210264 kb
Host smart-826f497c-9ef5-46f4-a32b-480ca9ccef17
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3105837655 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_alert_test.3105837655
Directory /workspace/32.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/32.rom_ctrl_corrupt_sig_fatal_chk.700768252
Short name T245
Test name
Test status
Simulation time 11135357178 ps
CPU time 180.37 seconds
Started Feb 04 12:47:41 PM PST 24
Finished Feb 04 12:50:44 PM PST 24
Peak memory 234056 kb
Host smart-a365a1a4-a3d9-42ac-aaec-2dc06f7e7fcd
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=700768252 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_c
orrupt_sig_fatal_chk.700768252
Directory /workspace/32.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/32.rom_ctrl_kmac_err_chk.2061366566
Short name T262
Test name
Test status
Simulation time 15672904568 ps
CPU time 33.62 seconds
Started Feb 04 12:47:40 PM PST 24
Finished Feb 04 12:48:17 PM PST 24
Peak memory 211060 kb
Host smart-2a2b478b-a1ce-4a55-af04-f7dbb1604be7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2061366566 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_kmac_err_chk.2061366566
Directory /workspace/32.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/32.rom_ctrl_max_throughput_chk.1919533292
Short name T364
Test name
Test status
Simulation time 3585881029 ps
CPU time 11.89 seconds
Started Feb 04 12:47:46 PM PST 24
Finished Feb 04 12:48:00 PM PST 24
Peak memory 210472 kb
Host smart-2cd6cff4-6545-4f39-9e68-ac899c5c8e00
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1919533292 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_max_throughput_chk.1919533292
Directory /workspace/32.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/32.rom_ctrl_smoke.2799403285
Short name T224
Test name
Test status
Simulation time 1041503628 ps
CPU time 13.86 seconds
Started Feb 04 12:47:52 PM PST 24
Finished Feb 04 12:48:07 PM PST 24
Peak memory 212300 kb
Host smart-cfd8fdea-9935-40c6-8bce-d9d9020f7193
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2799403285 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_smoke.2799403285
Directory /workspace/32.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/32.rom_ctrl_stress_all.3544917159
Short name T107
Test name
Test status
Simulation time 11465317340 ps
CPU time 50.48 seconds
Started Feb 04 12:47:39 PM PST 24
Finished Feb 04 12:48:34 PM PST 24
Peak memory 215756 kb
Host smart-14804267-e23d-4fbd-b46b-e0d366520226
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3544917159 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 32.rom_ctrl_stress_all.3544917159
Directory /workspace/32.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/32.rom_ctrl_stress_all_with_rand_reset.2810106329
Short name T406
Test name
Test status
Simulation time 26644957321 ps
CPU time 1454.52 seconds
Started Feb 04 12:47:51 PM PST 24
Finished Feb 04 01:12:07 PM PST 24
Peak memory 235148 kb
Host smart-57a2b3d7-bb98-41aa-8616-f2ffa30e3f68
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2810106329 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_stress_all_with_rand_reset.2810106329
Directory /workspace/32.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.rom_ctrl_alert_test.114303397
Short name T269
Test name
Test status
Simulation time 928150383 ps
CPU time 9.73 seconds
Started Feb 04 12:47:41 PM PST 24
Finished Feb 04 12:47:54 PM PST 24
Peak memory 210364 kb
Host smart-1e5f1eb6-f641-4108-9284-a3fa11b9ea76
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=114303397 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_alert_test.114303397
Directory /workspace/33.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/33.rom_ctrl_corrupt_sig_fatal_chk.1769383773
Short name T328
Test name
Test status
Simulation time 92090063562 ps
CPU time 210.6 seconds
Started Feb 04 12:47:46 PM PST 24
Finished Feb 04 12:51:19 PM PST 24
Peak memory 235804 kb
Host smart-8dba28c3-3890-4ace-99c4-9df23b63c5c7
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1769383773 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_
corrupt_sig_fatal_chk.1769383773
Directory /workspace/33.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/33.rom_ctrl_kmac_err_chk.20903708
Short name T289
Test name
Test status
Simulation time 22620348951 ps
CPU time 33.42 seconds
Started Feb 04 12:47:43 PM PST 24
Finished Feb 04 12:48:18 PM PST 24
Peak memory 211116 kb
Host smart-71b06a71-c002-4d49-b635-a45b59949308
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=20903708 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_kmac_err_chk.20903708
Directory /workspace/33.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/33.rom_ctrl_max_throughput_chk.3473227646
Short name T430
Test name
Test status
Simulation time 1534336109 ps
CPU time 8.09 seconds
Started Feb 04 12:47:48 PM PST 24
Finished Feb 04 12:47:57 PM PST 24
Peak memory 210372 kb
Host smart-98cffa9d-c408-487b-a8d5-8d529473f4e6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3473227646 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_max_throughput_chk.3473227646
Directory /workspace/33.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/33.rom_ctrl_smoke.2102369026
Short name T197
Test name
Test status
Simulation time 9119565512 ps
CPU time 17.87 seconds
Started Feb 04 12:47:40 PM PST 24
Finished Feb 04 12:48:02 PM PST 24
Peak memory 212872 kb
Host smart-5077ac44-8409-4ea5-b503-f93488ae4984
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2102369026 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_smoke.2102369026
Directory /workspace/33.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/33.rom_ctrl_stress_all.579762229
Short name T268
Test name
Test status
Simulation time 19840808297 ps
CPU time 21.53 seconds
Started Feb 04 12:47:44 PM PST 24
Finished Feb 04 12:48:07 PM PST 24
Peak memory 214468 kb
Host smart-542e5d95-7fb7-4d60-8b8f-7dfadec98c96
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=579762229 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 33.rom_ctrl_stress_all.579762229
Directory /workspace/33.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/33.rom_ctrl_stress_all_with_rand_reset.3092497618
Short name T282
Test name
Test status
Simulation time 47253672835 ps
CPU time 1704.38 seconds
Started Feb 04 12:47:46 PM PST 24
Finished Feb 04 01:16:13 PM PST 24
Peak memory 235740 kb
Host smart-04aba788-eb3e-473f-8870-b294b569b5f7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3092497618 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_stress_all_with_rand_reset.3092497618
Directory /workspace/33.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.rom_ctrl_alert_test.2145007492
Short name T388
Test name
Test status
Simulation time 1746586355 ps
CPU time 7.28 seconds
Started Feb 04 12:47:54 PM PST 24
Finished Feb 04 12:48:02 PM PST 24
Peak memory 210512 kb
Host smart-9be525f8-227c-4392-96ce-f19803182a32
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2145007492 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_alert_test.2145007492
Directory /workspace/34.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/34.rom_ctrl_corrupt_sig_fatal_chk.3378431401
Short name T206
Test name
Test status
Simulation time 10446762858 ps
CPU time 153.86 seconds
Started Feb 04 12:47:50 PM PST 24
Finished Feb 04 12:50:25 PM PST 24
Peak memory 224136 kb
Host smart-412510cb-b00a-410b-b84c-88c153b82b29
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3378431401 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_
corrupt_sig_fatal_chk.3378431401
Directory /workspace/34.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/34.rom_ctrl_kmac_err_chk.1255004400
Short name T329
Test name
Test status
Simulation time 3741239656 ps
CPU time 31.07 seconds
Started Feb 04 12:47:42 PM PST 24
Finished Feb 04 12:48:15 PM PST 24
Peak memory 210704 kb
Host smart-f50d7f5c-4bdd-4706-8dbd-4c8ef95d7407
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1255004400 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_kmac_err_chk.1255004400
Directory /workspace/34.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/34.rom_ctrl_max_throughput_chk.2458119564
Short name T320
Test name
Test status
Simulation time 6061276944 ps
CPU time 9.73 seconds
Started Feb 04 12:47:49 PM PST 24
Finished Feb 04 12:48:00 PM PST 24
Peak memory 210476 kb
Host smart-9f39f122-df72-4cc1-b5f7-e2f546faff50
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2458119564 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_max_throughput_chk.2458119564
Directory /workspace/34.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/34.rom_ctrl_smoke.3751534347
Short name T305
Test name
Test status
Simulation time 1430081915 ps
CPU time 13.93 seconds
Started Feb 04 12:47:48 PM PST 24
Finished Feb 04 12:48:03 PM PST 24
Peak memory 212136 kb
Host smart-cfbb4cd4-eac5-46bf-a442-b5e2cf8df344
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3751534347 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_smoke.3751534347
Directory /workspace/34.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/34.rom_ctrl_stress_all.14051276
Short name T213
Test name
Test status
Simulation time 6333300510 ps
CPU time 51.89 seconds
Started Feb 04 12:47:44 PM PST 24
Finished Feb 04 12:48:37 PM PST 24
Peak memory 212488 kb
Host smart-9c2f8a3d-79f6-42f9-87e4-ddbb4589156d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14051276 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +U
VM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n
ame 34.rom_ctrl_stress_all.14051276
Directory /workspace/34.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/34.rom_ctrl_stress_all_with_rand_reset.1160341349
Short name T264
Test name
Test status
Simulation time 94011099276 ps
CPU time 2966.55 seconds
Started Feb 04 12:47:46 PM PST 24
Finished Feb 04 01:37:14 PM PST 24
Peak memory 235188 kb
Host smart-1f307e2c-a2cc-4786-9e39-612dec7bbdcf
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1160341349 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_stress_all_with_rand_reset.1160341349
Directory /workspace/34.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.rom_ctrl_alert_test.3496142505
Short name T365
Test name
Test status
Simulation time 4452483108 ps
CPU time 10.76 seconds
Started Feb 04 12:47:52 PM PST 24
Finished Feb 04 12:48:03 PM PST 24
Peak memory 210524 kb
Host smart-e4e63912-3e38-4b42-9d1d-c1657c169972
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3496142505 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_alert_test.3496142505
Directory /workspace/35.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/35.rom_ctrl_corrupt_sig_fatal_chk.1554262260
Short name T6
Test name
Test status
Simulation time 28746843342 ps
CPU time 247.72 seconds
Started Feb 04 12:47:47 PM PST 24
Finished Feb 04 12:51:56 PM PST 24
Peak memory 211004 kb
Host smart-db95ccb8-3a98-4225-b8c7-a4dea3df3897
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1554262260 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_
corrupt_sig_fatal_chk.1554262260
Directory /workspace/35.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/35.rom_ctrl_kmac_err_chk.2789025584
Short name T278
Test name
Test status
Simulation time 333930174 ps
CPU time 9.45 seconds
Started Feb 04 12:47:54 PM PST 24
Finished Feb 04 12:48:04 PM PST 24
Peak memory 210908 kb
Host smart-10344f38-2ba2-4821-9b5f-b63bc5ce9ef1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2789025584 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_kmac_err_chk.2789025584
Directory /workspace/35.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/35.rom_ctrl_max_throughput_chk.3374645734
Short name T196
Test name
Test status
Simulation time 7678108534 ps
CPU time 16.65 seconds
Started Feb 04 12:47:47 PM PST 24
Finished Feb 04 12:48:05 PM PST 24
Peak memory 210440 kb
Host smart-745bb98c-abea-45b4-a3b6-653747518189
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3374645734 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_max_throughput_chk.3374645734
Directory /workspace/35.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/35.rom_ctrl_smoke.1406966318
Short name T304
Test name
Test status
Simulation time 18123864354 ps
CPU time 18 seconds
Started Feb 04 12:47:46 PM PST 24
Finished Feb 04 12:48:05 PM PST 24
Peak memory 213384 kb
Host smart-42c126e8-33ad-4c45-955c-51a1497577be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1406966318 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_smoke.1406966318
Directory /workspace/35.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/35.rom_ctrl_stress_all.601972895
Short name T272
Test name
Test status
Simulation time 2151374279 ps
CPU time 21.99 seconds
Started Feb 04 12:47:51 PM PST 24
Finished Feb 04 12:48:14 PM PST 24
Peak memory 212660 kb
Host smart-e5495c52-8956-4713-a0d8-edca66f0208a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=601972895 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 35.rom_ctrl_stress_all.601972895
Directory /workspace/35.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/36.rom_ctrl_alert_test.3648896397
Short name T303
Test name
Test status
Simulation time 9811526820 ps
CPU time 13.29 seconds
Started Feb 04 12:48:09 PM PST 24
Finished Feb 04 12:48:23 PM PST 24
Peak memory 210520 kb
Host smart-36adeca2-ee1a-40d9-9050-8b18863c9923
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3648896397 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_alert_test.3648896397
Directory /workspace/36.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/36.rom_ctrl_corrupt_sig_fatal_chk.2369498586
Short name T353
Test name
Test status
Simulation time 5902195026 ps
CPU time 178.21 seconds
Started Feb 04 12:48:09 PM PST 24
Finished Feb 04 12:51:08 PM PST 24
Peak memory 237028 kb
Host smart-45018eca-d470-424a-9c83-d36cd6590474
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2369498586 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_
corrupt_sig_fatal_chk.2369498586
Directory /workspace/36.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/36.rom_ctrl_kmac_err_chk.3427581368
Short name T248
Test name
Test status
Simulation time 1671063957 ps
CPU time 20.08 seconds
Started Feb 04 12:48:11 PM PST 24
Finished Feb 04 12:48:33 PM PST 24
Peak memory 210640 kb
Host smart-321b5dc4-0ae9-4922-9f34-9c35a4373105
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3427581368 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_kmac_err_chk.3427581368
Directory /workspace/36.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/36.rom_ctrl_max_throughput_chk.1483891413
Short name T402
Test name
Test status
Simulation time 4512548394 ps
CPU time 12.06 seconds
Started Feb 04 12:48:12 PM PST 24
Finished Feb 04 12:48:25 PM PST 24
Peak memory 210516 kb
Host smart-c7b9086b-f898-4f2d-99e5-74d650085539
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1483891413 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_max_throughput_chk.1483891413
Directory /workspace/36.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/36.rom_ctrl_smoke.1575395235
Short name T351
Test name
Test status
Simulation time 192932400 ps
CPU time 10.31 seconds
Started Feb 04 12:47:49 PM PST 24
Finished Feb 04 12:48:00 PM PST 24
Peak memory 212168 kb
Host smart-8e82f423-751d-46d6-b421-a349084bc339
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1575395235 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_smoke.1575395235
Directory /workspace/36.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/36.rom_ctrl_stress_all.2581152539
Short name T240
Test name
Test status
Simulation time 4645458699 ps
CPU time 43.07 seconds
Started Feb 04 12:47:46 PM PST 24
Finished Feb 04 12:48:31 PM PST 24
Peak memory 212280 kb
Host smart-727e16bf-9f2c-463b-a999-27a90aecead6
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2581152539 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 36.rom_ctrl_stress_all.2581152539
Directory /workspace/36.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/36.rom_ctrl_stress_all_with_rand_reset.177910570
Short name T195
Test name
Test status
Simulation time 253869698288 ps
CPU time 10539.4 seconds
Started Feb 04 12:48:07 PM PST 24
Finished Feb 04 03:43:50 PM PST 24
Peak memory 239800 kb
Host smart-ec7f7bf8-8b92-4256-8c08-f731d83ea041
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=177910570 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_stress_all_with_rand_reset.177910570
Directory /workspace/36.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.rom_ctrl_alert_test.4110657449
Short name T174
Test name
Test status
Simulation time 520962531 ps
CPU time 5.05 seconds
Started Feb 04 12:48:13 PM PST 24
Finished Feb 04 12:48:19 PM PST 24
Peak memory 210420 kb
Host smart-753e485b-6179-473f-ad51-941cde811d91
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4110657449 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_alert_test.4110657449
Directory /workspace/37.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/37.rom_ctrl_corrupt_sig_fatal_chk.3812059768
Short name T312
Test name
Test status
Simulation time 49335160941 ps
CPU time 141.99 seconds
Started Feb 04 12:48:03 PM PST 24
Finished Feb 04 12:50:30 PM PST 24
Peak memory 227848 kb
Host smart-0a441799-1d7c-4974-b516-ae4816fc0bd7
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3812059768 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_
corrupt_sig_fatal_chk.3812059768
Directory /workspace/37.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/37.rom_ctrl_kmac_err_chk.2413028995
Short name T257
Test name
Test status
Simulation time 16413574792 ps
CPU time 21.46 seconds
Started Feb 04 12:48:10 PM PST 24
Finished Feb 04 12:48:32 PM PST 24
Peak memory 211136 kb
Host smart-71550a5a-179f-4ace-a75d-b34f91e52947
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2413028995 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_kmac_err_chk.2413028995
Directory /workspace/37.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/37.rom_ctrl_smoke.3902327920
Short name T308
Test name
Test status
Simulation time 4474798560 ps
CPU time 34.68 seconds
Started Feb 04 12:48:06 PM PST 24
Finished Feb 04 12:48:43 PM PST 24
Peak memory 212656 kb
Host smart-0c44d452-acc4-4b3d-af97-5e64c8986059
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3902327920 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_smoke.3902327920
Directory /workspace/37.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/37.rom_ctrl_stress_all.593935113
Short name T298
Test name
Test status
Simulation time 1218899729 ps
CPU time 25.52 seconds
Started Feb 04 12:48:10 PM PST 24
Finished Feb 04 12:48:37 PM PST 24
Peak memory 213488 kb
Host smart-cb66ccbb-bbdc-4a5e-a404-83066f2b0cd8
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=593935113 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 37.rom_ctrl_stress_all.593935113
Directory /workspace/37.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/38.rom_ctrl_alert_test.871155501
Short name T333
Test name
Test status
Simulation time 692708445 ps
CPU time 5.85 seconds
Started Feb 04 12:48:18 PM PST 24
Finished Feb 04 12:48:26 PM PST 24
Peak memory 210472 kb
Host smart-aadf3ed4-523c-47be-a03a-27a8ac7d5cf2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=871155501 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_alert_test.871155501
Directory /workspace/38.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/38.rom_ctrl_corrupt_sig_fatal_chk.1424195717
Short name T62
Test name
Test status
Simulation time 61505595404 ps
CPU time 183.79 seconds
Started Feb 04 12:48:11 PM PST 24
Finished Feb 04 12:51:16 PM PST 24
Peak memory 227508 kb
Host smart-877c0e90-124b-4423-8cab-8e2a0e409938
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1424195717 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_
corrupt_sig_fatal_chk.1424195717
Directory /workspace/38.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/38.rom_ctrl_kmac_err_chk.2829837314
Short name T417
Test name
Test status
Simulation time 8803942583 ps
CPU time 17.42 seconds
Started Feb 04 12:48:12 PM PST 24
Finished Feb 04 12:48:30 PM PST 24
Peak memory 211144 kb
Host smart-cc69516a-bce4-498e-b9e0-c8114c6dbc60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2829837314 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_kmac_err_chk.2829837314
Directory /workspace/38.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/38.rom_ctrl_max_throughput_chk.2579417141
Short name T273
Test name
Test status
Simulation time 361396367 ps
CPU time 5.41 seconds
Started Feb 04 12:48:13 PM PST 24
Finished Feb 04 12:48:19 PM PST 24
Peak memory 210412 kb
Host smart-0a667146-ae98-4a3a-b287-5d63f7fc3c1e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2579417141 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_max_throughput_chk.2579417141
Directory /workspace/38.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/38.rom_ctrl_smoke.1332039960
Short name T285
Test name
Test status
Simulation time 10383167698 ps
CPU time 25.36 seconds
Started Feb 04 12:48:12 PM PST 24
Finished Feb 04 12:48:38 PM PST 24
Peak memory 213068 kb
Host smart-da39987f-041e-4aa9-a429-1b6f2d40ea94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1332039960 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_smoke.1332039960
Directory /workspace/38.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/38.rom_ctrl_stress_all.792309452
Short name T18
Test name
Test status
Simulation time 7274435272 ps
CPU time 45.36 seconds
Started Feb 04 12:48:02 PM PST 24
Finished Feb 04 12:48:54 PM PST 24
Peak memory 215708 kb
Host smart-66fb723e-efb5-490f-bb78-8b83197517d3
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=792309452 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 38.rom_ctrl_stress_all.792309452
Directory /workspace/38.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/39.rom_ctrl_alert_test.836395742
Short name T271
Test name
Test status
Simulation time 297887197 ps
CPU time 6.44 seconds
Started Feb 04 12:48:05 PM PST 24
Finished Feb 04 12:48:15 PM PST 24
Peak memory 210448 kb
Host smart-40363b50-8e4c-47bb-a18e-84c6c013ded8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=836395742 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_alert_test.836395742
Directory /workspace/39.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/39.rom_ctrl_corrupt_sig_fatal_chk.4037843123
Short name T339
Test name
Test status
Simulation time 30733235513 ps
CPU time 179.38 seconds
Started Feb 04 12:48:07 PM PST 24
Finished Feb 04 12:51:08 PM PST 24
Peak memory 236260 kb
Host smart-24854628-0c1d-48c1-8f56-1cd67a29b8b1
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4037843123 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_
corrupt_sig_fatal_chk.4037843123
Directory /workspace/39.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/39.rom_ctrl_kmac_err_chk.54805662
Short name T34
Test name
Test status
Simulation time 2021497257 ps
CPU time 21.24 seconds
Started Feb 04 12:48:18 PM PST 24
Finished Feb 04 12:48:41 PM PST 24
Peak memory 212016 kb
Host smart-e08d74b9-495b-46b9-a620-8daf5557ca6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=54805662 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_kmac_err_chk.54805662
Directory /workspace/39.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/39.rom_ctrl_max_throughput_chk.3756012482
Short name T180
Test name
Test status
Simulation time 732444595 ps
CPU time 7.8 seconds
Started Feb 04 12:48:11 PM PST 24
Finished Feb 04 12:48:20 PM PST 24
Peak memory 210424 kb
Host smart-1cc11ec8-04b8-435c-a23e-14192baee7f7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3756012482 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_max_throughput_chk.3756012482
Directory /workspace/39.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/39.rom_ctrl_smoke.654365434
Short name T394
Test name
Test status
Simulation time 1635964185 ps
CPU time 21.86 seconds
Started Feb 04 12:48:07 PM PST 24
Finished Feb 04 12:48:31 PM PST 24
Peak memory 211744 kb
Host smart-ea6ba850-7977-444f-b21c-e530962ebe46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=654365434 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_smoke.654365434
Directory /workspace/39.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/39.rom_ctrl_stress_all.4231763457
Short name T263
Test name
Test status
Simulation time 800623686 ps
CPU time 12.05 seconds
Started Feb 04 12:48:10 PM PST 24
Finished Feb 04 12:48:23 PM PST 24
Peak memory 212448 kb
Host smart-1867f48a-2325-4e0d-a315-590abb26f4ba
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4231763457 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 39.rom_ctrl_stress_all.4231763457
Directory /workspace/39.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/4.rom_ctrl_alert_test.470343266
Short name T173
Test name
Test status
Simulation time 1925858515 ps
CPU time 15.02 seconds
Started Feb 04 12:47:11 PM PST 24
Finished Feb 04 12:47:27 PM PST 24
Peak memory 210476 kb
Host smart-fce22d07-fa29-4405-8bbc-3ffd8a4b3c83
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=470343266 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_alert_test.470343266
Directory /workspace/4.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/4.rom_ctrl_corrupt_sig_fatal_chk.2255735082
Short name T205
Test name
Test status
Simulation time 8394864009 ps
CPU time 98 seconds
Started Feb 04 12:47:13 PM PST 24
Finished Feb 04 12:48:53 PM PST 24
Peak memory 226832 kb
Host smart-14e0fd30-993c-41db-bb0f-0633e665d539
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2255735082 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_c
orrupt_sig_fatal_chk.2255735082
Directory /workspace/4.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/4.rom_ctrl_kmac_err_chk.3320483076
Short name T387
Test name
Test status
Simulation time 3766233121 ps
CPU time 15.34 seconds
Started Feb 04 12:47:13 PM PST 24
Finished Feb 04 12:47:31 PM PST 24
Peak memory 210852 kb
Host smart-69c4832d-10c5-4f09-a048-d855750f10a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3320483076 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_kmac_err_chk.3320483076
Directory /workspace/4.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/4.rom_ctrl_max_throughput_chk.2511431875
Short name T390
Test name
Test status
Simulation time 7270477889 ps
CPU time 15.34 seconds
Started Feb 04 12:47:07 PM PST 24
Finished Feb 04 12:47:25 PM PST 24
Peak memory 210448 kb
Host smart-165d2fd4-4db4-4f9b-adfb-b0e9f2f35a06
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2511431875 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_max_throughput_chk.2511431875
Directory /workspace/4.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/4.rom_ctrl_smoke.3700100807
Short name T338
Test name
Test status
Simulation time 9804648993 ps
CPU time 25.18 seconds
Started Feb 04 12:47:09 PM PST 24
Finished Feb 04 12:47:37 PM PST 24
Peak memory 213136 kb
Host smart-bb76f478-8a74-406d-aaef-2cbc94bbdf6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3700100807 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_smoke.3700100807
Directory /workspace/4.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/4.rom_ctrl_stress_all.1251299448
Short name T252
Test name
Test status
Simulation time 2374039119 ps
CPU time 12.29 seconds
Started Feb 04 12:47:06 PM PST 24
Finished Feb 04 12:47:21 PM PST 24
Peak memory 210544 kb
Host smart-563c11ea-d8fb-4ba8-9d29-d25dd7e2d327
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1251299448 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 4.rom_ctrl_stress_all.1251299448
Directory /workspace/4.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/40.rom_ctrl_alert_test.3797532988
Short name T280
Test name
Test status
Simulation time 40535784906 ps
CPU time 15.91 seconds
Started Feb 04 12:48:06 PM PST 24
Finished Feb 04 12:48:24 PM PST 24
Peak memory 210512 kb
Host smart-6791abd9-b774-473f-955a-3e97b2893843
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3797532988 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_alert_test.3797532988
Directory /workspace/40.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/40.rom_ctrl_corrupt_sig_fatal_chk.4067707626
Short name T95
Test name
Test status
Simulation time 31483402740 ps
CPU time 256.57 seconds
Started Feb 04 12:48:12 PM PST 24
Finished Feb 04 12:52:30 PM PST 24
Peak memory 237128 kb
Host smart-6039b940-c5e8-4593-8cc2-49d035bb8d7d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4067707626 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_
corrupt_sig_fatal_chk.4067707626
Directory /workspace/40.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/40.rom_ctrl_kmac_err_chk.2080389042
Short name T40
Test name
Test status
Simulation time 3490292589 ps
CPU time 31.28 seconds
Started Feb 04 12:48:20 PM PST 24
Finished Feb 04 12:48:54 PM PST 24
Peak memory 210340 kb
Host smart-9c454981-0aa3-4be4-a103-b9715b41add8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2080389042 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_kmac_err_chk.2080389042
Directory /workspace/40.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/40.rom_ctrl_max_throughput_chk.1226736018
Short name T407
Test name
Test status
Simulation time 7610617932 ps
CPU time 16.1 seconds
Started Feb 04 12:48:12 PM PST 24
Finished Feb 04 12:48:30 PM PST 24
Peak memory 210476 kb
Host smart-3eae0e4b-d2ae-4863-99fb-c9842709e47f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1226736018 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_max_throughput_chk.1226736018
Directory /workspace/40.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/40.rom_ctrl_smoke.746303348
Short name T170
Test name
Test status
Simulation time 3853423763 ps
CPU time 35.71 seconds
Started Feb 04 12:48:05 PM PST 24
Finished Feb 04 12:48:44 PM PST 24
Peak memory 212084 kb
Host smart-d9abc3ce-9c52-4e88-beed-f6bf96aeb7ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=746303348 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_smoke.746303348
Directory /workspace/40.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/40.rom_ctrl_stress_all.133922633
Short name T225
Test name
Test status
Simulation time 1793730984 ps
CPU time 14.05 seconds
Started Feb 04 12:48:20 PM PST 24
Finished Feb 04 12:48:37 PM PST 24
Peak memory 210748 kb
Host smart-ec722d4b-d22a-49d6-a864-c48118dcd45f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=133922633 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 40.rom_ctrl_stress_all.133922633
Directory /workspace/40.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/41.rom_ctrl_alert_test.343913563
Short name T411
Test name
Test status
Simulation time 439247126 ps
CPU time 4.28 seconds
Started Feb 04 12:48:16 PM PST 24
Finished Feb 04 12:48:22 PM PST 24
Peak memory 210416 kb
Host smart-e4e0e757-f7b6-4f2a-98de-33568239fcb0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=343913563 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_alert_test.343913563
Directory /workspace/41.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/41.rom_ctrl_corrupt_sig_fatal_chk.2609822248
Short name T43
Test name
Test status
Simulation time 21306693507 ps
CPU time 176.45 seconds
Started Feb 04 12:48:11 PM PST 24
Finished Feb 04 12:51:08 PM PST 24
Peak memory 236380 kb
Host smart-516c920e-76bc-4a8c-af84-b106b644ee81
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2609822248 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_
corrupt_sig_fatal_chk.2609822248
Directory /workspace/41.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/41.rom_ctrl_kmac_err_chk.1827796020
Short name T317
Test name
Test status
Simulation time 2640209235 ps
CPU time 13.91 seconds
Started Feb 04 12:48:07 PM PST 24
Finished Feb 04 12:48:23 PM PST 24
Peak memory 211024 kb
Host smart-37d49306-6c14-44e6-960c-e09f13f29b51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1827796020 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_kmac_err_chk.1827796020
Directory /workspace/41.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/41.rom_ctrl_max_throughput_chk.3282401989
Short name T274
Test name
Test status
Simulation time 2226204736 ps
CPU time 17.79 seconds
Started Feb 04 12:48:18 PM PST 24
Finished Feb 04 12:48:38 PM PST 24
Peak memory 210532 kb
Host smart-eb53d120-4de5-4eea-a87f-ce40b72914d3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3282401989 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_max_throughput_chk.3282401989
Directory /workspace/41.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/41.rom_ctrl_smoke.1212348216
Short name T162
Test name
Test status
Simulation time 6070984144 ps
CPU time 28.17 seconds
Started Feb 04 12:48:08 PM PST 24
Finished Feb 04 12:48:37 PM PST 24
Peak memory 212524 kb
Host smart-26a2d2e4-f16c-459e-88a9-2cdc465c486d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1212348216 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_smoke.1212348216
Directory /workspace/41.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/41.rom_ctrl_stress_all.827777099
Short name T37
Test name
Test status
Simulation time 5981728271 ps
CPU time 62.7 seconds
Started Feb 04 12:48:07 PM PST 24
Finished Feb 04 12:49:11 PM PST 24
Peak memory 214232 kb
Host smart-432e9dc7-ae24-4dbb-8c7f-cca3de1613fd
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=827777099 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 41.rom_ctrl_stress_all.827777099
Directory /workspace/41.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/41.rom_ctrl_stress_all_with_rand_reset.1007683773
Short name T293
Test name
Test status
Simulation time 122201190637 ps
CPU time 4694.87 seconds
Started Feb 04 12:48:10 PM PST 24
Finished Feb 04 02:06:26 PM PST 24
Peak memory 235280 kb
Host smart-6ab1a391-83cc-4b9d-bb6c-795d8d0fd394
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1007683773 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_stress_all_with_rand_reset.1007683773
Directory /workspace/41.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.rom_ctrl_alert_test.293668600
Short name T3
Test name
Test status
Simulation time 4566069896 ps
CPU time 11.94 seconds
Started Feb 04 12:48:11 PM PST 24
Finished Feb 04 12:48:24 PM PST 24
Peak memory 210436 kb
Host smart-3da24a07-f718-45d9-9a77-e2919b6adafd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=293668600 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_alert_test.293668600
Directory /workspace/42.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/42.rom_ctrl_max_throughput_chk.3383834670
Short name T343
Test name
Test status
Simulation time 1475631969 ps
CPU time 13.76 seconds
Started Feb 04 12:48:04 PM PST 24
Finished Feb 04 12:48:22 PM PST 24
Peak memory 210472 kb
Host smart-837a7040-b623-4231-9171-8e46d1f88b56
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3383834670 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_max_throughput_chk.3383834670
Directory /workspace/42.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/42.rom_ctrl_smoke.851412387
Short name T346
Test name
Test status
Simulation time 3569404266 ps
CPU time 31.49 seconds
Started Feb 04 12:48:07 PM PST 24
Finished Feb 04 12:48:40 PM PST 24
Peak memory 211928 kb
Host smart-639d7753-72af-4f91-be4a-4b87b0a31ae0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=851412387 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_smoke.851412387
Directory /workspace/42.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/42.rom_ctrl_stress_all.4142367687
Short name T19
Test name
Test status
Simulation time 135895793 ps
CPU time 11.37 seconds
Started Feb 04 12:48:18 PM PST 24
Finished Feb 04 12:48:31 PM PST 24
Peak memory 210468 kb
Host smart-1d911070-bb67-4a08-b21d-d65c266768f3
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4142367687 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 42.rom_ctrl_stress_all.4142367687
Directory /workspace/42.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/43.rom_ctrl_alert_test.2260284705
Short name T1
Test name
Test status
Simulation time 133031976 ps
CPU time 5.03 seconds
Started Feb 04 12:48:11 PM PST 24
Finished Feb 04 12:48:17 PM PST 24
Peak memory 210524 kb
Host smart-ead4f49d-52b4-4df7-b96b-257c5a84e0eb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2260284705 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_alert_test.2260284705
Directory /workspace/43.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/43.rom_ctrl_corrupt_sig_fatal_chk.1385390209
Short name T375
Test name
Test status
Simulation time 67244722782 ps
CPU time 373.38 seconds
Started Feb 04 12:48:11 PM PST 24
Finished Feb 04 12:54:26 PM PST 24
Peak memory 223916 kb
Host smart-9e0ad621-2574-49d6-8437-6a627e68f6e9
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1385390209 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_
corrupt_sig_fatal_chk.1385390209
Directory /workspace/43.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/43.rom_ctrl_kmac_err_chk.3971107022
Short name T429
Test name
Test status
Simulation time 666502668 ps
CPU time 9.56 seconds
Started Feb 04 12:48:12 PM PST 24
Finished Feb 04 12:48:23 PM PST 24
Peak memory 210684 kb
Host smart-85e8d0f4-f459-4892-8d3e-fdb0e38f2da7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3971107022 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_kmac_err_chk.3971107022
Directory /workspace/43.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/43.rom_ctrl_max_throughput_chk.1325383383
Short name T385
Test name
Test status
Simulation time 444186580 ps
CPU time 5.48 seconds
Started Feb 04 12:48:20 PM PST 24
Finished Feb 04 12:48:28 PM PST 24
Peak memory 210292 kb
Host smart-183b82a4-2fc3-4a47-927d-df6155808e5f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1325383383 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_max_throughput_chk.1325383383
Directory /workspace/43.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/43.rom_ctrl_smoke.2795755927
Short name T185
Test name
Test status
Simulation time 4621555353 ps
CPU time 30.41 seconds
Started Feb 04 12:48:10 PM PST 24
Finished Feb 04 12:48:41 PM PST 24
Peak memory 212424 kb
Host smart-1ecc73da-daae-4e8e-ad06-076896fc5798
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2795755927 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_smoke.2795755927
Directory /workspace/43.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/43.rom_ctrl_stress_all.3744671616
Short name T241
Test name
Test status
Simulation time 398805228 ps
CPU time 21.76 seconds
Started Feb 04 12:48:03 PM PST 24
Finished Feb 04 12:48:30 PM PST 24
Peak memory 214136 kb
Host smart-7fa403e7-3531-4067-8396-4c78b218e5a0
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3744671616 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 43.rom_ctrl_stress_all.3744671616
Directory /workspace/43.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/43.rom_ctrl_stress_all_with_rand_reset.2908326916
Short name T16
Test name
Test status
Simulation time 155025528766 ps
CPU time 6689.42 seconds
Started Feb 04 12:48:11 PM PST 24
Finished Feb 04 02:39:42 PM PST 24
Peak memory 234884 kb
Host smart-967bec9b-b641-4c11-ae10-d2e2389350cc
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2908326916 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_stress_all_with_rand_reset.2908326916
Directory /workspace/43.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.rom_ctrl_alert_test.3692215396
Short name T432
Test name
Test status
Simulation time 85547250 ps
CPU time 4.21 seconds
Started Feb 04 12:48:14 PM PST 24
Finished Feb 04 12:48:20 PM PST 24
Peak memory 210400 kb
Host smart-69e2ad19-42e9-44de-940e-3215a2020784
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3692215396 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_alert_test.3692215396
Directory /workspace/44.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/44.rom_ctrl_corrupt_sig_fatal_chk.1130185304
Short name T316
Test name
Test status
Simulation time 23906002896 ps
CPU time 241.3 seconds
Started Feb 04 12:48:10 PM PST 24
Finished Feb 04 12:52:12 PM PST 24
Peak memory 223908 kb
Host smart-58af656a-4758-40ac-8dd5-d745b6392d59
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1130185304 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_
corrupt_sig_fatal_chk.1130185304
Directory /workspace/44.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/44.rom_ctrl_kmac_err_chk.552411210
Short name T393
Test name
Test status
Simulation time 7543408569 ps
CPU time 32.22 seconds
Started Feb 04 12:48:18 PM PST 24
Finished Feb 04 12:48:52 PM PST 24
Peak memory 211088 kb
Host smart-ab5278fc-a02f-419e-ad36-c16c33a5e92e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=552411210 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_kmac_err_chk.552411210
Directory /workspace/44.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/44.rom_ctrl_max_throughput_chk.1071053467
Short name T350
Test name
Test status
Simulation time 177820094 ps
CPU time 6.77 seconds
Started Feb 04 12:48:13 PM PST 24
Finished Feb 04 12:48:21 PM PST 24
Peak memory 210448 kb
Host smart-75fe89a4-efbc-4f60-8433-410e2580942f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1071053467 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_max_throughput_chk.1071053467
Directory /workspace/44.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/44.rom_ctrl_smoke.311567550
Short name T398
Test name
Test status
Simulation time 13101425632 ps
CPU time 27.74 seconds
Started Feb 04 12:48:20 PM PST 24
Finished Feb 04 12:48:50 PM PST 24
Peak memory 213020 kb
Host smart-4592d0dc-e93f-4aa7-ba7e-31f5845ca0be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=311567550 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_smoke.311567550
Directory /workspace/44.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/44.rom_ctrl_stress_all.3920720233
Short name T392
Test name
Test status
Simulation time 21218471376 ps
CPU time 25.65 seconds
Started Feb 04 12:48:15 PM PST 24
Finished Feb 04 12:48:42 PM PST 24
Peak memory 213536 kb
Host smart-0ce57543-4322-4d9a-9044-f22eadd6533f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3920720233 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 44.rom_ctrl_stress_all.3920720233
Directory /workspace/44.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/44.rom_ctrl_stress_all_with_rand_reset.732778434
Short name T412
Test name
Test status
Simulation time 42070742560 ps
CPU time 1488.63 seconds
Started Feb 04 12:48:11 PM PST 24
Finished Feb 04 01:13:01 PM PST 24
Peak memory 230892 kb
Host smart-017a3727-4b39-47d0-aeae-e74b016872d9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=732778434 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_stress_all_with_rand_reset.732778434
Directory /workspace/44.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.rom_ctrl_alert_test.3490270669
Short name T210
Test name
Test status
Simulation time 85868116 ps
CPU time 4.43 seconds
Started Feb 04 12:48:23 PM PST 24
Finished Feb 04 12:48:29 PM PST 24
Peak memory 210416 kb
Host smart-45f485df-42aa-4387-ad45-7818b6e43573
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3490270669 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_alert_test.3490270669
Directory /workspace/45.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/45.rom_ctrl_corrupt_sig_fatal_chk.2322083214
Short name T296
Test name
Test status
Simulation time 554486666519 ps
CPU time 301.2 seconds
Started Feb 04 12:48:19 PM PST 24
Finished Feb 04 12:53:23 PM PST 24
Peak memory 227656 kb
Host smart-aa5a9156-06cb-4f46-a638-284d5305eed3
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2322083214 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_
corrupt_sig_fatal_chk.2322083214
Directory /workspace/45.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/45.rom_ctrl_kmac_err_chk.931137727
Short name T373
Test name
Test status
Simulation time 2556433778 ps
CPU time 25.86 seconds
Started Feb 04 12:48:24 PM PST 24
Finished Feb 04 12:48:51 PM PST 24
Peak memory 210712 kb
Host smart-dbe339dc-52b5-4049-ad1d-f7d0c8144ba9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=931137727 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_kmac_err_chk.931137727
Directory /workspace/45.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/45.rom_ctrl_max_throughput_chk.94464916
Short name T377
Test name
Test status
Simulation time 6686803892 ps
CPU time 14.71 seconds
Started Feb 04 12:48:09 PM PST 24
Finished Feb 04 12:48:25 PM PST 24
Peak memory 210504 kb
Host smart-f25ed959-f2e7-4ebb-a4c1-28fb16117751
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=94464916 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_max_throughput_chk.94464916
Directory /workspace/45.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/45.rom_ctrl_smoke.2546308182
Short name T20
Test name
Test status
Simulation time 744855599 ps
CPU time 10.08 seconds
Started Feb 04 12:48:05 PM PST 24
Finished Feb 04 12:48:19 PM PST 24
Peak memory 212168 kb
Host smart-656e9097-b5a6-484a-90ac-50d420ed3900
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2546308182 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_smoke.2546308182
Directory /workspace/45.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/45.rom_ctrl_stress_all.2622641852
Short name T100
Test name
Test status
Simulation time 651481972 ps
CPU time 18.52 seconds
Started Feb 04 12:48:15 PM PST 24
Finished Feb 04 12:48:35 PM PST 24
Peak memory 212940 kb
Host smart-141d4783-7e23-4e30-a48c-217bf1a416d9
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2622641852 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 45.rom_ctrl_stress_all.2622641852
Directory /workspace/45.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/45.rom_ctrl_stress_all_with_rand_reset.3877502567
Short name T414
Test name
Test status
Simulation time 110134656059 ps
CPU time 4104.79 seconds
Started Feb 04 12:48:22 PM PST 24
Finished Feb 04 01:56:50 PM PST 24
Peak memory 236576 kb
Host smart-2afa71fb-6700-4d74-b781-a06f3f3be699
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3877502567 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_stress_all_with_rand_reset.3877502567
Directory /workspace/45.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.rom_ctrl_alert_test.2346099353
Short name T190
Test name
Test status
Simulation time 1152567877 ps
CPU time 6.41 seconds
Started Feb 04 12:48:22 PM PST 24
Finished Feb 04 12:48:31 PM PST 24
Peak memory 210424 kb
Host smart-92bebfe7-e9be-4695-9227-093fef4c398b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2346099353 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_alert_test.2346099353
Directory /workspace/46.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/46.rom_ctrl_corrupt_sig_fatal_chk.1635018495
Short name T8
Test name
Test status
Simulation time 2552494106 ps
CPU time 150.67 seconds
Started Feb 04 12:48:24 PM PST 24
Finished Feb 04 12:50:56 PM PST 24
Peak memory 223832 kb
Host smart-51b659fd-1c73-4425-93e5-7087e9d7a11c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1635018495 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_
corrupt_sig_fatal_chk.1635018495
Directory /workspace/46.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/46.rom_ctrl_kmac_err_chk.953794706
Short name T418
Test name
Test status
Simulation time 12079072697 ps
CPU time 28.47 seconds
Started Feb 04 12:48:22 PM PST 24
Finished Feb 04 12:48:53 PM PST 24
Peak memory 210972 kb
Host smart-ee813f08-5745-450c-a1ac-e0b7993c1374
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=953794706 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_kmac_err_chk.953794706
Directory /workspace/46.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/46.rom_ctrl_max_throughput_chk.2534778130
Short name T378
Test name
Test status
Simulation time 2827529371 ps
CPU time 9.14 seconds
Started Feb 04 12:48:30 PM PST 24
Finished Feb 04 12:48:44 PM PST 24
Peak memory 210448 kb
Host smart-b9bfc0f5-7d79-490f-a676-5ddddc155658
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2534778130 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_max_throughput_chk.2534778130
Directory /workspace/46.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/46.rom_ctrl_smoke.770757594
Short name T424
Test name
Test status
Simulation time 8301459233 ps
CPU time 22.83 seconds
Started Feb 04 12:48:24 PM PST 24
Finished Feb 04 12:48:48 PM PST 24
Peak memory 213532 kb
Host smart-ef8b91d3-21a5-493c-bd90-47b71851c5c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=770757594 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_smoke.770757594
Directory /workspace/46.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/46.rom_ctrl_stress_all.2344323836
Short name T234
Test name
Test status
Simulation time 34596769057 ps
CPU time 77.01 seconds
Started Feb 04 12:48:15 PM PST 24
Finished Feb 04 12:49:34 PM PST 24
Peak memory 218656 kb
Host smart-9b15b73d-e134-4f9f-ba7b-3383b1e93527
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2344323836 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 46.rom_ctrl_stress_all.2344323836
Directory /workspace/46.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/47.rom_ctrl_alert_test.1373934401
Short name T286
Test name
Test status
Simulation time 1409214487 ps
CPU time 12 seconds
Started Feb 04 12:48:09 PM PST 24
Finished Feb 04 12:48:22 PM PST 24
Peak memory 210532 kb
Host smart-acd6ec59-5791-4552-b8b0-8f4c66eda182
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1373934401 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_alert_test.1373934401
Directory /workspace/47.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/47.rom_ctrl_corrupt_sig_fatal_chk.2219255030
Short name T200
Test name
Test status
Simulation time 110200391926 ps
CPU time 366.72 seconds
Started Feb 04 12:48:22 PM PST 24
Finished Feb 04 12:54:31 PM PST 24
Peak memory 210732 kb
Host smart-be771ff6-21fc-43cf-b4f9-5432ce745cb1
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2219255030 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_
corrupt_sig_fatal_chk.2219255030
Directory /workspace/47.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/47.rom_ctrl_kmac_err_chk.2707601830
Short name T401
Test name
Test status
Simulation time 2732517021 ps
CPU time 25.28 seconds
Started Feb 04 12:48:29 PM PST 24
Finished Feb 04 12:48:59 PM PST 24
Peak memory 210804 kb
Host smart-f219464e-3872-4e32-9a44-ec4a0ccd3d5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2707601830 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_kmac_err_chk.2707601830
Directory /workspace/47.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/47.rom_ctrl_max_throughput_chk.3301313650
Short name T254
Test name
Test status
Simulation time 2120432432 ps
CPU time 12.14 seconds
Started Feb 04 12:48:29 PM PST 24
Finished Feb 04 12:48:45 PM PST 24
Peak memory 210400 kb
Host smart-ee4e2890-db40-4642-a6f2-b8785549b90c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3301313650 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_max_throughput_chk.3301313650
Directory /workspace/47.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/47.rom_ctrl_smoke.2307884348
Short name T403
Test name
Test status
Simulation time 192198316 ps
CPU time 10.03 seconds
Started Feb 04 12:48:22 PM PST 24
Finished Feb 04 12:48:34 PM PST 24
Peak memory 212116 kb
Host smart-15e6b398-08de-4e96-9e2e-cc05e1ab96b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2307884348 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_smoke.2307884348
Directory /workspace/47.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/47.rom_ctrl_stress_all.3994066199
Short name T177
Test name
Test status
Simulation time 415099704 ps
CPU time 5.61 seconds
Started Feb 04 12:48:20 PM PST 24
Finished Feb 04 12:48:28 PM PST 24
Peak memory 210420 kb
Host smart-bc9feada-b75b-4ac7-93d6-7557fbbd8b9d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3994066199 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 47.rom_ctrl_stress_all.3994066199
Directory /workspace/47.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/48.rom_ctrl_alert_test.458002887
Short name T176
Test name
Test status
Simulation time 1844622397 ps
CPU time 14.72 seconds
Started Feb 04 12:48:16 PM PST 24
Finished Feb 04 12:48:32 PM PST 24
Peak memory 210436 kb
Host smart-d8775b62-f90c-42ae-8b97-b4734bf1fe6e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=458002887 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_alert_test.458002887
Directory /workspace/48.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/48.rom_ctrl_corrupt_sig_fatal_chk.1605903205
Short name T427
Test name
Test status
Simulation time 43935587536 ps
CPU time 163.4 seconds
Started Feb 04 12:48:32 PM PST 24
Finished Feb 04 12:51:21 PM PST 24
Peak memory 210888 kb
Host smart-470e27cd-c56a-49fe-a9af-dd79af66898f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1605903205 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_
corrupt_sig_fatal_chk.1605903205
Directory /workspace/48.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/48.rom_ctrl_kmac_err_chk.1919760571
Short name T287
Test name
Test status
Simulation time 172394986 ps
CPU time 9.29 seconds
Started Feb 04 12:48:19 PM PST 24
Finished Feb 04 12:48:31 PM PST 24
Peak memory 210644 kb
Host smart-a4104a19-04ad-45d9-aa90-8a6506eeae26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1919760571 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_kmac_err_chk.1919760571
Directory /workspace/48.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/48.rom_ctrl_max_throughput_chk.3696152790
Short name T250
Test name
Test status
Simulation time 717606119 ps
CPU time 9.52 seconds
Started Feb 04 12:48:31 PM PST 24
Finished Feb 04 12:48:46 PM PST 24
Peak memory 210544 kb
Host smart-cec7d3fb-3bcc-4750-a124-165f97127f7c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3696152790 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_max_throughput_chk.3696152790
Directory /workspace/48.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/48.rom_ctrl_smoke.548529425
Short name T363
Test name
Test status
Simulation time 2384231003 ps
CPU time 28.97 seconds
Started Feb 04 12:48:20 PM PST 24
Finished Feb 04 12:48:52 PM PST 24
Peak memory 212276 kb
Host smart-c79ad17d-82ba-42bd-8ed1-4e386c22c21a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=548529425 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_smoke.548529425
Directory /workspace/48.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/48.rom_ctrl_stress_all.3965530563
Short name T260
Test name
Test status
Simulation time 22629670897 ps
CPU time 50.93 seconds
Started Feb 04 12:48:19 PM PST 24
Finished Feb 04 12:49:13 PM PST 24
Peak memory 213356 kb
Host smart-2e1c1814-bac8-4cf4-8e3b-f9c26aab026b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3965530563 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 48.rom_ctrl_stress_all.3965530563
Directory /workspace/48.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/48.rom_ctrl_stress_all_with_rand_reset.3476015933
Short name T96
Test name
Test status
Simulation time 34353640151 ps
CPU time 1339.29 seconds
Started Feb 04 12:48:32 PM PST 24
Finished Feb 04 01:10:57 PM PST 24
Peak memory 236732 kb
Host smart-65d893fd-b5df-47be-949d-3c4e965613e5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3476015933 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_stress_all_with_rand_reset.3476015933
Directory /workspace/48.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/49.rom_ctrl_alert_test.2285895299
Short name T159
Test name
Test status
Simulation time 897632442 ps
CPU time 9.76 seconds
Started Feb 04 12:48:15 PM PST 24
Finished Feb 04 12:48:27 PM PST 24
Peak memory 210436 kb
Host smart-100998e8-b3e0-48cc-b6cb-4c0f84e1f37e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2285895299 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_alert_test.2285895299
Directory /workspace/49.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/49.rom_ctrl_corrupt_sig_fatal_chk.1069282538
Short name T358
Test name
Test status
Simulation time 3639932310 ps
CPU time 111.48 seconds
Started Feb 04 12:48:31 PM PST 24
Finished Feb 04 12:50:28 PM PST 24
Peak memory 227488 kb
Host smart-34bacd3b-e0df-4d39-86a3-c444fe60f213
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1069282538 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_
corrupt_sig_fatal_chk.1069282538
Directory /workspace/49.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/49.rom_ctrl_kmac_err_chk.1795663232
Short name T220
Test name
Test status
Simulation time 9918667180 ps
CPU time 24.38 seconds
Started Feb 04 12:48:17 PM PST 24
Finished Feb 04 12:48:43 PM PST 24
Peak memory 210512 kb
Host smart-4a0932d8-23b7-4edd-8a19-fd649c2ebc67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1795663232 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_kmac_err_chk.1795663232
Directory /workspace/49.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/49.rom_ctrl_max_throughput_chk.1126628539
Short name T114
Test name
Test status
Simulation time 1325026674 ps
CPU time 12.95 seconds
Started Feb 04 12:48:32 PM PST 24
Finished Feb 04 12:48:51 PM PST 24
Peak memory 210536 kb
Host smart-b301c363-0ff1-4f6c-b54e-12b3b064be4c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1126628539 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_max_throughput_chk.1126628539
Directory /workspace/49.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/49.rom_ctrl_smoke.4133475438
Short name T325
Test name
Test status
Simulation time 4203637736 ps
CPU time 33.87 seconds
Started Feb 04 12:48:31 PM PST 24
Finished Feb 04 12:49:10 PM PST 24
Peak memory 211736 kb
Host smart-cf9ea6b5-56d1-4134-a9bc-862ab67da1f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4133475438 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_smoke.4133475438
Directory /workspace/49.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/49.rom_ctrl_stress_all.914104447
Short name T384
Test name
Test status
Simulation time 12018958104 ps
CPU time 16.61 seconds
Started Feb 04 12:48:17 PM PST 24
Finished Feb 04 12:48:35 PM PST 24
Peak memory 210428 kb
Host smart-1449c546-30d5-4866-87f3-ee85f73a8d56
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=914104447 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 49.rom_ctrl_stress_all.914104447
Directory /workspace/49.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/5.rom_ctrl_alert_test.805236213
Short name T22
Test name
Test status
Simulation time 1803731327 ps
CPU time 14.4 seconds
Started Feb 04 12:47:13 PM PST 24
Finished Feb 04 12:47:30 PM PST 24
Peak memory 210420 kb
Host smart-4b26c71d-fff6-4c5b-b8ce-3ea5f734f932
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=805236213 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_alert_test.805236213
Directory /workspace/5.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/5.rom_ctrl_corrupt_sig_fatal_chk.1615943105
Short name T175
Test name
Test status
Simulation time 64561370788 ps
CPU time 608.58 seconds
Started Feb 04 12:47:12 PM PST 24
Finished Feb 04 12:57:22 PM PST 24
Peak memory 223876 kb
Host smart-150ade93-bb17-4887-a930-9c75458b0ad5
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1615943105 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_c
orrupt_sig_fatal_chk.1615943105
Directory /workspace/5.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/5.rom_ctrl_kmac_err_chk.4079837229
Short name T35
Test name
Test status
Simulation time 334057268 ps
CPU time 9.45 seconds
Started Feb 04 12:47:04 PM PST 24
Finished Feb 04 12:47:14 PM PST 24
Peak memory 210612 kb
Host smart-7bf430a5-0d01-401b-8d4f-b5180adf3272
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4079837229 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_kmac_err_chk.4079837229
Directory /workspace/5.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/5.rom_ctrl_max_throughput_chk.1070379364
Short name T102
Test name
Test status
Simulation time 4567036742 ps
CPU time 12.17 seconds
Started Feb 04 12:47:13 PM PST 24
Finished Feb 04 12:47:28 PM PST 24
Peak memory 210524 kb
Host smart-ed3237b3-d684-4499-bb9c-173b867fe146
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1070379364 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_max_throughput_chk.1070379364
Directory /workspace/5.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/5.rom_ctrl_smoke.3521238154
Short name T408
Test name
Test status
Simulation time 4147776885 ps
CPU time 17.03 seconds
Started Feb 04 12:47:08 PM PST 24
Finished Feb 04 12:47:27 PM PST 24
Peak memory 212096 kb
Host smart-81415d9c-66c7-4fa3-b0b1-c47424c3a088
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3521238154 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_smoke.3521238154
Directory /workspace/5.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/5.rom_ctrl_stress_all.1679097470
Short name T7
Test name
Test status
Simulation time 9404808042 ps
CPU time 54.69 seconds
Started Feb 04 12:47:06 PM PST 24
Finished Feb 04 12:48:03 PM PST 24
Peak memory 218712 kb
Host smart-f5f69233-e858-49da-8c39-fa95d74b7d31
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1679097470 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 5.rom_ctrl_stress_all.1679097470
Directory /workspace/5.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/5.rom_ctrl_stress_all_with_rand_reset.3498472449
Short name T237
Test name
Test status
Simulation time 55941922947 ps
CPU time 2931.81 seconds
Started Feb 04 12:47:08 PM PST 24
Finished Feb 04 01:36:02 PM PST 24
Peak memory 237648 kb
Host smart-ad5f9580-884d-4583-9c9d-0c16c9804289
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3498472449 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_stress_all_with_rand_reset.3498472449
Directory /workspace/5.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.rom_ctrl_alert_test.2583037638
Short name T208
Test name
Test status
Simulation time 572908416 ps
CPU time 7.9 seconds
Started Feb 04 12:47:18 PM PST 24
Finished Feb 04 12:47:33 PM PST 24
Peak memory 210532 kb
Host smart-1b791537-04c6-4c82-b36c-b18f562e5f5f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2583037638 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_alert_test.2583037638
Directory /workspace/6.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/6.rom_ctrl_kmac_err_chk.2155369742
Short name T323
Test name
Test status
Simulation time 1129697872 ps
CPU time 16.93 seconds
Started Feb 04 12:47:23 PM PST 24
Finished Feb 04 12:47:43 PM PST 24
Peak memory 210648 kb
Host smart-b4583f52-5f26-4e0f-9cfe-0e671e75f6ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2155369742 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_kmac_err_chk.2155369742
Directory /workspace/6.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/6.rom_ctrl_max_throughput_chk.3580543645
Short name T318
Test name
Test status
Simulation time 1947077788 ps
CPU time 8.93 seconds
Started Feb 04 12:47:23 PM PST 24
Finished Feb 04 12:47:35 PM PST 24
Peak memory 210408 kb
Host smart-7b5c2d69-06af-4256-946e-cf6947c0f18a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3580543645 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_max_throughput_chk.3580543645
Directory /workspace/6.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/6.rom_ctrl_smoke.4140728652
Short name T203
Test name
Test status
Simulation time 3023302599 ps
CPU time 31.5 seconds
Started Feb 04 12:47:11 PM PST 24
Finished Feb 04 12:47:44 PM PST 24
Peak memory 212004 kb
Host smart-fa9283cd-f1a4-4f1b-a94e-0fa02dac2959
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4140728652 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_smoke.4140728652
Directory /workspace/6.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/6.rom_ctrl_stress_all.4066795912
Short name T164
Test name
Test status
Simulation time 42114702531 ps
CPU time 104.78 seconds
Started Feb 04 12:47:09 PM PST 24
Finished Feb 04 12:48:57 PM PST 24
Peak memory 216460 kb
Host smart-c31dc7a0-3341-48c3-ad7a-4186a298d045
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4066795912 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 6.rom_ctrl_stress_all.4066795912
Directory /workspace/6.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/6.rom_ctrl_stress_all_with_rand_reset.1165169837
Short name T397
Test name
Test status
Simulation time 27567877786 ps
CPU time 2046.46 seconds
Started Feb 04 12:47:30 PM PST 24
Finished Feb 04 01:21:41 PM PST 24
Peak memory 227064 kb
Host smart-6b2ec03e-8dd3-41cc-8d5d-577a6d9cc737
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1165169837 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_stress_all_with_rand_reset.1165169837
Directory /workspace/6.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.rom_ctrl_alert_test.1055574200
Short name T161
Test name
Test status
Simulation time 1553029756 ps
CPU time 13.79 seconds
Started Feb 04 12:47:26 PM PST 24
Finished Feb 04 12:47:42 PM PST 24
Peak memory 210404 kb
Host smart-6c522f48-5503-468c-a1b8-e207b5f521c4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1055574200 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_alert_test.1055574200
Directory /workspace/7.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/7.rom_ctrl_corrupt_sig_fatal_chk.495555567
Short name T255
Test name
Test status
Simulation time 7995229517 ps
CPU time 163.9 seconds
Started Feb 04 12:47:22 PM PST 24
Finished Feb 04 12:50:10 PM PST 24
Peak memory 236784 kb
Host smart-309c317b-bb2d-443e-99de-f62d955b3cd5
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=495555567 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_co
rrupt_sig_fatal_chk.495555567
Directory /workspace/7.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/7.rom_ctrl_kmac_err_chk.2622678335
Short name T355
Test name
Test status
Simulation time 1189480260 ps
CPU time 9.61 seconds
Started Feb 04 12:47:23 PM PST 24
Finished Feb 04 12:47:36 PM PST 24
Peak memory 211116 kb
Host smart-53c1c667-f607-4e43-9f58-59c52bb9a6a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2622678335 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_kmac_err_chk.2622678335
Directory /workspace/7.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/7.rom_ctrl_max_throughput_chk.1334366046
Short name T108
Test name
Test status
Simulation time 8130444991 ps
CPU time 13.72 seconds
Started Feb 04 12:47:25 PM PST 24
Finished Feb 04 12:47:41 PM PST 24
Peak memory 210504 kb
Host smart-6cd8f4bb-b1dd-4533-922c-bf58c44108de
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1334366046 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_max_throughput_chk.1334366046
Directory /workspace/7.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/7.rom_ctrl_smoke.3258161756
Short name T389
Test name
Test status
Simulation time 6843072953 ps
CPU time 22.19 seconds
Started Feb 04 12:47:30 PM PST 24
Finished Feb 04 12:47:57 PM PST 24
Peak memory 212676 kb
Host smart-894596dc-4056-4d78-ad9b-3156af1b6eb4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3258161756 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_smoke.3258161756
Directory /workspace/7.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/7.rom_ctrl_stress_all.1976353768
Short name T186
Test name
Test status
Simulation time 4320341922 ps
CPU time 19.96 seconds
Started Feb 04 12:47:30 PM PST 24
Finished Feb 04 12:47:55 PM PST 24
Peak memory 213612 kb
Host smart-152c7037-7250-4bf8-bad1-dc677ef05f35
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1976353768 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 7.rom_ctrl_stress_all.1976353768
Directory /workspace/7.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/7.rom_ctrl_stress_all_with_rand_reset.1799995621
Short name T340
Test name
Test status
Simulation time 13037903866 ps
CPU time 529.09 seconds
Started Feb 04 12:47:30 PM PST 24
Finished Feb 04 12:56:24 PM PST 24
Peak memory 230052 kb
Host smart-a1d0770e-b49f-4674-972b-c07ef3b671f2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1799995621 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_stress_all_with_rand_reset.1799995621
Directory /workspace/7.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.rom_ctrl_alert_test.1357492624
Short name T405
Test name
Test status
Simulation time 1176491379 ps
CPU time 11.33 seconds
Started Feb 04 12:47:25 PM PST 24
Finished Feb 04 12:47:38 PM PST 24
Peak memory 210396 kb
Host smart-b4b68493-4d01-423f-944f-75182f26748a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1357492624 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_alert_test.1357492624
Directory /workspace/8.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/8.rom_ctrl_corrupt_sig_fatal_chk.2900800241
Short name T217
Test name
Test status
Simulation time 45800066933 ps
CPU time 399.08 seconds
Started Feb 04 12:47:31 PM PST 24
Finished Feb 04 12:54:14 PM PST 24
Peak memory 234076 kb
Host smart-7dc59c5b-73b1-461a-bab7-ef099b00a097
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2900800241 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_c
orrupt_sig_fatal_chk.2900800241
Directory /workspace/8.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/8.rom_ctrl_kmac_err_chk.528552077
Short name T331
Test name
Test status
Simulation time 5301284670 ps
CPU time 25.33 seconds
Started Feb 04 12:47:24 PM PST 24
Finished Feb 04 12:47:52 PM PST 24
Peak memory 210556 kb
Host smart-9611027e-b54f-47a4-b600-e452c43a5c08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=528552077 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_kmac_err_chk.528552077
Directory /workspace/8.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/8.rom_ctrl_max_throughput_chk.2336954222
Short name T191
Test name
Test status
Simulation time 641907575 ps
CPU time 9.18 seconds
Started Feb 04 12:47:31 PM PST 24
Finished Feb 04 12:47:44 PM PST 24
Peak memory 210448 kb
Host smart-e6120f2b-a136-4ee9-9ff1-48ed63b98882
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2336954222 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_max_throughput_chk.2336954222
Directory /workspace/8.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/8.rom_ctrl_smoke.2863338587
Short name T233
Test name
Test status
Simulation time 1351943543 ps
CPU time 16.33 seconds
Started Feb 04 12:47:25 PM PST 24
Finished Feb 04 12:47:43 PM PST 24
Peak memory 211972 kb
Host smart-3317fc23-6265-4651-b1d4-4fce902e3005
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2863338587 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_smoke.2863338587
Directory /workspace/8.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/8.rom_ctrl_stress_all.4054266926
Short name T2
Test name
Test status
Simulation time 23511733164 ps
CPU time 37.24 seconds
Started Feb 04 12:47:20 PM PST 24
Finished Feb 04 12:48:03 PM PST 24
Peak memory 213092 kb
Host smart-4f412b57-4c4e-4834-83b7-13651999fe4e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4054266926 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 8.rom_ctrl_stress_all.4054266926
Directory /workspace/8.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/9.rom_ctrl_alert_test.661154850
Short name T421
Test name
Test status
Simulation time 128808857 ps
CPU time 5.05 seconds
Started Feb 04 12:47:31 PM PST 24
Finished Feb 04 12:47:40 PM PST 24
Peak memory 210372 kb
Host smart-4ba539ee-eb2b-4862-8a4c-ca49e5406eb8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=661154850 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_alert_test.661154850
Directory /workspace/9.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/9.rom_ctrl_corrupt_sig_fatal_chk.3538870642
Short name T326
Test name
Test status
Simulation time 7810316594 ps
CPU time 79.14 seconds
Started Feb 04 12:47:22 PM PST 24
Finished Feb 04 12:48:45 PM PST 24
Peak memory 227424 kb
Host smart-20fa816c-a1a9-4078-bf27-1b6c59e28e58
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3538870642 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_c
orrupt_sig_fatal_chk.3538870642
Directory /workspace/9.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/9.rom_ctrl_kmac_err_chk.1083496823
Short name T361
Test name
Test status
Simulation time 1896129320 ps
CPU time 22.23 seconds
Started Feb 04 12:47:29 PM PST 24
Finished Feb 04 12:47:56 PM PST 24
Peak memory 210744 kb
Host smart-8467425c-cde4-4855-81ca-b0e59088b3fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1083496823 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_kmac_err_chk.1083496823
Directory /workspace/9.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/9.rom_ctrl_max_throughput_chk.3219501795
Short name T169
Test name
Test status
Simulation time 6461042754 ps
CPU time 15.15 seconds
Started Feb 04 12:47:24 PM PST 24
Finished Feb 04 12:47:41 PM PST 24
Peak memory 210424 kb
Host smart-80ddd94c-6f6c-4459-bec0-6f53324183e8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3219501795 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_max_throughput_chk.3219501795
Directory /workspace/9.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/9.rom_ctrl_smoke.1820157678
Short name T376
Test name
Test status
Simulation time 4434778613 ps
CPU time 34.55 seconds
Started Feb 04 12:47:24 PM PST 24
Finished Feb 04 12:48:01 PM PST 24
Peak memory 211880 kb
Host smart-00fd875d-11de-48a8-a368-69fe231c8edb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1820157678 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_smoke.1820157678
Directory /workspace/9.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/9.rom_ctrl_stress_all.647714870
Short name T4
Test name
Test status
Simulation time 16600921212 ps
CPU time 62.81 seconds
Started Feb 04 12:47:30 PM PST 24
Finished Feb 04 12:48:38 PM PST 24
Peak memory 215988 kb
Host smart-af1af84b-9c0e-44f5-996c-ae0187414ec8
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=647714870 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 9.rom_ctrl_stress_all.647714870
Directory /workspace/9.rom_ctrl_stress_all/latest
0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%