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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
97.41 97.04 92.65 97.88 100.00 98.37 98.04 97.91


Total test records in report: 474
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T278 /workspace/coverage/default/41.rom_ctrl_stress_all.3712106388 Feb 07 01:04:01 PM PST 24 Feb 07 01:04:35 PM PST 24 3568731138 ps
T279 /workspace/coverage/default/6.rom_ctrl_max_throughput_chk.1258043623 Feb 07 01:01:41 PM PST 24 Feb 07 01:01:56 PM PST 24 1483504212 ps
T280 /workspace/coverage/default/27.rom_ctrl_smoke.3683618998 Feb 07 01:03:16 PM PST 24 Feb 07 01:03:31 PM PST 24 1061080637 ps
T281 /workspace/coverage/default/36.rom_ctrl_max_throughput_chk.2093767080 Feb 07 01:03:32 PM PST 24 Feb 07 01:03:38 PM PST 24 403691947 ps
T282 /workspace/coverage/default/31.rom_ctrl_stress_all_with_rand_reset.1098635110 Feb 07 01:03:22 PM PST 24 Feb 07 01:27:55 PM PST 24 70351880948 ps
T283 /workspace/coverage/default/46.rom_ctrl_stress_all.2670614100 Feb 07 01:04:13 PM PST 24 Feb 07 01:04:39 PM PST 24 9343487550 ps
T284 /workspace/coverage/default/18.rom_ctrl_kmac_err_chk.808792674 Feb 07 01:02:36 PM PST 24 Feb 07 01:02:52 PM PST 24 3745757097 ps
T285 /workspace/coverage/default/29.rom_ctrl_stress_all.3988446027 Feb 07 01:03:10 PM PST 24 Feb 07 01:04:12 PM PST 24 54512405303 ps
T286 /workspace/coverage/default/47.rom_ctrl_smoke.2316332340 Feb 07 01:04:22 PM PST 24 Feb 07 01:04:52 PM PST 24 5124332405 ps
T287 /workspace/coverage/default/49.rom_ctrl_kmac_err_chk.1593833585 Feb 07 01:04:27 PM PST 24 Feb 07 01:04:55 PM PST 24 7350402362 ps
T288 /workspace/coverage/default/20.rom_ctrl_stress_all.910654664 Feb 07 01:02:49 PM PST 24 Feb 07 01:03:04 PM PST 24 2342974347 ps
T289 /workspace/coverage/default/12.rom_ctrl_max_throughput_chk.1866738499 Feb 07 01:02:06 PM PST 24 Feb 07 01:02:20 PM PST 24 11922156741 ps
T290 /workspace/coverage/default/3.rom_ctrl_alert_test.3666240346 Feb 07 01:01:40 PM PST 24 Feb 07 01:01:58 PM PST 24 4273294378 ps
T291 /workspace/coverage/default/46.rom_ctrl_smoke.1642223137 Feb 07 01:04:12 PM PST 24 Feb 07 01:04:33 PM PST 24 22247063660 ps
T292 /workspace/coverage/default/19.rom_ctrl_stress_all_with_rand_reset.3586114122 Feb 07 01:02:46 PM PST 24 Feb 07 01:17:50 PM PST 24 15999738286 ps
T293 /workspace/coverage/default/6.rom_ctrl_kmac_err_chk.3053483942 Feb 07 01:01:37 PM PST 24 Feb 07 01:02:05 PM PST 24 2898773474 ps
T294 /workspace/coverage/default/0.rom_ctrl_stress_all.2945521600 Feb 07 01:01:01 PM PST 24 Feb 07 01:01:58 PM PST 24 23377124612 ps
T295 /workspace/coverage/default/33.rom_ctrl_smoke.3345553890 Feb 07 01:03:26 PM PST 24 Feb 07 01:03:37 PM PST 24 369611338 ps
T296 /workspace/coverage/default/36.rom_ctrl_stress_all_with_rand_reset.1806002127 Feb 07 01:03:35 PM PST 24 Feb 07 01:48:57 PM PST 24 189973782628 ps
T297 /workspace/coverage/default/22.rom_ctrl_smoke.3532467956 Feb 07 01:02:47 PM PST 24 Feb 07 01:03:09 PM PST 24 1552255380 ps
T298 /workspace/coverage/default/27.rom_ctrl_stress_all.2927615472 Feb 07 01:03:16 PM PST 24 Feb 07 01:04:15 PM PST 24 5457406046 ps
T299 /workspace/coverage/default/14.rom_ctrl_alert_test.509140827 Feb 07 01:02:25 PM PST 24 Feb 07 01:02:37 PM PST 24 3673262650 ps
T300 /workspace/coverage/default/0.rom_ctrl_corrupt_sig_fatal_chk.3488003964 Feb 07 01:01:04 PM PST 24 Feb 07 01:02:40 PM PST 24 6118131147 ps
T301 /workspace/coverage/default/39.rom_ctrl_smoke.1281948491 Feb 07 01:03:51 PM PST 24 Feb 07 01:04:02 PM PST 24 231164090 ps
T302 /workspace/coverage/default/18.rom_ctrl_stress_all_with_rand_reset.2322383520 Feb 07 01:02:48 PM PST 24 Feb 07 01:18:05 PM PST 24 47210103790 ps
T303 /workspace/coverage/default/7.rom_ctrl_corrupt_sig_fatal_chk.2282917929 Feb 07 01:01:52 PM PST 24 Feb 07 01:03:47 PM PST 24 7550610021 ps
T304 /workspace/coverage/default/44.rom_ctrl_stress_all.1646598620 Feb 07 01:04:13 PM PST 24 Feb 07 01:04:44 PM PST 24 12415891579 ps
T305 /workspace/coverage/default/16.rom_ctrl_corrupt_sig_fatal_chk.1578981323 Feb 07 01:02:20 PM PST 24 Feb 07 01:06:07 PM PST 24 56775230477 ps
T306 /workspace/coverage/default/33.rom_ctrl_corrupt_sig_fatal_chk.3008084005 Feb 07 01:03:23 PM PST 24 Feb 07 01:07:48 PM PST 24 143071789350 ps
T307 /workspace/coverage/default/46.rom_ctrl_max_throughput_chk.3606162630 Feb 07 01:04:16 PM PST 24 Feb 07 01:04:22 PM PST 24 161589418 ps
T308 /workspace/coverage/default/5.rom_ctrl_smoke.2705924285 Feb 07 01:01:40 PM PST 24 Feb 07 01:02:02 PM PST 24 1502322850 ps
T309 /workspace/coverage/default/35.rom_ctrl_corrupt_sig_fatal_chk.3127866043 Feb 07 01:03:42 PM PST 24 Feb 07 01:07:42 PM PST 24 17986372112 ps
T310 /workspace/coverage/default/13.rom_ctrl_corrupt_sig_fatal_chk.3716162838 Feb 07 01:02:24 PM PST 24 Feb 07 01:09:04 PM PST 24 43261394149 ps
T311 /workspace/coverage/default/2.rom_ctrl_alert_test.476356753 Feb 07 01:01:24 PM PST 24 Feb 07 01:01:39 PM PST 24 3346262693 ps
T312 /workspace/coverage/default/25.rom_ctrl_kmac_err_chk.1470915979 Feb 07 01:03:06 PM PST 24 Feb 07 01:03:36 PM PST 24 3181481493 ps
T313 /workspace/coverage/default/43.rom_ctrl_max_throughput_chk.1905985257 Feb 07 01:04:02 PM PST 24 Feb 07 01:04:20 PM PST 24 2073621324 ps
T314 /workspace/coverage/default/12.rom_ctrl_corrupt_sig_fatal_chk.468887587 Feb 07 01:02:05 PM PST 24 Feb 07 01:05:45 PM PST 24 17112531478 ps
T315 /workspace/coverage/default/2.rom_ctrl_smoke.1710769267 Feb 07 01:01:28 PM PST 24 Feb 07 01:01:44 PM PST 24 1211442354 ps
T316 /workspace/coverage/default/7.rom_ctrl_kmac_err_chk.46410403 Feb 07 01:01:53 PM PST 24 Feb 07 01:02:03 PM PST 24 476415835 ps
T317 /workspace/coverage/default/35.rom_ctrl_max_throughput_chk.22749753 Feb 07 01:03:32 PM PST 24 Feb 07 01:03:46 PM PST 24 6314258534 ps
T318 /workspace/coverage/default/26.rom_ctrl_smoke.2526794041 Feb 07 01:03:09 PM PST 24 Feb 07 01:03:20 PM PST 24 370769233 ps
T319 /workspace/coverage/default/22.rom_ctrl_stress_all.3815558264 Feb 07 01:02:47 PM PST 24 Feb 07 01:03:34 PM PST 24 15464313052 ps
T320 /workspace/coverage/default/40.rom_ctrl_max_throughput_chk.2955741743 Feb 07 01:04:04 PM PST 24 Feb 07 01:04:17 PM PST 24 4318581714 ps
T321 /workspace/coverage/default/29.rom_ctrl_kmac_err_chk.1931464174 Feb 07 01:03:13 PM PST 24 Feb 07 01:03:38 PM PST 24 2345363266 ps
T322 /workspace/coverage/default/2.rom_ctrl_max_throughput_chk.3871987711 Feb 07 01:01:26 PM PST 24 Feb 07 01:01:39 PM PST 24 2382428949 ps
T323 /workspace/coverage/default/43.rom_ctrl_smoke.3254556430 Feb 07 01:04:03 PM PST 24 Feb 07 01:04:28 PM PST 24 2707120543 ps
T324 /workspace/coverage/default/22.rom_ctrl_max_throughput_chk.1441772749 Feb 07 01:02:45 PM PST 24 Feb 07 01:03:06 PM PST 24 8464755318 ps
T325 /workspace/coverage/default/39.rom_ctrl_max_throughput_chk.625338290 Feb 07 01:03:51 PM PST 24 Feb 07 01:04:07 PM PST 24 4331752336 ps
T326 /workspace/coverage/default/34.rom_ctrl_alert_test.4075811092 Feb 07 01:03:34 PM PST 24 Feb 07 01:03:39 PM PST 24 89881636 ps
T327 /workspace/coverage/default/17.rom_ctrl_smoke.2153431012 Feb 07 01:02:39 PM PST 24 Feb 07 01:02:51 PM PST 24 711083925 ps
T328 /workspace/coverage/default/28.rom_ctrl_alert_test.2368373961 Feb 07 01:03:24 PM PST 24 Feb 07 01:03:37 PM PST 24 1388994047 ps
T13 /workspace/coverage/default/49.rom_ctrl_stress_all_with_rand_reset.2973918733 Feb 07 01:04:28 PM PST 24 Feb 07 01:12:29 PM PST 24 55582712282 ps
T329 /workspace/coverage/default/9.rom_ctrl_smoke.1300132055 Feb 07 01:01:54 PM PST 24 Feb 07 01:02:05 PM PST 24 1346524566 ps
T330 /workspace/coverage/default/42.rom_ctrl_kmac_err_chk.3768524491 Feb 07 01:04:03 PM PST 24 Feb 07 01:04:35 PM PST 24 3706107965 ps
T331 /workspace/coverage/default/9.rom_ctrl_max_throughput_chk.2889633047 Feb 07 01:01:52 PM PST 24 Feb 07 01:02:09 PM PST 24 23656341016 ps
T332 /workspace/coverage/default/22.rom_ctrl_kmac_err_chk.4221063347 Feb 07 01:02:47 PM PST 24 Feb 07 01:03:20 PM PST 24 4036225938 ps
T333 /workspace/coverage/default/48.rom_ctrl_corrupt_sig_fatal_chk.111523268 Feb 07 01:04:19 PM PST 24 Feb 07 01:05:46 PM PST 24 3457681232 ps
T334 /workspace/coverage/default/15.rom_ctrl_corrupt_sig_fatal_chk.45537549 Feb 07 01:02:28 PM PST 24 Feb 07 01:05:37 PM PST 24 48917416299 ps
T335 /workspace/coverage/default/47.rom_ctrl_corrupt_sig_fatal_chk.3865681596 Feb 07 01:04:12 PM PST 24 Feb 07 01:08:46 PM PST 24 29764798313 ps
T336 /workspace/coverage/default/34.rom_ctrl_max_throughput_chk.3274940859 Feb 07 01:03:20 PM PST 24 Feb 07 01:03:35 PM PST 24 1565713419 ps
T337 /workspace/coverage/default/29.rom_ctrl_smoke.2137108101 Feb 07 01:03:13 PM PST 24 Feb 07 01:03:39 PM PST 24 2652825345 ps
T338 /workspace/coverage/default/9.rom_ctrl_corrupt_sig_fatal_chk.3540525890 Feb 07 01:01:53 PM PST 24 Feb 07 01:03:16 PM PST 24 9708946269 ps
T339 /workspace/coverage/default/8.rom_ctrl_stress_all.4035465931 Feb 07 01:01:52 PM PST 24 Feb 07 01:02:09 PM PST 24 297607345 ps
T340 /workspace/coverage/default/11.rom_ctrl_alert_test.3052170106 Feb 07 01:02:02 PM PST 24 Feb 07 01:02:17 PM PST 24 6390075256 ps
T341 /workspace/coverage/default/8.rom_ctrl_corrupt_sig_fatal_chk.4145479775 Feb 07 01:01:54 PM PST 24 Feb 07 01:10:25 PM PST 24 55633673702 ps
T342 /workspace/coverage/default/38.rom_ctrl_stress_all.1866396197 Feb 07 01:03:50 PM PST 24 Feb 07 01:04:06 PM PST 24 562326369 ps
T343 /workspace/coverage/default/45.rom_ctrl_alert_test.2092434695 Feb 07 01:04:13 PM PST 24 Feb 07 01:04:18 PM PST 24 88183403 ps
T344 /workspace/coverage/default/42.rom_ctrl_max_throughput_chk.1512143600 Feb 07 01:04:05 PM PST 24 Feb 07 01:04:17 PM PST 24 6496180188 ps
T345 /workspace/coverage/default/23.rom_ctrl_kmac_err_chk.3069687240 Feb 07 01:03:08 PM PST 24 Feb 07 01:03:28 PM PST 24 1713495303 ps
T346 /workspace/coverage/default/44.rom_ctrl_max_throughput_chk.874002908 Feb 07 01:04:12 PM PST 24 Feb 07 01:04:27 PM PST 24 1590083257 ps
T347 /workspace/coverage/default/25.rom_ctrl_alert_test.212639383 Feb 07 01:03:10 PM PST 24 Feb 07 01:03:22 PM PST 24 6570362994 ps
T348 /workspace/coverage/default/49.rom_ctrl_corrupt_sig_fatal_chk.392087289 Feb 07 01:04:25 PM PST 24 Feb 07 01:06:53 PM PST 24 8890650927 ps
T349 /workspace/coverage/default/7.rom_ctrl_stress_all.986717989 Feb 07 01:01:51 PM PST 24 Feb 07 01:02:01 PM PST 24 486186020 ps
T350 /workspace/coverage/default/40.rom_ctrl_alert_test.2941644904 Feb 07 01:04:05 PM PST 24 Feb 07 01:04:20 PM PST 24 25102052319 ps
T351 /workspace/coverage/default/24.rom_ctrl_corrupt_sig_fatal_chk.1870622341 Feb 07 01:03:05 PM PST 24 Feb 07 01:06:56 PM PST 24 14418245574 ps
T352 /workspace/coverage/default/12.rom_ctrl_smoke.1697540882 Feb 07 01:02:04 PM PST 24 Feb 07 01:02:33 PM PST 24 2939695633 ps
T353 /workspace/coverage/default/1.rom_ctrl_stress_all_with_rand_reset.1769971125 Feb 07 01:01:18 PM PST 24 Feb 07 01:22:36 PM PST 24 140487656487 ps
T354 /workspace/coverage/default/20.rom_ctrl_alert_test.326373357 Feb 07 01:02:49 PM PST 24 Feb 07 01:03:03 PM PST 24 5094374092 ps
T355 /workspace/coverage/default/14.rom_ctrl_kmac_err_chk.511813034 Feb 07 01:02:24 PM PST 24 Feb 07 01:02:52 PM PST 24 7534889144 ps
T356 /workspace/coverage/default/3.rom_ctrl_stress_all.2319017137 Feb 07 01:01:26 PM PST 24 Feb 07 01:02:13 PM PST 24 21166540496 ps
T357 /workspace/coverage/default/28.rom_ctrl_smoke.1041196889 Feb 07 01:03:15 PM PST 24 Feb 07 01:03:50 PM PST 24 13416798464 ps
T358 /workspace/coverage/default/10.rom_ctrl_max_throughput_chk.2867108343 Feb 07 01:02:04 PM PST 24 Feb 07 01:02:20 PM PST 24 13110464975 ps
T359 /workspace/coverage/default/43.rom_ctrl_alert_test.2818549166 Feb 07 01:04:12 PM PST 24 Feb 07 01:04:23 PM PST 24 859954672 ps
T360 /workspace/coverage/default/32.rom_ctrl_alert_test.247502578 Feb 07 01:03:24 PM PST 24 Feb 07 01:03:35 PM PST 24 952945757 ps
T361 /workspace/coverage/default/43.rom_ctrl_kmac_err_chk.4240416056 Feb 07 01:04:05 PM PST 24 Feb 07 01:04:35 PM PST 24 19935902027 ps
T362 /workspace/coverage/default/37.rom_ctrl_corrupt_sig_fatal_chk.3818545826 Feb 07 01:03:50 PM PST 24 Feb 07 01:07:25 PM PST 24 13301974496 ps
T363 /workspace/coverage/default/41.rom_ctrl_kmac_err_chk.3903399164 Feb 07 01:04:03 PM PST 24 Feb 07 01:04:27 PM PST 24 2275415980 ps
T364 /workspace/coverage/default/48.rom_ctrl_stress_all_with_rand_reset.1788189432 Feb 07 01:04:14 PM PST 24 Feb 07 02:59:59 PM PST 24 101025067405 ps
T365 /workspace/coverage/default/20.rom_ctrl_corrupt_sig_fatal_chk.1460924094 Feb 07 01:02:47 PM PST 24 Feb 07 01:04:33 PM PST 24 3504392216 ps
T366 /workspace/coverage/default/3.rom_ctrl_corrupt_sig_fatal_chk.3684097360 Feb 07 01:01:22 PM PST 24 Feb 07 01:04:57 PM PST 24 54034188699 ps
T367 /workspace/coverage/default/1.rom_ctrl_corrupt_sig_fatal_chk.1804536819 Feb 07 01:01:15 PM PST 24 Feb 07 01:03:19 PM PST 24 21571710197 ps
T368 /workspace/coverage/default/49.rom_ctrl_smoke.3807371174 Feb 07 01:04:32 PM PST 24 Feb 07 01:04:53 PM PST 24 4025745905 ps
T369 /workspace/coverage/default/35.rom_ctrl_smoke.460639955 Feb 07 01:03:33 PM PST 24 Feb 07 01:04:04 PM PST 24 9226577889 ps
T370 /workspace/coverage/default/17.rom_ctrl_kmac_err_chk.2432694828 Feb 07 01:02:34 PM PST 24 Feb 07 01:03:08 PM PST 24 4191171825 ps
T371 /workspace/coverage/default/14.rom_ctrl_stress_all_with_rand_reset.432369072 Feb 07 01:02:20 PM PST 24 Feb 07 03:41:43 PM PST 24 158748681553 ps
T372 /workspace/coverage/default/26.rom_ctrl_corrupt_sig_fatal_chk.36814990 Feb 07 01:03:04 PM PST 24 Feb 07 01:07:54 PM PST 24 43984832095 ps
T373 /workspace/coverage/default/14.rom_ctrl_max_throughput_chk.1314875957 Feb 07 01:02:24 PM PST 24 Feb 07 01:02:34 PM PST 24 2083152690 ps
T374 /workspace/coverage/default/18.rom_ctrl_smoke.1080384401 Feb 07 01:02:37 PM PST 24 Feb 07 01:03:09 PM PST 24 3325414268 ps
T375 /workspace/coverage/default/8.rom_ctrl_smoke.3942856050 Feb 07 01:01:53 PM PST 24 Feb 07 01:02:23 PM PST 24 3855128685 ps
T376 /workspace/coverage/default/21.rom_ctrl_smoke.4182712304 Feb 07 01:02:48 PM PST 24 Feb 07 01:03:10 PM PST 24 7506646251 ps
T377 /workspace/coverage/default/15.rom_ctrl_max_throughput_chk.2958410565 Feb 07 01:02:24 PM PST 24 Feb 07 01:02:38 PM PST 24 1278116057 ps
T378 /workspace/coverage/default/29.rom_ctrl_max_throughput_chk.2379047472 Feb 07 01:03:12 PM PST 24 Feb 07 01:03:26 PM PST 24 2742708794 ps
T379 /workspace/coverage/default/19.rom_ctrl_corrupt_sig_fatal_chk.721737826 Feb 07 01:02:45 PM PST 24 Feb 07 01:05:59 PM PST 24 17650743526 ps
T380 /workspace/coverage/default/33.rom_ctrl_kmac_err_chk.1367366784 Feb 07 01:03:25 PM PST 24 Feb 07 01:03:48 PM PST 24 6058753453 ps
T381 /workspace/coverage/default/24.rom_ctrl_smoke.3717098404 Feb 07 01:03:06 PM PST 24 Feb 07 01:03:18 PM PST 24 2964000809 ps
T382 /workspace/coverage/default/24.rom_ctrl_stress_all_with_rand_reset.2895260719 Feb 07 01:03:10 PM PST 24 Feb 07 01:30:54 PM PST 24 150762858826 ps
T383 /workspace/coverage/default/36.rom_ctrl_stress_all.1259102548 Feb 07 01:03:34 PM PST 24 Feb 07 01:03:46 PM PST 24 215351140 ps
T384 /workspace/coverage/default/23.rom_ctrl_corrupt_sig_fatal_chk.4114890518 Feb 07 01:03:06 PM PST 24 Feb 07 01:06:17 PM PST 24 41656268222 ps
T385 /workspace/coverage/default/35.rom_ctrl_alert_test.2066168668 Feb 07 01:03:31 PM PST 24 Feb 07 01:03:47 PM PST 24 3577497278 ps
T386 /workspace/coverage/default/14.rom_ctrl_stress_all.2062052711 Feb 07 01:02:24 PM PST 24 Feb 07 01:04:15 PM PST 24 65804249695 ps
T387 /workspace/coverage/default/47.rom_ctrl_kmac_err_chk.1936801382 Feb 07 01:04:13 PM PST 24 Feb 07 01:04:33 PM PST 24 1960344855 ps
T388 /workspace/coverage/default/34.rom_ctrl_smoke.2903945950 Feb 07 01:03:21 PM PST 24 Feb 07 01:03:50 PM PST 24 3631365608 ps
T389 /workspace/coverage/default/40.rom_ctrl_kmac_err_chk.661265166 Feb 07 01:04:02 PM PST 24 Feb 07 01:04:12 PM PST 24 1385125403 ps
T390 /workspace/coverage/default/26.rom_ctrl_stress_all_with_rand_reset.713576848 Feb 07 01:03:04 PM PST 24 Feb 07 01:29:11 PM PST 24 40494882688 ps
T92 /workspace/coverage/default/41.rom_ctrl_max_throughput_chk.2441223857 Feb 07 01:04:02 PM PST 24 Feb 07 01:04:09 PM PST 24 100779210 ps
T93 /workspace/coverage/default/49.rom_ctrl_stress_all.732604993 Feb 07 01:04:24 PM PST 24 Feb 07 01:05:17 PM PST 24 7503163461 ps
T94 /workspace/coverage/default/15.rom_ctrl_alert_test.2428368447 Feb 07 01:02:21 PM PST 24 Feb 07 01:02:28 PM PST 24 261185061 ps
T95 /workspace/coverage/default/10.rom_ctrl_stress_all.3944533310 Feb 07 01:02:03 PM PST 24 Feb 07 01:02:21 PM PST 24 3220064988 ps
T96 /workspace/coverage/default/20.rom_ctrl_max_throughput_chk.3388496959 Feb 07 01:02:46 PM PST 24 Feb 07 01:02:55 PM PST 24 101158764 ps
T97 /workspace/coverage/default/7.rom_ctrl_smoke.1216060409 Feb 07 01:01:52 PM PST 24 Feb 07 01:02:24 PM PST 24 12950513295 ps
T98 /workspace/coverage/default/30.rom_ctrl_kmac_err_chk.1977001261 Feb 07 01:03:25 PM PST 24 Feb 07 01:03:51 PM PST 24 2940208476 ps
T99 /workspace/coverage/default/21.rom_ctrl_kmac_err_chk.1586270963 Feb 07 01:02:48 PM PST 24 Feb 07 01:03:08 PM PST 24 1273686193 ps
T100 /workspace/coverage/default/27.rom_ctrl_kmac_err_chk.243971913 Feb 07 01:03:10 PM PST 24 Feb 07 01:03:45 PM PST 24 16028195160 ps
T101 /workspace/coverage/default/39.rom_ctrl_stress_all.3270456692 Feb 07 01:03:50 PM PST 24 Feb 07 01:04:17 PM PST 24 2051369041 ps
T391 /workspace/coverage/default/49.rom_ctrl_alert_test.1879988536 Feb 07 01:04:27 PM PST 24 Feb 07 01:04:32 PM PST 24 85415687 ps
T392 /workspace/coverage/default/31.rom_ctrl_alert_test.1527131532 Feb 07 01:03:22 PM PST 24 Feb 07 01:03:36 PM PST 24 1564586130 ps
T393 /workspace/coverage/default/5.rom_ctrl_stress_all_with_rand_reset.2239997437 Feb 07 01:01:39 PM PST 24 Feb 07 01:24:09 PM PST 24 25429958700 ps
T394 /workspace/coverage/default/19.rom_ctrl_alert_test.3807430517 Feb 07 01:02:45 PM PST 24 Feb 07 01:02:53 PM PST 24 168317608 ps
T395 /workspace/coverage/default/47.rom_ctrl_stress_all.4142131477 Feb 07 01:04:12 PM PST 24 Feb 07 01:05:46 PM PST 24 7595776052 ps
T396 /workspace/coverage/default/42.rom_ctrl_alert_test.1758513495 Feb 07 01:04:06 PM PST 24 Feb 07 01:04:10 PM PST 24 437494607 ps
T397 /workspace/coverage/default/0.rom_ctrl_stress_all_with_rand_reset.3881653156 Feb 07 01:01:02 PM PST 24 Feb 07 01:24:18 PM PST 24 37862474900 ps
T398 /workspace/coverage/default/36.rom_ctrl_alert_test.1981161208 Feb 07 01:03:36 PM PST 24 Feb 07 01:03:40 PM PST 24 638505270 ps
T399 /workspace/coverage/default/31.rom_ctrl_smoke.2590913633 Feb 07 01:03:21 PM PST 24 Feb 07 01:03:54 PM PST 24 5777577600 ps
T400 /workspace/coverage/default/20.rom_ctrl_kmac_err_chk.3930233876 Feb 07 01:02:49 PM PST 24 Feb 07 01:03:17 PM PST 24 2996776214 ps
T401 /workspace/coverage/default/6.rom_ctrl_corrupt_sig_fatal_chk.2410764655 Feb 07 01:01:40 PM PST 24 Feb 07 01:05:47 PM PST 24 13196531094 ps
T402 /workspace/coverage/default/12.rom_ctrl_stress_all.3668917043 Feb 07 01:02:05 PM PST 24 Feb 07 01:02:46 PM PST 24 2870948850 ps
T403 /workspace/coverage/default/41.rom_ctrl_corrupt_sig_fatal_chk.3468535212 Feb 07 01:04:01 PM PST 24 Feb 07 01:07:50 PM PST 24 38133527123 ps
T404 /workspace/coverage/default/0.rom_ctrl_kmac_err_chk.135805126 Feb 07 01:01:00 PM PST 24 Feb 07 01:01:16 PM PST 24 2983500862 ps
T405 /workspace/coverage/default/8.rom_ctrl_alert_test.796324550 Feb 07 01:01:51 PM PST 24 Feb 07 01:02:02 PM PST 24 1640412358 ps
T406 /workspace/coverage/default/3.rom_ctrl_kmac_err_chk.2820856546 Feb 07 01:01:20 PM PST 24 Feb 07 01:01:49 PM PST 24 21695499232 ps
T407 /workspace/coverage/default/11.rom_ctrl_smoke.1827367959 Feb 07 01:02:04 PM PST 24 Feb 07 01:02:38 PM PST 24 4066987369 ps
T408 /workspace/coverage/default/38.rom_ctrl_max_throughput_chk.4213790650 Feb 07 01:03:49 PM PST 24 Feb 07 01:03:55 PM PST 24 198230656 ps
T409 /workspace/coverage/default/26.rom_ctrl_alert_test.3370017784 Feb 07 01:03:08 PM PST 24 Feb 07 01:03:25 PM PST 24 28506986265 ps
T410 /workspace/coverage/default/29.rom_ctrl_corrupt_sig_fatal_chk.1921052132 Feb 07 01:03:24 PM PST 24 Feb 07 01:10:23 PM PST 24 157026362692 ps
T411 /workspace/coverage/default/9.rom_ctrl_stress_all_with_rand_reset.1985662297 Feb 07 01:01:51 PM PST 24 Feb 07 01:34:57 PM PST 24 74739553344 ps
T412 /workspace/coverage/default/6.rom_ctrl_smoke.2050144696 Feb 07 01:01:39 PM PST 24 Feb 07 01:01:57 PM PST 24 958738134 ps
T413 /workspace/coverage/default/16.rom_ctrl_stress_all.2511230934 Feb 07 01:02:25 PM PST 24 Feb 07 01:02:51 PM PST 24 1047641083 ps
T414 /workspace/coverage/default/15.rom_ctrl_stress_all_with_rand_reset.975136634 Feb 07 01:02:24 PM PST 24 Feb 07 01:50:46 PM PST 24 78278627899 ps
T415 /workspace/coverage/default/45.rom_ctrl_kmac_err_chk.238063746 Feb 07 01:04:14 PM PST 24 Feb 07 01:04:23 PM PST 24 327384208 ps
T416 /workspace/coverage/default/45.rom_ctrl_corrupt_sig_fatal_chk.2462374928 Feb 07 01:04:13 PM PST 24 Feb 07 01:07:13 PM PST 24 37081356703 ps
T417 /workspace/coverage/default/27.rom_ctrl_alert_test.757492146 Feb 07 01:03:14 PM PST 24 Feb 07 01:03:30 PM PST 24 1927758263 ps
T418 /workspace/coverage/default/39.rom_ctrl_kmac_err_chk.1185382273 Feb 07 01:03:50 PM PST 24 Feb 07 01:04:14 PM PST 24 9257629532 ps
T419 /workspace/coverage/default/5.rom_ctrl_alert_test.3581762474 Feb 07 01:01:41 PM PST 24 Feb 07 01:01:50 PM PST 24 2431230691 ps
T420 /workspace/coverage/default/15.rom_ctrl_stress_all.4272776563 Feb 07 01:02:19 PM PST 24 Feb 07 01:02:42 PM PST 24 1646086742 ps
T421 /workspace/coverage/default/4.rom_ctrl_kmac_err_chk.2602763640 Feb 07 01:01:41 PM PST 24 Feb 07 01:02:07 PM PST 24 11748646809 ps
T422 /workspace/coverage/default/48.rom_ctrl_kmac_err_chk.3514267722 Feb 07 01:04:17 PM PST 24 Feb 07 01:04:29 PM PST 24 251092300 ps
T423 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_bit_bash.2405406284 Feb 07 01:41:50 PM PST 24 Feb 07 01:41:54 PM PST 24 85430832 ps
T424 /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_mem_rw_with_rand_reset.189221829 Feb 07 01:42:15 PM PST 24 Feb 07 01:42:28 PM PST 24 5276597834 ps
T425 /workspace/coverage/cover_reg_top/9.rom_ctrl_same_csr_outstanding.1900183835 Feb 07 01:42:00 PM PST 24 Feb 07 01:42:08 PM PST 24 546855506 ps
T426 /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_mem_rw_with_rand_reset.1009347242 Feb 07 01:42:15 PM PST 24 Feb 07 01:42:30 PM PST 24 1881675368 ps
T108 /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_intg_err.1802844031 Feb 07 01:41:59 PM PST 24 Feb 07 01:42:47 PM PST 24 4041021679 ps
T427 /workspace/coverage/cover_reg_top/0.rom_ctrl_same_csr_outstanding.571479582 Feb 07 01:41:51 PM PST 24 Feb 07 01:42:00 PM PST 24 620453574 ps
T428 /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_errors.636335995 Feb 07 01:42:13 PM PST 24 Feb 07 01:42:24 PM PST 24 292458619 ps
T429 /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_partial_access.3006999123 Feb 07 01:41:47 PM PST 24 Feb 07 01:41:55 PM PST 24 428204197 ps
T430 /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_rw.3788982292 Feb 07 01:41:59 PM PST 24 Feb 07 01:42:12 PM PST 24 1464707779 ps
T431 /workspace/coverage/cover_reg_top/16.rom_ctrl_same_csr_outstanding.231155840 Feb 07 01:42:15 PM PST 24 Feb 07 01:42:29 PM PST 24 1482123825 ps
T432 /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_walk.2285391548 Feb 07 01:41:42 PM PST 24 Feb 07 01:41:49 PM PST 24 1682301077 ps
T433 /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_rw.1202539840 Feb 07 01:42:20 PM PST 24 Feb 07 01:42:35 PM PST 24 3471199117 ps
T434 /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_mem_rw_with_rand_reset.4047601717 Feb 07 01:42:02 PM PST 24 Feb 07 01:42:17 PM PST 24 2851874952 ps
T80 /workspace/coverage/cover_reg_top/5.rom_ctrl_passthru_mem_tl_intg_err.3993479573 Feb 07 01:41:46 PM PST 24 Feb 07 01:43:26 PM PST 24 15498344260 ps
T435 /workspace/coverage/cover_reg_top/12.rom_ctrl_same_csr_outstanding.1879472055 Feb 07 01:42:08 PM PST 24 Feb 07 01:42:20 PM PST 24 4906019215 ps
T81 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_rw.1093675930 Feb 07 01:41:45 PM PST 24 Feb 07 01:41:52 PM PST 24 527550272 ps
T436 /workspace/coverage/cover_reg_top/8.rom_ctrl_same_csr_outstanding.125300743 Feb 07 01:42:03 PM PST 24 Feb 07 01:42:20 PM PST 24 1869770928 ps
T437 /workspace/coverage/cover_reg_top/14.rom_ctrl_passthru_mem_tl_intg_err.1498731468 Feb 07 01:42:11 PM PST 24 Feb 07 01:43:04 PM PST 24 1057587231 ps
T88 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_rw.1475434032 Feb 07 01:41:51 PM PST 24 Feb 07 01:42:07 PM PST 24 1970196552 ps
T111 /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_intg_err.2051872218 Feb 07 01:42:07 PM PST 24 Feb 07 01:42:50 PM PST 24 1153850649 ps
T438 /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_rw.2883098100 Feb 07 01:42:07 PM PST 24 Feb 07 01:42:20 PM PST 24 6043935400 ps
T83 /workspace/coverage/cover_reg_top/8.rom_ctrl_passthru_mem_tl_intg_err.2152137860 Feb 07 01:42:00 PM PST 24 Feb 07 01:43:37 PM PST 24 7764296346 ps
T439 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_hw_reset.2242712907 Feb 07 01:41:45 PM PST 24 Feb 07 01:41:53 PM PST 24 172535853 ps
T440 /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_mem_rw_with_rand_reset.270978990 Feb 07 01:42:06 PM PST 24 Feb 07 01:42:16 PM PST 24 829978546 ps
T441 /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_partial_access.1073906884 Feb 07 01:41:45 PM PST 24 Feb 07 01:41:52 PM PST 24 4108643654 ps
T442 /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_rw.3928924282 Feb 07 01:42:16 PM PST 24 Feb 07 01:42:28 PM PST 24 1584037052 ps
T443 /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_errors.401339633 Feb 07 01:42:01 PM PST 24 Feb 07 01:42:09 PM PST 24 86458457 ps
T444 /workspace/coverage/cover_reg_top/17.rom_ctrl_same_csr_outstanding.3981897115 Feb 07 01:42:14 PM PST 24 Feb 07 01:42:28 PM PST 24 1508278994 ps
T445 /workspace/coverage/cover_reg_top/19.rom_ctrl_same_csr_outstanding.4148865458 Feb 07 01:42:16 PM PST 24 Feb 07 01:42:22 PM PST 24 87279282 ps
T446 /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_errors.3354948657 Feb 07 01:41:45 PM PST 24 Feb 07 01:42:02 PM PST 24 1293866550 ps
T84 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_aliasing.397767907 Feb 07 01:41:47 PM PST 24 Feb 07 01:41:54 PM PST 24 493213773 ps
T89 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_hw_reset.1994359432 Feb 07 01:41:45 PM PST 24 Feb 07 01:41:59 PM PST 24 6649445014 ps
T447 /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_mem_rw_with_rand_reset.1320535584 Feb 07 01:42:00 PM PST 24 Feb 07 01:42:10 PM PST 24 3459557920 ps
T85 /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_rw.1178230542 Feb 07 01:42:03 PM PST 24 Feb 07 01:42:12 PM PST 24 1503320116 ps
T448 /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_errors.2643129154 Feb 07 01:42:08 PM PST 24 Feb 07 01:42:27 PM PST 24 7352177615 ps
T82 /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_rw.1563197625 Feb 07 01:42:09 PM PST 24 Feb 07 01:42:25 PM PST 24 1948588430 ps
T449 /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_errors.960360801 Feb 07 01:42:00 PM PST 24 Feb 07 01:42:20 PM PST 24 2426368814 ps
T105 /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_intg_err.1762626188 Feb 07 01:41:44 PM PST 24 Feb 07 01:43:06 PM PST 24 2416063232 ps
T450 /workspace/coverage/cover_reg_top/4.rom_ctrl_passthru_mem_tl_intg_err.3010840158 Feb 07 01:41:46 PM PST 24 Feb 07 01:44:16 PM PST 24 8207528998 ps
T451 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_aliasing.2680955045 Feb 07 01:41:50 PM PST 24 Feb 07 01:41:55 PM PST 24 86586170 ps
T452 /workspace/coverage/cover_reg_top/15.rom_ctrl_same_csr_outstanding.4014040676 Feb 07 01:42:13 PM PST 24 Feb 07 01:42:23 PM PST 24 940975540 ps
T453 /workspace/coverage/cover_reg_top/10.rom_ctrl_passthru_mem_tl_intg_err.2601361871 Feb 07 01:42:07 PM PST 24 Feb 07 01:42:58 PM PST 24 2038099188 ps
T454 /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_rw.2294279590 Feb 07 01:42:19 PM PST 24 Feb 07 01:42:26 PM PST 24 823746177 ps
T455 /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_errors.1019759709 Feb 07 01:42:17 PM PST 24 Feb 07 01:42:27 PM PST 24 449865298 ps
T112 /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_intg_err.765447536 Feb 07 01:42:15 PM PST 24 Feb 07 01:43:27 PM PST 24 245425750 ps
T90 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_aliasing.2588140452 Feb 07 01:41:45 PM PST 24 Feb 07 01:41:55 PM PST 24 2462633912 ps
T456 /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_walk.1875346709 Feb 07 01:41:46 PM PST 24 Feb 07 01:41:51 PM PST 24 161706462 ps
T457 /workspace/coverage/cover_reg_top/0.rom_ctrl_passthru_mem_tl_intg_err.1296113285 Feb 07 01:41:37 PM PST 24 Feb 07 01:42:50 PM PST 24 17047814261 ps
T458 /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_errors.2707211845 Feb 07 01:42:14 PM PST 24 Feb 07 01:42:24 PM PST 24 779557799 ps
T459 /workspace/coverage/cover_reg_top/17.rom_ctrl_passthru_mem_tl_intg_err.500970278 Feb 07 01:42:14 PM PST 24 Feb 07 01:45:18 PM PST 24 39632022034 ps
T460 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_bit_bash.480043457 Feb 07 01:41:47 PM PST 24 Feb 07 01:41:57 PM PST 24 2790367142 ps
T461 /workspace/coverage/cover_reg_top/1.rom_ctrl_same_csr_outstanding.663553209 Feb 07 01:41:42 PM PST 24 Feb 07 01:41:54 PM PST 24 3475919728 ps
T114 /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_intg_err.2996085821 Feb 07 01:41:46 PM PST 24 Feb 07 01:42:27 PM PST 24 796084807 ps
T462 /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_mem_rw_with_rand_reset.3823120983 Feb 07 01:42:16 PM PST 24 Feb 07 01:42:22 PM PST 24 427564415 ps
T91 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_rw.3981109615 Feb 07 01:41:46 PM PST 24 Feb 07 01:42:00 PM PST 24 4642707111 ps
T463 /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_mem_rw_with_rand_reset.936817515 Feb 07 01:42:00 PM PST 24 Feb 07 01:42:08 PM PST 24 502655550 ps
T464 /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_intg_err.2263218844 Feb 07 01:41:34 PM PST 24 Feb 07 01:42:53 PM PST 24 7666417077 ps
T465 /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_intg_err.3701069059 Feb 07 01:42:02 PM PST 24 Feb 07 01:42:43 PM PST 24 7345144528 ps
T466 /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_intg_err.2465925533 Feb 07 01:42:02 PM PST 24 Feb 07 01:43:16 PM PST 24 970695359 ps
T467 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_bit_bash.593596185 Feb 07 01:41:42 PM PST 24 Feb 07 01:41:47 PM PST 24 829267184 ps
T468 /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_errors.2622474775 Feb 07 01:42:11 PM PST 24 Feb 07 01:42:30 PM PST 24 1966158997 ps
T469 /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_mem_rw_with_rand_reset.752738841 Feb 07 01:42:05 PM PST 24 Feb 07 01:42:18 PM PST 24 1153575507 ps
T470 /workspace/coverage/cover_reg_top/11.rom_ctrl_same_csr_outstanding.4103839223 Feb 07 01:42:10 PM PST 24 Feb 07 01:42:25 PM PST 24 1727176930 ps
T471 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_bit_bash.291903863 Feb 07 01:41:45 PM PST 24 Feb 07 01:41:59 PM PST 24 5561890193 ps
T472 /workspace/coverage/cover_reg_top/18.rom_ctrl_passthru_mem_tl_intg_err.3836971973 Feb 07 01:42:20 PM PST 24 Feb 07 01:43:23 PM PST 24 3839122204 ps
T473 /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_errors.79874471 Feb 07 01:42:06 PM PST 24 Feb 07 01:42:15 PM PST 24 827074385 ps
T109 /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_intg_err.4155698182 Feb 07 01:42:02 PM PST 24 Feb 07 01:43:14 PM PST 24 271482103 ps
T474 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_rw.2174537408 Feb 07 01:41:46 PM PST 24 Feb 07 01:41:51 PM PST 24 85862965 ps

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_same_csr_outstanding.4089081067
Short name T30
Test name
Test status
Simulation time 10620194450 ps
CPU time 13.42 seconds
Started Feb 07 01:42:18 PM PST 24
Finished Feb 07 01:42:32 PM PST 24
Peak memory 218012 kb
Host smart-5c63abe3-b637-4f1b-9ded-4d0263e36162
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4089081067 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_
ctrl_same_csr_outstanding.4089081067
Directory /workspace/14.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/default/11.rom_ctrl_stress_all_with_rand_reset.2787493462
Short name T8
Test name
Test status
Simulation time 25115661262 ps
CPU time 975.04 seconds
Started Feb 07 01:02:07 PM PST 24
Finished Feb 07 01:18:25 PM PST 24
Peak memory 226968 kb
Host smart-23dfb54f-d2ba-44b5-846d-b9f335dfd67a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2787493462 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_stress_all_with_rand_reset.2787493462
Directory /workspace/11.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_passthru_mem_tl_intg_err.3974262861
Short name T45
Test name
Test status
Simulation time 8148521758 ps
CPU time 105.39 seconds
Started Feb 07 01:41:45 PM PST 24
Finished Feb 07 01:43:31 PM PST 24
Peak memory 218884 kb
Host smart-8b949902-26ce-4c8f-bf1d-08b9e4408ef1
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3974262861 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_pa
ssthru_mem_tl_intg_err.3974262861
Directory /workspace/2.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_errors.3387834580
Short name T34
Test name
Test status
Simulation time 98090920 ps
CPU time 6.31 seconds
Started Feb 07 01:41:43 PM PST 24
Finished Feb 07 01:41:50 PM PST 24
Peak memory 219108 kb
Host smart-ab8f1c20-d204-45ad-9d18-73e395b88e19
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3387834580 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_tl_errors.3387834580
Directory /workspace/4.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_intg_err.563205250
Short name T58
Test name
Test status
Simulation time 992740419 ps
CPU time 69.14 seconds
Started Feb 07 01:42:15 PM PST 24
Finished Feb 07 01:43:25 PM PST 24
Peak memory 218448 kb
Host smart-17f80bc4-98d9-44c0-9a18-f75fd003a9c1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=563205250 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_tl_in
tg_err.563205250
Directory /workspace/15.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/46.rom_ctrl_corrupt_sig_fatal_chk.2677977199
Short name T16
Test name
Test status
Simulation time 189023995088 ps
CPU time 469.91 seconds
Started Feb 07 01:04:22 PM PST 24
Finished Feb 07 01:12:12 PM PST 24
Peak memory 211812 kb
Host smart-8cf09726-12c7-426d-b258-56365157533c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2677977199 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_
corrupt_sig_fatal_chk.2677977199
Directory /workspace/46.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/0.rom_ctrl_smoke.2863920590
Short name T3
Test name
Test status
Simulation time 1323051902 ps
CPU time 20.78 seconds
Started Feb 07 01:01:01 PM PST 24
Finished Feb 07 01:01:23 PM PST 24
Peak memory 212496 kb
Host smart-5c92be0e-8d29-475d-ab72-da6c94f4cd42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2863920590 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_smoke.2863920590
Directory /workspace/0.rom_ctrl_smoke/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_errors.994934968
Short name T67
Test name
Test status
Simulation time 480225578 ps
CPU time 9.03 seconds
Started Feb 07 01:42:08 PM PST 24
Finished Feb 07 01:42:18 PM PST 24
Peak memory 218920 kb
Host smart-b7676f3b-935f-4e0f-8eec-c85315010746
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=994934968 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_tl_errors.994934968
Directory /workspace/13.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_passthru_mem_tl_intg_err.3993479573
Short name T80
Test name
Test status
Simulation time 15498344260 ps
CPU time 99 seconds
Started Feb 07 01:41:46 PM PST 24
Finished Feb 07 01:43:26 PM PST 24
Peak memory 210836 kb
Host smart-1d5adf56-d7f6-4c2c-b728-59c88e762e79
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3993479573 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_pa
ssthru_mem_tl_intg_err.3993479573
Directory /workspace/5.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/default/0.rom_ctrl_sec_cm.2596862955
Short name T49
Test name
Test status
Simulation time 646834338 ps
CPU time 127.51 seconds
Started Feb 07 01:01:06 PM PST 24
Finished Feb 07 01:03:14 PM PST 24
Peak memory 244288 kb
Host smart-48c8c05b-41a5-4105-84f1-eda9fd0865b4
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2596862955 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_sec_cm.2596862955
Directory /workspace/0.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_intg_err.2921488170
Short name T68
Test name
Test status
Simulation time 2500330151 ps
CPU time 72.88 seconds
Started Feb 07 01:41:45 PM PST 24
Finished Feb 07 01:42:59 PM PST 24
Peak memory 219120 kb
Host smart-07ac4ce7-694e-4a3f-a17a-804a3bf49d2c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2921488170 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_tl_in
tg_err.2921488170
Directory /workspace/1.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/14.rom_ctrl_corrupt_sig_fatal_chk.2338824490
Short name T21
Test name
Test status
Simulation time 97961033604 ps
CPU time 207.14 seconds
Started Feb 07 01:02:28 PM PST 24
Finished Feb 07 01:05:56 PM PST 24
Peak memory 233048 kb
Host smart-84b8c4fe-e1c8-4691-b512-1731f7ff181f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2338824490 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_
corrupt_sig_fatal_chk.2338824490
Directory /workspace/14.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/44.rom_ctrl_kmac_err_chk.3037989000
Short name T2
Test name
Test status
Simulation time 45389960062 ps
CPU time 27.42 seconds
Started Feb 07 01:04:16 PM PST 24
Finished Feb 07 01:04:45 PM PST 24
Peak memory 211112 kb
Host smart-5624a3b9-c1c2-4d73-8ccf-458eaaf61d80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3037989000 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_kmac_err_chk.3037989000
Directory /workspace/44.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/22.rom_ctrl_kmac_err_chk.4221063347
Short name T332
Test name
Test status
Simulation time 4036225938 ps
CPU time 29.52 seconds
Started Feb 07 01:02:47 PM PST 24
Finished Feb 07 01:03:20 PM PST 24
Peak memory 210796 kb
Host smart-eb8aa66b-3287-47e7-a040-7d7d83363208
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4221063347 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_kmac_err_chk.4221063347
Directory /workspace/22.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_mem_rw_with_rand_reset.1129819414
Short name T132
Test name
Test status
Simulation time 89888567 ps
CPU time 4.62 seconds
Started Feb 07 01:42:11 PM PST 24
Finished Feb 07 01:42:16 PM PST 24
Peak memory 219036 kb
Host smart-ec00dd64-c9cc-4d28-aa45-15ab0ca23b95
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1129819414 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 13.rom_ctrl_csr_mem_rw_with_rand_reset.1129819414
Directory /workspace/13.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_intg_err.2483996843
Short name T63
Test name
Test status
Simulation time 1433490112 ps
CPU time 76.01 seconds
Started Feb 07 01:42:17 PM PST 24
Finished Feb 07 01:43:33 PM PST 24
Peak memory 211188 kb
Host smart-ca84a9d4-b9d9-4a9c-af85-1b42eb303b1d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2483996843 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_tl_i
ntg_err.2483996843
Directory /workspace/19.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_intg_err.1170078648
Short name T107
Test name
Test status
Simulation time 694705190 ps
CPU time 40.32 seconds
Started Feb 07 01:41:41 PM PST 24
Finished Feb 07 01:42:22 PM PST 24
Peak memory 218972 kb
Host smart-0fb3d1d3-b340-47bb-9aa9-af82baadee27
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1170078648 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_tl_in
tg_err.1170078648
Directory /workspace/3.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/0.rom_ctrl_alert_test.3663896159
Short name T179
Test name
Test status
Simulation time 5994294391 ps
CPU time 12.89 seconds
Started Feb 07 01:01:06 PM PST 24
Finished Feb 07 01:01:19 PM PST 24
Peak memory 210620 kb
Host smart-8edb75dd-a6c6-46eb-9a33-3d89a31d33d8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3663896159 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_alert_test.3663896159
Directory /workspace/0.rom_ctrl_alert_test/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_passthru_mem_tl_intg_err.3793643215
Short name T37
Test name
Test status
Simulation time 1946703337 ps
CPU time 96.91 seconds
Started Feb 07 01:41:46 PM PST 24
Finished Feb 07 01:43:23 PM PST 24
Peak memory 218196 kb
Host smart-386d4495-2f19-4a6b-92a6-39c9917b247d
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3793643215 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_pa
ssthru_mem_tl_intg_err.3793643215
Directory /workspace/1.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_intg_err.2996085821
Short name T114
Test name
Test status
Simulation time 796084807 ps
CPU time 40.93 seconds
Started Feb 07 01:41:46 PM PST 24
Finished Feb 07 01:42:27 PM PST 24
Peak memory 218992 kb
Host smart-cde0fd3a-1aaa-4ec7-8b9c-57f40f0fa6c4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2996085821 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_tl_in
tg_err.2996085821
Directory /workspace/2.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/41.rom_ctrl_max_throughput_chk.2441223857
Short name T92
Test name
Test status
Simulation time 100779210 ps
CPU time 5.73 seconds
Started Feb 07 01:04:02 PM PST 24
Finished Feb 07 01:04:09 PM PST 24
Peak memory 210476 kb
Host smart-83e88f54-7f13-4e65-99d6-f6db83e197ca
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2441223857 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_max_throughput_chk.2441223857
Directory /workspace/41.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/49.rom_ctrl_stress_all_with_rand_reset.2973918733
Short name T13
Test name
Test status
Simulation time 55582712282 ps
CPU time 480.15 seconds
Started Feb 07 01:04:28 PM PST 24
Finished Feb 07 01:12:29 PM PST 24
Peak memory 224584 kb
Host smart-5d92ac9e-e831-4657-b459-7f95a08253f0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2973918733 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_stress_all_with_rand_reset.2973918733
Directory /workspace/49.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_aliasing.2588140452
Short name T90
Test name
Test status
Simulation time 2462633912 ps
CPU time 8.31 seconds
Started Feb 07 01:41:45 PM PST 24
Finished Feb 07 01:41:55 PM PST 24
Peak memory 210836 kb
Host smart-acad36c2-99df-4a61-8486-6a6475cac7b2
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2588140452 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_alia
sing.2588140452
Directory /workspace/0.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_bit_bash.1615283556
Short name T103
Test name
Test status
Simulation time 171937420 ps
CPU time 4.61 seconds
Started Feb 07 01:41:44 PM PST 24
Finished Feb 07 01:41:49 PM PST 24
Peak memory 216236 kb
Host smart-1209ea5d-7e86-4df9-906f-e061766de326
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1615283556 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_bit_
bash.1615283556
Directory /workspace/0.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_hw_reset.2895399322
Short name T118
Test name
Test status
Simulation time 1102591974 ps
CPU time 12.66 seconds
Started Feb 07 01:41:45 PM PST 24
Finished Feb 07 01:41:58 PM PST 24
Peak memory 210852 kb
Host smart-06632ee3-7295-441c-b968-4610c72056c1
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2895399322 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_hw_r
eset.2895399322
Directory /workspace/0.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_mem_rw_with_rand_reset.1206789738
Short name T115
Test name
Test status
Simulation time 358089632 ps
CPU time 4.81 seconds
Started Feb 07 01:41:43 PM PST 24
Finished Feb 07 01:41:48 PM PST 24
Peak memory 219028 kb
Host smart-66a68628-2f4c-4922-9bf7-f27884f7dbc8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1206789738 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 0.rom_ctrl_csr_mem_rw_with_rand_reset.1206789738
Directory /workspace/0.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_rw.2174537408
Short name T474
Test name
Test status
Simulation time 85862965 ps
CPU time 4.28 seconds
Started Feb 07 01:41:46 PM PST 24
Finished Feb 07 01:41:51 PM PST 24
Peak memory 215800 kb
Host smart-f375943c-e10a-4739-bff4-e46e9051c7d3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2174537408 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_rw.2174537408
Directory /workspace/0.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_partial_access.3006999123
Short name T429
Test name
Test status
Simulation time 428204197 ps
CPU time 6.9 seconds
Started Feb 07 01:41:47 PM PST 24
Finished Feb 07 01:41:55 PM PST 24
Peak memory 210748 kb
Host smart-49352d66-4985-4cac-b230-c6e840fbaef3
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3006999123 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctr
l_mem_partial_access.3006999123
Directory /workspace/0.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_walk.2392946829
Short name T120
Test name
Test status
Simulation time 1516987272 ps
CPU time 12.79 seconds
Started Feb 07 01:41:37 PM PST 24
Finished Feb 07 01:41:51 PM PST 24
Peak memory 210784 kb
Host smart-5fc13025-cde1-40ce-a4c2-e39fc5226028
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2392946829 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_mem_walk
.2392946829
Directory /workspace/0.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_passthru_mem_tl_intg_err.1296113285
Short name T457
Test name
Test status
Simulation time 17047814261 ps
CPU time 71.29 seconds
Started Feb 07 01:41:37 PM PST 24
Finished Feb 07 01:42:50 PM PST 24
Peak memory 210908 kb
Host smart-ff4a914c-8a63-4c03-a95c-b01582ee250e
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1296113285 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_pa
ssthru_mem_tl_intg_err.1296113285
Directory /workspace/0.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_same_csr_outstanding.571479582
Short name T427
Test name
Test status
Simulation time 620453574 ps
CPU time 8.28 seconds
Started Feb 07 01:41:51 PM PST 24
Finished Feb 07 01:42:00 PM PST 24
Peak memory 216744 kb
Host smart-9ccbda64-a5f3-4e2e-bf4d-aabe77d3f0ab
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=571479582 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ct
rl_same_csr_outstanding.571479582
Directory /workspace/0.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_errors.65581525
Short name T60
Test name
Test status
Simulation time 160939454 ps
CPU time 10.4 seconds
Started Feb 07 01:41:34 PM PST 24
Finished Feb 07 01:41:45 PM PST 24
Peak memory 219064 kb
Host smart-da5837e4-9915-4d7b-a3df-1911398aeb80
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=65581525 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_tl_errors.65581525
Directory /workspace/0.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_intg_err.2263218844
Short name T464
Test name
Test status
Simulation time 7666417077 ps
CPU time 78.12 seconds
Started Feb 07 01:41:34 PM PST 24
Finished Feb 07 01:42:53 PM PST 24
Peak memory 219048 kb
Host smart-58f67f69-14e7-45ae-8255-3075e1465792
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2263218844 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_tl_in
tg_err.2263218844
Directory /workspace/0.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_aliasing.397767907
Short name T84
Test name
Test status
Simulation time 493213773 ps
CPU time 5.75 seconds
Started Feb 07 01:41:47 PM PST 24
Finished Feb 07 01:41:54 PM PST 24
Peak memory 210864 kb
Host smart-1d643285-89f9-44ae-aaf9-0ee2b66f3a07
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=397767907 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_alias
ing.397767907
Directory /workspace/1.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_bit_bash.593596185
Short name T467
Test name
Test status
Simulation time 829267184 ps
CPU time 4.56 seconds
Started Feb 07 01:41:42 PM PST 24
Finished Feb 07 01:41:47 PM PST 24
Peak memory 210872 kb
Host smart-f65fd43b-60d2-46ff-aed6-75c00f360d26
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=593596185 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_bit_b
ash.593596185
Directory /workspace/1.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_hw_reset.2164507083
Short name T125
Test name
Test status
Simulation time 7009485522 ps
CPU time 13.64 seconds
Started Feb 07 01:41:46 PM PST 24
Finished Feb 07 01:42:01 PM PST 24
Peak memory 210900 kb
Host smart-647fadaf-54c3-41a5-9972-2c1b3c4ff558
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2164507083 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_hw_r
eset.2164507083
Directory /workspace/1.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_mem_rw_with_rand_reset.3701991445
Short name T131
Test name
Test status
Simulation time 4170071553 ps
CPU time 16.04 seconds
Started Feb 07 01:41:42 PM PST 24
Finished Feb 07 01:41:59 PM PST 24
Peak memory 212396 kb
Host smart-eaf42f25-28b0-43f8-95ba-882a1fe76dac
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3701991445 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 1.rom_ctrl_csr_mem_rw_with_rand_reset.3701991445
Directory /workspace/1.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_rw.1475434032
Short name T88
Test name
Test status
Simulation time 1970196552 ps
CPU time 15.91 seconds
Started Feb 07 01:41:51 PM PST 24
Finished Feb 07 01:42:07 PM PST 24
Peak memory 210824 kb
Host smart-b67da9ff-9156-4902-a593-a58b79f2ea99
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1475434032 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_rw.1475434032
Directory /workspace/1.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_partial_access.1856578730
Short name T139
Test name
Test status
Simulation time 5255138928 ps
CPU time 11.93 seconds
Started Feb 07 01:41:48 PM PST 24
Finished Feb 07 01:42:00 PM PST 24
Peak memory 210808 kb
Host smart-30c60049-34d2-4c3a-a67b-d2e4591ce754
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1856578730 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctr
l_mem_partial_access.1856578730
Directory /workspace/1.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_walk.1875346709
Short name T456
Test name
Test status
Simulation time 161706462 ps
CPU time 4.23 seconds
Started Feb 07 01:41:46 PM PST 24
Finished Feb 07 01:41:51 PM PST 24
Peak memory 210760 kb
Host smart-1b4e3e9e-2696-4c3b-a47d-7748d3b60709
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1875346709 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_mem_walk
.1875346709
Directory /workspace/1.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_same_csr_outstanding.663553209
Short name T461
Test name
Test status
Simulation time 3475919728 ps
CPU time 11.49 seconds
Started Feb 07 01:41:42 PM PST 24
Finished Feb 07 01:41:54 PM PST 24
Peak memory 210808 kb
Host smart-9850c77f-53a0-4b45-adca-0921765308a0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=663553209 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ct
rl_same_csr_outstanding.663553209
Directory /workspace/1.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_errors.3354948657
Short name T446
Test name
Test status
Simulation time 1293866550 ps
CPU time 16.86 seconds
Started Feb 07 01:41:45 PM PST 24
Finished Feb 07 01:42:02 PM PST 24
Peak memory 219060 kb
Host smart-da937376-aa8d-42be-8c54-515e84dfc7af
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3354948657 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_tl_errors.3354948657
Directory /workspace/1.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_mem_rw_with_rand_reset.2262789409
Short name T47
Test name
Test status
Simulation time 423164993 ps
CPU time 4.74 seconds
Started Feb 07 01:42:05 PM PST 24
Finished Feb 07 01:42:10 PM PST 24
Peak memory 219052 kb
Host smart-30398bc1-8f1b-48db-9ded-c0b1dc88ae8c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2262789409 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 10.rom_ctrl_csr_mem_rw_with_rand_reset.2262789409
Directory /workspace/10.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_rw.2655496377
Short name T130
Test name
Test status
Simulation time 2995751248 ps
CPU time 12.86 seconds
Started Feb 07 01:42:06 PM PST 24
Finished Feb 07 01:42:19 PM PST 24
Peak memory 217000 kb
Host smart-a97f84e8-fd9d-469a-9408-2008b1cb3ff3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2655496377 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_csr_rw.2655496377
Directory /workspace/10.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_passthru_mem_tl_intg_err.2601361871
Short name T453
Test name
Test status
Simulation time 2038099188 ps
CPU time 50.05 seconds
Started Feb 07 01:42:07 PM PST 24
Finished Feb 07 01:42:58 PM PST 24
Peak memory 210764 kb
Host smart-9a1434e1-b996-4c46-8906-248387371746
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2601361871 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_p
assthru_mem_tl_intg_err.2601361871
Directory /workspace/10.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_same_csr_outstanding.3847441213
Short name T87
Test name
Test status
Simulation time 1443498749 ps
CPU time 14.29 seconds
Started Feb 07 01:42:06 PM PST 24
Finished Feb 07 01:42:21 PM PST 24
Peak memory 210856 kb
Host smart-326f9338-96a3-4db6-8cfe-aedbfcbf0731
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3847441213 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_
ctrl_same_csr_outstanding.3847441213
Directory /workspace/10.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_errors.1498377604
Short name T36
Test name
Test status
Simulation time 88840634 ps
CPU time 6.37 seconds
Started Feb 07 01:42:08 PM PST 24
Finished Feb 07 01:42:15 PM PST 24
Peak memory 218972 kb
Host smart-ae7249cc-05dd-48ff-a94b-1fa3be7925b3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1498377604 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_tl_errors.1498377604
Directory /workspace/10.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_intg_err.3858468957
Short name T38
Test name
Test status
Simulation time 2932739613 ps
CPU time 38.04 seconds
Started Feb 07 01:42:06 PM PST 24
Finished Feb 07 01:42:45 PM PST 24
Peak memory 219100 kb
Host smart-6b08806c-3959-4de8-8775-5c7a90a2339c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3858468957 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_tl_i
ntg_err.3858468957
Directory /workspace/10.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_mem_rw_with_rand_reset.270978990
Short name T440
Test name
Test status
Simulation time 829978546 ps
CPU time 9.88 seconds
Started Feb 07 01:42:06 PM PST 24
Finished Feb 07 01:42:16 PM PST 24
Peak memory 219056 kb
Host smart-9f7d5cb1-b988-40cf-bd82-f5b53e8d93ef
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=270978990 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 11.rom_ctrl_csr_mem_rw_with_rand_reset.270978990
Directory /workspace/11.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_rw.1563197625
Short name T82
Test name
Test status
Simulation time 1948588430 ps
CPU time 15.44 seconds
Started Feb 07 01:42:09 PM PST 24
Finished Feb 07 01:42:25 PM PST 24
Peak memory 210860 kb
Host smart-086a1555-6b5f-4546-a2e4-31050535d9bc
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1563197625 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_csr_rw.1563197625
Directory /workspace/11.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_passthru_mem_tl_intg_err.128419867
Short name T73
Test name
Test status
Simulation time 52121562805 ps
CPU time 189.76 seconds
Started Feb 07 01:42:08 PM PST 24
Finished Feb 07 01:45:19 PM PST 24
Peak memory 212032 kb
Host smart-baf084b5-98ff-49e2-b3ee-b328999b1184
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=128419867 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_pa
ssthru_mem_tl_intg_err.128419867
Directory /workspace/11.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_same_csr_outstanding.4103839223
Short name T470
Test name
Test status
Simulation time 1727176930 ps
CPU time 14.38 seconds
Started Feb 07 01:42:10 PM PST 24
Finished Feb 07 01:42:25 PM PST 24
Peak memory 210696 kb
Host smart-5da5d108-6c39-4302-9f21-a4417cf9dcb5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4103839223 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_
ctrl_same_csr_outstanding.4103839223
Directory /workspace/11.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_errors.2643129154
Short name T448
Test name
Test status
Simulation time 7352177615 ps
CPU time 18.03 seconds
Started Feb 07 01:42:08 PM PST 24
Finished Feb 07 01:42:27 PM PST 24
Peak memory 219032 kb
Host smart-c78f8826-d23e-41da-aea4-e8c781d84816
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2643129154 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_tl_errors.2643129154
Directory /workspace/11.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_intg_err.1034942783
Short name T137
Test name
Test status
Simulation time 10722370213 ps
CPU time 46.73 seconds
Started Feb 07 01:42:06 PM PST 24
Finished Feb 07 01:42:53 PM PST 24
Peak memory 219060 kb
Host smart-c71b2d8d-26c4-48f9-87de-6f028f0699d4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1034942783 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_tl_i
ntg_err.1034942783
Directory /workspace/11.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_mem_rw_with_rand_reset.4126089691
Short name T141
Test name
Test status
Simulation time 197179717 ps
CPU time 4.41 seconds
Started Feb 07 01:42:07 PM PST 24
Finished Feb 07 01:42:12 PM PST 24
Peak memory 218696 kb
Host smart-a5edf1d9-ee59-4db1-b3ab-32665feda7ae
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4126089691 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 12.rom_ctrl_csr_mem_rw_with_rand_reset.4126089691
Directory /workspace/12.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_rw.3159225131
Short name T126
Test name
Test status
Simulation time 11378387195 ps
CPU time 13.82 seconds
Started Feb 07 01:42:07 PM PST 24
Finished Feb 07 01:42:22 PM PST 24
Peak memory 210808 kb
Host smart-0908f07c-53db-4625-91b3-02ac199b4948
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3159225131 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_csr_rw.3159225131
Directory /workspace/12.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_same_csr_outstanding.1879472055
Short name T435
Test name
Test status
Simulation time 4906019215 ps
CPU time 11.19 seconds
Started Feb 07 01:42:08 PM PST 24
Finished Feb 07 01:42:20 PM PST 24
Peak memory 210760 kb
Host smart-5dccd452-60d0-49a0-9581-34c20f018fad
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1879472055 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_
ctrl_same_csr_outstanding.1879472055
Directory /workspace/12.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_errors.2622474775
Short name T468
Test name
Test status
Simulation time 1966158997 ps
CPU time 18.08 seconds
Started Feb 07 01:42:11 PM PST 24
Finished Feb 07 01:42:30 PM PST 24
Peak memory 219080 kb
Host smart-0792816d-cd2e-45c0-9930-24a4a84bf3ef
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2622474775 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_tl_errors.2622474775
Directory /workspace/12.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_intg_err.4038451202
Short name T124
Test name
Test status
Simulation time 525280296 ps
CPU time 38.61 seconds
Started Feb 07 01:42:07 PM PST 24
Finished Feb 07 01:42:47 PM PST 24
Peak memory 210372 kb
Host smart-0e66099c-42ab-49a1-8b0c-75beba177680
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4038451202 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_tl_i
ntg_err.4038451202
Directory /workspace/12.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_rw.2883098100
Short name T438
Test name
Test status
Simulation time 6043935400 ps
CPU time 12.86 seconds
Started Feb 07 01:42:07 PM PST 24
Finished Feb 07 01:42:20 PM PST 24
Peak memory 210832 kb
Host smart-d71cdc3e-4c57-48d3-984c-d19de3a0c2f7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2883098100 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_csr_rw.2883098100
Directory /workspace/13.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_passthru_mem_tl_intg_err.2544237782
Short name T72
Test name
Test status
Simulation time 120945628046 ps
CPU time 339.61 seconds
Started Feb 07 01:42:06 PM PST 24
Finished Feb 07 01:47:46 PM PST 24
Peak memory 210964 kb
Host smart-8f171df9-00db-4df5-afd0-5c489cf8b02a
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2544237782 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_p
assthru_mem_tl_intg_err.2544237782
Directory /workspace/13.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_same_csr_outstanding.3713474116
Short name T129
Test name
Test status
Simulation time 1491162835 ps
CPU time 10.65 seconds
Started Feb 07 01:42:08 PM PST 24
Finished Feb 07 01:42:19 PM PST 24
Peak memory 210776 kb
Host smart-25acaaad-6dbb-4553-ae91-34014201de9c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3713474116 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_
ctrl_same_csr_outstanding.3713474116
Directory /workspace/13.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_intg_err.1424427153
Short name T136
Test name
Test status
Simulation time 664217843 ps
CPU time 40.15 seconds
Started Feb 07 01:42:05 PM PST 24
Finished Feb 07 01:42:45 PM PST 24
Peak memory 218980 kb
Host smart-0cdcb09d-7428-47b2-b75d-f6595badd88f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1424427153 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_tl_i
ntg_err.1424427153
Directory /workspace/13.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_mem_rw_with_rand_reset.189221829
Short name T424
Test name
Test status
Simulation time 5276597834 ps
CPU time 12.71 seconds
Started Feb 07 01:42:15 PM PST 24
Finished Feb 07 01:42:28 PM PST 24
Peak memory 219116 kb
Host smart-7bc8ef2d-25fa-49f1-a946-31efe5ddba29
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=189221829 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 14.rom_ctrl_csr_mem_rw_with_rand_reset.189221829
Directory /workspace/14.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_rw.3928924282
Short name T442
Test name
Test status
Simulation time 1584037052 ps
CPU time 10.73 seconds
Started Feb 07 01:42:16 PM PST 24
Finished Feb 07 01:42:28 PM PST 24
Peak memory 210824 kb
Host smart-f7c97f9f-6075-4dfa-989d-6bf37ca5a9a7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3928924282 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_csr_rw.3928924282
Directory /workspace/14.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_passthru_mem_tl_intg_err.1498731468
Short name T437
Test name
Test status
Simulation time 1057587231 ps
CPU time 52.34 seconds
Started Feb 07 01:42:11 PM PST 24
Finished Feb 07 01:43:04 PM PST 24
Peak memory 217860 kb
Host smart-06b9792b-8fae-48e8-8485-2241ffd657fe
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1498731468 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_p
assthru_mem_tl_intg_err.1498731468
Directory /workspace/14.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_errors.79874471
Short name T473
Test name
Test status
Simulation time 827074385 ps
CPU time 8.04 seconds
Started Feb 07 01:42:06 PM PST 24
Finished Feb 07 01:42:15 PM PST 24
Peak memory 219028 kb
Host smart-7e0f9af4-3b82-48e4-892e-2683cbe91895
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=79874471 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_tl_errors.79874471
Directory /workspace/14.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_intg_err.2051872218
Short name T111
Test name
Test status
Simulation time 1153850649 ps
CPU time 42.35 seconds
Started Feb 07 01:42:07 PM PST 24
Finished Feb 07 01:42:50 PM PST 24
Peak memory 218328 kb
Host smart-f6dc5c5c-f2a0-4055-a3ce-568ea241b15d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2051872218 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_tl_i
ntg_err.2051872218
Directory /workspace/14.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_mem_rw_with_rand_reset.3823120983
Short name T462
Test name
Test status
Simulation time 427564415 ps
CPU time 5.26 seconds
Started Feb 07 01:42:16 PM PST 24
Finished Feb 07 01:42:22 PM PST 24
Peak memory 219064 kb
Host smart-11d5e787-5279-4b5b-89a2-2cf83a1953d0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3823120983 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 15.rom_ctrl_csr_mem_rw_with_rand_reset.3823120983
Directory /workspace/15.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_rw.1665823242
Short name T79
Test name
Test status
Simulation time 2600551798 ps
CPU time 12.07 seconds
Started Feb 07 01:42:15 PM PST 24
Finished Feb 07 01:42:28 PM PST 24
Peak memory 210884 kb
Host smart-cf08bfa3-330a-4a4a-8343-02079c05d6a9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1665823242 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_csr_rw.1665823242
Directory /workspace/15.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_passthru_mem_tl_intg_err.1857570173
Short name T46
Test name
Test status
Simulation time 84371778742 ps
CPU time 387.31 seconds
Started Feb 07 01:42:16 PM PST 24
Finished Feb 07 01:48:44 PM PST 24
Peak memory 211880 kb
Host smart-bdc48983-bcf5-441b-b07c-0e1fc9c423ff
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1857570173 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_p
assthru_mem_tl_intg_err.1857570173
Directory /workspace/15.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_same_csr_outstanding.4014040676
Short name T452
Test name
Test status
Simulation time 940975540 ps
CPU time 10.04 seconds
Started Feb 07 01:42:13 PM PST 24
Finished Feb 07 01:42:23 PM PST 24
Peak memory 217632 kb
Host smart-c45737d9-42f6-4d13-9c9d-0263d619c627
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4014040676 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_
ctrl_same_csr_outstanding.4014040676
Directory /workspace/15.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_errors.1019759709
Short name T455
Test name
Test status
Simulation time 449865298 ps
CPU time 9.7 seconds
Started Feb 07 01:42:17 PM PST 24
Finished Feb 07 01:42:27 PM PST 24
Peak memory 219064 kb
Host smart-c0cf4b46-d7a6-4724-a301-e5979859a40a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1019759709 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_tl_errors.1019759709
Directory /workspace/15.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_mem_rw_with_rand_reset.4161078175
Short name T66
Test name
Test status
Simulation time 817928148 ps
CPU time 6.36 seconds
Started Feb 07 01:42:12 PM PST 24
Finished Feb 07 01:42:19 PM PST 24
Peak memory 219020 kb
Host smart-97fe3280-9404-4f77-98bc-3b058fe82d70
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4161078175 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 16.rom_ctrl_csr_mem_rw_with_rand_reset.4161078175
Directory /workspace/16.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_rw.2119630291
Short name T75
Test name
Test status
Simulation time 10728007150 ps
CPU time 15.86 seconds
Started Feb 07 01:42:19 PM PST 24
Finished Feb 07 01:42:35 PM PST 24
Peak memory 210868 kb
Host smart-4dd3e216-6487-4bff-aefc-675ba6f64fef
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2119630291 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_csr_rw.2119630291
Directory /workspace/16.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_passthru_mem_tl_intg_err.1160756605
Short name T65
Test name
Test status
Simulation time 979240674 ps
CPU time 50 seconds
Started Feb 07 01:42:15 PM PST 24
Finished Feb 07 01:43:05 PM PST 24
Peak memory 210764 kb
Host smart-904f99b8-7e5b-47c1-ac49-cf373a3147d2
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1160756605 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_p
assthru_mem_tl_intg_err.1160756605
Directory /workspace/16.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_same_csr_outstanding.231155840
Short name T431
Test name
Test status
Simulation time 1482123825 ps
CPU time 12.86 seconds
Started Feb 07 01:42:15 PM PST 24
Finished Feb 07 01:42:29 PM PST 24
Peak memory 210812 kb
Host smart-786ab41f-bd5e-4f29-8f3b-4970635a93dd
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=231155840 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_c
trl_same_csr_outstanding.231155840
Directory /workspace/16.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_errors.233240546
Short name T140
Test name
Test status
Simulation time 4717266080 ps
CPU time 16.62 seconds
Started Feb 07 01:42:15 PM PST 24
Finished Feb 07 01:42:32 PM PST 24
Peak memory 219136 kb
Host smart-ec1e8f4b-2b00-4f34-8c6a-c02b5f234694
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=233240546 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_tl_errors.233240546
Directory /workspace/16.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_intg_err.3856619654
Short name T106
Test name
Test status
Simulation time 4483958838 ps
CPU time 79.73 seconds
Started Feb 07 01:42:16 PM PST 24
Finished Feb 07 01:43:36 PM PST 24
Peak memory 219044 kb
Host smart-24b7ef94-9801-42eb-b6d2-c7e0ea89b787
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3856619654 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_tl_i
ntg_err.3856619654
Directory /workspace/16.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_mem_rw_with_rand_reset.1493459677
Short name T59
Test name
Test status
Simulation time 1944997697 ps
CPU time 8.46 seconds
Started Feb 07 01:42:13 PM PST 24
Finished Feb 07 01:42:22 PM PST 24
Peak memory 219104 kb
Host smart-6baa78e1-20b4-49c0-85a6-bbccb867a59e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1493459677 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 17.rom_ctrl_csr_mem_rw_with_rand_reset.1493459677
Directory /workspace/17.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_rw.1202539840
Short name T433
Test name
Test status
Simulation time 3471199117 ps
CPU time 14.21 seconds
Started Feb 07 01:42:20 PM PST 24
Finished Feb 07 01:42:35 PM PST 24
Peak memory 210860 kb
Host smart-2770c5e3-7e27-489c-916b-0587cd58bc3e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1202539840 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_csr_rw.1202539840
Directory /workspace/17.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_passthru_mem_tl_intg_err.500970278
Short name T459
Test name
Test status
Simulation time 39632022034 ps
CPU time 183.96 seconds
Started Feb 07 01:42:14 PM PST 24
Finished Feb 07 01:45:18 PM PST 24
Peak memory 210900 kb
Host smart-c000fd63-ad7d-453a-abb8-42d65a5c609f
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=500970278 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_pa
ssthru_mem_tl_intg_err.500970278
Directory /workspace/17.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_same_csr_outstanding.3981897115
Short name T444
Test name
Test status
Simulation time 1508278994 ps
CPU time 13.17 seconds
Started Feb 07 01:42:14 PM PST 24
Finished Feb 07 01:42:28 PM PST 24
Peak memory 217716 kb
Host smart-31704d93-5e88-4ebe-b794-d8479f5297bf
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3981897115 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_
ctrl_same_csr_outstanding.3981897115
Directory /workspace/17.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_errors.636335995
Short name T428
Test name
Test status
Simulation time 292458619 ps
CPU time 9.94 seconds
Started Feb 07 01:42:13 PM PST 24
Finished Feb 07 01:42:24 PM PST 24
Peak memory 219092 kb
Host smart-b947b941-1d17-46c9-8c8b-b484795330de
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=636335995 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_tl_errors.636335995
Directory /workspace/17.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_intg_err.2422511529
Short name T110
Test name
Test status
Simulation time 608775973 ps
CPU time 36.55 seconds
Started Feb 07 01:42:16 PM PST 24
Finished Feb 07 01:42:53 PM PST 24
Peak memory 218104 kb
Host smart-f79337b9-df41-4f76-bf12-260f28f0c0f5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2422511529 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_tl_i
ntg_err.2422511529
Directory /workspace/17.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_mem_rw_with_rand_reset.1009347242
Short name T426
Test name
Test status
Simulation time 1881675368 ps
CPU time 14.68 seconds
Started Feb 07 01:42:15 PM PST 24
Finished Feb 07 01:42:30 PM PST 24
Peak memory 219048 kb
Host smart-667afbf8-d617-4ca0-8887-e590ad8a4ac2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1009347242 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 18.rom_ctrl_csr_mem_rw_with_rand_reset.1009347242
Directory /workspace/18.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_rw.661895415
Short name T78
Test name
Test status
Simulation time 362436134 ps
CPU time 4.29 seconds
Started Feb 07 01:42:17 PM PST 24
Finished Feb 07 01:42:22 PM PST 24
Peak memory 216432 kb
Host smart-a1af85a9-a103-4ef9-9ef8-5f4c044c23f5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=661895415 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_csr_rw.661895415
Directory /workspace/18.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_passthru_mem_tl_intg_err.3836971973
Short name T472
Test name
Test status
Simulation time 3839122204 ps
CPU time 62.94 seconds
Started Feb 07 01:42:20 PM PST 24
Finished Feb 07 01:43:23 PM PST 24
Peak memory 218948 kb
Host smart-ae80d764-aecb-41fa-863b-976e5ddd0628
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3836971973 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_p
assthru_mem_tl_intg_err.3836971973
Directory /workspace/18.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_same_csr_outstanding.2641939782
Short name T86
Test name
Test status
Simulation time 557638247 ps
CPU time 7.4 seconds
Started Feb 07 01:42:18 PM PST 24
Finished Feb 07 01:42:27 PM PST 24
Peak memory 216592 kb
Host smart-25cd15d4-e1a2-4c00-9e28-2e123956d394
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2641939782 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_
ctrl_same_csr_outstanding.2641939782
Directory /workspace/18.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_errors.2707211845
Short name T458
Test name
Test status
Simulation time 779557799 ps
CPU time 9.22 seconds
Started Feb 07 01:42:14 PM PST 24
Finished Feb 07 01:42:24 PM PST 24
Peak memory 219088 kb
Host smart-ae8a7ecd-0d2b-48dc-b8c5-b7a7dcdc703f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2707211845 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_tl_errors.2707211845
Directory /workspace/18.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_intg_err.765447536
Short name T112
Test name
Test status
Simulation time 245425750 ps
CPU time 71.38 seconds
Started Feb 07 01:42:15 PM PST 24
Finished Feb 07 01:43:27 PM PST 24
Peak memory 211188 kb
Host smart-a75790e5-c118-49c3-81e4-f444197ec6d7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=765447536 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_tl_in
tg_err.765447536
Directory /workspace/18.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_mem_rw_with_rand_reset.220998475
Short name T121
Test name
Test status
Simulation time 178171549 ps
CPU time 4.64 seconds
Started Feb 07 01:42:14 PM PST 24
Finished Feb 07 01:42:19 PM PST 24
Peak memory 218956 kb
Host smart-b850a287-8bf5-4b6a-ae1d-0832886082b9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=220998475 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 19.rom_ctrl_csr_mem_rw_with_rand_reset.220998475
Directory /workspace/19.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_rw.2294279590
Short name T454
Test name
Test status
Simulation time 823746177 ps
CPU time 6.94 seconds
Started Feb 07 01:42:19 PM PST 24
Finished Feb 07 01:42:26 PM PST 24
Peak memory 210892 kb
Host smart-3949a821-08ce-4bc8-9d77-237ca56269df
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2294279590 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_csr_rw.2294279590
Directory /workspace/19.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_passthru_mem_tl_intg_err.3466889242
Short name T70
Test name
Test status
Simulation time 33690824961 ps
CPU time 340.49 seconds
Started Feb 07 01:42:12 PM PST 24
Finished Feb 07 01:47:53 PM PST 24
Peak memory 210868 kb
Host smart-1cefe0f2-c19c-4ac7-a83c-9b759f6e7cfa
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3466889242 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_p
assthru_mem_tl_intg_err.3466889242
Directory /workspace/19.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_same_csr_outstanding.4148865458
Short name T445
Test name
Test status
Simulation time 87279282 ps
CPU time 4.43 seconds
Started Feb 07 01:42:16 PM PST 24
Finished Feb 07 01:42:22 PM PST 24
Peak memory 216908 kb
Host smart-1e0f50f2-e563-4f5d-bf63-01b40b2e8862
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4148865458 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_
ctrl_same_csr_outstanding.4148865458
Directory /workspace/19.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_errors.3440564081
Short name T76
Test name
Test status
Simulation time 534871967 ps
CPU time 10.16 seconds
Started Feb 07 01:42:15 PM PST 24
Finished Feb 07 01:42:26 PM PST 24
Peak memory 219076 kb
Host smart-5de54db5-7e2a-43e3-8a9b-5457b63b95fb
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3440564081 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_tl_errors.3440564081
Directory /workspace/19.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_aliasing.2680955045
Short name T451
Test name
Test status
Simulation time 86586170 ps
CPU time 4.21 seconds
Started Feb 07 01:41:50 PM PST 24
Finished Feb 07 01:41:55 PM PST 24
Peak memory 215948 kb
Host smart-efae25b2-d702-400e-a2d0-e9560f8052fa
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2680955045 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_alia
sing.2680955045
Directory /workspace/2.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_bit_bash.291903863
Short name T471
Test name
Test status
Simulation time 5561890193 ps
CPU time 13.67 seconds
Started Feb 07 01:41:45 PM PST 24
Finished Feb 07 01:41:59 PM PST 24
Peak memory 210912 kb
Host smart-aa59ffd3-7076-42c9-9fbb-071c5e9505f5
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=291903863 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_bit_b
ash.291903863
Directory /workspace/2.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_hw_reset.2242712907
Short name T439
Test name
Test status
Simulation time 172535853 ps
CPU time 6.91 seconds
Started Feb 07 01:41:45 PM PST 24
Finished Feb 07 01:41:53 PM PST 24
Peak memory 210828 kb
Host smart-fb300e8b-5a89-45bc-9edf-5a0be8c3859c
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2242712907 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_hw_r
eset.2242712907
Directory /workspace/2.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_mem_rw_with_rand_reset.670911792
Short name T48
Test name
Test status
Simulation time 1855710674 ps
CPU time 13.41 seconds
Started Feb 07 01:41:45 PM PST 24
Finished Feb 07 01:41:59 PM PST 24
Peak memory 219056 kb
Host smart-52ea640e-8bf0-4c37-8c41-df829d3b6a65
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=670911792 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 2.rom_ctrl_csr_mem_rw_with_rand_reset.670911792
Directory /workspace/2.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_rw.2617429396
Short name T32
Test name
Test status
Simulation time 5147662864 ps
CPU time 11.06 seconds
Started Feb 07 01:41:50 PM PST 24
Finished Feb 07 01:42:02 PM PST 24
Peak memory 210612 kb
Host smart-544b8db7-566b-4b0e-a6a7-632f618d6426
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2617429396 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_rw.2617429396
Directory /workspace/2.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_partial_access.3179780459
Short name T33
Test name
Test status
Simulation time 6149605859 ps
CPU time 9.75 seconds
Started Feb 07 01:41:42 PM PST 24
Finished Feb 07 01:41:53 PM PST 24
Peak memory 210852 kb
Host smart-8d49e1b4-519d-4308-ad67-63aa026bf2f5
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3179780459 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctr
l_mem_partial_access.3179780459
Directory /workspace/2.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_walk.2285391548
Short name T432
Test name
Test status
Simulation time 1682301077 ps
CPU time 6.75 seconds
Started Feb 07 01:41:42 PM PST 24
Finished Feb 07 01:41:49 PM PST 24
Peak memory 210772 kb
Host smart-7d5f567d-5c34-4db4-9271-68146a6af2b1
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2285391548 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_mem_walk
.2285391548
Directory /workspace/2.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_same_csr_outstanding.2427564092
Short name T104
Test name
Test status
Simulation time 1021952060 ps
CPU time 6.29 seconds
Started Feb 07 01:41:47 PM PST 24
Finished Feb 07 01:41:54 PM PST 24
Peak memory 210800 kb
Host smart-38b49674-cf76-4830-b7bb-7af9a833f0ad
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2427564092 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_c
trl_same_csr_outstanding.2427564092
Directory /workspace/2.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_errors.2205180621
Short name T69
Test name
Test status
Simulation time 653064601 ps
CPU time 10.75 seconds
Started Feb 07 01:41:44 PM PST 24
Finished Feb 07 01:41:56 PM PST 24
Peak memory 219120 kb
Host smart-f5ed966b-2f8f-4089-b7ef-86589044ec65
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2205180621 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_tl_errors.2205180621
Directory /workspace/2.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_aliasing.3213745850
Short name T77
Test name
Test status
Simulation time 868670480 ps
CPU time 9.54 seconds
Started Feb 07 01:41:51 PM PST 24
Finished Feb 07 01:42:01 PM PST 24
Peak memory 217064 kb
Host smart-39ec50a5-231f-406a-a5f0-f73a245ff4e2
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3213745850 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_alia
sing.3213745850
Directory /workspace/3.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_bit_bash.2405406284
Short name T423
Test name
Test status
Simulation time 85430832 ps
CPU time 4.18 seconds
Started Feb 07 01:41:50 PM PST 24
Finished Feb 07 01:41:54 PM PST 24
Peak memory 215852 kb
Host smart-0ecf9608-71a6-48d9-adfd-e9df00e90a3f
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2405406284 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_bit_
bash.2405406284
Directory /workspace/3.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_hw_reset.1994359432
Short name T89
Test name
Test status
Simulation time 6649445014 ps
CPU time 13.97 seconds
Started Feb 07 01:41:45 PM PST 24
Finished Feb 07 01:41:59 PM PST 24
Peak memory 210948 kb
Host smart-b2d9c7aa-d9cf-4864-a374-af4d8fb384e1
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1994359432 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_hw_r
eset.1994359432
Directory /workspace/3.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_mem_rw_with_rand_reset.237764051
Short name T123
Test name
Test status
Simulation time 8555108738 ps
CPU time 15.51 seconds
Started Feb 07 01:41:45 PM PST 24
Finished Feb 07 01:42:01 PM PST 24
Peak memory 219060 kb
Host smart-8432a3a3-453f-42a1-8a48-672bd17a1e8b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=237764051 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 3.rom_ctrl_csr_mem_rw_with_rand_reset.237764051
Directory /workspace/3.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_rw.1093675930
Short name T81
Test name
Test status
Simulation time 527550272 ps
CPU time 6.02 seconds
Started Feb 07 01:41:45 PM PST 24
Finished Feb 07 01:41:52 PM PST 24
Peak memory 210864 kb
Host smart-b09cc9bb-6943-4686-a78e-aa2326dba0d0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1093675930 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_rw.1093675930
Directory /workspace/3.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_partial_access.427068790
Short name T119
Test name
Test status
Simulation time 1227539521 ps
CPU time 11.26 seconds
Started Feb 07 01:41:45 PM PST 24
Finished Feb 07 01:41:57 PM PST 24
Peak memory 210780 kb
Host smart-2112843b-64b2-4e60-b8f5-4112c9228f40
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=427068790 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl
_mem_partial_access.427068790
Directory /workspace/3.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_walk.4152835181
Short name T122
Test name
Test status
Simulation time 555193157 ps
CPU time 7.49 seconds
Started Feb 07 01:41:47 PM PST 24
Finished Feb 07 01:41:56 PM PST 24
Peak memory 210804 kb
Host smart-3d994dde-5568-423b-a3d7-3b7f47b99445
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4152835181 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_mem_walk
.4152835181
Directory /workspace/3.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_same_csr_outstanding.1554820228
Short name T39
Test name
Test status
Simulation time 10317553076 ps
CPU time 16.69 seconds
Started Feb 07 01:41:45 PM PST 24
Finished Feb 07 01:42:02 PM PST 24
Peak memory 210752 kb
Host smart-6c5bb9a8-1144-48b8-8876-a65e8a68b004
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1554820228 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_c
trl_same_csr_outstanding.1554820228
Directory /workspace/3.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_errors.2890025495
Short name T56
Test name
Test status
Simulation time 1722604803 ps
CPU time 16.55 seconds
Started Feb 07 01:41:42 PM PST 24
Finished Feb 07 01:41:59 PM PST 24
Peak memory 219004 kb
Host smart-30be871a-a0fa-453a-988c-0549a06480f6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2890025495 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_tl_errors.2890025495
Directory /workspace/3.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_aliasing.361793040
Short name T138
Test name
Test status
Simulation time 346278595 ps
CPU time 4.33 seconds
Started Feb 07 01:41:45 PM PST 24
Finished Feb 07 01:41:50 PM PST 24
Peak memory 216376 kb
Host smart-5aef55a7-1f15-43cc-ab6e-e7f269cdd46d
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=361793040 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_alias
ing.361793040
Directory /workspace/4.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_bit_bash.480043457
Short name T460
Test name
Test status
Simulation time 2790367142 ps
CPU time 8.92 seconds
Started Feb 07 01:41:47 PM PST 24
Finished Feb 07 01:41:57 PM PST 24
Peak memory 210868 kb
Host smart-c7449869-4b57-4c43-b438-cde77805065b
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=480043457 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_bit_b
ash.480043457
Directory /workspace/4.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_hw_reset.4196563101
Short name T61
Test name
Test status
Simulation time 1481227643 ps
CPU time 14.52 seconds
Started Feb 07 01:41:51 PM PST 24
Finished Feb 07 01:42:06 PM PST 24
Peak memory 210824 kb
Host smart-39362cd4-9ba7-4d15-9246-1e511b42332e
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4196563101 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_hw_r
eset.4196563101
Directory /workspace/4.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_mem_rw_with_rand_reset.2146929952
Short name T128
Test name
Test status
Simulation time 88623557 ps
CPU time 4.53 seconds
Started Feb 07 01:41:51 PM PST 24
Finished Feb 07 01:41:56 PM PST 24
Peak memory 219016 kb
Host smart-408dca0e-a6d2-4267-88d8-c061df387fd4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2146929952 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 4.rom_ctrl_csr_mem_rw_with_rand_reset.2146929952
Directory /workspace/4.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_rw.3981109615
Short name T91
Test name
Test status
Simulation time 4642707111 ps
CPU time 13.37 seconds
Started Feb 07 01:41:46 PM PST 24
Finished Feb 07 01:42:00 PM PST 24
Peak memory 210836 kb
Host smart-4913e345-5778-44e6-96a3-c415668d5789
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3981109615 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_rw.3981109615
Directory /workspace/4.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_partial_access.1073906884
Short name T441
Test name
Test status
Simulation time 4108643654 ps
CPU time 5.74 seconds
Started Feb 07 01:41:45 PM PST 24
Finished Feb 07 01:41:52 PM PST 24
Peak memory 210688 kb
Host smart-ab15db54-e773-42a5-ab92-9150a4250aea
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1073906884 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctr
l_mem_partial_access.1073906884
Directory /workspace/4.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_walk.2440147430
Short name T133
Test name
Test status
Simulation time 2178274773 ps
CPU time 15.86 seconds
Started Feb 07 01:41:46 PM PST 24
Finished Feb 07 01:42:03 PM PST 24
Peak memory 210816 kb
Host smart-34d28aac-7f28-440c-8cd8-7b3807236cf2
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2440147430 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_mem_walk
.2440147430
Directory /workspace/4.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_passthru_mem_tl_intg_err.3010840158
Short name T450
Test name
Test status
Simulation time 8207528998 ps
CPU time 149.19 seconds
Started Feb 07 01:41:46 PM PST 24
Finished Feb 07 01:44:16 PM PST 24
Peak memory 210940 kb
Host smart-8a80da4e-8498-46da-a659-05dd0f44ddc8
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3010840158 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_pa
ssthru_mem_tl_intg_err.3010840158
Directory /workspace/4.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_same_csr_outstanding.601440734
Short name T134
Test name
Test status
Simulation time 171641790 ps
CPU time 4.32 seconds
Started Feb 07 01:41:45 PM PST 24
Finished Feb 07 01:41:51 PM PST 24
Peak memory 210824 kb
Host smart-84c5a6ed-ff70-458c-a6da-a69c072d5542
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=601440734 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ct
rl_same_csr_outstanding.601440734
Directory /workspace/4.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_intg_err.1762626188
Short name T105
Test name
Test status
Simulation time 2416063232 ps
CPU time 81.08 seconds
Started Feb 07 01:41:44 PM PST 24
Finished Feb 07 01:43:06 PM PST 24
Peak memory 219008 kb
Host smart-85dc22af-f5e6-4a11-8c67-8d1eafb05096
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1762626188 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_tl_in
tg_err.1762626188
Directory /workspace/4.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_mem_rw_with_rand_reset.1320535584
Short name T447
Test name
Test status
Simulation time 3459557920 ps
CPU time 9.62 seconds
Started Feb 07 01:42:00 PM PST 24
Finished Feb 07 01:42:10 PM PST 24
Peak memory 219112 kb
Host smart-c3a64fbc-bbcb-4e62-843a-6feaf1d4d47b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1320535584 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 5.rom_ctrl_csr_mem_rw_with_rand_reset.1320535584
Directory /workspace/5.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_rw.1178230542
Short name T85
Test name
Test status
Simulation time 1503320116 ps
CPU time 8.5 seconds
Started Feb 07 01:42:03 PM PST 24
Finished Feb 07 01:42:12 PM PST 24
Peak memory 210804 kb
Host smart-a6336c26-3c9f-4ede-903f-35fb26ece8f5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1178230542 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_csr_rw.1178230542
Directory /workspace/5.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_same_csr_outstanding.3811812089
Short name T127
Test name
Test status
Simulation time 327915287 ps
CPU time 6.15 seconds
Started Feb 07 01:42:01 PM PST 24
Finished Feb 07 01:42:09 PM PST 24
Peak memory 210864 kb
Host smart-daea661e-2d65-4d81-a923-b5de793a22a1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3811812089 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_c
trl_same_csr_outstanding.3811812089
Directory /workspace/5.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_errors.1516620881
Short name T116
Test name
Test status
Simulation time 3437995574 ps
CPU time 17.88 seconds
Started Feb 07 01:41:45 PM PST 24
Finished Feb 07 01:42:04 PM PST 24
Peak memory 219164 kb
Host smart-db6d0065-a65d-44d1-9776-9d20fa6cfcb8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1516620881 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_tl_errors.1516620881
Directory /workspace/5.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_intg_err.4155698182
Short name T109
Test name
Test status
Simulation time 271482103 ps
CPU time 70.35 seconds
Started Feb 07 01:42:02 PM PST 24
Finished Feb 07 01:43:14 PM PST 24
Peak memory 218936 kb
Host smart-4fd31001-2405-4e4f-b897-eceee63415ef
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4155698182 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_tl_in
tg_err.4155698182
Directory /workspace/5.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_mem_rw_with_rand_reset.4047601717
Short name T434
Test name
Test status
Simulation time 2851874952 ps
CPU time 12.87 seconds
Started Feb 07 01:42:02 PM PST 24
Finished Feb 07 01:42:17 PM PST 24
Peak memory 219124 kb
Host smart-1a6274b5-3f2f-4157-9dcb-e4f6de88f87e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4047601717 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 6.rom_ctrl_csr_mem_rw_with_rand_reset.4047601717
Directory /workspace/6.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_rw.3588120919
Short name T62
Test name
Test status
Simulation time 640395670 ps
CPU time 4.15 seconds
Started Feb 07 01:41:59 PM PST 24
Finished Feb 07 01:42:04 PM PST 24
Peak memory 216344 kb
Host smart-e16727c5-b04e-4309-a4da-b07dbbb7db80
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3588120919 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_csr_rw.3588120919
Directory /workspace/6.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_same_csr_outstanding.3937113290
Short name T135
Test name
Test status
Simulation time 996158721 ps
CPU time 10.16 seconds
Started Feb 07 01:41:59 PM PST 24
Finished Feb 07 01:42:10 PM PST 24
Peak memory 210768 kb
Host smart-ff1557d0-e079-4b47-8d38-bfcd0e208d21
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3937113290 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_c
trl_same_csr_outstanding.3937113290
Directory /workspace/6.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_errors.3736557772
Short name T64
Test name
Test status
Simulation time 11383312411 ps
CPU time 16.02 seconds
Started Feb 07 01:42:02 PM PST 24
Finished Feb 07 01:42:20 PM PST 24
Peak memory 219072 kb
Host smart-f8985339-a85d-49ee-9d80-da023ee18ab7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3736557772 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_tl_errors.3736557772
Directory /workspace/6.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_intg_err.3701069059
Short name T465
Test name
Test status
Simulation time 7345144528 ps
CPU time 39.27 seconds
Started Feb 07 01:42:02 PM PST 24
Finished Feb 07 01:42:43 PM PST 24
Peak memory 219012 kb
Host smart-660da48d-929d-402d-bb83-a711a1172be6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3701069059 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_tl_in
tg_err.3701069059
Directory /workspace/6.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_mem_rw_with_rand_reset.936817515
Short name T463
Test name
Test status
Simulation time 502655550 ps
CPU time 7.77 seconds
Started Feb 07 01:42:00 PM PST 24
Finished Feb 07 01:42:08 PM PST 24
Peak memory 219028 kb
Host smart-da9866e6-849b-4f10-aa82-0c2dd67586cd
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=936817515 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 7.rom_ctrl_csr_mem_rw_with_rand_reset.936817515
Directory /workspace/7.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_rw.3788982292
Short name T430
Test name
Test status
Simulation time 1464707779 ps
CPU time 12.62 seconds
Started Feb 07 01:41:59 PM PST 24
Finished Feb 07 01:42:12 PM PST 24
Peak memory 217088 kb
Host smart-61df2a55-0c18-4419-b38f-ebb7883c282e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3788982292 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_csr_rw.3788982292
Directory /workspace/7.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_passthru_mem_tl_intg_err.3358349505
Short name T71
Test name
Test status
Simulation time 12944562627 ps
CPU time 132.41 seconds
Started Feb 07 01:42:00 PM PST 24
Finished Feb 07 01:44:13 PM PST 24
Peak memory 210804 kb
Host smart-3a7bf42e-bfd1-446d-b0af-728868d4768f
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3358349505 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_pa
ssthru_mem_tl_intg_err.3358349505
Directory /workspace/7.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_same_csr_outstanding.264333248
Short name T31
Test name
Test status
Simulation time 11846628601 ps
CPU time 11.15 seconds
Started Feb 07 01:42:03 PM PST 24
Finished Feb 07 01:42:15 PM PST 24
Peak memory 217948 kb
Host smart-0ebc8b37-98d6-414f-91e3-95863fde0c97
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=264333248 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ct
rl_same_csr_outstanding.264333248
Directory /workspace/7.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_errors.960360801
Short name T449
Test name
Test status
Simulation time 2426368814 ps
CPU time 18.79 seconds
Started Feb 07 01:42:00 PM PST 24
Finished Feb 07 01:42:20 PM PST 24
Peak memory 219104 kb
Host smart-f142364f-9649-405f-91ef-f1e3b8f263f9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=960360801 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_tl_errors.960360801
Directory /workspace/7.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_intg_err.2465925533
Short name T466
Test name
Test status
Simulation time 970695359 ps
CPU time 72.7 seconds
Started Feb 07 01:42:02 PM PST 24
Finished Feb 07 01:43:16 PM PST 24
Peak memory 218948 kb
Host smart-efde124c-b6d7-4248-9456-0950241f8f7d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2465925533 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_tl_in
tg_err.2465925533
Directory /workspace/7.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_mem_rw_with_rand_reset.2543172139
Short name T117
Test name
Test status
Simulation time 4535513454 ps
CPU time 14.47 seconds
Started Feb 07 01:42:00 PM PST 24
Finished Feb 07 01:42:15 PM PST 24
Peak memory 219108 kb
Host smart-406a0fcd-2565-4f39-a2d3-d0100a9cc348
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2543172139 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 8.rom_ctrl_csr_mem_rw_with_rand_reset.2543172139
Directory /workspace/8.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_rw.1599098326
Short name T35
Test name
Test status
Simulation time 1180370597 ps
CPU time 6.46 seconds
Started Feb 07 01:42:03 PM PST 24
Finished Feb 07 01:42:10 PM PST 24
Peak memory 210832 kb
Host smart-e485108f-3613-44ab-b441-5ec5a43fe69c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1599098326 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_csr_rw.1599098326
Directory /workspace/8.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_passthru_mem_tl_intg_err.2152137860
Short name T83
Test name
Test status
Simulation time 7764296346 ps
CPU time 95.95 seconds
Started Feb 07 01:42:00 PM PST 24
Finished Feb 07 01:43:37 PM PST 24
Peak memory 210932 kb
Host smart-50778ffb-6022-4a86-972b-99e10b5cde48
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2152137860 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_pa
ssthru_mem_tl_intg_err.2152137860
Directory /workspace/8.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_same_csr_outstanding.125300743
Short name T436
Test name
Test status
Simulation time 1869770928 ps
CPU time 16.06 seconds
Started Feb 07 01:42:03 PM PST 24
Finished Feb 07 01:42:20 PM PST 24
Peak memory 210836 kb
Host smart-f53679e7-71ba-4945-bd8a-264342a4d02d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=125300743 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ct
rl_same_csr_outstanding.125300743
Directory /workspace/8.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_errors.3605455237
Short name T57
Test name
Test status
Simulation time 4117229949 ps
CPU time 18.03 seconds
Started Feb 07 01:42:02 PM PST 24
Finished Feb 07 01:42:21 PM PST 24
Peak memory 219124 kb
Host smart-d2a6c1ed-f9cd-4c21-ab31-ea2d3f8f4932
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3605455237 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_tl_errors.3605455237
Directory /workspace/8.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_intg_err.1802844031
Short name T108
Test name
Test status
Simulation time 4041021679 ps
CPU time 46.97 seconds
Started Feb 07 01:41:59 PM PST 24
Finished Feb 07 01:42:47 PM PST 24
Peak memory 219088 kb
Host smart-448ad382-f5c2-46d0-aca7-0a850297c91f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1802844031 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_tl_in
tg_err.1802844031
Directory /workspace/8.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_mem_rw_with_rand_reset.752738841
Short name T469
Test name
Test status
Simulation time 1153575507 ps
CPU time 11.83 seconds
Started Feb 07 01:42:05 PM PST 24
Finished Feb 07 01:42:18 PM PST 24
Peak memory 219020 kb
Host smart-9bddb5e9-6852-4cc6-9f3f-9eb691eff0ad
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=752738841 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 9.rom_ctrl_csr_mem_rw_with_rand_reset.752738841
Directory /workspace/9.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_rw.712904814
Short name T142
Test name
Test status
Simulation time 1813726906 ps
CPU time 14.69 seconds
Started Feb 07 01:41:58 PM PST 24
Finished Feb 07 01:42:13 PM PST 24
Peak memory 217228 kb
Host smart-5343363a-9235-4a67-a18d-4d419527d4e7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=712904814 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_csr_rw.712904814
Directory /workspace/9.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_passthru_mem_tl_intg_err.3917635978
Short name T74
Test name
Test status
Simulation time 38190199476 ps
CPU time 307.14 seconds
Started Feb 07 01:42:00 PM PST 24
Finished Feb 07 01:47:08 PM PST 24
Peak memory 219056 kb
Host smart-315fa7c2-6bdf-4336-9e16-bbee471af001
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3917635978 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_pa
ssthru_mem_tl_intg_err.3917635978
Directory /workspace/9.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_same_csr_outstanding.1900183835
Short name T425
Test name
Test status
Simulation time 546855506 ps
CPU time 7.61 seconds
Started Feb 07 01:42:00 PM PST 24
Finished Feb 07 01:42:08 PM PST 24
Peak memory 210836 kb
Host smart-bfa181d3-aaa0-4671-a95a-8aea98e96b63
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1900183835 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_c
trl_same_csr_outstanding.1900183835
Directory /workspace/9.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_errors.401339633
Short name T443
Test name
Test status
Simulation time 86458457 ps
CPU time 7.01 seconds
Started Feb 07 01:42:01 PM PST 24
Finished Feb 07 01:42:09 PM PST 24
Peak memory 219052 kb
Host smart-624f9575-f0d2-4124-a27a-42546a0d1322
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=401339633 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_tl_errors.401339633
Directory /workspace/9.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_intg_err.2153266095
Short name T113
Test name
Test status
Simulation time 1341084185 ps
CPU time 42.76 seconds
Started Feb 07 01:42:01 PM PST 24
Finished Feb 07 01:42:45 PM PST 24
Peak memory 218952 kb
Host smart-ca54f38f-d938-45aa-9c2b-36bd82bf6265
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2153266095 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_tl_in
tg_err.2153266095
Directory /workspace/9.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/0.rom_ctrl_corrupt_sig_fatal_chk.3488003964
Short name T300
Test name
Test status
Simulation time 6118131147 ps
CPU time 95.11 seconds
Started Feb 07 01:01:04 PM PST 24
Finished Feb 07 01:02:40 PM PST 24
Peak memory 235948 kb
Host smart-0a32d49c-cc57-48d7-b297-45072eb88a15
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3488003964 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_c
orrupt_sig_fatal_chk.3488003964
Directory /workspace/0.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/0.rom_ctrl_kmac_err_chk.135805126
Short name T404
Test name
Test status
Simulation time 2983500862 ps
CPU time 14.91 seconds
Started Feb 07 01:01:00 PM PST 24
Finished Feb 07 01:01:16 PM PST 24
Peak memory 210772 kb
Host smart-a1ef6786-9830-4093-baeb-307e17b0ad21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=135805126 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_kmac_err_chk.135805126
Directory /workspace/0.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/0.rom_ctrl_max_throughput_chk.3537163607
Short name T204
Test name
Test status
Simulation time 1044886968 ps
CPU time 12.03 seconds
Started Feb 07 01:01:01 PM PST 24
Finished Feb 07 01:01:15 PM PST 24
Peak memory 210536 kb
Host smart-882a33f5-71da-47bb-96e2-c446a0cb5b0b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3537163607 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_max_throughput_chk.3537163607
Directory /workspace/0.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/0.rom_ctrl_stress_all.2945521600
Short name T294
Test name
Test status
Simulation time 23377124612 ps
CPU time 54.8 seconds
Started Feb 07 01:01:01 PM PST 24
Finished Feb 07 01:01:58 PM PST 24
Peak memory 213416 kb
Host smart-3e755d37-6aa0-44d1-95fd-13e67949a96c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2945521600 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 0.rom_ctrl_stress_all.2945521600
Directory /workspace/0.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/0.rom_ctrl_stress_all_with_rand_reset.3881653156
Short name T397
Test name
Test status
Simulation time 37862474900 ps
CPU time 1394.9 seconds
Started Feb 07 01:01:02 PM PST 24
Finished Feb 07 01:24:18 PM PST 24
Peak memory 235284 kb
Host smart-22af56ac-79c0-497f-89c2-4aded33d09cf
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3881653156 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_stress_all_with_rand_reset.3881653156
Directory /workspace/0.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.rom_ctrl_alert_test.3687202492
Short name T271
Test name
Test status
Simulation time 1956276595 ps
CPU time 15.75 seconds
Started Feb 07 01:01:15 PM PST 24
Finished Feb 07 01:01:32 PM PST 24
Peak memory 210420 kb
Host smart-1607db0f-30c6-49c4-a41c-1d39bf087255
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3687202492 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_alert_test.3687202492
Directory /workspace/1.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/1.rom_ctrl_corrupt_sig_fatal_chk.1804536819
Short name T367
Test name
Test status
Simulation time 21571710197 ps
CPU time 123.05 seconds
Started Feb 07 01:01:15 PM PST 24
Finished Feb 07 01:03:19 PM PST 24
Peak memory 233040 kb
Host smart-ca4e1c16-ced2-45aa-aedb-97e4e4925542
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1804536819 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_c
orrupt_sig_fatal_chk.1804536819
Directory /workspace/1.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/1.rom_ctrl_kmac_err_chk.1096773234
Short name T187
Test name
Test status
Simulation time 3917207620 ps
CPU time 32.49 seconds
Started Feb 07 01:01:18 PM PST 24
Finished Feb 07 01:01:50 PM PST 24
Peak memory 210732 kb
Host smart-f35172ff-f63b-402e-bb4a-7da0d51708cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1096773234 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_kmac_err_chk.1096773234
Directory /workspace/1.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/1.rom_ctrl_max_throughput_chk.2227961237
Short name T258
Test name
Test status
Simulation time 11920263446 ps
CPU time 11.48 seconds
Started Feb 07 01:01:14 PM PST 24
Finished Feb 07 01:01:26 PM PST 24
Peak memory 210580 kb
Host smart-78d583f1-d78b-4103-ab88-f83608120e6b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2227961237 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_max_throughput_chk.2227961237
Directory /workspace/1.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/1.rom_ctrl_sec_cm.2531511680
Short name T41
Test name
Test status
Simulation time 3870389321 ps
CPU time 108.37 seconds
Started Feb 07 01:01:14 PM PST 24
Finished Feb 07 01:03:03 PM PST 24
Peak memory 235792 kb
Host smart-222f16cb-2ee7-4044-a66a-7bb23b59e3fa
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2531511680 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_sec_cm.2531511680
Directory /workspace/1.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/1.rom_ctrl_smoke.4209079857
Short name T233
Test name
Test status
Simulation time 2564449585 ps
CPU time 29.17 seconds
Started Feb 07 01:01:07 PM PST 24
Finished Feb 07 01:01:36 PM PST 24
Peak memory 213284 kb
Host smart-8bd72817-9047-4b66-a442-783709a4c0fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4209079857 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_smoke.4209079857
Directory /workspace/1.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/1.rom_ctrl_stress_all.2099652943
Short name T259
Test name
Test status
Simulation time 7626600970 ps
CPU time 75.45 seconds
Started Feb 07 01:01:16 PM PST 24
Finished Feb 07 01:02:32 PM PST 24
Peak memory 215180 kb
Host smart-188a6030-44e1-4a93-b036-d69c32b436a2
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2099652943 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 1.rom_ctrl_stress_all.2099652943
Directory /workspace/1.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/1.rom_ctrl_stress_all_with_rand_reset.1769971125
Short name T353
Test name
Test status
Simulation time 140487656487 ps
CPU time 1277.52 seconds
Started Feb 07 01:01:18 PM PST 24
Finished Feb 07 01:22:36 PM PST 24
Peak memory 235316 kb
Host smart-e53efa89-7dc9-4610-9b20-290d37d4eea5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1769971125 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_stress_all_with_rand_reset.1769971125
Directory /workspace/1.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.rom_ctrl_alert_test.4131390194
Short name T43
Test name
Test status
Simulation time 1245035700 ps
CPU time 11.63 seconds
Started Feb 07 01:02:03 PM PST 24
Finished Feb 07 01:02:15 PM PST 24
Peak memory 210496 kb
Host smart-5c78fce0-c4be-404a-ab51-858696187a63
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4131390194 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_alert_test.4131390194
Directory /workspace/10.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/10.rom_ctrl_corrupt_sig_fatal_chk.2076185843
Short name T197
Test name
Test status
Simulation time 120735252123 ps
CPU time 561.09 seconds
Started Feb 07 01:02:02 PM PST 24
Finished Feb 07 01:11:25 PM PST 24
Peak memory 233144 kb
Host smart-39599606-8415-4c72-bc93-2ecd38cb4ec4
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2076185843 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_
corrupt_sig_fatal_chk.2076185843
Directory /workspace/10.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/10.rom_ctrl_kmac_err_chk.593061586
Short name T144
Test name
Test status
Simulation time 2210978099 ps
CPU time 22.87 seconds
Started Feb 07 01:02:05 PM PST 24
Finished Feb 07 01:02:29 PM PST 24
Peak memory 210828 kb
Host smart-0a9eecc7-72a0-49a1-8dba-1bceddc8d295
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=593061586 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_kmac_err_chk.593061586
Directory /workspace/10.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/10.rom_ctrl_max_throughput_chk.2867108343
Short name T358
Test name
Test status
Simulation time 13110464975 ps
CPU time 15.21 seconds
Started Feb 07 01:02:04 PM PST 24
Finished Feb 07 01:02:20 PM PST 24
Peak memory 210592 kb
Host smart-1d4c68cf-9330-48b0-a29f-411eb056862c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2867108343 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_max_throughput_chk.2867108343
Directory /workspace/10.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/10.rom_ctrl_smoke.2165469690
Short name T238
Test name
Test status
Simulation time 2842448246 ps
CPU time 25.83 seconds
Started Feb 07 01:01:54 PM PST 24
Finished Feb 07 01:02:20 PM PST 24
Peak memory 212020 kb
Host smart-86dff830-bc4e-4bd0-b2eb-6e2828b7d7bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2165469690 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_smoke.2165469690
Directory /workspace/10.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/10.rom_ctrl_stress_all.3944533310
Short name T95
Test name
Test status
Simulation time 3220064988 ps
CPU time 16.65 seconds
Started Feb 07 01:02:03 PM PST 24
Finished Feb 07 01:02:21 PM PST 24
Peak memory 210452 kb
Host smart-6d8e756e-4587-420b-88b0-ee6613025879
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3944533310 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 10.rom_ctrl_stress_all.3944533310
Directory /workspace/10.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/10.rom_ctrl_stress_all_with_rand_reset.1157099158
Short name T168
Test name
Test status
Simulation time 43178795589 ps
CPU time 2889.76 seconds
Started Feb 07 01:02:06 PM PST 24
Finished Feb 07 01:50:20 PM PST 24
Peak memory 234364 kb
Host smart-6dc060db-74a1-40a2-b0d5-1fec5bdc9339
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1157099158 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_stress_all_with_rand_reset.1157099158
Directory /workspace/10.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/11.rom_ctrl_alert_test.3052170106
Short name T340
Test name
Test status
Simulation time 6390075256 ps
CPU time 13.69 seconds
Started Feb 07 01:02:02 PM PST 24
Finished Feb 07 01:02:17 PM PST 24
Peak memory 210472 kb
Host smart-bc03c747-b93c-4f63-8dee-e42ffff5c28f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3052170106 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_alert_test.3052170106
Directory /workspace/11.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/11.rom_ctrl_corrupt_sig_fatal_chk.3043850737
Short name T193
Test name
Test status
Simulation time 19640148732 ps
CPU time 188.82 seconds
Started Feb 07 01:02:04 PM PST 24
Finished Feb 07 01:05:14 PM PST 24
Peak memory 227376 kb
Host smart-0dc216d0-b017-4c7b-a8b8-83949a2b65c2
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3043850737 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_
corrupt_sig_fatal_chk.3043850737
Directory /workspace/11.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/11.rom_ctrl_kmac_err_chk.1116698824
Short name T205
Test name
Test status
Simulation time 1812514639 ps
CPU time 20.81 seconds
Started Feb 07 01:02:03 PM PST 24
Finished Feb 07 01:02:25 PM PST 24
Peak memory 210732 kb
Host smart-2635ea89-0abd-46a8-9af6-a59dec3bf086
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1116698824 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_kmac_err_chk.1116698824
Directory /workspace/11.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/11.rom_ctrl_max_throughput_chk.2439056732
Short name T219
Test name
Test status
Simulation time 1213759152 ps
CPU time 13.13 seconds
Started Feb 07 01:02:04 PM PST 24
Finished Feb 07 01:02:18 PM PST 24
Peak memory 210528 kb
Host smart-37c6e3fe-fc2e-4f13-a538-97373b675fa9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2439056732 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_max_throughput_chk.2439056732
Directory /workspace/11.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/11.rom_ctrl_smoke.1827367959
Short name T407
Test name
Test status
Simulation time 4066987369 ps
CPU time 33.43 seconds
Started Feb 07 01:02:04 PM PST 24
Finished Feb 07 01:02:38 PM PST 24
Peak memory 211964 kb
Host smart-dfed17eb-80e9-4bcf-a216-1fa6b9703c59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1827367959 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_smoke.1827367959
Directory /workspace/11.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/11.rom_ctrl_stress_all.2451988199
Short name T4
Test name
Test status
Simulation time 1248616053 ps
CPU time 16.52 seconds
Started Feb 07 01:02:02 PM PST 24
Finished Feb 07 01:02:20 PM PST 24
Peak memory 212656 kb
Host smart-bb6140e3-31a4-40a2-8fb3-6843820c7bde
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2451988199 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 11.rom_ctrl_stress_all.2451988199
Directory /workspace/11.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/12.rom_ctrl_alert_test.3083664586
Short name T251
Test name
Test status
Simulation time 2791940804 ps
CPU time 12.74 seconds
Started Feb 07 01:02:03 PM PST 24
Finished Feb 07 01:02:17 PM PST 24
Peak memory 210616 kb
Host smart-91c23035-978a-494d-a3d6-484b3ea1f74b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3083664586 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_alert_test.3083664586
Directory /workspace/12.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/12.rom_ctrl_corrupt_sig_fatal_chk.468887587
Short name T314
Test name
Test status
Simulation time 17112531478 ps
CPU time 219.12 seconds
Started Feb 07 01:02:05 PM PST 24
Finished Feb 07 01:05:45 PM PST 24
Peak memory 235992 kb
Host smart-d6210153-5779-43d7-b0c3-c3be3f834b1f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=468887587 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_c
orrupt_sig_fatal_chk.468887587
Directory /workspace/12.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/12.rom_ctrl_kmac_err_chk.3277144199
Short name T247
Test name
Test status
Simulation time 10081736208 ps
CPU time 25.44 seconds
Started Feb 07 01:02:05 PM PST 24
Finished Feb 07 01:02:31 PM PST 24
Peak memory 211096 kb
Host smart-f046062b-557a-4427-a2b6-e815b49d24d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3277144199 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_kmac_err_chk.3277144199
Directory /workspace/12.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/12.rom_ctrl_max_throughput_chk.1866738499
Short name T289
Test name
Test status
Simulation time 11922156741 ps
CPU time 10.42 seconds
Started Feb 07 01:02:06 PM PST 24
Finished Feb 07 01:02:20 PM PST 24
Peak memory 209976 kb
Host smart-891a57a6-0649-40c1-bb85-0798a734635f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1866738499 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_max_throughput_chk.1866738499
Directory /workspace/12.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/12.rom_ctrl_smoke.1697540882
Short name T352
Test name
Test status
Simulation time 2939695633 ps
CPU time 27.24 seconds
Started Feb 07 01:02:04 PM PST 24
Finished Feb 07 01:02:33 PM PST 24
Peak memory 211420 kb
Host smart-48e8cef1-bc37-4cc2-a728-2dcbf92ef40f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1697540882 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_smoke.1697540882
Directory /workspace/12.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/12.rom_ctrl_stress_all.3668917043
Short name T402
Test name
Test status
Simulation time 2870948850 ps
CPU time 40.23 seconds
Started Feb 07 01:02:05 PM PST 24
Finished Feb 07 01:02:46 PM PST 24
Peak memory 214624 kb
Host smart-24104692-cd4d-440e-8770-22990d2997b4
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3668917043 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 12.rom_ctrl_stress_all.3668917043
Directory /workspace/12.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/12.rom_ctrl_stress_all_with_rand_reset.4262762526
Short name T157
Test name
Test status
Simulation time 129387943944 ps
CPU time 4777.62 seconds
Started Feb 07 01:02:20 PM PST 24
Finished Feb 07 02:22:01 PM PST 24
Peak memory 259896 kb
Host smart-524929e8-8915-49cb-910f-356d168c35f6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4262762526 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_stress_all_with_rand_reset.4262762526
Directory /workspace/12.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/13.rom_ctrl_alert_test.3843892524
Short name T44
Test name
Test status
Simulation time 378283403 ps
CPU time 4.26 seconds
Started Feb 07 01:02:21 PM PST 24
Finished Feb 07 01:02:27 PM PST 24
Peak memory 210512 kb
Host smart-0da04711-741a-4f75-ba8a-dd9f67264e0f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3843892524 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_alert_test.3843892524
Directory /workspace/13.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/13.rom_ctrl_corrupt_sig_fatal_chk.3716162838
Short name T310
Test name
Test status
Simulation time 43261394149 ps
CPU time 398.24 seconds
Started Feb 07 01:02:24 PM PST 24
Finished Feb 07 01:09:04 PM PST 24
Peak memory 227884 kb
Host smart-af4a2730-b7ab-4b80-a126-c45006ce2004
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3716162838 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_
corrupt_sig_fatal_chk.3716162838
Directory /workspace/13.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/13.rom_ctrl_kmac_err_chk.2331821230
Short name T276
Test name
Test status
Simulation time 2938649361 ps
CPU time 27.6 seconds
Started Feb 07 01:02:22 PM PST 24
Finished Feb 07 01:02:51 PM PST 24
Peak memory 210488 kb
Host smart-dc9dd7d1-b5c1-40ca-b3b2-efc096dae3f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2331821230 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_kmac_err_chk.2331821230
Directory /workspace/13.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/13.rom_ctrl_max_throughput_chk.2423307244
Short name T174
Test name
Test status
Simulation time 1245588802 ps
CPU time 12.39 seconds
Started Feb 07 01:02:28 PM PST 24
Finished Feb 07 01:02:41 PM PST 24
Peak memory 210464 kb
Host smart-3b055e6d-d56b-4310-8189-6cc783f87e75
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2423307244 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_max_throughput_chk.2423307244
Directory /workspace/13.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/13.rom_ctrl_smoke.3711681620
Short name T216
Test name
Test status
Simulation time 794303959 ps
CPU time 14.59 seconds
Started Feb 07 01:02:18 PM PST 24
Finished Feb 07 01:02:37 PM PST 24
Peak memory 212372 kb
Host smart-53bb757c-3f1e-400d-a326-4d458864bede
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3711681620 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_smoke.3711681620
Directory /workspace/13.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/13.rom_ctrl_stress_all.131133248
Short name T262
Test name
Test status
Simulation time 3753852222 ps
CPU time 10.34 seconds
Started Feb 07 01:02:28 PM PST 24
Finished Feb 07 01:02:39 PM PST 24
Peak memory 211232 kb
Host smart-8f725b8c-80e9-4b52-9779-d448eaa27a30
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=131133248 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 13.rom_ctrl_stress_all.131133248
Directory /workspace/13.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/14.rom_ctrl_alert_test.509140827
Short name T299
Test name
Test status
Simulation time 3673262650 ps
CPU time 10.62 seconds
Started Feb 07 01:02:25 PM PST 24
Finished Feb 07 01:02:37 PM PST 24
Peak memory 210600 kb
Host smart-2427a7df-e21a-4b76-846a-016c4cb63bec
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=509140827 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_alert_test.509140827
Directory /workspace/14.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/14.rom_ctrl_kmac_err_chk.511813034
Short name T355
Test name
Test status
Simulation time 7534889144 ps
CPU time 26.06 seconds
Started Feb 07 01:02:24 PM PST 24
Finished Feb 07 01:02:52 PM PST 24
Peak memory 211472 kb
Host smart-89e9f1b6-c1c8-47f3-8e4f-fbfb75e61592
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=511813034 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_kmac_err_chk.511813034
Directory /workspace/14.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/14.rom_ctrl_max_throughput_chk.1314875957
Short name T373
Test name
Test status
Simulation time 2083152690 ps
CPU time 8.58 seconds
Started Feb 07 01:02:24 PM PST 24
Finished Feb 07 01:02:34 PM PST 24
Peak memory 210536 kb
Host smart-b4e24875-4916-452c-85ed-70b7a55d4b89
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1314875957 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_max_throughput_chk.1314875957
Directory /workspace/14.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/14.rom_ctrl_smoke.2085281619
Short name T245
Test name
Test status
Simulation time 16829720130 ps
CPU time 39.22 seconds
Started Feb 07 01:02:22 PM PST 24
Finished Feb 07 01:03:02 PM PST 24
Peak memory 213172 kb
Host smart-337e8e70-1820-41c1-9923-c6eb9a1e350e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2085281619 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_smoke.2085281619
Directory /workspace/14.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/14.rom_ctrl_stress_all.2062052711
Short name T386
Test name
Test status
Simulation time 65804249695 ps
CPU time 109.08 seconds
Started Feb 07 01:02:24 PM PST 24
Finished Feb 07 01:04:15 PM PST 24
Peak memory 218724 kb
Host smart-53a1c42c-303a-48f5-a230-69e64ffbc6e4
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2062052711 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 14.rom_ctrl_stress_all.2062052711
Directory /workspace/14.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/14.rom_ctrl_stress_all_with_rand_reset.432369072
Short name T371
Test name
Test status
Simulation time 158748681553 ps
CPU time 9559.86 seconds
Started Feb 07 01:02:20 PM PST 24
Finished Feb 07 03:41:43 PM PST 24
Peak memory 234840 kb
Host smart-6439bac5-e342-443e-b24c-aba6e99c2bdc
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=432369072 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_stress_all_with_rand_reset.432369072
Directory /workspace/14.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/15.rom_ctrl_alert_test.2428368447
Short name T94
Test name
Test status
Simulation time 261185061 ps
CPU time 5.26 seconds
Started Feb 07 01:02:21 PM PST 24
Finished Feb 07 01:02:28 PM PST 24
Peak memory 210492 kb
Host smart-f088c5fb-fab4-40a8-ba85-29a7cd378a59
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2428368447 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_alert_test.2428368447
Directory /workspace/15.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/15.rom_ctrl_corrupt_sig_fatal_chk.45537549
Short name T334
Test name
Test status
Simulation time 48917416299 ps
CPU time 188.39 seconds
Started Feb 07 01:02:28 PM PST 24
Finished Feb 07 01:05:37 PM PST 24
Peak memory 232044 kb
Host smart-d423de91-c11f-4710-bd02-0a18a43c0fff
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=45537549 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_
sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_co
rrupt_sig_fatal_chk.45537549
Directory /workspace/15.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/15.rom_ctrl_kmac_err_chk.2578457217
Short name T203
Test name
Test status
Simulation time 425542725 ps
CPU time 12.37 seconds
Started Feb 07 01:02:19 PM PST 24
Finished Feb 07 01:02:35 PM PST 24
Peak memory 210868 kb
Host smart-9db603ae-8740-46e6-8a87-a01c37757c9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2578457217 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_kmac_err_chk.2578457217
Directory /workspace/15.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/15.rom_ctrl_max_throughput_chk.2958410565
Short name T377
Test name
Test status
Simulation time 1278116057 ps
CPU time 12.06 seconds
Started Feb 07 01:02:24 PM PST 24
Finished Feb 07 01:02:38 PM PST 24
Peak memory 210544 kb
Host smart-0feb57b1-a85e-4c78-8874-ab22630fbe43
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2958410565 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_max_throughput_chk.2958410565
Directory /workspace/15.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/15.rom_ctrl_smoke.4241421026
Short name T267
Test name
Test status
Simulation time 11435827601 ps
CPU time 25.86 seconds
Started Feb 07 01:02:25 PM PST 24
Finished Feb 07 01:02:52 PM PST 24
Peak memory 213424 kb
Host smart-b65a9446-9b54-4585-baa5-f95f32788cbd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4241421026 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_smoke.4241421026
Directory /workspace/15.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/15.rom_ctrl_stress_all.4272776563
Short name T420
Test name
Test status
Simulation time 1646086742 ps
CPU time 19.03 seconds
Started Feb 07 01:02:19 PM PST 24
Finished Feb 07 01:02:42 PM PST 24
Peak memory 210824 kb
Host smart-e7967c1e-47ad-47e4-a92b-7ee31c3a172b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4272776563 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 15.rom_ctrl_stress_all.4272776563
Directory /workspace/15.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/15.rom_ctrl_stress_all_with_rand_reset.975136634
Short name T414
Test name
Test status
Simulation time 78278627899 ps
CPU time 2900.03 seconds
Started Feb 07 01:02:24 PM PST 24
Finished Feb 07 01:50:46 PM PST 24
Peak memory 244544 kb
Host smart-b818aafb-6dcb-4ec5-b6ed-20607bbdfaf2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=975136634 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_stress_all_with_rand_reset.975136634
Directory /workspace/15.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/16.rom_ctrl_alert_test.2191078802
Short name T246
Test name
Test status
Simulation time 9641766790 ps
CPU time 13.28 seconds
Started Feb 07 01:02:33 PM PST 24
Finished Feb 07 01:02:48 PM PST 24
Peak memory 210620 kb
Host smart-5f0b4653-776d-4aed-a6f9-3cb64e2a4e65
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2191078802 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_alert_test.2191078802
Directory /workspace/16.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/16.rom_ctrl_corrupt_sig_fatal_chk.1578981323
Short name T305
Test name
Test status
Simulation time 56775230477 ps
CPU time 224.05 seconds
Started Feb 07 01:02:20 PM PST 24
Finished Feb 07 01:06:07 PM PST 24
Peak memory 232024 kb
Host smart-db68bea9-3c18-4c92-89f3-0b181194dc5a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1578981323 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_
corrupt_sig_fatal_chk.1578981323
Directory /workspace/16.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/16.rom_ctrl_kmac_err_chk.454090588
Short name T167
Test name
Test status
Simulation time 6886535462 ps
CPU time 19.65 seconds
Started Feb 07 01:02:35 PM PST 24
Finished Feb 07 01:02:55 PM PST 24
Peak memory 211356 kb
Host smart-10fb6769-88fa-45e6-9dac-fd10ade675c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=454090588 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_kmac_err_chk.454090588
Directory /workspace/16.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/16.rom_ctrl_max_throughput_chk.917070309
Short name T159
Test name
Test status
Simulation time 574576491 ps
CPU time 9.06 seconds
Started Feb 07 01:02:19 PM PST 24
Finished Feb 07 01:02:32 PM PST 24
Peak memory 210560 kb
Host smart-f44ad11d-2b54-4076-9810-46d4abbaf0a8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=917070309 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_max_throughput_chk.917070309
Directory /workspace/16.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/16.rom_ctrl_smoke.63754751
Short name T196
Test name
Test status
Simulation time 177464067 ps
CPU time 9.69 seconds
Started Feb 07 01:02:25 PM PST 24
Finished Feb 07 01:02:36 PM PST 24
Peak memory 212404 kb
Host smart-d8fe3fe3-1d55-44ab-8895-7fef330e732f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=63754751 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_smoke.63754751
Directory /workspace/16.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/16.rom_ctrl_stress_all.2511230934
Short name T413
Test name
Test status
Simulation time 1047641083 ps
CPU time 24.92 seconds
Started Feb 07 01:02:25 PM PST 24
Finished Feb 07 01:02:51 PM PST 24
Peak memory 213812 kb
Host smart-85f159bf-545c-4d92-bc4c-16d8583ff916
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2511230934 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 16.rom_ctrl_stress_all.2511230934
Directory /workspace/16.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/17.rom_ctrl_alert_test.3300268384
Short name T230
Test name
Test status
Simulation time 299350198 ps
CPU time 6.44 seconds
Started Feb 07 01:02:36 PM PST 24
Finished Feb 07 01:02:45 PM PST 24
Peak memory 210536 kb
Host smart-cca6f73e-00d4-44b4-9c02-3a1c063685f3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3300268384 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_alert_test.3300268384
Directory /workspace/17.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/17.rom_ctrl_corrupt_sig_fatal_chk.2083467370
Short name T201
Test name
Test status
Simulation time 114823953549 ps
CPU time 300.97 seconds
Started Feb 07 01:02:36 PM PST 24
Finished Feb 07 01:07:38 PM PST 24
Peak memory 233076 kb
Host smart-7fa9e2c1-b7e6-4dc1-a761-6d98a527bf09
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2083467370 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_
corrupt_sig_fatal_chk.2083467370
Directory /workspace/17.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/17.rom_ctrl_kmac_err_chk.2432694828
Short name T370
Test name
Test status
Simulation time 4191171825 ps
CPU time 33.17 seconds
Started Feb 07 01:02:34 PM PST 24
Finished Feb 07 01:03:08 PM PST 24
Peak memory 210864 kb
Host smart-706913b9-64a4-4917-889c-147c87326476
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2432694828 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_kmac_err_chk.2432694828
Directory /workspace/17.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/17.rom_ctrl_max_throughput_chk.2426080582
Short name T217
Test name
Test status
Simulation time 4123999249 ps
CPU time 9.53 seconds
Started Feb 07 01:02:35 PM PST 24
Finished Feb 07 01:02:45 PM PST 24
Peak memory 210588 kb
Host smart-3da20c3e-a886-4e6e-8bad-3ae3d728264d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2426080582 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_max_throughput_chk.2426080582
Directory /workspace/17.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/17.rom_ctrl_smoke.2153431012
Short name T327
Test name
Test status
Simulation time 711083925 ps
CPU time 10.19 seconds
Started Feb 07 01:02:39 PM PST 24
Finished Feb 07 01:02:51 PM PST 24
Peak memory 212124 kb
Host smart-ef7d7392-cf97-4e94-89aa-a239e631b5f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2153431012 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_smoke.2153431012
Directory /workspace/17.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/17.rom_ctrl_stress_all.1819931484
Short name T188
Test name
Test status
Simulation time 2192793460 ps
CPU time 18.13 seconds
Started Feb 07 01:02:35 PM PST 24
Finished Feb 07 01:02:54 PM PST 24
Peak memory 210488 kb
Host smart-a221619c-ce58-4635-b82a-eb6ad73451d6
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1819931484 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 17.rom_ctrl_stress_all.1819931484
Directory /workspace/17.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/18.rom_ctrl_alert_test.872749750
Short name T186
Test name
Test status
Simulation time 16938963824 ps
CPU time 16.54 seconds
Started Feb 07 01:02:48 PM PST 24
Finished Feb 07 01:03:07 PM PST 24
Peak memory 210556 kb
Host smart-6d2bbcaf-6ab6-4672-b6eb-0da7f0263b93
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=872749750 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_alert_test.872749750
Directory /workspace/18.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/18.rom_ctrl_corrupt_sig_fatal_chk.3059940868
Short name T171
Test name
Test status
Simulation time 114732030665 ps
CPU time 317.64 seconds
Started Feb 07 01:02:37 PM PST 24
Finished Feb 07 01:07:58 PM PST 24
Peak memory 237112 kb
Host smart-73232c2c-b8ac-4ef8-8dce-719c97c0f087
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3059940868 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_
corrupt_sig_fatal_chk.3059940868
Directory /workspace/18.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/18.rom_ctrl_kmac_err_chk.808792674
Short name T284
Test name
Test status
Simulation time 3745757097 ps
CPU time 15.56 seconds
Started Feb 07 01:02:36 PM PST 24
Finished Feb 07 01:02:52 PM PST 24
Peak memory 210976 kb
Host smart-a730e9c6-b940-4575-a5a5-ca872316be50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=808792674 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_kmac_err_chk.808792674
Directory /workspace/18.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/18.rom_ctrl_max_throughput_chk.2425970147
Short name T7
Test name
Test status
Simulation time 786607148 ps
CPU time 10.34 seconds
Started Feb 07 01:02:40 PM PST 24
Finished Feb 07 01:02:55 PM PST 24
Peak memory 210408 kb
Host smart-ef10910c-616b-494b-bb25-950fdaec4ed3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2425970147 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_max_throughput_chk.2425970147
Directory /workspace/18.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/18.rom_ctrl_smoke.1080384401
Short name T374
Test name
Test status
Simulation time 3325414268 ps
CPU time 28.88 seconds
Started Feb 07 01:02:37 PM PST 24
Finished Feb 07 01:03:09 PM PST 24
Peak memory 212280 kb
Host smart-5a28f29f-9603-49b4-a777-38f0c8560992
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1080384401 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_smoke.1080384401
Directory /workspace/18.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/18.rom_ctrl_stress_all.3236395334
Short name T273
Test name
Test status
Simulation time 11609668552 ps
CPU time 60.99 seconds
Started Feb 07 01:02:37 PM PST 24
Finished Feb 07 01:03:41 PM PST 24
Peak memory 212636 kb
Host smart-e549fd51-aa88-4e72-902c-c87294ba79f0
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3236395334 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 18.rom_ctrl_stress_all.3236395334
Directory /workspace/18.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/18.rom_ctrl_stress_all_with_rand_reset.2322383520
Short name T302
Test name
Test status
Simulation time 47210103790 ps
CPU time 914.33 seconds
Started Feb 07 01:02:48 PM PST 24
Finished Feb 07 01:18:05 PM PST 24
Peak memory 234472 kb
Host smart-fe6b3f75-a7a1-48cb-95fe-03baf8bce038
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2322383520 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_stress_all_with_rand_reset.2322383520
Directory /workspace/18.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/19.rom_ctrl_alert_test.3807430517
Short name T394
Test name
Test status
Simulation time 168317608 ps
CPU time 4.27 seconds
Started Feb 07 01:02:45 PM PST 24
Finished Feb 07 01:02:53 PM PST 24
Peak memory 210504 kb
Host smart-f9561ec8-c5fa-4717-a26d-459dbe47dba6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3807430517 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_alert_test.3807430517
Directory /workspace/19.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/19.rom_ctrl_corrupt_sig_fatal_chk.721737826
Short name T379
Test name
Test status
Simulation time 17650743526 ps
CPU time 190.76 seconds
Started Feb 07 01:02:45 PM PST 24
Finished Feb 07 01:05:59 PM PST 24
Peak memory 237104 kb
Host smart-18c85306-8a26-4154-a0cb-4982406d5276
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=721737826 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_c
orrupt_sig_fatal_chk.721737826
Directory /workspace/19.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/19.rom_ctrl_kmac_err_chk.290895657
Short name T214
Test name
Test status
Simulation time 7242680490 ps
CPU time 20.53 seconds
Started Feb 07 01:02:48 PM PST 24
Finished Feb 07 01:03:11 PM PST 24
Peak memory 211424 kb
Host smart-9f6ad55e-ad9b-46bf-a448-c1e8fd148c11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=290895657 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_kmac_err_chk.290895657
Directory /workspace/19.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/19.rom_ctrl_max_throughput_chk.2041558378
Short name T211
Test name
Test status
Simulation time 1319044864 ps
CPU time 13.5 seconds
Started Feb 07 01:02:44 PM PST 24
Finished Feb 07 01:02:59 PM PST 24
Peak memory 210532 kb
Host smart-4e863f40-7d35-4868-8c16-96a7dc0a6a10
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2041558378 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_max_throughput_chk.2041558378
Directory /workspace/19.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/19.rom_ctrl_smoke.3985151720
Short name T213
Test name
Test status
Simulation time 3310258351 ps
CPU time 33.12 seconds
Started Feb 07 01:02:44 PM PST 24
Finished Feb 07 01:03:19 PM PST 24
Peak memory 212492 kb
Host smart-4b8f0358-4faa-4b01-864f-fe5c431834e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3985151720 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_smoke.3985151720
Directory /workspace/19.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/19.rom_ctrl_stress_all.2602910089
Short name T185
Test name
Test status
Simulation time 14751462135 ps
CPU time 72.35 seconds
Started Feb 07 01:02:45 PM PST 24
Finished Feb 07 01:04:01 PM PST 24
Peak memory 215272 kb
Host smart-a000954b-2e1f-4d1d-b47e-81062764a496
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2602910089 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 19.rom_ctrl_stress_all.2602910089
Directory /workspace/19.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/19.rom_ctrl_stress_all_with_rand_reset.3586114122
Short name T292
Test name
Test status
Simulation time 15999738286 ps
CPU time 900.75 seconds
Started Feb 07 01:02:46 PM PST 24
Finished Feb 07 01:17:50 PM PST 24
Peak memory 230908 kb
Host smart-78331f2e-4158-4e27-baa8-da6218aca368
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3586114122 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_stress_all_with_rand_reset.3586114122
Directory /workspace/19.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.rom_ctrl_alert_test.476356753
Short name T311
Test name
Test status
Simulation time 3346262693 ps
CPU time 14.22 seconds
Started Feb 07 01:01:24 PM PST 24
Finished Feb 07 01:01:39 PM PST 24
Peak memory 210560 kb
Host smart-b6ac5a20-6350-4906-a152-273413edbeca
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=476356753 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_alert_test.476356753
Directory /workspace/2.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/2.rom_ctrl_corrupt_sig_fatal_chk.2540939390
Short name T237
Test name
Test status
Simulation time 4605377264 ps
CPU time 103.86 seconds
Started Feb 07 01:01:32 PM PST 24
Finished Feb 07 01:03:17 PM PST 24
Peak memory 224200 kb
Host smart-c7df15c5-3fbc-4061-9cdd-e2c198b9d765
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2540939390 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_c
orrupt_sig_fatal_chk.2540939390
Directory /workspace/2.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/2.rom_ctrl_kmac_err_chk.950801443
Short name T6
Test name
Test status
Simulation time 4111529014 ps
CPU time 32.66 seconds
Started Feb 07 01:01:30 PM PST 24
Finished Feb 07 01:02:03 PM PST 24
Peak memory 210684 kb
Host smart-814ac80a-03ab-4b35-b4c6-634c6f9c11e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=950801443 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_kmac_err_chk.950801443
Directory /workspace/2.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/2.rom_ctrl_max_throughput_chk.3871987711
Short name T322
Test name
Test status
Simulation time 2382428949 ps
CPU time 12.46 seconds
Started Feb 07 01:01:26 PM PST 24
Finished Feb 07 01:01:39 PM PST 24
Peak memory 210528 kb
Host smart-9f3579c3-e218-49ce-b239-7b8aff3ffc64
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3871987711 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_max_throughput_chk.3871987711
Directory /workspace/2.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/2.rom_ctrl_sec_cm.2686974500
Short name T40
Test name
Test status
Simulation time 334683520 ps
CPU time 54.43 seconds
Started Feb 07 01:01:25 PM PST 24
Finished Feb 07 01:02:20 PM PST 24
Peak memory 235396 kb
Host smart-4990aa1e-e40c-412b-a113-dc9a4a85cce7
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2686974500 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_sec_cm.2686974500
Directory /workspace/2.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/2.rom_ctrl_smoke.1710769267
Short name T315
Test name
Test status
Simulation time 1211442354 ps
CPU time 15.67 seconds
Started Feb 07 01:01:28 PM PST 24
Finished Feb 07 01:01:44 PM PST 24
Peak memory 211988 kb
Host smart-a804ac97-b655-40f3-b45a-7b91b720bb48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1710769267 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_smoke.1710769267
Directory /workspace/2.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/2.rom_ctrl_stress_all.1623689707
Short name T172
Test name
Test status
Simulation time 5239753406 ps
CPU time 50.41 seconds
Started Feb 07 01:01:27 PM PST 24
Finished Feb 07 01:02:18 PM PST 24
Peak memory 214168 kb
Host smart-28317c2f-e756-490b-bc43-d654ce1f19dc
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1623689707 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 2.rom_ctrl_stress_all.1623689707
Directory /workspace/2.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/2.rom_ctrl_stress_all_with_rand_reset.1122049919
Short name T231
Test name
Test status
Simulation time 45765361487 ps
CPU time 1163.53 seconds
Started Feb 07 01:01:19 PM PST 24
Finished Feb 07 01:20:43 PM PST 24
Peak memory 235308 kb
Host smart-1a3277c6-c3b6-42c8-be2a-c4c08d24ca08
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1122049919 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_stress_all_with_rand_reset.1122049919
Directory /workspace/2.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.rom_ctrl_alert_test.326373357
Short name T354
Test name
Test status
Simulation time 5094374092 ps
CPU time 12.31 seconds
Started Feb 07 01:02:49 PM PST 24
Finished Feb 07 01:03:03 PM PST 24
Peak memory 210568 kb
Host smart-fc3bfb44-de73-4d85-aefe-58c186842114
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=326373357 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_alert_test.326373357
Directory /workspace/20.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/20.rom_ctrl_corrupt_sig_fatal_chk.1460924094
Short name T365
Test name
Test status
Simulation time 3504392216 ps
CPU time 102.66 seconds
Started Feb 07 01:02:47 PM PST 24
Finished Feb 07 01:04:33 PM PST 24
Peak memory 237144 kb
Host smart-dfa9e1c5-9279-4007-9b6d-10b36e913ec7
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1460924094 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_
corrupt_sig_fatal_chk.1460924094
Directory /workspace/20.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/20.rom_ctrl_kmac_err_chk.3930233876
Short name T400
Test name
Test status
Simulation time 2996776214 ps
CPU time 27.04 seconds
Started Feb 07 01:02:49 PM PST 24
Finished Feb 07 01:03:17 PM PST 24
Peak memory 210864 kb
Host smart-2cd53d1b-b7bc-4dca-aff1-35e1c28f8193
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3930233876 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_kmac_err_chk.3930233876
Directory /workspace/20.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/20.rom_ctrl_max_throughput_chk.3388496959
Short name T96
Test name
Test status
Simulation time 101158764 ps
CPU time 5.58 seconds
Started Feb 07 01:02:46 PM PST 24
Finished Feb 07 01:02:55 PM PST 24
Peak memory 210464 kb
Host smart-6ab98a6b-9371-4957-9213-d86bd727812a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3388496959 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_max_throughput_chk.3388496959
Directory /workspace/20.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/20.rom_ctrl_smoke.3934508609
Short name T149
Test name
Test status
Simulation time 2573011747 ps
CPU time 33.32 seconds
Started Feb 07 01:02:50 PM PST 24
Finished Feb 07 01:03:24 PM PST 24
Peak memory 212500 kb
Host smart-4f3c5a19-fd49-4e53-b2bd-392a9da97eeb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3934508609 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_smoke.3934508609
Directory /workspace/20.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/20.rom_ctrl_stress_all.910654664
Short name T288
Test name
Test status
Simulation time 2342974347 ps
CPU time 14.17 seconds
Started Feb 07 01:02:49 PM PST 24
Finished Feb 07 01:03:04 PM PST 24
Peak memory 210564 kb
Host smart-b20fb542-dc2a-4c8b-bca7-1114f3779cc5
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=910654664 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 20.rom_ctrl_stress_all.910654664
Directory /workspace/20.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/21.rom_ctrl_alert_test.2989676380
Short name T224
Test name
Test status
Simulation time 8468065071 ps
CPU time 17.66 seconds
Started Feb 07 01:02:48 PM PST 24
Finished Feb 07 01:03:08 PM PST 24
Peak memory 210524 kb
Host smart-cf3ab58a-2a98-4f25-b250-c4604118d8eb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2989676380 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_alert_test.2989676380
Directory /workspace/21.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/21.rom_ctrl_corrupt_sig_fatal_chk.1774737603
Short name T266
Test name
Test status
Simulation time 8664379543 ps
CPU time 122.67 seconds
Started Feb 07 01:02:46 PM PST 24
Finished Feb 07 01:04:52 PM PST 24
Peak memory 236908 kb
Host smart-a61f9459-0033-426a-a1f5-2d681ae6a3d8
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1774737603 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_
corrupt_sig_fatal_chk.1774737603
Directory /workspace/21.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/21.rom_ctrl_kmac_err_chk.1586270963
Short name T99
Test name
Test status
Simulation time 1273686193 ps
CPU time 17.8 seconds
Started Feb 07 01:02:48 PM PST 24
Finished Feb 07 01:03:08 PM PST 24
Peak memory 210776 kb
Host smart-b0b4e3e9-0b44-44b8-b36b-13f75e6eeb9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1586270963 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_kmac_err_chk.1586270963
Directory /workspace/21.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/21.rom_ctrl_max_throughput_chk.3887738928
Short name T189
Test name
Test status
Simulation time 1223968719 ps
CPU time 12.28 seconds
Started Feb 07 01:02:44 PM PST 24
Finished Feb 07 01:02:58 PM PST 24
Peak memory 210524 kb
Host smart-b06a44d2-05cc-4a7b-bdba-7c3dc3bf596d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3887738928 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_max_throughput_chk.3887738928
Directory /workspace/21.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/21.rom_ctrl_smoke.4182712304
Short name T376
Test name
Test status
Simulation time 7506646251 ps
CPU time 19.99 seconds
Started Feb 07 01:02:48 PM PST 24
Finished Feb 07 01:03:10 PM PST 24
Peak memory 212960 kb
Host smart-883d2c59-d01a-427a-9aa2-355af3338502
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4182712304 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_smoke.4182712304
Directory /workspace/21.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/21.rom_ctrl_stress_all.2660402537
Short name T223
Test name
Test status
Simulation time 210214654 ps
CPU time 12.33 seconds
Started Feb 07 01:02:43 PM PST 24
Finished Feb 07 01:02:58 PM PST 24
Peak memory 211232 kb
Host smart-95cda05d-2fda-47b8-9040-d4acd617f5a9
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2660402537 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 21.rom_ctrl_stress_all.2660402537
Directory /workspace/21.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/21.rom_ctrl_stress_all_with_rand_reset.4093878006
Short name T253
Test name
Test status
Simulation time 22843600341 ps
CPU time 356.66 seconds
Started Feb 07 01:02:46 PM PST 24
Finished Feb 07 01:08:46 PM PST 24
Peak memory 219976 kb
Host smart-2c3c9c2b-5fee-485d-b9c9-7ec2a6e08eab
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4093878006 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_stress_all_with_rand_reset.4093878006
Directory /workspace/21.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/22.rom_ctrl_alert_test.2158440057
Short name T234
Test name
Test status
Simulation time 8187442046 ps
CPU time 12.17 seconds
Started Feb 07 01:02:45 PM PST 24
Finished Feb 07 01:03:01 PM PST 24
Peak memory 210472 kb
Host smart-20e7a214-93d6-4c19-b9f0-c28c63cefc30
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2158440057 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_alert_test.2158440057
Directory /workspace/22.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/22.rom_ctrl_corrupt_sig_fatal_chk.1242528243
Short name T227
Test name
Test status
Simulation time 3185631876 ps
CPU time 94.12 seconds
Started Feb 07 01:02:47 PM PST 24
Finished Feb 07 01:04:24 PM PST 24
Peak memory 237144 kb
Host smart-365a14e4-193e-4dce-b37b-1d39304d9a75
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1242528243 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_
corrupt_sig_fatal_chk.1242528243
Directory /workspace/22.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/22.rom_ctrl_max_throughput_chk.1441772749
Short name T324
Test name
Test status
Simulation time 8464755318 ps
CPU time 17.3 seconds
Started Feb 07 01:02:45 PM PST 24
Finished Feb 07 01:03:06 PM PST 24
Peak memory 210524 kb
Host smart-048fe8aa-4c0d-4136-b340-cf90dd0a0231
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1441772749 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_max_throughput_chk.1441772749
Directory /workspace/22.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/22.rom_ctrl_smoke.3532467956
Short name T297
Test name
Test status
Simulation time 1552255380 ps
CPU time 18.78 seconds
Started Feb 07 01:02:47 PM PST 24
Finished Feb 07 01:03:09 PM PST 24
Peak memory 212408 kb
Host smart-ab34863a-7fa4-4146-83d9-2b86bb82aca6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3532467956 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_smoke.3532467956
Directory /workspace/22.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/22.rom_ctrl_stress_all.3815558264
Short name T319
Test name
Test status
Simulation time 15464313052 ps
CPU time 44.56 seconds
Started Feb 07 01:02:47 PM PST 24
Finished Feb 07 01:03:34 PM PST 24
Peak memory 212968 kb
Host smart-be1c0f30-db8e-4f97-94ac-ffe333c64582
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3815558264 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 22.rom_ctrl_stress_all.3815558264
Directory /workspace/22.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/23.rom_ctrl_alert_test.3602324305
Short name T256
Test name
Test status
Simulation time 2687588083 ps
CPU time 12.33 seconds
Started Feb 07 01:03:09 PM PST 24
Finished Feb 07 01:03:22 PM PST 24
Peak memory 210620 kb
Host smart-5bc3fd30-7fc9-4170-a5e4-801e1bad4f3e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3602324305 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_alert_test.3602324305
Directory /workspace/23.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/23.rom_ctrl_corrupt_sig_fatal_chk.4114890518
Short name T384
Test name
Test status
Simulation time 41656268222 ps
CPU time 190.3 seconds
Started Feb 07 01:03:06 PM PST 24
Finished Feb 07 01:06:17 PM PST 24
Peak memory 211812 kb
Host smart-cb4b450c-cfb3-408c-8248-3bafdcc77aca
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4114890518 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_
corrupt_sig_fatal_chk.4114890518
Directory /workspace/23.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/23.rom_ctrl_kmac_err_chk.3069687240
Short name T345
Test name
Test status
Simulation time 1713495303 ps
CPU time 19.7 seconds
Started Feb 07 01:03:08 PM PST 24
Finished Feb 07 01:03:28 PM PST 24
Peak memory 210572 kb
Host smart-a375113d-88ec-40a4-9fc2-2f04edb47ed3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3069687240 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_kmac_err_chk.3069687240
Directory /workspace/23.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/23.rom_ctrl_max_throughput_chk.812240663
Short name T17
Test name
Test status
Simulation time 101294468 ps
CPU time 5.82 seconds
Started Feb 07 01:03:06 PM PST 24
Finished Feb 07 01:03:13 PM PST 24
Peak memory 210536 kb
Host smart-77b9452b-c76e-43b8-807a-18a8cd86c653
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=812240663 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_max_throughput_chk.812240663
Directory /workspace/23.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/23.rom_ctrl_smoke.609388301
Short name T183
Test name
Test status
Simulation time 43642310587 ps
CPU time 37.07 seconds
Started Feb 07 01:02:46 PM PST 24
Finished Feb 07 01:03:27 PM PST 24
Peak memory 212832 kb
Host smart-2d086cff-538e-4af7-a1bc-dd500c1a3215
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=609388301 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_smoke.609388301
Directory /workspace/23.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/23.rom_ctrl_stress_all.718943820
Short name T51
Test name
Test status
Simulation time 2724532622 ps
CPU time 35.32 seconds
Started Feb 07 01:03:05 PM PST 24
Finished Feb 07 01:03:42 PM PST 24
Peak memory 212800 kb
Host smart-01b871fa-2981-45cf-a62c-10c3eef0e783
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=718943820 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 23.rom_ctrl_stress_all.718943820
Directory /workspace/23.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/23.rom_ctrl_stress_all_with_rand_reset.1447583090
Short name T156
Test name
Test status
Simulation time 34608625368 ps
CPU time 621.19 seconds
Started Feb 07 01:03:04 PM PST 24
Finished Feb 07 01:13:27 PM PST 24
Peak memory 227728 kb
Host smart-b671e4fa-5352-4318-84b7-78ade7044853
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1447583090 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_stress_all_with_rand_reset.1447583090
Directory /workspace/23.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/24.rom_ctrl_alert_test.3751919126
Short name T220
Test name
Test status
Simulation time 175195364 ps
CPU time 5.51 seconds
Started Feb 07 01:03:10 PM PST 24
Finished Feb 07 01:03:17 PM PST 24
Peak memory 210512 kb
Host smart-9c075abf-d4cc-4105-b29f-02201affde05
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3751919126 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_alert_test.3751919126
Directory /workspace/24.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/24.rom_ctrl_corrupt_sig_fatal_chk.1870622341
Short name T351
Test name
Test status
Simulation time 14418245574 ps
CPU time 230.1 seconds
Started Feb 07 01:03:05 PM PST 24
Finished Feb 07 01:06:56 PM PST 24
Peak memory 224028 kb
Host smart-1a251099-c00e-4a5c-8f55-3b39e7fd6d02
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1870622341 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_
corrupt_sig_fatal_chk.1870622341
Directory /workspace/24.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/24.rom_ctrl_kmac_err_chk.1388754844
Short name T264
Test name
Test status
Simulation time 5883996393 ps
CPU time 26.6 seconds
Started Feb 07 01:03:09 PM PST 24
Finished Feb 07 01:03:37 PM PST 24
Peak memory 211244 kb
Host smart-f657db78-ed58-43ba-9c76-6e6c5077d66a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1388754844 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_kmac_err_chk.1388754844
Directory /workspace/24.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/24.rom_ctrl_max_throughput_chk.3626039933
Short name T268
Test name
Test status
Simulation time 138407284 ps
CPU time 6.6 seconds
Started Feb 07 01:03:04 PM PST 24
Finished Feb 07 01:03:12 PM PST 24
Peak memory 210492 kb
Host smart-2f07635d-2233-4eca-88c9-60d62ddbcfa7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3626039933 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_max_throughput_chk.3626039933
Directory /workspace/24.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/24.rom_ctrl_smoke.3717098404
Short name T381
Test name
Test status
Simulation time 2964000809 ps
CPU time 10.24 seconds
Started Feb 07 01:03:06 PM PST 24
Finished Feb 07 01:03:18 PM PST 24
Peak memory 212212 kb
Host smart-f24c32de-2c4c-4218-a369-44715f0f2090
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3717098404 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_smoke.3717098404
Directory /workspace/24.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/24.rom_ctrl_stress_all.2927423390
Short name T164
Test name
Test status
Simulation time 4949321142 ps
CPU time 65.8 seconds
Started Feb 07 01:03:04 PM PST 24
Finished Feb 07 01:04:11 PM PST 24
Peak memory 215324 kb
Host smart-f3688d7e-0629-42a9-a89c-d397058fa33e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2927423390 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 24.rom_ctrl_stress_all.2927423390
Directory /workspace/24.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/24.rom_ctrl_stress_all_with_rand_reset.2895260719
Short name T382
Test name
Test status
Simulation time 150762858826 ps
CPU time 1663.03 seconds
Started Feb 07 01:03:10 PM PST 24
Finished Feb 07 01:30:54 PM PST 24
Peak memory 235228 kb
Host smart-8e4bdea3-b9ca-4c75-9f32-475bc6ea74b5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2895260719 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_stress_all_with_rand_reset.2895260719
Directory /workspace/24.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/25.rom_ctrl_alert_test.212639383
Short name T347
Test name
Test status
Simulation time 6570362994 ps
CPU time 10.37 seconds
Started Feb 07 01:03:10 PM PST 24
Finished Feb 07 01:03:22 PM PST 24
Peak memory 210560 kb
Host smart-5ac74b00-43a8-4173-85f1-6f07bdd9ad91
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=212639383 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_alert_test.212639383
Directory /workspace/25.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/25.rom_ctrl_corrupt_sig_fatal_chk.3049937583
Short name T250
Test name
Test status
Simulation time 6487840981 ps
CPU time 102.59 seconds
Started Feb 07 01:03:05 PM PST 24
Finished Feb 07 01:04:49 PM PST 24
Peak memory 227840 kb
Host smart-658046a1-0a8c-4122-96f9-f3ce468a4a2a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3049937583 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_
corrupt_sig_fatal_chk.3049937583
Directory /workspace/25.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/25.rom_ctrl_kmac_err_chk.1470915979
Short name T312
Test name
Test status
Simulation time 3181481493 ps
CPU time 29.04 seconds
Started Feb 07 01:03:06 PM PST 24
Finished Feb 07 01:03:36 PM PST 24
Peak memory 210740 kb
Host smart-5cea1058-8237-40a6-8d90-e116975385cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1470915979 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_kmac_err_chk.1470915979
Directory /workspace/25.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/25.rom_ctrl_max_throughput_chk.1104652324
Short name T261
Test name
Test status
Simulation time 446755371 ps
CPU time 5.7 seconds
Started Feb 07 01:03:03 PM PST 24
Finished Feb 07 01:03:10 PM PST 24
Peak memory 210528 kb
Host smart-97dacb86-89be-4fe0-a93e-1b9afa4e6499
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1104652324 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_max_throughput_chk.1104652324
Directory /workspace/25.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/25.rom_ctrl_smoke.3528109194
Short name T241
Test name
Test status
Simulation time 6365828291 ps
CPU time 31.64 seconds
Started Feb 07 01:03:07 PM PST 24
Finished Feb 07 01:03:39 PM PST 24
Peak memory 213176 kb
Host smart-4ca0b49d-2724-46ec-933f-d3c73be8bd87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3528109194 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_smoke.3528109194
Directory /workspace/25.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/25.rom_ctrl_stress_all.902955576
Short name T152
Test name
Test status
Simulation time 4898926926 ps
CPU time 47.21 seconds
Started Feb 07 01:03:05 PM PST 24
Finished Feb 07 01:03:54 PM PST 24
Peak memory 216220 kb
Host smart-1f8bc75a-f9af-4b0e-80df-9ef0a054513b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=902955576 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 25.rom_ctrl_stress_all.902955576
Directory /workspace/25.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/26.rom_ctrl_alert_test.3370017784
Short name T409
Test name
Test status
Simulation time 28506986265 ps
CPU time 16.1 seconds
Started Feb 07 01:03:08 PM PST 24
Finished Feb 07 01:03:25 PM PST 24
Peak memory 210564 kb
Host smart-77976c28-a808-4315-bedd-8ae966502e2a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3370017784 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_alert_test.3370017784
Directory /workspace/26.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/26.rom_ctrl_corrupt_sig_fatal_chk.36814990
Short name T372
Test name
Test status
Simulation time 43984832095 ps
CPU time 288.93 seconds
Started Feb 07 01:03:04 PM PST 24
Finished Feb 07 01:07:54 PM PST 24
Peak memory 211820 kb
Host smart-96a6c629-303e-466a-9455-3d822903f10d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36814990 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_
sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_co
rrupt_sig_fatal_chk.36814990
Directory /workspace/26.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/26.rom_ctrl_kmac_err_chk.4284878400
Short name T177
Test name
Test status
Simulation time 2406656969 ps
CPU time 13.85 seconds
Started Feb 07 01:03:01 PM PST 24
Finished Feb 07 01:03:17 PM PST 24
Peak memory 210684 kb
Host smart-f744c833-b1fd-4167-9b45-a4dc425f17eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4284878400 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_kmac_err_chk.4284878400
Directory /workspace/26.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/26.rom_ctrl_max_throughput_chk.212191960
Short name T263
Test name
Test status
Simulation time 6753016035 ps
CPU time 9.03 seconds
Started Feb 07 01:03:08 PM PST 24
Finished Feb 07 01:03:18 PM PST 24
Peak memory 210592 kb
Host smart-e82b8173-1603-4100-b508-44daa0be05a6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=212191960 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_max_throughput_chk.212191960
Directory /workspace/26.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/26.rom_ctrl_smoke.2526794041
Short name T318
Test name
Test status
Simulation time 370769233 ps
CPU time 10.3 seconds
Started Feb 07 01:03:09 PM PST 24
Finished Feb 07 01:03:20 PM PST 24
Peak memory 212068 kb
Host smart-7e5c21d9-45c7-4b34-9bea-64fa35d52844
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2526794041 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_smoke.2526794041
Directory /workspace/26.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/26.rom_ctrl_stress_all.2319369849
Short name T249
Test name
Test status
Simulation time 2045135650 ps
CPU time 15.4 seconds
Started Feb 07 01:03:01 PM PST 24
Finished Feb 07 01:03:19 PM PST 24
Peak memory 213408 kb
Host smart-93b47642-648d-41d6-80cb-0ef1ae549436
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2319369849 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 26.rom_ctrl_stress_all.2319369849
Directory /workspace/26.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/26.rom_ctrl_stress_all_with_rand_reset.713576848
Short name T390
Test name
Test status
Simulation time 40494882688 ps
CPU time 1565.08 seconds
Started Feb 07 01:03:04 PM PST 24
Finished Feb 07 01:29:11 PM PST 24
Peak memory 231964 kb
Host smart-8145f182-4ce7-45e6-8962-29fe11241b34
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=713576848 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_stress_all_with_rand_reset.713576848
Directory /workspace/26.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/27.rom_ctrl_alert_test.757492146
Short name T417
Test name
Test status
Simulation time 1927758263 ps
CPU time 15.27 seconds
Started Feb 07 01:03:14 PM PST 24
Finished Feb 07 01:03:30 PM PST 24
Peak memory 210404 kb
Host smart-7331580e-42d9-4cb6-9e39-979832097322
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=757492146 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_alert_test.757492146
Directory /workspace/27.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/27.rom_ctrl_corrupt_sig_fatal_chk.1661477325
Short name T182
Test name
Test status
Simulation time 2515472443 ps
CPU time 88.66 seconds
Started Feb 07 01:03:24 PM PST 24
Finished Feb 07 01:04:53 PM PST 24
Peak memory 223916 kb
Host smart-395ba4e7-d0fb-44f5-9d99-28a7478c2ac6
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1661477325 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_
corrupt_sig_fatal_chk.1661477325
Directory /workspace/27.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/27.rom_ctrl_kmac_err_chk.243971913
Short name T100
Test name
Test status
Simulation time 16028195160 ps
CPU time 33.8 seconds
Started Feb 07 01:03:10 PM PST 24
Finished Feb 07 01:03:45 PM PST 24
Peak memory 210984 kb
Host smart-0033ac09-cd99-4c26-932a-2953bc6be038
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=243971913 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_kmac_err_chk.243971913
Directory /workspace/27.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/27.rom_ctrl_max_throughput_chk.1259302302
Short name T15
Test name
Test status
Simulation time 11185051139 ps
CPU time 17.37 seconds
Started Feb 07 01:03:15 PM PST 24
Finished Feb 07 01:03:33 PM PST 24
Peak memory 218748 kb
Host smart-5d1a3034-9efa-4a60-8644-994559af248b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1259302302 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_max_throughput_chk.1259302302
Directory /workspace/27.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/27.rom_ctrl_smoke.3683618998
Short name T280
Test name
Test status
Simulation time 1061080637 ps
CPU time 13.93 seconds
Started Feb 07 01:03:16 PM PST 24
Finished Feb 07 01:03:31 PM PST 24
Peak memory 212332 kb
Host smart-c4b75550-f397-47c8-905a-33ac0e765734
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3683618998 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_smoke.3683618998
Directory /workspace/27.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/27.rom_ctrl_stress_all.2927615472
Short name T298
Test name
Test status
Simulation time 5457406046 ps
CPU time 57.94 seconds
Started Feb 07 01:03:16 PM PST 24
Finished Feb 07 01:04:15 PM PST 24
Peak memory 215708 kb
Host smart-b886533e-b968-465c-bd26-f5f4d4bc4e4d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2927615472 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 27.rom_ctrl_stress_all.2927615472
Directory /workspace/27.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/27.rom_ctrl_stress_all_with_rand_reset.106012929
Short name T194
Test name
Test status
Simulation time 45645160473 ps
CPU time 622.57 seconds
Started Feb 07 01:03:16 PM PST 24
Finished Feb 07 01:13:39 PM PST 24
Peak memory 228420 kb
Host smart-a6ed3c20-fc88-4727-8fdc-c6b0e97a192a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=106012929 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_stress_all_with_rand_reset.106012929
Directory /workspace/27.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/28.rom_ctrl_alert_test.2368373961
Short name T328
Test name
Test status
Simulation time 1388994047 ps
CPU time 12.18 seconds
Started Feb 07 01:03:24 PM PST 24
Finished Feb 07 01:03:37 PM PST 24
Peak memory 210408 kb
Host smart-f2d9352d-50e5-49c4-97a4-f6424d549e09
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2368373961 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_alert_test.2368373961
Directory /workspace/28.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/28.rom_ctrl_corrupt_sig_fatal_chk.2336809262
Short name T252
Test name
Test status
Simulation time 20813112760 ps
CPU time 202.76 seconds
Started Feb 07 01:03:15 PM PST 24
Finished Feb 07 01:06:39 PM PST 24
Peak memory 237012 kb
Host smart-fe72774f-464f-4858-9605-e505225be096
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2336809262 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_
corrupt_sig_fatal_chk.2336809262
Directory /workspace/28.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/28.rom_ctrl_kmac_err_chk.2702296208
Short name T52
Test name
Test status
Simulation time 508704320 ps
CPU time 10.89 seconds
Started Feb 07 01:03:14 PM PST 24
Finished Feb 07 01:03:25 PM PST 24
Peak memory 210824 kb
Host smart-78586c4c-4e88-4184-b356-1f84b2b2e1d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2702296208 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_kmac_err_chk.2702296208
Directory /workspace/28.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/28.rom_ctrl_max_throughput_chk.2532771804
Short name T180
Test name
Test status
Simulation time 1827569267 ps
CPU time 15.98 seconds
Started Feb 07 01:03:17 PM PST 24
Finished Feb 07 01:03:34 PM PST 24
Peak memory 210560 kb
Host smart-0d073ed7-d38e-4446-b241-3b39190d7b4e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2532771804 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_max_throughput_chk.2532771804
Directory /workspace/28.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/28.rom_ctrl_smoke.1041196889
Short name T357
Test name
Test status
Simulation time 13416798464 ps
CPU time 34.5 seconds
Started Feb 07 01:03:15 PM PST 24
Finished Feb 07 01:03:50 PM PST 24
Peak memory 212764 kb
Host smart-8bbf6acb-0156-4fda-be70-2892190e1f02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1041196889 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_smoke.1041196889
Directory /workspace/28.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/28.rom_ctrl_stress_all.4107103741
Short name T265
Test name
Test status
Simulation time 3425877856 ps
CPU time 32.76 seconds
Started Feb 07 01:03:11 PM PST 24
Finished Feb 07 01:03:45 PM PST 24
Peak memory 213796 kb
Host smart-b1526b4a-4683-446a-9a68-e0d70c038157
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4107103741 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 28.rom_ctrl_stress_all.4107103741
Directory /workspace/28.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/29.rom_ctrl_alert_test.2613703060
Short name T272
Test name
Test status
Simulation time 2699404162 ps
CPU time 8.19 seconds
Started Feb 07 01:03:11 PM PST 24
Finished Feb 07 01:03:20 PM PST 24
Peak memory 210596 kb
Host smart-8b1c88a7-7dbe-4009-8bc7-245a0c9c554f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2613703060 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_alert_test.2613703060
Directory /workspace/29.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/29.rom_ctrl_corrupt_sig_fatal_chk.1921052132
Short name T410
Test name
Test status
Simulation time 157026362692 ps
CPU time 417.84 seconds
Started Feb 07 01:03:24 PM PST 24
Finished Feb 07 01:10:23 PM PST 24
Peak memory 223872 kb
Host smart-dbf851f6-65dc-49ac-8a97-4fa76b20382f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1921052132 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_
corrupt_sig_fatal_chk.1921052132
Directory /workspace/29.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/29.rom_ctrl_kmac_err_chk.1931464174
Short name T321
Test name
Test status
Simulation time 2345363266 ps
CPU time 23.94 seconds
Started Feb 07 01:03:13 PM PST 24
Finished Feb 07 01:03:38 PM PST 24
Peak memory 210740 kb
Host smart-66bd032a-a3ba-46d4-a26d-c3cde56040ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1931464174 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_kmac_err_chk.1931464174
Directory /workspace/29.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/29.rom_ctrl_max_throughput_chk.2379047472
Short name T378
Test name
Test status
Simulation time 2742708794 ps
CPU time 13.04 seconds
Started Feb 07 01:03:12 PM PST 24
Finished Feb 07 01:03:26 PM PST 24
Peak memory 210596 kb
Host smart-5eab1725-c783-4e3b-a8c9-8c4bfcce4a4e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2379047472 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_max_throughput_chk.2379047472
Directory /workspace/29.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/29.rom_ctrl_smoke.2137108101
Short name T337
Test name
Test status
Simulation time 2652825345 ps
CPU time 24.58 seconds
Started Feb 07 01:03:13 PM PST 24
Finished Feb 07 01:03:39 PM PST 24
Peak memory 212860 kb
Host smart-e24815f1-d391-42fe-bce8-6d726b012ba7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2137108101 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_smoke.2137108101
Directory /workspace/29.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/29.rom_ctrl_stress_all.3988446027
Short name T285
Test name
Test status
Simulation time 54512405303 ps
CPU time 60.62 seconds
Started Feb 07 01:03:10 PM PST 24
Finished Feb 07 01:04:12 PM PST 24
Peak memory 216700 kb
Host smart-2671a729-15aa-472d-8e5e-f64112340d67
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3988446027 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 29.rom_ctrl_stress_all.3988446027
Directory /workspace/29.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/29.rom_ctrl_stress_all_with_rand_reset.3004061812
Short name T22
Test name
Test status
Simulation time 98760754561 ps
CPU time 7017.42 seconds
Started Feb 07 01:03:15 PM PST 24
Finished Feb 07 03:00:14 PM PST 24
Peak memory 236612 kb
Host smart-9e4e3934-0476-4552-95b8-32ffc067596d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3004061812 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_stress_all_with_rand_reset.3004061812
Directory /workspace/29.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.rom_ctrl_alert_test.3666240346
Short name T290
Test name
Test status
Simulation time 4273294378 ps
CPU time 16.9 seconds
Started Feb 07 01:01:40 PM PST 24
Finished Feb 07 01:01:58 PM PST 24
Peak memory 210520 kb
Host smart-7fbdf1a7-6ffc-4371-8c08-1980122f1cc1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3666240346 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_alert_test.3666240346
Directory /workspace/3.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/3.rom_ctrl_corrupt_sig_fatal_chk.3684097360
Short name T366
Test name
Test status
Simulation time 54034188699 ps
CPU time 214.9 seconds
Started Feb 07 01:01:22 PM PST 24
Finished Feb 07 01:04:57 PM PST 24
Peak memory 227460 kb
Host smart-bcc85b33-e699-48f2-91ba-1b7867a282fa
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3684097360 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_c
orrupt_sig_fatal_chk.3684097360
Directory /workspace/3.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/3.rom_ctrl_kmac_err_chk.2820856546
Short name T406
Test name
Test status
Simulation time 21695499232 ps
CPU time 28.52 seconds
Started Feb 07 01:01:20 PM PST 24
Finished Feb 07 01:01:49 PM PST 24
Peak memory 211056 kb
Host smart-ee505029-c066-4935-bb69-84201d9349b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2820856546 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_kmac_err_chk.2820856546
Directory /workspace/3.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/3.rom_ctrl_max_throughput_chk.3562188677
Short name T190
Test name
Test status
Simulation time 2023351348 ps
CPU time 8.58 seconds
Started Feb 07 01:01:16 PM PST 24
Finished Feb 07 01:01:25 PM PST 24
Peak memory 210576 kb
Host smart-abcacf88-cd1e-463a-a3d0-f1f4551f8c87
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3562188677 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_max_throughput_chk.3562188677
Directory /workspace/3.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/3.rom_ctrl_sec_cm.396766798
Short name T50
Test name
Test status
Simulation time 14144410322 ps
CPU time 63.9 seconds
Started Feb 07 01:01:17 PM PST 24
Finished Feb 07 01:02:21 PM PST 24
Peak memory 235728 kb
Host smart-a91eabe0-01b5-423e-b86f-32788a02d76a
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=396766798 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_sec_cm.396766798
Directory /workspace/3.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/3.rom_ctrl_smoke.2015096022
Short name T150
Test name
Test status
Simulation time 378927438 ps
CPU time 10.25 seconds
Started Feb 07 01:01:20 PM PST 24
Finished Feb 07 01:01:31 PM PST 24
Peak memory 212184 kb
Host smart-bd7ff83d-c997-4d20-8685-545bf9e52065
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2015096022 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_smoke.2015096022
Directory /workspace/3.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/3.rom_ctrl_stress_all.2319017137
Short name T356
Test name
Test status
Simulation time 21166540496 ps
CPU time 46.77 seconds
Started Feb 07 01:01:26 PM PST 24
Finished Feb 07 01:02:13 PM PST 24
Peak memory 212724 kb
Host smart-2ba23df2-b59c-4936-b518-8e212aba4042
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2319017137 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 3.rom_ctrl_stress_all.2319017137
Directory /workspace/3.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/3.rom_ctrl_stress_all_with_rand_reset.1665541985
Short name T275
Test name
Test status
Simulation time 153336057779 ps
CPU time 2880.05 seconds
Started Feb 07 01:01:29 PM PST 24
Finished Feb 07 01:49:30 PM PST 24
Peak memory 245844 kb
Host smart-15e1d385-5d92-4121-af3d-a9e9a9011b73
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1665541985 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_stress_all_with_rand_reset.1665541985
Directory /workspace/3.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.rom_ctrl_alert_test.2920508300
Short name T169
Test name
Test status
Simulation time 4061338732 ps
CPU time 14.96 seconds
Started Feb 07 01:03:30 PM PST 24
Finished Feb 07 01:03:46 PM PST 24
Peak memory 210656 kb
Host smart-ce86288d-9065-47c7-ad48-3860fe33c00f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2920508300 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_alert_test.2920508300
Directory /workspace/30.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/30.rom_ctrl_corrupt_sig_fatal_chk.875402224
Short name T28
Test name
Test status
Simulation time 15850373616 ps
CPU time 134.56 seconds
Started Feb 07 01:03:09 PM PST 24
Finished Feb 07 01:05:25 PM PST 24
Peak memory 210764 kb
Host smart-aebe3db6-79e6-4a3f-be62-a9d21cf45c5b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=875402224 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_c
orrupt_sig_fatal_chk.875402224
Directory /workspace/30.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/30.rom_ctrl_kmac_err_chk.1977001261
Short name T98
Test name
Test status
Simulation time 2940208476 ps
CPU time 25.49 seconds
Started Feb 07 01:03:25 PM PST 24
Finished Feb 07 01:03:51 PM PST 24
Peak memory 210876 kb
Host smart-bcc89312-2b6d-4610-b8a7-3c7795365bd6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1977001261 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_kmac_err_chk.1977001261
Directory /workspace/30.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/30.rom_ctrl_max_throughput_chk.3625895056
Short name T151
Test name
Test status
Simulation time 1308448198 ps
CPU time 9.18 seconds
Started Feb 07 01:03:16 PM PST 24
Finished Feb 07 01:03:26 PM PST 24
Peak memory 210560 kb
Host smart-014d8994-c170-417f-9bd6-7758a5bdec5d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3625895056 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_max_throughput_chk.3625895056
Directory /workspace/30.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/30.rom_ctrl_smoke.3039512225
Short name T199
Test name
Test status
Simulation time 373749844 ps
CPU time 10.1 seconds
Started Feb 07 01:03:15 PM PST 24
Finished Feb 07 01:03:26 PM PST 24
Peak memory 212600 kb
Host smart-790f0f99-cb79-45f6-8274-717a6e86bbae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3039512225 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_smoke.3039512225
Directory /workspace/30.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/30.rom_ctrl_stress_all.2897050967
Short name T248
Test name
Test status
Simulation time 4806114171 ps
CPU time 35.06 seconds
Started Feb 07 01:03:11 PM PST 24
Finished Feb 07 01:03:47 PM PST 24
Peak memory 215328 kb
Host smart-85086b30-bfb8-4ad0-b3d7-654c866f172c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2897050967 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 30.rom_ctrl_stress_all.2897050967
Directory /workspace/30.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/31.rom_ctrl_alert_test.1527131532
Short name T392
Test name
Test status
Simulation time 1564586130 ps
CPU time 13.12 seconds
Started Feb 07 01:03:22 PM PST 24
Finished Feb 07 01:03:36 PM PST 24
Peak memory 210496 kb
Host smart-9a23dfbe-8c8f-40ef-8a63-776d804a19d5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1527131532 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_alert_test.1527131532
Directory /workspace/31.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/31.rom_ctrl_corrupt_sig_fatal_chk.4213506809
Short name T254
Test name
Test status
Simulation time 43582300280 ps
CPU time 312.52 seconds
Started Feb 07 01:03:26 PM PST 24
Finished Feb 07 01:08:39 PM PST 24
Peak memory 214976 kb
Host smart-ce86f233-e6b0-4aba-aacc-113ce90b8133
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4213506809 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_
corrupt_sig_fatal_chk.4213506809
Directory /workspace/31.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/31.rom_ctrl_kmac_err_chk.2534951793
Short name T20
Test name
Test status
Simulation time 450674020 ps
CPU time 9.55 seconds
Started Feb 07 01:03:25 PM PST 24
Finished Feb 07 01:03:35 PM PST 24
Peak memory 210756 kb
Host smart-aa497e69-cd33-4ec6-b527-7c27957d8058
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2534951793 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_kmac_err_chk.2534951793
Directory /workspace/31.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/31.rom_ctrl_max_throughput_chk.4030943045
Short name T175
Test name
Test status
Simulation time 11462003543 ps
CPU time 14.4 seconds
Started Feb 07 01:03:21 PM PST 24
Finished Feb 07 01:03:36 PM PST 24
Peak memory 210604 kb
Host smart-c4f4c5ad-98aa-4afb-922e-8e46cd2337c0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4030943045 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_max_throughput_chk.4030943045
Directory /workspace/31.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/31.rom_ctrl_smoke.2590913633
Short name T399
Test name
Test status
Simulation time 5777577600 ps
CPU time 32.27 seconds
Started Feb 07 01:03:21 PM PST 24
Finished Feb 07 01:03:54 PM PST 24
Peak memory 213060 kb
Host smart-9821f6a3-1f92-4576-afc3-64edc09bc12f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2590913633 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_smoke.2590913633
Directory /workspace/31.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/31.rom_ctrl_stress_all.1086739367
Short name T181
Test name
Test status
Simulation time 6879591118 ps
CPU time 15.96 seconds
Started Feb 07 01:03:22 PM PST 24
Finished Feb 07 01:03:39 PM PST 24
Peak memory 211292 kb
Host smart-a26359cf-bbcb-477f-89a6-56e36902d0ac
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1086739367 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 31.rom_ctrl_stress_all.1086739367
Directory /workspace/31.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/31.rom_ctrl_stress_all_with_rand_reset.1098635110
Short name T282
Test name
Test status
Simulation time 70351880948 ps
CPU time 1472.06 seconds
Started Feb 07 01:03:22 PM PST 24
Finished Feb 07 01:27:55 PM PST 24
Peak memory 235284 kb
Host smart-1f1e5e42-fe61-4449-b0ea-13914cd54435
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1098635110 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_stress_all_with_rand_reset.1098635110
Directory /workspace/31.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.rom_ctrl_alert_test.247502578
Short name T360
Test name
Test status
Simulation time 952945757 ps
CPU time 9.9 seconds
Started Feb 07 01:03:24 PM PST 24
Finished Feb 07 01:03:35 PM PST 24
Peak memory 210372 kb
Host smart-fbf60897-ec92-4b79-962e-d2f6fb4ba5fb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=247502578 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_alert_test.247502578
Directory /workspace/32.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/32.rom_ctrl_corrupt_sig_fatal_chk.1989310932
Short name T209
Test name
Test status
Simulation time 131717504108 ps
CPU time 318.54 seconds
Started Feb 07 01:03:31 PM PST 24
Finished Feb 07 01:08:50 PM PST 24
Peak memory 227912 kb
Host smart-51ade526-d208-43d3-88ba-b18b29146e89
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1989310932 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_
corrupt_sig_fatal_chk.1989310932
Directory /workspace/32.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/32.rom_ctrl_kmac_err_chk.2974683601
Short name T19
Test name
Test status
Simulation time 174100263 ps
CPU time 9.54 seconds
Started Feb 07 01:03:28 PM PST 24
Finished Feb 07 01:03:38 PM PST 24
Peak memory 210608 kb
Host smart-e8b74776-3fc8-4f04-8a40-63fd40ff76ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2974683601 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_kmac_err_chk.2974683601
Directory /workspace/32.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/32.rom_ctrl_max_throughput_chk.3186403994
Short name T154
Test name
Test status
Simulation time 418708493 ps
CPU time 5.34 seconds
Started Feb 07 01:03:23 PM PST 24
Finished Feb 07 01:03:29 PM PST 24
Peak memory 210500 kb
Host smart-af53e838-201f-4d76-ab01-d70dd4417233
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3186403994 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_max_throughput_chk.3186403994
Directory /workspace/32.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/32.rom_ctrl_smoke.110088610
Short name T10
Test name
Test status
Simulation time 7167359941 ps
CPU time 14.01 seconds
Started Feb 07 01:03:22 PM PST 24
Finished Feb 07 01:03:37 PM PST 24
Peak memory 213044 kb
Host smart-63e532c4-e637-414d-9133-6e8de3460fe3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=110088610 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_smoke.110088610
Directory /workspace/32.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/32.rom_ctrl_stress_all.1055151139
Short name T235
Test name
Test status
Simulation time 3545445099 ps
CPU time 31.58 seconds
Started Feb 07 01:03:25 PM PST 24
Finished Feb 07 01:03:57 PM PST 24
Peak memory 214344 kb
Host smart-9cc5b6f3-80b8-4ee3-8d99-5f2ac0ddcf93
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1055151139 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 32.rom_ctrl_stress_all.1055151139
Directory /workspace/32.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/32.rom_ctrl_stress_all_with_rand_reset.3095196501
Short name T163
Test name
Test status
Simulation time 230360242840 ps
CPU time 2296.28 seconds
Started Feb 07 01:03:30 PM PST 24
Finished Feb 07 01:41:47 PM PST 24
Peak memory 237220 kb
Host smart-9ee08c8d-b142-421c-b311-aca46be716c7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3095196501 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_stress_all_with_rand_reset.3095196501
Directory /workspace/32.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.rom_ctrl_alert_test.1204137768
Short name T226
Test name
Test status
Simulation time 1966759595 ps
CPU time 15.74 seconds
Started Feb 07 01:03:30 PM PST 24
Finished Feb 07 01:03:47 PM PST 24
Peak memory 210592 kb
Host smart-4f9a77d2-a54e-4c8d-87e8-2eafe936bb30
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1204137768 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_alert_test.1204137768
Directory /workspace/33.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/33.rom_ctrl_corrupt_sig_fatal_chk.3008084005
Short name T306
Test name
Test status
Simulation time 143071789350 ps
CPU time 264.57 seconds
Started Feb 07 01:03:23 PM PST 24
Finished Feb 07 01:07:48 PM PST 24
Peak memory 227796 kb
Host smart-64f9a1ae-2812-428b-9caf-24d02f06f37b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3008084005 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_
corrupt_sig_fatal_chk.3008084005
Directory /workspace/33.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/33.rom_ctrl_kmac_err_chk.1367366784
Short name T380
Test name
Test status
Simulation time 6058753453 ps
CPU time 22.46 seconds
Started Feb 07 01:03:25 PM PST 24
Finished Feb 07 01:03:48 PM PST 24
Peak memory 211416 kb
Host smart-bd2e8200-7e47-4768-aede-2262e780d981
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1367366784 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_kmac_err_chk.1367366784
Directory /workspace/33.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/33.rom_ctrl_max_throughput_chk.1392514779
Short name T102
Test name
Test status
Simulation time 7381191914 ps
CPU time 15.95 seconds
Started Feb 07 01:03:31 PM PST 24
Finished Feb 07 01:03:47 PM PST 24
Peak memory 210632 kb
Host smart-611a7278-4ac4-406e-ac7d-ac4fbe722064
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1392514779 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_max_throughput_chk.1392514779
Directory /workspace/33.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/33.rom_ctrl_smoke.3345553890
Short name T295
Test name
Test status
Simulation time 369611338 ps
CPU time 10.09 seconds
Started Feb 07 01:03:26 PM PST 24
Finished Feb 07 01:03:37 PM PST 24
Peak memory 212552 kb
Host smart-66595cd5-7edb-4798-8d86-b238527501ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3345553890 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_smoke.3345553890
Directory /workspace/33.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/33.rom_ctrl_stress_all.779768046
Short name T210
Test name
Test status
Simulation time 323845903 ps
CPU time 16.34 seconds
Started Feb 07 01:03:20 PM PST 24
Finished Feb 07 01:03:37 PM PST 24
Peak memory 213644 kb
Host smart-b1df0bff-3547-4de9-bb77-5f34edfc14c6
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=779768046 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 33.rom_ctrl_stress_all.779768046
Directory /workspace/33.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/33.rom_ctrl_stress_all_with_rand_reset.2842738010
Short name T11
Test name
Test status
Simulation time 239754424537 ps
CPU time 9697.35 seconds
Started Feb 07 01:03:25 PM PST 24
Finished Feb 07 03:45:04 PM PST 24
Peak memory 237084 kb
Host smart-5a06f81f-fd96-4913-bb75-d70a23d11686
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2842738010 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_stress_all_with_rand_reset.2842738010
Directory /workspace/33.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.rom_ctrl_alert_test.4075811092
Short name T326
Test name
Test status
Simulation time 89881636 ps
CPU time 4.32 seconds
Started Feb 07 01:03:34 PM PST 24
Finished Feb 07 01:03:39 PM PST 24
Peak memory 210608 kb
Host smart-88294a39-b852-4c1f-bdcc-b89313b1afbe
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4075811092 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_alert_test.4075811092
Directory /workspace/34.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/34.rom_ctrl_kmac_err_chk.1757319423
Short name T18
Test name
Test status
Simulation time 1038667679 ps
CPU time 9.52 seconds
Started Feb 07 01:03:23 PM PST 24
Finished Feb 07 01:03:33 PM PST 24
Peak memory 210680 kb
Host smart-18cbbc89-41c7-4485-9d2a-17916c29c20d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1757319423 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_kmac_err_chk.1757319423
Directory /workspace/34.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/34.rom_ctrl_max_throughput_chk.3274940859
Short name T336
Test name
Test status
Simulation time 1565713419 ps
CPU time 14.28 seconds
Started Feb 07 01:03:20 PM PST 24
Finished Feb 07 01:03:35 PM PST 24
Peak memory 210544 kb
Host smart-74424ba6-641a-47f8-8e3d-15c425c540d9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3274940859 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_max_throughput_chk.3274940859
Directory /workspace/34.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/34.rom_ctrl_smoke.2903945950
Short name T388
Test name
Test status
Simulation time 3631365608 ps
CPU time 28.38 seconds
Started Feb 07 01:03:21 PM PST 24
Finished Feb 07 01:03:50 PM PST 24
Peak memory 212184 kb
Host smart-81d3f180-b357-4ab5-a138-e2110ddc9dd3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2903945950 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_smoke.2903945950
Directory /workspace/34.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/34.rom_ctrl_stress_all.7333380
Short name T208
Test name
Test status
Simulation time 17779929276 ps
CPU time 70.95 seconds
Started Feb 07 01:03:25 PM PST 24
Finished Feb 07 01:04:37 PM PST 24
Peak memory 215028 kb
Host smart-f0ebd70e-5ba2-4a06-9c49-c66e0b11b3cb
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=7333380 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UV
M_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 34.rom_ctrl_stress_all.7333380
Directory /workspace/34.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/34.rom_ctrl_stress_all_with_rand_reset.2825672585
Short name T269
Test name
Test status
Simulation time 78008045450 ps
CPU time 1204.34 seconds
Started Feb 07 01:03:23 PM PST 24
Finished Feb 07 01:23:28 PM PST 24
Peak memory 235288 kb
Host smart-491c4d37-df35-4a89-9d48-6adaa3833f8d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2825672585 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_stress_all_with_rand_reset.2825672585
Directory /workspace/34.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.rom_ctrl_alert_test.2066168668
Short name T385
Test name
Test status
Simulation time 3577497278 ps
CPU time 14.77 seconds
Started Feb 07 01:03:31 PM PST 24
Finished Feb 07 01:03:47 PM PST 24
Peak memory 210560 kb
Host smart-241a706b-dcdb-4357-b46a-1ba73d60e3dd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2066168668 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_alert_test.2066168668
Directory /workspace/35.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/35.rom_ctrl_corrupt_sig_fatal_chk.3127866043
Short name T309
Test name
Test status
Simulation time 17986372112 ps
CPU time 239.69 seconds
Started Feb 07 01:03:42 PM PST 24
Finished Feb 07 01:07:42 PM PST 24
Peak memory 234156 kb
Host smart-9da302f0-7ac2-4c05-933a-29d3854b7d7b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3127866043 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_
corrupt_sig_fatal_chk.3127866043
Directory /workspace/35.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/35.rom_ctrl_kmac_err_chk.2387643873
Short name T173
Test name
Test status
Simulation time 15292702991 ps
CPU time 31.46 seconds
Started Feb 07 01:03:34 PM PST 24
Finished Feb 07 01:04:06 PM PST 24
Peak memory 210980 kb
Host smart-400ab5aa-fd98-4803-8947-80b8dff03b6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2387643873 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_kmac_err_chk.2387643873
Directory /workspace/35.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/35.rom_ctrl_max_throughput_chk.22749753
Short name T317
Test name
Test status
Simulation time 6314258534 ps
CPU time 13.92 seconds
Started Feb 07 01:03:32 PM PST 24
Finished Feb 07 01:03:46 PM PST 24
Peak memory 210552 kb
Host smart-985a7cda-a58a-4844-bc19-9b7deef5cf09
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=22749753 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_max_throughput_chk.22749753
Directory /workspace/35.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/35.rom_ctrl_smoke.460639955
Short name T369
Test name
Test status
Simulation time 9226577889 ps
CPU time 30.16 seconds
Started Feb 07 01:03:33 PM PST 24
Finished Feb 07 01:04:04 PM PST 24
Peak memory 212652 kb
Host smart-a8f431c7-a03c-4ef3-8b1a-0257c7846bfe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=460639955 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_smoke.460639955
Directory /workspace/35.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/35.rom_ctrl_stress_all.1880934951
Short name T143
Test name
Test status
Simulation time 287170922 ps
CPU time 16.12 seconds
Started Feb 07 01:03:34 PM PST 24
Finished Feb 07 01:03:51 PM PST 24
Peak memory 210976 kb
Host smart-48e2b645-0d91-4f5e-9397-5180fcfa56dc
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1880934951 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 35.rom_ctrl_stress_all.1880934951
Directory /workspace/35.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/36.rom_ctrl_alert_test.1981161208
Short name T398
Test name
Test status
Simulation time 638505270 ps
CPU time 4.09 seconds
Started Feb 07 01:03:36 PM PST 24
Finished Feb 07 01:03:40 PM PST 24
Peak memory 210556 kb
Host smart-ae5818cd-40c8-410c-927c-1133983a6569
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1981161208 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_alert_test.1981161208
Directory /workspace/36.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/36.rom_ctrl_corrupt_sig_fatal_chk.2230480426
Short name T26
Test name
Test status
Simulation time 4906449086 ps
CPU time 98.9 seconds
Started Feb 07 01:03:33 PM PST 24
Finished Feb 07 01:05:12 PM PST 24
Peak memory 227736 kb
Host smart-2695730a-a740-4009-a164-16e073085b06
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2230480426 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_
corrupt_sig_fatal_chk.2230480426
Directory /workspace/36.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/36.rom_ctrl_kmac_err_chk.1307216452
Short name T147
Test name
Test status
Simulation time 7189780809 ps
CPU time 17.17 seconds
Started Feb 07 01:03:34 PM PST 24
Finished Feb 07 01:03:51 PM PST 24
Peak memory 211356 kb
Host smart-f10b0ceb-daf5-4f13-bcaa-3e76e367b02f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1307216452 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_kmac_err_chk.1307216452
Directory /workspace/36.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/36.rom_ctrl_max_throughput_chk.2093767080
Short name T281
Test name
Test status
Simulation time 403691947 ps
CPU time 5.6 seconds
Started Feb 07 01:03:32 PM PST 24
Finished Feb 07 01:03:38 PM PST 24
Peak memory 210496 kb
Host smart-2b7e82c3-1d15-499c-9a85-dabe38d96a60
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2093767080 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_max_throughput_chk.2093767080
Directory /workspace/36.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/36.rom_ctrl_smoke.608988909
Short name T53
Test name
Test status
Simulation time 1377564670 ps
CPU time 9.87 seconds
Started Feb 07 01:03:41 PM PST 24
Finished Feb 07 01:03:52 PM PST 24
Peak memory 212368 kb
Host smart-7531e8e6-26b6-4073-be37-b36578aeba6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=608988909 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_smoke.608988909
Directory /workspace/36.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/36.rom_ctrl_stress_all.1259102548
Short name T383
Test name
Test status
Simulation time 215351140 ps
CPU time 11.6 seconds
Started Feb 07 01:03:34 PM PST 24
Finished Feb 07 01:03:46 PM PST 24
Peak memory 210440 kb
Host smart-b5fe427f-4a33-4627-ad30-08933ca02319
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1259102548 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 36.rom_ctrl_stress_all.1259102548
Directory /workspace/36.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/36.rom_ctrl_stress_all_with_rand_reset.1806002127
Short name T296
Test name
Test status
Simulation time 189973782628 ps
CPU time 2721.37 seconds
Started Feb 07 01:03:35 PM PST 24
Finished Feb 07 01:48:57 PM PST 24
Peak memory 239120 kb
Host smart-32761672-5128-4ece-8c94-eebc1d719f58
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1806002127 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_stress_all_with_rand_reset.1806002127
Directory /workspace/36.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.rom_ctrl_alert_test.4287470204
Short name T176
Test name
Test status
Simulation time 2309029266 ps
CPU time 9.44 seconds
Started Feb 07 01:03:50 PM PST 24
Finished Feb 07 01:04:00 PM PST 24
Peak memory 210620 kb
Host smart-8bedbfa2-840d-451f-9a74-3df0bd7792d8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4287470204 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_alert_test.4287470204
Directory /workspace/37.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/37.rom_ctrl_corrupt_sig_fatal_chk.3818545826
Short name T362
Test name
Test status
Simulation time 13301974496 ps
CPU time 214.73 seconds
Started Feb 07 01:03:50 PM PST 24
Finished Feb 07 01:07:25 PM PST 24
Peak memory 237088 kb
Host smart-4a1820dd-f711-4b16-aab0-df7a071a92bd
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3818545826 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_
corrupt_sig_fatal_chk.3818545826
Directory /workspace/37.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/37.rom_ctrl_kmac_err_chk.73512719
Short name T270
Test name
Test status
Simulation time 2366918301 ps
CPU time 9.47 seconds
Started Feb 07 01:03:51 PM PST 24
Finished Feb 07 01:04:01 PM PST 24
Peak memory 210760 kb
Host smart-37178450-993a-4b39-9b83-8265ace8c1b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=73512719 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_kmac_err_chk.73512719
Directory /workspace/37.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/37.rom_ctrl_max_throughput_chk.3349708032
Short name T153
Test name
Test status
Simulation time 2311220534 ps
CPU time 8.49 seconds
Started Feb 07 01:03:35 PM PST 24
Finished Feb 07 01:03:44 PM PST 24
Peak memory 210472 kb
Host smart-906f56c8-366b-4fb7-b8db-e7a0b51bd627
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3349708032 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_max_throughput_chk.3349708032
Directory /workspace/37.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/37.rom_ctrl_smoke.2880969457
Short name T198
Test name
Test status
Simulation time 450084546 ps
CPU time 12.77 seconds
Started Feb 07 01:03:32 PM PST 24
Finished Feb 07 01:03:45 PM PST 24
Peak memory 212252 kb
Host smart-bd2072de-6c05-4926-90a7-16bd5cf26d83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2880969457 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_smoke.2880969457
Directory /workspace/37.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/37.rom_ctrl_stress_all.2630241411
Short name T257
Test name
Test status
Simulation time 12049378934 ps
CPU time 58.11 seconds
Started Feb 07 01:03:33 PM PST 24
Finished Feb 07 01:04:32 PM PST 24
Peak memory 214616 kb
Host smart-6bf1605a-2e72-4abd-b217-cd3c8be25d6d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2630241411 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 37.rom_ctrl_stress_all.2630241411
Directory /workspace/37.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/38.rom_ctrl_alert_test.3309288987
Short name T215
Test name
Test status
Simulation time 9877679218 ps
CPU time 15.98 seconds
Started Feb 07 01:03:49 PM PST 24
Finished Feb 07 01:04:06 PM PST 24
Peak memory 210540 kb
Host smart-bb6438f5-60d6-4ef5-abe3-ff16ca5fede7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3309288987 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_alert_test.3309288987
Directory /workspace/38.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/38.rom_ctrl_corrupt_sig_fatal_chk.1748433378
Short name T27
Test name
Test status
Simulation time 2329564197 ps
CPU time 131.53 seconds
Started Feb 07 01:03:51 PM PST 24
Finished Feb 07 01:06:03 PM PST 24
Peak memory 235700 kb
Host smart-7a406219-d4dc-4413-861f-71fe5fcf26ba
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1748433378 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_
corrupt_sig_fatal_chk.1748433378
Directory /workspace/38.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/38.rom_ctrl_kmac_err_chk.1911682970
Short name T255
Test name
Test status
Simulation time 3762604589 ps
CPU time 32.63 seconds
Started Feb 07 01:03:49 PM PST 24
Finished Feb 07 01:04:23 PM PST 24
Peak memory 210772 kb
Host smart-16ee00e3-ea18-4bbe-b43f-a71ee18fab12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1911682970 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_kmac_err_chk.1911682970
Directory /workspace/38.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/38.rom_ctrl_max_throughput_chk.4213790650
Short name T408
Test name
Test status
Simulation time 198230656 ps
CPU time 5.73 seconds
Started Feb 07 01:03:49 PM PST 24
Finished Feb 07 01:03:55 PM PST 24
Peak memory 210464 kb
Host smart-5c38d8ac-792b-4b63-b66e-fd24c72c23ce
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4213790650 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_max_throughput_chk.4213790650
Directory /workspace/38.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/38.rom_ctrl_smoke.2494690464
Short name T221
Test name
Test status
Simulation time 8409791726 ps
CPU time 33.59 seconds
Started Feb 07 01:03:51 PM PST 24
Finished Feb 07 01:04:26 PM PST 24
Peak memory 213100 kb
Host smart-9f268b8d-2ef8-4923-a11b-bd262887dd26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2494690464 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_smoke.2494690464
Directory /workspace/38.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/38.rom_ctrl_stress_all.1866396197
Short name T342
Test name
Test status
Simulation time 562326369 ps
CPU time 15.7 seconds
Started Feb 07 01:03:50 PM PST 24
Finished Feb 07 01:04:06 PM PST 24
Peak memory 212532 kb
Host smart-7200e561-9574-4d60-be97-379169cecae3
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1866396197 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 38.rom_ctrl_stress_all.1866396197
Directory /workspace/38.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/39.rom_ctrl_alert_test.3425965401
Short name T212
Test name
Test status
Simulation time 2562469690 ps
CPU time 12.01 seconds
Started Feb 07 01:03:53 PM PST 24
Finished Feb 07 01:04:05 PM PST 24
Peak memory 210620 kb
Host smart-48af5677-6f20-47c9-9530-d80b1d1d390e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3425965401 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_alert_test.3425965401
Directory /workspace/39.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/39.rom_ctrl_corrupt_sig_fatal_chk.730110564
Short name T244
Test name
Test status
Simulation time 51082717166 ps
CPU time 521.51 seconds
Started Feb 07 01:03:48 PM PST 24
Finished Feb 07 01:12:30 PM PST 24
Peak memory 224288 kb
Host smart-66304ca5-b655-4cec-980f-b5f3683a8aa1
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=730110564 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_c
orrupt_sig_fatal_chk.730110564
Directory /workspace/39.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/39.rom_ctrl_kmac_err_chk.1185382273
Short name T418
Test name
Test status
Simulation time 9257629532 ps
CPU time 23.28 seconds
Started Feb 07 01:03:50 PM PST 24
Finished Feb 07 01:04:14 PM PST 24
Peak memory 211052 kb
Host smart-06adbdb9-0a2c-4e0b-926f-2e3c1dcf1a43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1185382273 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_kmac_err_chk.1185382273
Directory /workspace/39.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/39.rom_ctrl_max_throughput_chk.625338290
Short name T325
Test name
Test status
Simulation time 4331752336 ps
CPU time 14.75 seconds
Started Feb 07 01:03:51 PM PST 24
Finished Feb 07 01:04:07 PM PST 24
Peak memory 210504 kb
Host smart-396ffe04-6956-4bd4-a9e9-37825046bd6a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=625338290 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_max_throughput_chk.625338290
Directory /workspace/39.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/39.rom_ctrl_smoke.1281948491
Short name T301
Test name
Test status
Simulation time 231164090 ps
CPU time 10.28 seconds
Started Feb 07 01:03:51 PM PST 24
Finished Feb 07 01:04:02 PM PST 24
Peak memory 211760 kb
Host smart-4849e475-9f43-4b71-8d5a-181845a8bf03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1281948491 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_smoke.1281948491
Directory /workspace/39.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/39.rom_ctrl_stress_all.3270456692
Short name T101
Test name
Test status
Simulation time 2051369041 ps
CPU time 25.9 seconds
Started Feb 07 01:03:50 PM PST 24
Finished Feb 07 01:04:17 PM PST 24
Peak memory 215008 kb
Host smart-e40e5bc1-9ed4-4aa8-a2a1-64df00fd5997
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3270456692 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 39.rom_ctrl_stress_all.3270456692
Directory /workspace/39.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/4.rom_ctrl_alert_test.3885922680
Short name T200
Test name
Test status
Simulation time 9650888810 ps
CPU time 13.72 seconds
Started Feb 07 01:01:40 PM PST 24
Finished Feb 07 01:01:54 PM PST 24
Peak memory 210524 kb
Host smart-e00fbcf9-9d01-49e6-956b-904749866f58
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3885922680 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_alert_test.3885922680
Directory /workspace/4.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/4.rom_ctrl_corrupt_sig_fatal_chk.1729368739
Short name T260
Test name
Test status
Simulation time 67223362329 ps
CPU time 352.33 seconds
Started Feb 07 01:01:41 PM PST 24
Finished Feb 07 01:07:34 PM PST 24
Peak memory 233200 kb
Host smart-5a85068d-ae97-4586-94a2-5524c81299b2
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1729368739 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_c
orrupt_sig_fatal_chk.1729368739
Directory /workspace/4.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/4.rom_ctrl_kmac_err_chk.2602763640
Short name T421
Test name
Test status
Simulation time 11748646809 ps
CPU time 26.34 seconds
Started Feb 07 01:01:41 PM PST 24
Finished Feb 07 01:02:07 PM PST 24
Peak memory 210888 kb
Host smart-31f5b8c9-9210-4ffd-aa00-69e98a7ab298
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2602763640 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_kmac_err_chk.2602763640
Directory /workspace/4.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/4.rom_ctrl_max_throughput_chk.1771804003
Short name T166
Test name
Test status
Simulation time 1316019719 ps
CPU time 13.37 seconds
Started Feb 07 01:01:40 PM PST 24
Finished Feb 07 01:01:54 PM PST 24
Peak memory 210512 kb
Host smart-1aa43d8b-70d1-4a86-89b5-026c5c888239
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1771804003 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_max_throughput_chk.1771804003
Directory /workspace/4.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/4.rom_ctrl_sec_cm.2185291
Short name T29
Test name
Test status
Simulation time 1430475455 ps
CPU time 55.77 seconds
Started Feb 07 01:01:42 PM PST 24
Finished Feb 07 01:02:38 PM PST 24
Peak memory 234488 kb
Host smart-d09e8f40-4a54-4932-bea3-4390420667b7
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2185291 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_sec_cm.2185291
Directory /workspace/4.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/4.rom_ctrl_smoke.904752217
Short name T240
Test name
Test status
Simulation time 6478500359 ps
CPU time 35.75 seconds
Started Feb 07 01:01:39 PM PST 24
Finished Feb 07 01:02:15 PM PST 24
Peak memory 212812 kb
Host smart-f4241462-f7fc-4475-8c93-e9757421108c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=904752217 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_smoke.904752217
Directory /workspace/4.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/4.rom_ctrl_stress_all.2649201420
Short name T202
Test name
Test status
Simulation time 72114489809 ps
CPU time 56.98 seconds
Started Feb 07 01:01:41 PM PST 24
Finished Feb 07 01:02:39 PM PST 24
Peak memory 216024 kb
Host smart-704e8da9-99c2-4aec-b4be-9698c3ee2043
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2649201420 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 4.rom_ctrl_stress_all.2649201420
Directory /workspace/4.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/40.rom_ctrl_alert_test.2941644904
Short name T350
Test name
Test status
Simulation time 25102052319 ps
CPU time 14.62 seconds
Started Feb 07 01:04:05 PM PST 24
Finished Feb 07 01:04:20 PM PST 24
Peak memory 210588 kb
Host smart-42b34466-c673-4c85-80b3-3b1c8b758aca
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2941644904 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_alert_test.2941644904
Directory /workspace/40.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/40.rom_ctrl_corrupt_sig_fatal_chk.1766952702
Short name T170
Test name
Test status
Simulation time 195295447275 ps
CPU time 327.68 seconds
Started Feb 07 01:04:05 PM PST 24
Finished Feb 07 01:09:33 PM PST 24
Peak memory 232192 kb
Host smart-aa58327a-bf5f-4a91-b9b4-ea0ce349306e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1766952702 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_
corrupt_sig_fatal_chk.1766952702
Directory /workspace/40.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/40.rom_ctrl_kmac_err_chk.661265166
Short name T389
Test name
Test status
Simulation time 1385125403 ps
CPU time 9.34 seconds
Started Feb 07 01:04:02 PM PST 24
Finished Feb 07 01:04:12 PM PST 24
Peak memory 210728 kb
Host smart-358da723-8652-4b5f-8a1a-49342f4f8758
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=661265166 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_kmac_err_chk.661265166
Directory /workspace/40.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/40.rom_ctrl_max_throughput_chk.2955741743
Short name T320
Test name
Test status
Simulation time 4318581714 ps
CPU time 11.89 seconds
Started Feb 07 01:04:04 PM PST 24
Finished Feb 07 01:04:17 PM PST 24
Peak memory 210612 kb
Host smart-5cffcebf-ca90-40d2-80b3-3de71aa50ecc
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2955741743 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_max_throughput_chk.2955741743
Directory /workspace/40.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/40.rom_ctrl_smoke.1758368706
Short name T191
Test name
Test status
Simulation time 198831068 ps
CPU time 10 seconds
Started Feb 07 01:03:48 PM PST 24
Finished Feb 07 01:03:58 PM PST 24
Peak memory 211096 kb
Host smart-ffa3fc0f-c63c-49fd-9704-a8e58f2dce12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1758368706 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_smoke.1758368706
Directory /workspace/40.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/40.rom_ctrl_stress_all.2174886638
Short name T5
Test name
Test status
Simulation time 84570342621 ps
CPU time 80.88 seconds
Started Feb 07 01:03:50 PM PST 24
Finished Feb 07 01:05:12 PM PST 24
Peak memory 215984 kb
Host smart-68512bd1-72a3-4970-8304-7ab277095ab2
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2174886638 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 40.rom_ctrl_stress_all.2174886638
Directory /workspace/40.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/41.rom_ctrl_alert_test.2354764341
Short name T225
Test name
Test status
Simulation time 3806280391 ps
CPU time 10.44 seconds
Started Feb 07 01:04:06 PM PST 24
Finished Feb 07 01:04:17 PM PST 24
Peak memory 210572 kb
Host smart-d7a049b0-4001-41f1-a66a-3e743ec98438
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2354764341 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_alert_test.2354764341
Directory /workspace/41.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/41.rom_ctrl_corrupt_sig_fatal_chk.3468535212
Short name T403
Test name
Test status
Simulation time 38133527123 ps
CPU time 227.28 seconds
Started Feb 07 01:04:01 PM PST 24
Finished Feb 07 01:07:50 PM PST 24
Peak memory 227880 kb
Host smart-8aa6f3d2-03db-44ef-b9f2-8285283da184
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3468535212 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_
corrupt_sig_fatal_chk.3468535212
Directory /workspace/41.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/41.rom_ctrl_kmac_err_chk.3903399164
Short name T363
Test name
Test status
Simulation time 2275415980 ps
CPU time 23.4 seconds
Started Feb 07 01:04:03 PM PST 24
Finished Feb 07 01:04:27 PM PST 24
Peak memory 210744 kb
Host smart-fb0e0b44-d754-41d2-90f6-1d2cca10c24f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3903399164 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_kmac_err_chk.3903399164
Directory /workspace/41.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/41.rom_ctrl_smoke.1860924940
Short name T178
Test name
Test status
Simulation time 711968576 ps
CPU time 10.25 seconds
Started Feb 07 01:04:01 PM PST 24
Finished Feb 07 01:04:12 PM PST 24
Peak memory 212052 kb
Host smart-e4a7faff-34a4-4f55-802d-42ba1b4f1ec5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1860924940 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_smoke.1860924940
Directory /workspace/41.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/41.rom_ctrl_stress_all.3712106388
Short name T278
Test name
Test status
Simulation time 3568731138 ps
CPU time 33.07 seconds
Started Feb 07 01:04:01 PM PST 24
Finished Feb 07 01:04:35 PM PST 24
Peak memory 213532 kb
Host smart-eebd25e3-d735-4737-8b65-1c6a94048189
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3712106388 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 41.rom_ctrl_stress_all.3712106388
Directory /workspace/41.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/42.rom_ctrl_alert_test.1758513495
Short name T396
Test name
Test status
Simulation time 437494607 ps
CPU time 4.27 seconds
Started Feb 07 01:04:06 PM PST 24
Finished Feb 07 01:04:10 PM PST 24
Peak memory 210524 kb
Host smart-9b9d4cdb-9805-4f9f-8ccd-786b1faced85
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1758513495 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_alert_test.1758513495
Directory /workspace/42.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/42.rom_ctrl_corrupt_sig_fatal_chk.1145341098
Short name T55
Test name
Test status
Simulation time 203805105090 ps
CPU time 273.21 seconds
Started Feb 07 01:04:02 PM PST 24
Finished Feb 07 01:08:36 PM PST 24
Peak memory 232140 kb
Host smart-7ebf4298-eb0a-4fd6-bb00-6ef4b2f4efb3
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1145341098 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_
corrupt_sig_fatal_chk.1145341098
Directory /workspace/42.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/42.rom_ctrl_kmac_err_chk.3768524491
Short name T330
Test name
Test status
Simulation time 3706107965 ps
CPU time 31.19 seconds
Started Feb 07 01:04:03 PM PST 24
Finished Feb 07 01:04:35 PM PST 24
Peak memory 210760 kb
Host smart-cd4feb03-739f-4765-a40d-e1f32c0dc1cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3768524491 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_kmac_err_chk.3768524491
Directory /workspace/42.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/42.rom_ctrl_max_throughput_chk.1512143600
Short name T344
Test name
Test status
Simulation time 6496180188 ps
CPU time 11.49 seconds
Started Feb 07 01:04:05 PM PST 24
Finished Feb 07 01:04:17 PM PST 24
Peak memory 210592 kb
Host smart-700fbf3c-7ec0-426a-a184-8a60171ab658
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1512143600 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_max_throughput_chk.1512143600
Directory /workspace/42.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/42.rom_ctrl_smoke.766464942
Short name T155
Test name
Test status
Simulation time 355095824 ps
CPU time 12.85 seconds
Started Feb 07 01:04:01 PM PST 24
Finished Feb 07 01:04:15 PM PST 24
Peak memory 212512 kb
Host smart-5c544184-ede7-4a43-b52f-1c0f2d3aa881
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=766464942 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_smoke.766464942
Directory /workspace/42.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/42.rom_ctrl_stress_all.4271176951
Short name T145
Test name
Test status
Simulation time 8166579432 ps
CPU time 42.78 seconds
Started Feb 07 01:04:01 PM PST 24
Finished Feb 07 01:04:45 PM PST 24
Peak memory 215684 kb
Host smart-76e53f15-ab2a-4529-ada0-5b918958f100
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4271176951 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 42.rom_ctrl_stress_all.4271176951
Directory /workspace/42.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/43.rom_ctrl_alert_test.2818549166
Short name T359
Test name
Test status
Simulation time 859954672 ps
CPU time 10.07 seconds
Started Feb 07 01:04:12 PM PST 24
Finished Feb 07 01:04:23 PM PST 24
Peak memory 210532 kb
Host smart-c5ac2084-7448-4b77-af20-18a624ade6fc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2818549166 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_alert_test.2818549166
Directory /workspace/43.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/43.rom_ctrl_corrupt_sig_fatal_chk.1668685317
Short name T23
Test name
Test status
Simulation time 28267695879 ps
CPU time 360.76 seconds
Started Feb 07 01:04:01 PM PST 24
Finished Feb 07 01:10:03 PM PST 24
Peak memory 210812 kb
Host smart-48d1a668-6789-4c0d-918d-f1c93e4f1da8
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1668685317 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_
corrupt_sig_fatal_chk.1668685317
Directory /workspace/43.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/43.rom_ctrl_kmac_err_chk.4240416056
Short name T361
Test name
Test status
Simulation time 19935902027 ps
CPU time 29.71 seconds
Started Feb 07 01:04:05 PM PST 24
Finished Feb 07 01:04:35 PM PST 24
Peak memory 210840 kb
Host smart-f4096a27-1536-4fc1-8cbe-eff0774c8c5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4240416056 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_kmac_err_chk.4240416056
Directory /workspace/43.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/43.rom_ctrl_max_throughput_chk.1905985257
Short name T313
Test name
Test status
Simulation time 2073621324 ps
CPU time 17.65 seconds
Started Feb 07 01:04:02 PM PST 24
Finished Feb 07 01:04:20 PM PST 24
Peak memory 210520 kb
Host smart-bd270670-d91d-4310-ba06-203df6e5b398
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1905985257 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_max_throughput_chk.1905985257
Directory /workspace/43.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/43.rom_ctrl_smoke.3254556430
Short name T323
Test name
Test status
Simulation time 2707120543 ps
CPU time 25.11 seconds
Started Feb 07 01:04:03 PM PST 24
Finished Feb 07 01:04:28 PM PST 24
Peak memory 211828 kb
Host smart-7e8c8372-bdd9-403c-8aa8-f4c179715c6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3254556430 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_smoke.3254556430
Directory /workspace/43.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/43.rom_ctrl_stress_all.3046050148
Short name T207
Test name
Test status
Simulation time 747114862 ps
CPU time 43.42 seconds
Started Feb 07 01:04:01 PM PST 24
Finished Feb 07 01:04:46 PM PST 24
Peak memory 215736 kb
Host smart-154db456-1aab-4731-8979-a8bef8ccfe78
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3046050148 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 43.rom_ctrl_stress_all.3046050148
Directory /workspace/43.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/43.rom_ctrl_stress_all_with_rand_reset.3914040436
Short name T12
Test name
Test status
Simulation time 176840671073 ps
CPU time 2313.03 seconds
Started Feb 07 01:04:02 PM PST 24
Finished Feb 07 01:42:36 PM PST 24
Peak memory 235268 kb
Host smart-adac13ff-4259-4123-96ee-efb8ed5d5754
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3914040436 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_stress_all_with_rand_reset.3914040436
Directory /workspace/43.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.rom_ctrl_alert_test.1064729933
Short name T42
Test name
Test status
Simulation time 3109711636 ps
CPU time 13.62 seconds
Started Feb 07 01:04:12 PM PST 24
Finished Feb 07 01:04:27 PM PST 24
Peak memory 210584 kb
Host smart-feac3188-f437-43bb-9a62-ed139abb0859
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1064729933 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_alert_test.1064729933
Directory /workspace/44.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/44.rom_ctrl_corrupt_sig_fatal_chk.3015063334
Short name T25
Test name
Test status
Simulation time 19794375774 ps
CPU time 228.56 seconds
Started Feb 07 01:04:11 PM PST 24
Finished Feb 07 01:08:00 PM PST 24
Peak memory 227456 kb
Host smart-1bfdc3b5-30eb-416d-9b8d-4997656b819c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3015063334 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_
corrupt_sig_fatal_chk.3015063334
Directory /workspace/44.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/44.rom_ctrl_max_throughput_chk.874002908
Short name T346
Test name
Test status
Simulation time 1590083257 ps
CPU time 14.59 seconds
Started Feb 07 01:04:12 PM PST 24
Finished Feb 07 01:04:27 PM PST 24
Peak memory 210540 kb
Host smart-e99a2a36-c744-42b0-ad85-003655d07795
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=874002908 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_max_throughput_chk.874002908
Directory /workspace/44.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/44.rom_ctrl_smoke.4064502769
Short name T160
Test name
Test status
Simulation time 4226103849 ps
CPU time 33.48 seconds
Started Feb 07 01:04:15 PM PST 24
Finished Feb 07 01:04:49 PM PST 24
Peak memory 212048 kb
Host smart-3630db17-225e-4832-9f5c-13e0e35b24a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4064502769 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_smoke.4064502769
Directory /workspace/44.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/44.rom_ctrl_stress_all.1646598620
Short name T304
Test name
Test status
Simulation time 12415891579 ps
CPU time 30.97 seconds
Started Feb 07 01:04:13 PM PST 24
Finished Feb 07 01:04:44 PM PST 24
Peak memory 213612 kb
Host smart-60300717-a743-4547-8ab8-f42c44efa70f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1646598620 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 44.rom_ctrl_stress_all.1646598620
Directory /workspace/44.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/45.rom_ctrl_alert_test.2092434695
Short name T343
Test name
Test status
Simulation time 88183403 ps
CPU time 4.33 seconds
Started Feb 07 01:04:13 PM PST 24
Finished Feb 07 01:04:18 PM PST 24
Peak memory 210540 kb
Host smart-6ed02527-f248-4071-aa75-bbd1c385198f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2092434695 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_alert_test.2092434695
Directory /workspace/45.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/45.rom_ctrl_corrupt_sig_fatal_chk.2462374928
Short name T416
Test name
Test status
Simulation time 37081356703 ps
CPU time 179.93 seconds
Started Feb 07 01:04:13 PM PST 24
Finished Feb 07 01:07:13 PM PST 24
Peak memory 227832 kb
Host smart-ee22f6bf-c780-4e2c-a53c-c654f0ad610b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2462374928 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_
corrupt_sig_fatal_chk.2462374928
Directory /workspace/45.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/45.rom_ctrl_kmac_err_chk.238063746
Short name T415
Test name
Test status
Simulation time 327384208 ps
CPU time 9.4 seconds
Started Feb 07 01:04:14 PM PST 24
Finished Feb 07 01:04:23 PM PST 24
Peak memory 210632 kb
Host smart-5f90fa4c-7edb-4694-9bc0-11a9b733712e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=238063746 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_kmac_err_chk.238063746
Directory /workspace/45.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/45.rom_ctrl_max_throughput_chk.2526639432
Short name T165
Test name
Test status
Simulation time 3219547182 ps
CPU time 15.04 seconds
Started Feb 07 01:04:20 PM PST 24
Finished Feb 07 01:04:35 PM PST 24
Peak memory 210592 kb
Host smart-0fb8bb6f-319f-48f2-84e0-c789ce5604a3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2526639432 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_max_throughput_chk.2526639432
Directory /workspace/45.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/45.rom_ctrl_smoke.1951124172
Short name T148
Test name
Test status
Simulation time 363406456 ps
CPU time 10.19 seconds
Started Feb 07 01:04:12 PM PST 24
Finished Feb 07 01:04:22 PM PST 24
Peak memory 212168 kb
Host smart-5f26670a-90e6-430b-bc2c-c9d7ba2cfded
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1951124172 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_smoke.1951124172
Directory /workspace/45.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/45.rom_ctrl_stress_all.4172498959
Short name T222
Test name
Test status
Simulation time 197867061 ps
CPU time 11.79 seconds
Started Feb 07 01:04:13 PM PST 24
Finished Feb 07 01:04:25 PM PST 24
Peak memory 213400 kb
Host smart-022685d2-c9b2-49b8-9a95-a4df6b2543ad
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4172498959 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 45.rom_ctrl_stress_all.4172498959
Directory /workspace/45.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/46.rom_ctrl_alert_test.3485586907
Short name T236
Test name
Test status
Simulation time 86663982 ps
CPU time 4.37 seconds
Started Feb 07 01:04:13 PM PST 24
Finished Feb 07 01:04:18 PM PST 24
Peak memory 210460 kb
Host smart-b6c7b3c7-5537-41a2-82a3-556ef44c805f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3485586907 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_alert_test.3485586907
Directory /workspace/46.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/46.rom_ctrl_kmac_err_chk.189945218
Short name T158
Test name
Test status
Simulation time 13826058803 ps
CPU time 30.12 seconds
Started Feb 07 01:04:11 PM PST 24
Finished Feb 07 01:04:42 PM PST 24
Peak memory 211004 kb
Host smart-0a988da3-d2d0-437a-ac2a-83d471ad93cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=189945218 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_kmac_err_chk.189945218
Directory /workspace/46.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/46.rom_ctrl_max_throughput_chk.3606162630
Short name T307
Test name
Test status
Simulation time 161589418 ps
CPU time 5.61 seconds
Started Feb 07 01:04:16 PM PST 24
Finished Feb 07 01:04:22 PM PST 24
Peak memory 210548 kb
Host smart-f238f50a-126b-4119-a86d-a7f41ba38d65
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3606162630 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_max_throughput_chk.3606162630
Directory /workspace/46.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/46.rom_ctrl_smoke.1642223137
Short name T291
Test name
Test status
Simulation time 22247063660 ps
CPU time 20.07 seconds
Started Feb 07 01:04:12 PM PST 24
Finished Feb 07 01:04:33 PM PST 24
Peak memory 212812 kb
Host smart-2cae90b6-cf6d-4e29-8ebf-3daf490ebdb7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1642223137 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_smoke.1642223137
Directory /workspace/46.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/46.rom_ctrl_stress_all.2670614100
Short name T283
Test name
Test status
Simulation time 9343487550 ps
CPU time 25.38 seconds
Started Feb 07 01:04:13 PM PST 24
Finished Feb 07 01:04:39 PM PST 24
Peak memory 212840 kb
Host smart-156ccb08-c6fb-4270-b42c-cb6260d9f4cd
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2670614100 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 46.rom_ctrl_stress_all.2670614100
Directory /workspace/46.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/46.rom_ctrl_stress_all_with_rand_reset.912158185
Short name T229
Test name
Test status
Simulation time 46921402073 ps
CPU time 3748.33 seconds
Started Feb 07 01:04:11 PM PST 24
Finished Feb 07 02:06:40 PM PST 24
Peak memory 232392 kb
Host smart-e9ac99bc-162f-4dfd-a566-e23291a1e35e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=912158185 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_stress_all_with_rand_reset.912158185
Directory /workspace/46.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.rom_ctrl_alert_test.1052668333
Short name T184
Test name
Test status
Simulation time 1996843859 ps
CPU time 10.48 seconds
Started Feb 07 01:04:14 PM PST 24
Finished Feb 07 01:04:25 PM PST 24
Peak memory 210488 kb
Host smart-10117c2c-f928-4896-b2c5-670169180cc3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1052668333 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_alert_test.1052668333
Directory /workspace/47.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/47.rom_ctrl_corrupt_sig_fatal_chk.3865681596
Short name T335
Test name
Test status
Simulation time 29764798313 ps
CPU time 273 seconds
Started Feb 07 01:04:12 PM PST 24
Finished Feb 07 01:08:46 PM PST 24
Peak memory 223968 kb
Host smart-6e75178c-30e4-4eeb-87e0-165a8cbd4fa2
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3865681596 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_
corrupt_sig_fatal_chk.3865681596
Directory /workspace/47.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/47.rom_ctrl_kmac_err_chk.1936801382
Short name T387
Test name
Test status
Simulation time 1960344855 ps
CPU time 19.83 seconds
Started Feb 07 01:04:13 PM PST 24
Finished Feb 07 01:04:33 PM PST 24
Peak memory 210816 kb
Host smart-54a29184-fd2b-4040-b6ad-1d973ad1cde2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1936801382 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_kmac_err_chk.1936801382
Directory /workspace/47.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/47.rom_ctrl_max_throughput_chk.1173819693
Short name T274
Test name
Test status
Simulation time 95204706 ps
CPU time 5.27 seconds
Started Feb 07 01:04:11 PM PST 24
Finished Feb 07 01:04:17 PM PST 24
Peak memory 210480 kb
Host smart-7b828bf8-3cad-4fa9-b480-7b8ccdbf5695
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1173819693 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_max_throughput_chk.1173819693
Directory /workspace/47.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/47.rom_ctrl_smoke.2316332340
Short name T286
Test name
Test status
Simulation time 5124332405 ps
CPU time 29.66 seconds
Started Feb 07 01:04:22 PM PST 24
Finished Feb 07 01:04:52 PM PST 24
Peak memory 212792 kb
Host smart-0567a85f-2b46-4004-bbef-86d96f4099a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2316332340 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_smoke.2316332340
Directory /workspace/47.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/47.rom_ctrl_stress_all.4142131477
Short name T395
Test name
Test status
Simulation time 7595776052 ps
CPU time 92.9 seconds
Started Feb 07 01:04:12 PM PST 24
Finished Feb 07 01:05:46 PM PST 24
Peak memory 215236 kb
Host smart-369eec25-8acb-4601-9ba9-43e8f1743f93
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4142131477 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 47.rom_ctrl_stress_all.4142131477
Directory /workspace/47.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/48.rom_ctrl_alert_test.1591260470
Short name T242
Test name
Test status
Simulation time 524064253 ps
CPU time 5.09 seconds
Started Feb 07 01:04:26 PM PST 24
Finished Feb 07 01:04:31 PM PST 24
Peak memory 210568 kb
Host smart-cfe7dffb-a977-436a-8b09-0910135a8410
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1591260470 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_alert_test.1591260470
Directory /workspace/48.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/48.rom_ctrl_corrupt_sig_fatal_chk.111523268
Short name T333
Test name
Test status
Simulation time 3457681232 ps
CPU time 86.79 seconds
Started Feb 07 01:04:19 PM PST 24
Finished Feb 07 01:05:46 PM PST 24
Peak memory 226512 kb
Host smart-d648560e-c4b6-4e6b-b498-5ba14691bc37
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=111523268 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_c
orrupt_sig_fatal_chk.111523268
Directory /workspace/48.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/48.rom_ctrl_kmac_err_chk.3514267722
Short name T422
Test name
Test status
Simulation time 251092300 ps
CPU time 11.04 seconds
Started Feb 07 01:04:17 PM PST 24
Finished Feb 07 01:04:29 PM PST 24
Peak memory 210748 kb
Host smart-a8b71256-dc65-451a-85df-1117f2559790
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3514267722 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_kmac_err_chk.3514267722
Directory /workspace/48.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/48.rom_ctrl_max_throughput_chk.1220580248
Short name T1
Test name
Test status
Simulation time 1897544631 ps
CPU time 11.12 seconds
Started Feb 07 01:04:17 PM PST 24
Finished Feb 07 01:04:29 PM PST 24
Peak memory 210500 kb
Host smart-aeadaae0-051d-4982-82bd-b56869736fdd
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1220580248 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_max_throughput_chk.1220580248
Directory /workspace/48.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/48.rom_ctrl_smoke.2772509438
Short name T277
Test name
Test status
Simulation time 1858179012 ps
CPU time 22.02 seconds
Started Feb 07 01:04:12 PM PST 24
Finished Feb 07 01:04:34 PM PST 24
Peak memory 212548 kb
Host smart-a8df143e-888d-413a-85b0-3332fb12ace6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2772509438 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_smoke.2772509438
Directory /workspace/48.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/48.rom_ctrl_stress_all.1203506955
Short name T146
Test name
Test status
Simulation time 37839433225 ps
CPU time 74.84 seconds
Started Feb 07 01:04:15 PM PST 24
Finished Feb 07 01:05:30 PM PST 24
Peak memory 218664 kb
Host smart-67f28ad9-9db3-4bbc-a6db-8fa2162bca35
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1203506955 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 48.rom_ctrl_stress_all.1203506955
Directory /workspace/48.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/48.rom_ctrl_stress_all_with_rand_reset.1788189432
Short name T364
Test name
Test status
Simulation time 101025067405 ps
CPU time 6943.97 seconds
Started Feb 07 01:04:14 PM PST 24
Finished Feb 07 02:59:59 PM PST 24
Peak memory 238012 kb
Host smart-f489791d-4b19-448b-baf2-8a4a0415d68a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1788189432 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_stress_all_with_rand_reset.1788189432
Directory /workspace/48.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/49.rom_ctrl_alert_test.1879988536
Short name T391
Test name
Test status
Simulation time 85415687 ps
CPU time 4.22 seconds
Started Feb 07 01:04:27 PM PST 24
Finished Feb 07 01:04:32 PM PST 24
Peak memory 210592 kb
Host smart-d396c040-ead6-46e7-a503-01a76b7d15b9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1879988536 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_alert_test.1879988536
Directory /workspace/49.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/49.rom_ctrl_corrupt_sig_fatal_chk.392087289
Short name T348
Test name
Test status
Simulation time 8890650927 ps
CPU time 147.53 seconds
Started Feb 07 01:04:25 PM PST 24
Finished Feb 07 01:06:53 PM PST 24
Peak memory 233356 kb
Host smart-67aee251-c53d-4d2e-84fc-649954636933
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=392087289 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_c
orrupt_sig_fatal_chk.392087289
Directory /workspace/49.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/49.rom_ctrl_kmac_err_chk.1593833585
Short name T287
Test name
Test status
Simulation time 7350402362 ps
CPU time 27.22 seconds
Started Feb 07 01:04:27 PM PST 24
Finished Feb 07 01:04:55 PM PST 24
Peak memory 211420 kb
Host smart-20ec2d60-d866-4644-9418-b9e9bc6794f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1593833585 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_kmac_err_chk.1593833585
Directory /workspace/49.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/49.rom_ctrl_max_throughput_chk.390387510
Short name T161
Test name
Test status
Simulation time 2845757078 ps
CPU time 13.61 seconds
Started Feb 07 01:04:26 PM PST 24
Finished Feb 07 01:04:40 PM PST 24
Peak memory 210572 kb
Host smart-f2479a9a-795b-4d33-9165-aae8b1a3cf08
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=390387510 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_max_throughput_chk.390387510
Directory /workspace/49.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/49.rom_ctrl_smoke.3807371174
Short name T368
Test name
Test status
Simulation time 4025745905 ps
CPU time 17.01 seconds
Started Feb 07 01:04:32 PM PST 24
Finished Feb 07 01:04:53 PM PST 24
Peak memory 212596 kb
Host smart-dae78e0b-620a-4bd6-828e-05b98ca01179
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3807371174 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_smoke.3807371174
Directory /workspace/49.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/49.rom_ctrl_stress_all.732604993
Short name T93
Test name
Test status
Simulation time 7503163461 ps
CPU time 52.56 seconds
Started Feb 07 01:04:24 PM PST 24
Finished Feb 07 01:05:17 PM PST 24
Peak memory 215248 kb
Host smart-381f97ad-bb58-4446-b8f6-81fb4b90b5a1
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=732604993 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 49.rom_ctrl_stress_all.732604993
Directory /workspace/49.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/5.rom_ctrl_alert_test.3581762474
Short name T419
Test name
Test status
Simulation time 2431230691 ps
CPU time 8.48 seconds
Started Feb 07 01:01:41 PM PST 24
Finished Feb 07 01:01:50 PM PST 24
Peak memory 210640 kb
Host smart-4a9145e6-d81e-4aa9-875a-fab48af30def
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3581762474 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_alert_test.3581762474
Directory /workspace/5.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/5.rom_ctrl_corrupt_sig_fatal_chk.912483873
Short name T54
Test name
Test status
Simulation time 8877564391 ps
CPU time 179.18 seconds
Started Feb 07 01:01:40 PM PST 24
Finished Feb 07 01:04:40 PM PST 24
Peak memory 211804 kb
Host smart-6539a0c7-1f9e-4ffe-bfba-fb1afede0d55
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=912483873 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_co
rrupt_sig_fatal_chk.912483873
Directory /workspace/5.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/5.rom_ctrl_kmac_err_chk.3879473083
Short name T192
Test name
Test status
Simulation time 1879975489 ps
CPU time 21.12 seconds
Started Feb 07 01:01:41 PM PST 24
Finished Feb 07 01:02:03 PM PST 24
Peak memory 210764 kb
Host smart-2569d757-a867-4d31-a645-9f45c296ee0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3879473083 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_kmac_err_chk.3879473083
Directory /workspace/5.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/5.rom_ctrl_max_throughput_chk.1381736673
Short name T195
Test name
Test status
Simulation time 190106767 ps
CPU time 6.74 seconds
Started Feb 07 01:01:35 PM PST 24
Finished Feb 07 01:01:43 PM PST 24
Peak memory 210544 kb
Host smart-eb0b1672-8b5b-4e05-8cf7-2cc7255ec482
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1381736673 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_max_throughput_chk.1381736673
Directory /workspace/5.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/5.rom_ctrl_smoke.2705924285
Short name T308
Test name
Test status
Simulation time 1502322850 ps
CPU time 20.8 seconds
Started Feb 07 01:01:40 PM PST 24
Finished Feb 07 01:02:02 PM PST 24
Peak memory 212400 kb
Host smart-fea2204f-4cfc-4bfc-aa4c-c33fa37b0eb2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2705924285 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_smoke.2705924285
Directory /workspace/5.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/5.rom_ctrl_stress_all.520523227
Short name T228
Test name
Test status
Simulation time 4475312516 ps
CPU time 15.73 seconds
Started Feb 07 01:01:39 PM PST 24
Finished Feb 07 01:01:56 PM PST 24
Peak memory 211520 kb
Host smart-10394c8e-5893-4f4f-9de4-6880bdcc9e96
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=520523227 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 5.rom_ctrl_stress_all.520523227
Directory /workspace/5.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/5.rom_ctrl_stress_all_with_rand_reset.2239997437
Short name T393
Test name
Test status
Simulation time 25429958700 ps
CPU time 1349.34 seconds
Started Feb 07 01:01:39 PM PST 24
Finished Feb 07 01:24:09 PM PST 24
Peak memory 227480 kb
Host smart-1e323c69-7300-4b40-8c69-73cc1f37725b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2239997437 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_stress_all_with_rand_reset.2239997437
Directory /workspace/5.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.rom_ctrl_alert_test.3880530156
Short name T232
Test name
Test status
Simulation time 5719130942 ps
CPU time 13.02 seconds
Started Feb 07 01:01:55 PM PST 24
Finished Feb 07 01:02:09 PM PST 24
Peak memory 210600 kb
Host smart-57ceed94-f2f4-4d18-a173-a153a340f249
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3880530156 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_alert_test.3880530156
Directory /workspace/6.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/6.rom_ctrl_corrupt_sig_fatal_chk.2410764655
Short name T401
Test name
Test status
Simulation time 13196531094 ps
CPU time 246.82 seconds
Started Feb 07 01:01:40 PM PST 24
Finished Feb 07 01:05:47 PM PST 24
Peak memory 227452 kb
Host smart-b6058576-2c0d-4a68-a4f4-d66954259fd5
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2410764655 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_c
orrupt_sig_fatal_chk.2410764655
Directory /workspace/6.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/6.rom_ctrl_kmac_err_chk.3053483942
Short name T293
Test name
Test status
Simulation time 2898773474 ps
CPU time 27.38 seconds
Started Feb 07 01:01:37 PM PST 24
Finished Feb 07 01:02:05 PM PST 24
Peak memory 210688 kb
Host smart-fab6c80b-30a5-4215-8461-cd6a7e9eb1f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3053483942 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_kmac_err_chk.3053483942
Directory /workspace/6.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/6.rom_ctrl_max_throughput_chk.1258043623
Short name T279
Test name
Test status
Simulation time 1483504212 ps
CPU time 14.06 seconds
Started Feb 07 01:01:41 PM PST 24
Finished Feb 07 01:01:56 PM PST 24
Peak memory 210516 kb
Host smart-1cdd9252-3bce-447a-9c12-4f627fb054fb
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1258043623 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_max_throughput_chk.1258043623
Directory /workspace/6.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/6.rom_ctrl_smoke.2050144696
Short name T412
Test name
Test status
Simulation time 958738134 ps
CPU time 17.7 seconds
Started Feb 07 01:01:39 PM PST 24
Finished Feb 07 01:01:57 PM PST 24
Peak memory 211660 kb
Host smart-4a7c403c-c138-42a1-85bd-9a88d64484f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2050144696 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_smoke.2050144696
Directory /workspace/6.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/6.rom_ctrl_stress_all.777937828
Short name T9
Test name
Test status
Simulation time 16886838792 ps
CPU time 81.37 seconds
Started Feb 07 01:01:40 PM PST 24
Finished Feb 07 01:03:02 PM PST 24
Peak memory 213792 kb
Host smart-bbe8c5be-2d5e-468d-a5a6-7b5a4c81d24a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=777937828 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 6.rom_ctrl_stress_all.777937828
Directory /workspace/6.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/7.rom_ctrl_alert_test.1000911754
Short name T218
Test name
Test status
Simulation time 278009576 ps
CPU time 4.21 seconds
Started Feb 07 01:01:53 PM PST 24
Finished Feb 07 01:01:57 PM PST 24
Peak memory 210528 kb
Host smart-9292a68a-a96f-440a-9b14-b8b2935b246a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1000911754 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_alert_test.1000911754
Directory /workspace/7.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/7.rom_ctrl_corrupt_sig_fatal_chk.2282917929
Short name T303
Test name
Test status
Simulation time 7550610021 ps
CPU time 114.49 seconds
Started Feb 07 01:01:52 PM PST 24
Finished Feb 07 01:03:47 PM PST 24
Peak memory 233048 kb
Host smart-df8a9cc0-70be-4e99-8b5f-b79fdbe9dfb1
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2282917929 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_c
orrupt_sig_fatal_chk.2282917929
Directory /workspace/7.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/7.rom_ctrl_kmac_err_chk.46410403
Short name T316
Test name
Test status
Simulation time 476415835 ps
CPU time 9.47 seconds
Started Feb 07 01:01:53 PM PST 24
Finished Feb 07 01:02:03 PM PST 24
Peak memory 210764 kb
Host smart-4a70c07b-c701-4414-9bce-63a4fe1b30c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=46410403 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_kmac_err_chk.46410403
Directory /workspace/7.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/7.rom_ctrl_max_throughput_chk.1574571231
Short name T162
Test name
Test status
Simulation time 3871317187 ps
CPU time 15.82 seconds
Started Feb 07 01:01:52 PM PST 24
Finished Feb 07 01:02:09 PM PST 24
Peak memory 210596 kb
Host smart-d1665a15-f904-4bc8-adfe-fe262007f04a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1574571231 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_max_throughput_chk.1574571231
Directory /workspace/7.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/7.rom_ctrl_smoke.1216060409
Short name T97
Test name
Test status
Simulation time 12950513295 ps
CPU time 32.01 seconds
Started Feb 07 01:01:52 PM PST 24
Finished Feb 07 01:02:24 PM PST 24
Peak memory 212992 kb
Host smart-fedacff5-2caa-4d23-b4dc-acde97510b4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1216060409 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_smoke.1216060409
Directory /workspace/7.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/7.rom_ctrl_stress_all.986717989
Short name T349
Test name
Test status
Simulation time 486186020 ps
CPU time 9.25 seconds
Started Feb 07 01:01:51 PM PST 24
Finished Feb 07 01:02:01 PM PST 24
Peak memory 210532 kb
Host smart-5ee06ade-d6cc-4a23-bf7d-e51b0126aa54
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=986717989 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 7.rom_ctrl_stress_all.986717989
Directory /workspace/7.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/8.rom_ctrl_alert_test.796324550
Short name T405
Test name
Test status
Simulation time 1640412358 ps
CPU time 11.24 seconds
Started Feb 07 01:01:51 PM PST 24
Finished Feb 07 01:02:02 PM PST 24
Peak memory 210516 kb
Host smart-12388ea8-be76-4730-9dfa-44676774795c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=796324550 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_alert_test.796324550
Directory /workspace/8.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/8.rom_ctrl_corrupt_sig_fatal_chk.4145479775
Short name T341
Test name
Test status
Simulation time 55633673702 ps
CPU time 510.24 seconds
Started Feb 07 01:01:54 PM PST 24
Finished Feb 07 01:10:25 PM PST 24
Peak memory 225960 kb
Host smart-e2eaa610-defd-4901-8c58-bcef43d53959
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4145479775 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_c
orrupt_sig_fatal_chk.4145479775
Directory /workspace/8.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/8.rom_ctrl_kmac_err_chk.3950366046
Short name T206
Test name
Test status
Simulation time 1266019931 ps
CPU time 17.29 seconds
Started Feb 07 01:01:52 PM PST 24
Finished Feb 07 01:02:10 PM PST 24
Peak memory 210896 kb
Host smart-7ed6b375-7f4e-4783-83f9-8a5561547dd5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3950366046 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_kmac_err_chk.3950366046
Directory /workspace/8.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/8.rom_ctrl_max_throughput_chk.72601086
Short name T239
Test name
Test status
Simulation time 186228278 ps
CPU time 5.44 seconds
Started Feb 07 01:01:52 PM PST 24
Finished Feb 07 01:01:58 PM PST 24
Peak memory 210492 kb
Host smart-282f7c86-affe-4fc3-bff3-8562ef26f49a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=72601086 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_max_throughput_chk.72601086
Directory /workspace/8.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/8.rom_ctrl_smoke.3942856050
Short name T375
Test name
Test status
Simulation time 3855128685 ps
CPU time 29.59 seconds
Started Feb 07 01:01:53 PM PST 24
Finished Feb 07 01:02:23 PM PST 24
Peak memory 212016 kb
Host smart-7e062025-59b7-4001-b7e9-9cb8f5cff122
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3942856050 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_smoke.3942856050
Directory /workspace/8.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/8.rom_ctrl_stress_all.4035465931
Short name T339
Test name
Test status
Simulation time 297607345 ps
CPU time 16.49 seconds
Started Feb 07 01:01:52 PM PST 24
Finished Feb 07 01:02:09 PM PST 24
Peak memory 212440 kb
Host smart-49147ae1-694f-4215-9d0e-7db2637801f4
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4035465931 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 8.rom_ctrl_stress_all.4035465931
Directory /workspace/8.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/9.rom_ctrl_alert_test.2727477882
Short name T243
Test name
Test status
Simulation time 1299195645 ps
CPU time 6.49 seconds
Started Feb 07 01:01:51 PM PST 24
Finished Feb 07 01:01:59 PM PST 24
Peak memory 210556 kb
Host smart-caee5cb7-96ea-4b68-98e8-ea9c6b9a01fb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2727477882 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_alert_test.2727477882
Directory /workspace/9.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/9.rom_ctrl_corrupt_sig_fatal_chk.3540525890
Short name T338
Test name
Test status
Simulation time 9708946269 ps
CPU time 82.63 seconds
Started Feb 07 01:01:53 PM PST 24
Finished Feb 07 01:03:16 PM PST 24
Peak memory 233008 kb
Host smart-7cabcf93-ddfd-4ac2-9b8d-ad2a1d04279a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3540525890 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_c
orrupt_sig_fatal_chk.3540525890
Directory /workspace/9.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/9.rom_ctrl_kmac_err_chk.3096176989
Short name T24
Test name
Test status
Simulation time 3858569780 ps
CPU time 30.55 seconds
Started Feb 07 01:01:54 PM PST 24
Finished Feb 07 01:02:25 PM PST 24
Peak memory 210780 kb
Host smart-18995d5a-1277-4d36-adea-a4662d0d9474
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3096176989 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_kmac_err_chk.3096176989
Directory /workspace/9.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/9.rom_ctrl_max_throughput_chk.2889633047
Short name T331
Test name
Test status
Simulation time 23656341016 ps
CPU time 16.66 seconds
Started Feb 07 01:01:52 PM PST 24
Finished Feb 07 01:02:09 PM PST 24
Peak memory 210560 kb
Host smart-5e5fe656-fc11-44e1-a4e5-1ce9e5aa514c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2889633047 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_max_throughput_chk.2889633047
Directory /workspace/9.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/9.rom_ctrl_smoke.1300132055
Short name T329
Test name
Test status
Simulation time 1346524566 ps
CPU time 9.77 seconds
Started Feb 07 01:01:54 PM PST 24
Finished Feb 07 01:02:05 PM PST 24
Peak memory 212348 kb
Host smart-e709c0a4-af10-4dc4-9bc9-47e49fcfc303
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1300132055 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_smoke.1300132055
Directory /workspace/9.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/9.rom_ctrl_stress_all.3817329980
Short name T14
Test name
Test status
Simulation time 8458815499 ps
CPU time 73.53 seconds
Started Feb 07 01:01:51 PM PST 24
Finished Feb 07 01:03:05 PM PST 24
Peak memory 215244 kb
Host smart-e5438ba5-6424-4d10-bf18-af37ab01397f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3817329980 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 9.rom_ctrl_stress_all.3817329980
Directory /workspace/9.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/9.rom_ctrl_stress_all_with_rand_reset.1985662297
Short name T411
Test name
Test status
Simulation time 74739553344 ps
CPU time 1985.36 seconds
Started Feb 07 01:01:51 PM PST 24
Finished Feb 07 01:34:57 PM PST 24
Peak memory 235228 kb
Host smart-59cae93a-e436-4fc7-8903-f2db6b51e183
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1985662297 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_stress_all_with_rand_reset.1985662297
Directory /workspace/9.rom_ctrl_stress_all_with_rand_reset/latest
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