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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
97.61 97.04 92.80 97.88 100.00 98.69 98.04 98.84


Total test records in report: 464
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T298 /workspace/coverage/default/21.rom_ctrl_corrupt_sig_fatal_chk.2233648463 Feb 25 12:37:56 PM PST 24 Feb 25 12:40:05 PM PST 24 46756801698 ps
T299 /workspace/coverage/default/29.rom_ctrl_kmac_err_chk.1208515545 Feb 25 12:38:27 PM PST 24 Feb 25 12:38:50 PM PST 24 2126277579 ps
T300 /workspace/coverage/default/15.rom_ctrl_alert_test.58715063 Feb 25 12:37:54 PM PST 24 Feb 25 12:38:06 PM PST 24 5064866260 ps
T301 /workspace/coverage/default/23.rom_ctrl_smoke.2075260254 Feb 25 12:37:56 PM PST 24 Feb 25 12:38:32 PM PST 24 3953082193 ps
T302 /workspace/coverage/default/8.rom_ctrl_stress_all.4129854595 Feb 25 12:37:41 PM PST 24 Feb 25 12:37:58 PM PST 24 575604276 ps
T303 /workspace/coverage/default/41.rom_ctrl_kmac_err_chk.3244402045 Feb 25 12:38:16 PM PST 24 Feb 25 12:38:35 PM PST 24 5540853838 ps
T38 /workspace/coverage/default/4.rom_ctrl_sec_cm.3018902300 Feb 25 12:37:53 PM PST 24 Feb 25 12:40:00 PM PST 24 5117184364 ps
T304 /workspace/coverage/default/24.rom_ctrl_smoke.705023399 Feb 25 12:37:54 PM PST 24 Feb 25 12:38:05 PM PST 24 182965809 ps
T305 /workspace/coverage/default/7.rom_ctrl_alert_test.1086686317 Feb 25 12:37:56 PM PST 24 Feb 25 12:38:10 PM PST 24 5433178940 ps
T306 /workspace/coverage/default/30.rom_ctrl_smoke.2667206337 Feb 25 12:38:09 PM PST 24 Feb 25 12:38:43 PM PST 24 3745966283 ps
T307 /workspace/coverage/default/12.rom_ctrl_max_throughput_chk.2976891218 Feb 25 12:37:41 PM PST 24 Feb 25 12:37:59 PM PST 24 2228261384 ps
T308 /workspace/coverage/default/33.rom_ctrl_stress_all_with_rand_reset.3623659420 Feb 25 12:38:14 PM PST 24 Feb 25 01:37:10 PM PST 24 63605672328 ps
T309 /workspace/coverage/default/33.rom_ctrl_alert_test.918371241 Feb 25 12:38:11 PM PST 24 Feb 25 12:38:24 PM PST 24 7055839380 ps
T310 /workspace/coverage/default/42.rom_ctrl_stress_all_with_rand_reset.510912979 Feb 25 12:38:38 PM PST 24 Feb 25 12:52:34 PM PST 24 48211505850 ps
T311 /workspace/coverage/default/48.rom_ctrl_alert_test.1363467319 Feb 25 12:38:11 PM PST 24 Feb 25 12:38:16 PM PST 24 107286553 ps
T109 /workspace/coverage/default/34.rom_ctrl_stress_all_with_rand_reset.230807193 Feb 25 12:37:57 PM PST 24 Feb 25 12:44:53 PM PST 24 22501601214 ps
T312 /workspace/coverage/default/9.rom_ctrl_alert_test.118440763 Feb 25 12:37:54 PM PST 24 Feb 25 12:38:06 PM PST 24 5105241929 ps
T313 /workspace/coverage/default/15.rom_ctrl_corrupt_sig_fatal_chk.1740484065 Feb 25 12:37:54 PM PST 24 Feb 25 12:39:34 PM PST 24 5565129921 ps
T314 /workspace/coverage/default/40.rom_ctrl_corrupt_sig_fatal_chk.3180080090 Feb 25 12:38:13 PM PST 24 Feb 25 12:40:25 PM PST 24 20488803666 ps
T315 /workspace/coverage/default/8.rom_ctrl_kmac_err_chk.400555794 Feb 25 12:37:46 PM PST 24 Feb 25 12:38:07 PM PST 24 6788856771 ps
T316 /workspace/coverage/default/13.rom_ctrl_kmac_err_chk.3585131815 Feb 25 12:37:48 PM PST 24 Feb 25 12:38:19 PM PST 24 5941699897 ps
T317 /workspace/coverage/default/23.rom_ctrl_alert_test.2594649279 Feb 25 12:38:13 PM PST 24 Feb 25 12:38:30 PM PST 24 4091131623 ps
T318 /workspace/coverage/default/14.rom_ctrl_kmac_err_chk.597295252 Feb 25 12:37:55 PM PST 24 Feb 25 12:38:19 PM PST 24 2404029975 ps
T319 /workspace/coverage/default/26.rom_ctrl_stress_all.1221117829 Feb 25 12:38:11 PM PST 24 Feb 25 12:38:40 PM PST 24 10877949342 ps
T320 /workspace/coverage/default/34.rom_ctrl_kmac_err_chk.3864318251 Feb 25 12:38:14 PM PST 24 Feb 25 12:38:24 PM PST 24 340626543 ps
T321 /workspace/coverage/default/40.rom_ctrl_alert_test.2064540455 Feb 25 12:38:34 PM PST 24 Feb 25 12:38:45 PM PST 24 1992266450 ps
T322 /workspace/coverage/default/10.rom_ctrl_kmac_err_chk.1251504110 Feb 25 12:37:53 PM PST 24 Feb 25 12:38:25 PM PST 24 3649623949 ps
T323 /workspace/coverage/default/35.rom_ctrl_kmac_err_chk.525452397 Feb 25 12:37:59 PM PST 24 Feb 25 12:38:29 PM PST 24 14793266625 ps
T324 /workspace/coverage/default/6.rom_ctrl_smoke.715393756 Feb 25 12:37:41 PM PST 24 Feb 25 12:38:11 PM PST 24 5781288915 ps
T325 /workspace/coverage/default/47.rom_ctrl_stress_all.619821842 Feb 25 12:38:32 PM PST 24 Feb 25 12:38:52 PM PST 24 1386680386 ps
T326 /workspace/coverage/default/42.rom_ctrl_smoke.2824332882 Feb 25 12:38:11 PM PST 24 Feb 25 12:38:37 PM PST 24 2779276641 ps
T327 /workspace/coverage/default/24.rom_ctrl_max_throughput_chk.3788700736 Feb 25 12:37:55 PM PST 24 Feb 25 12:38:12 PM PST 24 8305967068 ps
T328 /workspace/coverage/default/5.rom_ctrl_max_throughput_chk.2183758912 Feb 25 12:38:05 PM PST 24 Feb 25 12:38:23 PM PST 24 8481948180 ps
T329 /workspace/coverage/default/22.rom_ctrl_stress_all.2806841427 Feb 25 12:37:54 PM PST 24 Feb 25 12:38:14 PM PST 24 1802237035 ps
T330 /workspace/coverage/default/45.rom_ctrl_max_throughput_chk.3789758225 Feb 25 12:38:19 PM PST 24 Feb 25 12:38:36 PM PST 24 9408908391 ps
T331 /workspace/coverage/default/36.rom_ctrl_stress_all.30423988 Feb 25 12:38:17 PM PST 24 Feb 25 12:38:25 PM PST 24 961032292 ps
T332 /workspace/coverage/default/5.rom_ctrl_alert_test.1346318181 Feb 25 12:37:50 PM PST 24 Feb 25 12:37:57 PM PST 24 1311099017 ps
T333 /workspace/coverage/default/38.rom_ctrl_corrupt_sig_fatal_chk.2351762445 Feb 25 12:38:08 PM PST 24 Feb 25 12:40:27 PM PST 24 2213047279 ps
T334 /workspace/coverage/default/5.rom_ctrl_corrupt_sig_fatal_chk.1727785257 Feb 25 12:37:46 PM PST 24 Feb 25 12:40:50 PM PST 24 35648266423 ps
T335 /workspace/coverage/default/44.rom_ctrl_kmac_err_chk.253052164 Feb 25 12:38:07 PM PST 24 Feb 25 12:38:40 PM PST 24 4033587801 ps
T336 /workspace/coverage/default/2.rom_ctrl_alert_test.1002040609 Feb 25 12:37:48 PM PST 24 Feb 25 12:37:52 PM PST 24 437201270 ps
T39 /workspace/coverage/default/2.rom_ctrl_sec_cm.59335590 Feb 25 12:37:50 PM PST 24 Feb 25 12:39:33 PM PST 24 2181840474 ps
T337 /workspace/coverage/default/10.rom_ctrl_max_throughput_chk.1286817566 Feb 25 12:37:53 PM PST 24 Feb 25 12:38:10 PM PST 24 2000454630 ps
T338 /workspace/coverage/default/37.rom_ctrl_kmac_err_chk.313842863 Feb 25 12:38:07 PM PST 24 Feb 25 12:38:27 PM PST 24 11126182179 ps
T339 /workspace/coverage/default/23.rom_ctrl_corrupt_sig_fatal_chk.2745101054 Feb 25 12:37:58 PM PST 24 Feb 25 12:40:30 PM PST 24 18134193727 ps
T340 /workspace/coverage/default/20.rom_ctrl_smoke.4266598484 Feb 25 12:38:02 PM PST 24 Feb 25 12:38:35 PM PST 24 35606750019 ps
T341 /workspace/coverage/default/4.rom_ctrl_stress_all.988045053 Feb 25 12:37:58 PM PST 24 Feb 25 12:38:10 PM PST 24 436796856 ps
T342 /workspace/coverage/default/32.rom_ctrl_max_throughput_chk.758401414 Feb 25 12:37:52 PM PST 24 Feb 25 12:38:08 PM PST 24 1889335130 ps
T343 /workspace/coverage/default/28.rom_ctrl_corrupt_sig_fatal_chk.3490135021 Feb 25 12:38:15 PM PST 24 Feb 25 12:39:30 PM PST 24 11076180872 ps
T344 /workspace/coverage/default/28.rom_ctrl_smoke.1846071549 Feb 25 12:38:16 PM PST 24 Feb 25 12:38:45 PM PST 24 10608677628 ps
T345 /workspace/coverage/default/29.rom_ctrl_max_throughput_chk.2333844576 Feb 25 12:38:00 PM PST 24 Feb 25 12:38:14 PM PST 24 1472501304 ps
T346 /workspace/coverage/default/15.rom_ctrl_max_throughput_chk.4182502779 Feb 25 12:38:08 PM PST 24 Feb 25 12:38:17 PM PST 24 967459721 ps
T347 /workspace/coverage/default/12.rom_ctrl_smoke.2944183764 Feb 25 12:37:49 PM PST 24 Feb 25 12:38:07 PM PST 24 1301497105 ps
T348 /workspace/coverage/default/37.rom_ctrl_max_throughput_chk.3090985642 Feb 25 12:38:20 PM PST 24 Feb 25 12:38:32 PM PST 24 5770296896 ps
T349 /workspace/coverage/default/2.rom_ctrl_kmac_err_chk.1175205549 Feb 25 12:37:32 PM PST 24 Feb 25 12:37:50 PM PST 24 10035499516 ps
T350 /workspace/coverage/default/16.rom_ctrl_max_throughput_chk.1154717397 Feb 25 12:38:11 PM PST 24 Feb 25 12:38:19 PM PST 24 1635666148 ps
T351 /workspace/coverage/default/7.rom_ctrl_stress_all_with_rand_reset.2670924957 Feb 25 12:37:56 PM PST 24 Feb 25 01:00:09 PM PST 24 36132840222 ps
T352 /workspace/coverage/default/16.rom_ctrl_corrupt_sig_fatal_chk.2171694238 Feb 25 12:38:00 PM PST 24 Feb 25 12:48:02 PM PST 24 62980502649 ps
T353 /workspace/coverage/default/17.rom_ctrl_corrupt_sig_fatal_chk.4292383369 Feb 25 12:37:55 PM PST 24 Feb 25 12:41:46 PM PST 24 34468107355 ps
T354 /workspace/coverage/default/20.rom_ctrl_corrupt_sig_fatal_chk.1659981175 Feb 25 12:38:19 PM PST 24 Feb 25 12:42:33 PM PST 24 19807903944 ps
T355 /workspace/coverage/default/44.rom_ctrl_max_throughput_chk.2280733492 Feb 25 12:38:20 PM PST 24 Feb 25 12:38:30 PM PST 24 864468472 ps
T356 /workspace/coverage/default/21.rom_ctrl_max_throughput_chk.2048892528 Feb 25 12:37:57 PM PST 24 Feb 25 12:38:03 PM PST 24 376147064 ps
T357 /workspace/coverage/default/18.rom_ctrl_stress_all.2186166346 Feb 25 12:37:58 PM PST 24 Feb 25 12:38:58 PM PST 24 24081461892 ps
T358 /workspace/coverage/default/45.rom_ctrl_corrupt_sig_fatal_chk.43449460 Feb 25 12:38:05 PM PST 24 Feb 25 12:41:59 PM PST 24 148381064299 ps
T359 /workspace/coverage/default/6.rom_ctrl_stress_all.231063035 Feb 25 12:37:45 PM PST 24 Feb 25 12:38:07 PM PST 24 387432365 ps
T360 /workspace/coverage/default/0.rom_ctrl_kmac_err_chk.3561412667 Feb 25 12:37:42 PM PST 24 Feb 25 12:38:00 PM PST 24 11664514330 ps
T361 /workspace/coverage/default/28.rom_ctrl_max_throughput_chk.4213613795 Feb 25 12:38:00 PM PST 24 Feb 25 12:38:09 PM PST 24 946718228 ps
T362 /workspace/coverage/default/45.rom_ctrl_alert_test.1214903950 Feb 25 12:38:36 PM PST 24 Feb 25 12:38:47 PM PST 24 10615784789 ps
T363 /workspace/coverage/default/0.rom_ctrl_alert_test.2054578509 Feb 25 12:37:42 PM PST 24 Feb 25 12:37:58 PM PST 24 9987010503 ps
T65 /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_rw.1342116145 Feb 25 12:29:17 PM PST 24 Feb 25 12:29:22 PM PST 24 174741979 ps
T66 /workspace/coverage/cover_reg_top/18.rom_ctrl_passthru_mem_tl_intg_err.1451390143 Feb 25 12:29:18 PM PST 24 Feb 25 12:30:21 PM PST 24 24652251736 ps
T67 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_aliasing.310151224 Feb 25 12:29:06 PM PST 24 Feb 25 12:29:21 PM PST 24 5097743760 ps
T72 /workspace/coverage/cover_reg_top/0.rom_ctrl_same_csr_outstanding.3942497570 Feb 25 12:29:18 PM PST 24 Feb 25 12:29:34 PM PST 24 1626113156 ps
T73 /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_rw.1135631671 Feb 25 12:29:14 PM PST 24 Feb 25 12:29:24 PM PST 24 3621265819 ps
T364 /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_mem_rw_with_rand_reset.2762281057 Feb 25 12:29:21 PM PST 24 Feb 25 12:29:35 PM PST 24 6212468396 ps
T74 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_rw.946253918 Feb 25 12:29:08 PM PST 24 Feb 25 12:29:24 PM PST 24 2076207106 ps
T62 /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_intg_err.603250195 Feb 25 12:29:21 PM PST 24 Feb 25 12:30:46 PM PST 24 13705776836 ps
T75 /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_rw.3309115367 Feb 25 12:29:38 PM PST 24 Feb 25 12:29:46 PM PST 24 574035379 ps
T365 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_bit_bash.362200480 Feb 25 12:29:05 PM PST 24 Feb 25 12:29:10 PM PST 24 438966030 ps
T366 /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_partial_access.2329942606 Feb 25 12:29:18 PM PST 24 Feb 25 12:29:23 PM PST 24 168079786 ps
T367 /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_errors.1672524998 Feb 25 12:29:12 PM PST 24 Feb 25 12:29:28 PM PST 24 3172432145 ps
T76 /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_rw.491139343 Feb 25 12:29:18 PM PST 24 Feb 25 12:29:27 PM PST 24 5404681938 ps
T77 /workspace/coverage/cover_reg_top/1.rom_ctrl_passthru_mem_tl_intg_err.867222490 Feb 25 12:29:17 PM PST 24 Feb 25 12:30:02 PM PST 24 18600700793 ps
T104 /workspace/coverage/cover_reg_top/1.rom_ctrl_same_csr_outstanding.208568250 Feb 25 12:29:06 PM PST 24 Feb 25 12:29:11 PM PST 24 592353374 ps
T78 /workspace/coverage/cover_reg_top/0.rom_ctrl_passthru_mem_tl_intg_err.3910991217 Feb 25 12:29:06 PM PST 24 Feb 25 12:29:26 PM PST 24 411877648 ps
T63 /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_intg_err.2613426258 Feb 25 12:29:29 PM PST 24 Feb 25 12:30:11 PM PST 24 1841064846 ps
T105 /workspace/coverage/cover_reg_top/15.rom_ctrl_same_csr_outstanding.2164691514 Feb 25 12:29:06 PM PST 24 Feb 25 12:29:16 PM PST 24 20577841085 ps
T368 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_mem_rw_with_rand_reset.1571512340 Feb 25 12:29:21 PM PST 24 Feb 25 12:29:33 PM PST 24 1011887627 ps
T64 /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_intg_err.28236465 Feb 25 12:29:30 PM PST 24 Feb 25 12:30:08 PM PST 24 816271994 ps
T369 /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_errors.1837113709 Feb 25 12:29:34 PM PST 24 Feb 25 12:29:51 PM PST 24 6495168686 ps
T370 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_aliasing.55606936 Feb 25 12:29:07 PM PST 24 Feb 25 12:29:19 PM PST 24 1929239680 ps
T371 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_bit_bash.2773767023 Feb 25 12:29:10 PM PST 24 Feb 25 12:29:25 PM PST 24 6759273952 ps
T112 /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_intg_err.993953908 Feb 25 12:29:02 PM PST 24 Feb 25 12:29:46 PM PST 24 4684604057 ps
T372 /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_rw.3741270604 Feb 25 12:29:29 PM PST 24 Feb 25 12:29:40 PM PST 24 3243401914 ps
T373 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_mem_rw_with_rand_reset.2076193861 Feb 25 12:29:05 PM PST 24 Feb 25 12:29:23 PM PST 24 8009343220 ps
T106 /workspace/coverage/cover_reg_top/11.rom_ctrl_same_csr_outstanding.2709356050 Feb 25 12:29:07 PM PST 24 Feb 25 12:29:23 PM PST 24 1739439656 ps
T374 /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_walk.148360677 Feb 25 12:29:16 PM PST 24 Feb 25 12:29:27 PM PST 24 4285150124 ps
T375 /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_errors.2706644828 Feb 25 12:29:06 PM PST 24 Feb 25 12:29:13 PM PST 24 88404268 ps
T376 /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_errors.1515844788 Feb 25 12:29:21 PM PST 24 Feb 25 12:29:37 PM PST 24 2617645686 ps
T377 /workspace/coverage/cover_reg_top/8.rom_ctrl_passthru_mem_tl_intg_err.430025860 Feb 25 12:29:22 PM PST 24 Feb 25 12:30:41 PM PST 24 9184284790 ps
T113 /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_intg_err.1124817852 Feb 25 12:29:33 PM PST 24 Feb 25 12:30:16 PM PST 24 6325485693 ps
T378 /workspace/coverage/cover_reg_top/10.rom_ctrl_passthru_mem_tl_intg_err.1991483613 Feb 25 12:29:11 PM PST 24 Feb 25 12:30:01 PM PST 24 3239600299 ps
T379 /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_errors.1798907827 Feb 25 12:29:06 PM PST 24 Feb 25 12:29:14 PM PST 24 89572427 ps
T84 /workspace/coverage/cover_reg_top/14.rom_ctrl_passthru_mem_tl_intg_err.237875445 Feb 25 12:29:18 PM PST 24 Feb 25 12:30:45 PM PST 24 39394403101 ps
T380 /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_walk.3327695732 Feb 25 12:29:22 PM PST 24 Feb 25 12:29:27 PM PST 24 175144680 ps
T381 /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_rw.1524373502 Feb 25 12:29:19 PM PST 24 Feb 25 12:29:34 PM PST 24 2159124343 ps
T382 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_aliasing.901088548 Feb 25 12:29:22 PM PST 24 Feb 25 12:29:28 PM PST 24 426359762 ps
T383 /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_mem_rw_with_rand_reset.466321354 Feb 25 12:29:05 PM PST 24 Feb 25 12:29:23 PM PST 24 8066923689 ps
T85 /workspace/coverage/cover_reg_top/19.rom_ctrl_passthru_mem_tl_intg_err.2746871453 Feb 25 12:29:22 PM PST 24 Feb 25 12:30:03 PM PST 24 20762308689 ps
T91 /workspace/coverage/cover_reg_top/16.rom_ctrl_passthru_mem_tl_intg_err.3327991695 Feb 25 12:29:20 PM PST 24 Feb 25 12:29:38 PM PST 24 4418676091 ps
T384 /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_mem_rw_with_rand_reset.679795988 Feb 25 12:29:07 PM PST 24 Feb 25 12:29:19 PM PST 24 4480996963 ps
T117 /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_intg_err.340304605 Feb 25 12:29:08 PM PST 24 Feb 25 12:29:53 PM PST 24 1597101428 ps
T385 /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_walk.1555876256 Feb 25 12:29:05 PM PST 24 Feb 25 12:29:09 PM PST 24 87956010 ps
T386 /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_mem_rw_with_rand_reset.2399732468 Feb 25 12:29:08 PM PST 24 Feb 25 12:29:19 PM PST 24 16381904962 ps
T121 /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_intg_err.431793866 Feb 25 12:29:21 PM PST 24 Feb 25 12:30:08 PM PST 24 1713312624 ps
T387 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_mem_rw_with_rand_reset.489537734 Feb 25 12:29:17 PM PST 24 Feb 25 12:29:22 PM PST 24 186524578 ps
T388 /workspace/coverage/cover_reg_top/13.rom_ctrl_same_csr_outstanding.2449527217 Feb 25 12:29:20 PM PST 24 Feb 25 12:29:36 PM PST 24 302637337 ps
T126 /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_intg_err.4051843046 Feb 25 12:29:33 PM PST 24 Feb 25 12:30:10 PM PST 24 591813012 ps
T86 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_hw_reset.2530742666 Feb 25 12:29:15 PM PST 24 Feb 25 12:29:21 PM PST 24 88686602 ps
T389 /workspace/coverage/cover_reg_top/6.rom_ctrl_same_csr_outstanding.2053563362 Feb 25 12:29:18 PM PST 24 Feb 25 12:29:27 PM PST 24 744954573 ps
T390 /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_partial_access.992105606 Feb 25 12:29:04 PM PST 24 Feb 25 12:29:15 PM PST 24 6364794082 ps
T118 /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_intg_err.2621569400 Feb 25 12:29:07 PM PST 24 Feb 25 12:29:45 PM PST 24 2914031171 ps
T391 /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_errors.1250440768 Feb 25 12:29:09 PM PST 24 Feb 25 12:29:16 PM PST 24 333620937 ps
T392 /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_errors.2091225582 Feb 25 12:29:17 PM PST 24 Feb 25 12:29:29 PM PST 24 666357223 ps
T393 /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_partial_access.4254388809 Feb 25 12:29:22 PM PST 24 Feb 25 12:29:32 PM PST 24 901205141 ps
T394 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_rw.1839081042 Feb 25 12:29:17 PM PST 24 Feb 25 12:29:33 PM PST 24 1890218991 ps
T395 /workspace/coverage/cover_reg_top/12.rom_ctrl_same_csr_outstanding.3409549192 Feb 25 12:30:00 PM PST 24 Feb 25 12:30:06 PM PST 24 169646789 ps
T396 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_bit_bash.4072356173 Feb 25 12:29:20 PM PST 24 Feb 25 12:29:30 PM PST 24 2923821400 ps
T87 /workspace/coverage/cover_reg_top/17.rom_ctrl_passthru_mem_tl_intg_err.3012511212 Feb 25 12:29:21 PM PST 24 Feb 25 12:30:45 PM PST 24 10021422664 ps
T397 /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_mem_rw_with_rand_reset.3170399445 Feb 25 12:29:20 PM PST 24 Feb 25 12:29:28 PM PST 24 475650374 ps
T398 /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_mem_rw_with_rand_reset.342615813 Feb 25 12:29:14 PM PST 24 Feb 25 12:29:23 PM PST 24 2200153738 ps
T399 /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_rw.3407670909 Feb 25 12:29:23 PM PST 24 Feb 25 12:29:39 PM PST 24 8541718315 ps
T400 /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_mem_rw_with_rand_reset.2656277580 Feb 25 12:29:09 PM PST 24 Feb 25 12:29:16 PM PST 24 224497424 ps
T401 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_bit_bash.3350058831 Feb 25 12:29:08 PM PST 24 Feb 25 12:29:17 PM PST 24 689237436 ps
T402 /workspace/coverage/cover_reg_top/2.rom_ctrl_passthru_mem_tl_intg_err.1382201219 Feb 25 12:29:07 PM PST 24 Feb 25 12:29:27 PM PST 24 729738982 ps
T403 /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_rw.1507238833 Feb 25 12:29:45 PM PST 24 Feb 25 12:29:56 PM PST 24 2087160884 ps
T404 /workspace/coverage/cover_reg_top/9.rom_ctrl_same_csr_outstanding.3759534122 Feb 25 12:29:24 PM PST 24 Feb 25 12:29:38 PM PST 24 6087133652 ps
T405 /workspace/coverage/cover_reg_top/5.rom_ctrl_same_csr_outstanding.3691275318 Feb 25 12:29:05 PM PST 24 Feb 25 12:29:18 PM PST 24 1475865621 ps
T406 /workspace/coverage/cover_reg_top/9.rom_ctrl_passthru_mem_tl_intg_err.1562838133 Feb 25 12:29:17 PM PST 24 Feb 25 12:30:02 PM PST 24 4618723838 ps
T110 /workspace/coverage/cover_reg_top/7.rom_ctrl_passthru_mem_tl_intg_err.1596201126 Feb 25 12:29:05 PM PST 24 Feb 25 12:30:04 PM PST 24 7136568427 ps
T407 /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_rw.3462893322 Feb 25 12:29:06 PM PST 24 Feb 25 12:29:10 PM PST 24 395789586 ps
T408 /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_mem_rw_with_rand_reset.551792611 Feb 25 12:29:07 PM PST 24 Feb 25 12:29:20 PM PST 24 1382327617 ps
T119 /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_intg_err.3354348965 Feb 25 12:29:08 PM PST 24 Feb 25 12:30:18 PM PST 24 909327788 ps
T409 /workspace/coverage/cover_reg_top/8.rom_ctrl_same_csr_outstanding.1485627897 Feb 25 12:29:05 PM PST 24 Feb 25 12:29:20 PM PST 24 10955056410 ps
T410 /workspace/coverage/cover_reg_top/2.rom_ctrl_same_csr_outstanding.364242813 Feb 25 12:29:17 PM PST 24 Feb 25 12:29:32 PM PST 24 4730472019 ps
T411 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_hw_reset.1236507256 Feb 25 12:29:08 PM PST 24 Feb 25 12:29:27 PM PST 24 8262530713 ps
T412 /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_mem_rw_with_rand_reset.2297073886 Feb 25 12:29:25 PM PST 24 Feb 25 12:29:30 PM PST 24 1565345889 ps
T413 /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_mem_rw_with_rand_reset.1929935189 Feb 25 12:29:48 PM PST 24 Feb 25 12:30:04 PM PST 24 1742513382 ps
T414 /workspace/coverage/cover_reg_top/18.rom_ctrl_same_csr_outstanding.890647013 Feb 25 12:29:29 PM PST 24 Feb 25 12:29:36 PM PST 24 100975339 ps
T88 /workspace/coverage/cover_reg_top/5.rom_ctrl_passthru_mem_tl_intg_err.3997490074 Feb 25 12:29:30 PM PST 24 Feb 25 12:29:58 PM PST 24 1213149555 ps
T415 /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_errors.4046896831 Feb 25 12:29:09 PM PST 24 Feb 25 12:29:27 PM PST 24 6703499557 ps
T416 /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_partial_access.774147445 Feb 25 12:29:06 PM PST 24 Feb 25 12:29:18 PM PST 24 1351657702 ps
T417 /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_errors.1295674934 Feb 25 12:29:02 PM PST 24 Feb 25 12:29:18 PM PST 24 6144984998 ps
T418 /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_rw.249603304 Feb 25 12:29:21 PM PST 24 Feb 25 12:29:25 PM PST 24 85416464 ps
T419 /workspace/coverage/cover_reg_top/4.rom_ctrl_same_csr_outstanding.92574470 Feb 25 12:29:14 PM PST 24 Feb 25 12:29:21 PM PST 24 413265600 ps
T420 /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_partial_access.3918074111 Feb 25 12:29:06 PM PST 24 Feb 25 12:29:20 PM PST 24 2119626924 ps
T421 /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_errors.248725757 Feb 25 12:29:06 PM PST 24 Feb 25 12:29:23 PM PST 24 1556355385 ps
T422 /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_errors.1014601249 Feb 25 12:29:28 PM PST 24 Feb 25 12:29:36 PM PST 24 128012434 ps
T423 /workspace/coverage/cover_reg_top/16.rom_ctrl_same_csr_outstanding.3483259975 Feb 25 12:29:11 PM PST 24 Feb 25 12:29:27 PM PST 24 8624623444 ps
T424 /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_errors.2870331666 Feb 25 12:29:28 PM PST 24 Feb 25 12:29:37 PM PST 24 307437122 ps
T425 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_rw.3935899614 Feb 25 12:29:03 PM PST 24 Feb 25 12:29:10 PM PST 24 257453128 ps
T426 /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_errors.2361216710 Feb 25 12:29:22 PM PST 24 Feb 25 12:29:29 PM PST 24 180002817 ps
T111 /workspace/coverage/cover_reg_top/6.rom_ctrl_passthru_mem_tl_intg_err.1474561147 Feb 25 12:29:21 PM PST 24 Feb 25 12:30:22 PM PST 24 11360931465 ps
T427 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_hw_reset.2149646651 Feb 25 12:29:15 PM PST 24 Feb 25 12:29:25 PM PST 24 4552212826 ps
T428 /workspace/coverage/cover_reg_top/7.rom_ctrl_same_csr_outstanding.2614513053 Feb 25 12:29:19 PM PST 24 Feb 25 12:29:35 PM PST 24 8071910555 ps
T429 /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_mem_rw_with_rand_reset.3176798202 Feb 25 12:29:05 PM PST 24 Feb 25 12:29:17 PM PST 24 3188128272 ps
T430 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_rw.3401172393 Feb 25 12:29:19 PM PST 24 Feb 25 12:29:36 PM PST 24 13110545006 ps
T431 /workspace/coverage/cover_reg_top/10.rom_ctrl_same_csr_outstanding.2364584998 Feb 25 12:29:23 PM PST 24 Feb 25 12:29:34 PM PST 24 7561754650 ps
T432 /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_mem_rw_with_rand_reset.4263931512 Feb 25 12:29:04 PM PST 24 Feb 25 12:29:12 PM PST 24 455838237 ps
T433 /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_mem_rw_with_rand_reset.2516342925 Feb 25 12:29:06 PM PST 24 Feb 25 12:29:14 PM PST 24 393014622 ps
T434 /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_mem_rw_with_rand_reset.3646508974 Feb 25 12:29:45 PM PST 24 Feb 25 12:29:52 PM PST 24 150616995 ps
T92 /workspace/coverage/cover_reg_top/3.rom_ctrl_passthru_mem_tl_intg_err.3972677226 Feb 25 12:29:20 PM PST 24 Feb 25 12:30:46 PM PST 24 42064590668 ps
T114 /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_intg_err.531810166 Feb 25 12:29:20 PM PST 24 Feb 25 12:30:29 PM PST 24 349351005 ps
T122 /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_intg_err.1944794445 Feb 25 12:29:33 PM PST 24 Feb 25 12:30:54 PM PST 24 2282084910 ps
T435 /workspace/coverage/cover_reg_top/14.rom_ctrl_same_csr_outstanding.1587353522 Feb 25 12:29:05 PM PST 24 Feb 25 12:29:21 PM PST 24 2085586939 ps
T115 /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_intg_err.815936332 Feb 25 12:29:11 PM PST 24 Feb 25 12:30:26 PM PST 24 955657496 ps
T436 /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_rw.2391151224 Feb 25 12:29:18 PM PST 24 Feb 25 12:29:29 PM PST 24 1845087827 ps
T437 /workspace/coverage/cover_reg_top/3.rom_ctrl_same_csr_outstanding.1319715457 Feb 25 12:29:15 PM PST 24 Feb 25 12:29:22 PM PST 24 860627935 ps
T127 /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_intg_err.2661977487 Feb 25 12:29:21 PM PST 24 Feb 25 12:30:29 PM PST 24 722993736 ps
T124 /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_intg_err.4225701839 Feb 25 12:29:07 PM PST 24 Feb 25 12:29:45 PM PST 24 166529048 ps
T438 /workspace/coverage/cover_reg_top/12.rom_ctrl_passthru_mem_tl_intg_err.1268695567 Feb 25 12:29:26 PM PST 24 Feb 25 12:30:09 PM PST 24 9822430093 ps
T123 /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_intg_err.739962955 Feb 25 12:29:35 PM PST 24 Feb 25 12:30:12 PM PST 24 1443178207 ps
T439 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_rw.485529483 Feb 25 12:29:08 PM PST 24 Feb 25 12:29:15 PM PST 24 2596269184 ps
T440 /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_rw.2128909285 Feb 25 12:29:24 PM PST 24 Feb 25 12:29:32 PM PST 24 9008206368 ps
T116 /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_intg_err.1510639390 Feb 25 12:29:22 PM PST 24 Feb 25 12:30:01 PM PST 24 470474792 ps
T441 /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_walk.2418596873 Feb 25 12:29:07 PM PST 24 Feb 25 12:29:17 PM PST 24 1176060955 ps
T442 /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_errors.2088327098 Feb 25 12:29:13 PM PST 24 Feb 25 12:29:19 PM PST 24 174802769 ps
T443 /workspace/coverage/cover_reg_top/4.rom_ctrl_passthru_mem_tl_intg_err.3870547386 Feb 25 12:29:18 PM PST 24 Feb 25 12:29:53 PM PST 24 5282467752 ps
T444 /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_errors.658741163 Feb 25 12:29:04 PM PST 24 Feb 25 12:29:13 PM PST 24 243412899 ps
T445 /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_walk.2744712414 Feb 25 12:29:03 PM PST 24 Feb 25 12:29:15 PM PST 24 18193539529 ps
T446 /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_rw.3315561315 Feb 25 12:29:26 PM PST 24 Feb 25 12:29:31 PM PST 24 86523785 ps
T447 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_mem_rw_with_rand_reset.2484179042 Feb 25 12:29:16 PM PST 24 Feb 25 12:29:38 PM PST 24 2154505544 ps
T448 /workspace/coverage/cover_reg_top/19.rom_ctrl_same_csr_outstanding.4235171495 Feb 25 12:29:24 PM PST 24 Feb 25 12:29:33 PM PST 24 819975064 ps
T449 /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_mem_rw_with_rand_reset.901495493 Feb 25 12:29:22 PM PST 24 Feb 25 12:29:33 PM PST 24 1014353002 ps
T450 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_mem_rw_with_rand_reset.1256008041 Feb 25 12:29:03 PM PST 24 Feb 25 12:29:13 PM PST 24 795853437 ps
T451 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_bit_bash.2366186003 Feb 25 12:29:22 PM PST 24 Feb 25 12:29:33 PM PST 24 2638696093 ps
T93 /workspace/coverage/cover_reg_top/15.rom_ctrl_passthru_mem_tl_intg_err.952887857 Feb 25 12:29:07 PM PST 24 Feb 25 12:29:36 PM PST 24 546690699 ps
T120 /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_intg_err.4273961297 Feb 25 12:29:18 PM PST 24 Feb 25 12:30:37 PM PST 24 12334106975 ps
T452 /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_errors.919965520 Feb 25 12:29:15 PM PST 24 Feb 25 12:29:24 PM PST 24 508255375 ps
T453 /workspace/coverage/cover_reg_top/11.rom_ctrl_passthru_mem_tl_intg_err.2242804951 Feb 25 12:29:33 PM PST 24 Feb 25 12:30:01 PM PST 24 548307727 ps
T454 /workspace/coverage/cover_reg_top/13.rom_ctrl_passthru_mem_tl_intg_err.666224327 Feb 25 12:29:05 PM PST 24 Feb 25 12:29:32 PM PST 24 2848965229 ps
T455 /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_errors.3323895783 Feb 25 12:29:22 PM PST 24 Feb 25 12:29:29 PM PST 24 89082115 ps
T89 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_aliasing.945854907 Feb 25 12:29:25 PM PST 24 Feb 25 12:29:32 PM PST 24 564160359 ps
T125 /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_intg_err.3161977888 Feb 25 12:29:04 PM PST 24 Feb 25 12:30:16 PM PST 24 738752674 ps
T456 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_hw_reset.3685552823 Feb 25 12:29:06 PM PST 24 Feb 25 12:29:21 PM PST 24 25365241792 ps
T457 /workspace/coverage/cover_reg_top/17.rom_ctrl_same_csr_outstanding.1200724788 Feb 25 12:29:14 PM PST 24 Feb 25 12:29:29 PM PST 24 6171523113 ps
T458 /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_intg_err.340129583 Feb 25 12:29:06 PM PST 24 Feb 25 12:30:21 PM PST 24 1270852615 ps
T459 /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_rw.1009286905 Feb 25 12:29:04 PM PST 24 Feb 25 12:29:18 PM PST 24 6696779227 ps
T460 /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_errors.954677337 Feb 25 12:29:18 PM PST 24 Feb 25 12:29:27 PM PST 24 1378673150 ps
T461 /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_errors.463510610 Feb 25 12:29:12 PM PST 24 Feb 25 12:29:26 PM PST 24 11547434933 ps
T462 /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_rw.1312583028 Feb 25 12:29:22 PM PST 24 Feb 25 12:29:40 PM PST 24 23740324089 ps
T90 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_aliasing.4074798059 Feb 25 12:29:11 PM PST 24 Feb 25 12:29:25 PM PST 24 6179879576 ps
T463 /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_errors.3728250752 Feb 25 12:29:34 PM PST 24 Feb 25 12:29:54 PM PST 24 3669025759 ps
T464 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_hw_reset.98539604 Feb 25 12:29:18 PM PST 24 Feb 25 12:29:33 PM PST 24 1541599433 ps

Test location /workspace/coverage/default/25.rom_ctrl_corrupt_sig_fatal_chk.2777553103
Short name T5
Test name
Test status
Simulation time 16419756726 ps
CPU time 112.94 seconds
Started Feb 25 12:38:02 PM PST 24
Finished Feb 25 12:39:56 PM PST 24
Peak memory 227756 kb
Host smart-cf9a2777-ace6-4259-8a6e-1ee8eb157a36
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2777553103 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_
corrupt_sig_fatal_chk.2777553103
Directory /workspace/25.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/43.rom_ctrl_stress_all_with_rand_reset.1107000522
Short name T13
Test name
Test status
Simulation time 129254800185 ps
CPU time 2829.75 seconds
Started Feb 25 12:38:17 PM PST 24
Finished Feb 25 01:25:27 PM PST 24
Peak memory 232608 kb
Host smart-a1bb8edc-7a9c-42e8-9191-9e3002a757d5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1107000522 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_stress_all_with_rand_reset.1107000522
Directory /workspace/43.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/16.rom_ctrl_smoke.2973768284
Short name T16
Test name
Test status
Simulation time 6288426176 ps
CPU time 20.09 seconds
Started Feb 25 12:38:02 PM PST 24
Finished Feb 25 12:38:23 PM PST 24
Peak memory 214276 kb
Host smart-f64d3911-f922-4edc-90b1-40f9fb6d18f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2973768284 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_smoke.2973768284
Directory /workspace/16.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/33.rom_ctrl_corrupt_sig_fatal_chk.1027356438
Short name T49
Test name
Test status
Simulation time 18385877996 ps
CPU time 223.56 seconds
Started Feb 25 12:38:08 PM PST 24
Finished Feb 25 12:41:52 PM PST 24
Peak memory 237792 kb
Host smart-787abe64-0087-4f77-a41a-4dcf134cdaa3
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1027356438 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_
corrupt_sig_fatal_chk.1027356438
Directory /workspace/33.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/12.rom_ctrl_stress_all_with_rand_reset.3227008899
Short name T17
Test name
Test status
Simulation time 23544848441 ps
CPU time 1612.92 seconds
Started Feb 25 12:38:07 PM PST 24
Finished Feb 25 01:05:00 PM PST 24
Peak memory 228496 kb
Host smart-a8520542-3ab1-4700-b095-5765cad97855
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3227008899 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_stress_all_with_rand_reset.3227008899
Directory /workspace/12.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_intg_err.28236465
Short name T64
Test name
Test status
Simulation time 816271994 ps
CPU time 37.93 seconds
Started Feb 25 12:29:30 PM PST 24
Finished Feb 25 12:30:08 PM PST 24
Peak memory 210584 kb
Host smart-59c4e0cf-f738-4639-85ab-170db09666bc
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28236465 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_tl_int
g_err.28236465
Directory /workspace/15.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/0.rom_ctrl_sec_cm.1247047261
Short name T33
Test name
Test status
Simulation time 372496388 ps
CPU time 102.42 seconds
Started Feb 25 12:37:39 PM PST 24
Finished Feb 25 12:39:22 PM PST 24
Peak memory 232628 kb
Host smart-1aa49c37-7bc0-4fa3-b42b-799d7c27981a
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1247047261 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_sec_cm.1247047261
Directory /workspace/0.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_intg_err.3354348965
Short name T119
Test name
Test status
Simulation time 909327788 ps
CPU time 69.37 seconds
Started Feb 25 12:29:08 PM PST 24
Finished Feb 25 12:30:18 PM PST 24
Peak memory 210584 kb
Host smart-c6fde1e6-8a1e-4389-addd-19cb98f19ec9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3354348965 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_tl_i
ntg_err.3354348965
Directory /workspace/10.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_passthru_mem_tl_intg_err.237875445
Short name T84
Test name
Test status
Simulation time 39394403101 ps
CPU time 86.68 seconds
Started Feb 25 12:29:18 PM PST 24
Finished Feb 25 12:30:45 PM PST 24
Peak memory 210604 kb
Host smart-06e32dde-d70a-4e33-8ee4-8efdf7fdc010
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=237875445 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_pa
ssthru_mem_tl_intg_err.237875445
Directory /workspace/14.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/default/34.rom_ctrl_stress_all_with_rand_reset.230807193
Short name T109
Test name
Test status
Simulation time 22501601214 ps
CPU time 415.73 seconds
Started Feb 25 12:37:57 PM PST 24
Finished Feb 25 12:44:53 PM PST 24
Peak memory 224340 kb
Host smart-dfb14645-fef6-4b6d-847d-483936abc4f0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=230807193 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_stress_all_with_rand_reset.230807193
Directory /workspace/34.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.rom_ctrl_alert_test.1557941972
Short name T3
Test name
Test status
Simulation time 2257725822 ps
CPU time 16.77 seconds
Started Feb 25 12:37:53 PM PST 24
Finished Feb 25 12:38:10 PM PST 24
Peak memory 211144 kb
Host smart-ffa81816-7722-4574-82eb-6b64d7978833
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1557941972 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_alert_test.1557941972
Directory /workspace/1.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/11.rom_ctrl_kmac_err_chk.274676139
Short name T22
Test name
Test status
Simulation time 665804580 ps
CPU time 9.57 seconds
Started Feb 25 12:37:58 PM PST 24
Finished Feb 25 12:38:07 PM PST 24
Peak memory 211024 kb
Host smart-934fe524-7f24-4917-8ff8-834d4cd64421
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=274676139 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_kmac_err_chk.274676139
Directory /workspace/11.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/16.rom_ctrl_kmac_err_chk.2386130610
Short name T26
Test name
Test status
Simulation time 5644782043 ps
CPU time 15.81 seconds
Started Feb 25 12:37:52 PM PST 24
Finished Feb 25 12:38:08 PM PST 24
Peak memory 211832 kb
Host smart-b7c0edb4-9e80-4eaa-a1d6-2424de838942
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2386130610 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_kmac_err_chk.2386130610
Directory /workspace/16.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/18.rom_ctrl_kmac_err_chk.2985353461
Short name T150
Test name
Test status
Simulation time 3512841751 ps
CPU time 30 seconds
Started Feb 25 12:37:54 PM PST 24
Finished Feb 25 12:38:24 PM PST 24
Peak memory 211444 kb
Host smart-1abd8e11-af05-4d3c-bb5e-ee196ac39d61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2985353461 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_kmac_err_chk.2985353461
Directory /workspace/18.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_intg_err.4273961297
Short name T120
Test name
Test status
Simulation time 12334106975 ps
CPU time 78.23 seconds
Started Feb 25 12:29:18 PM PST 24
Finished Feb 25 12:30:37 PM PST 24
Peak memory 210704 kb
Host smart-3c130b5e-bfb9-4729-8747-cc96ffbe4dd8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4273961297 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_tl_i
ntg_err.4273961297
Directory /workspace/11.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_same_csr_outstanding.3942497570
Short name T72
Test name
Test status
Simulation time 1626113156 ps
CPU time 15.67 seconds
Started Feb 25 12:29:18 PM PST 24
Finished Feb 25 12:29:34 PM PST 24
Peak memory 210576 kb
Host smart-dac7ddb7-30c3-4a61-b92a-75ddae440986
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3942497570 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_c
trl_same_csr_outstanding.3942497570
Directory /workspace/0.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_intg_err.531810166
Short name T114
Test name
Test status
Simulation time 349351005 ps
CPU time 69.58 seconds
Started Feb 25 12:29:20 PM PST 24
Finished Feb 25 12:30:29 PM PST 24
Peak memory 211280 kb
Host smart-e7f31edf-dddc-4c38-9046-c380135bdef2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=531810166 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_tl_in
tg_err.531810166
Directory /workspace/18.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_intg_err.4051843046
Short name T126
Test name
Test status
Simulation time 591813012 ps
CPU time 36.01 seconds
Started Feb 25 12:29:33 PM PST 24
Finished Feb 25 12:30:10 PM PST 24
Peak memory 210584 kb
Host smart-4fd88942-c063-41da-ac53-5784d1790c39
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4051843046 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_tl_in
tg_err.4051843046
Directory /workspace/3.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/10.rom_ctrl_smoke.2874515364
Short name T79
Test name
Test status
Simulation time 2560863559 ps
CPU time 28.68 seconds
Started Feb 25 12:37:56 PM PST 24
Finished Feb 25 12:38:26 PM PST 24
Peak memory 212892 kb
Host smart-2ad2f0b5-5c93-42fe-b8be-b863c156a9fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2874515364 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_smoke.2874515364
Directory /workspace/10.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/22.rom_ctrl_max_throughput_chk.305727187
Short name T94
Test name
Test status
Simulation time 15062253945 ps
CPU time 11.59 seconds
Started Feb 25 12:37:49 PM PST 24
Finished Feb 25 12:38:00 PM PST 24
Peak memory 211176 kb
Host smart-119ba6b3-7804-4ded-95f0-4b5e743801e5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=305727187 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_max_throughput_chk.305727187
Directory /workspace/22.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_aliasing.901088548
Short name T382
Test name
Test status
Simulation time 426359762 ps
CPU time 5.81 seconds
Started Feb 25 12:29:22 PM PST 24
Finished Feb 25 12:29:28 PM PST 24
Peak memory 210528 kb
Host smart-fa74d2a9-5fe5-4494-9d6f-605c8334b793
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=901088548 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_alias
ing.901088548
Directory /workspace/0.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_bit_bash.2773767023
Short name T371
Test name
Test status
Simulation time 6759273952 ps
CPU time 14.22 seconds
Started Feb 25 12:29:10 PM PST 24
Finished Feb 25 12:29:25 PM PST 24
Peak memory 210584 kb
Host smart-3927a0e7-1a7a-40f7-bfd8-45538fb9e5ec
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2773767023 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_bit_
bash.2773767023
Directory /workspace/0.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_hw_reset.1236507256
Short name T411
Test name
Test status
Simulation time 8262530713 ps
CPU time 18.22 seconds
Started Feb 25 12:29:08 PM PST 24
Finished Feb 25 12:29:27 PM PST 24
Peak memory 210576 kb
Host smart-8a759cb4-13aa-4468-ab91-b98554ca37a5
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1236507256 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_hw_r
eset.1236507256
Directory /workspace/0.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_mem_rw_with_rand_reset.1571512340
Short name T368
Test name
Test status
Simulation time 1011887627 ps
CPU time 11.51 seconds
Started Feb 25 12:29:21 PM PST 24
Finished Feb 25 12:29:33 PM PST 24
Peak memory 214312 kb
Host smart-ad8ce201-775c-47be-8f84-935e7201e232
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1571512340 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 0.rom_ctrl_csr_mem_rw_with_rand_reset.1571512340
Directory /workspace/0.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_rw.946253918
Short name T74
Test name
Test status
Simulation time 2076207106 ps
CPU time 15.43 seconds
Started Feb 25 12:29:08 PM PST 24
Finished Feb 25 12:29:24 PM PST 24
Peak memory 210536 kb
Host smart-d5d66223-4f2b-4576-80f8-9a010fbbacd8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=946253918 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_rw.946253918
Directory /workspace/0.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_partial_access.3918074111
Short name T420
Test name
Test status
Simulation time 2119626924 ps
CPU time 13.54 seconds
Started Feb 25 12:29:06 PM PST 24
Finished Feb 25 12:29:20 PM PST 24
Peak memory 210532 kb
Host smart-e9315d73-d6f8-4e87-a5e4-1b1b58b2cb31
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3918074111 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctr
l_mem_partial_access.3918074111
Directory /workspace/0.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_walk.148360677
Short name T374
Test name
Test status
Simulation time 4285150124 ps
CPU time 10.36 seconds
Started Feb 25 12:29:16 PM PST 24
Finished Feb 25 12:29:27 PM PST 24
Peak memory 210524 kb
Host smart-6a0fd5aa-4535-416c-81b9-8f092bc27cf7
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=148360677 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_mem_walk.
148360677
Directory /workspace/0.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_passthru_mem_tl_intg_err.3910991217
Short name T78
Test name
Test status
Simulation time 411877648 ps
CPU time 18.95 seconds
Started Feb 25 12:29:06 PM PST 24
Finished Feb 25 12:29:26 PM PST 24
Peak memory 210528 kb
Host smart-902b9970-a05e-47c6-adcd-0e61d1fb508d
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3910991217 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_pa
ssthru_mem_tl_intg_err.3910991217
Directory /workspace/0.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_errors.2088327098
Short name T442
Test name
Test status
Simulation time 174802769 ps
CPU time 6.04 seconds
Started Feb 25 12:29:13 PM PST 24
Finished Feb 25 12:29:19 PM PST 24
Peak memory 213244 kb
Host smart-872b26d7-9ee4-4b2c-aea3-ee90af195d4f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2088327098 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_tl_errors.2088327098
Directory /workspace/0.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_intg_err.993953908
Short name T112
Test name
Test status
Simulation time 4684604057 ps
CPU time 43.61 seconds
Started Feb 25 12:29:02 PM PST 24
Finished Feb 25 12:29:46 PM PST 24
Peak memory 210840 kb
Host smart-b1209f8b-15be-469d-bed6-885d708b45b2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=993953908 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_tl_int
g_err.993953908
Directory /workspace/0.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_aliasing.945854907
Short name T89
Test name
Test status
Simulation time 564160359 ps
CPU time 6.34 seconds
Started Feb 25 12:29:25 PM PST 24
Finished Feb 25 12:29:32 PM PST 24
Peak memory 210512 kb
Host smart-e330d5ad-c3aa-4bd1-91b9-74001531ec81
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=945854907 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_alias
ing.945854907
Directory /workspace/1.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_bit_bash.4072356173
Short name T396
Test name
Test status
Simulation time 2923821400 ps
CPU time 9.18 seconds
Started Feb 25 12:29:20 PM PST 24
Finished Feb 25 12:29:30 PM PST 24
Peak memory 210572 kb
Host smart-7427d55c-4bf3-4976-9d64-e5ed8749113f
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4072356173 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_bit_
bash.4072356173
Directory /workspace/1.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_hw_reset.2530742666
Short name T86
Test name
Test status
Simulation time 88686602 ps
CPU time 5.83 seconds
Started Feb 25 12:29:15 PM PST 24
Finished Feb 25 12:29:21 PM PST 24
Peak memory 210516 kb
Host smart-d6abdbd5-bffd-4dc2-bcef-04f39a20c028
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2530742666 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_hw_r
eset.2530742666
Directory /workspace/1.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_mem_rw_with_rand_reset.1256008041
Short name T450
Test name
Test status
Simulation time 795853437 ps
CPU time 9.55 seconds
Started Feb 25 12:29:03 PM PST 24
Finished Feb 25 12:29:13 PM PST 24
Peak memory 213740 kb
Host smart-653c8abd-9814-4c6b-9ea2-c48f13566037
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1256008041 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 1.rom_ctrl_csr_mem_rw_with_rand_reset.1256008041
Directory /workspace/1.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_rw.3935899614
Short name T425
Test name
Test status
Simulation time 257453128 ps
CPU time 6.03 seconds
Started Feb 25 12:29:03 PM PST 24
Finished Feb 25 12:29:10 PM PST 24
Peak memory 209800 kb
Host smart-e70245fc-929d-465e-9bfb-823d099c5c17
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3935899614 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_rw.3935899614
Directory /workspace/1.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_partial_access.4254388809
Short name T393
Test name
Test status
Simulation time 901205141 ps
CPU time 9.55 seconds
Started Feb 25 12:29:22 PM PST 24
Finished Feb 25 12:29:32 PM PST 24
Peak memory 210200 kb
Host smart-117de1e4-bae6-4ab8-a6d1-42fb92cb78a1
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4254388809 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctr
l_mem_partial_access.4254388809
Directory /workspace/1.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_walk.2744712414
Short name T445
Test name
Test status
Simulation time 18193539529 ps
CPU time 12.03 seconds
Started Feb 25 12:29:03 PM PST 24
Finished Feb 25 12:29:15 PM PST 24
Peak memory 210516 kb
Host smart-7b61c6e5-b7f3-4a9a-bb79-5b42e5c74fc1
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2744712414 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_mem_walk
.2744712414
Directory /workspace/1.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_passthru_mem_tl_intg_err.867222490
Short name T77
Test name
Test status
Simulation time 18600700793 ps
CPU time 45.09 seconds
Started Feb 25 12:29:17 PM PST 24
Finished Feb 25 12:30:02 PM PST 24
Peak memory 210592 kb
Host smart-f1bd266f-dab9-463a-94d9-bb8942f2344b
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=867222490 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_pas
sthru_mem_tl_intg_err.867222490
Directory /workspace/1.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_same_csr_outstanding.208568250
Short name T104
Test name
Test status
Simulation time 592353374 ps
CPU time 4.08 seconds
Started Feb 25 12:29:06 PM PST 24
Finished Feb 25 12:29:11 PM PST 24
Peak memory 210592 kb
Host smart-72433972-ee08-459c-a7d0-28ce2f06fe90
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=208568250 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ct
rl_same_csr_outstanding.208568250
Directory /workspace/1.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_errors.658741163
Short name T444
Test name
Test status
Simulation time 243412899 ps
CPU time 8.52 seconds
Started Feb 25 12:29:04 PM PST 24
Finished Feb 25 12:29:13 PM PST 24
Peak memory 214876 kb
Host smart-dcc2a05a-627c-4352-a3ae-c0378e3b6cf2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=658741163 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_tl_errors.658741163
Directory /workspace/1.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_intg_err.340304605
Short name T117
Test name
Test status
Simulation time 1597101428 ps
CPU time 44.43 seconds
Started Feb 25 12:29:08 PM PST 24
Finished Feb 25 12:29:53 PM PST 24
Peak memory 210508 kb
Host smart-3eab719e-1dbe-4780-bea0-587d6f2cfb3a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=340304605 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_tl_int
g_err.340304605
Directory /workspace/1.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_mem_rw_with_rand_reset.2297073886
Short name T412
Test name
Test status
Simulation time 1565345889 ps
CPU time 5.39 seconds
Started Feb 25 12:29:25 PM PST 24
Finished Feb 25 12:29:30 PM PST 24
Peak memory 215236 kb
Host smart-113fde5c-5505-401c-9a9b-1de4e78ce644
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2297073886 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 10.rom_ctrl_csr_mem_rw_with_rand_reset.2297073886
Directory /workspace/10.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_rw.2128909285
Short name T440
Test name
Test status
Simulation time 9008206368 ps
CPU time 7.35 seconds
Started Feb 25 12:29:24 PM PST 24
Finished Feb 25 12:29:32 PM PST 24
Peak memory 210608 kb
Host smart-73e78763-650a-4ad9-9056-2193f0e601f3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2128909285 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_csr_rw.2128909285
Directory /workspace/10.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_passthru_mem_tl_intg_err.1991483613
Short name T378
Test name
Test status
Simulation time 3239600299 ps
CPU time 49.94 seconds
Started Feb 25 12:29:11 PM PST 24
Finished Feb 25 12:30:01 PM PST 24
Peak memory 210852 kb
Host smart-bd38b5f9-edfe-4095-9713-b3471801399a
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1991483613 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_p
assthru_mem_tl_intg_err.1991483613
Directory /workspace/10.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_same_csr_outstanding.2364584998
Short name T431
Test name
Test status
Simulation time 7561754650 ps
CPU time 11.18 seconds
Started Feb 25 12:29:23 PM PST 24
Finished Feb 25 12:29:34 PM PST 24
Peak memory 210636 kb
Host smart-8ddb0f54-93a5-4d70-b3b8-b19e29804c83
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2364584998 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_
ctrl_same_csr_outstanding.2364584998
Directory /workspace/10.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_errors.2706644828
Short name T375
Test name
Test status
Simulation time 88404268 ps
CPU time 6.1 seconds
Started Feb 25 12:29:06 PM PST 24
Finished Feb 25 12:29:13 PM PST 24
Peak memory 213748 kb
Host smart-56c21d53-d6e7-44bc-96ff-8c99cbf2b061
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2706644828 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_tl_errors.2706644828
Directory /workspace/10.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_mem_rw_with_rand_reset.466321354
Short name T383
Test name
Test status
Simulation time 8066923689 ps
CPU time 17.25 seconds
Started Feb 25 12:29:05 PM PST 24
Finished Feb 25 12:29:23 PM PST 24
Peak memory 213156 kb
Host smart-8f4e2a7a-759e-4e61-a5fc-958991c2229f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=466321354 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 11.rom_ctrl_csr_mem_rw_with_rand_reset.466321354
Directory /workspace/11.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_rw.3407670909
Short name T399
Test name
Test status
Simulation time 8541718315 ps
CPU time 16.13 seconds
Started Feb 25 12:29:23 PM PST 24
Finished Feb 25 12:29:39 PM PST 24
Peak memory 210604 kb
Host smart-ecd56f52-a51f-42ff-8609-76fdde9fd6fd
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3407670909 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_csr_rw.3407670909
Directory /workspace/11.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_passthru_mem_tl_intg_err.2242804951
Short name T453
Test name
Test status
Simulation time 548307727 ps
CPU time 27.25 seconds
Started Feb 25 12:29:33 PM PST 24
Finished Feb 25 12:30:01 PM PST 24
Peak memory 210532 kb
Host smart-40b50cd9-11cb-4699-b83b-f61f833183e8
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2242804951 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_p
assthru_mem_tl_intg_err.2242804951
Directory /workspace/11.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_same_csr_outstanding.2709356050
Short name T106
Test name
Test status
Simulation time 1739439656 ps
CPU time 14.25 seconds
Started Feb 25 12:29:07 PM PST 24
Finished Feb 25 12:29:23 PM PST 24
Peak memory 210052 kb
Host smart-0cfabb21-f65c-4e67-8af1-8edc068bdf0d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2709356050 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_
ctrl_same_csr_outstanding.2709356050
Directory /workspace/11.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_errors.1250440768
Short name T391
Test name
Test status
Simulation time 333620937 ps
CPU time 6.56 seconds
Started Feb 25 12:29:09 PM PST 24
Finished Feb 25 12:29:16 PM PST 24
Peak memory 213892 kb
Host smart-bb919dd5-f9a6-4aeb-add3-3257ea0fa0f8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1250440768 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_tl_errors.1250440768
Directory /workspace/11.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_mem_rw_with_rand_reset.3646508974
Short name T434
Test name
Test status
Simulation time 150616995 ps
CPU time 5.89 seconds
Started Feb 25 12:29:45 PM PST 24
Finished Feb 25 12:29:52 PM PST 24
Peak memory 214064 kb
Host smart-19f121c8-82b9-4ec3-9143-9163a2f69507
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3646508974 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 12.rom_ctrl_csr_mem_rw_with_rand_reset.3646508974
Directory /workspace/12.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_rw.1524373502
Short name T381
Test name
Test status
Simulation time 2159124343 ps
CPU time 14.47 seconds
Started Feb 25 12:29:19 PM PST 24
Finished Feb 25 12:29:34 PM PST 24
Peak memory 210652 kb
Host smart-c56cf39d-f395-447d-9a09-83182c676393
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1524373502 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_csr_rw.1524373502
Directory /workspace/12.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_passthru_mem_tl_intg_err.1268695567
Short name T438
Test name
Test status
Simulation time 9822430093 ps
CPU time 41.79 seconds
Started Feb 25 12:29:26 PM PST 24
Finished Feb 25 12:30:09 PM PST 24
Peak memory 210584 kb
Host smart-8fe16379-a778-4f25-835a-01a54278bca4
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1268695567 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_p
assthru_mem_tl_intg_err.1268695567
Directory /workspace/12.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_same_csr_outstanding.3409549192
Short name T395
Test name
Test status
Simulation time 169646789 ps
CPU time 5.66 seconds
Started Feb 25 12:30:00 PM PST 24
Finished Feb 25 12:30:06 PM PST 24
Peak memory 210648 kb
Host smart-399acd5f-78d2-468e-a877-d52283931c30
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3409549192 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_
ctrl_same_csr_outstanding.3409549192
Directory /workspace/12.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_errors.2091225582
Short name T392
Test name
Test status
Simulation time 666357223 ps
CPU time 11.08 seconds
Started Feb 25 12:29:17 PM PST 24
Finished Feb 25 12:29:29 PM PST 24
Peak memory 218860 kb
Host smart-0c2d131d-246f-4493-80fe-997172c58bf8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2091225582 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_tl_errors.2091225582
Directory /workspace/12.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_intg_err.739962955
Short name T123
Test name
Test status
Simulation time 1443178207 ps
CPU time 36.43 seconds
Started Feb 25 12:29:35 PM PST 24
Finished Feb 25 12:30:12 PM PST 24
Peak memory 210588 kb
Host smart-68886a79-f90f-4d8d-a302-3f9c998ddbee
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=739962955 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_tl_in
tg_err.739962955
Directory /workspace/12.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_mem_rw_with_rand_reset.3170399445
Short name T397
Test name
Test status
Simulation time 475650374 ps
CPU time 7.75 seconds
Started Feb 25 12:29:20 PM PST 24
Finished Feb 25 12:29:28 PM PST 24
Peak memory 218804 kb
Host smart-7721d03b-367c-4767-a363-3131d1ebc97d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3170399445 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 13.rom_ctrl_csr_mem_rw_with_rand_reset.3170399445
Directory /workspace/13.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_rw.3315561315
Short name T446
Test name
Test status
Simulation time 86523785 ps
CPU time 4.43 seconds
Started Feb 25 12:29:26 PM PST 24
Finished Feb 25 12:29:31 PM PST 24
Peak memory 209800 kb
Host smart-e27c1e81-fe63-49c9-b6f1-a8629c1cb970
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3315561315 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_csr_rw.3315561315
Directory /workspace/13.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_passthru_mem_tl_intg_err.666224327
Short name T454
Test name
Test status
Simulation time 2848965229 ps
CPU time 27.11 seconds
Started Feb 25 12:29:05 PM PST 24
Finished Feb 25 12:29:32 PM PST 24
Peak memory 210588 kb
Host smart-bdf7f639-4c55-4a91-8dff-0166c01c8298
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=666224327 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_pa
ssthru_mem_tl_intg_err.666224327
Directory /workspace/13.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_same_csr_outstanding.2449527217
Short name T388
Test name
Test status
Simulation time 302637337 ps
CPU time 6.16 seconds
Started Feb 25 12:29:20 PM PST 24
Finished Feb 25 12:29:36 PM PST 24
Peak memory 210584 kb
Host smart-5df3e7e0-845b-472f-b238-67200389201d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2449527217 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_
ctrl_same_csr_outstanding.2449527217
Directory /workspace/13.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_errors.2870331666
Short name T424
Test name
Test status
Simulation time 307437122 ps
CPU time 8.78 seconds
Started Feb 25 12:29:28 PM PST 24
Finished Feb 25 12:29:37 PM PST 24
Peak memory 213788 kb
Host smart-c0f960fc-64fc-492b-85f4-3ba54a89e970
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2870331666 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_tl_errors.2870331666
Directory /workspace/13.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_intg_err.1124817852
Short name T113
Test name
Test status
Simulation time 6325485693 ps
CPU time 42.66 seconds
Started Feb 25 12:29:33 PM PST 24
Finished Feb 25 12:30:16 PM PST 24
Peak memory 211508 kb
Host smart-536e9793-36fa-432b-b8b7-0cbaacde4561
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1124817852 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_tl_i
ntg_err.1124817852
Directory /workspace/13.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_mem_rw_with_rand_reset.3176798202
Short name T429
Test name
Test status
Simulation time 3188128272 ps
CPU time 11.52 seconds
Started Feb 25 12:29:05 PM PST 24
Finished Feb 25 12:29:17 PM PST 24
Peak memory 213644 kb
Host smart-917a34be-576b-46c2-883c-ec01f22cf585
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3176798202 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 14.rom_ctrl_csr_mem_rw_with_rand_reset.3176798202
Directory /workspace/14.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_rw.2391151224
Short name T436
Test name
Test status
Simulation time 1845087827 ps
CPU time 10.67 seconds
Started Feb 25 12:29:18 PM PST 24
Finished Feb 25 12:29:29 PM PST 24
Peak memory 210536 kb
Host smart-da6c0e6f-1232-4685-bd2b-3d046a726199
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2391151224 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_csr_rw.2391151224
Directory /workspace/14.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_same_csr_outstanding.1587353522
Short name T435
Test name
Test status
Simulation time 2085586939 ps
CPU time 16.28 seconds
Started Feb 25 12:29:05 PM PST 24
Finished Feb 25 12:29:21 PM PST 24
Peak memory 210584 kb
Host smart-f7fc9f50-d858-4efb-ab34-a26072f9c0de
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1587353522 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_
ctrl_same_csr_outstanding.1587353522
Directory /workspace/14.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_errors.954677337
Short name T460
Test name
Test status
Simulation time 1378673150 ps
CPU time 8.73 seconds
Started Feb 25 12:29:18 PM PST 24
Finished Feb 25 12:29:27 PM PST 24
Peak memory 214784 kb
Host smart-099fe304-0f07-4988-a00a-2cb759c50a34
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=954677337 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_tl_errors.954677337
Directory /workspace/14.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_intg_err.1510639390
Short name T116
Test name
Test status
Simulation time 470474792 ps
CPU time 38.97 seconds
Started Feb 25 12:29:22 PM PST 24
Finished Feb 25 12:30:01 PM PST 24
Peak memory 210952 kb
Host smart-acb398f2-f1b4-4ff0-bf81-c7cf9ab3fc76
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1510639390 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_tl_i
ntg_err.1510639390
Directory /workspace/14.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_mem_rw_with_rand_reset.679795988
Short name T384
Test name
Test status
Simulation time 4480996963 ps
CPU time 11.98 seconds
Started Feb 25 12:29:07 PM PST 24
Finished Feb 25 12:29:19 PM PST 24
Peak memory 214860 kb
Host smart-9c8f8379-4107-4605-8d96-f4a06365f291
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=679795988 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 15.rom_ctrl_csr_mem_rw_with_rand_reset.679795988
Directory /workspace/15.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_rw.1135631671
Short name T73
Test name
Test status
Simulation time 3621265819 ps
CPU time 9.87 seconds
Started Feb 25 12:29:14 PM PST 24
Finished Feb 25 12:29:24 PM PST 24
Peak memory 210596 kb
Host smart-ed7e6e65-cbbc-4542-908a-701339156a10
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1135631671 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_csr_rw.1135631671
Directory /workspace/15.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_passthru_mem_tl_intg_err.952887857
Short name T93
Test name
Test status
Simulation time 546690699 ps
CPU time 27.93 seconds
Started Feb 25 12:29:07 PM PST 24
Finished Feb 25 12:29:36 PM PST 24
Peak memory 210528 kb
Host smart-6afbf52d-67fc-4025-b15f-9935c4c7d28b
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=952887857 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_pa
ssthru_mem_tl_intg_err.952887857
Directory /workspace/15.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_same_csr_outstanding.2164691514
Short name T105
Test name
Test status
Simulation time 20577841085 ps
CPU time 10.69 seconds
Started Feb 25 12:29:06 PM PST 24
Finished Feb 25 12:29:16 PM PST 24
Peak memory 210268 kb
Host smart-15e25a03-b6a5-41a5-b931-73ad8a8418ff
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2164691514 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_
ctrl_same_csr_outstanding.2164691514
Directory /workspace/15.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_errors.248725757
Short name T421
Test name
Test status
Simulation time 1556355385 ps
CPU time 16.84 seconds
Started Feb 25 12:29:06 PM PST 24
Finished Feb 25 12:29:23 PM PST 24
Peak memory 214856 kb
Host smart-2098e305-ac00-4de5-ae7f-730784ddf84d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=248725757 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_tl_errors.248725757
Directory /workspace/15.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_mem_rw_with_rand_reset.2516342925
Short name T433
Test name
Test status
Simulation time 393014622 ps
CPU time 7.49 seconds
Started Feb 25 12:29:06 PM PST 24
Finished Feb 25 12:29:14 PM PST 24
Peak memory 214888 kb
Host smart-50cd89c5-2791-4b73-95a9-ead883a4b50d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2516342925 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 16.rom_ctrl_csr_mem_rw_with_rand_reset.2516342925
Directory /workspace/16.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_rw.3309115367
Short name T75
Test name
Test status
Simulation time 574035379 ps
CPU time 7.79 seconds
Started Feb 25 12:29:38 PM PST 24
Finished Feb 25 12:29:46 PM PST 24
Peak memory 210528 kb
Host smart-093234b6-021d-4f79-9140-2c9f94d5bd58
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3309115367 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_csr_rw.3309115367
Directory /workspace/16.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_passthru_mem_tl_intg_err.3327991695
Short name T91
Test name
Test status
Simulation time 4418676091 ps
CPU time 18.75 seconds
Started Feb 25 12:29:20 PM PST 24
Finished Feb 25 12:29:38 PM PST 24
Peak memory 210596 kb
Host smart-156fa2cb-0df9-4161-9dee-65ffda439eae
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3327991695 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_p
assthru_mem_tl_intg_err.3327991695
Directory /workspace/16.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_same_csr_outstanding.3483259975
Short name T423
Test name
Test status
Simulation time 8624623444 ps
CPU time 15.78 seconds
Started Feb 25 12:29:11 PM PST 24
Finished Feb 25 12:29:27 PM PST 24
Peak memory 210644 kb
Host smart-d1a0fe26-99bd-4f5e-82bf-630463fd080e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3483259975 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_
ctrl_same_csr_outstanding.3483259975
Directory /workspace/16.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_errors.1798907827
Short name T379
Test name
Test status
Simulation time 89572427 ps
CPU time 7.06 seconds
Started Feb 25 12:29:06 PM PST 24
Finished Feb 25 12:29:14 PM PST 24
Peak memory 214764 kb
Host smart-946154af-fc7b-4ef6-9fe3-a477e3ed96b4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1798907827 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_tl_errors.1798907827
Directory /workspace/16.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_intg_err.815936332
Short name T115
Test name
Test status
Simulation time 955657496 ps
CPU time 74.85 seconds
Started Feb 25 12:29:11 PM PST 24
Finished Feb 25 12:30:26 PM PST 24
Peak memory 212208 kb
Host smart-a69872aa-0965-41a3-a4fc-d1b56bc695c0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=815936332 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_tl_in
tg_err.815936332
Directory /workspace/16.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_mem_rw_with_rand_reset.901495493
Short name T449
Test name
Test status
Simulation time 1014353002 ps
CPU time 10.49 seconds
Started Feb 25 12:29:22 PM PST 24
Finished Feb 25 12:29:33 PM PST 24
Peak memory 213516 kb
Host smart-4880f1c9-fc03-40f6-94ec-cbcf71940ef1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=901495493 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 17.rom_ctrl_csr_mem_rw_with_rand_reset.901495493
Directory /workspace/17.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_rw.1312583028
Short name T462
Test name
Test status
Simulation time 23740324089 ps
CPU time 17.7 seconds
Started Feb 25 12:29:22 PM PST 24
Finished Feb 25 12:29:40 PM PST 24
Peak memory 209608 kb
Host smart-250ec324-b683-4568-b6dc-f0c9da0d03af
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1312583028 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_csr_rw.1312583028
Directory /workspace/17.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_passthru_mem_tl_intg_err.3012511212
Short name T87
Test name
Test status
Simulation time 10021422664 ps
CPU time 83.24 seconds
Started Feb 25 12:29:21 PM PST 24
Finished Feb 25 12:30:45 PM PST 24
Peak memory 210604 kb
Host smart-93fcfa6d-ee34-4a14-bf76-8a720cba42f2
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3012511212 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_p
assthru_mem_tl_intg_err.3012511212
Directory /workspace/17.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_same_csr_outstanding.1200724788
Short name T457
Test name
Test status
Simulation time 6171523113 ps
CPU time 14.89 seconds
Started Feb 25 12:29:14 PM PST 24
Finished Feb 25 12:29:29 PM PST 24
Peak memory 210648 kb
Host smart-efcc4e66-a588-45e7-b609-65fdfd917018
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1200724788 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_
ctrl_same_csr_outstanding.1200724788
Directory /workspace/17.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_errors.4046896831
Short name T415
Test name
Test status
Simulation time 6703499557 ps
CPU time 17.66 seconds
Started Feb 25 12:29:09 PM PST 24
Finished Feb 25 12:29:27 PM PST 24
Peak memory 216324 kb
Host smart-c6c18f4e-a6bb-41c9-b314-5cbaf553fb47
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4046896831 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_tl_errors.4046896831
Directory /workspace/17.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_intg_err.2613426258
Short name T63
Test name
Test status
Simulation time 1841064846 ps
CPU time 41.59 seconds
Started Feb 25 12:29:29 PM PST 24
Finished Feb 25 12:30:11 PM PST 24
Peak memory 211128 kb
Host smart-8abf0aff-ddef-4713-85cb-bb019f5114c5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2613426258 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_tl_i
ntg_err.2613426258
Directory /workspace/17.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_mem_rw_with_rand_reset.342615813
Short name T398
Test name
Test status
Simulation time 2200153738 ps
CPU time 8.41 seconds
Started Feb 25 12:29:14 PM PST 24
Finished Feb 25 12:29:23 PM PST 24
Peak memory 214252 kb
Host smart-0240e2b8-7596-4271-8b9b-3b4045a7db89
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=342615813 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 18.rom_ctrl_csr_mem_rw_with_rand_reset.342615813
Directory /workspace/18.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_rw.1507238833
Short name T403
Test name
Test status
Simulation time 2087160884 ps
CPU time 10.52 seconds
Started Feb 25 12:29:45 PM PST 24
Finished Feb 25 12:29:56 PM PST 24
Peak memory 210540 kb
Host smart-610e4777-00c3-4f1d-bdb8-cc0037db5ac4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1507238833 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_csr_rw.1507238833
Directory /workspace/18.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_passthru_mem_tl_intg_err.1451390143
Short name T66
Test name
Test status
Simulation time 24652251736 ps
CPU time 62.34 seconds
Started Feb 25 12:29:18 PM PST 24
Finished Feb 25 12:30:21 PM PST 24
Peak memory 210608 kb
Host smart-a27d268e-8d6a-4f22-8ccf-f3e977b4e2a2
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1451390143 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_p
assthru_mem_tl_intg_err.1451390143
Directory /workspace/18.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_same_csr_outstanding.890647013
Short name T414
Test name
Test status
Simulation time 100975339 ps
CPU time 6.15 seconds
Started Feb 25 12:29:29 PM PST 24
Finished Feb 25 12:29:36 PM PST 24
Peak memory 210584 kb
Host smart-67ea2741-c7fd-460a-aa7a-c94ea1afeedc
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=890647013 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_c
trl_same_csr_outstanding.890647013
Directory /workspace/18.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_errors.2361216710
Short name T426
Test name
Test status
Simulation time 180002817 ps
CPU time 6.97 seconds
Started Feb 25 12:29:22 PM PST 24
Finished Feb 25 12:29:29 PM PST 24
Peak memory 214224 kb
Host smart-98361296-3bfc-44fc-81d8-17fa8a504129
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2361216710 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_tl_errors.2361216710
Directory /workspace/18.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_mem_rw_with_rand_reset.1929935189
Short name T413
Test name
Test status
Simulation time 1742513382 ps
CPU time 15.69 seconds
Started Feb 25 12:29:48 PM PST 24
Finished Feb 25 12:30:04 PM PST 24
Peak memory 216176 kb
Host smart-b707eee8-6dd3-4e36-87b3-de50c667d0d7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1929935189 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 19.rom_ctrl_csr_mem_rw_with_rand_reset.1929935189
Directory /workspace/19.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_rw.3741270604
Short name T372
Test name
Test status
Simulation time 3243401914 ps
CPU time 10.03 seconds
Started Feb 25 12:29:29 PM PST 24
Finished Feb 25 12:29:40 PM PST 24
Peak memory 210592 kb
Host smart-ca616353-92d2-47eb-85a8-3ba6bd1eea62
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3741270604 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_csr_rw.3741270604
Directory /workspace/19.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_passthru_mem_tl_intg_err.2746871453
Short name T85
Test name
Test status
Simulation time 20762308689 ps
CPU time 39.93 seconds
Started Feb 25 12:29:22 PM PST 24
Finished Feb 25 12:30:03 PM PST 24
Peak memory 210592 kb
Host smart-4f113b75-655b-4e1e-ac5e-60499941de98
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2746871453 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_p
assthru_mem_tl_intg_err.2746871453
Directory /workspace/19.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_same_csr_outstanding.4235171495
Short name T448
Test name
Test status
Simulation time 819975064 ps
CPU time 9.25 seconds
Started Feb 25 12:29:24 PM PST 24
Finished Feb 25 12:29:33 PM PST 24
Peak memory 210584 kb
Host smart-28b7c360-c757-4800-9fe0-6ce489493bfc
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4235171495 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_
ctrl_same_csr_outstanding.4235171495
Directory /workspace/19.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_errors.1014601249
Short name T422
Test name
Test status
Simulation time 128012434 ps
CPU time 7.19 seconds
Started Feb 25 12:29:28 PM PST 24
Finished Feb 25 12:29:36 PM PST 24
Peak memory 214556 kb
Host smart-1b5428eb-3173-468a-8db8-f7814b5277b6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1014601249 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_tl_errors.1014601249
Directory /workspace/19.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_intg_err.1944794445
Short name T122
Test name
Test status
Simulation time 2282084910 ps
CPU time 79.64 seconds
Started Feb 25 12:29:33 PM PST 24
Finished Feb 25 12:30:54 PM PST 24
Peak memory 211108 kb
Host smart-1ecae7df-27e7-4c01-96bb-a0f3f391e8a3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1944794445 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_tl_i
ntg_err.1944794445
Directory /workspace/19.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_aliasing.310151224
Short name T67
Test name
Test status
Simulation time 5097743760 ps
CPU time 9.29 seconds
Started Feb 25 12:29:06 PM PST 24
Finished Feb 25 12:29:21 PM PST 24
Peak memory 210580 kb
Host smart-3417f43c-fc72-4fab-abde-035922ed3ffb
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=310151224 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_alias
ing.310151224
Directory /workspace/2.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_bit_bash.2366186003
Short name T451
Test name
Test status
Simulation time 2638696093 ps
CPU time 10.44 seconds
Started Feb 25 12:29:22 PM PST 24
Finished Feb 25 12:29:33 PM PST 24
Peak memory 210576 kb
Host smart-9fec2df0-b7a3-4a2d-be77-4f2102c70fb0
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2366186003 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_bit_
bash.2366186003
Directory /workspace/2.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_hw_reset.2149646651
Short name T427
Test name
Test status
Simulation time 4552212826 ps
CPU time 10.39 seconds
Started Feb 25 12:29:15 PM PST 24
Finished Feb 25 12:29:25 PM PST 24
Peak memory 210572 kb
Host smart-cb8d8aa0-6c87-4326-85fc-8270fa4f4a60
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2149646651 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_hw_r
eset.2149646651
Directory /workspace/2.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_mem_rw_with_rand_reset.2076193861
Short name T373
Test name
Test status
Simulation time 8009343220 ps
CPU time 17.37 seconds
Started Feb 25 12:29:05 PM PST 24
Finished Feb 25 12:29:23 PM PST 24
Peak memory 214168 kb
Host smart-fc68dfc3-f636-43c8-a79e-c14ab853fd76
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2076193861 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 2.rom_ctrl_csr_mem_rw_with_rand_reset.2076193861
Directory /workspace/2.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_rw.1839081042
Short name T394
Test name
Test status
Simulation time 1890218991 ps
CPU time 15.54 seconds
Started Feb 25 12:29:17 PM PST 24
Finished Feb 25 12:29:33 PM PST 24
Peak memory 209796 kb
Host smart-fa02b25c-020e-4623-8ebc-1954da55ae90
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1839081042 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_rw.1839081042
Directory /workspace/2.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_partial_access.992105606
Short name T390
Test name
Test status
Simulation time 6364794082 ps
CPU time 10.63 seconds
Started Feb 25 12:29:04 PM PST 24
Finished Feb 25 12:29:15 PM PST 24
Peak memory 210584 kb
Host smart-ebdf3ebc-f09c-41d2-a6fc-e457ff299a7d
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=992105606 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl
_mem_partial_access.992105606
Directory /workspace/2.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_walk.3327695732
Short name T380
Test name
Test status
Simulation time 175144680 ps
CPU time 4.12 seconds
Started Feb 25 12:29:22 PM PST 24
Finished Feb 25 12:29:27 PM PST 24
Peak memory 210088 kb
Host smart-6a9c9d8e-f22b-4a16-b917-bdbb2cfb29fa
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3327695732 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_mem_walk
.3327695732
Directory /workspace/2.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_passthru_mem_tl_intg_err.1382201219
Short name T402
Test name
Test status
Simulation time 729738982 ps
CPU time 18.61 seconds
Started Feb 25 12:29:07 PM PST 24
Finished Feb 25 12:29:27 PM PST 24
Peak memory 210528 kb
Host smart-af8cd165-bbf1-478d-b025-19e97ad42ee0
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1382201219 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_pa
ssthru_mem_tl_intg_err.1382201219
Directory /workspace/2.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_same_csr_outstanding.364242813
Short name T410
Test name
Test status
Simulation time 4730472019 ps
CPU time 14.75 seconds
Started Feb 25 12:29:17 PM PST 24
Finished Feb 25 12:29:32 PM PST 24
Peak memory 210648 kb
Host smart-f5c5885b-8693-433f-96c3-6083acbfbd77
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=364242813 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ct
rl_same_csr_outstanding.364242813
Directory /workspace/2.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_errors.463510610
Short name T461
Test name
Test status
Simulation time 11547434933 ps
CPU time 13.73 seconds
Started Feb 25 12:29:12 PM PST 24
Finished Feb 25 12:29:26 PM PST 24
Peak memory 218864 kb
Host smart-7fad9eb5-11cb-4226-b358-9378701e7d8b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=463510610 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_tl_errors.463510610
Directory /workspace/2.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_intg_err.603250195
Short name T62
Test name
Test status
Simulation time 13705776836 ps
CPU time 74.44 seconds
Started Feb 25 12:29:21 PM PST 24
Finished Feb 25 12:30:46 PM PST 24
Peak memory 210048 kb
Host smart-f19e4f1b-edea-4942-aa61-782dfa46f81a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=603250195 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_tl_int
g_err.603250195
Directory /workspace/2.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_aliasing.4074798059
Short name T90
Test name
Test status
Simulation time 6179879576 ps
CPU time 13.8 seconds
Started Feb 25 12:29:11 PM PST 24
Finished Feb 25 12:29:25 PM PST 24
Peak memory 210856 kb
Host smart-11093e33-4481-4152-be92-52bdc5a2f639
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4074798059 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_alia
sing.4074798059
Directory /workspace/3.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_bit_bash.362200480
Short name T365
Test name
Test status
Simulation time 438966030 ps
CPU time 4.6 seconds
Started Feb 25 12:29:05 PM PST 24
Finished Feb 25 12:29:10 PM PST 24
Peak memory 210456 kb
Host smart-76e3fa79-4aec-4ffc-a9ca-23a85bfa1c75
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=362200480 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_bit_b
ash.362200480
Directory /workspace/3.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_hw_reset.98539604
Short name T464
Test name
Test status
Simulation time 1541599433 ps
CPU time 15.15 seconds
Started Feb 25 12:29:18 PM PST 24
Finished Feb 25 12:29:33 PM PST 24
Peak memory 210520 kb
Host smart-46054f61-d3e7-4815-a8ff-c0b528d49994
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=98539604 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_hw_res
et.98539604
Directory /workspace/3.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_mem_rw_with_rand_reset.489537734
Short name T387
Test name
Test status
Simulation time 186524578 ps
CPU time 4.69 seconds
Started Feb 25 12:29:17 PM PST 24
Finished Feb 25 12:29:22 PM PST 24
Peak memory 213788 kb
Host smart-4289d4eb-f1f3-4838-8e0c-42ded77d78f5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=489537734 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 3.rom_ctrl_csr_mem_rw_with_rand_reset.489537734
Directory /workspace/3.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_rw.3401172393
Short name T430
Test name
Test status
Simulation time 13110545006 ps
CPU time 16.63 seconds
Started Feb 25 12:29:19 PM PST 24
Finished Feb 25 12:29:36 PM PST 24
Peak memory 210596 kb
Host smart-3eef5fe2-fd78-44a8-bbc9-dae7b84fa9fb
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3401172393 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_rw.3401172393
Directory /workspace/3.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_partial_access.2329942606
Short name T366
Test name
Test status
Simulation time 168079786 ps
CPU time 4.32 seconds
Started Feb 25 12:29:18 PM PST 24
Finished Feb 25 12:29:23 PM PST 24
Peak memory 210544 kb
Host smart-62632b04-bd0f-4bfd-8659-75be5bf8c2ce
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2329942606 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctr
l_mem_partial_access.2329942606
Directory /workspace/3.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_walk.1555876256
Short name T385
Test name
Test status
Simulation time 87956010 ps
CPU time 4.09 seconds
Started Feb 25 12:29:05 PM PST 24
Finished Feb 25 12:29:09 PM PST 24
Peak memory 210456 kb
Host smart-b07ab323-d495-43c6-87df-2e5ad3dda709
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1555876256 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_mem_walk
.1555876256
Directory /workspace/3.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_passthru_mem_tl_intg_err.3972677226
Short name T92
Test name
Test status
Simulation time 42064590668 ps
CPU time 85.68 seconds
Started Feb 25 12:29:20 PM PST 24
Finished Feb 25 12:30:46 PM PST 24
Peak memory 210584 kb
Host smart-a921f9d9-9b8f-4991-8b66-5b0be73e5169
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3972677226 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_pa
ssthru_mem_tl_intg_err.3972677226
Directory /workspace/3.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_same_csr_outstanding.1319715457
Short name T437
Test name
Test status
Simulation time 860627935 ps
CPU time 5.87 seconds
Started Feb 25 12:29:15 PM PST 24
Finished Feb 25 12:29:22 PM PST 24
Peak memory 210596 kb
Host smart-f33e6bd8-aec6-4970-831c-cd12d312121c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1319715457 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_c
trl_same_csr_outstanding.1319715457
Directory /workspace/3.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_errors.919965520
Short name T452
Test name
Test status
Simulation time 508255375 ps
CPU time 8.88 seconds
Started Feb 25 12:29:15 PM PST 24
Finished Feb 25 12:29:24 PM PST 24
Peak memory 214684 kb
Host smart-46c76148-b2e4-4a16-9689-bf92b395bff9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=919965520 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_tl_errors.919965520
Directory /workspace/3.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_aliasing.55606936
Short name T370
Test name
Test status
Simulation time 1929239680 ps
CPU time 10.55 seconds
Started Feb 25 12:29:07 PM PST 24
Finished Feb 25 12:29:19 PM PST 24
Peak memory 210520 kb
Host smart-7b461eef-a339-426d-ab36-4356d49242c9
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=55606936 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_aliasi
ng.55606936
Directory /workspace/4.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_bit_bash.3350058831
Short name T401
Test name
Test status
Simulation time 689237436 ps
CPU time 8.3 seconds
Started Feb 25 12:29:08 PM PST 24
Finished Feb 25 12:29:17 PM PST 24
Peak memory 210520 kb
Host smart-fe2f33cf-49ed-4dd6-86c0-a68e7c38149e
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3350058831 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_bit_
bash.3350058831
Directory /workspace/4.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_hw_reset.3685552823
Short name T456
Test name
Test status
Simulation time 25365241792 ps
CPU time 15.37 seconds
Started Feb 25 12:29:06 PM PST 24
Finished Feb 25 12:29:21 PM PST 24
Peak memory 210580 kb
Host smart-a71972c7-e2a8-4750-96be-8894c48c8bca
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3685552823 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_hw_r
eset.3685552823
Directory /workspace/4.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_mem_rw_with_rand_reset.2484179042
Short name T447
Test name
Test status
Simulation time 2154505544 ps
CPU time 16.71 seconds
Started Feb 25 12:29:16 PM PST 24
Finished Feb 25 12:29:38 PM PST 24
Peak memory 215016 kb
Host smart-5936f3f6-081b-42c2-afce-d3588b89ae72
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2484179042 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 4.rom_ctrl_csr_mem_rw_with_rand_reset.2484179042
Directory /workspace/4.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_rw.485529483
Short name T439
Test name
Test status
Simulation time 2596269184 ps
CPU time 6.15 seconds
Started Feb 25 12:29:08 PM PST 24
Finished Feb 25 12:29:15 PM PST 24
Peak memory 210596 kb
Host smart-bac3e812-4768-440d-af85-9c07fabbaa83
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=485529483 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_rw.485529483
Directory /workspace/4.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_partial_access.774147445
Short name T416
Test name
Test status
Simulation time 1351657702 ps
CPU time 11.66 seconds
Started Feb 25 12:29:06 PM PST 24
Finished Feb 25 12:29:18 PM PST 24
Peak memory 210524 kb
Host smart-9e604efa-b1d8-4327-b568-51d3002a15ed
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=774147445 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl
_mem_partial_access.774147445
Directory /workspace/4.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_walk.2418596873
Short name T441
Test name
Test status
Simulation time 1176060955 ps
CPU time 9.6 seconds
Started Feb 25 12:29:07 PM PST 24
Finished Feb 25 12:29:17 PM PST 24
Peak memory 210212 kb
Host smart-0c8a09d1-8625-4509-867b-8659efa2d847
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2418596873 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_mem_walk
.2418596873
Directory /workspace/4.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_passthru_mem_tl_intg_err.3870547386
Short name T443
Test name
Test status
Simulation time 5282467752 ps
CPU time 35.08 seconds
Started Feb 25 12:29:18 PM PST 24
Finished Feb 25 12:29:53 PM PST 24
Peak memory 210604 kb
Host smart-cf195bf8-0e29-4380-badb-183aac9619e1
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3870547386 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_pa
ssthru_mem_tl_intg_err.3870547386
Directory /workspace/4.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_same_csr_outstanding.92574470
Short name T419
Test name
Test status
Simulation time 413265600 ps
CPU time 6.67 seconds
Started Feb 25 12:29:14 PM PST 24
Finished Feb 25 12:29:21 PM PST 24
Peak memory 210592 kb
Host smart-48077fdc-ee65-4f17-ae60-63e9f6b1c0d3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=92574470 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctr
l_same_csr_outstanding.92574470
Directory /workspace/4.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_errors.3728250752
Short name T463
Test name
Test status
Simulation time 3669025759 ps
CPU time 19.39 seconds
Started Feb 25 12:29:34 PM PST 24
Finished Feb 25 12:29:54 PM PST 24
Peak memory 216120 kb
Host smart-8928e427-18c7-492f-bc63-1a48728c1584
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3728250752 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_tl_errors.3728250752
Directory /workspace/4.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_intg_err.340129583
Short name T458
Test name
Test status
Simulation time 1270852615 ps
CPU time 73.8 seconds
Started Feb 25 12:29:06 PM PST 24
Finished Feb 25 12:30:21 PM PST 24
Peak memory 212212 kb
Host smart-5ba4170e-9a33-4cef-ab94-71128d4fb9f7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=340129583 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_tl_int
g_err.340129583
Directory /workspace/4.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_mem_rw_with_rand_reset.2762281057
Short name T364
Test name
Test status
Simulation time 6212468396 ps
CPU time 13.99 seconds
Started Feb 25 12:29:21 PM PST 24
Finished Feb 25 12:29:35 PM PST 24
Peak memory 215224 kb
Host smart-a5f864cc-9657-4389-baf9-e514e2b6d02b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2762281057 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 5.rom_ctrl_csr_mem_rw_with_rand_reset.2762281057
Directory /workspace/5.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_rw.1342116145
Short name T65
Test name
Test status
Simulation time 174741979 ps
CPU time 4.21 seconds
Started Feb 25 12:29:17 PM PST 24
Finished Feb 25 12:29:22 PM PST 24
Peak memory 210536 kb
Host smart-44f6c5ed-ca0f-4270-a0b0-88268505910e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1342116145 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_csr_rw.1342116145
Directory /workspace/5.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_passthru_mem_tl_intg_err.3997490074
Short name T88
Test name
Test status
Simulation time 1213149555 ps
CPU time 27.63 seconds
Started Feb 25 12:29:30 PM PST 24
Finished Feb 25 12:29:58 PM PST 24
Peak memory 210548 kb
Host smart-0a3d5ea2-30c5-4a55-b007-d65ee79c0699
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3997490074 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_pa
ssthru_mem_tl_intg_err.3997490074
Directory /workspace/5.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_same_csr_outstanding.3691275318
Short name T405
Test name
Test status
Simulation time 1475865621 ps
CPU time 12.9 seconds
Started Feb 25 12:29:05 PM PST 24
Finished Feb 25 12:29:18 PM PST 24
Peak memory 210584 kb
Host smart-ea6ae4f1-2553-434a-a02a-0125916abd8c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3691275318 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_c
trl_same_csr_outstanding.3691275318
Directory /workspace/5.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_errors.1295674934
Short name T417
Test name
Test status
Simulation time 6144984998 ps
CPU time 15.9 seconds
Started Feb 25 12:29:02 PM PST 24
Finished Feb 25 12:29:18 PM PST 24
Peak memory 214936 kb
Host smart-0ba9c743-6ecd-435f-8668-17e2ee0a45e2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1295674934 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_tl_errors.1295674934
Directory /workspace/5.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_intg_err.2661977487
Short name T127
Test name
Test status
Simulation time 722993736 ps
CPU time 68 seconds
Started Feb 25 12:29:21 PM PST 24
Finished Feb 25 12:30:29 PM PST 24
Peak memory 210588 kb
Host smart-893f700a-162f-45a7-acbc-5824965f31ad
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2661977487 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_tl_in
tg_err.2661977487
Directory /workspace/5.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_mem_rw_with_rand_reset.2656277580
Short name T400
Test name
Test status
Simulation time 224497424 ps
CPU time 6.65 seconds
Started Feb 25 12:29:09 PM PST 24
Finished Feb 25 12:29:16 PM PST 24
Peak memory 215364 kb
Host smart-908374c6-d526-4179-91d6-4b36b4e5a244
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2656277580 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 6.rom_ctrl_csr_mem_rw_with_rand_reset.2656277580
Directory /workspace/6.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_rw.1009286905
Short name T459
Test name
Test status
Simulation time 6696779227 ps
CPU time 14.22 seconds
Started Feb 25 12:29:04 PM PST 24
Finished Feb 25 12:29:18 PM PST 24
Peak memory 210596 kb
Host smart-37ee3e03-b987-4ebd-9f2e-4e49bd65f148
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1009286905 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_csr_rw.1009286905
Directory /workspace/6.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_passthru_mem_tl_intg_err.1474561147
Short name T111
Test name
Test status
Simulation time 11360931465 ps
CPU time 60.73 seconds
Started Feb 25 12:29:21 PM PST 24
Finished Feb 25 12:30:22 PM PST 24
Peak memory 210592 kb
Host smart-6e13a7a0-453c-4500-b948-6aed183e34cd
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1474561147 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_pa
ssthru_mem_tl_intg_err.1474561147
Directory /workspace/6.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_same_csr_outstanding.2053563362
Short name T389
Test name
Test status
Simulation time 744954573 ps
CPU time 8.77 seconds
Started Feb 25 12:29:18 PM PST 24
Finished Feb 25 12:29:27 PM PST 24
Peak memory 210600 kb
Host smart-d9cba4bf-4fd1-400a-bc27-bff21013c4f5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2053563362 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_c
trl_same_csr_outstanding.2053563362
Directory /workspace/6.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_errors.1672524998
Short name T367
Test name
Test status
Simulation time 3172432145 ps
CPU time 15.5 seconds
Started Feb 25 12:29:12 PM PST 24
Finished Feb 25 12:29:28 PM PST 24
Peak memory 213616 kb
Host smart-ead3b867-c583-4ec6-8758-a852f5533b8a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1672524998 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_tl_errors.1672524998
Directory /workspace/6.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_intg_err.3161977888
Short name T125
Test name
Test status
Simulation time 738752674 ps
CPU time 71.5 seconds
Started Feb 25 12:29:04 PM PST 24
Finished Feb 25 12:30:16 PM PST 24
Peak memory 210588 kb
Host smart-f2232750-e4c9-4b73-b4ed-b1899a9253f9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3161977888 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_tl_in
tg_err.3161977888
Directory /workspace/6.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_mem_rw_with_rand_reset.551792611
Short name T408
Test name
Test status
Simulation time 1382327617 ps
CPU time 13.07 seconds
Started Feb 25 12:29:07 PM PST 24
Finished Feb 25 12:29:20 PM PST 24
Peak memory 214940 kb
Host smart-e9fd9b24-e62e-4d94-90d8-93c883ebc7a0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=551792611 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 7.rom_ctrl_csr_mem_rw_with_rand_reset.551792611
Directory /workspace/7.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_rw.3462893322
Short name T407
Test name
Test status
Simulation time 395789586 ps
CPU time 4.25 seconds
Started Feb 25 12:29:06 PM PST 24
Finished Feb 25 12:29:10 PM PST 24
Peak memory 210528 kb
Host smart-b891eded-403e-49b4-a55b-3fa819d5986e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3462893322 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_csr_rw.3462893322
Directory /workspace/7.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_passthru_mem_tl_intg_err.1596201126
Short name T110
Test name
Test status
Simulation time 7136568427 ps
CPU time 58.33 seconds
Started Feb 25 12:29:05 PM PST 24
Finished Feb 25 12:30:04 PM PST 24
Peak memory 210592 kb
Host smart-b9eb773c-2aa7-4370-8253-3bbe7c5eddc4
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1596201126 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_pa
ssthru_mem_tl_intg_err.1596201126
Directory /workspace/7.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_same_csr_outstanding.2614513053
Short name T428
Test name
Test status
Simulation time 8071910555 ps
CPU time 16.05 seconds
Started Feb 25 12:29:19 PM PST 24
Finished Feb 25 12:29:35 PM PST 24
Peak memory 210644 kb
Host smart-5fd51491-1ef4-4960-aa21-ac8080b6c090
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2614513053 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_c
trl_same_csr_outstanding.2614513053
Directory /workspace/7.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_errors.1515844788
Short name T376
Test name
Test status
Simulation time 2617645686 ps
CPU time 14.68 seconds
Started Feb 25 12:29:21 PM PST 24
Finished Feb 25 12:29:37 PM PST 24
Peak memory 215064 kb
Host smart-dfdd1ed9-0565-4fab-bfd3-c64a0a147fc3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1515844788 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_tl_errors.1515844788
Directory /workspace/7.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_intg_err.4225701839
Short name T124
Test name
Test status
Simulation time 166529048 ps
CPU time 37.46 seconds
Started Feb 25 12:29:07 PM PST 24
Finished Feb 25 12:29:45 PM PST 24
Peak memory 210580 kb
Host smart-ed24af80-4b67-4969-a42e-696da455bef9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4225701839 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_tl_in
tg_err.4225701839
Directory /workspace/7.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_mem_rw_with_rand_reset.2399732468
Short name T386
Test name
Test status
Simulation time 16381904962 ps
CPU time 10.79 seconds
Started Feb 25 12:29:08 PM PST 24
Finished Feb 25 12:29:19 PM PST 24
Peak memory 218864 kb
Host smart-4140cdb9-4118-4029-bb71-6827168bfe17
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2399732468 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 8.rom_ctrl_csr_mem_rw_with_rand_reset.2399732468
Directory /workspace/8.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_rw.491139343
Short name T76
Test name
Test status
Simulation time 5404681938 ps
CPU time 9.63 seconds
Started Feb 25 12:29:18 PM PST 24
Finished Feb 25 12:29:27 PM PST 24
Peak memory 210596 kb
Host smart-2ed69219-19ef-40ac-b43c-6c3dae8f9823
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=491139343 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_csr_rw.491139343
Directory /workspace/8.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_passthru_mem_tl_intg_err.430025860
Short name T377
Test name
Test status
Simulation time 9184284790 ps
CPU time 79.3 seconds
Started Feb 25 12:29:22 PM PST 24
Finished Feb 25 12:30:41 PM PST 24
Peak memory 210064 kb
Host smart-158ac0ad-9b3a-4cfe-86fa-b9ad7e50d330
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=430025860 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_pas
sthru_mem_tl_intg_err.430025860
Directory /workspace/8.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_same_csr_outstanding.1485627897
Short name T409
Test name
Test status
Simulation time 10955056410 ps
CPU time 9.82 seconds
Started Feb 25 12:29:05 PM PST 24
Finished Feb 25 12:29:20 PM PST 24
Peak memory 210648 kb
Host smart-a6e59be4-6255-4817-9756-3d0d91a2d401
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1485627897 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_c
trl_same_csr_outstanding.1485627897
Directory /workspace/8.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_errors.3323895783
Short name T455
Test name
Test status
Simulation time 89082115 ps
CPU time 6.46 seconds
Started Feb 25 12:29:22 PM PST 24
Finished Feb 25 12:29:29 PM PST 24
Peak memory 214688 kb
Host smart-b62732b2-e925-4612-b570-578a90a9edad
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3323895783 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_tl_errors.3323895783
Directory /workspace/8.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_intg_err.2621569400
Short name T118
Test name
Test status
Simulation time 2914031171 ps
CPU time 36.68 seconds
Started Feb 25 12:29:07 PM PST 24
Finished Feb 25 12:29:45 PM PST 24
Peak memory 209872 kb
Host smart-c821ce20-c4d4-41d2-aff8-0ebd976426ab
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2621569400 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_tl_in
tg_err.2621569400
Directory /workspace/8.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_mem_rw_with_rand_reset.4263931512
Short name T432
Test name
Test status
Simulation time 455838237 ps
CPU time 7.54 seconds
Started Feb 25 12:29:04 PM PST 24
Finished Feb 25 12:29:12 PM PST 24
Peak memory 214016 kb
Host smart-3b02f02b-7de4-467b-a2db-7fd029c96cf4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4263931512 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 9.rom_ctrl_csr_mem_rw_with_rand_reset.4263931512
Directory /workspace/9.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_rw.249603304
Short name T418
Test name
Test status
Simulation time 85416464 ps
CPU time 4.27 seconds
Started Feb 25 12:29:21 PM PST 24
Finished Feb 25 12:29:25 PM PST 24
Peak memory 210548 kb
Host smart-163bc770-82ff-4685-ab49-f44e219ef2df
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=249603304 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_csr_rw.249603304
Directory /workspace/9.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_passthru_mem_tl_intg_err.1562838133
Short name T406
Test name
Test status
Simulation time 4618723838 ps
CPU time 44.96 seconds
Started Feb 25 12:29:17 PM PST 24
Finished Feb 25 12:30:02 PM PST 24
Peak memory 210580 kb
Host smart-627fba94-1ad1-487e-9d0b-9f18c7256172
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1562838133 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_pa
ssthru_mem_tl_intg_err.1562838133
Directory /workspace/9.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_same_csr_outstanding.3759534122
Short name T404
Test name
Test status
Simulation time 6087133652 ps
CPU time 13.62 seconds
Started Feb 25 12:29:24 PM PST 24
Finished Feb 25 12:29:38 PM PST 24
Peak memory 210364 kb
Host smart-1b7f79fd-40ea-4e29-864a-7e8dcd866fe1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3759534122 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_c
trl_same_csr_outstanding.3759534122
Directory /workspace/9.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_errors.1837113709
Short name T369
Test name
Test status
Simulation time 6495168686 ps
CPU time 16.82 seconds
Started Feb 25 12:29:34 PM PST 24
Finished Feb 25 12:29:51 PM PST 24
Peak memory 215236 kb
Host smart-823d2ca1-2329-4947-be29-0b72e108a689
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1837113709 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_tl_errors.1837113709
Directory /workspace/9.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_intg_err.431793866
Short name T121
Test name
Test status
Simulation time 1713312624 ps
CPU time 45.56 seconds
Started Feb 25 12:29:21 PM PST 24
Finished Feb 25 12:30:08 PM PST 24
Peak memory 210576 kb
Host smart-753e04de-f4ce-4afd-98cf-49b7c26aded5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=431793866 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_tl_int
g_err.431793866
Directory /workspace/9.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/0.rom_ctrl_alert_test.2054578509
Short name T363
Test name
Test status
Simulation time 9987010503 ps
CPU time 15.62 seconds
Started Feb 25 12:37:42 PM PST 24
Finished Feb 25 12:37:58 PM PST 24
Peak memory 211168 kb
Host smart-051506df-4228-4322-995a-514553d3983b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2054578509 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_alert_test.2054578509
Directory /workspace/0.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/0.rom_ctrl_corrupt_sig_fatal_chk.3034387309
Short name T148
Test name
Test status
Simulation time 19660135758 ps
CPU time 159.52 seconds
Started Feb 25 12:37:45 PM PST 24
Finished Feb 25 12:40:26 PM PST 24
Peak memory 234004 kb
Host smart-1ac942f7-e34e-4cce-9bd1-730463175667
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3034387309 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_c
orrupt_sig_fatal_chk.3034387309
Directory /workspace/0.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/0.rom_ctrl_kmac_err_chk.3561412667
Short name T360
Test name
Test status
Simulation time 11664514330 ps
CPU time 18.48 seconds
Started Feb 25 12:37:42 PM PST 24
Finished Feb 25 12:38:00 PM PST 24
Peak memory 211976 kb
Host smart-a9e69cba-b6e1-4761-9fe0-789eaa4f46be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3561412667 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_kmac_err_chk.3561412667
Directory /workspace/0.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/0.rom_ctrl_max_throughput_chk.1494413339
Short name T8
Test name
Test status
Simulation time 2202229619 ps
CPU time 12.31 seconds
Started Feb 25 12:37:42 PM PST 24
Finished Feb 25 12:37:54 PM PST 24
Peak memory 211120 kb
Host smart-145cdd30-f450-4761-81da-83ad04dd8f34
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1494413339 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_max_throughput_chk.1494413339
Directory /workspace/0.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/0.rom_ctrl_smoke.3808913512
Short name T168
Test name
Test status
Simulation time 751178722 ps
CPU time 10.64 seconds
Started Feb 25 12:37:37 PM PST 24
Finished Feb 25 12:37:52 PM PST 24
Peak memory 213788 kb
Host smart-5cb2f727-e79c-485b-bb5f-eb3a5fb007d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3808913512 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_smoke.3808913512
Directory /workspace/0.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/0.rom_ctrl_stress_all.186338670
Short name T288
Test name
Test status
Simulation time 103246042816 ps
CPU time 61.22 seconds
Started Feb 25 12:37:46 PM PST 24
Finished Feb 25 12:38:47 PM PST 24
Peak memory 216844 kb
Host smart-576683ba-9020-49e3-9a4d-ce7d2ee55b62
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=186338670 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 0.rom_ctrl_stress_all.186338670
Directory /workspace/0.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/1.rom_ctrl_corrupt_sig_fatal_chk.311283327
Short name T160
Test name
Test status
Simulation time 127154715097 ps
CPU time 316.91 seconds
Started Feb 25 12:37:47 PM PST 24
Finished Feb 25 12:43:04 PM PST 24
Peak memory 228800 kb
Host smart-095b177f-9120-4cd7-be31-871cbfed9c26
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=311283327 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_co
rrupt_sig_fatal_chk.311283327
Directory /workspace/1.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/1.rom_ctrl_kmac_err_chk.3899328284
Short name T287
Test name
Test status
Simulation time 13564646264 ps
CPU time 24.67 seconds
Started Feb 25 12:37:57 PM PST 24
Finished Feb 25 12:38:22 PM PST 24
Peak memory 211884 kb
Host smart-9d86753a-484b-4e10-8a6b-7529648218c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3899328284 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_kmac_err_chk.3899328284
Directory /workspace/1.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/1.rom_ctrl_max_throughput_chk.2903079222
Short name T158
Test name
Test status
Simulation time 7402692423 ps
CPU time 14.34 seconds
Started Feb 25 12:37:49 PM PST 24
Finished Feb 25 12:38:03 PM PST 24
Peak memory 211168 kb
Host smart-5453a7a0-9a3e-4b5d-bae0-43c96956ed9d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2903079222 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_max_throughput_chk.2903079222
Directory /workspace/1.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/1.rom_ctrl_sec_cm.2152123504
Short name T35
Test name
Test status
Simulation time 4405071058 ps
CPU time 104.95 seconds
Started Feb 25 12:38:00 PM PST 24
Finished Feb 25 12:39:45 PM PST 24
Peak memory 235936 kb
Host smart-e5a36008-4a64-4a82-8a43-6e9747e60d91
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2152123504 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_sec_cm.2152123504
Directory /workspace/1.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/1.rom_ctrl_smoke.556751302
Short name T41
Test name
Test status
Simulation time 12333017824 ps
CPU time 27.68 seconds
Started Feb 25 12:37:38 PM PST 24
Finished Feb 25 12:38:07 PM PST 24
Peak memory 213660 kb
Host smart-958db963-f26c-4057-9fc3-68428901904d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=556751302 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_smoke.556751302
Directory /workspace/1.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/1.rom_ctrl_stress_all.1278770508
Short name T174
Test name
Test status
Simulation time 8046818778 ps
CPU time 52.73 seconds
Started Feb 25 12:37:36 PM PST 24
Finished Feb 25 12:38:29 PM PST 24
Peak memory 215648 kb
Host smart-383a1046-db48-4263-9e73-b6c0e8c94b6f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1278770508 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 1.rom_ctrl_stress_all.1278770508
Directory /workspace/1.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/1.rom_ctrl_stress_all_with_rand_reset.2520418484
Short name T18
Test name
Test status
Simulation time 20311909013 ps
CPU time 1239.93 seconds
Started Feb 25 12:37:37 PM PST 24
Finished Feb 25 12:58:17 PM PST 24
Peak memory 224040 kb
Host smart-c218dcdf-3cee-45a0-86fc-f4e2104f274e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2520418484 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_stress_all_with_rand_reset.2520418484
Directory /workspace/1.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.rom_ctrl_alert_test.1563486473
Short name T200
Test name
Test status
Simulation time 1376817079 ps
CPU time 4.45 seconds
Started Feb 25 12:37:57 PM PST 24
Finished Feb 25 12:38:02 PM PST 24
Peak memory 211036 kb
Host smart-605656ba-c27c-4ea1-8922-6b18e5176fb1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1563486473 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_alert_test.1563486473
Directory /workspace/10.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/10.rom_ctrl_corrupt_sig_fatal_chk.3326901061
Short name T138
Test name
Test status
Simulation time 267817055213 ps
CPU time 166.63 seconds
Started Feb 25 12:37:51 PM PST 24
Finished Feb 25 12:40:37 PM PST 24
Peak memory 229576 kb
Host smart-27b03d94-05b9-4c51-b5ea-3b55b9bff401
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3326901061 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_
corrupt_sig_fatal_chk.3326901061
Directory /workspace/10.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/10.rom_ctrl_kmac_err_chk.1251504110
Short name T322
Test name
Test status
Simulation time 3649623949 ps
CPU time 31.48 seconds
Started Feb 25 12:37:53 PM PST 24
Finished Feb 25 12:38:25 PM PST 24
Peak memory 211608 kb
Host smart-c29ed7e0-f8c1-4947-8e35-bec81c32ce5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1251504110 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_kmac_err_chk.1251504110
Directory /workspace/10.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/10.rom_ctrl_max_throughput_chk.1286817566
Short name T337
Test name
Test status
Simulation time 2000454630 ps
CPU time 16.92 seconds
Started Feb 25 12:37:53 PM PST 24
Finished Feb 25 12:38:10 PM PST 24
Peak memory 211088 kb
Host smart-3aae2aa2-e317-4ff4-a34d-8af145a25117
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1286817566 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_max_throughput_chk.1286817566
Directory /workspace/10.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/10.rom_ctrl_stress_all.1741601896
Short name T203
Test name
Test status
Simulation time 78685358184 ps
CPU time 62.71 seconds
Started Feb 25 12:37:53 PM PST 24
Finished Feb 25 12:38:56 PM PST 24
Peak memory 219344 kb
Host smart-89852868-74e3-4bd9-989c-9f4e4bee8ce8
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1741601896 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 10.rom_ctrl_stress_all.1741601896
Directory /workspace/10.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/10.rom_ctrl_stress_all_with_rand_reset.4259947220
Short name T56
Test name
Test status
Simulation time 171295986213 ps
CPU time 1752.93 seconds
Started Feb 25 12:37:51 PM PST 24
Finished Feb 25 01:07:05 PM PST 24
Peak memory 244000 kb
Host smart-121adf4a-f21c-4417-a480-3b3b01ad4705
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4259947220 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_stress_all_with_rand_reset.4259947220
Directory /workspace/10.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/11.rom_ctrl_alert_test.3141820042
Short name T268
Test name
Test status
Simulation time 1725836098 ps
CPU time 9.73 seconds
Started Feb 25 12:37:53 PM PST 24
Finished Feb 25 12:38:03 PM PST 24
Peak memory 211020 kb
Host smart-c692efa3-935d-4540-9d61-863d15b756d7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3141820042 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_alert_test.3141820042
Directory /workspace/11.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/11.rom_ctrl_corrupt_sig_fatal_chk.2407624758
Short name T136
Test name
Test status
Simulation time 3610944078 ps
CPU time 159.9 seconds
Started Feb 25 12:37:58 PM PST 24
Finished Feb 25 12:40:38 PM PST 24
Peak memory 224964 kb
Host smart-928e4164-137d-4910-905b-b18d28a4013c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2407624758 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_
corrupt_sig_fatal_chk.2407624758
Directory /workspace/11.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/11.rom_ctrl_max_throughput_chk.1760724838
Short name T108
Test name
Test status
Simulation time 2295956570 ps
CPU time 11.96 seconds
Started Feb 25 12:37:45 PM PST 24
Finished Feb 25 12:37:58 PM PST 24
Peak memory 211080 kb
Host smart-4206d251-4996-49c9-9983-775889cf3694
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1760724838 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_max_throughput_chk.1760724838
Directory /workspace/11.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/11.rom_ctrl_smoke.3536726375
Short name T266
Test name
Test status
Simulation time 2625287167 ps
CPU time 33.54 seconds
Started Feb 25 12:37:53 PM PST 24
Finished Feb 25 12:38:26 PM PST 24
Peak memory 213268 kb
Host smart-c17961d7-0e79-4326-87d0-68b16d6025da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3536726375 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_smoke.3536726375
Directory /workspace/11.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/11.rom_ctrl_stress_all.3981768572
Short name T237
Test name
Test status
Simulation time 15545317951 ps
CPU time 56.37 seconds
Started Feb 25 12:37:52 PM PST 24
Finished Feb 25 12:38:49 PM PST 24
Peak memory 217400 kb
Host smart-f6feb8bd-157b-4a43-b361-cb7a5edac647
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3981768572 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 11.rom_ctrl_stress_all.3981768572
Directory /workspace/11.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/12.rom_ctrl_alert_test.451317729
Short name T162
Test name
Test status
Simulation time 89074146 ps
CPU time 4.4 seconds
Started Feb 25 12:37:54 PM PST 24
Finished Feb 25 12:37:58 PM PST 24
Peak memory 211260 kb
Host smart-df55351b-1151-41d4-a8a0-cb0c8758cd74
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=451317729 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_alert_test.451317729
Directory /workspace/12.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/12.rom_ctrl_corrupt_sig_fatal_chk.1819580702
Short name T229
Test name
Test status
Simulation time 22294066158 ps
CPU time 149.86 seconds
Started Feb 25 12:37:54 PM PST 24
Finished Feb 25 12:40:24 PM PST 24
Peak memory 212460 kb
Host smart-2914d9c2-9bfa-4cc3-a056-1d534f7d5683
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1819580702 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_
corrupt_sig_fatal_chk.1819580702
Directory /workspace/12.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/12.rom_ctrl_kmac_err_chk.4152980928
Short name T258
Test name
Test status
Simulation time 12678248111 ps
CPU time 27.65 seconds
Started Feb 25 12:37:54 PM PST 24
Finished Feb 25 12:38:22 PM PST 24
Peak memory 211872 kb
Host smart-69f76ce0-8561-40cf-97bf-40d8885d7e62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4152980928 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_kmac_err_chk.4152980928
Directory /workspace/12.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/12.rom_ctrl_max_throughput_chk.2976891218
Short name T307
Test name
Test status
Simulation time 2228261384 ps
CPU time 17.78 seconds
Started Feb 25 12:37:41 PM PST 24
Finished Feb 25 12:37:59 PM PST 24
Peak memory 211104 kb
Host smart-06394dcb-d0b5-404e-bb13-c5b15befdc08
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2976891218 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_max_throughput_chk.2976891218
Directory /workspace/12.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/12.rom_ctrl_smoke.2944183764
Short name T347
Test name
Test status
Simulation time 1301497105 ps
CPU time 17.17 seconds
Started Feb 25 12:37:49 PM PST 24
Finished Feb 25 12:38:07 PM PST 24
Peak memory 212888 kb
Host smart-c72684d0-8c4e-4de3-b667-313de055b2d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2944183764 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_smoke.2944183764
Directory /workspace/12.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/12.rom_ctrl_stress_all.2860282606
Short name T187
Test name
Test status
Simulation time 1033708147 ps
CPU time 6.35 seconds
Started Feb 25 12:37:59 PM PST 24
Finished Feb 25 12:38:06 PM PST 24
Peak memory 211048 kb
Host smart-3e1b6ba4-be5a-4d15-bd6c-a9f9bcf05f64
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2860282606 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 12.rom_ctrl_stress_all.2860282606
Directory /workspace/12.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/13.rom_ctrl_alert_test.3997009368
Short name T192
Test name
Test status
Simulation time 1971603284 ps
CPU time 11.91 seconds
Started Feb 25 12:37:52 PM PST 24
Finished Feb 25 12:38:04 PM PST 24
Peak memory 211012 kb
Host smart-78ce83cc-6199-4d99-8619-e32b6a7ff970
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3997009368 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_alert_test.3997009368
Directory /workspace/13.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/13.rom_ctrl_corrupt_sig_fatal_chk.2818249031
Short name T263
Test name
Test status
Simulation time 148294107487 ps
CPU time 401.53 seconds
Started Feb 25 12:37:51 PM PST 24
Finished Feb 25 12:44:33 PM PST 24
Peak memory 213396 kb
Host smart-2ddd2ace-6913-46bb-b77d-5e9419815789
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2818249031 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_
corrupt_sig_fatal_chk.2818249031
Directory /workspace/13.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/13.rom_ctrl_kmac_err_chk.3585131815
Short name T316
Test name
Test status
Simulation time 5941699897 ps
CPU time 30.49 seconds
Started Feb 25 12:37:48 PM PST 24
Finished Feb 25 12:38:19 PM PST 24
Peak memory 212300 kb
Host smart-e4a47998-06bb-413e-9e03-df78c169f537
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3585131815 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_kmac_err_chk.3585131815
Directory /workspace/13.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/13.rom_ctrl_max_throughput_chk.3150828514
Short name T191
Test name
Test status
Simulation time 97572946 ps
CPU time 5.52 seconds
Started Feb 25 12:37:51 PM PST 24
Finished Feb 25 12:37:57 PM PST 24
Peak memory 211020 kb
Host smart-c1693fb0-85c2-4a06-bf0d-00d467ee8203
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3150828514 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_max_throughput_chk.3150828514
Directory /workspace/13.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/13.rom_ctrl_smoke.3304427863
Short name T277
Test name
Test status
Simulation time 187430597 ps
CPU time 10.13 seconds
Started Feb 25 12:37:54 PM PST 24
Finished Feb 25 12:38:04 PM PST 24
Peak memory 213016 kb
Host smart-07b90844-3087-4073-961c-f567bae3673b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3304427863 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_smoke.3304427863
Directory /workspace/13.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/13.rom_ctrl_stress_all.1725434483
Short name T208
Test name
Test status
Simulation time 446163566 ps
CPU time 20.06 seconds
Started Feb 25 12:37:54 PM PST 24
Finished Feb 25 12:38:14 PM PST 24
Peak memory 219432 kb
Host smart-6e830362-ba80-40c8-8925-900b5733ae52
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1725434483 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 13.rom_ctrl_stress_all.1725434483
Directory /workspace/13.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/14.rom_ctrl_alert_test.3844752928
Short name T102
Test name
Test status
Simulation time 533527856 ps
CPU time 7.74 seconds
Started Feb 25 12:38:04 PM PST 24
Finished Feb 25 12:38:12 PM PST 24
Peak memory 211108 kb
Host smart-0eeb22ae-b2fa-4c8b-9ea6-3e60240eebae
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3844752928 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_alert_test.3844752928
Directory /workspace/14.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/14.rom_ctrl_corrupt_sig_fatal_chk.4180638964
Short name T217
Test name
Test status
Simulation time 77344982253 ps
CPU time 167.95 seconds
Started Feb 25 12:38:06 PM PST 24
Finished Feb 25 12:40:54 PM PST 24
Peak memory 230036 kb
Host smart-3f6204f6-2e39-46c3-b7ca-701e0e7dca94
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4180638964 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_
corrupt_sig_fatal_chk.4180638964
Directory /workspace/14.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/14.rom_ctrl_kmac_err_chk.597295252
Short name T318
Test name
Test status
Simulation time 2404029975 ps
CPU time 23.29 seconds
Started Feb 25 12:37:55 PM PST 24
Finished Feb 25 12:38:19 PM PST 24
Peak memory 211548 kb
Host smart-f5c6218c-fabc-4409-be7f-aa1e97c70f1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=597295252 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_kmac_err_chk.597295252
Directory /workspace/14.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/14.rom_ctrl_max_throughput_chk.2008315995
Short name T44
Test name
Test status
Simulation time 102159506 ps
CPU time 5.86 seconds
Started Feb 25 12:37:55 PM PST 24
Finished Feb 25 12:38:01 PM PST 24
Peak memory 211052 kb
Host smart-9886969d-fcf9-4a3a-b468-4dafe6d94f6f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2008315995 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_max_throughput_chk.2008315995
Directory /workspace/14.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/14.rom_ctrl_smoke.368009680
Short name T43
Test name
Test status
Simulation time 4624962450 ps
CPU time 19.42 seconds
Started Feb 25 12:37:51 PM PST 24
Finished Feb 25 12:38:10 PM PST 24
Peak memory 213684 kb
Host smart-a84f4c61-7e7e-4930-b57c-1fa19adea4bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=368009680 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_smoke.368009680
Directory /workspace/14.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/14.rom_ctrl_stress_all.1091394852
Short name T98
Test name
Test status
Simulation time 3692652464 ps
CPU time 17.06 seconds
Started Feb 25 12:37:46 PM PST 24
Finished Feb 25 12:38:03 PM PST 24
Peak memory 213488 kb
Host smart-d59975d3-5ce6-4ad6-a55e-c9abfcf43d75
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1091394852 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 14.rom_ctrl_stress_all.1091394852
Directory /workspace/14.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/15.rom_ctrl_alert_test.58715063
Short name T300
Test name
Test status
Simulation time 5064866260 ps
CPU time 12.37 seconds
Started Feb 25 12:37:54 PM PST 24
Finished Feb 25 12:38:06 PM PST 24
Peak memory 211136 kb
Host smart-9348084a-8453-4777-b276-5bff937b67ad
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58715063 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_alert_test.58715063
Directory /workspace/15.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/15.rom_ctrl_corrupt_sig_fatal_chk.1740484065
Short name T313
Test name
Test status
Simulation time 5565129921 ps
CPU time 100 seconds
Started Feb 25 12:37:54 PM PST 24
Finished Feb 25 12:39:34 PM PST 24
Peak memory 237844 kb
Host smart-613a3487-3012-4d7e-bec3-5ef5eea73dd8
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1740484065 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_
corrupt_sig_fatal_chk.1740484065
Directory /workspace/15.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/15.rom_ctrl_kmac_err_chk.1879254533
Short name T273
Test name
Test status
Simulation time 876333063 ps
CPU time 15.16 seconds
Started Feb 25 12:37:58 PM PST 24
Finished Feb 25 12:38:14 PM PST 24
Peak memory 211784 kb
Host smart-d519571c-69fe-4f4c-9c9a-9b4aa386c5fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1879254533 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_kmac_err_chk.1879254533
Directory /workspace/15.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/15.rom_ctrl_max_throughput_chk.4182502779
Short name T346
Test name
Test status
Simulation time 967459721 ps
CPU time 8.81 seconds
Started Feb 25 12:38:08 PM PST 24
Finished Feb 25 12:38:17 PM PST 24
Peak memory 211016 kb
Host smart-03a78dec-5417-4d93-bbf3-357eb9cd7bdc
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4182502779 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_max_throughput_chk.4182502779
Directory /workspace/15.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/15.rom_ctrl_smoke.4195223595
Short name T48
Test name
Test status
Simulation time 3530476151 ps
CPU time 15.48 seconds
Started Feb 25 12:37:54 PM PST 24
Finished Feb 25 12:38:09 PM PST 24
Peak memory 211828 kb
Host smart-3782ccb5-545c-4b1c-85ce-8cdaefed2fd3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4195223595 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_smoke.4195223595
Directory /workspace/15.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/15.rom_ctrl_stress_all.1221324851
Short name T212
Test name
Test status
Simulation time 357944472 ps
CPU time 10.3 seconds
Started Feb 25 12:37:52 PM PST 24
Finished Feb 25 12:38:02 PM PST 24
Peak memory 214264 kb
Host smart-82ad58a1-501f-457e-a740-7def8c8832f8
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1221324851 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 15.rom_ctrl_stress_all.1221324851
Directory /workspace/15.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/16.rom_ctrl_alert_test.787562774
Short name T96
Test name
Test status
Simulation time 2656841312 ps
CPU time 11.99 seconds
Started Feb 25 12:37:57 PM PST 24
Finished Feb 25 12:38:09 PM PST 24
Peak memory 211072 kb
Host smart-c7dd2827-d82a-4d6c-ad28-9990be1f80f7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=787562774 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_alert_test.787562774
Directory /workspace/16.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/16.rom_ctrl_corrupt_sig_fatal_chk.2171694238
Short name T352
Test name
Test status
Simulation time 62980502649 ps
CPU time 600.97 seconds
Started Feb 25 12:38:00 PM PST 24
Finished Feb 25 12:48:02 PM PST 24
Peak memory 213272 kb
Host smart-15a42a5b-b140-4b5e-80e1-b902cad2103c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2171694238 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_
corrupt_sig_fatal_chk.2171694238
Directory /workspace/16.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/16.rom_ctrl_max_throughput_chk.1154717397
Short name T350
Test name
Test status
Simulation time 1635666148 ps
CPU time 7.95 seconds
Started Feb 25 12:38:11 PM PST 24
Finished Feb 25 12:38:19 PM PST 24
Peak memory 211048 kb
Host smart-6efc3c0f-0cba-4583-a8af-db5b79e01d18
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1154717397 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_max_throughput_chk.1154717397
Directory /workspace/16.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/16.rom_ctrl_stress_all.3164132820
Short name T250
Test name
Test status
Simulation time 8099296955 ps
CPU time 83.76 seconds
Started Feb 25 12:37:55 PM PST 24
Finished Feb 25 12:39:19 PM PST 24
Peak memory 215128 kb
Host smart-61ee9230-7034-496d-bfa3-46febf203864
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3164132820 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 16.rom_ctrl_stress_all.3164132820
Directory /workspace/16.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/17.rom_ctrl_alert_test.555443374
Short name T71
Test name
Test status
Simulation time 14545014664 ps
CPU time 12.59 seconds
Started Feb 25 12:37:58 PM PST 24
Finished Feb 25 12:38:11 PM PST 24
Peak memory 211164 kb
Host smart-65c944c3-650f-44da-ba9c-4a75f366dd1a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=555443374 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_alert_test.555443374
Directory /workspace/17.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/17.rom_ctrl_corrupt_sig_fatal_chk.4292383369
Short name T353
Test name
Test status
Simulation time 34468107355 ps
CPU time 230.58 seconds
Started Feb 25 12:37:55 PM PST 24
Finished Feb 25 12:41:46 PM PST 24
Peak memory 237876 kb
Host smart-426ae2f1-9bc5-44d1-abc1-5155de6e3151
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4292383369 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_
corrupt_sig_fatal_chk.4292383369
Directory /workspace/17.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/17.rom_ctrl_kmac_err_chk.929915045
Short name T99
Test name
Test status
Simulation time 10690112254 ps
CPU time 27.66 seconds
Started Feb 25 12:37:58 PM PST 24
Finished Feb 25 12:38:26 PM PST 24
Peak memory 212008 kb
Host smart-004e0649-2520-4a02-b467-6ab4ba5a25b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=929915045 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_kmac_err_chk.929915045
Directory /workspace/17.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/17.rom_ctrl_max_throughput_chk.35694807
Short name T163
Test name
Test status
Simulation time 1268253882 ps
CPU time 5.34 seconds
Started Feb 25 12:37:57 PM PST 24
Finished Feb 25 12:38:02 PM PST 24
Peak memory 211020 kb
Host smart-013188e2-7eb3-4dc5-aacc-a0cc5ec10eed
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=35694807 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_max_throughput_chk.35694807
Directory /workspace/17.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/17.rom_ctrl_smoke.2231015782
Short name T249
Test name
Test status
Simulation time 4021588074 ps
CPU time 37.84 seconds
Started Feb 25 12:37:55 PM PST 24
Finished Feb 25 12:38:33 PM PST 24
Peak memory 212180 kb
Host smart-0c39f43b-359c-41db-af08-43dea494d502
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2231015782 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_smoke.2231015782
Directory /workspace/17.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/17.rom_ctrl_stress_all.1745099874
Short name T209
Test name
Test status
Simulation time 183252087552 ps
CPU time 167.38 seconds
Started Feb 25 12:37:54 PM PST 24
Finished Feb 25 12:40:42 PM PST 24
Peak memory 216356 kb
Host smart-1e8817e7-59a5-4ff2-853b-f38cb468586a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1745099874 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 17.rom_ctrl_stress_all.1745099874
Directory /workspace/17.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/18.rom_ctrl_alert_test.1394935071
Short name T260
Test name
Test status
Simulation time 1047031236 ps
CPU time 10.79 seconds
Started Feb 25 12:37:53 PM PST 24
Finished Feb 25 12:38:04 PM PST 24
Peak memory 211048 kb
Host smart-62136901-580c-414f-ad6f-b142f6d9b9d4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1394935071 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_alert_test.1394935071
Directory /workspace/18.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/18.rom_ctrl_corrupt_sig_fatal_chk.2644576954
Short name T32
Test name
Test status
Simulation time 36833206855 ps
CPU time 323.9 seconds
Started Feb 25 12:37:57 PM PST 24
Finished Feb 25 12:43:22 PM PST 24
Peak memory 224612 kb
Host smart-8827d7d6-7cb7-48f1-8a82-9340a3149344
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2644576954 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_
corrupt_sig_fatal_chk.2644576954
Directory /workspace/18.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/18.rom_ctrl_max_throughput_chk.3661074990
Short name T251
Test name
Test status
Simulation time 6352318724 ps
CPU time 10.68 seconds
Started Feb 25 12:37:56 PM PST 24
Finished Feb 25 12:38:06 PM PST 24
Peak memory 211116 kb
Host smart-6ec1ddde-90e8-4d73-943e-542b820156ce
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3661074990 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_max_throughput_chk.3661074990
Directory /workspace/18.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/18.rom_ctrl_smoke.1040675147
Short name T12
Test name
Test status
Simulation time 593717615 ps
CPU time 15.57 seconds
Started Feb 25 12:38:04 PM PST 24
Finished Feb 25 12:38:20 PM PST 24
Peak memory 213368 kb
Host smart-12b4e980-80a8-4f61-9880-0d1554050992
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1040675147 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_smoke.1040675147
Directory /workspace/18.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/18.rom_ctrl_stress_all.2186166346
Short name T357
Test name
Test status
Simulation time 24081461892 ps
CPU time 60.05 seconds
Started Feb 25 12:37:58 PM PST 24
Finished Feb 25 12:38:58 PM PST 24
Peak memory 213600 kb
Host smart-70fe8247-765a-4d9a-93ec-77c831326385
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2186166346 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 18.rom_ctrl_stress_all.2186166346
Directory /workspace/18.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/19.rom_ctrl_alert_test.668102759
Short name T202
Test name
Test status
Simulation time 17751181485 ps
CPU time 16.62 seconds
Started Feb 25 12:37:53 PM PST 24
Finished Feb 25 12:38:09 PM PST 24
Peak memory 211136 kb
Host smart-4046cdf5-28af-4a3d-af14-c3f9656dc695
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=668102759 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_alert_test.668102759
Directory /workspace/19.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/19.rom_ctrl_corrupt_sig_fatal_chk.108719216
Short name T103
Test name
Test status
Simulation time 29960631914 ps
CPU time 119.52 seconds
Started Feb 25 12:37:56 PM PST 24
Finished Feb 25 12:39:55 PM PST 24
Peak memory 228296 kb
Host smart-43446a01-4a39-4654-bd54-6b09e376a50a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=108719216 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_c
orrupt_sig_fatal_chk.108719216
Directory /workspace/19.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/19.rom_ctrl_kmac_err_chk.2804341938
Short name T28
Test name
Test status
Simulation time 9025135975 ps
CPU time 15.86 seconds
Started Feb 25 12:38:11 PM PST 24
Finished Feb 25 12:38:27 PM PST 24
Peak memory 211752 kb
Host smart-4ca77116-c18b-4502-b4f4-609f5ee4b2ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2804341938 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_kmac_err_chk.2804341938
Directory /workspace/19.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/19.rom_ctrl_max_throughput_chk.1832581683
Short name T7
Test name
Test status
Simulation time 97327676 ps
CPU time 5.65 seconds
Started Feb 25 12:37:54 PM PST 24
Finished Feb 25 12:38:00 PM PST 24
Peak memory 211020 kb
Host smart-816de12d-6be3-425f-bd4c-db103a63007b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1832581683 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_max_throughput_chk.1832581683
Directory /workspace/19.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/19.rom_ctrl_smoke.1967421565
Short name T252
Test name
Test status
Simulation time 8928340164 ps
CPU time 22.37 seconds
Started Feb 25 12:38:06 PM PST 24
Finished Feb 25 12:38:28 PM PST 24
Peak memory 213840 kb
Host smart-bda086e3-329d-4181-ace2-cd3c5a591842
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1967421565 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_smoke.1967421565
Directory /workspace/19.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/19.rom_ctrl_stress_all.3942581625
Short name T181
Test name
Test status
Simulation time 2150305725 ps
CPU time 46.23 seconds
Started Feb 25 12:38:06 PM PST 24
Finished Feb 25 12:38:52 PM PST 24
Peak memory 216336 kb
Host smart-1ac5f0d1-0839-432b-8734-2b9efae198cb
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3942581625 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 19.rom_ctrl_stress_all.3942581625
Directory /workspace/19.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/19.rom_ctrl_stress_all_with_rand_reset.507035788
Short name T53
Test name
Test status
Simulation time 28009288609 ps
CPU time 985.85 seconds
Started Feb 25 12:38:13 PM PST 24
Finished Feb 25 12:54:40 PM PST 24
Peak memory 229332 kb
Host smart-b87bc535-4045-44c6-9ae0-bf4ffabfafcc
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=507035788 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_stress_all_with_rand_reset.507035788
Directory /workspace/19.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.rom_ctrl_alert_test.1002040609
Short name T336
Test name
Test status
Simulation time 437201270 ps
CPU time 4.29 seconds
Started Feb 25 12:37:48 PM PST 24
Finished Feb 25 12:37:52 PM PST 24
Peak memory 211000 kb
Host smart-97397b65-89f0-45b1-b256-0d5965b343f9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1002040609 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_alert_test.1002040609
Directory /workspace/2.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/2.rom_ctrl_corrupt_sig_fatal_chk.4084772330
Short name T282
Test name
Test status
Simulation time 54599460386 ps
CPU time 198.61 seconds
Started Feb 25 12:37:50 PM PST 24
Finished Feb 25 12:41:09 PM PST 24
Peak memory 228432 kb
Host smart-a6cd1610-9443-4fae-b206-b55d7822aab6
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4084772330 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_c
orrupt_sig_fatal_chk.4084772330
Directory /workspace/2.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/2.rom_ctrl_kmac_err_chk.1175205549
Short name T349
Test name
Test status
Simulation time 10035499516 ps
CPU time 17.74 seconds
Started Feb 25 12:37:32 PM PST 24
Finished Feb 25 12:37:50 PM PST 24
Peak memory 211984 kb
Host smart-56db55e7-71ff-415c-baa8-3d610edded67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1175205549 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_kmac_err_chk.1175205549
Directory /workspace/2.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/2.rom_ctrl_max_throughput_chk.1543836720
Short name T232
Test name
Test status
Simulation time 2006527365 ps
CPU time 16.86 seconds
Started Feb 25 12:37:31 PM PST 24
Finished Feb 25 12:37:48 PM PST 24
Peak memory 211052 kb
Host smart-68dc80b4-131b-4231-b3b7-5b6af7ac49d1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1543836720 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_max_throughput_chk.1543836720
Directory /workspace/2.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/2.rom_ctrl_sec_cm.59335590
Short name T39
Test name
Test status
Simulation time 2181840474 ps
CPU time 102.61 seconds
Started Feb 25 12:37:50 PM PST 24
Finished Feb 25 12:39:33 PM PST 24
Peak memory 232820 kb
Host smart-207d4c28-b87a-4026-a592-aab55df5e1d7
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=59335590 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_sec_cm.59335590
Directory /workspace/2.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/2.rom_ctrl_smoke.1244649572
Short name T235
Test name
Test status
Simulation time 2689172416 ps
CPU time 15.64 seconds
Started Feb 25 12:37:25 PM PST 24
Finished Feb 25 12:37:41 PM PST 24
Peak memory 211892 kb
Host smart-88d78241-5afd-429a-bd5a-a4d1878a035f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1244649572 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_smoke.1244649572
Directory /workspace/2.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/2.rom_ctrl_stress_all.2762695848
Short name T140
Test name
Test status
Simulation time 4123160036 ps
CPU time 17.79 seconds
Started Feb 25 12:37:52 PM PST 24
Finished Feb 25 12:38:10 PM PST 24
Peak memory 211108 kb
Host smart-5715e6e5-75be-43ea-ac5d-4fc65080c3d8
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2762695848 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 2.rom_ctrl_stress_all.2762695848
Directory /workspace/2.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/20.rom_ctrl_alert_test.1001902178
Short name T205
Test name
Test status
Simulation time 2723376472 ps
CPU time 8.3 seconds
Started Feb 25 12:38:09 PM PST 24
Finished Feb 25 12:38:17 PM PST 24
Peak memory 211016 kb
Host smart-84c0e2a4-2cfc-486a-aac6-d30aff2ad748
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1001902178 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_alert_test.1001902178
Directory /workspace/20.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/20.rom_ctrl_corrupt_sig_fatal_chk.1659981175
Short name T354
Test name
Test status
Simulation time 19807903944 ps
CPU time 254.03 seconds
Started Feb 25 12:38:19 PM PST 24
Finished Feb 25 12:42:33 PM PST 24
Peak memory 212376 kb
Host smart-1d68043f-f401-428e-b30a-28c367453b27
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1659981175 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_
corrupt_sig_fatal_chk.1659981175
Directory /workspace/20.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/20.rom_ctrl_kmac_err_chk.2893295524
Short name T261
Test name
Test status
Simulation time 692104025 ps
CPU time 9.35 seconds
Started Feb 25 12:38:08 PM PST 24
Finished Feb 25 12:38:18 PM PST 24
Peak memory 211780 kb
Host smart-190635f4-564d-4280-95c7-1549853bcda9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2893295524 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_kmac_err_chk.2893295524
Directory /workspace/20.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/20.rom_ctrl_max_throughput_chk.433889114
Short name T11
Test name
Test status
Simulation time 1511274416 ps
CPU time 13.31 seconds
Started Feb 25 12:38:05 PM PST 24
Finished Feb 25 12:38:18 PM PST 24
Peak memory 211016 kb
Host smart-f617202a-7d0a-48fa-af06-672e6ce3e478
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=433889114 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_max_throughput_chk.433889114
Directory /workspace/20.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/20.rom_ctrl_smoke.4266598484
Short name T340
Test name
Test status
Simulation time 35606750019 ps
CPU time 31.47 seconds
Started Feb 25 12:38:02 PM PST 24
Finished Feb 25 12:38:35 PM PST 24
Peak memory 213960 kb
Host smart-c1c999b1-52db-4aea-b3fe-5fa6b19602dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4266598484 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_smoke.4266598484
Directory /workspace/20.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/20.rom_ctrl_stress_all.2384719048
Short name T45
Test name
Test status
Simulation time 19759538722 ps
CPU time 69.03 seconds
Started Feb 25 12:37:58 PM PST 24
Finished Feb 25 12:39:07 PM PST 24
Peak memory 219408 kb
Host smart-9648a4af-22c5-4389-889e-d162ce103e9f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2384719048 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 20.rom_ctrl_stress_all.2384719048
Directory /workspace/20.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/21.rom_ctrl_alert_test.3703233085
Short name T224
Test name
Test status
Simulation time 19267608311 ps
CPU time 12.77 seconds
Started Feb 25 12:38:07 PM PST 24
Finished Feb 25 12:38:20 PM PST 24
Peak memory 211252 kb
Host smart-b8d92bea-7e7a-424b-845b-249e38accec1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3703233085 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_alert_test.3703233085
Directory /workspace/21.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/21.rom_ctrl_corrupt_sig_fatal_chk.2233648463
Short name T298
Test name
Test status
Simulation time 46756801698 ps
CPU time 128.21 seconds
Started Feb 25 12:37:56 PM PST 24
Finished Feb 25 12:40:05 PM PST 24
Peak memory 236844 kb
Host smart-06c4ce68-b081-4f2d-9337-b81bf4ac7c47
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2233648463 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_
corrupt_sig_fatal_chk.2233648463
Directory /workspace/21.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/21.rom_ctrl_kmac_err_chk.2375805368
Short name T175
Test name
Test status
Simulation time 175748447 ps
CPU time 9.39 seconds
Started Feb 25 12:37:57 PM PST 24
Finished Feb 25 12:38:06 PM PST 24
Peak memory 211792 kb
Host smart-bb28bb54-3213-447c-b12a-e4502dcbc6aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2375805368 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_kmac_err_chk.2375805368
Directory /workspace/21.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/21.rom_ctrl_max_throughput_chk.2048892528
Short name T356
Test name
Test status
Simulation time 376147064 ps
CPU time 5.93 seconds
Started Feb 25 12:37:57 PM PST 24
Finished Feb 25 12:38:03 PM PST 24
Peak memory 211032 kb
Host smart-70099ef0-5db2-4404-91d1-9a501e351752
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2048892528 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_max_throughput_chk.2048892528
Directory /workspace/21.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/21.rom_ctrl_smoke.2701116770
Short name T269
Test name
Test status
Simulation time 961926991 ps
CPU time 17.73 seconds
Started Feb 25 12:38:04 PM PST 24
Finished Feb 25 12:38:21 PM PST 24
Peak memory 212916 kb
Host smart-9f792a41-c268-4edf-b67d-be6f3e604eaa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2701116770 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_smoke.2701116770
Directory /workspace/21.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/21.rom_ctrl_stress_all.3281099466
Short name T100
Test name
Test status
Simulation time 34272180915 ps
CPU time 82.35 seconds
Started Feb 25 12:38:02 PM PST 24
Finished Feb 25 12:39:26 PM PST 24
Peak memory 217444 kb
Host smart-44abffe4-3b31-4048-ab58-78e293314abc
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3281099466 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 21.rom_ctrl_stress_all.3281099466
Directory /workspace/21.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/22.rom_ctrl_alert_test.1542133067
Short name T214
Test name
Test status
Simulation time 972459248 ps
CPU time 10.17 seconds
Started Feb 25 12:37:56 PM PST 24
Finished Feb 25 12:38:07 PM PST 24
Peak memory 210988 kb
Host smart-e10c9e2f-dc1d-4a54-b153-73594f0a5cac
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1542133067 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_alert_test.1542133067
Directory /workspace/22.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/22.rom_ctrl_corrupt_sig_fatal_chk.1747140670
Short name T144
Test name
Test status
Simulation time 270343149252 ps
CPU time 344.92 seconds
Started Feb 25 12:38:14 PM PST 24
Finished Feb 25 12:43:59 PM PST 24
Peak memory 236612 kb
Host smart-f989c0a1-95e6-4993-9dbf-7b717ff1d5cd
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1747140670 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_
corrupt_sig_fatal_chk.1747140670
Directory /workspace/22.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/22.rom_ctrl_kmac_err_chk.2694285090
Short name T157
Test name
Test status
Simulation time 8353641690 ps
CPU time 25.66 seconds
Started Feb 25 12:37:58 PM PST 24
Finished Feb 25 12:38:24 PM PST 24
Peak memory 212328 kb
Host smart-4bc9ab04-f416-42d6-b36f-36acc6215d06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2694285090 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_kmac_err_chk.2694285090
Directory /workspace/22.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/22.rom_ctrl_smoke.1838764992
Short name T185
Test name
Test status
Simulation time 7674608199 ps
CPU time 30.01 seconds
Started Feb 25 12:38:04 PM PST 24
Finished Feb 25 12:38:34 PM PST 24
Peak memory 213744 kb
Host smart-18ea7df2-5719-44c6-a4a3-2662f57cbada
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1838764992 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_smoke.1838764992
Directory /workspace/22.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/22.rom_ctrl_stress_all.2806841427
Short name T329
Test name
Test status
Simulation time 1802237035 ps
CPU time 20.46 seconds
Started Feb 25 12:37:54 PM PST 24
Finished Feb 25 12:38:14 PM PST 24
Peak memory 210860 kb
Host smart-f06f23c0-6fdb-450f-9a0b-8d66282273f6
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2806841427 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 22.rom_ctrl_stress_all.2806841427
Directory /workspace/22.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/23.rom_ctrl_alert_test.2594649279
Short name T317
Test name
Test status
Simulation time 4091131623 ps
CPU time 15.88 seconds
Started Feb 25 12:38:13 PM PST 24
Finished Feb 25 12:38:30 PM PST 24
Peak memory 211080 kb
Host smart-5db9aa8d-f643-444e-9ffb-59f7944bb9de
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2594649279 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_alert_test.2594649279
Directory /workspace/23.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/23.rom_ctrl_corrupt_sig_fatal_chk.2745101054
Short name T339
Test name
Test status
Simulation time 18134193727 ps
CPU time 151.1 seconds
Started Feb 25 12:37:58 PM PST 24
Finished Feb 25 12:40:30 PM PST 24
Peak memory 237776 kb
Host smart-8576ab03-b60b-44fc-8fa5-85ae063a2261
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2745101054 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_
corrupt_sig_fatal_chk.2745101054
Directory /workspace/23.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/23.rom_ctrl_kmac_err_chk.3676919172
Short name T167
Test name
Test status
Simulation time 4221136890 ps
CPU time 32.27 seconds
Started Feb 25 12:38:00 PM PST 24
Finished Feb 25 12:38:32 PM PST 24
Peak memory 212088 kb
Host smart-88ca86be-c0b3-4117-8317-4d859ec69647
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3676919172 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_kmac_err_chk.3676919172
Directory /workspace/23.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/23.rom_ctrl_max_throughput_chk.2075919568
Short name T47
Test name
Test status
Simulation time 100171736 ps
CPU time 5.48 seconds
Started Feb 25 12:38:08 PM PST 24
Finished Feb 25 12:38:13 PM PST 24
Peak memory 211020 kb
Host smart-caf7fb8f-1843-4464-a3cb-d1c035b52846
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2075919568 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_max_throughput_chk.2075919568
Directory /workspace/23.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/23.rom_ctrl_smoke.2075260254
Short name T301
Test name
Test status
Simulation time 3953082193 ps
CPU time 35.88 seconds
Started Feb 25 12:37:56 PM PST 24
Finished Feb 25 12:38:32 PM PST 24
Peak memory 213448 kb
Host smart-bcaf2868-ab06-4d68-89c8-7c80a1beb2fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2075260254 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_smoke.2075260254
Directory /workspace/23.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/23.rom_ctrl_stress_all.3302390219
Short name T19
Test name
Test status
Simulation time 14494318451 ps
CPU time 53.13 seconds
Started Feb 25 12:38:11 PM PST 24
Finished Feb 25 12:39:04 PM PST 24
Peak memory 213024 kb
Host smart-1fa79343-80cb-4b63-9b45-acce039b91b1
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3302390219 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 23.rom_ctrl_stress_all.3302390219
Directory /workspace/23.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/24.rom_ctrl_alert_test.2999220135
Short name T291
Test name
Test status
Simulation time 6881671186 ps
CPU time 14.02 seconds
Started Feb 25 12:38:13 PM PST 24
Finished Feb 25 12:38:28 PM PST 24
Peak memory 211096 kb
Host smart-f8544226-bb17-44a7-bc2b-1250cd40aadb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2999220135 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_alert_test.2999220135
Directory /workspace/24.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/24.rom_ctrl_corrupt_sig_fatal_chk.454496886
Short name T222
Test name
Test status
Simulation time 23391344700 ps
CPU time 247.94 seconds
Started Feb 25 12:38:03 PM PST 24
Finished Feb 25 12:42:11 PM PST 24
Peak memory 228716 kb
Host smart-0b7b7065-ecce-4efb-a1ec-2201fd1d5ec2
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=454496886 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_c
orrupt_sig_fatal_chk.454496886
Directory /workspace/24.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/24.rom_ctrl_kmac_err_chk.1553654579
Short name T29
Test name
Test status
Simulation time 9585066868 ps
CPU time 24.24 seconds
Started Feb 25 12:38:04 PM PST 24
Finished Feb 25 12:38:29 PM PST 24
Peak memory 211832 kb
Host smart-02f63a49-5e86-4318-a18b-c55ba273ad60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1553654579 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_kmac_err_chk.1553654579
Directory /workspace/24.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/24.rom_ctrl_max_throughput_chk.3788700736
Short name T327
Test name
Test status
Simulation time 8305967068 ps
CPU time 16.93 seconds
Started Feb 25 12:37:55 PM PST 24
Finished Feb 25 12:38:12 PM PST 24
Peak memory 211176 kb
Host smart-0d200624-ebb7-4702-9f96-8ce57f8572d0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3788700736 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_max_throughput_chk.3788700736
Directory /workspace/24.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/24.rom_ctrl_smoke.705023399
Short name T304
Test name
Test status
Simulation time 182965809 ps
CPU time 10.35 seconds
Started Feb 25 12:37:54 PM PST 24
Finished Feb 25 12:38:05 PM PST 24
Peak memory 213572 kb
Host smart-3c532133-f013-4032-837b-f8dc64ada848
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=705023399 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_smoke.705023399
Directory /workspace/24.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/24.rom_ctrl_stress_all.511386791
Short name T107
Test name
Test status
Simulation time 38847573617 ps
CPU time 33.99 seconds
Started Feb 25 12:38:01 PM PST 24
Finished Feb 25 12:38:35 PM PST 24
Peak memory 216904 kb
Host smart-60a656b0-eb1e-4851-9c0a-9ef8783cca0f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=511386791 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 24.rom_ctrl_stress_all.511386791
Directory /workspace/24.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/25.rom_ctrl_alert_test.940055486
Short name T143
Test name
Test status
Simulation time 828508077 ps
CPU time 4.3 seconds
Started Feb 25 12:38:13 PM PST 24
Finished Feb 25 12:38:18 PM PST 24
Peak memory 211140 kb
Host smart-bb79f879-cfa8-4da2-80e2-893bc0efd55d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=940055486 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_alert_test.940055486
Directory /workspace/25.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/25.rom_ctrl_kmac_err_chk.140006025
Short name T280
Test name
Test status
Simulation time 2550733343 ps
CPU time 25.53 seconds
Started Feb 25 12:37:57 PM PST 24
Finished Feb 25 12:38:23 PM PST 24
Peak memory 211548 kb
Host smart-71a80c92-5dd6-4651-bd22-a5aad81f4bde
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=140006025 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_kmac_err_chk.140006025
Directory /workspace/25.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/25.rom_ctrl_max_throughput_chk.1622076592
Short name T171
Test name
Test status
Simulation time 1363231086 ps
CPU time 13.14 seconds
Started Feb 25 12:37:55 PM PST 24
Finished Feb 25 12:38:09 PM PST 24
Peak memory 211004 kb
Host smart-528b8b74-f48e-4bd3-b21e-461319ee2c91
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1622076592 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_max_throughput_chk.1622076592
Directory /workspace/25.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/25.rom_ctrl_smoke.494247654
Short name T193
Test name
Test status
Simulation time 1119037281 ps
CPU time 10.03 seconds
Started Feb 25 12:38:07 PM PST 24
Finished Feb 25 12:38:17 PM PST 24
Peak memory 213540 kb
Host smart-0c944a70-0006-44ed-b9e6-5d769ea250e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=494247654 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_smoke.494247654
Directory /workspace/25.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/25.rom_ctrl_stress_all.2482660787
Short name T173
Test name
Test status
Simulation time 6346419161 ps
CPU time 28.8 seconds
Started Feb 25 12:38:10 PM PST 24
Finished Feb 25 12:38:39 PM PST 24
Peak memory 214220 kb
Host smart-8e9a589a-116a-4a7d-b193-7c083ff31414
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2482660787 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 25.rom_ctrl_stress_all.2482660787
Directory /workspace/25.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/25.rom_ctrl_stress_all_with_rand_reset.3454871632
Short name T15
Test name
Test status
Simulation time 38353728792 ps
CPU time 351.73 seconds
Started Feb 25 12:37:56 PM PST 24
Finished Feb 25 12:43:48 PM PST 24
Peak memory 220044 kb
Host smart-204d0013-d584-407b-92b0-d204deb10710
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3454871632 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_stress_all_with_rand_reset.3454871632
Directory /workspace/25.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/26.rom_ctrl_alert_test.2164774265
Short name T139
Test name
Test status
Simulation time 1735302662 ps
CPU time 13.63 seconds
Started Feb 25 12:38:09 PM PST 24
Finished Feb 25 12:38:23 PM PST 24
Peak memory 210960 kb
Host smart-dda85dd3-1ca4-4148-abd6-34a7a18a9c06
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2164774265 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_alert_test.2164774265
Directory /workspace/26.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/26.rom_ctrl_corrupt_sig_fatal_chk.2807762388
Short name T59
Test name
Test status
Simulation time 9160642407 ps
CPU time 139.03 seconds
Started Feb 25 12:38:16 PM PST 24
Finished Feb 25 12:40:35 PM PST 24
Peak memory 212400 kb
Host smart-c16c8eed-ad14-4906-9d69-ff065ef48fe4
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2807762388 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_
corrupt_sig_fatal_chk.2807762388
Directory /workspace/26.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/26.rom_ctrl_kmac_err_chk.1343173760
Short name T265
Test name
Test status
Simulation time 1036719782 ps
CPU time 10.81 seconds
Started Feb 25 12:38:09 PM PST 24
Finished Feb 25 12:38:20 PM PST 24
Peak memory 211424 kb
Host smart-4f5f9f98-443f-479e-9563-eee683dfd201
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1343173760 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_kmac_err_chk.1343173760
Directory /workspace/26.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/26.rom_ctrl_max_throughput_chk.992057131
Short name T61
Test name
Test status
Simulation time 1336494481 ps
CPU time 12.09 seconds
Started Feb 25 12:38:03 PM PST 24
Finished Feb 25 12:38:15 PM PST 24
Peak memory 211124 kb
Host smart-253855da-92bc-4a1a-8876-b4f7de19b52a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=992057131 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_max_throughput_chk.992057131
Directory /workspace/26.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/26.rom_ctrl_smoke.3223054346
Short name T227
Test name
Test status
Simulation time 184119675 ps
CPU time 10.39 seconds
Started Feb 25 12:38:08 PM PST 24
Finished Feb 25 12:38:19 PM PST 24
Peak memory 213040 kb
Host smart-a3acde0c-ae6f-4f1b-b8bf-30e4ae26b505
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3223054346 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_smoke.3223054346
Directory /workspace/26.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/26.rom_ctrl_stress_all.1221117829
Short name T319
Test name
Test status
Simulation time 10877949342 ps
CPU time 28.9 seconds
Started Feb 25 12:38:11 PM PST 24
Finished Feb 25 12:38:40 PM PST 24
Peak memory 212692 kb
Host smart-766756ce-d4fc-4d98-a0b9-737da0000bef
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1221117829 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 26.rom_ctrl_stress_all.1221117829
Directory /workspace/26.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/26.rom_ctrl_stress_all_with_rand_reset.46852693
Short name T55
Test name
Test status
Simulation time 6919407670 ps
CPU time 667.21 seconds
Started Feb 25 12:37:56 PM PST 24
Finished Feb 25 12:49:04 PM PST 24
Peak memory 222864 kb
Host smart-e323b0fc-b306-4f9c-b321-e30bc5208de9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=46852693 -assert nopos
tproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_stress_all_with_rand_reset.46852693
Directory /workspace/26.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/27.rom_ctrl_alert_test.753828286
Short name T281
Test name
Test status
Simulation time 2192232948 ps
CPU time 12.45 seconds
Started Feb 25 12:38:08 PM PST 24
Finished Feb 25 12:38:21 PM PST 24
Peak memory 211124 kb
Host smart-f6b3e88b-3a0a-4255-a729-b6d550141115
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=753828286 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_alert_test.753828286
Directory /workspace/27.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/27.rom_ctrl_corrupt_sig_fatal_chk.3725792367
Short name T1
Test name
Test status
Simulation time 2203857625 ps
CPU time 120.65 seconds
Started Feb 25 12:38:03 PM PST 24
Finished Feb 25 12:40:04 PM PST 24
Peak memory 219460 kb
Host smart-b3513c57-0c83-44d6-8e80-94badb1a0521
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3725792367 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_
corrupt_sig_fatal_chk.3725792367
Directory /workspace/27.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/27.rom_ctrl_kmac_err_chk.1280933378
Short name T21
Test name
Test status
Simulation time 327125445 ps
CPU time 9.61 seconds
Started Feb 25 12:37:58 PM PST 24
Finished Feb 25 12:38:08 PM PST 24
Peak memory 211024 kb
Host smart-afaaa94d-eb8d-4c43-83d7-61a7cee46e96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1280933378 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_kmac_err_chk.1280933378
Directory /workspace/27.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/27.rom_ctrl_max_throughput_chk.4266630580
Short name T247
Test name
Test status
Simulation time 976015347 ps
CPU time 10.75 seconds
Started Feb 25 12:38:08 PM PST 24
Finished Feb 25 12:38:19 PM PST 24
Peak memory 211140 kb
Host smart-a4c744b7-1c07-4219-8771-b25b1925300b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4266630580 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_max_throughput_chk.4266630580
Directory /workspace/27.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/27.rom_ctrl_smoke.3987027488
Short name T81
Test name
Test status
Simulation time 16908807372 ps
CPU time 35.65 seconds
Started Feb 25 12:37:54 PM PST 24
Finished Feb 25 12:38:30 PM PST 24
Peak memory 219288 kb
Host smart-285524c2-d962-4690-9cea-86f525f55cad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3987027488 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_smoke.3987027488
Directory /workspace/27.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/27.rom_ctrl_stress_all.3144404750
Short name T10
Test name
Test status
Simulation time 7233438521 ps
CPU time 66.16 seconds
Started Feb 25 12:38:13 PM PST 24
Finished Feb 25 12:39:19 PM PST 24
Peak memory 219328 kb
Host smart-26fccec7-a4a5-4927-960d-bc028cbe691f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3144404750 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 27.rom_ctrl_stress_all.3144404750
Directory /workspace/27.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/28.rom_ctrl_alert_test.2268794405
Short name T146
Test name
Test status
Simulation time 1704736130 ps
CPU time 13.56 seconds
Started Feb 25 12:38:00 PM PST 24
Finished Feb 25 12:38:14 PM PST 24
Peak memory 211052 kb
Host smart-25227e9b-1d5f-4787-83df-39eb40337798
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2268794405 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_alert_test.2268794405
Directory /workspace/28.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/28.rom_ctrl_corrupt_sig_fatal_chk.3490135021
Short name T343
Test name
Test status
Simulation time 11076180872 ps
CPU time 75.24 seconds
Started Feb 25 12:38:15 PM PST 24
Finished Feb 25 12:39:30 PM PST 24
Peak memory 213460 kb
Host smart-9b230ae9-38f8-49ee-baee-90b4fa757a4d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3490135021 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_
corrupt_sig_fatal_chk.3490135021
Directory /workspace/28.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/28.rom_ctrl_kmac_err_chk.173760442
Short name T241
Test name
Test status
Simulation time 3782962385 ps
CPU time 32.25 seconds
Started Feb 25 12:38:02 PM PST 24
Finished Feb 25 12:38:36 PM PST 24
Peak memory 211596 kb
Host smart-99d8e374-9a36-4c2c-8564-f11ffeee3036
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=173760442 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_kmac_err_chk.173760442
Directory /workspace/28.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/28.rom_ctrl_max_throughput_chk.4213613795
Short name T361
Test name
Test status
Simulation time 946718228 ps
CPU time 8.35 seconds
Started Feb 25 12:38:00 PM PST 24
Finished Feb 25 12:38:09 PM PST 24
Peak memory 211052 kb
Host smart-519d7c9b-dabe-4cd5-8235-9a3f994a85d7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4213613795 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_max_throughput_chk.4213613795
Directory /workspace/28.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/28.rom_ctrl_smoke.1846071549
Short name T344
Test name
Test status
Simulation time 10608677628 ps
CPU time 28.66 seconds
Started Feb 25 12:38:16 PM PST 24
Finished Feb 25 12:38:45 PM PST 24
Peak memory 219348 kb
Host smart-48621dbb-c055-43c6-ae0d-de17f883e2d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1846071549 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_smoke.1846071549
Directory /workspace/28.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/28.rom_ctrl_stress_all.3559246041
Short name T238
Test name
Test status
Simulation time 1976678284 ps
CPU time 22.54 seconds
Started Feb 25 12:38:13 PM PST 24
Finished Feb 25 12:38:36 PM PST 24
Peak memory 213304 kb
Host smart-e037baa9-4c32-4542-b08a-8c019f6cdf32
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3559246041 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 28.rom_ctrl_stress_all.3559246041
Directory /workspace/28.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/29.rom_ctrl_alert_test.2372667851
Short name T180
Test name
Test status
Simulation time 2966740824 ps
CPU time 10.42 seconds
Started Feb 25 12:38:13 PM PST 24
Finished Feb 25 12:38:24 PM PST 24
Peak memory 210984 kb
Host smart-e864661f-08d6-4f67-891a-38c8a5f5d357
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2372667851 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_alert_test.2372667851
Directory /workspace/29.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/29.rom_ctrl_corrupt_sig_fatal_chk.2283012963
Short name T30
Test name
Test status
Simulation time 6332696281 ps
CPU time 94.26 seconds
Started Feb 25 12:38:08 PM PST 24
Finished Feb 25 12:39:43 PM PST 24
Peak memory 233040 kb
Host smart-d79bb8bf-7a84-45d2-9186-41633819211c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2283012963 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_
corrupt_sig_fatal_chk.2283012963
Directory /workspace/29.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/29.rom_ctrl_kmac_err_chk.1208515545
Short name T299
Test name
Test status
Simulation time 2126277579 ps
CPU time 21.87 seconds
Started Feb 25 12:38:27 PM PST 24
Finished Feb 25 12:38:50 PM PST 24
Peak memory 211544 kb
Host smart-af914b47-3974-4e40-8989-47db2e7cdbde
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1208515545 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_kmac_err_chk.1208515545
Directory /workspace/29.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/29.rom_ctrl_max_throughput_chk.2333844576
Short name T345
Test name
Test status
Simulation time 1472501304 ps
CPU time 13.25 seconds
Started Feb 25 12:38:00 PM PST 24
Finished Feb 25 12:38:14 PM PST 24
Peak memory 210996 kb
Host smart-a41d90f1-9041-4e4b-8c26-3c34a9e470ea
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2333844576 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_max_throughput_chk.2333844576
Directory /workspace/29.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/29.rom_ctrl_smoke.139579778
Short name T149
Test name
Test status
Simulation time 1074089066 ps
CPU time 11.86 seconds
Started Feb 25 12:37:59 PM PST 24
Finished Feb 25 12:38:11 PM PST 24
Peak memory 212968 kb
Host smart-391f57ca-91cd-4fe7-97b1-9536692f25a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=139579778 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_smoke.139579778
Directory /workspace/29.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/29.rom_ctrl_stress_all.2783776920
Short name T283
Test name
Test status
Simulation time 1155609040 ps
CPU time 15.24 seconds
Started Feb 25 12:38:03 PM PST 24
Finished Feb 25 12:38:19 PM PST 24
Peak memory 214532 kb
Host smart-124c9910-296f-4f85-871a-cbf0fdc80d19
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2783776920 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 29.rom_ctrl_stress_all.2783776920
Directory /workspace/29.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/3.rom_ctrl_alert_test.2177776705
Short name T246
Test name
Test status
Simulation time 2061778142 ps
CPU time 7.61 seconds
Started Feb 25 12:37:51 PM PST 24
Finished Feb 25 12:37:59 PM PST 24
Peak memory 211024 kb
Host smart-683a7104-023e-40b9-8fc2-3b9b00e8a91b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2177776705 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_alert_test.2177776705
Directory /workspace/3.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/3.rom_ctrl_corrupt_sig_fatal_chk.2617760792
Short name T223
Test name
Test status
Simulation time 1217825181 ps
CPU time 77.4 seconds
Started Feb 25 12:37:44 PM PST 24
Finished Feb 25 12:39:02 PM PST 24
Peak memory 225320 kb
Host smart-67035a5a-1cc3-4851-a110-dc939df8189d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2617760792 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_c
orrupt_sig_fatal_chk.2617760792
Directory /workspace/3.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/3.rom_ctrl_kmac_err_chk.2651816944
Short name T286
Test name
Test status
Simulation time 23807396159 ps
CPU time 26.65 seconds
Started Feb 25 12:37:38 PM PST 24
Finished Feb 25 12:38:06 PM PST 24
Peak memory 211952 kb
Host smart-32a25229-938d-4a52-813e-befd3f5b0eea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2651816944 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_kmac_err_chk.2651816944
Directory /workspace/3.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/3.rom_ctrl_max_throughput_chk.2713046652
Short name T204
Test name
Test status
Simulation time 3028190659 ps
CPU time 7.19 seconds
Started Feb 25 12:37:39 PM PST 24
Finished Feb 25 12:37:47 PM PST 24
Peak memory 211180 kb
Host smart-7a528421-2494-4994-bde6-940cfb4634d5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2713046652 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_max_throughput_chk.2713046652
Directory /workspace/3.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/3.rom_ctrl_sec_cm.4077483750
Short name T34
Test name
Test status
Simulation time 14952478203 ps
CPU time 65.43 seconds
Started Feb 25 12:37:57 PM PST 24
Finished Feb 25 12:39:03 PM PST 24
Peak memory 232484 kb
Host smart-cc44e76b-727d-45b3-b5e9-857aee189216
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4077483750 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_sec_cm.4077483750
Directory /workspace/3.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/3.rom_ctrl_smoke.2736758662
Short name T83
Test name
Test status
Simulation time 17410667345 ps
CPU time 45.79 seconds
Started Feb 25 12:37:45 PM PST 24
Finished Feb 25 12:38:32 PM PST 24
Peak memory 213876 kb
Host smart-825b6a6d-ebde-47c0-8f52-9a02c9e58016
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2736758662 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_smoke.2736758662
Directory /workspace/3.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/3.rom_ctrl_stress_all.3752304615
Short name T101
Test name
Test status
Simulation time 1104836639 ps
CPU time 11.06 seconds
Started Feb 25 12:37:45 PM PST 24
Finished Feb 25 12:37:57 PM PST 24
Peak memory 210996 kb
Host smart-0bd45888-f86d-42a9-8346-d776e77b47b7
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3752304615 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 3.rom_ctrl_stress_all.3752304615
Directory /workspace/3.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/30.rom_ctrl_alert_test.2872026746
Short name T69
Test name
Test status
Simulation time 602438753 ps
CPU time 8.04 seconds
Started Feb 25 12:38:17 PM PST 24
Finished Feb 25 12:38:25 PM PST 24
Peak memory 211228 kb
Host smart-cbf8db63-6a01-42fa-a17e-83f62b5566c7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2872026746 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_alert_test.2872026746
Directory /workspace/30.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/30.rom_ctrl_corrupt_sig_fatal_chk.847988004
Short name T50
Test name
Test status
Simulation time 35385151577 ps
CPU time 358.9 seconds
Started Feb 25 12:38:14 PM PST 24
Finished Feb 25 12:44:13 PM PST 24
Peak memory 230244 kb
Host smart-2823c3c1-8617-4f2f-a889-545d317b5799
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=847988004 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_c
orrupt_sig_fatal_chk.847988004
Directory /workspace/30.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/30.rom_ctrl_kmac_err_chk.3301560581
Short name T278
Test name
Test status
Simulation time 15950266032 ps
CPU time 32.62 seconds
Started Feb 25 12:37:58 PM PST 24
Finished Feb 25 12:38:31 PM PST 24
Peak memory 212560 kb
Host smart-a7dbb484-785d-441c-a3a8-a1c1c3c1c661
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3301560581 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_kmac_err_chk.3301560581
Directory /workspace/30.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/30.rom_ctrl_max_throughput_chk.4015617269
Short name T137
Test name
Test status
Simulation time 628469670 ps
CPU time 5.63 seconds
Started Feb 25 12:38:14 PM PST 24
Finished Feb 25 12:38:20 PM PST 24
Peak memory 211016 kb
Host smart-5ca0ab95-9a9f-45e3-bf23-8640865b43a3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4015617269 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_max_throughput_chk.4015617269
Directory /workspace/30.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/30.rom_ctrl_smoke.2667206337
Short name T306
Test name
Test status
Simulation time 3745966283 ps
CPU time 33.35 seconds
Started Feb 25 12:38:09 PM PST 24
Finished Feb 25 12:38:43 PM PST 24
Peak memory 213460 kb
Host smart-90479f1c-f877-4074-b174-ec38d5bd6210
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2667206337 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_smoke.2667206337
Directory /workspace/30.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/30.rom_ctrl_stress_all.3163279077
Short name T145
Test name
Test status
Simulation time 2323754372 ps
CPU time 29.29 seconds
Started Feb 25 12:38:00 PM PST 24
Finished Feb 25 12:38:29 PM PST 24
Peak memory 214912 kb
Host smart-263d3027-8670-4bac-a8f2-aa9e94a96ba3
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3163279077 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 30.rom_ctrl_stress_all.3163279077
Directory /workspace/30.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/31.rom_ctrl_alert_test.3609218067
Short name T68
Test name
Test status
Simulation time 2710368487 ps
CPU time 5.51 seconds
Started Feb 25 12:38:14 PM PST 24
Finished Feb 25 12:38:20 PM PST 24
Peak memory 211104 kb
Host smart-340d5362-cfc3-4a0b-81a6-1ab2059dfa2e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3609218067 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_alert_test.3609218067
Directory /workspace/31.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/31.rom_ctrl_corrupt_sig_fatal_chk.593974368
Short name T31
Test name
Test status
Simulation time 83193281439 ps
CPU time 409.11 seconds
Started Feb 25 12:37:57 PM PST 24
Finished Feb 25 12:44:47 PM PST 24
Peak memory 238836 kb
Host smart-43181365-050a-426b-ac8d-9c63affeddeb
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=593974368 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_c
orrupt_sig_fatal_chk.593974368
Directory /workspace/31.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/31.rom_ctrl_kmac_err_chk.3609924425
Short name T27
Test name
Test status
Simulation time 3396112057 ps
CPU time 28.36 seconds
Started Feb 25 12:38:13 PM PST 24
Finished Feb 25 12:38:42 PM PST 24
Peak memory 211668 kb
Host smart-fd078998-eca3-4e27-b216-8e31f758c0af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3609924425 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_kmac_err_chk.3609924425
Directory /workspace/31.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/31.rom_ctrl_max_throughput_chk.1182873593
Short name T135
Test name
Test status
Simulation time 13146134947 ps
CPU time 13.38 seconds
Started Feb 25 12:38:15 PM PST 24
Finished Feb 25 12:38:29 PM PST 24
Peak memory 211164 kb
Host smart-2c02a472-7807-484c-b3df-441b704b071e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1182873593 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_max_throughput_chk.1182873593
Directory /workspace/31.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/31.rom_ctrl_smoke.3526687005
Short name T129
Test name
Test status
Simulation time 9488999458 ps
CPU time 26.02 seconds
Started Feb 25 12:38:11 PM PST 24
Finished Feb 25 12:38:37 PM PST 24
Peak memory 219344 kb
Host smart-c232d1c7-f7c7-4794-89a5-985ee911a701
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3526687005 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_smoke.3526687005
Directory /workspace/31.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/31.rom_ctrl_stress_all.2556406157
Short name T276
Test name
Test status
Simulation time 19016966765 ps
CPU time 60.43 seconds
Started Feb 25 12:38:13 PM PST 24
Finished Feb 25 12:39:13 PM PST 24
Peak memory 216960 kb
Host smart-da8c1c36-c0f7-4ed6-839f-9911f50169f7
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2556406157 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 31.rom_ctrl_stress_all.2556406157
Directory /workspace/31.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/32.rom_ctrl_alert_test.2645223157
Short name T70
Test name
Test status
Simulation time 42347825902 ps
CPU time 16.62 seconds
Started Feb 25 12:38:08 PM PST 24
Finished Feb 25 12:38:25 PM PST 24
Peak memory 211108 kb
Host smart-4c8f73ab-ea73-4e7d-adb4-21100858d926
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2645223157 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_alert_test.2645223157
Directory /workspace/32.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/32.rom_ctrl_corrupt_sig_fatal_chk.3224982209
Short name T9
Test name
Test status
Simulation time 1750874316 ps
CPU time 104.55 seconds
Started Feb 25 12:38:00 PM PST 24
Finished Feb 25 12:39:45 PM PST 24
Peak memory 239804 kb
Host smart-642a273e-773c-444a-a1d9-eac4e400f041
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3224982209 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_
corrupt_sig_fatal_chk.3224982209
Directory /workspace/32.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/32.rom_ctrl_kmac_err_chk.1335606206
Short name T230
Test name
Test status
Simulation time 9911272395 ps
CPU time 24.59 seconds
Started Feb 25 12:37:56 PM PST 24
Finished Feb 25 12:38:22 PM PST 24
Peak memory 211856 kb
Host smart-588305f3-6c33-427f-8c94-94948c1e527e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1335606206 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_kmac_err_chk.1335606206
Directory /workspace/32.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/32.rom_ctrl_max_throughput_chk.758401414
Short name T342
Test name
Test status
Simulation time 1889335130 ps
CPU time 15.75 seconds
Started Feb 25 12:37:52 PM PST 24
Finished Feb 25 12:38:08 PM PST 24
Peak memory 211028 kb
Host smart-1dfe06a9-c48b-42ad-8105-2e347a567403
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=758401414 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_max_throughput_chk.758401414
Directory /workspace/32.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/32.rom_ctrl_smoke.1954182169
Short name T194
Test name
Test status
Simulation time 9094148980 ps
CPU time 20.81 seconds
Started Feb 25 12:38:00 PM PST 24
Finished Feb 25 12:38:21 PM PST 24
Peak memory 213728 kb
Host smart-1ab00103-845f-4fb0-b95d-0063187bbc21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1954182169 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_smoke.1954182169
Directory /workspace/32.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/32.rom_ctrl_stress_all.1029160984
Short name T245
Test name
Test status
Simulation time 2565595053 ps
CPU time 31.37 seconds
Started Feb 25 12:38:09 PM PST 24
Finished Feb 25 12:38:41 PM PST 24
Peak memory 213096 kb
Host smart-51039520-ab9f-46d5-bb5a-b17072d2bc6d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1029160984 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 32.rom_ctrl_stress_all.1029160984
Directory /workspace/32.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/33.rom_ctrl_alert_test.918371241
Short name T309
Test name
Test status
Simulation time 7055839380 ps
CPU time 12.55 seconds
Started Feb 25 12:38:11 PM PST 24
Finished Feb 25 12:38:24 PM PST 24
Peak memory 211220 kb
Host smart-49b05d3b-4912-47be-9962-908bd653d77f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=918371241 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_alert_test.918371241
Directory /workspace/33.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/33.rom_ctrl_kmac_err_chk.113128966
Short name T23
Test name
Test status
Simulation time 1045973039 ps
CPU time 16.09 seconds
Started Feb 25 12:37:55 PM PST 24
Finished Feb 25 12:38:12 PM PST 24
Peak memory 211416 kb
Host smart-62f17a71-e5e5-4323-acc5-51cb0dab9195
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=113128966 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_kmac_err_chk.113128966
Directory /workspace/33.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/33.rom_ctrl_max_throughput_chk.3340828409
Short name T244
Test name
Test status
Simulation time 1649688992 ps
CPU time 14.82 seconds
Started Feb 25 12:38:16 PM PST 24
Finished Feb 25 12:38:31 PM PST 24
Peak memory 211020 kb
Host smart-78ca7b35-d307-4dc6-a6b0-19f7fb0bc4e8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3340828409 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_max_throughput_chk.3340828409
Directory /workspace/33.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/33.rom_ctrl_smoke.231500646
Short name T128
Test name
Test status
Simulation time 8280874064 ps
CPU time 29.83 seconds
Started Feb 25 12:37:55 PM PST 24
Finished Feb 25 12:38:25 PM PST 24
Peak memory 219324 kb
Host smart-58a9b5cf-1fdb-49d9-824b-c88ae51de309
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=231500646 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_smoke.231500646
Directory /workspace/33.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/33.rom_ctrl_stress_all.2366492265
Short name T60
Test name
Test status
Simulation time 3329130117 ps
CPU time 10.11 seconds
Started Feb 25 12:37:58 PM PST 24
Finished Feb 25 12:38:08 PM PST 24
Peak memory 211012 kb
Host smart-b1e0d6bf-9390-4c06-a51a-451e183aa211
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2366492265 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 33.rom_ctrl_stress_all.2366492265
Directory /workspace/33.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/33.rom_ctrl_stress_all_with_rand_reset.3623659420
Short name T308
Test name
Test status
Simulation time 63605672328 ps
CPU time 3535.21 seconds
Started Feb 25 12:38:14 PM PST 24
Finished Feb 25 01:37:10 PM PST 24
Peak memory 228564 kb
Host smart-b2601078-7a18-4568-99d8-b72ca1de517a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3623659420 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_stress_all_with_rand_reset.3623659420
Directory /workspace/33.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.rom_ctrl_alert_test.433515517
Short name T37
Test name
Test status
Simulation time 6015463907 ps
CPU time 9.87 seconds
Started Feb 25 12:38:10 PM PST 24
Finished Feb 25 12:38:20 PM PST 24
Peak memory 211172 kb
Host smart-fcdd8306-e989-4b92-b41e-715eba60307b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=433515517 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_alert_test.433515517
Directory /workspace/34.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/34.rom_ctrl_corrupt_sig_fatal_chk.1593566398
Short name T97
Test name
Test status
Simulation time 488135742385 ps
CPU time 366.54 seconds
Started Feb 25 12:38:06 PM PST 24
Finished Feb 25 12:44:12 PM PST 24
Peak memory 228604 kb
Host smart-68d97b15-0981-49c1-a210-c7f522cdb1a1
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1593566398 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_
corrupt_sig_fatal_chk.1593566398
Directory /workspace/34.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/34.rom_ctrl_kmac_err_chk.3864318251
Short name T320
Test name
Test status
Simulation time 340626543 ps
CPU time 9.54 seconds
Started Feb 25 12:38:14 PM PST 24
Finished Feb 25 12:38:24 PM PST 24
Peak memory 211560 kb
Host smart-b8091ce3-2191-458f-a35f-0052501a822a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3864318251 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_kmac_err_chk.3864318251
Directory /workspace/34.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/34.rom_ctrl_max_throughput_chk.2855758995
Short name T58
Test name
Test status
Simulation time 368212830 ps
CPU time 5.43 seconds
Started Feb 25 12:38:06 PM PST 24
Finished Feb 25 12:38:12 PM PST 24
Peak memory 211016 kb
Host smart-2b844ca6-2853-425f-a2a0-36de449a4d91
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2855758995 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_max_throughput_chk.2855758995
Directory /workspace/34.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/34.rom_ctrl_smoke.536827212
Short name T257
Test name
Test status
Simulation time 715359629 ps
CPU time 10.4 seconds
Started Feb 25 12:38:14 PM PST 24
Finished Feb 25 12:38:25 PM PST 24
Peak memory 212748 kb
Host smart-8f1cd76d-bdb4-4ad1-a684-e37e548f0630
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=536827212 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_smoke.536827212
Directory /workspace/34.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/34.rom_ctrl_stress_all.3419580073
Short name T130
Test name
Test status
Simulation time 7116349045 ps
CPU time 41.3 seconds
Started Feb 25 12:38:12 PM PST 24
Finished Feb 25 12:38:53 PM PST 24
Peak memory 219336 kb
Host smart-bc14ce28-d99f-472f-869d-0e78588ad14c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3419580073 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 34.rom_ctrl_stress_all.3419580073
Directory /workspace/34.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/35.rom_ctrl_alert_test.556236105
Short name T151
Test name
Test status
Simulation time 3772357820 ps
CPU time 16.17 seconds
Started Feb 25 12:38:08 PM PST 24
Finished Feb 25 12:38:25 PM PST 24
Peak memory 211068 kb
Host smart-995811d0-1d22-479f-b68d-dd453130ed55
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=556236105 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_alert_test.556236105
Directory /workspace/35.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/35.rom_ctrl_corrupt_sig_fatal_chk.3263037004
Short name T51
Test name
Test status
Simulation time 36321293999 ps
CPU time 332.34 seconds
Started Feb 25 12:38:04 PM PST 24
Finished Feb 25 12:43:36 PM PST 24
Peak memory 237052 kb
Host smart-72975543-09e0-4f33-94b1-a008eadb574c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3263037004 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_
corrupt_sig_fatal_chk.3263037004
Directory /workspace/35.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/35.rom_ctrl_kmac_err_chk.525452397
Short name T323
Test name
Test status
Simulation time 14793266625 ps
CPU time 30.61 seconds
Started Feb 25 12:37:59 PM PST 24
Finished Feb 25 12:38:29 PM PST 24
Peak memory 211804 kb
Host smart-13ebc566-ae9d-4923-89c2-804bfb70542c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=525452397 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_kmac_err_chk.525452397
Directory /workspace/35.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/35.rom_ctrl_max_throughput_chk.3870598017
Short name T182
Test name
Test status
Simulation time 189511702 ps
CPU time 5.56 seconds
Started Feb 25 12:37:58 PM PST 24
Finished Feb 25 12:38:04 PM PST 24
Peak memory 211024 kb
Host smart-385d2e06-6369-4030-af96-52581bd9a58a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3870598017 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_max_throughput_chk.3870598017
Directory /workspace/35.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/35.rom_ctrl_smoke.3091915180
Short name T40
Test name
Test status
Simulation time 197706019 ps
CPU time 10.2 seconds
Started Feb 25 12:37:58 PM PST 24
Finished Feb 25 12:38:09 PM PST 24
Peak memory 213116 kb
Host smart-363a7172-5ad6-4834-bdc1-9ef57941fd86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3091915180 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_smoke.3091915180
Directory /workspace/35.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/35.rom_ctrl_stress_all.1999131517
Short name T234
Test name
Test status
Simulation time 744634745 ps
CPU time 14.89 seconds
Started Feb 25 12:38:00 PM PST 24
Finished Feb 25 12:38:15 PM PST 24
Peak memory 211972 kb
Host smart-5156f3d8-47a7-4cb4-9a66-ae34ed26d3f7
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1999131517 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 35.rom_ctrl_stress_all.1999131517
Directory /workspace/35.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/36.rom_ctrl_alert_test.3465369287
Short name T184
Test name
Test status
Simulation time 6273293175 ps
CPU time 14.75 seconds
Started Feb 25 12:38:11 PM PST 24
Finished Feb 25 12:38:26 PM PST 24
Peak memory 211176 kb
Host smart-343478e6-752f-42b4-b085-eb4445637f64
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3465369287 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_alert_test.3465369287
Directory /workspace/36.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/36.rom_ctrl_corrupt_sig_fatal_chk.2243325252
Short name T147
Test name
Test status
Simulation time 7760929305 ps
CPU time 121.84 seconds
Started Feb 25 12:38:31 PM PST 24
Finished Feb 25 12:40:34 PM PST 24
Peak memory 239432 kb
Host smart-3a98b8cb-fee3-4d2d-a17e-b769dc787e58
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2243325252 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_
corrupt_sig_fatal_chk.2243325252
Directory /workspace/36.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/36.rom_ctrl_kmac_err_chk.1420443340
Short name T225
Test name
Test status
Simulation time 2069540731 ps
CPU time 9.45 seconds
Started Feb 25 12:38:17 PM PST 24
Finished Feb 25 12:38:26 PM PST 24
Peak memory 211532 kb
Host smart-ee3d9479-2d64-4a8d-84cc-7a2161ad8769
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1420443340 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_kmac_err_chk.1420443340
Directory /workspace/36.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/36.rom_ctrl_max_throughput_chk.1601144035
Short name T141
Test name
Test status
Simulation time 7504141893 ps
CPU time 7.92 seconds
Started Feb 25 12:38:20 PM PST 24
Finished Feb 25 12:38:28 PM PST 24
Peak memory 211216 kb
Host smart-5b1b16d5-4d4d-43a3-85c9-fbec28df6f4d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1601144035 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_max_throughput_chk.1601144035
Directory /workspace/36.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/36.rom_ctrl_smoke.28355345
Short name T239
Test name
Test status
Simulation time 14491391110 ps
CPU time 30.22 seconds
Started Feb 25 12:38:11 PM PST 24
Finished Feb 25 12:38:41 PM PST 24
Peak memory 213940 kb
Host smart-9b62d4d9-f851-4dda-8123-3fa5a0c55911
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=28355345 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_smoke.28355345
Directory /workspace/36.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/36.rom_ctrl_stress_all.30423988
Short name T331
Test name
Test status
Simulation time 961032292 ps
CPU time 7.32 seconds
Started Feb 25 12:38:17 PM PST 24
Finished Feb 25 12:38:25 PM PST 24
Peak memory 211052 kb
Host smart-96742553-96aa-46d2-9110-c54255133646
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30423988 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +U
VM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n
ame 36.rom_ctrl_stress_all.30423988
Directory /workspace/36.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/37.rom_ctrl_alert_test.2361528386
Short name T176
Test name
Test status
Simulation time 347440147 ps
CPU time 4.25 seconds
Started Feb 25 12:38:28 PM PST 24
Finished Feb 25 12:38:34 PM PST 24
Peak memory 211012 kb
Host smart-d4c07581-1b53-4d0a-ac3f-c85358372910
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2361528386 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_alert_test.2361528386
Directory /workspace/37.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/37.rom_ctrl_corrupt_sig_fatal_chk.716239483
Short name T198
Test name
Test status
Simulation time 36980005704 ps
CPU time 132.97 seconds
Started Feb 25 12:38:11 PM PST 24
Finished Feb 25 12:40:24 PM PST 24
Peak memory 236656 kb
Host smart-0990a197-43ff-42c1-9c57-be2b0f9cb73f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=716239483 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_c
orrupt_sig_fatal_chk.716239483
Directory /workspace/37.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/37.rom_ctrl_kmac_err_chk.313842863
Short name T338
Test name
Test status
Simulation time 11126182179 ps
CPU time 19.43 seconds
Started Feb 25 12:38:07 PM PST 24
Finished Feb 25 12:38:27 PM PST 24
Peak memory 212112 kb
Host smart-83340f46-03a2-4bc4-8887-b8b79008f873
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=313842863 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_kmac_err_chk.313842863
Directory /workspace/37.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/37.rom_ctrl_max_throughput_chk.3090985642
Short name T348
Test name
Test status
Simulation time 5770296896 ps
CPU time 11.97 seconds
Started Feb 25 12:38:20 PM PST 24
Finished Feb 25 12:38:32 PM PST 24
Peak memory 211156 kb
Host smart-0202db3d-2047-4c20-a1b8-5cbb0db82333
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3090985642 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_max_throughput_chk.3090985642
Directory /workspace/37.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/37.rom_ctrl_smoke.1816812584
Short name T210
Test name
Test status
Simulation time 12098021966 ps
CPU time 27.71 seconds
Started Feb 25 12:38:15 PM PST 24
Finished Feb 25 12:38:43 PM PST 24
Peak memory 214112 kb
Host smart-900ea0e0-5303-4a94-baa7-e960aec512c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1816812584 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_smoke.1816812584
Directory /workspace/37.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/37.rom_ctrl_stress_all.1492703945
Short name T242
Test name
Test status
Simulation time 3908427371 ps
CPU time 48.78 seconds
Started Feb 25 12:38:08 PM PST 24
Finished Feb 25 12:38:57 PM PST 24
Peak memory 216360 kb
Host smart-af125ef2-2c9b-4a11-9d12-b6d5d77854b9
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1492703945 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 37.rom_ctrl_stress_all.1492703945
Directory /workspace/37.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/38.rom_ctrl_alert_test.2873472141
Short name T207
Test name
Test status
Simulation time 2133415777 ps
CPU time 16.42 seconds
Started Feb 25 12:38:14 PM PST 24
Finished Feb 25 12:38:31 PM PST 24
Peak memory 211108 kb
Host smart-2e77d5af-be00-46b5-be09-2709a5cb49b2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2873472141 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_alert_test.2873472141
Directory /workspace/38.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/38.rom_ctrl_corrupt_sig_fatal_chk.2351762445
Short name T333
Test name
Test status
Simulation time 2213047279 ps
CPU time 133.21 seconds
Started Feb 25 12:38:08 PM PST 24
Finished Feb 25 12:40:27 PM PST 24
Peak memory 219448 kb
Host smart-dd4ab2f6-3c48-4b08-a36a-e16caa9dbce4
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2351762445 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_
corrupt_sig_fatal_chk.2351762445
Directory /workspace/38.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/38.rom_ctrl_kmac_err_chk.488234772
Short name T271
Test name
Test status
Simulation time 15380806107 ps
CPU time 32.69 seconds
Started Feb 25 12:38:11 PM PST 24
Finished Feb 25 12:38:44 PM PST 24
Peak memory 211768 kb
Host smart-79b66ec9-a9b2-4452-b145-243e2416d302
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=488234772 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_kmac_err_chk.488234772
Directory /workspace/38.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/38.rom_ctrl_max_throughput_chk.2991673961
Short name T188
Test name
Test status
Simulation time 94571897 ps
CPU time 5.47 seconds
Started Feb 25 12:38:33 PM PST 24
Finished Feb 25 12:38:40 PM PST 24
Peak memory 210912 kb
Host smart-74b55f0a-b6e2-46cd-87d8-176e59ef8ac7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2991673961 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_max_throughput_chk.2991673961
Directory /workspace/38.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/38.rom_ctrl_smoke.458903340
Short name T215
Test name
Test status
Simulation time 7428344668 ps
CPU time 30.62 seconds
Started Feb 25 12:38:13 PM PST 24
Finished Feb 25 12:38:43 PM PST 24
Peak memory 213540 kb
Host smart-7de79e1f-a071-484e-9ba6-4a02e94838bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=458903340 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_smoke.458903340
Directory /workspace/38.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/38.rom_ctrl_stress_all.3326769331
Short name T25
Test name
Test status
Simulation time 19027767722 ps
CPU time 50.14 seconds
Started Feb 25 12:38:14 PM PST 24
Finished Feb 25 12:39:04 PM PST 24
Peak memory 219292 kb
Host smart-60e28421-241b-4228-af84-4a341ee04eff
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3326769331 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 38.rom_ctrl_stress_all.3326769331
Directory /workspace/38.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/39.rom_ctrl_alert_test.2976555427
Short name T36
Test name
Test status
Simulation time 3169347931 ps
CPU time 13.63 seconds
Started Feb 25 12:38:16 PM PST 24
Finished Feb 25 12:38:30 PM PST 24
Peak memory 211080 kb
Host smart-3fabb93b-91e0-463b-88f1-f057d72376c0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2976555427 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_alert_test.2976555427
Directory /workspace/39.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/39.rom_ctrl_corrupt_sig_fatal_chk.2328689255
Short name T255
Test name
Test status
Simulation time 42968896764 ps
CPU time 399.4 seconds
Started Feb 25 12:38:12 PM PST 24
Finished Feb 25 12:44:51 PM PST 24
Peak memory 233736 kb
Host smart-1f54adcd-ecb6-46d7-8e11-176a0d430135
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2328689255 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_
corrupt_sig_fatal_chk.2328689255
Directory /workspace/39.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/39.rom_ctrl_kmac_err_chk.2289817222
Short name T253
Test name
Test status
Simulation time 3878394958 ps
CPU time 22.17 seconds
Started Feb 25 12:38:16 PM PST 24
Finished Feb 25 12:38:38 PM PST 24
Peak memory 211544 kb
Host smart-9a9d44cd-5874-48b5-b633-6ab6289b565d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2289817222 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_kmac_err_chk.2289817222
Directory /workspace/39.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/39.rom_ctrl_max_throughput_chk.2514244270
Short name T132
Test name
Test status
Simulation time 3624609274 ps
CPU time 11.14 seconds
Started Feb 25 12:38:48 PM PST 24
Finished Feb 25 12:39:00 PM PST 24
Peak memory 211080 kb
Host smart-4c9fc680-d1c6-4cfa-86ab-aa52c4b87314
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2514244270 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_max_throughput_chk.2514244270
Directory /workspace/39.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/39.rom_ctrl_smoke.2144428685
Short name T289
Test name
Test status
Simulation time 15039992984 ps
CPU time 30.24 seconds
Started Feb 25 12:38:17 PM PST 24
Finished Feb 25 12:38:47 PM PST 24
Peak memory 213652 kb
Host smart-e310346a-719c-490b-962f-7e21bc92b83b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2144428685 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_smoke.2144428685
Directory /workspace/39.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/39.rom_ctrl_stress_all.821609729
Short name T272
Test name
Test status
Simulation time 4354235858 ps
CPU time 33.78 seconds
Started Feb 25 12:38:12 PM PST 24
Finished Feb 25 12:38:46 PM PST 24
Peak memory 214068 kb
Host smart-2af8d01e-f927-4e02-a9f3-7faacf343a5c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=821609729 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 39.rom_ctrl_stress_all.821609729
Directory /workspace/39.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/39.rom_ctrl_stress_all_with_rand_reset.3774532352
Short name T54
Test name
Test status
Simulation time 21756263784 ps
CPU time 6655.76 seconds
Started Feb 25 12:38:13 PM PST 24
Finished Feb 25 02:29:10 PM PST 24
Peak memory 231428 kb
Host smart-e56e17d4-7eeb-4ed4-9865-b2c0e8ea434f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3774532352 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_stress_all_with_rand_reset.3774532352
Directory /workspace/39.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.rom_ctrl_alert_test.2726021247
Short name T275
Test name
Test status
Simulation time 4315697440 ps
CPU time 10.56 seconds
Started Feb 25 12:37:55 PM PST 24
Finished Feb 25 12:38:05 PM PST 24
Peak memory 211144 kb
Host smart-e16216d1-e4a7-46f3-8aee-d9a754b5f84b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2726021247 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_alert_test.2726021247
Directory /workspace/4.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/4.rom_ctrl_corrupt_sig_fatal_chk.2451907580
Short name T294
Test name
Test status
Simulation time 2645088741 ps
CPU time 88.8 seconds
Started Feb 25 12:37:38 PM PST 24
Finished Feb 25 12:39:08 PM PST 24
Peak memory 239608 kb
Host smart-85ec917e-0df2-488f-add4-cfb56cb57e6b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2451907580 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_c
orrupt_sig_fatal_chk.2451907580
Directory /workspace/4.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/4.rom_ctrl_kmac_err_chk.3667402238
Short name T259
Test name
Test status
Simulation time 695516902 ps
CPU time 13.85 seconds
Started Feb 25 12:37:49 PM PST 24
Finished Feb 25 12:38:03 PM PST 24
Peak memory 211644 kb
Host smart-54fd29d5-6622-447d-931d-cba71c88a743
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3667402238 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_kmac_err_chk.3667402238
Directory /workspace/4.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/4.rom_ctrl_max_throughput_chk.430604600
Short name T20
Test name
Test status
Simulation time 1130123914 ps
CPU time 12.28 seconds
Started Feb 25 12:37:53 PM PST 24
Finished Feb 25 12:38:05 PM PST 24
Peak memory 211036 kb
Host smart-642ec75a-bdd9-451e-acb0-50f5ddeb35e0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=430604600 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_max_throughput_chk.430604600
Directory /workspace/4.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/4.rom_ctrl_sec_cm.3018902300
Short name T38
Test name
Test status
Simulation time 5117184364 ps
CPU time 126.37 seconds
Started Feb 25 12:37:53 PM PST 24
Finished Feb 25 12:40:00 PM PST 24
Peak memory 239380 kb
Host smart-b5b2b056-9f6b-410f-ac81-9a7b5e311226
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3018902300 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_sec_cm.3018902300
Directory /workspace/4.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/4.rom_ctrl_smoke.3734211283
Short name T6
Test name
Test status
Simulation time 2458060134 ps
CPU time 27.58 seconds
Started Feb 25 12:37:40 PM PST 24
Finished Feb 25 12:38:08 PM PST 24
Peak memory 213004 kb
Host smart-684264fd-b7c3-45e6-b020-bb72cacab6a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3734211283 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_smoke.3734211283
Directory /workspace/4.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/4.rom_ctrl_stress_all.988045053
Short name T341
Test name
Test status
Simulation time 436796856 ps
CPU time 12.48 seconds
Started Feb 25 12:37:58 PM PST 24
Finished Feb 25 12:38:10 PM PST 24
Peak memory 211716 kb
Host smart-4ac5a79c-766c-4a40-a1a5-12a60e7fca57
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=988045053 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 4.rom_ctrl_stress_all.988045053
Directory /workspace/4.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/40.rom_ctrl_alert_test.2064540455
Short name T321
Test name
Test status
Simulation time 1992266450 ps
CPU time 10.59 seconds
Started Feb 25 12:38:34 PM PST 24
Finished Feb 25 12:38:45 PM PST 24
Peak memory 211012 kb
Host smart-24d263b8-485b-411f-9fe2-331349254f3b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2064540455 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_alert_test.2064540455
Directory /workspace/40.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/40.rom_ctrl_corrupt_sig_fatal_chk.3180080090
Short name T314
Test name
Test status
Simulation time 20488803666 ps
CPU time 132.15 seconds
Started Feb 25 12:38:13 PM PST 24
Finished Feb 25 12:40:25 PM PST 24
Peak memory 234536 kb
Host smart-3559a4d9-b70b-4a37-9e31-8c30bf80b390
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3180080090 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_
corrupt_sig_fatal_chk.3180080090
Directory /workspace/40.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/40.rom_ctrl_kmac_err_chk.3052044780
Short name T211
Test name
Test status
Simulation time 3761402864 ps
CPU time 15.52 seconds
Started Feb 25 12:38:08 PM PST 24
Finished Feb 25 12:38:23 PM PST 24
Peak memory 211612 kb
Host smart-b19aafbe-8eda-4642-8798-77ecc3aa17d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3052044780 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_kmac_err_chk.3052044780
Directory /workspace/40.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/40.rom_ctrl_max_throughput_chk.1659124194
Short name T95
Test name
Test status
Simulation time 1573094287 ps
CPU time 14.61 seconds
Started Feb 25 12:38:11 PM PST 24
Finished Feb 25 12:38:26 PM PST 24
Peak memory 211052 kb
Host smart-e49341ab-fb94-4f6a-bd0a-01c5a0c8ffbb
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1659124194 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_max_throughput_chk.1659124194
Directory /workspace/40.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/40.rom_ctrl_smoke.2664595812
Short name T274
Test name
Test status
Simulation time 3138680066 ps
CPU time 32.41 seconds
Started Feb 25 12:38:11 PM PST 24
Finished Feb 25 12:38:43 PM PST 24
Peak memory 212316 kb
Host smart-551bc698-55c3-4620-a3c1-7b4046f27689
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2664595812 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_smoke.2664595812
Directory /workspace/40.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/40.rom_ctrl_stress_all.3821910635
Short name T131
Test name
Test status
Simulation time 8255099830 ps
CPU time 72.88 seconds
Started Feb 25 12:38:33 PM PST 24
Finished Feb 25 12:39:48 PM PST 24
Peak memory 217124 kb
Host smart-2974a441-40c5-46be-9171-8764f4c3b5f5
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3821910635 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 40.rom_ctrl_stress_all.3821910635
Directory /workspace/40.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/41.rom_ctrl_alert_test.1328353716
Short name T243
Test name
Test status
Simulation time 1874341929 ps
CPU time 7.2 seconds
Started Feb 25 12:38:11 PM PST 24
Finished Feb 25 12:38:18 PM PST 24
Peak memory 211004 kb
Host smart-c0e63ca8-880a-4265-96fc-6b6f2387fc42
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1328353716 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_alert_test.1328353716
Directory /workspace/41.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/41.rom_ctrl_corrupt_sig_fatal_chk.3588455295
Short name T155
Test name
Test status
Simulation time 1840374062 ps
CPU time 105.23 seconds
Started Feb 25 12:38:31 PM PST 24
Finished Feb 25 12:40:19 PM PST 24
Peak memory 212452 kb
Host smart-1cf4de4a-7cba-4ce5-ad61-768bd0e03cbc
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3588455295 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_
corrupt_sig_fatal_chk.3588455295
Directory /workspace/41.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/41.rom_ctrl_kmac_err_chk.3244402045
Short name T303
Test name
Test status
Simulation time 5540853838 ps
CPU time 18.28 seconds
Started Feb 25 12:38:16 PM PST 24
Finished Feb 25 12:38:35 PM PST 24
Peak memory 211808 kb
Host smart-2e1367fa-2338-4478-a576-a98a4cdd7d85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3244402045 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_kmac_err_chk.3244402045
Directory /workspace/41.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/41.rom_ctrl_max_throughput_chk.1967088837
Short name T186
Test name
Test status
Simulation time 1956224441 ps
CPU time 11.22 seconds
Started Feb 25 12:38:18 PM PST 24
Finished Feb 25 12:38:29 PM PST 24
Peak memory 211052 kb
Host smart-a6f4d851-9e40-41d1-bb64-7214f696ea03
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1967088837 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_max_throughput_chk.1967088837
Directory /workspace/41.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/41.rom_ctrl_smoke.3374146114
Short name T80
Test name
Test status
Simulation time 4517017707 ps
CPU time 29.14 seconds
Started Feb 25 12:38:15 PM PST 24
Finished Feb 25 12:38:45 PM PST 24
Peak memory 213184 kb
Host smart-95513e81-fb09-4879-af97-3fa4fbe03d6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3374146114 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_smoke.3374146114
Directory /workspace/41.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/41.rom_ctrl_stress_all.535422584
Short name T165
Test name
Test status
Simulation time 5267834954 ps
CPU time 28.84 seconds
Started Feb 25 12:38:10 PM PST 24
Finished Feb 25 12:38:39 PM PST 24
Peak memory 219404 kb
Host smart-64bcd8f0-d690-4a18-b0f3-d5674d84706a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=535422584 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 41.rom_ctrl_stress_all.535422584
Directory /workspace/41.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/42.rom_ctrl_alert_test.2178625322
Short name T279
Test name
Test status
Simulation time 416214998 ps
CPU time 4.32 seconds
Started Feb 25 12:38:25 PM PST 24
Finished Feb 25 12:38:29 PM PST 24
Peak memory 211112 kb
Host smart-dfda4de9-37b2-4f32-a1a5-bb32d7aba63e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2178625322 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_alert_test.2178625322
Directory /workspace/42.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/42.rom_ctrl_corrupt_sig_fatal_chk.2189859107
Short name T156
Test name
Test status
Simulation time 34150813895 ps
CPU time 94.55 seconds
Started Feb 25 12:38:21 PM PST 24
Finished Feb 25 12:39:56 PM PST 24
Peak memory 235740 kb
Host smart-0e330e5a-c498-4ec6-b495-6414f795ccce
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2189859107 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_
corrupt_sig_fatal_chk.2189859107
Directory /workspace/42.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/42.rom_ctrl_kmac_err_chk.2777644149
Short name T228
Test name
Test status
Simulation time 9025538617 ps
CPU time 32.15 seconds
Started Feb 25 12:38:16 PM PST 24
Finished Feb 25 12:38:48 PM PST 24
Peak memory 212028 kb
Host smart-81239727-d2c1-4c1a-b2b4-5131ce2726e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2777644149 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_kmac_err_chk.2777644149
Directory /workspace/42.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/42.rom_ctrl_max_throughput_chk.2795480077
Short name T295
Test name
Test status
Simulation time 1554183338 ps
CPU time 10.33 seconds
Started Feb 25 12:38:06 PM PST 24
Finished Feb 25 12:38:16 PM PST 24
Peak memory 211060 kb
Host smart-64c72227-400f-42cf-8eb2-cf1016af9103
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2795480077 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_max_throughput_chk.2795480077
Directory /workspace/42.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/42.rom_ctrl_smoke.2824332882
Short name T326
Test name
Test status
Simulation time 2779276641 ps
CPU time 25.64 seconds
Started Feb 25 12:38:11 PM PST 24
Finished Feb 25 12:38:37 PM PST 24
Peak memory 212740 kb
Host smart-2719143e-fb4d-4f4f-a504-ca77081b8ae4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2824332882 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_smoke.2824332882
Directory /workspace/42.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/42.rom_ctrl_stress_all.2204119682
Short name T284
Test name
Test status
Simulation time 3424371002 ps
CPU time 16.31 seconds
Started Feb 25 12:38:24 PM PST 24
Finished Feb 25 12:38:40 PM PST 24
Peak memory 219240 kb
Host smart-1a6d4393-5c45-427e-be2e-ca1acaa9657d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2204119682 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 42.rom_ctrl_stress_all.2204119682
Directory /workspace/42.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/42.rom_ctrl_stress_all_with_rand_reset.510912979
Short name T310
Test name
Test status
Simulation time 48211505850 ps
CPU time 835.25 seconds
Started Feb 25 12:38:38 PM PST 24
Finished Feb 25 12:52:34 PM PST 24
Peak memory 235880 kb
Host smart-337982e5-7567-42f2-8303-3626fd0b39db
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=510912979 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_stress_all_with_rand_reset.510912979
Directory /workspace/42.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.rom_ctrl_alert_test.1014177668
Short name T293
Test name
Test status
Simulation time 9547644876 ps
CPU time 14.32 seconds
Started Feb 25 12:38:39 PM PST 24
Finished Feb 25 12:38:54 PM PST 24
Peak memory 211232 kb
Host smart-42e0d6ea-f844-466a-bb40-faae17975c0c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1014177668 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_alert_test.1014177668
Directory /workspace/43.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/43.rom_ctrl_corrupt_sig_fatal_chk.2292772524
Short name T195
Test name
Test status
Simulation time 85775099290 ps
CPU time 183.17 seconds
Started Feb 25 12:38:20 PM PST 24
Finished Feb 25 12:41:24 PM PST 24
Peak memory 228524 kb
Host smart-a57fd61d-e7e5-4243-8933-d7b3cd895f73
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2292772524 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_
corrupt_sig_fatal_chk.2292772524
Directory /workspace/43.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/43.rom_ctrl_kmac_err_chk.3031727893
Short name T161
Test name
Test status
Simulation time 11591765134 ps
CPU time 24.83 seconds
Started Feb 25 12:38:28 PM PST 24
Finished Feb 25 12:38:53 PM PST 24
Peak memory 211928 kb
Host smart-50a30be7-eac7-492e-8438-927a548aa63d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3031727893 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_kmac_err_chk.3031727893
Directory /workspace/43.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/43.rom_ctrl_max_throughput_chk.3191667485
Short name T133
Test name
Test status
Simulation time 6066554554 ps
CPU time 13.61 seconds
Started Feb 25 12:38:30 PM PST 24
Finished Feb 25 12:38:46 PM PST 24
Peak memory 211148 kb
Host smart-87c97bc3-c265-465e-a6d5-2bd05393842e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3191667485 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_max_throughput_chk.3191667485
Directory /workspace/43.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/43.rom_ctrl_smoke.1956171524
Short name T262
Test name
Test status
Simulation time 2743060765 ps
CPU time 28.07 seconds
Started Feb 25 12:38:14 PM PST 24
Finished Feb 25 12:38:42 PM PST 24
Peak memory 213328 kb
Host smart-59c461b7-49d2-4fe2-a7fa-d1fa1c6d3da3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1956171524 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_smoke.1956171524
Directory /workspace/43.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/43.rom_ctrl_stress_all.969667984
Short name T177
Test name
Test status
Simulation time 33809318871 ps
CPU time 95.23 seconds
Started Feb 25 12:38:00 PM PST 24
Finished Feb 25 12:39:36 PM PST 24
Peak memory 217784 kb
Host smart-e4f247ed-d0ce-4798-9746-2633de63000b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=969667984 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 43.rom_ctrl_stress_all.969667984
Directory /workspace/43.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/44.rom_ctrl_alert_test.3786578026
Short name T189
Test name
Test status
Simulation time 6178173813 ps
CPU time 13.41 seconds
Started Feb 25 12:38:11 PM PST 24
Finished Feb 25 12:38:25 PM PST 24
Peak memory 211036 kb
Host smart-3634cd60-eebc-4122-9d44-8bd002a4aa75
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3786578026 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_alert_test.3786578026
Directory /workspace/44.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/44.rom_ctrl_corrupt_sig_fatal_chk.1327326461
Short name T270
Test name
Test status
Simulation time 75449374586 ps
CPU time 159.54 seconds
Started Feb 25 12:38:22 PM PST 24
Finished Feb 25 12:41:01 PM PST 24
Peak memory 228520 kb
Host smart-de19bf09-0af0-4ab2-b2dc-2ec990c4b5af
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1327326461 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_
corrupt_sig_fatal_chk.1327326461
Directory /workspace/44.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/44.rom_ctrl_kmac_err_chk.253052164
Short name T335
Test name
Test status
Simulation time 4033587801 ps
CPU time 32.74 seconds
Started Feb 25 12:38:07 PM PST 24
Finished Feb 25 12:38:40 PM PST 24
Peak memory 211668 kb
Host smart-17e0bd1f-9bbd-4189-992b-f35b284ac7fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=253052164 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_kmac_err_chk.253052164
Directory /workspace/44.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/44.rom_ctrl_max_throughput_chk.2280733492
Short name T355
Test name
Test status
Simulation time 864468472 ps
CPU time 10.14 seconds
Started Feb 25 12:38:20 PM PST 24
Finished Feb 25 12:38:30 PM PST 24
Peak memory 211028 kb
Host smart-b0d40100-ab68-45d9-925e-ee57b7bc857b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2280733492 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_max_throughput_chk.2280733492
Directory /workspace/44.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/44.rom_ctrl_smoke.2340390156
Short name T24
Test name
Test status
Simulation time 23702625592 ps
CPU time 32.98 seconds
Started Feb 25 12:38:14 PM PST 24
Finished Feb 25 12:38:48 PM PST 24
Peak memory 213344 kb
Host smart-0c3e35db-229e-4c86-8497-876f4ae1df1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2340390156 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_smoke.2340390156
Directory /workspace/44.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/44.rom_ctrl_stress_all.987548026
Short name T213
Test name
Test status
Simulation time 35722277315 ps
CPU time 54.59 seconds
Started Feb 25 12:38:30 PM PST 24
Finished Feb 25 12:39:26 PM PST 24
Peak memory 215192 kb
Host smart-70a259bc-c760-4785-b52c-0dc3c894e220
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=987548026 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 44.rom_ctrl_stress_all.987548026
Directory /workspace/44.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/45.rom_ctrl_alert_test.1214903950
Short name T362
Test name
Test status
Simulation time 10615784789 ps
CPU time 10.88 seconds
Started Feb 25 12:38:36 PM PST 24
Finished Feb 25 12:38:47 PM PST 24
Peak memory 211220 kb
Host smart-13b9e1b7-01da-4f8b-9638-a242786162da
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1214903950 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_alert_test.1214903950
Directory /workspace/45.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/45.rom_ctrl_corrupt_sig_fatal_chk.43449460
Short name T358
Test name
Test status
Simulation time 148381064299 ps
CPU time 233.6 seconds
Started Feb 25 12:38:05 PM PST 24
Finished Feb 25 12:41:59 PM PST 24
Peak memory 212380 kb
Host smart-d553f3b1-aec8-4c7b-84d7-e71af532161c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=43449460 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_
sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_co
rrupt_sig_fatal_chk.43449460
Directory /workspace/45.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/45.rom_ctrl_kmac_err_chk.2781828685
Short name T264
Test name
Test status
Simulation time 1722626068 ps
CPU time 20.63 seconds
Started Feb 25 12:38:09 PM PST 24
Finished Feb 25 12:38:30 PM PST 24
Peak memory 211460 kb
Host smart-fc5853fc-9cea-4e34-9a90-68a2ebabbb95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2781828685 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_kmac_err_chk.2781828685
Directory /workspace/45.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/45.rom_ctrl_max_throughput_chk.3789758225
Short name T330
Test name
Test status
Simulation time 9408908391 ps
CPU time 17.18 seconds
Started Feb 25 12:38:19 PM PST 24
Finished Feb 25 12:38:36 PM PST 24
Peak memory 211148 kb
Host smart-77116562-104e-464f-afb9-de224a5a48be
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3789758225 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_max_throughput_chk.3789758225
Directory /workspace/45.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/45.rom_ctrl_smoke.4051722515
Short name T183
Test name
Test status
Simulation time 3501960818 ps
CPU time 33.04 seconds
Started Feb 25 12:38:29 PM PST 24
Finished Feb 25 12:39:03 PM PST 24
Peak memory 212172 kb
Host smart-2a006c8f-cf2e-4aa6-acbf-c79dd65c6a5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4051722515 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_smoke.4051722515
Directory /workspace/45.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/45.rom_ctrl_stress_all.757495006
Short name T178
Test name
Test status
Simulation time 31696985205 ps
CPU time 67.94 seconds
Started Feb 25 12:38:28 PM PST 24
Finished Feb 25 12:39:37 PM PST 24
Peak memory 219340 kb
Host smart-a9533613-d26c-414b-b718-47a25e9ec8d8
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=757495006 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 45.rom_ctrl_stress_all.757495006
Directory /workspace/45.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/46.rom_ctrl_alert_test.1112602115
Short name T256
Test name
Test status
Simulation time 741285097 ps
CPU time 8.84 seconds
Started Feb 25 12:38:20 PM PST 24
Finished Feb 25 12:38:29 PM PST 24
Peak memory 211016 kb
Host smart-22a409a3-fc0d-49c5-a4a3-bf2268c1c0e6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1112602115 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_alert_test.1112602115
Directory /workspace/46.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/46.rom_ctrl_corrupt_sig_fatal_chk.394709141
Short name T231
Test name
Test status
Simulation time 20633280390 ps
CPU time 220.6 seconds
Started Feb 25 12:38:17 PM PST 24
Finished Feb 25 12:41:58 PM PST 24
Peak memory 234840 kb
Host smart-7e50c978-e226-477f-b526-450c7fe06cec
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=394709141 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_c
orrupt_sig_fatal_chk.394709141
Directory /workspace/46.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/46.rom_ctrl_kmac_err_chk.4250281619
Short name T153
Test name
Test status
Simulation time 1675559669 ps
CPU time 20.65 seconds
Started Feb 25 12:38:36 PM PST 24
Finished Feb 25 12:38:57 PM PST 24
Peak memory 211624 kb
Host smart-59089545-24b8-4592-bec0-ab5fecd6962b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4250281619 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_kmac_err_chk.4250281619
Directory /workspace/46.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/46.rom_ctrl_max_throughput_chk.2244745208
Short name T134
Test name
Test status
Simulation time 4154944177 ps
CPU time 7.79 seconds
Started Feb 25 12:38:34 PM PST 24
Finished Feb 25 12:38:43 PM PST 24
Peak memory 211120 kb
Host smart-003ec4e2-83e4-4766-b8a0-06f0f0f1fefd
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2244745208 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_max_throughput_chk.2244745208
Directory /workspace/46.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/46.rom_ctrl_smoke.2429781162
Short name T82
Test name
Test status
Simulation time 2239677672 ps
CPU time 25.59 seconds
Started Feb 25 12:38:16 PM PST 24
Finished Feb 25 12:38:42 PM PST 24
Peak memory 212944 kb
Host smart-589d4e9c-b099-4bb0-9dc6-1446d1d8d769
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2429781162 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_smoke.2429781162
Directory /workspace/46.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/46.rom_ctrl_stress_all.2928514687
Short name T169
Test name
Test status
Simulation time 17202621878 ps
CPU time 58.63 seconds
Started Feb 25 12:38:31 PM PST 24
Finished Feb 25 12:39:33 PM PST 24
Peak memory 219528 kb
Host smart-f16b9be3-2a6b-42c1-9efd-55b327570ea0
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2928514687 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 46.rom_ctrl_stress_all.2928514687
Directory /workspace/46.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/47.rom_ctrl_alert_test.1162812606
Short name T164
Test name
Test status
Simulation time 1893730653 ps
CPU time 10.4 seconds
Started Feb 25 12:38:29 PM PST 24
Finished Feb 25 12:38:41 PM PST 24
Peak memory 210988 kb
Host smart-a1196c2e-3825-4e7a-ac8f-74b8e1785ff7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1162812606 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_alert_test.1162812606
Directory /workspace/47.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/47.rom_ctrl_corrupt_sig_fatal_chk.1227571768
Short name T4
Test name
Test status
Simulation time 4046638082 ps
CPU time 146.98 seconds
Started Feb 25 12:38:19 PM PST 24
Finished Feb 25 12:40:46 PM PST 24
Peak memory 228416 kb
Host smart-c66ea86a-4224-414c-a356-4dd12b58f600
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1227571768 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_
corrupt_sig_fatal_chk.1227571768
Directory /workspace/47.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/47.rom_ctrl_kmac_err_chk.376615498
Short name T196
Test name
Test status
Simulation time 4297054585 ps
CPU time 35.14 seconds
Started Feb 25 12:38:17 PM PST 24
Finished Feb 25 12:38:52 PM PST 24
Peak memory 211476 kb
Host smart-2bffcd27-049f-43bd-833b-a511ecc7b967
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=376615498 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_kmac_err_chk.376615498
Directory /workspace/47.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/47.rom_ctrl_max_throughput_chk.1466305519
Short name T170
Test name
Test status
Simulation time 1989955779 ps
CPU time 16.48 seconds
Started Feb 25 12:38:30 PM PST 24
Finished Feb 25 12:38:48 PM PST 24
Peak memory 211096 kb
Host smart-7728e37c-e4e0-4a1c-bac3-344eb00ab644
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1466305519 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_max_throughput_chk.1466305519
Directory /workspace/47.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/47.rom_ctrl_smoke.4026265046
Short name T46
Test name
Test status
Simulation time 7188561504 ps
CPU time 26.11 seconds
Started Feb 25 12:38:14 PM PST 24
Finished Feb 25 12:38:40 PM PST 24
Peak memory 214232 kb
Host smart-39b37cab-9468-4d10-ad40-88d875b5f1a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4026265046 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_smoke.4026265046
Directory /workspace/47.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/47.rom_ctrl_stress_all.619821842
Short name T325
Test name
Test status
Simulation time 1386680386 ps
CPU time 17.9 seconds
Started Feb 25 12:38:32 PM PST 24
Finished Feb 25 12:38:52 PM PST 24
Peak memory 219184 kb
Host smart-1f7d815b-696b-42f3-9e9c-4b6a4b47e03c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=619821842 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 47.rom_ctrl_stress_all.619821842
Directory /workspace/47.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/47.rom_ctrl_stress_all_with_rand_reset.2407670193
Short name T52
Test name
Test status
Simulation time 3985148491 ps
CPU time 159.14 seconds
Started Feb 25 12:38:46 PM PST 24
Finished Feb 25 12:41:26 PM PST 24
Peak memory 230040 kb
Host smart-1b468d86-85a5-4460-9607-5c24096549f8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2407670193 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_stress_all_with_rand_reset.2407670193
Directory /workspace/47.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.rom_ctrl_alert_test.1363467319
Short name T311
Test name
Test status
Simulation time 107286553 ps
CPU time 4.26 seconds
Started Feb 25 12:38:11 PM PST 24
Finished Feb 25 12:38:16 PM PST 24
Peak memory 211092 kb
Host smart-b43a5882-df5f-4fe5-90a8-5caac9e09656
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1363467319 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_alert_test.1363467319
Directory /workspace/48.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/48.rom_ctrl_corrupt_sig_fatal_chk.3719906371
Short name T218
Test name
Test status
Simulation time 13630116982 ps
CPU time 131.08 seconds
Started Feb 25 12:38:33 PM PST 24
Finished Feb 25 12:40:46 PM PST 24
Peak memory 234208 kb
Host smart-6922d051-91bc-4069-895f-066051ed1f13
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3719906371 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_
corrupt_sig_fatal_chk.3719906371
Directory /workspace/48.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/48.rom_ctrl_kmac_err_chk.1522210578
Short name T154
Test name
Test status
Simulation time 11483338755 ps
CPU time 26.39 seconds
Started Feb 25 12:38:14 PM PST 24
Finished Feb 25 12:38:40 PM PST 24
Peak memory 212192 kb
Host smart-55992782-0c23-4133-b410-b0f8aab05e32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1522210578 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_kmac_err_chk.1522210578
Directory /workspace/48.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/48.rom_ctrl_max_throughput_chk.4204369849
Short name T233
Test name
Test status
Simulation time 2022556750 ps
CPU time 17.23 seconds
Started Feb 25 12:38:21 PM PST 24
Finished Feb 25 12:38:38 PM PST 24
Peak memory 211056 kb
Host smart-8b4f0506-9e41-488f-bd53-242b9d424c1a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4204369849 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_max_throughput_chk.4204369849
Directory /workspace/48.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/48.rom_ctrl_smoke.3305898167
Short name T179
Test name
Test status
Simulation time 3260927364 ps
CPU time 33.99 seconds
Started Feb 25 12:38:10 PM PST 24
Finished Feb 25 12:38:45 PM PST 24
Peak memory 212856 kb
Host smart-0c0bec0d-4222-456f-864c-b7079d83a5ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3305898167 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_smoke.3305898167
Directory /workspace/48.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/48.rom_ctrl_stress_all.2315966625
Short name T152
Test name
Test status
Simulation time 3542590599 ps
CPU time 40.02 seconds
Started Feb 25 12:38:03 PM PST 24
Finished Feb 25 12:38:43 PM PST 24
Peak memory 212280 kb
Host smart-b72279fd-02fc-4b83-8696-2420df319f9d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2315966625 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 48.rom_ctrl_stress_all.2315966625
Directory /workspace/48.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/49.rom_ctrl_alert_test.2236335497
Short name T297
Test name
Test status
Simulation time 4024329052 ps
CPU time 16.57 seconds
Started Feb 25 12:38:52 PM PST 24
Finished Feb 25 12:39:09 PM PST 24
Peak memory 211008 kb
Host smart-ac139bde-f545-416e-b95b-917b64a60393
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2236335497 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_alert_test.2236335497
Directory /workspace/49.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/49.rom_ctrl_corrupt_sig_fatal_chk.780124439
Short name T216
Test name
Test status
Simulation time 87339705332 ps
CPU time 193.97 seconds
Started Feb 25 12:38:42 PM PST 24
Finished Feb 25 12:41:57 PM PST 24
Peak memory 236792 kb
Host smart-6a1503c0-2ec9-437f-82a5-867e2a15fe27
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=780124439 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_c
orrupt_sig_fatal_chk.780124439
Directory /workspace/49.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/49.rom_ctrl_kmac_err_chk.3825750223
Short name T290
Test name
Test status
Simulation time 3752509403 ps
CPU time 26.11 seconds
Started Feb 25 12:38:35 PM PST 24
Finished Feb 25 12:39:01 PM PST 24
Peak memory 211540 kb
Host smart-d9c1b90a-4398-4cfd-8899-fdb69b3288d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3825750223 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_kmac_err_chk.3825750223
Directory /workspace/49.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/49.rom_ctrl_max_throughput_chk.1680719500
Short name T254
Test name
Test status
Simulation time 11067033460 ps
CPU time 9.72 seconds
Started Feb 25 12:38:12 PM PST 24
Finished Feb 25 12:38:22 PM PST 24
Peak memory 211080 kb
Host smart-40ab007b-9f88-423f-a28f-0689fc992beb
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1680719500 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_max_throughput_chk.1680719500
Directory /workspace/49.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/49.rom_ctrl_smoke.464237341
Short name T166
Test name
Test status
Simulation time 2474877767 ps
CPU time 27.67 seconds
Started Feb 25 12:38:13 PM PST 24
Finished Feb 25 12:38:42 PM PST 24
Peak memory 213000 kb
Host smart-7d3ed515-0455-48dc-aa98-615f23d7b63b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=464237341 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_smoke.464237341
Directory /workspace/49.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/49.rom_ctrl_stress_all.2389728601
Short name T42
Test name
Test status
Simulation time 2957576889 ps
CPU time 21.44 seconds
Started Feb 25 12:38:19 PM PST 24
Finished Feb 25 12:38:41 PM PST 24
Peak memory 213780 kb
Host smart-6d5e12a6-53cc-4de7-98a4-7da2a10250ee
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2389728601 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 49.rom_ctrl_stress_all.2389728601
Directory /workspace/49.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/49.rom_ctrl_stress_all_with_rand_reset.510486740
Short name T14
Test name
Test status
Simulation time 69056844477 ps
CPU time 2603.13 seconds
Started Feb 25 12:38:35 PM PST 24
Finished Feb 25 01:21:59 PM PST 24
Peak memory 252188 kb
Host smart-629c3a26-677e-42f1-8436-aa70c5947ea8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=510486740 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_stress_all_with_rand_reset.510486740
Directory /workspace/49.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.rom_ctrl_alert_test.1346318181
Short name T332
Test name
Test status
Simulation time 1311099017 ps
CPU time 6.68 seconds
Started Feb 25 12:37:50 PM PST 24
Finished Feb 25 12:37:57 PM PST 24
Peak memory 211032 kb
Host smart-4afc1608-8187-43c4-a5ee-4bf5e3c37bba
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1346318181 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_alert_test.1346318181
Directory /workspace/5.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/5.rom_ctrl_corrupt_sig_fatal_chk.1727785257
Short name T334
Test name
Test status
Simulation time 35648266423 ps
CPU time 183.84 seconds
Started Feb 25 12:37:46 PM PST 24
Finished Feb 25 12:40:50 PM PST 24
Peak memory 233664 kb
Host smart-f7a93274-cd4b-4be4-9828-222f48f0445b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1727785257 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_c
orrupt_sig_fatal_chk.1727785257
Directory /workspace/5.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/5.rom_ctrl_kmac_err_chk.1376755680
Short name T292
Test name
Test status
Simulation time 11041180171 ps
CPU time 24.3 seconds
Started Feb 25 12:37:50 PM PST 24
Finished Feb 25 12:38:14 PM PST 24
Peak memory 212168 kb
Host smart-d265ba54-0a97-4d3d-b6dd-b2a271511e8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1376755680 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_kmac_err_chk.1376755680
Directory /workspace/5.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/5.rom_ctrl_max_throughput_chk.2183758912
Short name T328
Test name
Test status
Simulation time 8481948180 ps
CPU time 17.61 seconds
Started Feb 25 12:38:05 PM PST 24
Finished Feb 25 12:38:23 PM PST 24
Peak memory 211176 kb
Host smart-a4bd7045-a155-49d3-9b3e-bcc37dda6415
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2183758912 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_max_throughput_chk.2183758912
Directory /workspace/5.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/5.rom_ctrl_smoke.1618803826
Short name T142
Test name
Test status
Simulation time 2061360259 ps
CPU time 27.33 seconds
Started Feb 25 12:37:51 PM PST 24
Finished Feb 25 12:38:18 PM PST 24
Peak memory 211748 kb
Host smart-74be8ab7-b3b1-4b36-93a5-23a2be03a437
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1618803826 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_smoke.1618803826
Directory /workspace/5.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/5.rom_ctrl_stress_all.911657272
Short name T285
Test name
Test status
Simulation time 6035001109 ps
CPU time 56.28 seconds
Started Feb 25 12:37:51 PM PST 24
Finished Feb 25 12:38:48 PM PST 24
Peak memory 216560 kb
Host smart-ab124939-c9a5-4b65-89ed-f624c3afe1c1
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=911657272 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 5.rom_ctrl_stress_all.911657272
Directory /workspace/5.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/6.rom_ctrl_alert_test.1012878408
Short name T197
Test name
Test status
Simulation time 987789231 ps
CPU time 10.31 seconds
Started Feb 25 12:37:50 PM PST 24
Finished Feb 25 12:38:01 PM PST 24
Peak memory 211008 kb
Host smart-3bed3dd1-4fa5-4af9-9acf-c5bec2d0c320
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1012878408 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_alert_test.1012878408
Directory /workspace/6.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/6.rom_ctrl_corrupt_sig_fatal_chk.1144827257
Short name T206
Test name
Test status
Simulation time 884263066775 ps
CPU time 448.79 seconds
Started Feb 25 12:37:54 PM PST 24
Finished Feb 25 12:45:23 PM PST 24
Peak memory 236524 kb
Host smart-a42f892a-62b4-4262-9bb0-0a8e656481cd
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1144827257 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_c
orrupt_sig_fatal_chk.1144827257
Directory /workspace/6.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/6.rom_ctrl_kmac_err_chk.3661305200
Short name T296
Test name
Test status
Simulation time 665961693 ps
CPU time 9.24 seconds
Started Feb 25 12:37:34 PM PST 24
Finished Feb 25 12:37:44 PM PST 24
Peak memory 210992 kb
Host smart-b4862d0d-826d-419a-a1b7-ce20c1d32823
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3661305200 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_kmac_err_chk.3661305200
Directory /workspace/6.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/6.rom_ctrl_max_throughput_chk.1647736096
Short name T267
Test name
Test status
Simulation time 329156006 ps
CPU time 7.19 seconds
Started Feb 25 12:37:52 PM PST 24
Finished Feb 25 12:37:59 PM PST 24
Peak memory 210904 kb
Host smart-e36b7280-6d9f-4b3d-a4bc-8acaa3867c43
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1647736096 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_max_throughput_chk.1647736096
Directory /workspace/6.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/6.rom_ctrl_smoke.715393756
Short name T324
Test name
Test status
Simulation time 5781288915 ps
CPU time 30.47 seconds
Started Feb 25 12:37:41 PM PST 24
Finished Feb 25 12:38:11 PM PST 24
Peak memory 213348 kb
Host smart-124fcd6d-6a07-4e47-ad43-ade66928e4b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=715393756 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_smoke.715393756
Directory /workspace/6.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/6.rom_ctrl_stress_all.231063035
Short name T359
Test name
Test status
Simulation time 387432365 ps
CPU time 21.63 seconds
Started Feb 25 12:37:45 PM PST 24
Finished Feb 25 12:38:07 PM PST 24
Peak memory 215148 kb
Host smart-1f9c8500-6b1a-4a84-8026-011fa3c6ef6f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=231063035 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 6.rom_ctrl_stress_all.231063035
Directory /workspace/6.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/7.rom_ctrl_alert_test.1086686317
Short name T305
Test name
Test status
Simulation time 5433178940 ps
CPU time 12.62 seconds
Started Feb 25 12:37:56 PM PST 24
Finished Feb 25 12:38:10 PM PST 24
Peak memory 211168 kb
Host smart-3e7da85f-8fb1-4a1b-812c-ac92ec67863a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1086686317 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_alert_test.1086686317
Directory /workspace/7.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/7.rom_ctrl_corrupt_sig_fatal_chk.3431131611
Short name T219
Test name
Test status
Simulation time 23762364303 ps
CPU time 273.83 seconds
Started Feb 25 12:37:44 PM PST 24
Finished Feb 25 12:42:18 PM PST 24
Peak memory 229696 kb
Host smart-085ee808-7ea2-4d49-84f3-27f8a406d8ed
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3431131611 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_c
orrupt_sig_fatal_chk.3431131611
Directory /workspace/7.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/7.rom_ctrl_kmac_err_chk.2912038768
Short name T159
Test name
Test status
Simulation time 2433130101 ps
CPU time 14.33 seconds
Started Feb 25 12:37:50 PM PST 24
Finished Feb 25 12:38:05 PM PST 24
Peak memory 211476 kb
Host smart-d1589015-0232-44f7-8f8a-18a3ca9161b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2912038768 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_kmac_err_chk.2912038768
Directory /workspace/7.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/7.rom_ctrl_max_throughput_chk.2615516890
Short name T201
Test name
Test status
Simulation time 1807011315 ps
CPU time 15.47 seconds
Started Feb 25 12:37:56 PM PST 24
Finished Feb 25 12:38:13 PM PST 24
Peak memory 211088 kb
Host smart-6555bd83-b1bf-4b17-968f-b78be407e64b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2615516890 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_max_throughput_chk.2615516890
Directory /workspace/7.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/7.rom_ctrl_smoke.42628774
Short name T199
Test name
Test status
Simulation time 8243138379 ps
CPU time 25.28 seconds
Started Feb 25 12:37:50 PM PST 24
Finished Feb 25 12:38:15 PM PST 24
Peak memory 213252 kb
Host smart-aa2fa703-2cca-435c-b80e-8de1adc2e92f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=42628774 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_smoke.42628774
Directory /workspace/7.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/7.rom_ctrl_stress_all.3038846984
Short name T221
Test name
Test status
Simulation time 3156708891 ps
CPU time 16.54 seconds
Started Feb 25 12:37:48 PM PST 24
Finished Feb 25 12:38:04 PM PST 24
Peak memory 210936 kb
Host smart-1be927b1-8f9e-41c3-8c50-545d552766ce
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3038846984 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 7.rom_ctrl_stress_all.3038846984
Directory /workspace/7.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/7.rom_ctrl_stress_all_with_rand_reset.2670924957
Short name T351
Test name
Test status
Simulation time 36132840222 ps
CPU time 1331.93 seconds
Started Feb 25 12:37:56 PM PST 24
Finished Feb 25 01:00:09 PM PST 24
Peak memory 235784 kb
Host smart-e759e2d8-d06e-474d-863e-3b3182a2f9ab
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2670924957 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_stress_all_with_rand_reset.2670924957
Directory /workspace/7.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.rom_ctrl_alert_test.2255946664
Short name T220
Test name
Test status
Simulation time 3207715549 ps
CPU time 13.94 seconds
Started Feb 25 12:37:48 PM PST 24
Finished Feb 25 12:38:02 PM PST 24
Peak memory 211100 kb
Host smart-5917ea20-f535-4de9-8b2d-0fa89eece431
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2255946664 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_alert_test.2255946664
Directory /workspace/8.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/8.rom_ctrl_corrupt_sig_fatal_chk.1083464411
Short name T248
Test name
Test status
Simulation time 1242824226 ps
CPU time 79.43 seconds
Started Feb 25 12:38:07 PM PST 24
Finished Feb 25 12:39:27 PM PST 24
Peak memory 228132 kb
Host smart-d23e1a9f-8b3f-4afe-b385-1327918c9982
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1083464411 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_c
orrupt_sig_fatal_chk.1083464411
Directory /workspace/8.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/8.rom_ctrl_kmac_err_chk.400555794
Short name T315
Test name
Test status
Simulation time 6788856771 ps
CPU time 19.85 seconds
Started Feb 25 12:37:46 PM PST 24
Finished Feb 25 12:38:07 PM PST 24
Peak memory 212248 kb
Host smart-aa399287-b9ee-47c7-ae87-ffc30811406a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=400555794 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_kmac_err_chk.400555794
Directory /workspace/8.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/8.rom_ctrl_max_throughput_chk.2341132454
Short name T2
Test name
Test status
Simulation time 107344254 ps
CPU time 5.18 seconds
Started Feb 25 12:37:45 PM PST 24
Finished Feb 25 12:37:51 PM PST 24
Peak memory 210996 kb
Host smart-aba182ae-a3ef-423e-ab9a-0478d3b03fd1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2341132454 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_max_throughput_chk.2341132454
Directory /workspace/8.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/8.rom_ctrl_smoke.2074471486
Short name T172
Test name
Test status
Simulation time 2256432834 ps
CPU time 24.28 seconds
Started Feb 25 12:37:44 PM PST 24
Finished Feb 25 12:38:09 PM PST 24
Peak memory 212996 kb
Host smart-3f344b56-3a2e-4940-8476-e1d594edcd40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2074471486 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_smoke.2074471486
Directory /workspace/8.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/8.rom_ctrl_stress_all.4129854595
Short name T302
Test name
Test status
Simulation time 575604276 ps
CPU time 16.5 seconds
Started Feb 25 12:37:41 PM PST 24
Finished Feb 25 12:37:58 PM PST 24
Peak memory 214528 kb
Host smart-cd1f4fb3-53d6-41d0-b2de-a7fcc5e82c0b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4129854595 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 8.rom_ctrl_stress_all.4129854595
Directory /workspace/8.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/9.rom_ctrl_alert_test.118440763
Short name T312
Test name
Test status
Simulation time 5105241929 ps
CPU time 11.43 seconds
Started Feb 25 12:37:54 PM PST 24
Finished Feb 25 12:38:06 PM PST 24
Peak memory 211224 kb
Host smart-bc79a460-0989-4642-9ec6-5c14787b9ea2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=118440763 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_alert_test.118440763
Directory /workspace/9.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/9.rom_ctrl_corrupt_sig_fatal_chk.3762891151
Short name T226
Test name
Test status
Simulation time 1888652702 ps
CPU time 124.75 seconds
Started Feb 25 12:37:49 PM PST 24
Finished Feb 25 12:39:54 PM PST 24
Peak memory 238824 kb
Host smart-50cfe386-39d0-4363-aa7b-0aedbeffc85e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3762891151 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_c
orrupt_sig_fatal_chk.3762891151
Directory /workspace/9.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/9.rom_ctrl_kmac_err_chk.1353440875
Short name T190
Test name
Test status
Simulation time 12919081372 ps
CPU time 29.28 seconds
Started Feb 25 12:37:57 PM PST 24
Finished Feb 25 12:38:26 PM PST 24
Peak memory 212016 kb
Host smart-b20d79d3-fbfb-476f-a6c6-4078be7036d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1353440875 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_kmac_err_chk.1353440875
Directory /workspace/9.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/9.rom_ctrl_max_throughput_chk.748152060
Short name T236
Test name
Test status
Simulation time 2650034441 ps
CPU time 9.37 seconds
Started Feb 25 12:37:48 PM PST 24
Finished Feb 25 12:37:57 PM PST 24
Peak memory 211112 kb
Host smart-b7186a9e-0722-41de-a109-d69003def552
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=748152060 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_max_throughput_chk.748152060
Directory /workspace/9.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/9.rom_ctrl_smoke.3965856072
Short name T240
Test name
Test status
Simulation time 10851827776 ps
CPU time 26.93 seconds
Started Feb 25 12:37:50 PM PST 24
Finished Feb 25 12:38:17 PM PST 24
Peak memory 213212 kb
Host smart-c061f881-2148-46ee-bc0c-faa459722052
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3965856072 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_smoke.3965856072
Directory /workspace/9.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/9.rom_ctrl_stress_all.47742174
Short name T57
Test name
Test status
Simulation time 4101156987 ps
CPU time 18.35 seconds
Started Feb 25 12:37:38 PM PST 24
Finished Feb 25 12:37:56 PM PST 24
Peak memory 213128 kb
Host smart-c002aa40-9bfe-456f-9cc9-6a0a396c7f80
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=47742174 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +U
VM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n
ame 9.rom_ctrl_stress_all.47742174
Directory /workspace/9.rom_ctrl_stress_all/latest
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