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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
97.45 97.04 92.65 97.88 100.00 98.37 98.04 98.14


Total test records in report: 471
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T303 /workspace/coverage/default/21.rom_ctrl_kmac_err_chk.1982563460 Feb 29 01:11:51 PM PST 24 Feb 29 01:12:06 PM PST 24 1684839869 ps
T304 /workspace/coverage/default/47.rom_ctrl_alert_test.4098730992 Feb 29 01:12:17 PM PST 24 Feb 29 01:12:30 PM PST 24 2596119141 ps
T305 /workspace/coverage/default/25.rom_ctrl_smoke.1528617746 Feb 29 01:11:59 PM PST 24 Feb 29 01:12:31 PM PST 24 5885777484 ps
T306 /workspace/coverage/default/37.rom_ctrl_max_throughput_chk.1660075001 Feb 29 01:12:09 PM PST 24 Feb 29 01:12:23 PM PST 24 2769028749 ps
T307 /workspace/coverage/default/16.rom_ctrl_stress_all_with_rand_reset.2734909433 Feb 29 01:11:42 PM PST 24 Feb 29 01:51:22 PM PST 24 385500867850 ps
T308 /workspace/coverage/default/8.rom_ctrl_alert_test.3133057239 Feb 29 01:11:38 PM PST 24 Feb 29 01:11:52 PM PST 24 1629066012 ps
T309 /workspace/coverage/default/17.rom_ctrl_alert_test.1638005856 Feb 29 01:11:43 PM PST 24 Feb 29 01:11:49 PM PST 24 688692213 ps
T310 /workspace/coverage/default/14.rom_ctrl_stress_all.598640008 Feb 29 01:11:46 PM PST 24 Feb 29 01:12:04 PM PST 24 3633297553 ps
T311 /workspace/coverage/default/49.rom_ctrl_corrupt_sig_fatal_chk.678386954 Feb 29 01:12:16 PM PST 24 Feb 29 01:14:27 PM PST 24 5154258887 ps
T312 /workspace/coverage/default/36.rom_ctrl_alert_test.4018514473 Feb 29 01:12:06 PM PST 24 Feb 29 01:12:17 PM PST 24 2294616793 ps
T313 /workspace/coverage/default/26.rom_ctrl_max_throughput_chk.3107796697 Feb 29 01:11:52 PM PST 24 Feb 29 01:12:01 PM PST 24 2577788409 ps
T314 /workspace/coverage/default/21.rom_ctrl_alert_test.1044485538 Feb 29 01:11:51 PM PST 24 Feb 29 01:11:56 PM PST 24 332634564 ps
T315 /workspace/coverage/default/39.rom_ctrl_smoke.3208851435 Feb 29 01:12:06 PM PST 24 Feb 29 01:12:16 PM PST 24 185842598 ps
T316 /workspace/coverage/default/25.rom_ctrl_corrupt_sig_fatal_chk.1157002050 Feb 29 01:11:54 PM PST 24 Feb 29 01:18:20 PM PST 24 156163252004 ps
T317 /workspace/coverage/default/17.rom_ctrl_stress_all.3453629602 Feb 29 01:11:45 PM PST 24 Feb 29 01:12:33 PM PST 24 6429207077 ps
T318 /workspace/coverage/default/12.rom_ctrl_max_throughput_chk.3392254119 Feb 29 01:11:41 PM PST 24 Feb 29 01:11:46 PM PST 24 1026065751 ps
T319 /workspace/coverage/default/10.rom_ctrl_corrupt_sig_fatal_chk.4099955877 Feb 29 01:11:39 PM PST 24 Feb 29 01:15:15 PM PST 24 356000689513 ps
T320 /workspace/coverage/default/0.rom_ctrl_smoke.3233253760 Feb 29 01:11:14 PM PST 24 Feb 29 01:11:32 PM PST 24 1182293055 ps
T321 /workspace/coverage/default/4.rom_ctrl_max_throughput_chk.4027293836 Feb 29 01:11:29 PM PST 24 Feb 29 01:11:42 PM PST 24 2698622447 ps
T322 /workspace/coverage/default/5.rom_ctrl_corrupt_sig_fatal_chk.726496504 Feb 29 01:11:24 PM PST 24 Feb 29 01:16:55 PM PST 24 38610211850 ps
T323 /workspace/coverage/default/2.rom_ctrl_kmac_err_chk.3061620589 Feb 29 01:11:25 PM PST 24 Feb 29 01:11:39 PM PST 24 1178285718 ps
T324 /workspace/coverage/default/12.rom_ctrl_alert_test.118079665 Feb 29 01:11:40 PM PST 24 Feb 29 01:11:52 PM PST 24 10651675586 ps
T325 /workspace/coverage/default/41.rom_ctrl_stress_all.1240716988 Feb 29 01:12:19 PM PST 24 Feb 29 01:12:42 PM PST 24 409587786 ps
T326 /workspace/coverage/default/3.rom_ctrl_smoke.1110617680 Feb 29 01:11:24 PM PST 24 Feb 29 01:11:42 PM PST 24 809909361 ps
T327 /workspace/coverage/default/32.rom_ctrl_max_throughput_chk.1103891824 Feb 29 01:12:05 PM PST 24 Feb 29 01:12:17 PM PST 24 17336125719 ps
T328 /workspace/coverage/default/43.rom_ctrl_corrupt_sig_fatal_chk.509535714 Feb 29 01:12:14 PM PST 24 Feb 29 01:17:07 PM PST 24 150500786653 ps
T35 /workspace/coverage/default/4.rom_ctrl_sec_cm.898727096 Feb 29 01:11:27 PM PST 24 Feb 29 01:12:24 PM PST 24 863619830 ps
T329 /workspace/coverage/default/8.rom_ctrl_corrupt_sig_fatal_chk.3819344526 Feb 29 01:11:40 PM PST 24 Feb 29 01:17:09 PM PST 24 28097171774 ps
T330 /workspace/coverage/default/7.rom_ctrl_kmac_err_chk.3420950372 Feb 29 01:11:41 PM PST 24 Feb 29 01:11:50 PM PST 24 168531020 ps
T331 /workspace/coverage/default/46.rom_ctrl_stress_all.3216026220 Feb 29 01:12:10 PM PST 24 Feb 29 01:12:23 PM PST 24 3015656417 ps
T332 /workspace/coverage/default/15.rom_ctrl_stress_all.1994805035 Feb 29 01:11:41 PM PST 24 Feb 29 01:11:46 PM PST 24 222848415 ps
T333 /workspace/coverage/default/43.rom_ctrl_alert_test.2830102504 Feb 29 01:12:11 PM PST 24 Feb 29 01:12:22 PM PST 24 1150718778 ps
T334 /workspace/coverage/default/12.rom_ctrl_smoke.3023810289 Feb 29 01:11:45 PM PST 24 Feb 29 01:11:56 PM PST 24 671007237 ps
T335 /workspace/coverage/default/18.rom_ctrl_kmac_err_chk.2544955377 Feb 29 01:11:53 PM PST 24 Feb 29 01:12:02 PM PST 24 615584326 ps
T336 /workspace/coverage/default/30.rom_ctrl_alert_test.3217967150 Feb 29 01:12:05 PM PST 24 Feb 29 01:12:22 PM PST 24 6594603751 ps
T337 /workspace/coverage/default/20.rom_ctrl_alert_test.3520278846 Feb 29 01:11:55 PM PST 24 Feb 29 01:12:04 PM PST 24 3140585770 ps
T338 /workspace/coverage/default/26.rom_ctrl_kmac_err_chk.3301577393 Feb 29 01:12:00 PM PST 24 Feb 29 01:12:23 PM PST 24 9902875173 ps
T339 /workspace/coverage/default/45.rom_ctrl_stress_all.3755351359 Feb 29 01:12:08 PM PST 24 Feb 29 01:12:52 PM PST 24 8878763668 ps
T36 /workspace/coverage/default/2.rom_ctrl_sec_cm.2399525026 Feb 29 01:11:27 PM PST 24 Feb 29 01:12:19 PM PST 24 548691626 ps
T340 /workspace/coverage/default/36.rom_ctrl_kmac_err_chk.2520969132 Feb 29 01:12:02 PM PST 24 Feb 29 01:12:32 PM PST 24 3407086687 ps
T341 /workspace/coverage/default/18.rom_ctrl_smoke.3317725296 Feb 29 01:11:44 PM PST 24 Feb 29 01:12:03 PM PST 24 5194850709 ps
T342 /workspace/coverage/default/12.rom_ctrl_kmac_err_chk.2578704695 Feb 29 01:11:41 PM PST 24 Feb 29 01:11:50 PM PST 24 693127058 ps
T343 /workspace/coverage/default/40.rom_ctrl_alert_test.4123271845 Feb 29 01:12:21 PM PST 24 Feb 29 01:12:33 PM PST 24 4985104984 ps
T344 /workspace/coverage/default/41.rom_ctrl_stress_all_with_rand_reset.3941366389 Feb 29 01:12:22 PM PST 24 Feb 29 01:44:10 PM PST 24 198405879716 ps
T345 /workspace/coverage/default/40.rom_ctrl_stress_all.2162812906 Feb 29 01:12:09 PM PST 24 Feb 29 01:13:20 PM PST 24 8212539151 ps
T346 /workspace/coverage/default/4.rom_ctrl_corrupt_sig_fatal_chk.2424302780 Feb 29 01:11:27 PM PST 24 Feb 29 01:15:29 PM PST 24 222406175688 ps
T347 /workspace/coverage/default/45.rom_ctrl_max_throughput_chk.918202229 Feb 29 01:12:22 PM PST 24 Feb 29 01:12:28 PM PST 24 384110853 ps
T348 /workspace/coverage/default/38.rom_ctrl_stress_all.3945386646 Feb 29 01:12:06 PM PST 24 Feb 29 01:13:09 PM PST 24 4665441545 ps
T349 /workspace/coverage/default/44.rom_ctrl_kmac_err_chk.487685394 Feb 29 01:12:14 PM PST 24 Feb 29 01:12:42 PM PST 24 24576156267 ps
T350 /workspace/coverage/default/34.rom_ctrl_max_throughput_chk.897065036 Feb 29 01:12:04 PM PST 24 Feb 29 01:12:21 PM PST 24 3770225817 ps
T351 /workspace/coverage/default/13.rom_ctrl_smoke.3831177724 Feb 29 01:11:41 PM PST 24 Feb 29 01:12:20 PM PST 24 8355337454 ps
T352 /workspace/coverage/default/44.rom_ctrl_stress_all_with_rand_reset.1713678149 Feb 29 01:12:10 PM PST 24 Feb 29 02:12:19 PM PST 24 172313929049 ps
T353 /workspace/coverage/default/46.rom_ctrl_alert_test.1656781410 Feb 29 01:12:08 PM PST 24 Feb 29 01:12:13 PM PST 24 88978804 ps
T354 /workspace/coverage/default/8.rom_ctrl_stress_all.129928745 Feb 29 01:11:40 PM PST 24 Feb 29 01:12:14 PM PST 24 8020104433 ps
T355 /workspace/coverage/default/4.rom_ctrl_alert_test.210365193 Feb 29 01:11:28 PM PST 24 Feb 29 01:11:39 PM PST 24 6931286578 ps
T356 /workspace/coverage/default/21.rom_ctrl_stress_all.2612642375 Feb 29 01:11:59 PM PST 24 Feb 29 01:12:48 PM PST 24 6105120623 ps
T357 /workspace/coverage/default/43.rom_ctrl_smoke.3926655652 Feb 29 01:12:09 PM PST 24 Feb 29 01:12:43 PM PST 24 3981375808 ps
T358 /workspace/coverage/default/1.rom_ctrl_stress_all_with_rand_reset.1667092584 Feb 29 01:11:27 PM PST 24 Feb 29 01:28:15 PM PST 24 24842489382 ps
T359 /workspace/coverage/default/21.rom_ctrl_max_throughput_chk.3494264951 Feb 29 01:11:51 PM PST 24 Feb 29 01:12:04 PM PST 24 2238893447 ps
T360 /workspace/coverage/default/15.rom_ctrl_kmac_err_chk.3822831963 Feb 29 01:11:42 PM PST 24 Feb 29 01:12:04 PM PST 24 2034229173 ps
T361 /workspace/coverage/default/35.rom_ctrl_stress_all.2625879606 Feb 29 01:12:10 PM PST 24 Feb 29 01:12:46 PM PST 24 8092504932 ps
T362 /workspace/coverage/default/25.rom_ctrl_stress_all.3263208274 Feb 29 01:11:54 PM PST 24 Feb 29 01:12:17 PM PST 24 4725836389 ps
T363 /workspace/coverage/default/17.rom_ctrl_stress_all_with_rand_reset.2486749628 Feb 29 01:11:43 PM PST 24 Feb 29 01:49:52 PM PST 24 102296385017 ps
T364 /workspace/coverage/default/15.rom_ctrl_max_throughput_chk.1511489505 Feb 29 01:11:42 PM PST 24 Feb 29 01:11:48 PM PST 24 94886278 ps
T365 /workspace/coverage/default/19.rom_ctrl_alert_test.1942984866 Feb 29 01:12:01 PM PST 24 Feb 29 01:12:14 PM PST 24 1474027308 ps
T366 /workspace/coverage/default/40.rom_ctrl_smoke.8888485 Feb 29 01:12:12 PM PST 24 Feb 29 01:12:50 PM PST 24 4250095910 ps
T367 /workspace/coverage/default/0.rom_ctrl_corrupt_sig_fatal_chk.1563759640 Feb 29 01:11:14 PM PST 24 Feb 29 01:16:55 PM PST 24 150238714564 ps
T368 /workspace/coverage/default/5.rom_ctrl_alert_test.1649722182 Feb 29 01:11:24 PM PST 24 Feb 29 01:11:37 PM PST 24 1167205257 ps
T369 /workspace/coverage/default/12.rom_ctrl_stress_all.1224179378 Feb 29 01:11:40 PM PST 24 Feb 29 01:12:04 PM PST 24 10815467508 ps
T370 /workspace/coverage/default/27.rom_ctrl_kmac_err_chk.3832496442 Feb 29 01:11:52 PM PST 24 Feb 29 01:12:10 PM PST 24 1385125706 ps
T371 /workspace/coverage/default/2.rom_ctrl_max_throughput_chk.2432307240 Feb 29 01:11:27 PM PST 24 Feb 29 01:11:40 PM PST 24 4840924838 ps
T372 /workspace/coverage/default/14.rom_ctrl_smoke.1710520212 Feb 29 01:11:41 PM PST 24 Feb 29 01:12:06 PM PST 24 3635808611 ps
T373 /workspace/coverage/default/26.rom_ctrl_smoke.1795302346 Feb 29 01:11:55 PM PST 24 Feb 29 01:12:05 PM PST 24 1115334013 ps
T374 /workspace/coverage/default/42.rom_ctrl_kmac_err_chk.4254131827 Feb 29 01:12:14 PM PST 24 Feb 29 01:12:23 PM PST 24 172129447 ps
T375 /workspace/coverage/default/18.rom_ctrl_stress_all.4074619614 Feb 29 01:11:47 PM PST 24 Feb 29 01:12:28 PM PST 24 4874219442 ps
T108 /workspace/coverage/default/43.rom_ctrl_stress_all_with_rand_reset.2006315942 Feb 29 01:12:09 PM PST 24 Feb 29 01:55:39 PM PST 24 275556313596 ps
T51 /workspace/coverage/cover_reg_top/19.rom_ctrl_passthru_mem_tl_intg_err.2725164297 Feb 29 12:45:57 PM PST 24 Feb 29 12:46:41 PM PST 24 3952275802 ps
T376 /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_walk.2409149556 Feb 29 12:46:00 PM PST 24 Feb 29 12:46:15 PM PST 24 24499393165 ps
T52 /workspace/coverage/cover_reg_top/13.rom_ctrl_same_csr_outstanding.3688628200 Feb 29 12:45:51 PM PST 24 Feb 29 12:45:55 PM PST 24 171671171 ps
T53 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_mem_rw_with_rand_reset.322145750 Feb 29 12:45:39 PM PST 24 Feb 29 12:45:52 PM PST 24 1270080754 ps
T57 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_rw.3759424739 Feb 29 12:45:21 PM PST 24 Feb 29 12:45:34 PM PST 24 6133984277 ps
T48 /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_intg_err.2004028998 Feb 29 12:45:56 PM PST 24 Feb 29 12:46:43 PM PST 24 2059644550 ps
T98 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_aliasing.3508969583 Feb 29 12:45:57 PM PST 24 Feb 29 12:46:05 PM PST 24 411930840 ps
T58 /workspace/coverage/cover_reg_top/18.rom_ctrl_passthru_mem_tl_intg_err.2184408116 Feb 29 12:46:01 PM PST 24 Feb 29 12:46:25 PM PST 24 699649584 ps
T59 /workspace/coverage/cover_reg_top/13.rom_ctrl_passthru_mem_tl_intg_err.3551040976 Feb 29 12:45:46 PM PST 24 Feb 29 12:46:54 PM PST 24 8655107079 ps
T60 /workspace/coverage/cover_reg_top/11.rom_ctrl_passthru_mem_tl_intg_err.1879383529 Feb 29 12:46:10 PM PST 24 Feb 29 12:46:59 PM PST 24 10346054480 ps
T92 /workspace/coverage/cover_reg_top/7.rom_ctrl_same_csr_outstanding.554544647 Feb 29 12:46:10 PM PST 24 Feb 29 12:46:15 PM PST 24 88434533 ps
T377 /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_mem_rw_with_rand_reset.2364172285 Feb 29 12:45:52 PM PST 24 Feb 29 12:46:05 PM PST 24 1545240827 ps
T93 /workspace/coverage/cover_reg_top/19.rom_ctrl_same_csr_outstanding.62878782 Feb 29 12:45:50 PM PST 24 Feb 29 12:45:57 PM PST 24 456454696 ps
T378 /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_errors.2075934404 Feb 29 12:45:56 PM PST 24 Feb 29 12:46:15 PM PST 24 2011134366 ps
T379 /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_mem_rw_with_rand_reset.2939322026 Feb 29 12:46:05 PM PST 24 Feb 29 12:46:13 PM PST 24 1194570803 ps
T99 /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_rw.3920747549 Feb 29 12:45:36 PM PST 24 Feb 29 12:45:46 PM PST 24 970598084 ps
T380 /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_errors.1633867772 Feb 29 12:46:00 PM PST 24 Feb 29 12:46:15 PM PST 24 1942279403 ps
T49 /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_intg_err.1325631391 Feb 29 12:45:57 PM PST 24 Feb 29 12:47:13 PM PST 24 5528730273 ps
T100 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_aliasing.4156581729 Feb 29 12:45:45 PM PST 24 Feb 29 12:45:55 PM PST 24 836663997 ps
T50 /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_intg_err.2479127057 Feb 29 12:45:36 PM PST 24 Feb 29 12:46:55 PM PST 24 4192804200 ps
T61 /workspace/coverage/cover_reg_top/6.rom_ctrl_passthru_mem_tl_intg_err.2199755254 Feb 29 12:46:05 PM PST 24 Feb 29 12:47:08 PM PST 24 12385271896 ps
T381 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_mem_rw_with_rand_reset.642865890 Feb 29 12:45:39 PM PST 24 Feb 29 12:45:54 PM PST 24 32944703772 ps
T382 /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_errors.2539987310 Feb 29 12:45:40 PM PST 24 Feb 29 12:46:01 PM PST 24 2179274210 ps
T383 /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_errors.883539186 Feb 29 12:46:22 PM PST 24 Feb 29 12:46:44 PM PST 24 2242025012 ps
T94 /workspace/coverage/cover_reg_top/14.rom_ctrl_same_csr_outstanding.3298083061 Feb 29 12:46:05 PM PST 24 Feb 29 12:46:22 PM PST 24 2085212529 ps
T109 /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_intg_err.1140813624 Feb 29 12:46:07 PM PST 24 Feb 29 12:46:44 PM PST 24 163555986 ps
T62 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_hw_reset.415820847 Feb 29 12:45:32 PM PST 24 Feb 29 12:45:39 PM PST 24 94368649 ps
T384 /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_rw.220272530 Feb 29 12:45:50 PM PST 24 Feb 29 12:45:55 PM PST 24 518209239 ps
T385 /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_mem_rw_with_rand_reset.2494947039 Feb 29 12:45:57 PM PST 24 Feb 29 12:46:07 PM PST 24 1217001595 ps
T386 /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_rw.2200694443 Feb 29 12:45:53 PM PST 24 Feb 29 12:45:58 PM PST 24 1658215474 ps
T95 /workspace/coverage/cover_reg_top/10.rom_ctrl_same_csr_outstanding.717103903 Feb 29 12:45:55 PM PST 24 Feb 29 12:46:10 PM PST 24 1493377789 ps
T63 /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_rw.1607345253 Feb 29 12:45:56 PM PST 24 Feb 29 12:46:10 PM PST 24 2606387002 ps
T387 /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_walk.1450867738 Feb 29 12:45:56 PM PST 24 Feb 29 12:46:08 PM PST 24 7924708272 ps
T388 /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_mem_rw_with_rand_reset.3237715980 Feb 29 12:45:54 PM PST 24 Feb 29 12:46:04 PM PST 24 5554485865 ps
T64 /workspace/coverage/cover_reg_top/16.rom_ctrl_passthru_mem_tl_intg_err.2385016003 Feb 29 12:46:18 PM PST 24 Feb 29 12:47:41 PM PST 24 9541636681 ps
T389 /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_walk.1322260645 Feb 29 12:45:24 PM PST 24 Feb 29 12:45:35 PM PST 24 1056005648 ps
T390 /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_errors.3313267392 Feb 29 12:45:38 PM PST 24 Feb 29 12:45:57 PM PST 24 6098940625 ps
T115 /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_intg_err.955697186 Feb 29 12:45:59 PM PST 24 Feb 29 12:46:45 PM PST 24 1558030822 ps
T391 /workspace/coverage/cover_reg_top/5.rom_ctrl_passthru_mem_tl_intg_err.4266130317 Feb 29 12:45:42 PM PST 24 Feb 29 12:46:33 PM PST 24 10753334845 ps
T392 /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_mem_rw_with_rand_reset.3310894590 Feb 29 12:46:03 PM PST 24 Feb 29 12:46:17 PM PST 24 3253008378 ps
T393 /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_partial_access.2428309634 Feb 29 12:45:50 PM PST 24 Feb 29 12:46:00 PM PST 24 4086074085 ps
T394 /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_walk.261596754 Feb 29 12:45:39 PM PST 24 Feb 29 12:45:52 PM PST 24 1185238201 ps
T395 /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_mem_rw_with_rand_reset.3998846310 Feb 29 12:45:57 PM PST 24 Feb 29 12:46:14 PM PST 24 2001641720 ps
T396 /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_errors.1229213808 Feb 29 12:46:02 PM PST 24 Feb 29 12:46:18 PM PST 24 6385208390 ps
T70 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_aliasing.1059699982 Feb 29 12:45:21 PM PST 24 Feb 29 12:45:37 PM PST 24 23002812058 ps
T397 /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_rw.2277307581 Feb 29 12:45:54 PM PST 24 Feb 29 12:45:59 PM PST 24 89279430 ps
T96 /workspace/coverage/cover_reg_top/5.rom_ctrl_same_csr_outstanding.1995670383 Feb 29 12:45:48 PM PST 24 Feb 29 12:45:52 PM PST 24 639354906 ps
T71 /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_rw.4157905795 Feb 29 12:46:00 PM PST 24 Feb 29 12:46:13 PM PST 24 1309377234 ps
T398 /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_rw.470359279 Feb 29 12:45:57 PM PST 24 Feb 29 12:46:03 PM PST 24 86685530 ps
T399 /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_errors.3895669592 Feb 29 12:45:21 PM PST 24 Feb 29 12:45:31 PM PST 24 1424326194 ps
T400 /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_errors.71612861 Feb 29 12:45:56 PM PST 24 Feb 29 12:46:11 PM PST 24 4571790610 ps
T401 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_bit_bash.2094358643 Feb 29 12:45:24 PM PST 24 Feb 29 12:45:47 PM PST 24 3662341849 ps
T402 /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_partial_access.4180912723 Feb 29 12:45:24 PM PST 24 Feb 29 12:45:38 PM PST 24 1668105503 ps
T72 /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_rw.3120303193 Feb 29 12:46:03 PM PST 24 Feb 29 12:46:13 PM PST 24 6022947959 ps
T403 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_bit_bash.2120414690 Feb 29 12:45:54 PM PST 24 Feb 29 12:46:09 PM PST 24 3995917212 ps
T404 /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_mem_rw_with_rand_reset.354836991 Feb 29 12:45:54 PM PST 24 Feb 29 12:46:07 PM PST 24 1416859077 ps
T405 /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_rw.1631109154 Feb 29 12:45:57 PM PST 24 Feb 29 12:46:04 PM PST 24 85707312 ps
T406 /workspace/coverage/cover_reg_top/16.rom_ctrl_same_csr_outstanding.4181251563 Feb 29 12:46:21 PM PST 24 Feb 29 12:46:31 PM PST 24 3258857865 ps
T113 /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_intg_err.2050124431 Feb 29 12:45:54 PM PST 24 Feb 29 12:47:11 PM PST 24 5972717805 ps
T407 /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_partial_access.2388859654 Feb 29 12:45:59 PM PST 24 Feb 29 12:46:06 PM PST 24 1487849104 ps
T110 /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_intg_err.2231095240 Feb 29 12:46:04 PM PST 24 Feb 29 12:46:42 PM PST 24 171113192 ps
T408 /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_errors.1242086812 Feb 29 12:46:01 PM PST 24 Feb 29 12:46:21 PM PST 24 8590192001 ps
T409 /workspace/coverage/cover_reg_top/3.rom_ctrl_same_csr_outstanding.50912516 Feb 29 12:46:06 PM PST 24 Feb 29 12:46:18 PM PST 24 131785255 ps
T410 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_hw_reset.2152432041 Feb 29 12:46:03 PM PST 24 Feb 29 12:46:14 PM PST 24 1075198160 ps
T411 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_hw_reset.1800101032 Feb 29 12:45:39 PM PST 24 Feb 29 12:45:55 PM PST 24 6053058608 ps
T412 /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_mem_rw_with_rand_reset.1977739007 Feb 29 12:46:02 PM PST 24 Feb 29 12:46:07 PM PST 24 188096503 ps
T111 /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_intg_err.3564537281 Feb 29 12:45:34 PM PST 24 Feb 29 12:46:48 PM PST 24 3740066431 ps
T413 /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_partial_access.2883386288 Feb 29 12:45:53 PM PST 24 Feb 29 12:45:58 PM PST 24 1652542353 ps
T80 /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_rw.3086109193 Feb 29 12:46:08 PM PST 24 Feb 29 12:46:23 PM PST 24 3933674275 ps
T114 /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_intg_err.1135104944 Feb 29 12:45:37 PM PST 24 Feb 29 12:46:54 PM PST 24 2012280631 ps
T414 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_mem_rw_with_rand_reset.2604687183 Feb 29 12:45:53 PM PST 24 Feb 29 12:46:03 PM PST 24 1908329219 ps
T415 /workspace/coverage/cover_reg_top/1.rom_ctrl_same_csr_outstanding.898826424 Feb 29 12:45:42 PM PST 24 Feb 29 12:45:48 PM PST 24 173682871 ps
T117 /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_intg_err.2364398662 Feb 29 12:45:45 PM PST 24 Feb 29 12:46:30 PM PST 24 3416253543 ps
T416 /workspace/coverage/cover_reg_top/8.rom_ctrl_same_csr_outstanding.3257883949 Feb 29 12:45:40 PM PST 24 Feb 29 12:45:48 PM PST 24 98763670 ps
T417 /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_mem_rw_with_rand_reset.2979508344 Feb 29 12:45:57 PM PST 24 Feb 29 12:46:04 PM PST 24 522937404 ps
T418 /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_rw.545422844 Feb 29 12:45:50 PM PST 24 Feb 29 12:45:58 PM PST 24 4067134959 ps
T419 /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_mem_rw_with_rand_reset.3770303819 Feb 29 12:45:59 PM PST 24 Feb 29 12:46:15 PM PST 24 3398299913 ps
T420 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_bit_bash.2062206969 Feb 29 12:45:39 PM PST 24 Feb 29 12:45:52 PM PST 24 8213656366 ps
T421 /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_errors.1815656470 Feb 29 12:45:57 PM PST 24 Feb 29 12:46:12 PM PST 24 7910048253 ps
T73 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_hw_reset.978656322 Feb 29 12:45:22 PM PST 24 Feb 29 12:45:29 PM PST 24 93645790 ps
T422 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_aliasing.2943893760 Feb 29 12:45:36 PM PST 24 Feb 29 12:45:51 PM PST 24 3693258699 ps
T423 /workspace/coverage/cover_reg_top/6.rom_ctrl_same_csr_outstanding.3886328516 Feb 29 12:45:51 PM PST 24 Feb 29 12:46:01 PM PST 24 940588617 ps
T112 /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_intg_err.2121073524 Feb 29 12:46:02 PM PST 24 Feb 29 12:46:43 PM PST 24 1629766249 ps
T424 /workspace/coverage/cover_reg_top/15.rom_ctrl_same_csr_outstanding.762667925 Feb 29 12:46:02 PM PST 24 Feb 29 12:46:14 PM PST 24 780332692 ps
T425 /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_walk.938454990 Feb 29 12:45:38 PM PST 24 Feb 29 12:45:46 PM PST 24 2486515020 ps
T426 /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_errors.1566809854 Feb 29 12:46:04 PM PST 24 Feb 29 12:46:21 PM PST 24 1724496639 ps
T81 /workspace/coverage/cover_reg_top/8.rom_ctrl_passthru_mem_tl_intg_err.3522687046 Feb 29 12:46:12 PM PST 24 Feb 29 12:46:40 PM PST 24 5878370035 ps
T427 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_bit_bash.3373044531 Feb 29 12:45:40 PM PST 24 Feb 29 12:45:53 PM PST 24 3756902191 ps
T428 /workspace/coverage/cover_reg_top/2.rom_ctrl_same_csr_outstanding.1714452789 Feb 29 12:45:39 PM PST 24 Feb 29 12:45:44 PM PST 24 85864405 ps
T429 /workspace/coverage/cover_reg_top/9.rom_ctrl_passthru_mem_tl_intg_err.2544758594 Feb 29 12:45:36 PM PST 24 Feb 29 12:45:55 PM PST 24 360996600 ps
T430 /workspace/coverage/cover_reg_top/12.rom_ctrl_same_csr_outstanding.2186851334 Feb 29 12:45:56 PM PST 24 Feb 29 12:46:10 PM PST 24 1573106025 ps
T120 /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_intg_err.1970188754 Feb 29 12:46:21 PM PST 24 Feb 29 12:47:05 PM PST 24 1260351608 ps
T82 /workspace/coverage/cover_reg_top/2.rom_ctrl_passthru_mem_tl_intg_err.3035676329 Feb 29 12:45:51 PM PST 24 Feb 29 12:46:26 PM PST 24 9651798130 ps
T74 /workspace/coverage/cover_reg_top/10.rom_ctrl_passthru_mem_tl_intg_err.1823638930 Feb 29 12:45:42 PM PST 24 Feb 29 12:46:15 PM PST 24 9779589443 ps
T78 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_rw.381162713 Feb 29 12:45:48 PM PST 24 Feb 29 12:46:05 PM PST 24 2188728584 ps
T431 /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_intg_err.1209577049 Feb 29 12:45:56 PM PST 24 Feb 29 12:46:34 PM PST 24 688743306 ps
T432 /workspace/coverage/cover_reg_top/17.rom_ctrl_same_csr_outstanding.697268846 Feb 29 12:45:38 PM PST 24 Feb 29 12:45:46 PM PST 24 1420511627 ps
T433 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_aliasing.81314844 Feb 29 12:46:03 PM PST 24 Feb 29 12:46:14 PM PST 24 1104946022 ps
T434 /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_errors.2761710609 Feb 29 12:46:01 PM PST 24 Feb 29 12:46:16 PM PST 24 6109278803 ps
T435 /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_errors.3506208288 Feb 29 12:45:35 PM PST 24 Feb 29 12:45:48 PM PST 24 2139411162 ps
T436 /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_intg_err.1211445851 Feb 29 12:45:39 PM PST 24 Feb 29 12:47:00 PM PST 24 7534699180 ps
T437 /workspace/coverage/cover_reg_top/0.rom_ctrl_passthru_mem_tl_intg_err.2488892024 Feb 29 12:45:22 PM PST 24 Feb 29 12:46:46 PM PST 24 39642601000 ps
T438 /workspace/coverage/cover_reg_top/0.rom_ctrl_same_csr_outstanding.291737035 Feb 29 12:45:20 PM PST 24 Feb 29 12:45:35 PM PST 24 1818981347 ps
T116 /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_intg_err.1177179181 Feb 29 12:45:55 PM PST 24 Feb 29 12:47:08 PM PST 24 12155728620 ps
T439 /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_rw.3873109704 Feb 29 12:45:53 PM PST 24 Feb 29 12:45:59 PM PST 24 173856510 ps
T118 /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_intg_err.4268472507 Feb 29 12:45:34 PM PST 24 Feb 29 12:46:18 PM PST 24 5362845314 ps
T105 /workspace/coverage/cover_reg_top/4.rom_ctrl_passthru_mem_tl_intg_err.2074278704 Feb 29 12:45:58 PM PST 24 Feb 29 12:46:43 PM PST 24 4324392284 ps
T440 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_rw.1869840915 Feb 29 12:45:56 PM PST 24 Feb 29 12:46:10 PM PST 24 30173411364 ps
T441 /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_mem_rw_with_rand_reset.4070688867 Feb 29 12:46:06 PM PST 24 Feb 29 12:46:20 PM PST 24 1632928878 ps
T442 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_rw.2931567555 Feb 29 12:46:10 PM PST 24 Feb 29 12:46:28 PM PST 24 2128509086 ps
T443 /workspace/coverage/cover_reg_top/1.rom_ctrl_passthru_mem_tl_intg_err.231295877 Feb 29 12:45:24 PM PST 24 Feb 29 12:45:43 PM PST 24 378796327 ps
T444 /workspace/coverage/cover_reg_top/4.rom_ctrl_same_csr_outstanding.871902191 Feb 29 12:45:58 PM PST 24 Feb 29 12:46:03 PM PST 24 85755270 ps
T75 /workspace/coverage/cover_reg_top/3.rom_ctrl_passthru_mem_tl_intg_err.3759015835 Feb 29 12:45:39 PM PST 24 Feb 29 12:46:07 PM PST 24 1137648785 ps
T445 /workspace/coverage/cover_reg_top/7.rom_ctrl_passthru_mem_tl_intg_err.3830926720 Feb 29 12:46:01 PM PST 24 Feb 29 12:47:18 PM PST 24 8637562840 ps
T446 /workspace/coverage/cover_reg_top/18.rom_ctrl_same_csr_outstanding.3302741812 Feb 29 12:46:06 PM PST 24 Feb 29 12:46:10 PM PST 24 347469826 ps
T447 /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_errors.3576944646 Feb 29 12:45:55 PM PST 24 Feb 29 12:46:08 PM PST 24 924369787 ps
T448 /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_intg_err.1628377605 Feb 29 12:46:03 PM PST 24 Feb 29 12:46:51 PM PST 24 8468953592 ps
T449 /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_errors.4088048870 Feb 29 12:46:22 PM PST 24 Feb 29 12:46:29 PM PST 24 175360782 ps
T76 /workspace/coverage/cover_reg_top/14.rom_ctrl_passthru_mem_tl_intg_err.2922904137 Feb 29 12:46:06 PM PST 24 Feb 29 12:46:56 PM PST 24 3498771203 ps
T450 /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_intg_err.3612223864 Feb 29 12:46:00 PM PST 24 Feb 29 12:46:47 PM PST 24 12453612328 ps
T451 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_mem_rw_with_rand_reset.1856456156 Feb 29 12:46:00 PM PST 24 Feb 29 12:46:09 PM PST 24 222881786 ps
T106 /workspace/coverage/cover_reg_top/17.rom_ctrl_passthru_mem_tl_intg_err.3573269049 Feb 29 12:45:57 PM PST 24 Feb 29 12:46:31 PM PST 24 8272343253 ps
T452 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_hw_reset.2477895183 Feb 29 12:46:12 PM PST 24 Feb 29 12:46:29 PM PST 24 1571739201 ps
T453 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_mem_rw_with_rand_reset.3427065785 Feb 29 12:45:25 PM PST 24 Feb 29 12:45:38 PM PST 24 2992005299 ps
T454 /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_errors.1488867859 Feb 29 12:46:07 PM PST 24 Feb 29 12:46:15 PM PST 24 334323219 ps
T455 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_bit_bash.148464076 Feb 29 12:45:55 PM PST 24 Feb 29 12:46:00 PM PST 24 333885216 ps
T77 /workspace/coverage/cover_reg_top/15.rom_ctrl_passthru_mem_tl_intg_err.4132793761 Feb 29 12:45:53 PM PST 24 Feb 29 12:47:30 PM PST 24 12865003259 ps
T119 /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_intg_err.492875181 Feb 29 12:45:50 PM PST 24 Feb 29 12:46:32 PM PST 24 6773389635 ps
T456 /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_partial_access.883569706 Feb 29 12:45:52 PM PST 24 Feb 29 12:46:02 PM PST 24 171926521 ps
T79 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_rw.1297786044 Feb 29 12:46:06 PM PST 24 Feb 29 12:46:10 PM PST 24 89272438 ps
T457 /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_mem_rw_with_rand_reset.4263117679 Feb 29 12:46:16 PM PST 24 Feb 29 12:46:34 PM PST 24 2140738141 ps
T458 /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_errors.292436781 Feb 29 12:45:24 PM PST 24 Feb 29 12:45:33 PM PST 24 291386939 ps
T459 /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_intg_err.1549846519 Feb 29 12:45:22 PM PST 24 Feb 29 12:46:32 PM PST 24 1573671139 ps
T460 /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_mem_rw_with_rand_reset.529705867 Feb 29 12:45:41 PM PST 24 Feb 29 12:45:48 PM PST 24 739062241 ps
T461 /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_mem_rw_with_rand_reset.4172129207 Feb 29 12:45:56 PM PST 24 Feb 29 12:46:09 PM PST 24 4785856928 ps
T462 /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_errors.1105281793 Feb 29 12:46:07 PM PST 24 Feb 29 12:46:24 PM PST 24 1863446333 ps
T463 /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_errors.3875912842 Feb 29 12:46:11 PM PST 24 Feb 29 12:46:33 PM PST 24 2145380374 ps
T464 /workspace/coverage/cover_reg_top/12.rom_ctrl_passthru_mem_tl_intg_err.1897894550 Feb 29 12:46:19 PM PST 24 Feb 29 12:47:37 PM PST 24 8874985057 ps
T465 /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_rw.1129994373 Feb 29 12:45:56 PM PST 24 Feb 29 12:46:07 PM PST 24 2096563850 ps
T466 /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_errors.585382106 Feb 29 12:45:53 PM PST 24 Feb 29 12:46:13 PM PST 24 8332785530 ps
T467 /workspace/coverage/cover_reg_top/11.rom_ctrl_same_csr_outstanding.3379195074 Feb 29 12:46:06 PM PST 24 Feb 29 12:46:15 PM PST 24 702870972 ps
T468 /workspace/coverage/cover_reg_top/9.rom_ctrl_same_csr_outstanding.1227465483 Feb 29 12:45:37 PM PST 24 Feb 29 12:45:46 PM PST 24 679133430 ps
T469 /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_rw.1443722749 Feb 29 12:46:01 PM PST 24 Feb 29 12:46:15 PM PST 24 1445166671 ps
T470 /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_rw.3607192702 Feb 29 12:46:01 PM PST 24 Feb 29 12:46:11 PM PST 24 1004639035 ps
T471 /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_mem_rw_with_rand_reset.3443370629 Feb 29 12:45:50 PM PST 24 Feb 29 12:45:55 PM PST 24 180176422 ps

Test location /workspace/coverage/default/47.rom_ctrl_corrupt_sig_fatal_chk.2844332201
Short name T3
Test name
Test status
Simulation time 129623404458 ps
CPU time 291.58 seconds
Started Feb 29 01:12:13 PM PST 24
Finished Feb 29 01:17:05 PM PST 24
Peak memory 232700 kb
Host smart-618fd46a-16ab-4dc0-abb3-8c086b92f143
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2844332201 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_
corrupt_sig_fatal_chk.2844332201
Directory /workspace/47.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/5.rom_ctrl_stress_all_with_rand_reset.1372105855
Short name T12
Test name
Test status
Simulation time 22920283569 ps
CPU time 8133.71 seconds
Started Feb 29 01:11:28 PM PST 24
Finished Feb 29 03:27:03 PM PST 24
Peak memory 228088 kb
Host smart-f43280a1-33d6-4b60-b2b1-fdd6ec626b7e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1372105855 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_stress_all_with_rand_reset.1372105855
Directory /workspace/5.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/27.rom_ctrl_stress_all_with_rand_reset.1739982156
Short name T14
Test name
Test status
Simulation time 29567774712 ps
CPU time 2657.74 seconds
Started Feb 29 01:12:04 PM PST 24
Finished Feb 29 01:56:23 PM PST 24
Peak memory 227656 kb
Host smart-187ef7c7-ba25-4287-973c-dd3c33b86d4d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1739982156 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_stress_all_with_rand_reset.1739982156
Directory /workspace/27.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.rom_ctrl_corrupt_sig_fatal_chk.2511847476
Short name T216
Test name
Test status
Simulation time 139493197622 ps
CPU time 349.32 seconds
Started Feb 29 01:11:24 PM PST 24
Finished Feb 29 01:17:14 PM PST 24
Peak memory 234316 kb
Host smart-49e0d313-99da-4fbb-a85e-16a1217accd2
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2511847476 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_c
orrupt_sig_fatal_chk.2511847476
Directory /workspace/3.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_intg_err.2479127057
Short name T50
Test name
Test status
Simulation time 4192804200 ps
CPU time 78.8 seconds
Started Feb 29 12:45:36 PM PST 24
Finished Feb 29 12:46:55 PM PST 24
Peak memory 210668 kb
Host smart-093c3f25-9440-4b94-97a2-e0e8725075b9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2479127057 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_tl_i
ntg_err.2479127057
Directory /workspace/17.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/6.rom_ctrl_stress_all.1826858822
Short name T11
Test name
Test status
Simulation time 5589203036 ps
CPU time 60.26 seconds
Started Feb 29 01:11:25 PM PST 24
Finished Feb 29 01:12:25 PM PST 24
Peak memory 219224 kb
Host smart-2f346cdd-1d8e-4a63-ae69-bd79763b02b1
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1826858822 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 6.rom_ctrl_stress_all.1826858822
Directory /workspace/6.rom_ctrl_stress_all/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_passthru_mem_tl_intg_err.1879383529
Short name T60
Test name
Test status
Simulation time 10346054480 ps
CPU time 47.12 seconds
Started Feb 29 12:46:10 PM PST 24
Finished Feb 29 12:46:59 PM PST 24
Peak memory 210636 kb
Host smart-8ab4bfb8-fb42-423a-987f-525ad260b107
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1879383529 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_p
assthru_mem_tl_intg_err.1879383529
Directory /workspace/11.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/default/0.rom_ctrl_sec_cm.3456535242
Short name T4
Test name
Test status
Simulation time 1584378648 ps
CPU time 56.9 seconds
Started Feb 29 01:11:21 PM PST 24
Finished Feb 29 01:12:19 PM PST 24
Peak memory 236408 kb
Host smart-e7ec98a0-9eca-4c6f-8116-88db8b43a6b0
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3456535242 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_sec_cm.3456535242
Directory /workspace/0.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_intg_err.2364398662
Short name T117
Test name
Test status
Simulation time 3416253543 ps
CPU time 45.27 seconds
Started Feb 29 12:45:45 PM PST 24
Finished Feb 29 12:46:30 PM PST 24
Peak memory 210644 kb
Host smart-493240ce-4902-486f-9473-1f951f3f105b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2364398662 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_tl_in
tg_err.2364398662
Directory /workspace/3.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/1.rom_ctrl_alert_test.2773622252
Short name T9
Test name
Test status
Simulation time 2735498375 ps
CPU time 5.68 seconds
Started Feb 29 01:11:25 PM PST 24
Finished Feb 29 01:11:31 PM PST 24
Peak memory 211136 kb
Host smart-b8c48554-e999-4dd5-9a1b-d57b8834ad84
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2773622252 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_alert_test.2773622252
Directory /workspace/1.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/11.rom_ctrl_kmac_err_chk.2651994794
Short name T137
Test name
Test status
Simulation time 42047132977 ps
CPU time 26.03 seconds
Started Feb 29 01:11:41 PM PST 24
Finished Feb 29 01:12:07 PM PST 24
Peak memory 211844 kb
Host smart-c80db466-1ffa-4061-88b2-659e92a1ccbd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2651994794 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_kmac_err_chk.2651994794
Directory /workspace/11.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/1.rom_ctrl_kmac_err_chk.2217166553
Short name T208
Test name
Test status
Simulation time 693479291 ps
CPU time 9.35 seconds
Started Feb 29 01:11:24 PM PST 24
Finished Feb 29 01:11:35 PM PST 24
Peak memory 211036 kb
Host smart-370160f6-b2fd-48cd-ab59-b29173ba810b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2217166553 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_kmac_err_chk.2217166553
Directory /workspace/1.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_intg_err.1325631391
Short name T49
Test name
Test status
Simulation time 5528730273 ps
CPU time 74.64 seconds
Started Feb 29 12:45:57 PM PST 24
Finished Feb 29 12:47:13 PM PST 24
Peak memory 212560 kb
Host smart-735200df-7166-40b9-841d-270ab67d0d46
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1325631391 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_tl_i
ntg_err.1325631391
Directory /workspace/11.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_passthru_mem_tl_intg_err.1897894550
Short name T464
Test name
Test status
Simulation time 8874985057 ps
CPU time 77.8 seconds
Started Feb 29 12:46:19 PM PST 24
Finished Feb 29 12:47:37 PM PST 24
Peak memory 211712 kb
Host smart-6cb8d16f-2f9f-48cb-afb6-40725ee80334
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1897894550 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_p
assthru_mem_tl_intg_err.1897894550
Directory /workspace/12.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_intg_err.955697186
Short name T115
Test name
Test status
Simulation time 1558030822 ps
CPU time 45.16 seconds
Started Feb 29 12:45:59 PM PST 24
Finished Feb 29 12:46:45 PM PST 24
Peak memory 211312 kb
Host smart-52cb496b-a32d-480c-a892-317fcf4c48f2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=955697186 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_tl_int
g_err.955697186
Directory /workspace/4.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/18.rom_ctrl_corrupt_sig_fatal_chk.3064414047
Short name T89
Test name
Test status
Simulation time 1294143836 ps
CPU time 77.82 seconds
Started Feb 29 01:11:50 PM PST 24
Finished Feb 29 01:13:08 PM PST 24
Peak memory 239684 kb
Host smart-4defe56b-6d5d-47fe-be1f-3f49d07f12f7
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3064414047 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_
corrupt_sig_fatal_chk.3064414047
Directory /workspace/18.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_same_csr_outstanding.717103903
Short name T95
Test name
Test status
Simulation time 1493377789 ps
CPU time 14.11 seconds
Started Feb 29 12:45:55 PM PST 24
Finished Feb 29 12:46:10 PM PST 24
Peak memory 210584 kb
Host smart-8c1c3ed3-b8f5-41f4-aaf0-ca4ef4905da0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=717103903 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_c
trl_same_csr_outstanding.717103903
Directory /workspace/10.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/default/17.rom_ctrl_smoke.4239146182
Short name T97
Test name
Test status
Simulation time 1899709132 ps
CPU time 24 seconds
Started Feb 29 01:11:43 PM PST 24
Finished Feb 29 01:12:07 PM PST 24
Peak memory 211576 kb
Host smart-be581f1f-8767-4a9a-ad14-4fcde7de315f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4239146182 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_smoke.4239146182
Directory /workspace/17.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/2.rom_ctrl_stress_all.2530762658
Short name T7
Test name
Test status
Simulation time 14795585923 ps
CPU time 71.72 seconds
Started Feb 29 01:11:28 PM PST 24
Finished Feb 29 01:12:40 PM PST 24
Peak memory 219300 kb
Host smart-b216ea60-2a43-467d-96dc-feb1790b4e66
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2530762658 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 2.rom_ctrl_stress_all.2530762658
Directory /workspace/2.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/15.rom_ctrl_stress_all_with_rand_reset.4151320487
Short name T17
Test name
Test status
Simulation time 175181920532 ps
CPU time 5807.83 seconds
Started Feb 29 01:11:40 PM PST 24
Finished Feb 29 02:48:28 PM PST 24
Peak memory 236100 kb
Host smart-ec12d0bb-8f49-4b07-9641-2842b898a6de
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4151320487 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_stress_all_with_rand_reset.4151320487
Directory /workspace/15.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_aliasing.1059699982
Short name T70
Test name
Test status
Simulation time 23002812058 ps
CPU time 15.22 seconds
Started Feb 29 12:45:21 PM PST 24
Finished Feb 29 12:45:37 PM PST 24
Peak memory 210864 kb
Host smart-181f14e7-4448-4585-9b63-b473ecc1d795
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1059699982 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_alia
sing.1059699982
Directory /workspace/0.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_bit_bash.2094358643
Short name T401
Test name
Test status
Simulation time 3662341849 ps
CPU time 16.76 seconds
Started Feb 29 12:45:24 PM PST 24
Finished Feb 29 12:45:47 PM PST 24
Peak memory 210552 kb
Host smart-712d5e05-a39e-4ea4-9e45-bb634c1cf088
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2094358643 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_bit_
bash.2094358643
Directory /workspace/0.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_hw_reset.978656322
Short name T73
Test name
Test status
Simulation time 93645790 ps
CPU time 7.32 seconds
Started Feb 29 12:45:22 PM PST 24
Finished Feb 29 12:45:29 PM PST 24
Peak memory 210800 kb
Host smart-eac2cd5d-165c-4637-ae74-0e435ee92863
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=978656322 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_hw_re
set.978656322
Directory /workspace/0.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_mem_rw_with_rand_reset.3427065785
Short name T453
Test name
Test status
Simulation time 2992005299 ps
CPU time 12.99 seconds
Started Feb 29 12:45:25 PM PST 24
Finished Feb 29 12:45:38 PM PST 24
Peak memory 218984 kb
Host smart-641da62d-fa42-40fb-b3b6-37e7af79f4a9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3427065785 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 0.rom_ctrl_csr_mem_rw_with_rand_reset.3427065785
Directory /workspace/0.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_rw.3759424739
Short name T57
Test name
Test status
Simulation time 6133984277 ps
CPU time 13.22 seconds
Started Feb 29 12:45:21 PM PST 24
Finished Feb 29 12:45:34 PM PST 24
Peak memory 210876 kb
Host smart-c109d541-c99b-4270-8468-5272eb352f9a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3759424739 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_rw.3759424739
Directory /workspace/0.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_partial_access.4180912723
Short name T402
Test name
Test status
Simulation time 1668105503 ps
CPU time 13.62 seconds
Started Feb 29 12:45:24 PM PST 24
Finished Feb 29 12:45:38 PM PST 24
Peak memory 210536 kb
Host smart-06f521d7-ab74-4b08-9399-5690945c0d1f
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4180912723 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctr
l_mem_partial_access.4180912723
Directory /workspace/0.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_walk.1322260645
Short name T389
Test name
Test status
Simulation time 1056005648 ps
CPU time 10.47 seconds
Started Feb 29 12:45:24 PM PST 24
Finished Feb 29 12:45:35 PM PST 24
Peak memory 210472 kb
Host smart-33c31a61-30df-4ed1-8bee-f159e8e74be7
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1322260645 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_mem_walk
.1322260645
Directory /workspace/0.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_passthru_mem_tl_intg_err.2488892024
Short name T437
Test name
Test status
Simulation time 39642601000 ps
CPU time 84.2 seconds
Started Feb 29 12:45:22 PM PST 24
Finished Feb 29 12:46:46 PM PST 24
Peak memory 210516 kb
Host smart-037feafd-108b-4bbb-8d32-2fa6fd5e14dc
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2488892024 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_pa
ssthru_mem_tl_intg_err.2488892024
Directory /workspace/0.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_same_csr_outstanding.291737035
Short name T438
Test name
Test status
Simulation time 1818981347 ps
CPU time 14.47 seconds
Started Feb 29 12:45:20 PM PST 24
Finished Feb 29 12:45:35 PM PST 24
Peak memory 210872 kb
Host smart-ff00ae19-1e43-4736-b017-50d24212e1e7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=291737035 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ct
rl_same_csr_outstanding.291737035
Directory /workspace/0.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_errors.3895669592
Short name T399
Test name
Test status
Simulation time 1424326194 ps
CPU time 8.92 seconds
Started Feb 29 12:45:21 PM PST 24
Finished Feb 29 12:45:31 PM PST 24
Peak memory 214552 kb
Host smart-91a8adca-fe41-410b-a981-58027bf4bcdd
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3895669592 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_tl_errors.3895669592
Directory /workspace/0.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_intg_err.1549846519
Short name T459
Test name
Test status
Simulation time 1573671139 ps
CPU time 69.89 seconds
Started Feb 29 12:45:22 PM PST 24
Finished Feb 29 12:46:32 PM PST 24
Peak memory 210448 kb
Host smart-e7c00c1a-f9b1-449c-8b36-03fbff42bd2d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1549846519 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_tl_in
tg_err.1549846519
Directory /workspace/0.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_aliasing.2943893760
Short name T422
Test name
Test status
Simulation time 3693258699 ps
CPU time 14.84 seconds
Started Feb 29 12:45:36 PM PST 24
Finished Feb 29 12:45:51 PM PST 24
Peak memory 210600 kb
Host smart-cd7f8aa9-8a84-4379-a10e-8d5bb492ac5f
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2943893760 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_alia
sing.2943893760
Directory /workspace/1.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_bit_bash.2062206969
Short name T420
Test name
Test status
Simulation time 8213656366 ps
CPU time 12.13 seconds
Started Feb 29 12:45:39 PM PST 24
Finished Feb 29 12:45:52 PM PST 24
Peak memory 210676 kb
Host smart-36714108-b13a-4987-9f7d-02ae45e6eecd
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2062206969 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_bit_
bash.2062206969
Directory /workspace/1.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_hw_reset.415820847
Short name T62
Test name
Test status
Simulation time 94368649 ps
CPU time 7.4 seconds
Started Feb 29 12:45:32 PM PST 24
Finished Feb 29 12:45:39 PM PST 24
Peak memory 210512 kb
Host smart-b0be02b0-a607-40b8-a458-0c94cefa32e1
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=415820847 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_hw_re
set.415820847
Directory /workspace/1.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_mem_rw_with_rand_reset.1856456156
Short name T451
Test name
Test status
Simulation time 222881786 ps
CPU time 6.28 seconds
Started Feb 29 12:46:00 PM PST 24
Finished Feb 29 12:46:09 PM PST 24
Peak memory 212876 kb
Host smart-35912338-3269-46ef-b41d-8838f1758e11
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1856456156 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 1.rom_ctrl_csr_mem_rw_with_rand_reset.1856456156
Directory /workspace/1.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_rw.381162713
Short name T78
Test name
Test status
Simulation time 2188728584 ps
CPU time 16.9 seconds
Started Feb 29 12:45:48 PM PST 24
Finished Feb 29 12:46:05 PM PST 24
Peak memory 210628 kb
Host smart-a6452420-4f73-4ea4-a9d3-eb7b633bdc3b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=381162713 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_rw.381162713
Directory /workspace/1.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_partial_access.2428309634
Short name T393
Test name
Test status
Simulation time 4086074085 ps
CPU time 9.7 seconds
Started Feb 29 12:45:50 PM PST 24
Finished Feb 29 12:46:00 PM PST 24
Peak memory 210652 kb
Host smart-e45400bf-0d2e-4f04-9493-612bb0d66fed
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2428309634 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctr
l_mem_partial_access.2428309634
Directory /workspace/1.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_walk.938454990
Short name T425
Test name
Test status
Simulation time 2486515020 ps
CPU time 7.95 seconds
Started Feb 29 12:45:38 PM PST 24
Finished Feb 29 12:45:46 PM PST 24
Peak memory 210480 kb
Host smart-1f09297c-a292-4ad3-a53d-eac78fd7eb9b
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=938454990 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_mem_walk.
938454990
Directory /workspace/1.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_passthru_mem_tl_intg_err.231295877
Short name T443
Test name
Test status
Simulation time 378796327 ps
CPU time 18.7 seconds
Started Feb 29 12:45:24 PM PST 24
Finished Feb 29 12:45:43 PM PST 24
Peak memory 210504 kb
Host smart-c62e4934-b462-4722-9abf-02b0520cec4f
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=231295877 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_pas
sthru_mem_tl_intg_err.231295877
Directory /workspace/1.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_same_csr_outstanding.898826424
Short name T415
Test name
Test status
Simulation time 173682871 ps
CPU time 5.54 seconds
Started Feb 29 12:45:42 PM PST 24
Finished Feb 29 12:45:48 PM PST 24
Peak memory 210632 kb
Host smart-9184fc0a-6435-4048-b3c8-c963186c11df
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=898826424 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ct
rl_same_csr_outstanding.898826424
Directory /workspace/1.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_errors.292436781
Short name T458
Test name
Test status
Simulation time 291386939 ps
CPU time 8.67 seconds
Started Feb 29 12:45:24 PM PST 24
Finished Feb 29 12:45:33 PM PST 24
Peak memory 214652 kb
Host smart-1aa5db46-b071-4185-a166-28d8cb88516c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=292436781 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_tl_errors.292436781
Directory /workspace/1.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_intg_err.3564537281
Short name T111
Test name
Test status
Simulation time 3740066431 ps
CPU time 73.68 seconds
Started Feb 29 12:45:34 PM PST 24
Finished Feb 29 12:46:48 PM PST 24
Peak memory 211364 kb
Host smart-fe06fe7f-32fa-44dd-b138-b1e68f66bfe0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3564537281 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_tl_in
tg_err.3564537281
Directory /workspace/1.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_mem_rw_with_rand_reset.2364172285
Short name T377
Test name
Test status
Simulation time 1545240827 ps
CPU time 13.11 seconds
Started Feb 29 12:45:52 PM PST 24
Finished Feb 29 12:46:05 PM PST 24
Peak memory 214444 kb
Host smart-40bf3acb-6336-4404-a552-2dc416d63ecb
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2364172285 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 10.rom_ctrl_csr_mem_rw_with_rand_reset.2364172285
Directory /workspace/10.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_rw.1631109154
Short name T405
Test name
Test status
Simulation time 85707312 ps
CPU time 4.22 seconds
Started Feb 29 12:45:57 PM PST 24
Finished Feb 29 12:46:04 PM PST 24
Peak memory 210612 kb
Host smart-c3f81a64-411a-4a8b-9e71-c0b69d890a45
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1631109154 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_csr_rw.1631109154
Directory /workspace/10.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_passthru_mem_tl_intg_err.1823638930
Short name T74
Test name
Test status
Simulation time 9779589443 ps
CPU time 32.73 seconds
Started Feb 29 12:45:42 PM PST 24
Finished Feb 29 12:46:15 PM PST 24
Peak memory 210592 kb
Host smart-13028aac-b45b-4dae-bd16-22d6488517cd
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1823638930 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_p
assthru_mem_tl_intg_err.1823638930
Directory /workspace/10.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_errors.1633867772
Short name T380
Test name
Test status
Simulation time 1942279403 ps
CPU time 12.5 seconds
Started Feb 29 12:46:00 PM PST 24
Finished Feb 29 12:46:15 PM PST 24
Peak memory 214892 kb
Host smart-00e2922b-b679-498b-a271-45bd052f075f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1633867772 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_tl_errors.1633867772
Directory /workspace/10.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_intg_err.1177179181
Short name T116
Test name
Test status
Simulation time 12155728620 ps
CPU time 72.5 seconds
Started Feb 29 12:45:55 PM PST 24
Finished Feb 29 12:47:08 PM PST 24
Peak memory 210640 kb
Host smart-670f4035-4545-4b2e-ab2f-d7800d21ec6f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1177179181 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_tl_i
ntg_err.1177179181
Directory /workspace/10.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_mem_rw_with_rand_reset.3998846310
Short name T395
Test name
Test status
Simulation time 2001641720 ps
CPU time 15 seconds
Started Feb 29 12:45:57 PM PST 24
Finished Feb 29 12:46:14 PM PST 24
Peak memory 212336 kb
Host smart-74cce0ac-c8f9-4252-ae38-935e0acdc976
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3998846310 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 11.rom_ctrl_csr_mem_rw_with_rand_reset.3998846310
Directory /workspace/11.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_rw.1607345253
Short name T63
Test name
Test status
Simulation time 2606387002 ps
CPU time 12.23 seconds
Started Feb 29 12:45:56 PM PST 24
Finished Feb 29 12:46:10 PM PST 24
Peak memory 210640 kb
Host smart-396b9126-6eb5-47c2-999d-269425e70ade
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1607345253 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_csr_rw.1607345253
Directory /workspace/11.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_same_csr_outstanding.3379195074
Short name T467
Test name
Test status
Simulation time 702870972 ps
CPU time 8.92 seconds
Started Feb 29 12:46:06 PM PST 24
Finished Feb 29 12:46:15 PM PST 24
Peak memory 210596 kb
Host smart-176ecea4-bc06-4e47-91eb-876782430bc5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3379195074 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_
ctrl_same_csr_outstanding.3379195074
Directory /workspace/11.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_errors.1815656470
Short name T421
Test name
Test status
Simulation time 7910048253 ps
CPU time 13.34 seconds
Started Feb 29 12:45:57 PM PST 24
Finished Feb 29 12:46:12 PM PST 24
Peak memory 215308 kb
Host smart-6729dad8-8be9-4805-8250-f02768aaf56c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1815656470 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_tl_errors.1815656470
Directory /workspace/11.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_mem_rw_with_rand_reset.2979508344
Short name T417
Test name
Test status
Simulation time 522937404 ps
CPU time 6.07 seconds
Started Feb 29 12:45:57 PM PST 24
Finished Feb 29 12:46:04 PM PST 24
Peak memory 212320 kb
Host smart-e88fa9e5-7809-4984-8ba5-a6a526b210f5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2979508344 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 12.rom_ctrl_csr_mem_rw_with_rand_reset.2979508344
Directory /workspace/12.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_rw.1443722749
Short name T469
Test name
Test status
Simulation time 1445166671 ps
CPU time 11.94 seconds
Started Feb 29 12:46:01 PM PST 24
Finished Feb 29 12:46:15 PM PST 24
Peak memory 210296 kb
Host smart-f0495aaf-219b-42c1-8298-51f0958dad68
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1443722749 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_csr_rw.1443722749
Directory /workspace/12.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_same_csr_outstanding.2186851334
Short name T430
Test name
Test status
Simulation time 1573106025 ps
CPU time 13.26 seconds
Started Feb 29 12:45:56 PM PST 24
Finished Feb 29 12:46:10 PM PST 24
Peak memory 210616 kb
Host smart-56c213be-3012-48c7-8154-fadd664bac75
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2186851334 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_
ctrl_same_csr_outstanding.2186851334
Directory /workspace/12.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_errors.1566809854
Short name T426
Test name
Test status
Simulation time 1724496639 ps
CPU time 16.19 seconds
Started Feb 29 12:46:04 PM PST 24
Finished Feb 29 12:46:21 PM PST 24
Peak memory 214868 kb
Host smart-d31f1a6b-150e-4f37-aecc-bb7323778282
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1566809854 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_tl_errors.1566809854
Directory /workspace/12.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_intg_err.2121073524
Short name T112
Test name
Test status
Simulation time 1629766249 ps
CPU time 39.75 seconds
Started Feb 29 12:46:02 PM PST 24
Finished Feb 29 12:46:43 PM PST 24
Peak memory 210972 kb
Host smart-953554d0-e02d-40b0-aece-d5fd6e8a3eaf
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2121073524 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_tl_i
ntg_err.2121073524
Directory /workspace/12.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_mem_rw_with_rand_reset.3310894590
Short name T392
Test name
Test status
Simulation time 3253008378 ps
CPU time 13.69 seconds
Started Feb 29 12:46:03 PM PST 24
Finished Feb 29 12:46:17 PM PST 24
Peak memory 212272 kb
Host smart-8e3ce823-2047-422d-8104-80a87f26e3db
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3310894590 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 13.rom_ctrl_csr_mem_rw_with_rand_reset.3310894590
Directory /workspace/13.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_rw.4157905795
Short name T71
Test name
Test status
Simulation time 1309377234 ps
CPU time 10.53 seconds
Started Feb 29 12:46:00 PM PST 24
Finished Feb 29 12:46:13 PM PST 24
Peak memory 210564 kb
Host smart-1fb4ef49-52a8-4336-8f92-921ab190edc5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4157905795 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_csr_rw.4157905795
Directory /workspace/13.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_passthru_mem_tl_intg_err.3551040976
Short name T59
Test name
Test status
Simulation time 8655107079 ps
CPU time 67.04 seconds
Started Feb 29 12:45:46 PM PST 24
Finished Feb 29 12:46:54 PM PST 24
Peak memory 210608 kb
Host smart-f0fbf045-e2bd-4280-8212-00c1dc1a63da
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3551040976 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_p
assthru_mem_tl_intg_err.3551040976
Directory /workspace/13.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_same_csr_outstanding.3688628200
Short name T52
Test name
Test status
Simulation time 171671171 ps
CPU time 4.34 seconds
Started Feb 29 12:45:51 PM PST 24
Finished Feb 29 12:45:55 PM PST 24
Peak memory 210588 kb
Host smart-56478c5d-1ff7-46d7-b888-e400048ca44f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3688628200 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_
ctrl_same_csr_outstanding.3688628200
Directory /workspace/13.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_errors.1488867859
Short name T454
Test name
Test status
Simulation time 334323219 ps
CPU time 7.94 seconds
Started Feb 29 12:46:07 PM PST 24
Finished Feb 29 12:46:15 PM PST 24
Peak memory 215024 kb
Host smart-f44ed15e-a894-4051-828d-f5bdc00ab09e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1488867859 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_tl_errors.1488867859
Directory /workspace/13.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_intg_err.1209577049
Short name T431
Test name
Test status
Simulation time 688743306 ps
CPU time 36.46 seconds
Started Feb 29 12:45:56 PM PST 24
Finished Feb 29 12:46:34 PM PST 24
Peak memory 210624 kb
Host smart-4230d3cb-01e9-4ea6-a6c8-170e2636d22d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1209577049 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_tl_i
ntg_err.1209577049
Directory /workspace/13.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_mem_rw_with_rand_reset.2939322026
Short name T379
Test name
Test status
Simulation time 1194570803 ps
CPU time 7.33 seconds
Started Feb 29 12:46:05 PM PST 24
Finished Feb 29 12:46:13 PM PST 24
Peak memory 214504 kb
Host smart-147f5df0-b870-4179-97a4-20ee66b87171
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2939322026 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 14.rom_ctrl_csr_mem_rw_with_rand_reset.2939322026
Directory /workspace/14.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_rw.545422844
Short name T418
Test name
Test status
Simulation time 4067134959 ps
CPU time 8.72 seconds
Started Feb 29 12:45:50 PM PST 24
Finished Feb 29 12:45:58 PM PST 24
Peak memory 210620 kb
Host smart-af819333-f1ff-4829-bfea-acbcaab0a5c0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=545422844 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_csr_rw.545422844
Directory /workspace/14.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_passthru_mem_tl_intg_err.2922904137
Short name T76
Test name
Test status
Simulation time 3498771203 ps
CPU time 49.36 seconds
Started Feb 29 12:46:06 PM PST 24
Finished Feb 29 12:46:56 PM PST 24
Peak memory 210592 kb
Host smart-e366e452-a190-4b8d-88e3-cdeefb470975
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2922904137 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_p
assthru_mem_tl_intg_err.2922904137
Directory /workspace/14.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_same_csr_outstanding.3298083061
Short name T94
Test name
Test status
Simulation time 2085212529 ps
CPU time 16.52 seconds
Started Feb 29 12:46:05 PM PST 24
Finished Feb 29 12:46:22 PM PST 24
Peak memory 210608 kb
Host smart-09901eef-d866-439e-82f1-864feee7c677
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3298083061 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_
ctrl_same_csr_outstanding.3298083061
Directory /workspace/14.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_errors.3875912842
Short name T463
Test name
Test status
Simulation time 2145380374 ps
CPU time 19.96 seconds
Started Feb 29 12:46:11 PM PST 24
Finished Feb 29 12:46:33 PM PST 24
Peak memory 214940 kb
Host smart-a8a978d6-00b5-4f97-93a7-a0712a42f6dd
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3875912842 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_tl_errors.3875912842
Directory /workspace/14.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_intg_err.2231095240
Short name T110
Test name
Test status
Simulation time 171113192 ps
CPU time 37.55 seconds
Started Feb 29 12:46:04 PM PST 24
Finished Feb 29 12:46:42 PM PST 24
Peak memory 210592 kb
Host smart-c5fb3dd4-7122-4411-9358-bc399d29ace4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2231095240 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_tl_i
ntg_err.2231095240
Directory /workspace/14.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_mem_rw_with_rand_reset.4070688867
Short name T441
Test name
Test status
Simulation time 1632928878 ps
CPU time 13.67 seconds
Started Feb 29 12:46:06 PM PST 24
Finished Feb 29 12:46:20 PM PST 24
Peak memory 215312 kb
Host smart-88f047c5-cbfd-4053-9a6c-c1470f92bda9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4070688867 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 15.rom_ctrl_csr_mem_rw_with_rand_reset.4070688867
Directory /workspace/15.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_rw.3086109193
Short name T80
Test name
Test status
Simulation time 3933674275 ps
CPU time 15.17 seconds
Started Feb 29 12:46:08 PM PST 24
Finished Feb 29 12:46:23 PM PST 24
Peak memory 210640 kb
Host smart-2264c591-9208-4257-8851-c95c6cfe1b7b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3086109193 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_csr_rw.3086109193
Directory /workspace/15.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_passthru_mem_tl_intg_err.4132793761
Short name T77
Test name
Test status
Simulation time 12865003259 ps
CPU time 95.88 seconds
Started Feb 29 12:45:53 PM PST 24
Finished Feb 29 12:47:30 PM PST 24
Peak memory 210612 kb
Host smart-c87e79f8-3076-4095-bd2b-b243de872e2a
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4132793761 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_p
assthru_mem_tl_intg_err.4132793761
Directory /workspace/15.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_same_csr_outstanding.762667925
Short name T424
Test name
Test status
Simulation time 780332692 ps
CPU time 10.68 seconds
Started Feb 29 12:46:02 PM PST 24
Finished Feb 29 12:46:14 PM PST 24
Peak memory 210588 kb
Host smart-441e5380-6c9c-497f-9fa1-369e272ffe03
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=762667925 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_c
trl_same_csr_outstanding.762667925
Directory /workspace/15.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_errors.1242086812
Short name T408
Test name
Test status
Simulation time 8590192001 ps
CPU time 18.71 seconds
Started Feb 29 12:46:01 PM PST 24
Finished Feb 29 12:46:21 PM PST 24
Peak memory 216468 kb
Host smart-a4df46d2-bfca-4d3e-9e0d-99dfe5ed5f70
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1242086812 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_tl_errors.1242086812
Directory /workspace/15.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_intg_err.1628377605
Short name T448
Test name
Test status
Simulation time 8468953592 ps
CPU time 47.64 seconds
Started Feb 29 12:46:03 PM PST 24
Finished Feb 29 12:46:51 PM PST 24
Peak memory 211500 kb
Host smart-bf3a71a2-2fc7-4791-995d-e8ba3cfc965b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1628377605 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_tl_i
ntg_err.1628377605
Directory /workspace/15.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_mem_rw_with_rand_reset.1977739007
Short name T412
Test name
Test status
Simulation time 188096503 ps
CPU time 4.42 seconds
Started Feb 29 12:46:02 PM PST 24
Finished Feb 29 12:46:07 PM PST 24
Peak memory 212684 kb
Host smart-04f6e69b-05a6-4d3b-aa4d-8c441cdaa7e8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1977739007 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 16.rom_ctrl_csr_mem_rw_with_rand_reset.1977739007
Directory /workspace/16.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_rw.2200694443
Short name T386
Test name
Test status
Simulation time 1658215474 ps
CPU time 4.28 seconds
Started Feb 29 12:45:53 PM PST 24
Finished Feb 29 12:45:58 PM PST 24
Peak memory 210632 kb
Host smart-95e4d2c6-2aa9-4013-9d95-8625026f489d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2200694443 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_csr_rw.2200694443
Directory /workspace/16.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_passthru_mem_tl_intg_err.2385016003
Short name T64
Test name
Test status
Simulation time 9541636681 ps
CPU time 82.71 seconds
Started Feb 29 12:46:18 PM PST 24
Finished Feb 29 12:47:41 PM PST 24
Peak memory 210596 kb
Host smart-45dc0fd6-63fc-494c-b5a5-3ff7436dd82a
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2385016003 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_p
assthru_mem_tl_intg_err.2385016003
Directory /workspace/16.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_same_csr_outstanding.4181251563
Short name T406
Test name
Test status
Simulation time 3258857865 ps
CPU time 10 seconds
Started Feb 29 12:46:21 PM PST 24
Finished Feb 29 12:46:31 PM PST 24
Peak memory 210644 kb
Host smart-464a544f-f987-4f49-ae3c-9a8a5b3e2328
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4181251563 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_
ctrl_same_csr_outstanding.4181251563
Directory /workspace/16.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_errors.2761710609
Short name T434
Test name
Test status
Simulation time 6109278803 ps
CPU time 13.32 seconds
Started Feb 29 12:46:01 PM PST 24
Finished Feb 29 12:46:16 PM PST 24
Peak memory 215372 kb
Host smart-f558f0d6-5304-437f-8b32-833a13ce76f3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2761710609 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_tl_errors.2761710609
Directory /workspace/16.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_intg_err.1135104944
Short name T114
Test name
Test status
Simulation time 2012280631 ps
CPU time 76.67 seconds
Started Feb 29 12:45:37 PM PST 24
Finished Feb 29 12:46:54 PM PST 24
Peak memory 211088 kb
Host smart-3ede6fe9-02a5-45b2-9f1d-5dd140d4bab4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1135104944 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_tl_i
ntg_err.1135104944
Directory /workspace/16.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_mem_rw_with_rand_reset.529705867
Short name T460
Test name
Test status
Simulation time 739062241 ps
CPU time 5.78 seconds
Started Feb 29 12:45:41 PM PST 24
Finished Feb 29 12:45:48 PM PST 24
Peak memory 215396 kb
Host smart-3319ee9b-4230-445d-9ed3-5f2512d024b7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=529705867 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 17.rom_ctrl_csr_mem_rw_with_rand_reset.529705867
Directory /workspace/17.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_rw.3920747549
Short name T99
Test name
Test status
Simulation time 970598084 ps
CPU time 9.73 seconds
Started Feb 29 12:45:36 PM PST 24
Finished Feb 29 12:45:46 PM PST 24
Peak memory 210560 kb
Host smart-de7540c1-f46b-47f2-b7fc-360909887947
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3920747549 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_csr_rw.3920747549
Directory /workspace/17.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_passthru_mem_tl_intg_err.3573269049
Short name T106
Test name
Test status
Simulation time 8272343253 ps
CPU time 31.78 seconds
Started Feb 29 12:45:57 PM PST 24
Finished Feb 29 12:46:31 PM PST 24
Peak memory 210684 kb
Host smart-ee36f1f8-67b0-4949-ae0a-290aaae38128
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3573269049 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_p
assthru_mem_tl_intg_err.3573269049
Directory /workspace/17.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_same_csr_outstanding.697268846
Short name T432
Test name
Test status
Simulation time 1420511627 ps
CPU time 8.41 seconds
Started Feb 29 12:45:38 PM PST 24
Finished Feb 29 12:45:46 PM PST 24
Peak memory 210748 kb
Host smart-9a82faa7-881c-42fe-85c0-a59824402c36
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=697268846 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_c
trl_same_csr_outstanding.697268846
Directory /workspace/17.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_errors.3313267392
Short name T390
Test name
Test status
Simulation time 6098940625 ps
CPU time 18.19 seconds
Started Feb 29 12:45:38 PM PST 24
Finished Feb 29 12:45:57 PM PST 24
Peak memory 216516 kb
Host smart-040c7dd7-40f7-4ff2-bf3a-0871ce4f3df7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3313267392 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_tl_errors.3313267392
Directory /workspace/17.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_mem_rw_with_rand_reset.2494947039
Short name T385
Test name
Test status
Simulation time 1217001595 ps
CPU time 8.46 seconds
Started Feb 29 12:45:57 PM PST 24
Finished Feb 29 12:46:07 PM PST 24
Peak memory 214740 kb
Host smart-a85113c0-f08e-440f-a8fa-955d68ddad7f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2494947039 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 18.rom_ctrl_csr_mem_rw_with_rand_reset.2494947039
Directory /workspace/18.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_rw.470359279
Short name T398
Test name
Test status
Simulation time 86685530 ps
CPU time 4.21 seconds
Started Feb 29 12:45:57 PM PST 24
Finished Feb 29 12:46:03 PM PST 24
Peak memory 210580 kb
Host smart-e1733c93-1740-496a-a69b-68e965f4f664
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=470359279 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_csr_rw.470359279
Directory /workspace/18.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_passthru_mem_tl_intg_err.2184408116
Short name T58
Test name
Test status
Simulation time 699649584 ps
CPU time 22.75 seconds
Started Feb 29 12:46:01 PM PST 24
Finished Feb 29 12:46:25 PM PST 24
Peak memory 210564 kb
Host smart-d42158e9-338c-42db-bcac-68f33f1b4215
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2184408116 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_p
assthru_mem_tl_intg_err.2184408116
Directory /workspace/18.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_same_csr_outstanding.3302741812
Short name T446
Test name
Test status
Simulation time 347469826 ps
CPU time 4.24 seconds
Started Feb 29 12:46:06 PM PST 24
Finished Feb 29 12:46:10 PM PST 24
Peak memory 210632 kb
Host smart-31f4fb93-d3d4-4719-8d8c-0d055a7643c0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3302741812 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_
ctrl_same_csr_outstanding.3302741812
Directory /workspace/18.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_errors.3506208288
Short name T435
Test name
Test status
Simulation time 2139411162 ps
CPU time 12.62 seconds
Started Feb 29 12:45:35 PM PST 24
Finished Feb 29 12:45:48 PM PST 24
Peak memory 213472 kb
Host smart-0cb597e2-f3a2-4a27-8fde-7cc8e63ee579
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3506208288 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_tl_errors.3506208288
Directory /workspace/18.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_intg_err.1211445851
Short name T436
Test name
Test status
Simulation time 7534699180 ps
CPU time 75.48 seconds
Started Feb 29 12:45:39 PM PST 24
Finished Feb 29 12:47:00 PM PST 24
Peak memory 212672 kb
Host smart-cc9fb220-764f-44d6-b391-f49db9cc97d3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1211445851 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_tl_i
ntg_err.1211445851
Directory /workspace/18.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_mem_rw_with_rand_reset.4172129207
Short name T461
Test name
Test status
Simulation time 4785856928 ps
CPU time 12.33 seconds
Started Feb 29 12:45:56 PM PST 24
Finished Feb 29 12:46:09 PM PST 24
Peak memory 216148 kb
Host smart-f21015a4-82b4-41c5-a3ee-7d9297ff86db
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4172129207 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 19.rom_ctrl_csr_mem_rw_with_rand_reset.4172129207
Directory /workspace/19.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_rw.3607192702
Short name T470
Test name
Test status
Simulation time 1004639035 ps
CPU time 8.77 seconds
Started Feb 29 12:46:01 PM PST 24
Finished Feb 29 12:46:11 PM PST 24
Peak memory 210576 kb
Host smart-97a309c1-6ee2-450f-aeb6-33c98a86d5be
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3607192702 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_csr_rw.3607192702
Directory /workspace/19.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_passthru_mem_tl_intg_err.2725164297
Short name T51
Test name
Test status
Simulation time 3952275802 ps
CPU time 42.88 seconds
Started Feb 29 12:45:57 PM PST 24
Finished Feb 29 12:46:41 PM PST 24
Peak memory 210636 kb
Host smart-6072c633-edd9-49d2-bbaf-8746e739160d
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2725164297 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_p
assthru_mem_tl_intg_err.2725164297
Directory /workspace/19.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_same_csr_outstanding.62878782
Short name T93
Test name
Test status
Simulation time 456454696 ps
CPU time 7.23 seconds
Started Feb 29 12:45:50 PM PST 24
Finished Feb 29 12:45:57 PM PST 24
Peak memory 210636 kb
Host smart-257097ae-7d11-48ef-adb4-7272044b735b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=62878782 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ct
rl_same_csr_outstanding.62878782
Directory /workspace/19.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_errors.71612861
Short name T400
Test name
Test status
Simulation time 4571790610 ps
CPU time 14.17 seconds
Started Feb 29 12:45:56 PM PST 24
Finished Feb 29 12:46:11 PM PST 24
Peak memory 214232 kb
Host smart-37ad7df0-98ee-4c52-834c-f19ef5dabc41
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71612861 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_tl_errors.71612861
Directory /workspace/19.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_intg_err.2004028998
Short name T48
Test name
Test status
Simulation time 2059644550 ps
CPU time 45.35 seconds
Started Feb 29 12:45:56 PM PST 24
Finished Feb 29 12:46:43 PM PST 24
Peak memory 210864 kb
Host smart-0942b6db-8b4f-464f-8a96-e725b433ad9f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2004028998 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_tl_i
ntg_err.2004028998
Directory /workspace/19.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_aliasing.4156581729
Short name T100
Test name
Test status
Simulation time 836663997 ps
CPU time 9.34 seconds
Started Feb 29 12:45:45 PM PST 24
Finished Feb 29 12:45:55 PM PST 24
Peak memory 210584 kb
Host smart-34ff14f1-1bb0-46f7-bbe1-0299fc2e9386
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4156581729 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_alia
sing.4156581729
Directory /workspace/2.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_bit_bash.3373044531
Short name T427
Test name
Test status
Simulation time 3756902191 ps
CPU time 11.36 seconds
Started Feb 29 12:45:40 PM PST 24
Finished Feb 29 12:45:53 PM PST 24
Peak memory 210652 kb
Host smart-b10098f1-e661-40fb-86cf-c778ab9ef2e5
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3373044531 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_bit_
bash.3373044531
Directory /workspace/2.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_hw_reset.1800101032
Short name T411
Test name
Test status
Simulation time 6053058608 ps
CPU time 15.01 seconds
Started Feb 29 12:45:39 PM PST 24
Finished Feb 29 12:45:55 PM PST 24
Peak memory 210652 kb
Host smart-c4794c73-23e5-469f-bdc1-e13677e5b23e
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1800101032 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_hw_r
eset.1800101032
Directory /workspace/2.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_mem_rw_with_rand_reset.322145750
Short name T53
Test name
Test status
Simulation time 1270080754 ps
CPU time 11.89 seconds
Started Feb 29 12:45:39 PM PST 24
Finished Feb 29 12:45:52 PM PST 24
Peak memory 214256 kb
Host smart-21d3a635-19c4-4bd1-a531-70a900b6dc3e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=322145750 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 2.rom_ctrl_csr_mem_rw_with_rand_reset.322145750
Directory /workspace/2.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_rw.1297786044
Short name T79
Test name
Test status
Simulation time 89272438 ps
CPU time 4.26 seconds
Started Feb 29 12:46:06 PM PST 24
Finished Feb 29 12:46:10 PM PST 24
Peak memory 210632 kb
Host smart-6d156294-4024-458a-8620-3eddb97b58f8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1297786044 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_rw.1297786044
Directory /workspace/2.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_partial_access.2883386288
Short name T413
Test name
Test status
Simulation time 1652542353 ps
CPU time 4.14 seconds
Started Feb 29 12:45:53 PM PST 24
Finished Feb 29 12:45:58 PM PST 24
Peak memory 210608 kb
Host smart-25fe0928-c9b0-43da-a3ca-15d569b9e902
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2883386288 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctr
l_mem_partial_access.2883386288
Directory /workspace/2.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_walk.1450867738
Short name T387
Test name
Test status
Simulation time 7924708272 ps
CPU time 11.87 seconds
Started Feb 29 12:45:56 PM PST 24
Finished Feb 29 12:46:08 PM PST 24
Peak memory 210656 kb
Host smart-2721bc23-b5d6-4259-ab01-727295a7d2da
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1450867738 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_mem_walk
.1450867738
Directory /workspace/2.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_passthru_mem_tl_intg_err.3035676329
Short name T82
Test name
Test status
Simulation time 9651798130 ps
CPU time 34.21 seconds
Started Feb 29 12:45:51 PM PST 24
Finished Feb 29 12:46:26 PM PST 24
Peak memory 210612 kb
Host smart-5eeaa21e-45c5-49b5-874f-5fcaaf258701
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3035676329 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_pa
ssthru_mem_tl_intg_err.3035676329
Directory /workspace/2.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_same_csr_outstanding.1714452789
Short name T428
Test name
Test status
Simulation time 85864405 ps
CPU time 4.17 seconds
Started Feb 29 12:45:39 PM PST 24
Finished Feb 29 12:45:44 PM PST 24
Peak memory 210684 kb
Host smart-2128c244-54ca-4227-967e-847c1a2be79c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1714452789 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_c
trl_same_csr_outstanding.1714452789
Directory /workspace/2.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_errors.585382106
Short name T466
Test name
Test status
Simulation time 8332785530 ps
CPU time 19.91 seconds
Started Feb 29 12:45:53 PM PST 24
Finished Feb 29 12:46:13 PM PST 24
Peak memory 216292 kb
Host smart-e82ea2e9-e75f-4b14-afd9-724955515b52
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=585382106 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_tl_errors.585382106
Directory /workspace/2.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_intg_err.492875181
Short name T119
Test name
Test status
Simulation time 6773389635 ps
CPU time 42.25 seconds
Started Feb 29 12:45:50 PM PST 24
Finished Feb 29 12:46:32 PM PST 24
Peak memory 211636 kb
Host smart-b4709708-93e0-469a-93bb-a1f2a94c92cb
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=492875181 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_tl_int
g_err.492875181
Directory /workspace/2.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_aliasing.3508969583
Short name T98
Test name
Test status
Simulation time 411930840 ps
CPU time 6.9 seconds
Started Feb 29 12:45:57 PM PST 24
Finished Feb 29 12:46:05 PM PST 24
Peak memory 210552 kb
Host smart-18131f18-c6c3-49e9-aecd-9e03310db627
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3508969583 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_alia
sing.3508969583
Directory /workspace/3.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_bit_bash.148464076
Short name T455
Test name
Test status
Simulation time 333885216 ps
CPU time 4.56 seconds
Started Feb 29 12:45:55 PM PST 24
Finished Feb 29 12:46:00 PM PST 24
Peak memory 210596 kb
Host smart-881eeb76-27bf-4cef-8553-cac582e504dd
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=148464076 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_bit_b
ash.148464076
Directory /workspace/3.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_hw_reset.2477895183
Short name T452
Test name
Test status
Simulation time 1571739201 ps
CPU time 16.14 seconds
Started Feb 29 12:46:12 PM PST 24
Finished Feb 29 12:46:29 PM PST 24
Peak memory 210516 kb
Host smart-643fe558-e807-4045-8486-b5cfe2ad9ce8
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2477895183 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_hw_r
eset.2477895183
Directory /workspace/3.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_mem_rw_with_rand_reset.2604687183
Short name T414
Test name
Test status
Simulation time 1908329219 ps
CPU time 9.9 seconds
Started Feb 29 12:45:53 PM PST 24
Finished Feb 29 12:46:03 PM PST 24
Peak memory 213236 kb
Host smart-77b71d39-6dc6-4a68-ae27-654c0b52f69e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2604687183 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 3.rom_ctrl_csr_mem_rw_with_rand_reset.2604687183
Directory /workspace/3.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_rw.2931567555
Short name T442
Test name
Test status
Simulation time 2128509086 ps
CPU time 16.23 seconds
Started Feb 29 12:46:10 PM PST 24
Finished Feb 29 12:46:28 PM PST 24
Peak memory 210532 kb
Host smart-6d23795b-1538-4352-87d4-2b0d215705f2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2931567555 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_rw.2931567555
Directory /workspace/3.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_partial_access.883569706
Short name T456
Test name
Test status
Simulation time 171926521 ps
CPU time 4.07 seconds
Started Feb 29 12:45:52 PM PST 24
Finished Feb 29 12:46:02 PM PST 24
Peak memory 210572 kb
Host smart-07e74bb5-a31f-4955-aada-e3fb037035fc
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=883569706 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl
_mem_partial_access.883569706
Directory /workspace/3.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_walk.2409149556
Short name T376
Test name
Test status
Simulation time 24499393165 ps
CPU time 12.67 seconds
Started Feb 29 12:46:00 PM PST 24
Finished Feb 29 12:46:15 PM PST 24
Peak memory 210592 kb
Host smart-9bd6938a-57f2-4d33-92d9-ac9bbef25bc9
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2409149556 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_mem_walk
.2409149556
Directory /workspace/3.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_passthru_mem_tl_intg_err.3759015835
Short name T75
Test name
Test status
Simulation time 1137648785 ps
CPU time 27 seconds
Started Feb 29 12:45:39 PM PST 24
Finished Feb 29 12:46:07 PM PST 24
Peak memory 210604 kb
Host smart-d793e955-016e-4e0d-8c60-003f658e13df
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3759015835 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_pa
ssthru_mem_tl_intg_err.3759015835
Directory /workspace/3.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_same_csr_outstanding.50912516
Short name T409
Test name
Test status
Simulation time 131785255 ps
CPU time 5.12 seconds
Started Feb 29 12:46:06 PM PST 24
Finished Feb 29 12:46:18 PM PST 24
Peak memory 210688 kb
Host smart-2ab1b368-c11a-4e86-8d3b-7c94881df864
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=50912516 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctr
l_same_csr_outstanding.50912516
Directory /workspace/3.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_errors.2075934404
Short name T378
Test name
Test status
Simulation time 2011134366 ps
CPU time 18.1 seconds
Started Feb 29 12:45:56 PM PST 24
Finished Feb 29 12:46:15 PM PST 24
Peak memory 214900 kb
Host smart-b0647918-8231-4c86-9068-5c5d14d77df8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2075934404 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_tl_errors.2075934404
Directory /workspace/3.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_aliasing.81314844
Short name T433
Test name
Test status
Simulation time 1104946022 ps
CPU time 10.67 seconds
Started Feb 29 12:46:03 PM PST 24
Finished Feb 29 12:46:14 PM PST 24
Peak memory 210440 kb
Host smart-aafdd3e0-8a48-476e-ae90-a7eba8d7f07c
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=81314844 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_aliasi
ng.81314844
Directory /workspace/4.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_bit_bash.2120414690
Short name T403
Test name
Test status
Simulation time 3995917212 ps
CPU time 15.59 seconds
Started Feb 29 12:45:54 PM PST 24
Finished Feb 29 12:46:09 PM PST 24
Peak memory 210556 kb
Host smart-86ff27d7-5ac4-4a3f-85e7-33b1222eeb2b
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2120414690 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_bit_
bash.2120414690
Directory /workspace/4.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_hw_reset.2152432041
Short name T410
Test name
Test status
Simulation time 1075198160 ps
CPU time 10.57 seconds
Started Feb 29 12:46:03 PM PST 24
Finished Feb 29 12:46:14 PM PST 24
Peak memory 210424 kb
Host smart-032add45-635b-4285-b289-92fe6b959d4f
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2152432041 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_hw_r
eset.2152432041
Directory /workspace/4.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_mem_rw_with_rand_reset.642865890
Short name T381
Test name
Test status
Simulation time 32944703772 ps
CPU time 14.13 seconds
Started Feb 29 12:45:39 PM PST 24
Finished Feb 29 12:45:54 PM PST 24
Peak memory 213420 kb
Host smart-65d69cb5-75f8-4363-934a-f5dceb8d69fd
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=642865890 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 4.rom_ctrl_csr_mem_rw_with_rand_reset.642865890
Directory /workspace/4.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_rw.1869840915
Short name T440
Test name
Test status
Simulation time 30173411364 ps
CPU time 12.92 seconds
Started Feb 29 12:45:56 PM PST 24
Finished Feb 29 12:46:10 PM PST 24
Peak memory 210572 kb
Host smart-2ea46df6-57bd-4011-9c84-6187e519687f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1869840915 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_rw.1869840915
Directory /workspace/4.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_partial_access.2388859654
Short name T407
Test name
Test status
Simulation time 1487849104 ps
CPU time 6.47 seconds
Started Feb 29 12:45:59 PM PST 24
Finished Feb 29 12:46:06 PM PST 24
Peak memory 210500 kb
Host smart-a61a8598-b20e-4aa1-87fa-99513151e822
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2388859654 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctr
l_mem_partial_access.2388859654
Directory /workspace/4.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_walk.261596754
Short name T394
Test name
Test status
Simulation time 1185238201 ps
CPU time 11.59 seconds
Started Feb 29 12:45:39 PM PST 24
Finished Feb 29 12:45:52 PM PST 24
Peak memory 210552 kb
Host smart-f30a74e5-9c4f-4994-b64e-58ea24c39e9a
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=261596754 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_mem_walk.
261596754
Directory /workspace/4.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_passthru_mem_tl_intg_err.2074278704
Short name T105
Test name
Test status
Simulation time 4324392284 ps
CPU time 43.81 seconds
Started Feb 29 12:45:58 PM PST 24
Finished Feb 29 12:46:43 PM PST 24
Peak memory 210584 kb
Host smart-a6c677db-6195-4429-af59-e90b5d0cf42b
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2074278704 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_pa
ssthru_mem_tl_intg_err.2074278704
Directory /workspace/4.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_same_csr_outstanding.871902191
Short name T444
Test name
Test status
Simulation time 85755270 ps
CPU time 4.01 seconds
Started Feb 29 12:45:58 PM PST 24
Finished Feb 29 12:46:03 PM PST 24
Peak memory 210624 kb
Host smart-bc0a1146-d632-45fd-adca-0f54d54933f5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=871902191 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ct
rl_same_csr_outstanding.871902191
Directory /workspace/4.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_errors.3576944646
Short name T447
Test name
Test status
Simulation time 924369787 ps
CPU time 12.07 seconds
Started Feb 29 12:45:55 PM PST 24
Finished Feb 29 12:46:08 PM PST 24
Peak memory 214656 kb
Host smart-5b3a90c3-8b75-4993-aff6-2e18c52afd78
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3576944646 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_tl_errors.3576944646
Directory /workspace/4.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_mem_rw_with_rand_reset.3770303819
Short name T419
Test name
Test status
Simulation time 3398299913 ps
CPU time 13.8 seconds
Started Feb 29 12:45:59 PM PST 24
Finished Feb 29 12:46:15 PM PST 24
Peak memory 214640 kb
Host smart-78b763b3-2c85-4025-9800-88fb535278c0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3770303819 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 5.rom_ctrl_csr_mem_rw_with_rand_reset.3770303819
Directory /workspace/5.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_rw.3120303193
Short name T72
Test name
Test status
Simulation time 6022947959 ps
CPU time 10.01 seconds
Started Feb 29 12:46:03 PM PST 24
Finished Feb 29 12:46:13 PM PST 24
Peak memory 210600 kb
Host smart-c3fab689-e6cb-45d5-b0f9-13d9aae397f9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3120303193 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_csr_rw.3120303193
Directory /workspace/5.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_passthru_mem_tl_intg_err.4266130317
Short name T391
Test name
Test status
Simulation time 10753334845 ps
CPU time 51.2 seconds
Started Feb 29 12:45:42 PM PST 24
Finished Feb 29 12:46:33 PM PST 24
Peak memory 210632 kb
Host smart-a340e0a2-cd6b-42d4-b91f-a38d86354b3b
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4266130317 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_pa
ssthru_mem_tl_intg_err.4266130317
Directory /workspace/5.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_same_csr_outstanding.1995670383
Short name T96
Test name
Test status
Simulation time 639354906 ps
CPU time 4.25 seconds
Started Feb 29 12:45:48 PM PST 24
Finished Feb 29 12:45:52 PM PST 24
Peak memory 210588 kb
Host smart-269c0359-d643-40a3-a1b7-48be2383162a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1995670383 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_c
trl_same_csr_outstanding.1995670383
Directory /workspace/5.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_errors.1105281793
Short name T462
Test name
Test status
Simulation time 1863446333 ps
CPU time 16.96 seconds
Started Feb 29 12:46:07 PM PST 24
Finished Feb 29 12:46:24 PM PST 24
Peak memory 214712 kb
Host smart-c163501a-fd26-4a51-a102-58fd6f7601c3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1105281793 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_tl_errors.1105281793
Directory /workspace/5.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_intg_err.1140813624
Short name T109
Test name
Test status
Simulation time 163555986 ps
CPU time 36.96 seconds
Started Feb 29 12:46:07 PM PST 24
Finished Feb 29 12:46:44 PM PST 24
Peak memory 210924 kb
Host smart-3730fd0d-72f2-42f3-8588-52734aea00a2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1140813624 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_tl_in
tg_err.1140813624
Directory /workspace/5.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_mem_rw_with_rand_reset.3237715980
Short name T388
Test name
Test status
Simulation time 5554485865 ps
CPU time 8.95 seconds
Started Feb 29 12:45:54 PM PST 24
Finished Feb 29 12:46:04 PM PST 24
Peak memory 214408 kb
Host smart-e42e4c6b-d7b3-4f64-8d49-734be9f30881
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3237715980 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 6.rom_ctrl_csr_mem_rw_with_rand_reset.3237715980
Directory /workspace/6.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_rw.2277307581
Short name T397
Test name
Test status
Simulation time 89279430 ps
CPU time 4.23 seconds
Started Feb 29 12:45:54 PM PST 24
Finished Feb 29 12:45:59 PM PST 24
Peak memory 210652 kb
Host smart-cbaf3324-72ee-40bc-99bc-65560e1d195e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2277307581 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_csr_rw.2277307581
Directory /workspace/6.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_passthru_mem_tl_intg_err.2199755254
Short name T61
Test name
Test status
Simulation time 12385271896 ps
CPU time 62.53 seconds
Started Feb 29 12:46:05 PM PST 24
Finished Feb 29 12:47:08 PM PST 24
Peak memory 210588 kb
Host smart-8a8d92be-9cfc-4c27-8e29-8ca2551586d4
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2199755254 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_pa
ssthru_mem_tl_intg_err.2199755254
Directory /workspace/6.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_same_csr_outstanding.3886328516
Short name T423
Test name
Test status
Simulation time 940588617 ps
CPU time 10.06 seconds
Started Feb 29 12:45:51 PM PST 24
Finished Feb 29 12:46:01 PM PST 24
Peak memory 210696 kb
Host smart-f28d3190-68f2-4fdc-a844-fb391522fb71
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3886328516 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_c
trl_same_csr_outstanding.3886328516
Directory /workspace/6.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_errors.883539186
Short name T383
Test name
Test status
Simulation time 2242025012 ps
CPU time 21.44 seconds
Started Feb 29 12:46:22 PM PST 24
Finished Feb 29 12:46:44 PM PST 24
Peak memory 215100 kb
Host smart-eccdbf6b-2baa-4dbe-a884-9108bf241c2b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=883539186 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_tl_errors.883539186
Directory /workspace/6.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_intg_err.3612223864
Short name T450
Test name
Test status
Simulation time 12453612328 ps
CPU time 46.1 seconds
Started Feb 29 12:46:00 PM PST 24
Finished Feb 29 12:46:47 PM PST 24
Peak memory 211460 kb
Host smart-068cb978-1955-45fe-a87e-83a35faafe40
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3612223864 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_tl_in
tg_err.3612223864
Directory /workspace/6.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_mem_rw_with_rand_reset.4263117679
Short name T457
Test name
Test status
Simulation time 2140738141 ps
CPU time 16.42 seconds
Started Feb 29 12:46:16 PM PST 24
Finished Feb 29 12:46:34 PM PST 24
Peak memory 212708 kb
Host smart-b7e6169b-2c35-4ba9-aa7c-fe4aff7d2220
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4263117679 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 7.rom_ctrl_csr_mem_rw_with_rand_reset.4263117679
Directory /workspace/7.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_rw.3873109704
Short name T439
Test name
Test status
Simulation time 173856510 ps
CPU time 5.32 seconds
Started Feb 29 12:45:53 PM PST 24
Finished Feb 29 12:45:59 PM PST 24
Peak memory 210544 kb
Host smart-ac5c4f6b-5a29-4f9f-a0f6-d85151194e18
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3873109704 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_csr_rw.3873109704
Directory /workspace/7.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_passthru_mem_tl_intg_err.3830926720
Short name T445
Test name
Test status
Simulation time 8637562840 ps
CPU time 75.57 seconds
Started Feb 29 12:46:01 PM PST 24
Finished Feb 29 12:47:18 PM PST 24
Peak memory 210612 kb
Host smart-29ef5d65-2981-4261-99d5-f797884bda75
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3830926720 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_pa
ssthru_mem_tl_intg_err.3830926720
Directory /workspace/7.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_same_csr_outstanding.554544647
Short name T92
Test name
Test status
Simulation time 88434533 ps
CPU time 4.21 seconds
Started Feb 29 12:46:10 PM PST 24
Finished Feb 29 12:46:15 PM PST 24
Peak memory 210704 kb
Host smart-913fea16-2186-45a8-9116-ebfd514871a0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=554544647 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ct
rl_same_csr_outstanding.554544647
Directory /workspace/7.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_errors.1229213808
Short name T396
Test name
Test status
Simulation time 6385208390 ps
CPU time 14.97 seconds
Started Feb 29 12:46:02 PM PST 24
Finished Feb 29 12:46:18 PM PST 24
Peak memory 215380 kb
Host smart-8b7b491c-edc9-483c-8ab2-64a2a7864ab3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1229213808 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_tl_errors.1229213808
Directory /workspace/7.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_intg_err.1970188754
Short name T120
Test name
Test status
Simulation time 1260351608 ps
CPU time 43.37 seconds
Started Feb 29 12:46:21 PM PST 24
Finished Feb 29 12:47:05 PM PST 24
Peak memory 210584 kb
Host smart-dba49dc3-64b1-4a53-9b55-67bf2c49eac8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1970188754 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_tl_in
tg_err.1970188754
Directory /workspace/7.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_mem_rw_with_rand_reset.3443370629
Short name T471
Test name
Test status
Simulation time 180176422 ps
CPU time 4.49 seconds
Started Feb 29 12:45:50 PM PST 24
Finished Feb 29 12:45:55 PM PST 24
Peak memory 212076 kb
Host smart-7dcd9adc-c9f5-4e28-9c5b-f144f096cac3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3443370629 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 8.rom_ctrl_csr_mem_rw_with_rand_reset.3443370629
Directory /workspace/8.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_rw.1129994373
Short name T465
Test name
Test status
Simulation time 2096563850 ps
CPU time 9.45 seconds
Started Feb 29 12:45:56 PM PST 24
Finished Feb 29 12:46:07 PM PST 24
Peak memory 210576 kb
Host smart-29e93bea-982c-462e-8206-eb557f9fbbc2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1129994373 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_csr_rw.1129994373
Directory /workspace/8.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_passthru_mem_tl_intg_err.3522687046
Short name T81
Test name
Test status
Simulation time 5878370035 ps
CPU time 26.85 seconds
Started Feb 29 12:46:12 PM PST 24
Finished Feb 29 12:46:40 PM PST 24
Peak memory 210632 kb
Host smart-7dae32b4-c91f-47c2-8533-fb8ce1e24aa2
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3522687046 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_pa
ssthru_mem_tl_intg_err.3522687046
Directory /workspace/8.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_same_csr_outstanding.3257883949
Short name T416
Test name
Test status
Simulation time 98763670 ps
CPU time 6.17 seconds
Started Feb 29 12:45:40 PM PST 24
Finished Feb 29 12:45:48 PM PST 24
Peak memory 210608 kb
Host smart-9bb4feba-f3b5-4eec-b4ad-3d059c033c67
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3257883949 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_c
trl_same_csr_outstanding.3257883949
Directory /workspace/8.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_errors.4088048870
Short name T449
Test name
Test status
Simulation time 175360782 ps
CPU time 7.32 seconds
Started Feb 29 12:46:22 PM PST 24
Finished Feb 29 12:46:29 PM PST 24
Peak memory 214716 kb
Host smart-da8d000f-0bd2-40fe-94c5-d7b37599aa10
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4088048870 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_tl_errors.4088048870
Directory /workspace/8.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_intg_err.4268472507
Short name T118
Test name
Test status
Simulation time 5362845314 ps
CPU time 43.22 seconds
Started Feb 29 12:45:34 PM PST 24
Finished Feb 29 12:46:18 PM PST 24
Peak memory 211192 kb
Host smart-6db29675-ff2b-421d-a9a6-965c4924cb3c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4268472507 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_tl_in
tg_err.4268472507
Directory /workspace/8.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_mem_rw_with_rand_reset.354836991
Short name T404
Test name
Test status
Simulation time 1416859077 ps
CPU time 12.53 seconds
Started Feb 29 12:45:54 PM PST 24
Finished Feb 29 12:46:07 PM PST 24
Peak memory 212596 kb
Host smart-84eec268-f2aa-4cd1-a336-2557e331ac01
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=354836991 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 9.rom_ctrl_csr_mem_rw_with_rand_reset.354836991
Directory /workspace/9.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_rw.220272530
Short name T384
Test name
Test status
Simulation time 518209239 ps
CPU time 4.25 seconds
Started Feb 29 12:45:50 PM PST 24
Finished Feb 29 12:45:55 PM PST 24
Peak memory 210512 kb
Host smart-908edf32-7e6f-4a91-84a4-9e62ba1a4aae
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=220272530 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_csr_rw.220272530
Directory /workspace/9.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_passthru_mem_tl_intg_err.2544758594
Short name T429
Test name
Test status
Simulation time 360996600 ps
CPU time 18.62 seconds
Started Feb 29 12:45:36 PM PST 24
Finished Feb 29 12:45:55 PM PST 24
Peak memory 210548 kb
Host smart-df58cd52-b07d-45f6-8797-5b6bc62531fb
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2544758594 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_pa
ssthru_mem_tl_intg_err.2544758594
Directory /workspace/9.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_same_csr_outstanding.1227465483
Short name T468
Test name
Test status
Simulation time 679133430 ps
CPU time 8.25 seconds
Started Feb 29 12:45:37 PM PST 24
Finished Feb 29 12:45:46 PM PST 24
Peak memory 210668 kb
Host smart-202d2925-b830-4350-b0f3-8f10703cd08a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1227465483 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_c
trl_same_csr_outstanding.1227465483
Directory /workspace/9.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_errors.2539987310
Short name T382
Test name
Test status
Simulation time 2179274210 ps
CPU time 19.27 seconds
Started Feb 29 12:45:40 PM PST 24
Finished Feb 29 12:46:01 PM PST 24
Peak memory 214792 kb
Host smart-c7c02bf3-09d5-446d-9c8a-41c4371cbe17
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2539987310 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_tl_errors.2539987310
Directory /workspace/9.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_intg_err.2050124431
Short name T113
Test name
Test status
Simulation time 5972717805 ps
CPU time 76.22 seconds
Started Feb 29 12:45:54 PM PST 24
Finished Feb 29 12:47:11 PM PST 24
Peak memory 212796 kb
Host smart-ec8e3029-d922-4639-9c44-df458dee523c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2050124431 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_tl_in
tg_err.2050124431
Directory /workspace/9.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/0.rom_ctrl_alert_test.2819464619
Short name T146
Test name
Test status
Simulation time 2589504478 ps
CPU time 12.13 seconds
Started Feb 29 01:11:19 PM PST 24
Finished Feb 29 01:11:31 PM PST 24
Peak memory 211128 kb
Host smart-c516dbf0-b483-4186-828c-03b89fb17b11
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2819464619 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_alert_test.2819464619
Directory /workspace/0.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/0.rom_ctrl_corrupt_sig_fatal_chk.1563759640
Short name T367
Test name
Test status
Simulation time 150238714564 ps
CPU time 340.58 seconds
Started Feb 29 01:11:14 PM PST 24
Finished Feb 29 01:16:55 PM PST 24
Peak memory 237820 kb
Host smart-e6a8d889-7a92-4416-99d3-ae55e6b1ed6e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1563759640 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_c
orrupt_sig_fatal_chk.1563759640
Directory /workspace/0.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/0.rom_ctrl_kmac_err_chk.4215683768
Short name T268
Test name
Test status
Simulation time 1891639456 ps
CPU time 21.45 seconds
Started Feb 29 01:11:13 PM PST 24
Finished Feb 29 01:11:35 PM PST 24
Peak memory 211664 kb
Host smart-ecd7372b-f905-4d50-96ff-24e47bacc0ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4215683768 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_kmac_err_chk.4215683768
Directory /workspace/0.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/0.rom_ctrl_max_throughput_chk.4193999572
Short name T292
Test name
Test status
Simulation time 1825277358 ps
CPU time 16.07 seconds
Started Feb 29 01:11:13 PM PST 24
Finished Feb 29 01:11:29 PM PST 24
Peak memory 211056 kb
Host smart-ea3de482-b1e5-4c28-98bb-209c4132647d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4193999572 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_max_throughput_chk.4193999572
Directory /workspace/0.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/0.rom_ctrl_smoke.3233253760
Short name T320
Test name
Test status
Simulation time 1182293055 ps
CPU time 17.41 seconds
Started Feb 29 01:11:14 PM PST 24
Finished Feb 29 01:11:32 PM PST 24
Peak memory 213284 kb
Host smart-08fe4889-5b48-41f6-b573-97cd81114c1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3233253760 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_smoke.3233253760
Directory /workspace/0.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/0.rom_ctrl_stress_all.1160298393
Short name T133
Test name
Test status
Simulation time 8020961721 ps
CPU time 18.06 seconds
Started Feb 29 01:11:16 PM PST 24
Finished Feb 29 01:11:34 PM PST 24
Peak memory 212044 kb
Host smart-f340c924-fec1-47d0-a727-93db3cc8d3d8
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1160298393 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 0.rom_ctrl_stress_all.1160298393
Directory /workspace/0.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/0.rom_ctrl_stress_all_with_rand_reset.4048374364
Short name T42
Test name
Test status
Simulation time 73074246822 ps
CPU time 669.61 seconds
Started Feb 29 01:11:15 PM PST 24
Finished Feb 29 01:22:24 PM PST 24
Peak memory 235812 kb
Host smart-2b2d01e8-6ce7-4bd7-9968-eda911873315
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4048374364 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_stress_all_with_rand_reset.4048374364
Directory /workspace/0.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.rom_ctrl_corrupt_sig_fatal_chk.4198968005
Short name T184
Test name
Test status
Simulation time 33279947652 ps
CPU time 318.47 seconds
Started Feb 29 01:11:24 PM PST 24
Finished Feb 29 01:16:44 PM PST 24
Peak memory 233712 kb
Host smart-7efe3802-ab61-4d14-966b-f5163eb8e75f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4198968005 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_c
orrupt_sig_fatal_chk.4198968005
Directory /workspace/1.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/1.rom_ctrl_max_throughput_chk.2177258834
Short name T157
Test name
Test status
Simulation time 7248652582 ps
CPU time 8.93 seconds
Started Feb 29 01:11:23 PM PST 24
Finished Feb 29 01:11:34 PM PST 24
Peak memory 211232 kb
Host smart-4c720dc3-5022-4a72-a7ef-69a3ecbaec69
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2177258834 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_max_throughput_chk.2177258834
Directory /workspace/1.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/1.rom_ctrl_sec_cm.2748645232
Short name T32
Test name
Test status
Simulation time 2707181588 ps
CPU time 60.14 seconds
Started Feb 29 01:11:24 PM PST 24
Finished Feb 29 01:12:25 PM PST 24
Peak memory 236252 kb
Host smart-59fc00af-ee8f-431b-9bdc-4bca5a9a5c37
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2748645232 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_sec_cm.2748645232
Directory /workspace/1.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/1.rom_ctrl_smoke.1531352567
Short name T259
Test name
Test status
Simulation time 3208809026 ps
CPU time 34.08 seconds
Started Feb 29 01:11:22 PM PST 24
Finished Feb 29 01:11:57 PM PST 24
Peak memory 212792 kb
Host smart-6999e6b5-c78d-439f-8c33-ee16fa165634
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1531352567 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_smoke.1531352567
Directory /workspace/1.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/1.rom_ctrl_stress_all.3635968445
Short name T215
Test name
Test status
Simulation time 200341879 ps
CPU time 12.39 seconds
Started Feb 29 01:11:15 PM PST 24
Finished Feb 29 01:11:27 PM PST 24
Peak memory 212480 kb
Host smart-77b10bec-8557-4528-b21d-a379bda66a7d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3635968445 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 1.rom_ctrl_stress_all.3635968445
Directory /workspace/1.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/1.rom_ctrl_stress_all_with_rand_reset.1667092584
Short name T358
Test name
Test status
Simulation time 24842489382 ps
CPU time 1007.28 seconds
Started Feb 29 01:11:27 PM PST 24
Finished Feb 29 01:28:15 PM PST 24
Peak memory 235764 kb
Host smart-7b05bb6c-c113-489f-8aa5-bb4148851874
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1667092584 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_stress_all_with_rand_reset.1667092584
Directory /workspace/1.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.rom_ctrl_alert_test.1400892885
Short name T139
Test name
Test status
Simulation time 1486248783 ps
CPU time 12.92 seconds
Started Feb 29 01:11:41 PM PST 24
Finished Feb 29 01:11:54 PM PST 24
Peak memory 211004 kb
Host smart-edcdf4fd-ca89-4a98-a854-0ea360452476
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1400892885 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_alert_test.1400892885
Directory /workspace/10.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/10.rom_ctrl_corrupt_sig_fatal_chk.4099955877
Short name T319
Test name
Test status
Simulation time 356000689513 ps
CPU time 216.44 seconds
Started Feb 29 01:11:39 PM PST 24
Finished Feb 29 01:15:15 PM PST 24
Peak memory 229240 kb
Host smart-d8f4f032-6d93-4aff-b8bf-5d7e619e7a0d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4099955877 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_
corrupt_sig_fatal_chk.4099955877
Directory /workspace/10.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/10.rom_ctrl_kmac_err_chk.2660975230
Short name T191
Test name
Test status
Simulation time 1911372719 ps
CPU time 21.4 seconds
Started Feb 29 01:11:38 PM PST 24
Finished Feb 29 01:12:00 PM PST 24
Peak memory 211456 kb
Host smart-3f6296ba-fd1f-463c-ae45-c92368d12357
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2660975230 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_kmac_err_chk.2660975230
Directory /workspace/10.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/10.rom_ctrl_max_throughput_chk.3082597083
Short name T136
Test name
Test status
Simulation time 6588013234 ps
CPU time 14.3 seconds
Started Feb 29 01:11:40 PM PST 24
Finished Feb 29 01:11:54 PM PST 24
Peak memory 211232 kb
Host smart-7366cc45-114a-4471-a5ed-36c2f3bbf07a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3082597083 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_max_throughput_chk.3082597083
Directory /workspace/10.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/10.rom_ctrl_smoke.926300179
Short name T19
Test name
Test status
Simulation time 21306503124 ps
CPU time 18.94 seconds
Started Feb 29 01:11:42 PM PST 24
Finished Feb 29 01:12:01 PM PST 24
Peak memory 219360 kb
Host smart-29d00097-52f8-4fa0-b8c0-14f4065edceb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=926300179 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_smoke.926300179
Directory /workspace/10.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/10.rom_ctrl_stress_all.1491023069
Short name T297
Test name
Test status
Simulation time 4123540430 ps
CPU time 13.48 seconds
Started Feb 29 01:11:39 PM PST 24
Finished Feb 29 01:11:53 PM PST 24
Peak memory 211760 kb
Host smart-33f8c5e0-d624-41dc-8fea-5669d88439c4
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1491023069 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 10.rom_ctrl_stress_all.1491023069
Directory /workspace/10.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/10.rom_ctrl_stress_all_with_rand_reset.101327686
Short name T271
Test name
Test status
Simulation time 159385429855 ps
CPU time 5741.88 seconds
Started Feb 29 01:11:40 PM PST 24
Finished Feb 29 02:47:22 PM PST 24
Peak memory 235672 kb
Host smart-2f9df414-7c2d-4da2-90a2-33582fded5a4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=101327686 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_stress_all_with_rand_reset.101327686
Directory /workspace/10.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/11.rom_ctrl_alert_test.3728067480
Short name T84
Test name
Test status
Simulation time 85435639 ps
CPU time 4.3 seconds
Started Feb 29 01:11:42 PM PST 24
Finished Feb 29 01:11:46 PM PST 24
Peak memory 211076 kb
Host smart-eae95903-80a8-415a-a7da-b6b1215ba4d2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3728067480 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_alert_test.3728067480
Directory /workspace/11.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/11.rom_ctrl_corrupt_sig_fatal_chk.3117849776
Short name T301
Test name
Test status
Simulation time 37540666019 ps
CPU time 159.49 seconds
Started Feb 29 01:11:37 PM PST 24
Finished Feb 29 01:14:17 PM PST 24
Peak memory 212340 kb
Host smart-60e7707c-f32f-4175-ab35-8069b95acd04
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3117849776 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_
corrupt_sig_fatal_chk.3117849776
Directory /workspace/11.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/11.rom_ctrl_max_throughput_chk.3956141771
Short name T194
Test name
Test status
Simulation time 1598596909 ps
CPU time 14.3 seconds
Started Feb 29 01:11:40 PM PST 24
Finished Feb 29 01:11:54 PM PST 24
Peak memory 210984 kb
Host smart-2c5b0cfc-d913-4fd8-81ee-b659dd551139
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3956141771 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_max_throughput_chk.3956141771
Directory /workspace/11.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/11.rom_ctrl_smoke.4032118442
Short name T202
Test name
Test status
Simulation time 8330765911 ps
CPU time 17.93 seconds
Started Feb 29 01:11:40 PM PST 24
Finished Feb 29 01:11:58 PM PST 24
Peak memory 213276 kb
Host smart-534f2adc-ca48-4936-b0b0-3a793356d9e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4032118442 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_smoke.4032118442
Directory /workspace/11.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/11.rom_ctrl_stress_all.3991964685
Short name T219
Test name
Test status
Simulation time 1519325714 ps
CPU time 14.48 seconds
Started Feb 29 01:11:46 PM PST 24
Finished Feb 29 01:12:01 PM PST 24
Peak memory 210920 kb
Host smart-68e97be5-e6dd-4d6c-87d8-2ae9e0040d03
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3991964685 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 11.rom_ctrl_stress_all.3991964685
Directory /workspace/11.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/12.rom_ctrl_alert_test.118079665
Short name T324
Test name
Test status
Simulation time 10651675586 ps
CPU time 12.39 seconds
Started Feb 29 01:11:40 PM PST 24
Finished Feb 29 01:11:52 PM PST 24
Peak memory 211192 kb
Host smart-50fecf1e-371c-44d0-b8dc-fda078518b33
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=118079665 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_alert_test.118079665
Directory /workspace/12.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/12.rom_ctrl_corrupt_sig_fatal_chk.26022111
Short name T288
Test name
Test status
Simulation time 37970905705 ps
CPU time 394.64 seconds
Started Feb 29 01:11:41 PM PST 24
Finished Feb 29 01:18:15 PM PST 24
Peak memory 219476 kb
Host smart-9a90c600-679a-4e66-8410-89f60cc0e20b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26022111 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_
sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_co
rrupt_sig_fatal_chk.26022111
Directory /workspace/12.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/12.rom_ctrl_kmac_err_chk.2578704695
Short name T342
Test name
Test status
Simulation time 693127058 ps
CPU time 9.44 seconds
Started Feb 29 01:11:41 PM PST 24
Finished Feb 29 01:11:50 PM PST 24
Peak memory 211044 kb
Host smart-abbc2fae-20a2-402e-80d3-15b7e2a77a4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2578704695 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_kmac_err_chk.2578704695
Directory /workspace/12.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/12.rom_ctrl_max_throughput_chk.3392254119
Short name T318
Test name
Test status
Simulation time 1026065751 ps
CPU time 5.43 seconds
Started Feb 29 01:11:41 PM PST 24
Finished Feb 29 01:11:46 PM PST 24
Peak memory 211072 kb
Host smart-2fe9f81a-3c8b-40b3-97a1-e1194b2a52e2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3392254119 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_max_throughput_chk.3392254119
Directory /workspace/12.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/12.rom_ctrl_smoke.3023810289
Short name T334
Test name
Test status
Simulation time 671007237 ps
CPU time 10.31 seconds
Started Feb 29 01:11:45 PM PST 24
Finished Feb 29 01:11:56 PM PST 24
Peak memory 213152 kb
Host smart-a4872f1a-2da4-4c21-8088-188503223c74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3023810289 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_smoke.3023810289
Directory /workspace/12.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/12.rom_ctrl_stress_all.1224179378
Short name T369
Test name
Test status
Simulation time 10815467508 ps
CPU time 23.63 seconds
Started Feb 29 01:11:40 PM PST 24
Finished Feb 29 01:12:04 PM PST 24
Peak memory 214404 kb
Host smart-1c4642f7-f249-4980-b66c-1683b5758f7f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1224179378 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 12.rom_ctrl_stress_all.1224179378
Directory /workspace/12.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/13.rom_ctrl_alert_test.1765876489
Short name T226
Test name
Test status
Simulation time 88407774 ps
CPU time 4.27 seconds
Started Feb 29 01:11:39 PM PST 24
Finished Feb 29 01:11:43 PM PST 24
Peak memory 211028 kb
Host smart-ad2ed12e-b33d-43b1-96f7-e72118a3f119
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1765876489 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_alert_test.1765876489
Directory /workspace/13.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/13.rom_ctrl_corrupt_sig_fatal_chk.1525713235
Short name T138
Test name
Test status
Simulation time 68346939317 ps
CPU time 183.12 seconds
Started Feb 29 01:11:41 PM PST 24
Finished Feb 29 01:14:44 PM PST 24
Peak memory 237736 kb
Host smart-d1f48420-fd47-4262-8ba1-49634364bd0e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1525713235 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_
corrupt_sig_fatal_chk.1525713235
Directory /workspace/13.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/13.rom_ctrl_kmac_err_chk.944059731
Short name T189
Test name
Test status
Simulation time 5203242976 ps
CPU time 25.25 seconds
Started Feb 29 01:11:41 PM PST 24
Finished Feb 29 01:12:06 PM PST 24
Peak memory 212100 kb
Host smart-a5d0a6a6-5d43-4440-9479-707df0a228b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=944059731 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_kmac_err_chk.944059731
Directory /workspace/13.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/13.rom_ctrl_max_throughput_chk.2066012123
Short name T290
Test name
Test status
Simulation time 5220648165 ps
CPU time 12.91 seconds
Started Feb 29 01:11:41 PM PST 24
Finished Feb 29 01:11:54 PM PST 24
Peak memory 211204 kb
Host smart-165d57f8-974a-4405-aed8-5175c2e46b79
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2066012123 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_max_throughput_chk.2066012123
Directory /workspace/13.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/13.rom_ctrl_smoke.3831177724
Short name T351
Test name
Test status
Simulation time 8355337454 ps
CPU time 38.88 seconds
Started Feb 29 01:11:41 PM PST 24
Finished Feb 29 01:12:20 PM PST 24
Peak memory 213124 kb
Host smart-3e2900b6-a308-4f92-b6d2-700ba5a0f5f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3831177724 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_smoke.3831177724
Directory /workspace/13.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/13.rom_ctrl_stress_all.3137307170
Short name T284
Test name
Test status
Simulation time 9125356478 ps
CPU time 14.06 seconds
Started Feb 29 01:11:42 PM PST 24
Finished Feb 29 01:11:57 PM PST 24
Peak memory 212292 kb
Host smart-16c1f251-ee62-4f94-bd3f-fc376f6ad24a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3137307170 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 13.rom_ctrl_stress_all.3137307170
Directory /workspace/13.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/13.rom_ctrl_stress_all_with_rand_reset.1712625762
Short name T247
Test name
Test status
Simulation time 82403893322 ps
CPU time 612.05 seconds
Started Feb 29 01:11:40 PM PST 24
Finished Feb 29 01:21:52 PM PST 24
Peak memory 231772 kb
Host smart-2b286d20-523d-4837-8b4d-de0d423670ef
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1712625762 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_stress_all_with_rand_reset.1712625762
Directory /workspace/13.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/14.rom_ctrl_alert_test.1563486308
Short name T197
Test name
Test status
Simulation time 21138512971 ps
CPU time 14.61 seconds
Started Feb 29 01:11:40 PM PST 24
Finished Feb 29 01:11:55 PM PST 24
Peak memory 211168 kb
Host smart-f7930685-5d3e-4bd8-9449-ce7700ad6144
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1563486308 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_alert_test.1563486308
Directory /workspace/14.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/14.rom_ctrl_corrupt_sig_fatal_chk.319908716
Short name T165
Test name
Test status
Simulation time 18961490480 ps
CPU time 139.54 seconds
Started Feb 29 01:11:47 PM PST 24
Finished Feb 29 01:14:07 PM PST 24
Peak memory 236672 kb
Host smart-38185a0d-6f2c-4f65-814b-060d0ea3066b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=319908716 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_c
orrupt_sig_fatal_chk.319908716
Directory /workspace/14.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/14.rom_ctrl_kmac_err_chk.164873906
Short name T158
Test name
Test status
Simulation time 589999088 ps
CPU time 13.24 seconds
Started Feb 29 01:11:41 PM PST 24
Finished Feb 29 01:11:54 PM PST 24
Peak memory 211480 kb
Host smart-7ea0c42c-a39a-4953-aeb4-d5a0b1a3951d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=164873906 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_kmac_err_chk.164873906
Directory /workspace/14.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/14.rom_ctrl_max_throughput_chk.4121155398
Short name T190
Test name
Test status
Simulation time 25996981625 ps
CPU time 14.16 seconds
Started Feb 29 01:11:47 PM PST 24
Finished Feb 29 01:12:01 PM PST 24
Peak memory 211092 kb
Host smart-f517f308-0c90-4147-8df8-e2db23033e97
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4121155398 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_max_throughput_chk.4121155398
Directory /workspace/14.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/14.rom_ctrl_smoke.1710520212
Short name T372
Test name
Test status
Simulation time 3635808611 ps
CPU time 24.92 seconds
Started Feb 29 01:11:41 PM PST 24
Finished Feb 29 01:12:06 PM PST 24
Peak memory 212444 kb
Host smart-70e11d27-019f-4bec-b969-73890d66dc89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1710520212 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_smoke.1710520212
Directory /workspace/14.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/14.rom_ctrl_stress_all.598640008
Short name T310
Test name
Test status
Simulation time 3633297553 ps
CPU time 17.39 seconds
Started Feb 29 01:11:46 PM PST 24
Finished Feb 29 01:12:04 PM PST 24
Peak memory 213420 kb
Host smart-53b4c638-0721-472c-9460-ca4396647117
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=598640008 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 14.rom_ctrl_stress_all.598640008
Directory /workspace/14.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/14.rom_ctrl_stress_all_with_rand_reset.667574079
Short name T274
Test name
Test status
Simulation time 80605161575 ps
CPU time 641.06 seconds
Started Feb 29 01:11:40 PM PST 24
Finished Feb 29 01:22:21 PM PST 24
Peak memory 235792 kb
Host smart-c10f9f01-f72d-4a4f-9beb-91dd88149d73
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=667574079 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_stress_all_with_rand_reset.667574079
Directory /workspace/14.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/15.rom_ctrl_alert_test.3079051443
Short name T150
Test name
Test status
Simulation time 2930716635 ps
CPU time 13.78 seconds
Started Feb 29 01:11:40 PM PST 24
Finished Feb 29 01:11:54 PM PST 24
Peak memory 211120 kb
Host smart-a00184be-4468-48ec-b60c-134df3ddde3c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3079051443 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_alert_test.3079051443
Directory /workspace/15.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/15.rom_ctrl_corrupt_sig_fatal_chk.3032854004
Short name T124
Test name
Test status
Simulation time 157069222511 ps
CPU time 383.86 seconds
Started Feb 29 01:11:44 PM PST 24
Finished Feb 29 01:18:08 PM PST 24
Peak memory 237800 kb
Host smart-2cc5911f-4169-4e6c-8245-c4c5e3ef970d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3032854004 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_
corrupt_sig_fatal_chk.3032854004
Directory /workspace/15.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/15.rom_ctrl_kmac_err_chk.3822831963
Short name T360
Test name
Test status
Simulation time 2034229173 ps
CPU time 22.71 seconds
Started Feb 29 01:11:42 PM PST 24
Finished Feb 29 01:12:04 PM PST 24
Peak memory 211432 kb
Host smart-fb54cb54-7dc7-4888-b83c-0e5c883e0246
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3822831963 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_kmac_err_chk.3822831963
Directory /workspace/15.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/15.rom_ctrl_max_throughput_chk.1511489505
Short name T364
Test name
Test status
Simulation time 94886278 ps
CPU time 5.44 seconds
Started Feb 29 01:11:42 PM PST 24
Finished Feb 29 01:11:48 PM PST 24
Peak memory 211048 kb
Host smart-444d6a26-2331-43dd-b2c1-2ac9b19f0b4f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1511489505 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_max_throughput_chk.1511489505
Directory /workspace/15.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/15.rom_ctrl_smoke.1730881117
Short name T149
Test name
Test status
Simulation time 2548407816 ps
CPU time 27.81 seconds
Started Feb 29 01:11:43 PM PST 24
Finished Feb 29 01:12:11 PM PST 24
Peak memory 213296 kb
Host smart-4630bebd-74eb-4c97-ace9-746c16b7f823
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1730881117 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_smoke.1730881117
Directory /workspace/15.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/15.rom_ctrl_stress_all.1994805035
Short name T332
Test name
Test status
Simulation time 222848415 ps
CPU time 5.67 seconds
Started Feb 29 01:11:41 PM PST 24
Finished Feb 29 01:11:46 PM PST 24
Peak memory 211032 kb
Host smart-9c483668-0620-4a58-b174-9cfaae9db67d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1994805035 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 15.rom_ctrl_stress_all.1994805035
Directory /workspace/15.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/16.rom_ctrl_alert_test.3118611835
Short name T56
Test name
Test status
Simulation time 2023080331 ps
CPU time 11.71 seconds
Started Feb 29 01:11:39 PM PST 24
Finished Feb 29 01:11:51 PM PST 24
Peak memory 210992 kb
Host smart-0e2cb874-61b0-4646-8002-0e529244a75e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3118611835 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_alert_test.3118611835
Directory /workspace/16.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/16.rom_ctrl_corrupt_sig_fatal_chk.3563351705
Short name T207
Test name
Test status
Simulation time 12552090754 ps
CPU time 160.9 seconds
Started Feb 29 01:11:39 PM PST 24
Finished Feb 29 01:14:20 PM PST 24
Peak memory 239720 kb
Host smart-8431b475-7d34-474c-9cbb-10439a1d1a07
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3563351705 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_
corrupt_sig_fatal_chk.3563351705
Directory /workspace/16.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/16.rom_ctrl_kmac_err_chk.1426384666
Short name T199
Test name
Test status
Simulation time 1586301593 ps
CPU time 19.71 seconds
Started Feb 29 01:11:43 PM PST 24
Finished Feb 29 01:12:03 PM PST 24
Peak memory 211464 kb
Host smart-3b6cb4af-fe1a-4fd4-9476-c916c6db4ddc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1426384666 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_kmac_err_chk.1426384666
Directory /workspace/16.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/16.rom_ctrl_max_throughput_chk.3665266161
Short name T264
Test name
Test status
Simulation time 7692248452 ps
CPU time 16.23 seconds
Started Feb 29 01:11:43 PM PST 24
Finished Feb 29 01:11:59 PM PST 24
Peak memory 211180 kb
Host smart-2f1f7e27-b6a3-45c1-952c-1a1857dff1a9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3665266161 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_max_throughput_chk.3665266161
Directory /workspace/16.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/16.rom_ctrl_smoke.2697331982
Short name T266
Test name
Test status
Simulation time 2798447950 ps
CPU time 14.38 seconds
Started Feb 29 01:11:41 PM PST 24
Finished Feb 29 01:11:55 PM PST 24
Peak memory 211820 kb
Host smart-7eca31b3-5691-4d05-ad4b-3cc5cfd4beb7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2697331982 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_smoke.2697331982
Directory /workspace/16.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/16.rom_ctrl_stress_all.2919836037
Short name T129
Test name
Test status
Simulation time 507254366 ps
CPU time 26.17 seconds
Started Feb 29 01:11:44 PM PST 24
Finished Feb 29 01:12:11 PM PST 24
Peak memory 219252 kb
Host smart-69520f93-0b4e-4250-8a73-ba9c9e3bfcf0
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2919836037 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 16.rom_ctrl_stress_all.2919836037
Directory /workspace/16.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/16.rom_ctrl_stress_all_with_rand_reset.2734909433
Short name T307
Test name
Test status
Simulation time 385500867850 ps
CPU time 2378.94 seconds
Started Feb 29 01:11:42 PM PST 24
Finished Feb 29 01:51:22 PM PST 24
Peak memory 243980 kb
Host smart-3f60828f-a77d-4aca-920e-6759d583544e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2734909433 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_stress_all_with_rand_reset.2734909433
Directory /workspace/16.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/17.rom_ctrl_alert_test.1638005856
Short name T309
Test name
Test status
Simulation time 688692213 ps
CPU time 5.31 seconds
Started Feb 29 01:11:43 PM PST 24
Finished Feb 29 01:11:49 PM PST 24
Peak memory 211016 kb
Host smart-5ff9568c-75cc-43e3-bb75-71a02613add8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1638005856 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_alert_test.1638005856
Directory /workspace/17.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/17.rom_ctrl_corrupt_sig_fatal_chk.454654473
Short name T169
Test name
Test status
Simulation time 2670777984 ps
CPU time 83.03 seconds
Started Feb 29 01:11:42 PM PST 24
Finished Feb 29 01:13:05 PM PST 24
Peak memory 232768 kb
Host smart-25612609-dc3d-46ff-90d8-82761277aba2
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=454654473 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_c
orrupt_sig_fatal_chk.454654473
Directory /workspace/17.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/17.rom_ctrl_kmac_err_chk.1123211474
Short name T126
Test name
Test status
Simulation time 5631910357 ps
CPU time 26.94 seconds
Started Feb 29 01:11:47 PM PST 24
Finished Feb 29 01:12:14 PM PST 24
Peak memory 211792 kb
Host smart-c7625be9-9f88-488e-ab1f-adbe3dc0daf4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1123211474 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_kmac_err_chk.1123211474
Directory /workspace/17.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/17.rom_ctrl_max_throughput_chk.1586329566
Short name T260
Test name
Test status
Simulation time 2008888975 ps
CPU time 17.08 seconds
Started Feb 29 01:11:43 PM PST 24
Finished Feb 29 01:12:00 PM PST 24
Peak memory 211032 kb
Host smart-4186804c-470c-4692-a4bf-3ceb484032ae
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1586329566 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_max_throughput_chk.1586329566
Directory /workspace/17.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/17.rom_ctrl_stress_all.3453629602
Short name T317
Test name
Test status
Simulation time 6429207077 ps
CPU time 47.66 seconds
Started Feb 29 01:11:45 PM PST 24
Finished Feb 29 01:12:33 PM PST 24
Peak memory 213548 kb
Host smart-1e1fb8c9-b079-4df1-847e-fceaa9b1f5c7
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3453629602 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 17.rom_ctrl_stress_all.3453629602
Directory /workspace/17.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/17.rom_ctrl_stress_all_with_rand_reset.2486749628
Short name T363
Test name
Test status
Simulation time 102296385017 ps
CPU time 2287.81 seconds
Started Feb 29 01:11:43 PM PST 24
Finished Feb 29 01:49:52 PM PST 24
Peak memory 235776 kb
Host smart-32b3db8c-7126-4701-92ef-d025e3350375
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2486749628 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_stress_all_with_rand_reset.2486749628
Directory /workspace/17.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/18.rom_ctrl_alert_test.1937419503
Short name T198
Test name
Test status
Simulation time 379292387 ps
CPU time 4.39 seconds
Started Feb 29 01:11:52 PM PST 24
Finished Feb 29 01:11:57 PM PST 24
Peak memory 211000 kb
Host smart-89133eaa-e9df-4ca5-bf74-7dbc99476d3e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1937419503 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_alert_test.1937419503
Directory /workspace/18.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/18.rom_ctrl_kmac_err_chk.2544955377
Short name T335
Test name
Test status
Simulation time 615584326 ps
CPU time 9.72 seconds
Started Feb 29 01:11:53 PM PST 24
Finished Feb 29 01:12:02 PM PST 24
Peak memory 211600 kb
Host smart-e312fc07-762c-4059-bfdd-0becce7e79f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2544955377 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_kmac_err_chk.2544955377
Directory /workspace/18.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/18.rom_ctrl_max_throughput_chk.2183300504
Short name T221
Test name
Test status
Simulation time 4050392487 ps
CPU time 18.15 seconds
Started Feb 29 01:11:58 PM PST 24
Finished Feb 29 01:12:17 PM PST 24
Peak memory 211144 kb
Host smart-ec12d671-b957-4142-b564-c49b602daaec
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2183300504 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_max_throughput_chk.2183300504
Directory /workspace/18.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/18.rom_ctrl_smoke.3317725296
Short name T341
Test name
Test status
Simulation time 5194850709 ps
CPU time 19.2 seconds
Started Feb 29 01:11:44 PM PST 24
Finished Feb 29 01:12:03 PM PST 24
Peak memory 213588 kb
Host smart-97c99551-628e-4743-bf06-0fdabe9e3920
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3317725296 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_smoke.3317725296
Directory /workspace/18.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/18.rom_ctrl_stress_all.4074619614
Short name T375
Test name
Test status
Simulation time 4874219442 ps
CPU time 41.37 seconds
Started Feb 29 01:11:47 PM PST 24
Finished Feb 29 01:12:28 PM PST 24
Peak memory 216080 kb
Host smart-72ff56b2-0177-477a-a6b4-6a54d9645eed
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4074619614 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 18.rom_ctrl_stress_all.4074619614
Directory /workspace/18.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/19.rom_ctrl_alert_test.1942984866
Short name T365
Test name
Test status
Simulation time 1474027308 ps
CPU time 13.18 seconds
Started Feb 29 01:12:01 PM PST 24
Finished Feb 29 01:12:14 PM PST 24
Peak memory 211004 kb
Host smart-78ff7b21-0d2b-45c1-addc-007610e6ad95
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1942984866 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_alert_test.1942984866
Directory /workspace/19.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/19.rom_ctrl_corrupt_sig_fatal_chk.200549787
Short name T170
Test name
Test status
Simulation time 12349506986 ps
CPU time 132.41 seconds
Started Feb 29 01:11:50 PM PST 24
Finished Feb 29 01:14:02 PM PST 24
Peak memory 236960 kb
Host smart-ff3001ce-8687-482c-93d8-885050309bef
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=200549787 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_c
orrupt_sig_fatal_chk.200549787
Directory /workspace/19.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/19.rom_ctrl_kmac_err_chk.1601795714
Short name T241
Test name
Test status
Simulation time 4012421440 ps
CPU time 32.3 seconds
Started Feb 29 01:11:55 PM PST 24
Finished Feb 29 01:12:27 PM PST 24
Peak memory 211748 kb
Host smart-7666fbb6-d3d3-4f41-95de-f7d430686a92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1601795714 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_kmac_err_chk.1601795714
Directory /workspace/19.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/19.rom_ctrl_max_throughput_chk.864765406
Short name T252
Test name
Test status
Simulation time 7240395005 ps
CPU time 11.08 seconds
Started Feb 29 01:11:50 PM PST 24
Finished Feb 29 01:12:01 PM PST 24
Peak memory 211180 kb
Host smart-b08fd612-8407-4bbb-a118-bc344689aa57
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=864765406 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_max_throughput_chk.864765406
Directory /workspace/19.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/19.rom_ctrl_smoke.3747006795
Short name T204
Test name
Test status
Simulation time 3417457002 ps
CPU time 14.02 seconds
Started Feb 29 01:11:59 PM PST 24
Finished Feb 29 01:12:13 PM PST 24
Peak memory 212972 kb
Host smart-2fb19c9a-5bcd-4e65-a941-fc8fe3d5b776
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3747006795 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_smoke.3747006795
Directory /workspace/19.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/19.rom_ctrl_stress_all.2503250900
Short name T255
Test name
Test status
Simulation time 709839130 ps
CPU time 13.67 seconds
Started Feb 29 01:11:50 PM PST 24
Finished Feb 29 01:12:04 PM PST 24
Peak memory 219192 kb
Host smart-a7663885-b709-4583-8348-f4251dc9c1f9
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2503250900 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 19.rom_ctrl_stress_all.2503250900
Directory /workspace/19.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/2.rom_ctrl_alert_test.2803379812
Short name T195
Test name
Test status
Simulation time 4900279863 ps
CPU time 12.48 seconds
Started Feb 29 01:11:24 PM PST 24
Finished Feb 29 01:11:37 PM PST 24
Peak memory 211228 kb
Host smart-0962c04f-af01-41d5-8d88-056b09ba6119
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2803379812 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_alert_test.2803379812
Directory /workspace/2.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/2.rom_ctrl_kmac_err_chk.3061620589
Short name T323
Test name
Test status
Simulation time 1178285718 ps
CPU time 13.71 seconds
Started Feb 29 01:11:25 PM PST 24
Finished Feb 29 01:11:39 PM PST 24
Peak memory 211596 kb
Host smart-a9fb0c31-2fa0-4950-a0f7-4d70516f23d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3061620589 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_kmac_err_chk.3061620589
Directory /workspace/2.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/2.rom_ctrl_max_throughput_chk.2432307240
Short name T371
Test name
Test status
Simulation time 4840924838 ps
CPU time 12.25 seconds
Started Feb 29 01:11:27 PM PST 24
Finished Feb 29 01:11:40 PM PST 24
Peak memory 211196 kb
Host smart-d5dee26a-c7f8-4353-abf7-3ac4321cff65
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2432307240 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_max_throughput_chk.2432307240
Directory /workspace/2.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/2.rom_ctrl_sec_cm.2399525026
Short name T36
Test name
Test status
Simulation time 548691626 ps
CPU time 51.68 seconds
Started Feb 29 01:11:27 PM PST 24
Finished Feb 29 01:12:19 PM PST 24
Peak memory 231056 kb
Host smart-19eca87f-d5a0-4dc4-8d15-b4d459d1ebf1
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2399525026 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_sec_cm.2399525026
Directory /workspace/2.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/2.rom_ctrl_smoke.554500092
Short name T65
Test name
Test status
Simulation time 698801767 ps
CPU time 13.04 seconds
Started Feb 29 01:11:25 PM PST 24
Finished Feb 29 01:11:38 PM PST 24
Peak memory 212664 kb
Host smart-da5bc9b9-7a22-4451-83f5-f459bf5b6ca8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=554500092 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_smoke.554500092
Directory /workspace/2.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/20.rom_ctrl_alert_test.3520278846
Short name T337
Test name
Test status
Simulation time 3140585770 ps
CPU time 9.02 seconds
Started Feb 29 01:11:55 PM PST 24
Finished Feb 29 01:12:04 PM PST 24
Peak memory 211108 kb
Host smart-636506a1-5002-4325-9a76-a24e553db27f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3520278846 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_alert_test.3520278846
Directory /workspace/20.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/20.rom_ctrl_corrupt_sig_fatal_chk.3804295063
Short name T244
Test name
Test status
Simulation time 173352013460 ps
CPU time 378.32 seconds
Started Feb 29 01:11:54 PM PST 24
Finished Feb 29 01:18:12 PM PST 24
Peak memory 237880 kb
Host smart-74d69467-fb65-478b-a10e-1630e72c8b1d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3804295063 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_
corrupt_sig_fatal_chk.3804295063
Directory /workspace/20.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/20.rom_ctrl_kmac_err_chk.157993359
Short name T187
Test name
Test status
Simulation time 1309733502 ps
CPU time 18.01 seconds
Started Feb 29 01:11:57 PM PST 24
Finished Feb 29 01:12:15 PM PST 24
Peak memory 211580 kb
Host smart-2c933239-e16e-4a80-83f9-953518ad076a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=157993359 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_kmac_err_chk.157993359
Directory /workspace/20.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/20.rom_ctrl_max_throughput_chk.21940369
Short name T164
Test name
Test status
Simulation time 10633358406 ps
CPU time 16.95 seconds
Started Feb 29 01:11:52 PM PST 24
Finished Feb 29 01:12:09 PM PST 24
Peak memory 211168 kb
Host smart-5b052d96-505a-4094-bd2c-aac720064b81
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=21940369 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_max_throughput_chk.21940369
Directory /workspace/20.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/20.rom_ctrl_smoke.1141871788
Short name T142
Test name
Test status
Simulation time 664445670 ps
CPU time 9.71 seconds
Started Feb 29 01:11:47 PM PST 24
Finished Feb 29 01:11:57 PM PST 24
Peak memory 212816 kb
Host smart-c27f90f2-c913-46e7-9a11-47c4db1d3895
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1141871788 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_smoke.1141871788
Directory /workspace/20.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/20.rom_ctrl_stress_all.3290463575
Short name T236
Test name
Test status
Simulation time 6255356301 ps
CPU time 61.15 seconds
Started Feb 29 01:11:52 PM PST 24
Finished Feb 29 01:12:53 PM PST 24
Peak memory 213196 kb
Host smart-cf7f7f92-b1d3-49fc-bc3f-626fce9b7c63
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3290463575 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 20.rom_ctrl_stress_all.3290463575
Directory /workspace/20.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/20.rom_ctrl_stress_all_with_rand_reset.2409554111
Short name T15
Test name
Test status
Simulation time 186608923145 ps
CPU time 2218.84 seconds
Started Feb 29 01:11:52 PM PST 24
Finished Feb 29 01:48:52 PM PST 24
Peak memory 234676 kb
Host smart-562ca769-c49b-407a-9c2e-b7710ee13101
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2409554111 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_stress_all_with_rand_reset.2409554111
Directory /workspace/20.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/21.rom_ctrl_alert_test.1044485538
Short name T314
Test name
Test status
Simulation time 332634564 ps
CPU time 4.38 seconds
Started Feb 29 01:11:51 PM PST 24
Finished Feb 29 01:11:56 PM PST 24
Peak memory 210976 kb
Host smart-68f4ef0a-2c15-455d-a517-72ff3dafa124
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1044485538 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_alert_test.1044485538
Directory /workspace/21.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/21.rom_ctrl_corrupt_sig_fatal_chk.2677629963
Short name T172
Test name
Test status
Simulation time 37156689697 ps
CPU time 350.47 seconds
Started Feb 29 01:11:50 PM PST 24
Finished Feb 29 01:17:40 PM PST 24
Peak memory 227956 kb
Host smart-1fb587d1-53bf-4346-9e98-b20086eb6253
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2677629963 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_
corrupt_sig_fatal_chk.2677629963
Directory /workspace/21.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/21.rom_ctrl_kmac_err_chk.1982563460
Short name T303
Test name
Test status
Simulation time 1684839869 ps
CPU time 14.77 seconds
Started Feb 29 01:11:51 PM PST 24
Finished Feb 29 01:12:06 PM PST 24
Peak memory 211456 kb
Host smart-0057ef52-8096-4cc7-ba21-0369b336f7bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1982563460 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_kmac_err_chk.1982563460
Directory /workspace/21.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/21.rom_ctrl_max_throughput_chk.3494264951
Short name T359
Test name
Test status
Simulation time 2238893447 ps
CPU time 12.24 seconds
Started Feb 29 01:11:51 PM PST 24
Finished Feb 29 01:12:04 PM PST 24
Peak memory 211076 kb
Host smart-c5478a80-1def-496d-936e-c8addaf7b33a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3494264951 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_max_throughput_chk.3494264951
Directory /workspace/21.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/21.rom_ctrl_smoke.1075817325
Short name T140
Test name
Test status
Simulation time 12668092597 ps
CPU time 26.07 seconds
Started Feb 29 01:11:49 PM PST 24
Finished Feb 29 01:12:16 PM PST 24
Peak memory 213692 kb
Host smart-ee7000fa-a448-4e86-879d-eeceff384615
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1075817325 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_smoke.1075817325
Directory /workspace/21.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/21.rom_ctrl_stress_all.2612642375
Short name T356
Test name
Test status
Simulation time 6105120623 ps
CPU time 48.7 seconds
Started Feb 29 01:11:59 PM PST 24
Finished Feb 29 01:12:48 PM PST 24
Peak memory 219308 kb
Host smart-6bb19aac-1d81-488f-921b-9748d3ada158
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2612642375 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 21.rom_ctrl_stress_all.2612642375
Directory /workspace/21.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/22.rom_ctrl_alert_test.760118448
Short name T127
Test name
Test status
Simulation time 7946444131 ps
CPU time 12.27 seconds
Started Feb 29 01:11:54 PM PST 24
Finished Feb 29 01:12:06 PM PST 24
Peak memory 211192 kb
Host smart-b2c81ee7-210c-4143-b577-d32485ed463c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=760118448 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_alert_test.760118448
Directory /workspace/22.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/22.rom_ctrl_corrupt_sig_fatal_chk.3191227625
Short name T299
Test name
Test status
Simulation time 17911425043 ps
CPU time 85.04 seconds
Started Feb 29 01:11:59 PM PST 24
Finished Feb 29 01:13:24 PM PST 24
Peak memory 237620 kb
Host smart-ee2cffd4-43a7-4fd1-97a3-0da62e1d1237
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3191227625 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_
corrupt_sig_fatal_chk.3191227625
Directory /workspace/22.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/22.rom_ctrl_kmac_err_chk.36083281
Short name T135
Test name
Test status
Simulation time 1728047543 ps
CPU time 12.54 seconds
Started Feb 29 01:11:57 PM PST 24
Finished Feb 29 01:12:10 PM PST 24
Peak memory 211816 kb
Host smart-fcaaff3f-52ed-477b-b61b-9316346c9ca5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=36083281 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_kmac_err_chk.36083281
Directory /workspace/22.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/22.rom_ctrl_max_throughput_chk.2130930402
Short name T298
Test name
Test status
Simulation time 7582457675 ps
CPU time 15.54 seconds
Started Feb 29 01:12:02 PM PST 24
Finished Feb 29 01:12:17 PM PST 24
Peak memory 211120 kb
Host smart-bb1a3d84-54cf-44f7-bd3e-df0671659acb
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2130930402 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_max_throughput_chk.2130930402
Directory /workspace/22.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/22.rom_ctrl_smoke.930494370
Short name T161
Test name
Test status
Simulation time 9706649516 ps
CPU time 22.6 seconds
Started Feb 29 01:11:54 PM PST 24
Finished Feb 29 01:12:16 PM PST 24
Peak memory 213184 kb
Host smart-bc57db98-0311-40cd-a703-8eb51951cd75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=930494370 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_smoke.930494370
Directory /workspace/22.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/22.rom_ctrl_stress_all.3094380747
Short name T231
Test name
Test status
Simulation time 3094363821 ps
CPU time 36.58 seconds
Started Feb 29 01:11:49 PM PST 24
Finished Feb 29 01:12:26 PM PST 24
Peak memory 215896 kb
Host smart-e894fcbe-b201-4972-8e3f-ccbb92f2dcbe
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3094380747 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 22.rom_ctrl_stress_all.3094380747
Directory /workspace/22.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/22.rom_ctrl_stress_all_with_rand_reset.2940135197
Short name T41
Test name
Test status
Simulation time 73544818226 ps
CPU time 2795.91 seconds
Started Feb 29 01:11:53 PM PST 24
Finished Feb 29 01:58:30 PM PST 24
Peak memory 244072 kb
Host smart-2483a5c4-0267-499d-a6d2-5cd98c3971b0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2940135197 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_stress_all_with_rand_reset.2940135197
Directory /workspace/22.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/23.rom_ctrl_alert_test.1307848756
Short name T220
Test name
Test status
Simulation time 1031306144 ps
CPU time 10.18 seconds
Started Feb 29 01:11:52 PM PST 24
Finished Feb 29 01:12:03 PM PST 24
Peak memory 211140 kb
Host smart-fed36c7c-f458-4f9e-88e6-a26db5bf3268
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1307848756 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_alert_test.1307848756
Directory /workspace/23.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/23.rom_ctrl_corrupt_sig_fatal_chk.4030167195
Short name T38
Test name
Test status
Simulation time 45997564058 ps
CPU time 230.67 seconds
Started Feb 29 01:12:02 PM PST 24
Finished Feb 29 01:15:53 PM PST 24
Peak memory 224476 kb
Host smart-c867db41-bdc2-4499-b97e-1422cc045387
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4030167195 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_
corrupt_sig_fatal_chk.4030167195
Directory /workspace/23.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/23.rom_ctrl_kmac_err_chk.1087553630
Short name T283
Test name
Test status
Simulation time 4835305033 ps
CPU time 23.84 seconds
Started Feb 29 01:11:51 PM PST 24
Finished Feb 29 01:12:14 PM PST 24
Peak memory 211976 kb
Host smart-50cb57e7-c398-4db1-a1f1-3a6a3e19c3a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1087553630 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_kmac_err_chk.1087553630
Directory /workspace/23.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/23.rom_ctrl_max_throughput_chk.929223397
Short name T131
Test name
Test status
Simulation time 4668138690 ps
CPU time 11.98 seconds
Started Feb 29 01:11:57 PM PST 24
Finished Feb 29 01:12:09 PM PST 24
Peak memory 211168 kb
Host smart-851c3cd5-725b-4913-85fe-08271f680d1c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=929223397 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_max_throughput_chk.929223397
Directory /workspace/23.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/23.rom_ctrl_smoke.4281115630
Short name T174
Test name
Test status
Simulation time 9678397744 ps
CPU time 21.96 seconds
Started Feb 29 01:11:52 PM PST 24
Finished Feb 29 01:12:14 PM PST 24
Peak memory 213820 kb
Host smart-0ca20a80-8998-4ee9-916a-59198ec562c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4281115630 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_smoke.4281115630
Directory /workspace/23.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/23.rom_ctrl_stress_all.4071408346
Short name T273
Test name
Test status
Simulation time 7101002094 ps
CPU time 16.56 seconds
Started Feb 29 01:11:59 PM PST 24
Finished Feb 29 01:12:16 PM PST 24
Peak memory 211236 kb
Host smart-c4e2317e-0ca4-4c5a-937c-9ccd2d6af71b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4071408346 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 23.rom_ctrl_stress_all.4071408346
Directory /workspace/23.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/24.rom_ctrl_alert_test.1921961868
Short name T233
Test name
Test status
Simulation time 2242522729 ps
CPU time 16.82 seconds
Started Feb 29 01:11:52 PM PST 24
Finished Feb 29 01:12:09 PM PST 24
Peak memory 211168 kb
Host smart-215e0c87-dd72-4924-8d9d-8b10b376b84e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1921961868 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_alert_test.1921961868
Directory /workspace/24.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/24.rom_ctrl_corrupt_sig_fatal_chk.683047029
Short name T278
Test name
Test status
Simulation time 25016217932 ps
CPU time 134.76 seconds
Started Feb 29 01:11:59 PM PST 24
Finished Feb 29 01:14:14 PM PST 24
Peak memory 212340 kb
Host smart-b4f4a5dd-ead3-4f47-8654-6c040657ec1c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=683047029 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_c
orrupt_sig_fatal_chk.683047029
Directory /workspace/24.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/24.rom_ctrl_kmac_err_chk.4219407567
Short name T8
Test name
Test status
Simulation time 3788121077 ps
CPU time 31.81 seconds
Started Feb 29 01:11:59 PM PST 24
Finished Feb 29 01:12:31 PM PST 24
Peak memory 211656 kb
Host smart-b1d5d767-6b9e-455e-9b7a-0c7dc69f205a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4219407567 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_kmac_err_chk.4219407567
Directory /workspace/24.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/24.rom_ctrl_max_throughput_chk.3747606656
Short name T263
Test name
Test status
Simulation time 3566102793 ps
CPU time 10.97 seconds
Started Feb 29 01:11:51 PM PST 24
Finished Feb 29 01:12:02 PM PST 24
Peak memory 211096 kb
Host smart-ccb108f2-d119-4f83-bd38-600a1d8e017b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3747606656 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_max_throughput_chk.3747606656
Directory /workspace/24.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/24.rom_ctrl_smoke.3500311877
Short name T151
Test name
Test status
Simulation time 7595858063 ps
CPU time 22.55 seconds
Started Feb 29 01:11:54 PM PST 24
Finished Feb 29 01:12:17 PM PST 24
Peak memory 212664 kb
Host smart-97f425a3-d15b-49d7-bd06-c8914c53964d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3500311877 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_smoke.3500311877
Directory /workspace/24.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/24.rom_ctrl_stress_all.1124359814
Short name T25
Test name
Test status
Simulation time 6124991703 ps
CPU time 50.11 seconds
Started Feb 29 01:12:01 PM PST 24
Finished Feb 29 01:12:51 PM PST 24
Peak memory 216132 kb
Host smart-2d11343c-0c46-4126-9d8e-e42998899ca2
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1124359814 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 24.rom_ctrl_stress_all.1124359814
Directory /workspace/24.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/25.rom_ctrl_alert_test.1190224068
Short name T228
Test name
Test status
Simulation time 6583158938 ps
CPU time 6.89 seconds
Started Feb 29 01:11:52 PM PST 24
Finished Feb 29 01:12:00 PM PST 24
Peak memory 211156 kb
Host smart-a6624d2d-ac83-4cc1-a2b1-c85a1d3082e9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1190224068 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_alert_test.1190224068
Directory /workspace/25.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/25.rom_ctrl_corrupt_sig_fatal_chk.1157002050
Short name T316
Test name
Test status
Simulation time 156163252004 ps
CPU time 385.2 seconds
Started Feb 29 01:11:54 PM PST 24
Finished Feb 29 01:18:20 PM PST 24
Peak memory 228304 kb
Host smart-f3fd0315-caee-47c5-a458-c8d2bf4fb50f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1157002050 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_
corrupt_sig_fatal_chk.1157002050
Directory /workspace/25.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/25.rom_ctrl_kmac_err_chk.3599415611
Short name T224
Test name
Test status
Simulation time 2150331378 ps
CPU time 21.89 seconds
Started Feb 29 01:11:54 PM PST 24
Finished Feb 29 01:12:16 PM PST 24
Peak memory 211724 kb
Host smart-ed858477-0ae2-41bb-ade7-c76f94fb8ad2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3599415611 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_kmac_err_chk.3599415611
Directory /workspace/25.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/25.rom_ctrl_max_throughput_chk.1876024057
Short name T267
Test name
Test status
Simulation time 1985032163 ps
CPU time 16.89 seconds
Started Feb 29 01:11:55 PM PST 24
Finished Feb 29 01:12:12 PM PST 24
Peak memory 211260 kb
Host smart-085788d5-30cb-4d9e-a514-2595521b2faa
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1876024057 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_max_throughput_chk.1876024057
Directory /workspace/25.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/25.rom_ctrl_smoke.1528617746
Short name T305
Test name
Test status
Simulation time 5885777484 ps
CPU time 31.93 seconds
Started Feb 29 01:11:59 PM PST 24
Finished Feb 29 01:12:31 PM PST 24
Peak memory 213712 kb
Host smart-397823cc-1b4d-471c-a88a-43f0e6a6931f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1528617746 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_smoke.1528617746
Directory /workspace/25.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/25.rom_ctrl_stress_all.3263208274
Short name T362
Test name
Test status
Simulation time 4725836389 ps
CPU time 22.6 seconds
Started Feb 29 01:11:54 PM PST 24
Finished Feb 29 01:12:17 PM PST 24
Peak memory 216076 kb
Host smart-931ce035-ea7b-4d98-8c2c-9e33f12c8286
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3263208274 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 25.rom_ctrl_stress_all.3263208274
Directory /workspace/25.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/26.rom_ctrl_alert_test.3789320629
Short name T193
Test name
Test status
Simulation time 5758389009 ps
CPU time 6.35 seconds
Started Feb 29 01:11:59 PM PST 24
Finished Feb 29 01:12:06 PM PST 24
Peak memory 211148 kb
Host smart-4765887d-5ff1-40b2-a404-e8d658a48112
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3789320629 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_alert_test.3789320629
Directory /workspace/26.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/26.rom_ctrl_corrupt_sig_fatal_chk.2723589962
Short name T24
Test name
Test status
Simulation time 82659504940 ps
CPU time 391.14 seconds
Started Feb 29 01:12:04 PM PST 24
Finished Feb 29 01:18:35 PM PST 24
Peak memory 236852 kb
Host smart-acd93cbe-2a7c-4c08-b5f0-2165b19f521e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2723589962 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_
corrupt_sig_fatal_chk.2723589962
Directory /workspace/26.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/26.rom_ctrl_kmac_err_chk.3301577393
Short name T338
Test name
Test status
Simulation time 9902875173 ps
CPU time 23.26 seconds
Started Feb 29 01:12:00 PM PST 24
Finished Feb 29 01:12:23 PM PST 24
Peak memory 212256 kb
Host smart-fe122b9b-81bf-4fca-8eb2-48916d97fa27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3301577393 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_kmac_err_chk.3301577393
Directory /workspace/26.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/26.rom_ctrl_max_throughput_chk.3107796697
Short name T313
Test name
Test status
Simulation time 2577788409 ps
CPU time 9.64 seconds
Started Feb 29 01:11:52 PM PST 24
Finished Feb 29 01:12:01 PM PST 24
Peak memory 211080 kb
Host smart-73b241e9-3ff9-4a7b-912d-0f696a41b3cd
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3107796697 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_max_throughput_chk.3107796697
Directory /workspace/26.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/26.rom_ctrl_smoke.1795302346
Short name T373
Test name
Test status
Simulation time 1115334013 ps
CPU time 10.25 seconds
Started Feb 29 01:11:55 PM PST 24
Finished Feb 29 01:12:05 PM PST 24
Peak memory 213268 kb
Host smart-f2788f8c-6771-4901-b7a9-8bfca52da615
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1795302346 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_smoke.1795302346
Directory /workspace/26.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/26.rom_ctrl_stress_all.3480648809
Short name T88
Test name
Test status
Simulation time 223536828 ps
CPU time 12.65 seconds
Started Feb 29 01:11:53 PM PST 24
Finished Feb 29 01:12:05 PM PST 24
Peak memory 214488 kb
Host smart-c4802a8a-c74c-444b-8117-54928ff4391e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3480648809 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 26.rom_ctrl_stress_all.3480648809
Directory /workspace/26.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/26.rom_ctrl_stress_all_with_rand_reset.514294847
Short name T40
Test name
Test status
Simulation time 14094535733 ps
CPU time 574.27 seconds
Started Feb 29 01:11:54 PM PST 24
Finished Feb 29 01:21:29 PM PST 24
Peak memory 227876 kb
Host smart-5ce667dd-3926-4681-8b2b-71319e5e0b13
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=514294847 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_stress_all_with_rand_reset.514294847
Directory /workspace/26.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/27.rom_ctrl_alert_test.378980283
Short name T237
Test name
Test status
Simulation time 3015547907 ps
CPU time 13.66 seconds
Started Feb 29 01:12:04 PM PST 24
Finished Feb 29 01:12:18 PM PST 24
Peak memory 211092 kb
Host smart-e5cdfb4d-f0e8-4220-afee-f46a4dd13101
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=378980283 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_alert_test.378980283
Directory /workspace/27.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/27.rom_ctrl_corrupt_sig_fatal_chk.4164367903
Short name T181
Test name
Test status
Simulation time 72239603276 ps
CPU time 211.29 seconds
Started Feb 29 01:12:04 PM PST 24
Finished Feb 29 01:15:36 PM PST 24
Peak memory 212456 kb
Host smart-1d6d119b-8871-4810-963c-b215042c4220
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4164367903 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_
corrupt_sig_fatal_chk.4164367903
Directory /workspace/27.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/27.rom_ctrl_kmac_err_chk.3832496442
Short name T370
Test name
Test status
Simulation time 1385125706 ps
CPU time 17.67 seconds
Started Feb 29 01:11:52 PM PST 24
Finished Feb 29 01:12:10 PM PST 24
Peak memory 211072 kb
Host smart-7f40a530-1526-41fd-8742-9e915290f995
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3832496442 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_kmac_err_chk.3832496442
Directory /workspace/27.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/27.rom_ctrl_max_throughput_chk.926866997
Short name T178
Test name
Test status
Simulation time 447321315 ps
CPU time 8.13 seconds
Started Feb 29 01:12:03 PM PST 24
Finished Feb 29 01:12:12 PM PST 24
Peak memory 211076 kb
Host smart-3e5cc687-9e6c-4c8d-9c03-fa03725986d9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=926866997 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_max_throughput_chk.926866997
Directory /workspace/27.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/27.rom_ctrl_smoke.2701363325
Short name T200
Test name
Test status
Simulation time 11060588274 ps
CPU time 30.65 seconds
Started Feb 29 01:12:02 PM PST 24
Finished Feb 29 01:12:33 PM PST 24
Peak memory 213552 kb
Host smart-07f36ae4-1ec0-4ff7-8468-c2921069d8b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2701363325 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_smoke.2701363325
Directory /workspace/27.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/27.rom_ctrl_stress_all.1275568707
Short name T230
Test name
Test status
Simulation time 1245427502 ps
CPU time 15.44 seconds
Started Feb 29 01:11:54 PM PST 24
Finished Feb 29 01:12:10 PM PST 24
Peak memory 214916 kb
Host smart-bd58e2c8-c002-4e3e-9f82-0ea1b6fcc8a3
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1275568707 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 27.rom_ctrl_stress_all.1275568707
Directory /workspace/27.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/28.rom_ctrl_alert_test.1133738416
Short name T44
Test name
Test status
Simulation time 6310724593 ps
CPU time 13.39 seconds
Started Feb 29 01:12:00 PM PST 24
Finished Feb 29 01:12:13 PM PST 24
Peak memory 211148 kb
Host smart-cd7e8cf5-317b-44cf-85c5-79b4cd9f13c2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1133738416 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_alert_test.1133738416
Directory /workspace/28.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/28.rom_ctrl_corrupt_sig_fatal_chk.1398743058
Short name T289
Test name
Test status
Simulation time 146409871942 ps
CPU time 372.14 seconds
Started Feb 29 01:11:56 PM PST 24
Finished Feb 29 01:18:08 PM PST 24
Peak memory 224508 kb
Host smart-f8f98a80-077f-463f-b74c-7861e15bd9ca
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1398743058 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_
corrupt_sig_fatal_chk.1398743058
Directory /workspace/28.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/28.rom_ctrl_kmac_err_chk.1018861095
Short name T23
Test name
Test status
Simulation time 18074868405 ps
CPU time 20.44 seconds
Started Feb 29 01:12:04 PM PST 24
Finished Feb 29 01:12:25 PM PST 24
Peak memory 213424 kb
Host smart-e79a4b9c-54e7-4dd6-9c23-ec18c6c14fa6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1018861095 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_kmac_err_chk.1018861095
Directory /workspace/28.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/28.rom_ctrl_max_throughput_chk.3514470880
Short name T238
Test name
Test status
Simulation time 5482491099 ps
CPU time 13.76 seconds
Started Feb 29 01:11:57 PM PST 24
Finished Feb 29 01:12:11 PM PST 24
Peak memory 211112 kb
Host smart-28d4c8ee-51c2-4e65-b7ee-19aeb93a1869
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3514470880 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_max_throughput_chk.3514470880
Directory /workspace/28.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/28.rom_ctrl_smoke.2178635232
Short name T20
Test name
Test status
Simulation time 757199854 ps
CPU time 9.83 seconds
Started Feb 29 01:12:04 PM PST 24
Finished Feb 29 01:12:14 PM PST 24
Peak memory 213396 kb
Host smart-d020f776-3d26-4bca-94f9-99a8bdbeae0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2178635232 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_smoke.2178635232
Directory /workspace/28.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/28.rom_ctrl_stress_all.2461945622
Short name T145
Test name
Test status
Simulation time 4132393132 ps
CPU time 44.9 seconds
Started Feb 29 01:11:55 PM PST 24
Finished Feb 29 01:12:40 PM PST 24
Peak memory 212904 kb
Host smart-196d8fe6-122e-47a0-92ad-60333e15aae7
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2461945622 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 28.rom_ctrl_stress_all.2461945622
Directory /workspace/28.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/28.rom_ctrl_stress_all_with_rand_reset.1246854017
Short name T13
Test name
Test status
Simulation time 81166091299 ps
CPU time 1091.93 seconds
Started Feb 29 01:12:04 PM PST 24
Finished Feb 29 01:30:17 PM PST 24
Peak memory 235784 kb
Host smart-43e96382-efd2-47f6-a1d4-26c17d0f924e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1246854017 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_stress_all_with_rand_reset.1246854017
Directory /workspace/28.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/29.rom_ctrl_alert_test.1626956449
Short name T206
Test name
Test status
Simulation time 175442557 ps
CPU time 4.1 seconds
Started Feb 29 01:12:01 PM PST 24
Finished Feb 29 01:12:06 PM PST 24
Peak memory 211044 kb
Host smart-2c65faa0-e8d8-48c7-8ef4-7a761016d294
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1626956449 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_alert_test.1626956449
Directory /workspace/29.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/29.rom_ctrl_corrupt_sig_fatal_chk.728347930
Short name T1
Test name
Test status
Simulation time 2560106916 ps
CPU time 163.62 seconds
Started Feb 29 01:12:04 PM PST 24
Finished Feb 29 01:14:48 PM PST 24
Peak memory 228380 kb
Host smart-5cb1f869-f1b8-4130-afa4-f26235fa4286
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=728347930 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_c
orrupt_sig_fatal_chk.728347930
Directory /workspace/29.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/29.rom_ctrl_kmac_err_chk.2924575004
Short name T258
Test name
Test status
Simulation time 3848578726 ps
CPU time 13.49 seconds
Started Feb 29 01:12:00 PM PST 24
Finished Feb 29 01:12:14 PM PST 24
Peak memory 211108 kb
Host smart-adddb52b-1212-48b0-ac0e-85a7299e85db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2924575004 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_kmac_err_chk.2924575004
Directory /workspace/29.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/29.rom_ctrl_max_throughput_chk.65826665
Short name T171
Test name
Test status
Simulation time 880631102 ps
CPU time 10.88 seconds
Started Feb 29 01:11:54 PM PST 24
Finished Feb 29 01:12:05 PM PST 24
Peak memory 211084 kb
Host smart-2cd1bd45-24b2-4d81-9b06-f6c51a3142cc
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=65826665 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_max_throughput_chk.65826665
Directory /workspace/29.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/29.rom_ctrl_smoke.1071926319
Short name T186
Test name
Test status
Simulation time 6200732586 ps
CPU time 18.97 seconds
Started Feb 29 01:11:59 PM PST 24
Finished Feb 29 01:12:19 PM PST 24
Peak memory 213496 kb
Host smart-e386632e-3834-4933-86cc-dd60c63b4e4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1071926319 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_smoke.1071926319
Directory /workspace/29.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/29.rom_ctrl_stress_all.3377909596
Short name T276
Test name
Test status
Simulation time 35381709997 ps
CPU time 60.65 seconds
Started Feb 29 01:12:01 PM PST 24
Finished Feb 29 01:13:02 PM PST 24
Peak memory 219356 kb
Host smart-64be095d-a635-4a57-bc22-0b1b26e14088
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3377909596 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 29.rom_ctrl_stress_all.3377909596
Directory /workspace/29.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/3.rom_ctrl_alert_test.1923586078
Short name T287
Test name
Test status
Simulation time 1128841798 ps
CPU time 7.82 seconds
Started Feb 29 01:11:27 PM PST 24
Finished Feb 29 01:11:35 PM PST 24
Peak memory 210992 kb
Host smart-40143046-1991-46c0-af92-5dc13a353c8a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1923586078 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_alert_test.1923586078
Directory /workspace/3.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/3.rom_ctrl_kmac_err_chk.1376397781
Short name T242
Test name
Test status
Simulation time 2104513249 ps
CPU time 14.75 seconds
Started Feb 29 01:11:24 PM PST 24
Finished Feb 29 01:11:39 PM PST 24
Peak memory 211912 kb
Host smart-267244cf-8371-4eb7-9509-813613274b16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1376397781 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_kmac_err_chk.1376397781
Directory /workspace/3.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/3.rom_ctrl_max_throughput_chk.319965382
Short name T83
Test name
Test status
Simulation time 1091160736 ps
CPU time 11.84 seconds
Started Feb 29 01:11:23 PM PST 24
Finished Feb 29 01:11:37 PM PST 24
Peak memory 210948 kb
Host smart-07c852be-c0bd-4d08-a16c-00572fb6747e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=319965382 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_max_throughput_chk.319965382
Directory /workspace/3.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/3.rom_ctrl_sec_cm.2501151900
Short name T33
Test name
Test status
Simulation time 2640005442 ps
CPU time 107.16 seconds
Started Feb 29 01:11:27 PM PST 24
Finished Feb 29 01:13:15 PM PST 24
Peak memory 236560 kb
Host smart-73ef01e6-0ae2-45b0-adef-d1345e766c97
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2501151900 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_sec_cm.2501151900
Directory /workspace/3.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/3.rom_ctrl_smoke.1110617680
Short name T326
Test name
Test status
Simulation time 809909361 ps
CPU time 17.18 seconds
Started Feb 29 01:11:24 PM PST 24
Finished Feb 29 01:11:42 PM PST 24
Peak memory 213296 kb
Host smart-c684cec9-45fb-4026-8068-e59919267e81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1110617680 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_smoke.1110617680
Directory /workspace/3.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/3.rom_ctrl_stress_all.3879586119
Short name T254
Test name
Test status
Simulation time 261968515 ps
CPU time 7.55 seconds
Started Feb 29 01:11:27 PM PST 24
Finished Feb 29 01:11:35 PM PST 24
Peak memory 211076 kb
Host smart-0d4c48a9-95c0-46db-b8a5-a0acb700133f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3879586119 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 3.rom_ctrl_stress_all.3879586119
Directory /workspace/3.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/3.rom_ctrl_stress_all_with_rand_reset.2626423316
Short name T251
Test name
Test status
Simulation time 64871937883 ps
CPU time 2442.37 seconds
Started Feb 29 01:11:30 PM PST 24
Finished Feb 29 01:52:12 PM PST 24
Peak memory 243940 kb
Host smart-0d161dae-19ee-40f3-8d37-674682f31407
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2626423316 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_stress_all_with_rand_reset.2626423316
Directory /workspace/3.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.rom_ctrl_alert_test.3217967150
Short name T336
Test name
Test status
Simulation time 6594603751 ps
CPU time 16.58 seconds
Started Feb 29 01:12:05 PM PST 24
Finished Feb 29 01:12:22 PM PST 24
Peak memory 210992 kb
Host smart-82c9a119-8290-4b0c-ba86-8eddddcc4de2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3217967150 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_alert_test.3217967150
Directory /workspace/30.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/30.rom_ctrl_corrupt_sig_fatal_chk.4233700355
Short name T122
Test name
Test status
Simulation time 2878590816 ps
CPU time 83.92 seconds
Started Feb 29 01:12:01 PM PST 24
Finished Feb 29 01:13:25 PM PST 24
Peak memory 213348 kb
Host smart-03513b94-f9e3-41c3-85c7-2bd78acd613c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4233700355 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_
corrupt_sig_fatal_chk.4233700355
Directory /workspace/30.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/30.rom_ctrl_kmac_err_chk.3499746008
Short name T269
Test name
Test status
Simulation time 170248437 ps
CPU time 9.19 seconds
Started Feb 29 01:12:01 PM PST 24
Finished Feb 29 01:12:10 PM PST 24
Peak memory 211656 kb
Host smart-80c6ca1d-efac-4764-8f07-1b907dcd6828
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3499746008 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_kmac_err_chk.3499746008
Directory /workspace/30.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/30.rom_ctrl_max_throughput_chk.3891576568
Short name T222
Test name
Test status
Simulation time 399463211 ps
CPU time 5.24 seconds
Started Feb 29 01:12:04 PM PST 24
Finished Feb 29 01:12:10 PM PST 24
Peak memory 210952 kb
Host smart-96755ffc-2bb7-40b4-b76b-540058c0335b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3891576568 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_max_throughput_chk.3891576568
Directory /workspace/30.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/30.rom_ctrl_smoke.2222848828
Short name T66
Test name
Test status
Simulation time 728506420 ps
CPU time 10.19 seconds
Started Feb 29 01:12:04 PM PST 24
Finished Feb 29 01:12:14 PM PST 24
Peak memory 213040 kb
Host smart-7de1d11b-128b-4eb3-99a7-57f018d056ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2222848828 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_smoke.2222848828
Directory /workspace/30.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/30.rom_ctrl_stress_all.564882605
Short name T272
Test name
Test status
Simulation time 347811420 ps
CPU time 17.12 seconds
Started Feb 29 01:12:04 PM PST 24
Finished Feb 29 01:12:21 PM PST 24
Peak memory 214628 kb
Host smart-255bd585-3530-4869-aeaa-7746671f41e9
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=564882605 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 30.rom_ctrl_stress_all.564882605
Directory /workspace/30.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/30.rom_ctrl_stress_all_with_rand_reset.2660342958
Short name T39
Test name
Test status
Simulation time 14720791357 ps
CPU time 545.57 seconds
Started Feb 29 01:12:00 PM PST 24
Finished Feb 29 01:21:06 PM PST 24
Peak memory 233092 kb
Host smart-0f825a7c-4250-4cbd-9c17-497020020880
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2660342958 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_stress_all_with_rand_reset.2660342958
Directory /workspace/30.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.rom_ctrl_alert_test.3462409247
Short name T201
Test name
Test status
Simulation time 303998564 ps
CPU time 6.08 seconds
Started Feb 29 01:12:05 PM PST 24
Finished Feb 29 01:12:11 PM PST 24
Peak memory 211004 kb
Host smart-aab4e4d1-dc3b-45f7-904d-f73598dd071f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3462409247 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_alert_test.3462409247
Directory /workspace/31.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/31.rom_ctrl_corrupt_sig_fatal_chk.71142284
Short name T90
Test name
Test status
Simulation time 73003822193 ps
CPU time 379.27 seconds
Started Feb 29 01:12:05 PM PST 24
Finished Feb 29 01:18:25 PM PST 24
Peak memory 236672 kb
Host smart-10f85631-97e0-4cfa-b682-84caf9a0e341
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71142284 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_
sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_co
rrupt_sig_fatal_chk.71142284
Directory /workspace/31.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/31.rom_ctrl_kmac_err_chk.3866413416
Short name T243
Test name
Test status
Simulation time 221310272 ps
CPU time 9.39 seconds
Started Feb 29 01:12:04 PM PST 24
Finished Feb 29 01:12:14 PM PST 24
Peak memory 211492 kb
Host smart-2053bce5-9732-497f-be85-ca5b017cc583
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3866413416 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_kmac_err_chk.3866413416
Directory /workspace/31.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/31.rom_ctrl_max_throughput_chk.429782149
Short name T180
Test name
Test status
Simulation time 1004712191 ps
CPU time 8.92 seconds
Started Feb 29 01:12:04 PM PST 24
Finished Feb 29 01:12:14 PM PST 24
Peak memory 211004 kb
Host smart-8880b434-b8db-491f-9e5e-1181ad6483d8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=429782149 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_max_throughput_chk.429782149
Directory /workspace/31.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/31.rom_ctrl_smoke.1274950850
Short name T104
Test name
Test status
Simulation time 11745731810 ps
CPU time 26.79 seconds
Started Feb 29 01:12:05 PM PST 24
Finished Feb 29 01:12:32 PM PST 24
Peak memory 213840 kb
Host smart-87d5eabe-0063-4a4f-900f-bc52292072c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1274950850 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_smoke.1274950850
Directory /workspace/31.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/31.rom_ctrl_stress_all.437945045
Short name T249
Test name
Test status
Simulation time 742642781 ps
CPU time 9.5 seconds
Started Feb 29 01:12:05 PM PST 24
Finished Feb 29 01:12:14 PM PST 24
Peak memory 211008 kb
Host smart-c6dea43c-f48b-481f-a974-c63c830a95a1
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=437945045 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 31.rom_ctrl_stress_all.437945045
Directory /workspace/31.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/32.rom_ctrl_alert_test.2801958817
Short name T302
Test name
Test status
Simulation time 4117776662 ps
CPU time 7.7 seconds
Started Feb 29 01:12:09 PM PST 24
Finished Feb 29 01:12:17 PM PST 24
Peak memory 211084 kb
Host smart-31c7fd7f-a42a-4a46-b821-b58603071793
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2801958817 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_alert_test.2801958817
Directory /workspace/32.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/32.rom_ctrl_corrupt_sig_fatal_chk.3359739806
Short name T173
Test name
Test status
Simulation time 91470735488 ps
CPU time 211.09 seconds
Started Feb 29 01:12:03 PM PST 24
Finished Feb 29 01:15:35 PM PST 24
Peak memory 228572 kb
Host smart-95a9efd9-44cf-485c-9784-43e206edff76
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3359739806 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_
corrupt_sig_fatal_chk.3359739806
Directory /workspace/32.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/32.rom_ctrl_kmac_err_chk.3546957580
Short name T22
Test name
Test status
Simulation time 692727706 ps
CPU time 9.28 seconds
Started Feb 29 01:12:09 PM PST 24
Finished Feb 29 01:12:19 PM PST 24
Peak memory 211060 kb
Host smart-bad206fd-a75b-4471-8500-90dc8e26dad3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3546957580 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_kmac_err_chk.3546957580
Directory /workspace/32.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/32.rom_ctrl_max_throughput_chk.1103891824
Short name T327
Test name
Test status
Simulation time 17336125719 ps
CPU time 11.97 seconds
Started Feb 29 01:12:05 PM PST 24
Finished Feb 29 01:12:17 PM PST 24
Peak memory 210972 kb
Host smart-cded340b-1009-4e3f-b40e-06679ffa2b54
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1103891824 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_max_throughput_chk.1103891824
Directory /workspace/32.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/32.rom_ctrl_smoke.424277212
Short name T265
Test name
Test status
Simulation time 3879659598 ps
CPU time 31.67 seconds
Started Feb 29 01:12:10 PM PST 24
Finished Feb 29 01:12:42 PM PST 24
Peak memory 212492 kb
Host smart-f832f0f3-b325-4c2a-a60f-28005184cf6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=424277212 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_smoke.424277212
Directory /workspace/32.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/32.rom_ctrl_stress_all.882901875
Short name T212
Test name
Test status
Simulation time 939175732 ps
CPU time 24.1 seconds
Started Feb 29 01:12:05 PM PST 24
Finished Feb 29 01:12:29 PM PST 24
Peak memory 215544 kb
Host smart-73a27a6f-a2f5-4eb5-bed3-fcc3559d28e0
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=882901875 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 32.rom_ctrl_stress_all.882901875
Directory /workspace/32.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/33.rom_ctrl_alert_test.2694291369
Short name T217
Test name
Test status
Simulation time 11703307907 ps
CPU time 16.51 seconds
Started Feb 29 01:12:09 PM PST 24
Finished Feb 29 01:12:27 PM PST 24
Peak memory 211164 kb
Host smart-5867973b-c386-4ba4-a5b6-dcceae7cfed7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2694291369 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_alert_test.2694291369
Directory /workspace/33.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/33.rom_ctrl_corrupt_sig_fatal_chk.1573446112
Short name T123
Test name
Test status
Simulation time 13623008812 ps
CPU time 144.97 seconds
Started Feb 29 01:11:53 PM PST 24
Finished Feb 29 01:14:19 PM PST 24
Peak memory 229796 kb
Host smart-4fb13b92-61a9-4907-b212-04834d77a215
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1573446112 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_
corrupt_sig_fatal_chk.1573446112
Directory /workspace/33.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/33.rom_ctrl_kmac_err_chk.1261449885
Short name T291
Test name
Test status
Simulation time 2137720854 ps
CPU time 16.25 seconds
Started Feb 29 01:12:09 PM PST 24
Finished Feb 29 01:12:26 PM PST 24
Peak memory 211212 kb
Host smart-e0cf2bf3-6521-40af-912c-35d0aada5e2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1261449885 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_kmac_err_chk.1261449885
Directory /workspace/33.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/33.rom_ctrl_max_throughput_chk.3120479338
Short name T300
Test name
Test status
Simulation time 19834114085 ps
CPU time 15.99 seconds
Started Feb 29 01:11:56 PM PST 24
Finished Feb 29 01:12:12 PM PST 24
Peak memory 211164 kb
Host smart-d05f9a49-6240-4666-87dd-f0f1e6c41db5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3120479338 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_max_throughput_chk.3120479338
Directory /workspace/33.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/33.rom_ctrl_smoke.2473905184
Short name T148
Test name
Test status
Simulation time 9190550992 ps
CPU time 26.91 seconds
Started Feb 29 01:12:08 PM PST 24
Finished Feb 29 01:12:36 PM PST 24
Peak memory 213332 kb
Host smart-82fe3ae7-20f0-4e66-a842-58b19b08cb2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2473905184 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_smoke.2473905184
Directory /workspace/33.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/33.rom_ctrl_stress_all.1247390396
Short name T166
Test name
Test status
Simulation time 9902198554 ps
CPU time 17.27 seconds
Started Feb 29 01:11:55 PM PST 24
Finished Feb 29 01:12:12 PM PST 24
Peak memory 212460 kb
Host smart-0653b34a-3b68-4f7b-94e2-d4f7c3be8fee
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1247390396 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 33.rom_ctrl_stress_all.1247390396
Directory /workspace/33.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/34.rom_ctrl_alert_test.394687448
Short name T286
Test name
Test status
Simulation time 2077808477 ps
CPU time 16.39 seconds
Started Feb 29 01:12:09 PM PST 24
Finished Feb 29 01:12:26 PM PST 24
Peak memory 211024 kb
Host smart-76145852-6a7b-4c15-a9ae-bdcf91a898f9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=394687448 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_alert_test.394687448
Directory /workspace/34.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/34.rom_ctrl_corrupt_sig_fatal_chk.1759092976
Short name T246
Test name
Test status
Simulation time 72359449059 ps
CPU time 269.45 seconds
Started Feb 29 01:12:08 PM PST 24
Finished Feb 29 01:16:38 PM PST 24
Peak memory 233560 kb
Host smart-69e3631e-6231-40d3-9b0c-8d9fbf5af676
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1759092976 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_
corrupt_sig_fatal_chk.1759092976
Directory /workspace/34.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/34.rom_ctrl_kmac_err_chk.3762161486
Short name T27
Test name
Test status
Simulation time 2414617938 ps
CPU time 22.92 seconds
Started Feb 29 01:12:08 PM PST 24
Finished Feb 29 01:12:32 PM PST 24
Peak memory 211092 kb
Host smart-129519af-5864-4c3b-92bf-233284f24280
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3762161486 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_kmac_err_chk.3762161486
Directory /workspace/34.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/34.rom_ctrl_max_throughput_chk.897065036
Short name T350
Test name
Test status
Simulation time 3770225817 ps
CPU time 16.17 seconds
Started Feb 29 01:12:04 PM PST 24
Finished Feb 29 01:12:21 PM PST 24
Peak memory 211128 kb
Host smart-ffa9ea50-dbce-44bd-813a-d0a0563453ac
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=897065036 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_max_throughput_chk.897065036
Directory /workspace/34.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/34.rom_ctrl_smoke.3990342568
Short name T176
Test name
Test status
Simulation time 620132299 ps
CPU time 9.92 seconds
Started Feb 29 01:12:03 PM PST 24
Finished Feb 29 01:12:14 PM PST 24
Peak memory 212592 kb
Host smart-82df7bd9-81e0-4f4b-98c6-04ee89ce8726
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3990342568 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_smoke.3990342568
Directory /workspace/34.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/34.rom_ctrl_stress_all.507420127
Short name T211
Test name
Test status
Simulation time 7038182845 ps
CPU time 30.72 seconds
Started Feb 29 01:12:11 PM PST 24
Finished Feb 29 01:12:43 PM PST 24
Peak memory 219392 kb
Host smart-62c54f1c-0341-4906-96ad-e5ffedb10a36
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=507420127 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 34.rom_ctrl_stress_all.507420127
Directory /workspace/34.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/35.rom_ctrl_alert_test.3911799258
Short name T54
Test name
Test status
Simulation time 1894372513 ps
CPU time 7.57 seconds
Started Feb 29 01:12:06 PM PST 24
Finished Feb 29 01:12:14 PM PST 24
Peak memory 210540 kb
Host smart-42ade352-0cf7-4145-985b-43b8f213a30b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3911799258 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_alert_test.3911799258
Directory /workspace/35.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/35.rom_ctrl_corrupt_sig_fatal_chk.1294267632
Short name T30
Test name
Test status
Simulation time 1692234421 ps
CPU time 93.39 seconds
Started Feb 29 01:12:06 PM PST 24
Finished Feb 29 01:13:39 PM PST 24
Peak memory 212224 kb
Host smart-b0b2d0b6-dbdf-4280-9dc0-586194e4c79a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1294267632 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_
corrupt_sig_fatal_chk.1294267632
Directory /workspace/35.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/35.rom_ctrl_kmac_err_chk.3213786483
Short name T240
Test name
Test status
Simulation time 7635522679 ps
CPU time 33.2 seconds
Started Feb 29 01:12:11 PM PST 24
Finished Feb 29 01:12:44 PM PST 24
Peak memory 212184 kb
Host smart-0c8da807-f2a9-4e7c-a0c9-d844111c33eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3213786483 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_kmac_err_chk.3213786483
Directory /workspace/35.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/35.rom_ctrl_max_throughput_chk.65743786
Short name T296
Test name
Test status
Simulation time 424085653 ps
CPU time 5.36 seconds
Started Feb 29 01:12:10 PM PST 24
Finished Feb 29 01:12:16 PM PST 24
Peak memory 211060 kb
Host smart-8cd05f64-543b-444e-9d91-d21a37abc25f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=65743786 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_max_throughput_chk.65743786
Directory /workspace/35.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/35.rom_ctrl_smoke.2989320020
Short name T5
Test name
Test status
Simulation time 1007473018 ps
CPU time 19.41 seconds
Started Feb 29 01:12:10 PM PST 24
Finished Feb 29 01:12:30 PM PST 24
Peak memory 213296 kb
Host smart-2f604930-3e44-46c3-9e7f-8885cc35774f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2989320020 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_smoke.2989320020
Directory /workspace/35.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/35.rom_ctrl_stress_all.2625879606
Short name T361
Test name
Test status
Simulation time 8092504932 ps
CPU time 35.37 seconds
Started Feb 29 01:12:10 PM PST 24
Finished Feb 29 01:12:46 PM PST 24
Peak memory 217012 kb
Host smart-057dae98-4b6b-41b1-aee7-632c2b1ccffa
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2625879606 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 35.rom_ctrl_stress_all.2625879606
Directory /workspace/35.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/36.rom_ctrl_alert_test.4018514473
Short name T312
Test name
Test status
Simulation time 2294616793 ps
CPU time 11.37 seconds
Started Feb 29 01:12:06 PM PST 24
Finished Feb 29 01:12:17 PM PST 24
Peak memory 211144 kb
Host smart-072ab9fd-cb41-4a1c-a7ce-d2fefa141072
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4018514473 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_alert_test.4018514473
Directory /workspace/36.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/36.rom_ctrl_corrupt_sig_fatal_chk.4191815432
Short name T29
Test name
Test status
Simulation time 67654652381 ps
CPU time 305.53 seconds
Started Feb 29 01:12:06 PM PST 24
Finished Feb 29 01:17:11 PM PST 24
Peak memory 230080 kb
Host smart-500efd43-a4a3-46f2-af62-0db8fca66c07
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4191815432 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_
corrupt_sig_fatal_chk.4191815432
Directory /workspace/36.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/36.rom_ctrl_kmac_err_chk.2520969132
Short name T340
Test name
Test status
Simulation time 3407086687 ps
CPU time 29.94 seconds
Started Feb 29 01:12:02 PM PST 24
Finished Feb 29 01:12:32 PM PST 24
Peak memory 211360 kb
Host smart-5177c77d-3829-464b-b396-21307bb1da39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2520969132 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_kmac_err_chk.2520969132
Directory /workspace/36.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/36.rom_ctrl_max_throughput_chk.3860350373
Short name T179
Test name
Test status
Simulation time 1333670357 ps
CPU time 7.45 seconds
Started Feb 29 01:12:07 PM PST 24
Finished Feb 29 01:12:14 PM PST 24
Peak memory 211084 kb
Host smart-4fee1d57-aeb9-4f9f-b518-32ce4a777012
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3860350373 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_max_throughput_chk.3860350373
Directory /workspace/36.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/36.rom_ctrl_smoke.3751811207
Short name T21
Test name
Test status
Simulation time 3591430125 ps
CPU time 32.79 seconds
Started Feb 29 01:12:05 PM PST 24
Finished Feb 29 01:12:38 PM PST 24
Peak memory 212480 kb
Host smart-bbe94250-b414-4117-a1ed-6d2c108e6375
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3751811207 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_smoke.3751811207
Directory /workspace/36.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/36.rom_ctrl_stress_all.1850133082
Short name T261
Test name
Test status
Simulation time 434431404 ps
CPU time 7.24 seconds
Started Feb 29 01:12:03 PM PST 24
Finished Feb 29 01:12:11 PM PST 24
Peak memory 211036 kb
Host smart-859b2435-e32d-478f-b114-55b5b5769cc6
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1850133082 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 36.rom_ctrl_stress_all.1850133082
Directory /workspace/36.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/37.rom_ctrl_alert_test.4011816332
Short name T134
Test name
Test status
Simulation time 1829831411 ps
CPU time 14.78 seconds
Started Feb 29 01:12:11 PM PST 24
Finished Feb 29 01:12:26 PM PST 24
Peak memory 211048 kb
Host smart-5d323e9c-9498-4263-8e03-04a45754edff
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4011816332 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_alert_test.4011816332
Directory /workspace/37.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/37.rom_ctrl_corrupt_sig_fatal_chk.815949447
Short name T182
Test name
Test status
Simulation time 13052513782 ps
CPU time 134.3 seconds
Started Feb 29 01:12:08 PM PST 24
Finished Feb 29 01:14:23 PM PST 24
Peak memory 212288 kb
Host smart-f83dcf8c-84ed-4072-8f53-0d95075aad5b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=815949447 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_c
orrupt_sig_fatal_chk.815949447
Directory /workspace/37.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/37.rom_ctrl_kmac_err_chk.1040904900
Short name T279
Test name
Test status
Simulation time 16718567574 ps
CPU time 32.32 seconds
Started Feb 29 01:12:07 PM PST 24
Finished Feb 29 01:12:40 PM PST 24
Peak memory 211876 kb
Host smart-6d9bdc9d-fa63-4900-b6ce-4de3dba9f735
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1040904900 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_kmac_err_chk.1040904900
Directory /workspace/37.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/37.rom_ctrl_max_throughput_chk.1660075001
Short name T306
Test name
Test status
Simulation time 2769028749 ps
CPU time 13.66 seconds
Started Feb 29 01:12:09 PM PST 24
Finished Feb 29 01:12:23 PM PST 24
Peak memory 211016 kb
Host smart-33bce57b-a6d6-42b4-97ea-1fe23595af3f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1660075001 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_max_throughput_chk.1660075001
Directory /workspace/37.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/37.rom_ctrl_smoke.351591375
Short name T125
Test name
Test status
Simulation time 2581064732 ps
CPU time 24.54 seconds
Started Feb 29 01:12:08 PM PST 24
Finished Feb 29 01:12:33 PM PST 24
Peak memory 212956 kb
Host smart-ebd20585-6860-4ef5-a145-0df1352a00cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=351591375 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_smoke.351591375
Directory /workspace/37.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/37.rom_ctrl_stress_all.1340946244
Short name T153
Test name
Test status
Simulation time 2780134316 ps
CPU time 28.97 seconds
Started Feb 29 01:12:10 PM PST 24
Finished Feb 29 01:12:40 PM PST 24
Peak memory 215080 kb
Host smart-fff5640c-909f-462c-897e-5898d4c09628
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1340946244 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 37.rom_ctrl_stress_all.1340946244
Directory /workspace/37.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/38.rom_ctrl_alert_test.1088432601
Short name T294
Test name
Test status
Simulation time 7480375295 ps
CPU time 15.65 seconds
Started Feb 29 01:12:12 PM PST 24
Finished Feb 29 01:12:28 PM PST 24
Peak memory 211196 kb
Host smart-d01da004-5002-4e34-a506-c479a46318e7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1088432601 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_alert_test.1088432601
Directory /workspace/38.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/38.rom_ctrl_corrupt_sig_fatal_chk.4276628806
Short name T168
Test name
Test status
Simulation time 135866198735 ps
CPU time 311.22 seconds
Started Feb 29 01:12:08 PM PST 24
Finished Feb 29 01:17:19 PM PST 24
Peak memory 234784 kb
Host smart-da025145-b227-4947-86a7-afd7d4adc8e4
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4276628806 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_
corrupt_sig_fatal_chk.4276628806
Directory /workspace/38.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/38.rom_ctrl_kmac_err_chk.1579774165
Short name T147
Test name
Test status
Simulation time 172253686 ps
CPU time 9.3 seconds
Started Feb 29 01:12:03 PM PST 24
Finished Feb 29 01:12:14 PM PST 24
Peak memory 211136 kb
Host smart-01ed962f-3950-433d-b250-d5a27f01ed29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1579774165 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_kmac_err_chk.1579774165
Directory /workspace/38.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/38.rom_ctrl_max_throughput_chk.2851371152
Short name T87
Test name
Test status
Simulation time 187299049 ps
CPU time 5.53 seconds
Started Feb 29 01:12:09 PM PST 24
Finished Feb 29 01:12:15 PM PST 24
Peak memory 211028 kb
Host smart-c5fc30fa-36ea-4b13-8fa7-5a151f5d4c40
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2851371152 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_max_throughput_chk.2851371152
Directory /workspace/38.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/38.rom_ctrl_smoke.3729422613
Short name T262
Test name
Test status
Simulation time 11759999706 ps
CPU time 27.7 seconds
Started Feb 29 01:12:05 PM PST 24
Finished Feb 29 01:12:33 PM PST 24
Peak memory 213696 kb
Host smart-db2177f7-b855-48d5-a801-fd24b6af8478
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3729422613 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_smoke.3729422613
Directory /workspace/38.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/38.rom_ctrl_stress_all.3945386646
Short name T348
Test name
Test status
Simulation time 4665441545 ps
CPU time 62.81 seconds
Started Feb 29 01:12:06 PM PST 24
Finished Feb 29 01:13:09 PM PST 24
Peak memory 216192 kb
Host smart-c28483b5-47d5-4d58-b226-9515b0b4ef14
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3945386646 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 38.rom_ctrl_stress_all.3945386646
Directory /workspace/38.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/39.rom_ctrl_alert_test.3447234834
Short name T270
Test name
Test status
Simulation time 832812971 ps
CPU time 7.18 seconds
Started Feb 29 01:12:08 PM PST 24
Finished Feb 29 01:12:15 PM PST 24
Peak memory 211260 kb
Host smart-4af46a18-cbcc-4c08-945e-50a898195c74
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3447234834 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_alert_test.3447234834
Directory /workspace/39.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/39.rom_ctrl_corrupt_sig_fatal_chk.3129922245
Short name T285
Test name
Test status
Simulation time 389877236675 ps
CPU time 241.43 seconds
Started Feb 29 01:12:07 PM PST 24
Finished Feb 29 01:16:09 PM PST 24
Peak memory 233896 kb
Host smart-2d973b11-71ac-43ea-b926-1fa7713b395c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3129922245 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_
corrupt_sig_fatal_chk.3129922245
Directory /workspace/39.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/39.rom_ctrl_kmac_err_chk.3174247274
Short name T167
Test name
Test status
Simulation time 4129089848 ps
CPU time 32.14 seconds
Started Feb 29 01:12:15 PM PST 24
Finished Feb 29 01:12:48 PM PST 24
Peak memory 214392 kb
Host smart-ad92718d-cfad-4bfd-8403-afa036f083cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3174247274 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_kmac_err_chk.3174247274
Directory /workspace/39.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/39.rom_ctrl_max_throughput_chk.1922013566
Short name T234
Test name
Test status
Simulation time 980818877 ps
CPU time 11.26 seconds
Started Feb 29 01:12:09 PM PST 24
Finished Feb 29 01:12:21 PM PST 24
Peak memory 211028 kb
Host smart-1b704f8a-72e1-4466-8eaf-d0a6d059c2eb
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1922013566 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_max_throughput_chk.1922013566
Directory /workspace/39.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/39.rom_ctrl_smoke.3208851435
Short name T315
Test name
Test status
Simulation time 185842598 ps
CPU time 10.2 seconds
Started Feb 29 01:12:06 PM PST 24
Finished Feb 29 01:12:16 PM PST 24
Peak memory 212788 kb
Host smart-f28f40d5-7ba5-49ee-a13d-7ae0cbf6fe28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3208851435 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_smoke.3208851435
Directory /workspace/39.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/39.rom_ctrl_stress_all.436537362
Short name T69
Test name
Test status
Simulation time 34831451930 ps
CPU time 38.32 seconds
Started Feb 29 01:12:08 PM PST 24
Finished Feb 29 01:12:46 PM PST 24
Peak memory 219380 kb
Host smart-e76338b8-2699-4c72-acf2-e8f28e9aadf0
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=436537362 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 39.rom_ctrl_stress_all.436537362
Directory /workspace/39.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/4.rom_ctrl_alert_test.210365193
Short name T355
Test name
Test status
Simulation time 6931286578 ps
CPU time 9.74 seconds
Started Feb 29 01:11:28 PM PST 24
Finished Feb 29 01:11:39 PM PST 24
Peak memory 211188 kb
Host smart-b558b7cf-300f-4d53-8f04-07edaab989f3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=210365193 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_alert_test.210365193
Directory /workspace/4.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/4.rom_ctrl_corrupt_sig_fatal_chk.2424302780
Short name T346
Test name
Test status
Simulation time 222406175688 ps
CPU time 241.51 seconds
Started Feb 29 01:11:27 PM PST 24
Finished Feb 29 01:15:29 PM PST 24
Peak memory 237496 kb
Host smart-e57bcb4f-d3dc-4f7d-8c14-6f79980a0609
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2424302780 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_c
orrupt_sig_fatal_chk.2424302780
Directory /workspace/4.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/4.rom_ctrl_kmac_err_chk.3409404907
Short name T177
Test name
Test status
Simulation time 1038262426 ps
CPU time 9.65 seconds
Started Feb 29 01:11:26 PM PST 24
Finished Feb 29 01:11:36 PM PST 24
Peak memory 211564 kb
Host smart-d0baa62e-77b7-4d1a-8b6f-784a1fe1039a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3409404907 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_kmac_err_chk.3409404907
Directory /workspace/4.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/4.rom_ctrl_max_throughput_chk.4027293836
Short name T321
Test name
Test status
Simulation time 2698622447 ps
CPU time 13.21 seconds
Started Feb 29 01:11:29 PM PST 24
Finished Feb 29 01:11:42 PM PST 24
Peak memory 211132 kb
Host smart-89f5178c-7e9b-4800-80b3-2ee0c23ba8b5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4027293836 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_max_throughput_chk.4027293836
Directory /workspace/4.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/4.rom_ctrl_sec_cm.898727096
Short name T35
Test name
Test status
Simulation time 863619830 ps
CPU time 56.31 seconds
Started Feb 29 01:11:27 PM PST 24
Finished Feb 29 01:12:24 PM PST 24
Peak memory 230960 kb
Host smart-c23e592c-65f0-40b3-a693-1cad51dfd0d5
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=898727096 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_sec_cm.898727096
Directory /workspace/4.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/4.rom_ctrl_smoke.1651450459
Short name T18
Test name
Test status
Simulation time 13736405403 ps
CPU time 36.54 seconds
Started Feb 29 01:11:25 PM PST 24
Finished Feb 29 01:12:02 PM PST 24
Peak memory 213820 kb
Host smart-4a6443cf-7313-4746-b12f-b68107f09ef8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1651450459 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_smoke.1651450459
Directory /workspace/4.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/4.rom_ctrl_stress_all.3261172241
Short name T152
Test name
Test status
Simulation time 1338376383 ps
CPU time 12.75 seconds
Started Feb 29 01:11:27 PM PST 24
Finished Feb 29 01:11:40 PM PST 24
Peak memory 210916 kb
Host smart-82307e8b-8e5a-4471-ba9e-a56b931a10e8
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3261172241 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 4.rom_ctrl_stress_all.3261172241
Directory /workspace/4.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/40.rom_ctrl_alert_test.4123271845
Short name T343
Test name
Test status
Simulation time 4985104984 ps
CPU time 11.41 seconds
Started Feb 29 01:12:21 PM PST 24
Finished Feb 29 01:12:33 PM PST 24
Peak memory 211072 kb
Host smart-55836d49-f12d-445d-8c1d-4697a37eaf15
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4123271845 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_alert_test.4123271845
Directory /workspace/40.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/40.rom_ctrl_corrupt_sig_fatal_chk.1953286289
Short name T37
Test name
Test status
Simulation time 71998546731 ps
CPU time 255.4 seconds
Started Feb 29 01:12:12 PM PST 24
Finished Feb 29 01:16:28 PM PST 24
Peak memory 212380 kb
Host smart-8a8bdd62-18d6-4498-9a71-ea7617882b3b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1953286289 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_
corrupt_sig_fatal_chk.1953286289
Directory /workspace/40.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/40.rom_ctrl_kmac_err_chk.886805706
Short name T205
Test name
Test status
Simulation time 1454716110 ps
CPU time 18.66 seconds
Started Feb 29 01:12:13 PM PST 24
Finished Feb 29 01:12:32 PM PST 24
Peak memory 211436 kb
Host smart-170a98ab-e2aa-43af-ad74-9c28de3f5f7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=886805706 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_kmac_err_chk.886805706
Directory /workspace/40.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/40.rom_ctrl_max_throughput_chk.440740438
Short name T101
Test name
Test status
Simulation time 1672863989 ps
CPU time 14.74 seconds
Started Feb 29 01:12:09 PM PST 24
Finished Feb 29 01:12:25 PM PST 24
Peak memory 211064 kb
Host smart-8008d8a7-5bd6-447a-8d42-6a41a3263bc1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=440740438 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_max_throughput_chk.440740438
Directory /workspace/40.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/40.rom_ctrl_smoke.8888485
Short name T366
Test name
Test status
Simulation time 4250095910 ps
CPU time 37.44 seconds
Started Feb 29 01:12:12 PM PST 24
Finished Feb 29 01:12:50 PM PST 24
Peak memory 213160 kb
Host smart-7f925434-5a40-4249-9957-001f7a5e72f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=8888485 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_smoke.8888485
Directory /workspace/40.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/40.rom_ctrl_stress_all.2162812906
Short name T345
Test name
Test status
Simulation time 8212539151 ps
CPU time 69.99 seconds
Started Feb 29 01:12:09 PM PST 24
Finished Feb 29 01:13:20 PM PST 24
Peak memory 219352 kb
Host smart-ebe59805-a9da-4054-afb2-324b61383c8b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2162812906 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 40.rom_ctrl_stress_all.2162812906
Directory /workspace/40.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/41.rom_ctrl_alert_test.335593874
Short name T55
Test name
Test status
Simulation time 2052687416 ps
CPU time 16.63 seconds
Started Feb 29 01:12:13 PM PST 24
Finished Feb 29 01:12:30 PM PST 24
Peak memory 210972 kb
Host smart-868951f5-929a-4f2a-be8c-fd7b97ce9311
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=335593874 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_alert_test.335593874
Directory /workspace/41.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/41.rom_ctrl_corrupt_sig_fatal_chk.710208760
Short name T245
Test name
Test status
Simulation time 89501789679 ps
CPU time 428.99 seconds
Started Feb 29 01:12:13 PM PST 24
Finished Feb 29 01:19:23 PM PST 24
Peak memory 224652 kb
Host smart-be247466-53d1-458a-927b-e3ab30c62ee0
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=710208760 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_c
orrupt_sig_fatal_chk.710208760
Directory /workspace/41.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/41.rom_ctrl_kmac_err_chk.1222677884
Short name T227
Test name
Test status
Simulation time 4421315118 ps
CPU time 16 seconds
Started Feb 29 01:12:18 PM PST 24
Finished Feb 29 01:12:34 PM PST 24
Peak memory 212188 kb
Host smart-1ccf44b4-d7f0-4aef-a528-754ac9ee3c4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1222677884 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_kmac_err_chk.1222677884
Directory /workspace/41.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/41.rom_ctrl_max_throughput_chk.3592345019
Short name T102
Test name
Test status
Simulation time 1562215071 ps
CPU time 10.06 seconds
Started Feb 29 01:12:13 PM PST 24
Finished Feb 29 01:12:24 PM PST 24
Peak memory 210708 kb
Host smart-8ef8cc08-397c-495f-9b06-39d91f43ef3e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3592345019 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_max_throughput_chk.3592345019
Directory /workspace/41.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/41.rom_ctrl_smoke.4110264932
Short name T232
Test name
Test status
Simulation time 37468324272 ps
CPU time 30.45 seconds
Started Feb 29 01:12:15 PM PST 24
Finished Feb 29 01:12:46 PM PST 24
Peak memory 213840 kb
Host smart-0d277d63-aba4-4224-ac8e-c2da8adf90d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4110264932 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_smoke.4110264932
Directory /workspace/41.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/41.rom_ctrl_stress_all.1240716988
Short name T325
Test name
Test status
Simulation time 409587786 ps
CPU time 22.53 seconds
Started Feb 29 01:12:19 PM PST 24
Finished Feb 29 01:12:42 PM PST 24
Peak memory 216156 kb
Host smart-09b47eb4-3c07-433e-a240-dcf68b0fa999
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1240716988 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 41.rom_ctrl_stress_all.1240716988
Directory /workspace/41.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/41.rom_ctrl_stress_all_with_rand_reset.3941366389
Short name T344
Test name
Test status
Simulation time 198405879716 ps
CPU time 1907.65 seconds
Started Feb 29 01:12:22 PM PST 24
Finished Feb 29 01:44:10 PM PST 24
Peak memory 238644 kb
Host smart-97fd7908-0c23-4341-ae23-2cea1ceae6b3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3941366389 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_stress_all_with_rand_reset.3941366389
Directory /workspace/41.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.rom_ctrl_alert_test.3908986718
Short name T10
Test name
Test status
Simulation time 2138864445 ps
CPU time 10.71 seconds
Started Feb 29 01:12:21 PM PST 24
Finished Feb 29 01:12:32 PM PST 24
Peak memory 211040 kb
Host smart-38db444a-881a-4d50-8120-741ddf0fbb98
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3908986718 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_alert_test.3908986718
Directory /workspace/42.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/42.rom_ctrl_corrupt_sig_fatal_chk.2548938534
Short name T6
Test name
Test status
Simulation time 143241340508 ps
CPU time 428.79 seconds
Started Feb 29 01:12:07 PM PST 24
Finished Feb 29 01:19:16 PM PST 24
Peak memory 212472 kb
Host smart-cc60f244-db6a-480f-b653-6569939e7628
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2548938534 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_
corrupt_sig_fatal_chk.2548938534
Directory /workspace/42.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/42.rom_ctrl_kmac_err_chk.4254131827
Short name T374
Test name
Test status
Simulation time 172129447 ps
CPU time 9.48 seconds
Started Feb 29 01:12:14 PM PST 24
Finished Feb 29 01:12:23 PM PST 24
Peak memory 211568 kb
Host smart-a61b18a5-e3df-4a06-94a7-819090d64bb1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4254131827 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_kmac_err_chk.4254131827
Directory /workspace/42.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/42.rom_ctrl_max_throughput_chk.3650908995
Short name T132
Test name
Test status
Simulation time 190191875 ps
CPU time 5.53 seconds
Started Feb 29 01:12:22 PM PST 24
Finished Feb 29 01:12:28 PM PST 24
Peak memory 210968 kb
Host smart-faf48cb3-c3c1-44d7-8c81-3ff4ef80705e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3650908995 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_max_throughput_chk.3650908995
Directory /workspace/42.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/42.rom_ctrl_smoke.3070222985
Short name T155
Test name
Test status
Simulation time 10303903724 ps
CPU time 27.75 seconds
Started Feb 29 01:12:21 PM PST 24
Finished Feb 29 01:12:49 PM PST 24
Peak memory 213860 kb
Host smart-aac1dd14-ee2f-4df8-8787-231af7c7e7e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3070222985 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_smoke.3070222985
Directory /workspace/42.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/42.rom_ctrl_stress_all.4263587467
Short name T223
Test name
Test status
Simulation time 4590819848 ps
CPU time 19.4 seconds
Started Feb 29 01:12:20 PM PST 24
Finished Feb 29 01:12:40 PM PST 24
Peak memory 213760 kb
Host smart-df23a2ca-7b69-4af6-8a78-de861dd1d885
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4263587467 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 42.rom_ctrl_stress_all.4263587467
Directory /workspace/42.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/43.rom_ctrl_alert_test.2830102504
Short name T333
Test name
Test status
Simulation time 1150718778 ps
CPU time 11.05 seconds
Started Feb 29 01:12:11 PM PST 24
Finished Feb 29 01:12:22 PM PST 24
Peak memory 211076 kb
Host smart-6e6d6878-da66-4dc3-8950-df73fde85d89
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2830102504 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_alert_test.2830102504
Directory /workspace/43.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/43.rom_ctrl_corrupt_sig_fatal_chk.509535714
Short name T328
Test name
Test status
Simulation time 150500786653 ps
CPU time 292.85 seconds
Started Feb 29 01:12:14 PM PST 24
Finished Feb 29 01:17:07 PM PST 24
Peak memory 213348 kb
Host smart-fb35beda-0a80-4687-9445-e1b56955fc7f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=509535714 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_c
orrupt_sig_fatal_chk.509535714
Directory /workspace/43.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/43.rom_ctrl_kmac_err_chk.3397507930
Short name T28
Test name
Test status
Simulation time 10705587145 ps
CPU time 18.87 seconds
Started Feb 29 01:12:22 PM PST 24
Finished Feb 29 01:12:41 PM PST 24
Peak memory 211696 kb
Host smart-432e76c7-afe6-4c54-b866-08d1db694d07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3397507930 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_kmac_err_chk.3397507930
Directory /workspace/43.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/43.rom_ctrl_max_throughput_chk.540905736
Short name T45
Test name
Test status
Simulation time 3528383711 ps
CPU time 8.74 seconds
Started Feb 29 01:12:20 PM PST 24
Finished Feb 29 01:12:30 PM PST 24
Peak memory 211072 kb
Host smart-01002941-e0a3-4203-acdf-c9123750c6c3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=540905736 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_max_throughput_chk.540905736
Directory /workspace/43.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/43.rom_ctrl_smoke.3926655652
Short name T357
Test name
Test status
Simulation time 3981375808 ps
CPU time 33.27 seconds
Started Feb 29 01:12:09 PM PST 24
Finished Feb 29 01:12:43 PM PST 24
Peak memory 213052 kb
Host smart-e2cca4c4-cb0e-445b-9549-f0fcbcea5964
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3926655652 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_smoke.3926655652
Directory /workspace/43.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/43.rom_ctrl_stress_all.3705097245
Short name T253
Test name
Test status
Simulation time 1799860702 ps
CPU time 28.49 seconds
Started Feb 29 01:12:21 PM PST 24
Finished Feb 29 01:12:50 PM PST 24
Peak memory 214896 kb
Host smart-eee371e4-74fc-4a9f-a638-703b5dbae1e6
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3705097245 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 43.rom_ctrl_stress_all.3705097245
Directory /workspace/43.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/43.rom_ctrl_stress_all_with_rand_reset.2006315942
Short name T108
Test name
Test status
Simulation time 275556313596 ps
CPU time 2610.05 seconds
Started Feb 29 01:12:09 PM PST 24
Finished Feb 29 01:55:39 PM PST 24
Peak memory 250788 kb
Host smart-7681b0d7-3e52-4d9e-8ea4-729db63ca552
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2006315942 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_stress_all_with_rand_reset.2006315942
Directory /workspace/43.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.rom_ctrl_alert_test.3427680038
Short name T85
Test name
Test status
Simulation time 8800633419 ps
CPU time 16.42 seconds
Started Feb 29 01:12:12 PM PST 24
Finished Feb 29 01:12:28 PM PST 24
Peak memory 211140 kb
Host smart-53fd0439-ff64-4119-96b1-76ba9cd5c245
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3427680038 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_alert_test.3427680038
Directory /workspace/44.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/44.rom_ctrl_corrupt_sig_fatal_chk.2106435959
Short name T250
Test name
Test status
Simulation time 51731077890 ps
CPU time 226.94 seconds
Started Feb 29 01:12:22 PM PST 24
Finished Feb 29 01:16:10 PM PST 24
Peak memory 228520 kb
Host smart-64bcfae0-6c69-4f56-bebe-548d596d9137
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2106435959 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_
corrupt_sig_fatal_chk.2106435959
Directory /workspace/44.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/44.rom_ctrl_kmac_err_chk.487685394
Short name T349
Test name
Test status
Simulation time 24576156267 ps
CPU time 27.88 seconds
Started Feb 29 01:12:14 PM PST 24
Finished Feb 29 01:12:42 PM PST 24
Peak memory 211792 kb
Host smart-ae38dae4-59bb-47cd-be75-a573138e2c6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=487685394 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_kmac_err_chk.487685394
Directory /workspace/44.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/44.rom_ctrl_max_throughput_chk.2712154756
Short name T103
Test name
Test status
Simulation time 2766459796 ps
CPU time 12.34 seconds
Started Feb 29 01:12:22 PM PST 24
Finished Feb 29 01:12:35 PM PST 24
Peak memory 211008 kb
Host smart-0ee87966-7510-467f-9604-a6bf99d64988
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2712154756 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_max_throughput_chk.2712154756
Directory /workspace/44.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/44.rom_ctrl_smoke.2602244944
Short name T86
Test name
Test status
Simulation time 730162415 ps
CPU time 10.12 seconds
Started Feb 29 01:12:14 PM PST 24
Finished Feb 29 01:12:24 PM PST 24
Peak memory 212992 kb
Host smart-cfd6b1c2-dafa-425b-b2c6-50288ee57bd0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2602244944 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_smoke.2602244944
Directory /workspace/44.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/44.rom_ctrl_stress_all.379950631
Short name T162
Test name
Test status
Simulation time 41848408626 ps
CPU time 36.66 seconds
Started Feb 29 01:12:22 PM PST 24
Finished Feb 29 01:12:59 PM PST 24
Peak memory 216836 kb
Host smart-a0c9d059-7504-4110-a7d3-e412abfd3327
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=379950631 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 44.rom_ctrl_stress_all.379950631
Directory /workspace/44.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/44.rom_ctrl_stress_all_with_rand_reset.1713678149
Short name T352
Test name
Test status
Simulation time 172313929049 ps
CPU time 3608.54 seconds
Started Feb 29 01:12:10 PM PST 24
Finished Feb 29 02:12:19 PM PST 24
Peak memory 235420 kb
Host smart-29f2ed69-7bb0-44ff-a858-521f43aefbc2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1713678149 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_stress_all_with_rand_reset.1713678149
Directory /workspace/44.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.rom_ctrl_alert_test.1861942154
Short name T154
Test name
Test status
Simulation time 348009303 ps
CPU time 4.13 seconds
Started Feb 29 01:12:20 PM PST 24
Finished Feb 29 01:12:25 PM PST 24
Peak memory 210948 kb
Host smart-0b384b45-b10b-4fd3-a9fd-bc6d2c850694
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1861942154 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_alert_test.1861942154
Directory /workspace/45.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/45.rom_ctrl_corrupt_sig_fatal_chk.1905938561
Short name T256
Test name
Test status
Simulation time 21902983786 ps
CPU time 130.69 seconds
Started Feb 29 01:12:14 PM PST 24
Finished Feb 29 01:14:25 PM PST 24
Peak memory 219168 kb
Host smart-47f77c0b-3c6b-4a28-b6b8-6e1ad7b2259d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1905938561 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_
corrupt_sig_fatal_chk.1905938561
Directory /workspace/45.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/45.rom_ctrl_kmac_err_chk.2711596160
Short name T281
Test name
Test status
Simulation time 1111799978 ps
CPU time 16.08 seconds
Started Feb 29 01:12:20 PM PST 24
Finished Feb 29 01:12:37 PM PST 24
Peak memory 211444 kb
Host smart-bf9340a6-2c8e-4478-bd95-d95283cc9dfc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2711596160 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_kmac_err_chk.2711596160
Directory /workspace/45.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/45.rom_ctrl_max_throughput_chk.918202229
Short name T347
Test name
Test status
Simulation time 384110853 ps
CPU time 5.46 seconds
Started Feb 29 01:12:22 PM PST 24
Finished Feb 29 01:12:28 PM PST 24
Peak memory 210860 kb
Host smart-2acf7406-dd56-49d4-93fa-107ddb13512e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=918202229 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_max_throughput_chk.918202229
Directory /workspace/45.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/45.rom_ctrl_smoke.27873517
Short name T175
Test name
Test status
Simulation time 4393348762 ps
CPU time 23.78 seconds
Started Feb 29 01:12:12 PM PST 24
Finished Feb 29 01:12:36 PM PST 24
Peak memory 213780 kb
Host smart-4fe6562a-68a6-4c4b-8db3-447e612733d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=27873517 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_smoke.27873517
Directory /workspace/45.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/45.rom_ctrl_stress_all.3755351359
Short name T339
Test name
Test status
Simulation time 8878763668 ps
CPU time 43.08 seconds
Started Feb 29 01:12:08 PM PST 24
Finished Feb 29 01:12:52 PM PST 24
Peak memory 217408 kb
Host smart-53089fc1-2a06-4223-b418-892ecb7e07ae
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3755351359 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 45.rom_ctrl_stress_all.3755351359
Directory /workspace/45.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/45.rom_ctrl_stress_all_with_rand_reset.2221590467
Short name T16
Test name
Test status
Simulation time 15831117621 ps
CPU time 2368.56 seconds
Started Feb 29 01:12:14 PM PST 24
Finished Feb 29 01:51:43 PM PST 24
Peak memory 227976 kb
Host smart-937016da-f835-4e74-989d-2ccd67666be4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2221590467 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_stress_all_with_rand_reset.2221590467
Directory /workspace/45.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.rom_ctrl_alert_test.1656781410
Short name T353
Test name
Test status
Simulation time 88978804 ps
CPU time 4.19 seconds
Started Feb 29 01:12:08 PM PST 24
Finished Feb 29 01:12:13 PM PST 24
Peak memory 211036 kb
Host smart-761e0c64-a7d1-46a1-890b-5be717b9b1cb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1656781410 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_alert_test.1656781410
Directory /workspace/46.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/46.rom_ctrl_corrupt_sig_fatal_chk.4072962892
Short name T121
Test name
Test status
Simulation time 11531896911 ps
CPU time 200.57 seconds
Started Feb 29 01:12:04 PM PST 24
Finished Feb 29 01:15:25 PM PST 24
Peak memory 228556 kb
Host smart-2d82b001-c950-4982-9fb0-5b4689fefc36
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4072962892 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_
corrupt_sig_fatal_chk.4072962892
Directory /workspace/46.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/46.rom_ctrl_kmac_err_chk.46691637
Short name T91
Test name
Test status
Simulation time 13511280193 ps
CPU time 29.67 seconds
Started Feb 29 01:12:05 PM PST 24
Finished Feb 29 01:12:34 PM PST 24
Peak memory 212168 kb
Host smart-256abdc6-42ba-4151-9da4-033ccdcd2f15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=46691637 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_kmac_err_chk.46691637
Directory /workspace/46.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/46.rom_ctrl_max_throughput_chk.512412642
Short name T239
Test name
Test status
Simulation time 1102096857 ps
CPU time 7.12 seconds
Started Feb 29 01:12:11 PM PST 24
Finished Feb 29 01:12:18 PM PST 24
Peak memory 211048 kb
Host smart-a80e3f6b-0bcd-4dba-86ca-0580abfc6fd3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=512412642 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_max_throughput_chk.512412642
Directory /workspace/46.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/46.rom_ctrl_smoke.3630307140
Short name T68
Test name
Test status
Simulation time 4168037190 ps
CPU time 42.77 seconds
Started Feb 29 01:12:14 PM PST 24
Finished Feb 29 01:12:57 PM PST 24
Peak memory 213284 kb
Host smart-51d99b8e-8315-4179-a5ca-73e0b2db687a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3630307140 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_smoke.3630307140
Directory /workspace/46.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/46.rom_ctrl_stress_all.3216026220
Short name T331
Test name
Test status
Simulation time 3015656417 ps
CPU time 12.39 seconds
Started Feb 29 01:12:10 PM PST 24
Finished Feb 29 01:12:23 PM PST 24
Peak memory 211144 kb
Host smart-f1c6b0d4-7c88-40dd-844d-95395ccee817
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3216026220 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 46.rom_ctrl_stress_all.3216026220
Directory /workspace/46.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/46.rom_ctrl_stress_all_with_rand_reset.2053817888
Short name T43
Test name
Test status
Simulation time 86943421949 ps
CPU time 946.66 seconds
Started Feb 29 01:12:10 PM PST 24
Finished Feb 29 01:27:57 PM PST 24
Peak memory 234704 kb
Host smart-b4ea8db1-b010-47e7-b706-abe148876732
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2053817888 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_stress_all_with_rand_reset.2053817888
Directory /workspace/46.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.rom_ctrl_alert_test.4098730992
Short name T304
Test name
Test status
Simulation time 2596119141 ps
CPU time 12.12 seconds
Started Feb 29 01:12:17 PM PST 24
Finished Feb 29 01:12:30 PM PST 24
Peak memory 211268 kb
Host smart-a07a6bf3-120d-4b31-b46e-858f70e0cc60
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4098730992 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_alert_test.4098730992
Directory /workspace/47.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/47.rom_ctrl_kmac_err_chk.112276982
Short name T141
Test name
Test status
Simulation time 5179561576 ps
CPU time 31.5 seconds
Started Feb 29 01:12:13 PM PST 24
Finished Feb 29 01:12:45 PM PST 24
Peak memory 211856 kb
Host smart-2bae42d8-ca45-40d1-8dd7-948109465d87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=112276982 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_kmac_err_chk.112276982
Directory /workspace/47.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/47.rom_ctrl_max_throughput_chk.3712279101
Short name T257
Test name
Test status
Simulation time 19057362099 ps
CPU time 10.98 seconds
Started Feb 29 01:12:15 PM PST 24
Finished Feb 29 01:12:27 PM PST 24
Peak memory 211344 kb
Host smart-56fee844-90d8-4c7a-813b-55f7246bad2b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3712279101 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_max_throughput_chk.3712279101
Directory /workspace/47.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/47.rom_ctrl_smoke.4172801826
Short name T67
Test name
Test status
Simulation time 1970782669 ps
CPU time 23.91 seconds
Started Feb 29 01:12:13 PM PST 24
Finished Feb 29 01:12:37 PM PST 24
Peak memory 212792 kb
Host smart-04cd764f-8589-4c37-85d5-72d07b7b3431
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4172801826 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_smoke.4172801826
Directory /workspace/47.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/47.rom_ctrl_stress_all.1346193376
Short name T185
Test name
Test status
Simulation time 28803529413 ps
CPU time 78.05 seconds
Started Feb 29 01:12:15 PM PST 24
Finished Feb 29 01:13:34 PM PST 24
Peak memory 219532 kb
Host smart-2a44fd0b-e70b-4c37-b7eb-32e0566955d3
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1346193376 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 47.rom_ctrl_stress_all.1346193376
Directory /workspace/47.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/48.rom_ctrl_alert_test.2906678514
Short name T34
Test name
Test status
Simulation time 1539533644 ps
CPU time 12.98 seconds
Started Feb 29 01:12:29 PM PST 24
Finished Feb 29 01:12:42 PM PST 24
Peak memory 211256 kb
Host smart-54489fa2-d849-4a6d-a41d-dbefc484729a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2906678514 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_alert_test.2906678514
Directory /workspace/48.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/48.rom_ctrl_corrupt_sig_fatal_chk.703263606
Short name T277
Test name
Test status
Simulation time 7618557823 ps
CPU time 128.2 seconds
Started Feb 29 01:12:28 PM PST 24
Finished Feb 29 01:14:37 PM PST 24
Peak memory 228468 kb
Host smart-886891db-ccb9-43ec-9f2f-6252b317ace1
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=703263606 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_c
orrupt_sig_fatal_chk.703263606
Directory /workspace/48.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/48.rom_ctrl_kmac_err_chk.3662429858
Short name T293
Test name
Test status
Simulation time 6841121096 ps
CPU time 19.58 seconds
Started Feb 29 01:12:28 PM PST 24
Finished Feb 29 01:12:48 PM PST 24
Peak memory 212680 kb
Host smart-80345526-9e2d-4d0e-beb8-396d0c959dbd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3662429858 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_kmac_err_chk.3662429858
Directory /workspace/48.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/48.rom_ctrl_max_throughput_chk.3022061896
Short name T275
Test name
Test status
Simulation time 6903847817 ps
CPU time 15.56 seconds
Started Feb 29 01:12:07 PM PST 24
Finished Feb 29 01:12:23 PM PST 24
Peak memory 211192 kb
Host smart-f64bc94c-626f-4a54-8020-85ffc86d436c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3022061896 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_max_throughput_chk.3022061896
Directory /workspace/48.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/48.rom_ctrl_smoke.2239103156
Short name T128
Test name
Test status
Simulation time 10842945860 ps
CPU time 22.58 seconds
Started Feb 29 01:12:05 PM PST 24
Finished Feb 29 01:12:28 PM PST 24
Peak memory 213980 kb
Host smart-cf5e2fee-670d-4949-81a3-6e2d6d03f2b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2239103156 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_smoke.2239103156
Directory /workspace/48.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/48.rom_ctrl_stress_all.1084190946
Short name T188
Test name
Test status
Simulation time 23165493322 ps
CPU time 51.87 seconds
Started Feb 29 01:12:13 PM PST 24
Finished Feb 29 01:13:05 PM PST 24
Peak memory 214856 kb
Host smart-2a011cd3-4e88-4141-9c36-6fd714408e01
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1084190946 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 48.rom_ctrl_stress_all.1084190946
Directory /workspace/48.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/49.rom_ctrl_alert_test.1961947812
Short name T144
Test name
Test status
Simulation time 27470839170 ps
CPU time 16 seconds
Started Feb 29 01:12:15 PM PST 24
Finished Feb 29 01:12:31 PM PST 24
Peak memory 211152 kb
Host smart-3c26e1bb-dbdb-4724-9a89-bbca7504353e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1961947812 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_alert_test.1961947812
Directory /workspace/49.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/49.rom_ctrl_corrupt_sig_fatal_chk.678386954
Short name T311
Test name
Test status
Simulation time 5154258887 ps
CPU time 130.73 seconds
Started Feb 29 01:12:16 PM PST 24
Finished Feb 29 01:14:27 PM PST 24
Peak memory 236764 kb
Host smart-55d00248-054b-40ed-bf34-33074e599365
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=678386954 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_c
orrupt_sig_fatal_chk.678386954
Directory /workspace/49.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/49.rom_ctrl_kmac_err_chk.1256721529
Short name T210
Test name
Test status
Simulation time 169207779 ps
CPU time 9.65 seconds
Started Feb 29 01:12:13 PM PST 24
Finished Feb 29 01:12:23 PM PST 24
Peak memory 211832 kb
Host smart-564d24f6-7d16-4484-9b9f-d1e8fa11c6c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1256721529 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_kmac_err_chk.1256721529
Directory /workspace/49.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/49.rom_ctrl_max_throughput_chk.2465803147
Short name T130
Test name
Test status
Simulation time 4167458813 ps
CPU time 8.41 seconds
Started Feb 29 01:12:28 PM PST 24
Finished Feb 29 01:12:37 PM PST 24
Peak memory 211288 kb
Host smart-72f3cdd3-9990-49e3-87f6-a78e8aa1fa2a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2465803147 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_max_throughput_chk.2465803147
Directory /workspace/49.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/49.rom_ctrl_smoke.1975783480
Short name T209
Test name
Test status
Simulation time 565002349 ps
CPU time 9.82 seconds
Started Feb 29 01:12:22 PM PST 24
Finished Feb 29 01:12:32 PM PST 24
Peak memory 212844 kb
Host smart-5737464f-1845-4626-afa5-a8080fd8d4d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1975783480 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_smoke.1975783480
Directory /workspace/49.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/49.rom_ctrl_stress_all.1836210939
Short name T282
Test name
Test status
Simulation time 4029347378 ps
CPU time 37.81 seconds
Started Feb 29 01:12:14 PM PST 24
Finished Feb 29 01:12:52 PM PST 24
Peak memory 219164 kb
Host smart-8bb2309b-f257-4e2f-bb38-a4a4ce1819b8
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1836210939 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 49.rom_ctrl_stress_all.1836210939
Directory /workspace/49.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/49.rom_ctrl_stress_all_with_rand_reset.29060396
Short name T107
Test name
Test status
Simulation time 314138084654 ps
CPU time 1467.77 seconds
Started Feb 29 01:12:16 PM PST 24
Finished Feb 29 01:36:44 PM PST 24
Peak memory 238852 kb
Host smart-e87c72d7-06ba-44fa-a044-e34f48eac016
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29060396 -assert nopos
tproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_stress_all_with_rand_reset.29060396
Directory /workspace/49.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.rom_ctrl_alert_test.1649722182
Short name T368
Test name
Test status
Simulation time 1167205257 ps
CPU time 11.4 seconds
Started Feb 29 01:11:24 PM PST 24
Finished Feb 29 01:11:37 PM PST 24
Peak memory 211044 kb
Host smart-1c167794-8295-4317-b583-89eb68f05c6f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1649722182 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_alert_test.1649722182
Directory /workspace/5.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/5.rom_ctrl_corrupt_sig_fatal_chk.726496504
Short name T322
Test name
Test status
Simulation time 38610211850 ps
CPU time 329.85 seconds
Started Feb 29 01:11:24 PM PST 24
Finished Feb 29 01:16:55 PM PST 24
Peak memory 237732 kb
Host smart-146d67ed-2e43-4582-aa0a-ae1b3c6a660f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=726496504 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_co
rrupt_sig_fatal_chk.726496504
Directory /workspace/5.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/5.rom_ctrl_kmac_err_chk.3134191843
Short name T163
Test name
Test status
Simulation time 8533324797 ps
CPU time 22.94 seconds
Started Feb 29 01:11:22 PM PST 24
Finished Feb 29 01:11:46 PM PST 24
Peak memory 212248 kb
Host smart-b931db7d-46ae-4ce3-be75-35b2dbaba8bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3134191843 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_kmac_err_chk.3134191843
Directory /workspace/5.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/5.rom_ctrl_max_throughput_chk.3440024716
Short name T280
Test name
Test status
Simulation time 185644359 ps
CPU time 5.51 seconds
Started Feb 29 01:11:26 PM PST 24
Finished Feb 29 01:11:32 PM PST 24
Peak memory 211032 kb
Host smart-bdd09da9-ea00-42ef-bfdd-c88690b1834c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3440024716 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_max_throughput_chk.3440024716
Directory /workspace/5.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/5.rom_ctrl_smoke.776027221
Short name T2
Test name
Test status
Simulation time 8749125155 ps
CPU time 17.91 seconds
Started Feb 29 01:11:26 PM PST 24
Finished Feb 29 01:11:45 PM PST 24
Peak memory 219308 kb
Host smart-42ad5df5-b335-4ea0-a21a-c7b949d6d5db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=776027221 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_smoke.776027221
Directory /workspace/5.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/5.rom_ctrl_stress_all.2810610846
Short name T160
Test name
Test status
Simulation time 24332308237 ps
CPU time 81.99 seconds
Started Feb 29 01:11:28 PM PST 24
Finished Feb 29 01:12:50 PM PST 24
Peak memory 219368 kb
Host smart-5bef4cdf-3415-45a2-a2e7-f77829fb2b28
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2810610846 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 5.rom_ctrl_stress_all.2810610846
Directory /workspace/5.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/6.rom_ctrl_alert_test.3186698457
Short name T46
Test name
Test status
Simulation time 2914637818 ps
CPU time 12.3 seconds
Started Feb 29 01:11:26 PM PST 24
Finished Feb 29 01:11:39 PM PST 24
Peak memory 211108 kb
Host smart-9d998ac6-c5e8-43bd-bc8d-3a78ef5934f1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3186698457 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_alert_test.3186698457
Directory /workspace/6.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/6.rom_ctrl_corrupt_sig_fatal_chk.2458827730
Short name T156
Test name
Test status
Simulation time 64228536915 ps
CPU time 172.04 seconds
Started Feb 29 01:11:26 PM PST 24
Finished Feb 29 01:14:18 PM PST 24
Peak memory 237632 kb
Host smart-a8b14af4-5652-4c9f-83c5-fa0aff72d2d3
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2458827730 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_c
orrupt_sig_fatal_chk.2458827730
Directory /workspace/6.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/6.rom_ctrl_kmac_err_chk.1778554369
Short name T26
Test name
Test status
Simulation time 22962579295 ps
CPU time 24.25 seconds
Started Feb 29 01:11:28 PM PST 24
Finished Feb 29 01:11:52 PM PST 24
Peak memory 212104 kb
Host smart-aeb64503-cf7f-4acc-9e91-d92ebf65e87b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1778554369 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_kmac_err_chk.1778554369
Directory /workspace/6.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/6.rom_ctrl_max_throughput_chk.777658837
Short name T235
Test name
Test status
Simulation time 2086695912 ps
CPU time 8.49 seconds
Started Feb 29 01:11:25 PM PST 24
Finished Feb 29 01:11:34 PM PST 24
Peak memory 210900 kb
Host smart-1ceeb389-5b4d-4735-a56b-2eff5d3bba67
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=777658837 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_max_throughput_chk.777658837
Directory /workspace/6.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/6.rom_ctrl_smoke.2385958884
Short name T218
Test name
Test status
Simulation time 34481038639 ps
CPU time 37.02 seconds
Started Feb 29 01:11:25 PM PST 24
Finished Feb 29 01:12:02 PM PST 24
Peak memory 214092 kb
Host smart-99af103a-a6d5-4da8-bff9-89e8dc4dd2a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2385958884 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_smoke.2385958884
Directory /workspace/6.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/7.rom_ctrl_alert_test.870497100
Short name T225
Test name
Test status
Simulation time 2086974883 ps
CPU time 15.55 seconds
Started Feb 29 01:11:41 PM PST 24
Finished Feb 29 01:11:57 PM PST 24
Peak memory 211040 kb
Host smart-19cb81e7-993e-4368-b645-b2d533856656
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=870497100 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_alert_test.870497100
Directory /workspace/7.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/7.rom_ctrl_corrupt_sig_fatal_chk.3627397780
Short name T196
Test name
Test status
Simulation time 17173976709 ps
CPU time 193.25 seconds
Started Feb 29 01:11:30 PM PST 24
Finished Feb 29 01:14:43 PM PST 24
Peak memory 229724 kb
Host smart-0998c310-1b31-40c7-8cc2-1223837e84b9
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3627397780 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_c
orrupt_sig_fatal_chk.3627397780
Directory /workspace/7.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/7.rom_ctrl_kmac_err_chk.3420950372
Short name T330
Test name
Test status
Simulation time 168531020 ps
CPU time 9.54 seconds
Started Feb 29 01:11:41 PM PST 24
Finished Feb 29 01:11:50 PM PST 24
Peak memory 211592 kb
Host smart-1677712b-d941-4e42-b222-d8502a994118
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3420950372 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_kmac_err_chk.3420950372
Directory /workspace/7.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/7.rom_ctrl_max_throughput_chk.1454036736
Short name T183
Test name
Test status
Simulation time 681989685 ps
CPU time 6.22 seconds
Started Feb 29 01:11:23 PM PST 24
Finished Feb 29 01:11:30 PM PST 24
Peak memory 211080 kb
Host smart-7b4a4ec7-f00e-4deb-b14c-1d95269f6845
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1454036736 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_max_throughput_chk.1454036736
Directory /workspace/7.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/7.rom_ctrl_smoke.642748673
Short name T159
Test name
Test status
Simulation time 2404615939 ps
CPU time 25.12 seconds
Started Feb 29 01:11:27 PM PST 24
Finished Feb 29 01:11:52 PM PST 24
Peak memory 213124 kb
Host smart-e084eb40-6be7-4460-8426-72e6872789e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=642748673 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_smoke.642748673
Directory /workspace/7.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/7.rom_ctrl_stress_all.3671226981
Short name T192
Test name
Test status
Simulation time 299122874 ps
CPU time 17.43 seconds
Started Feb 29 01:11:26 PM PST 24
Finished Feb 29 01:11:44 PM PST 24
Peak memory 214460 kb
Host smart-e451a095-cc59-4cfe-9431-fbd8ae429e56
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3671226981 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 7.rom_ctrl_stress_all.3671226981
Directory /workspace/7.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/8.rom_ctrl_alert_test.3133057239
Short name T308
Test name
Test status
Simulation time 1629066012 ps
CPU time 13.94 seconds
Started Feb 29 01:11:38 PM PST 24
Finished Feb 29 01:11:52 PM PST 24
Peak memory 211076 kb
Host smart-ca30800d-86b6-44ec-985f-5c577b30f32f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3133057239 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_alert_test.3133057239
Directory /workspace/8.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/8.rom_ctrl_corrupt_sig_fatal_chk.3819344526
Short name T329
Test name
Test status
Simulation time 28097171774 ps
CPU time 328.57 seconds
Started Feb 29 01:11:40 PM PST 24
Finished Feb 29 01:17:09 PM PST 24
Peak memory 228544 kb
Host smart-7d265387-2dee-4ca3-8b4c-b21a3d8c56c7
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3819344526 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_c
orrupt_sig_fatal_chk.3819344526
Directory /workspace/8.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/8.rom_ctrl_kmac_err_chk.3855515313
Short name T203
Test name
Test status
Simulation time 724007386 ps
CPU time 9.6 seconds
Started Feb 29 01:11:38 PM PST 24
Finished Feb 29 01:11:47 PM PST 24
Peak memory 211228 kb
Host smart-514e3eb4-11ce-47bb-a9b5-8897bb417bcd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3855515313 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_kmac_err_chk.3855515313
Directory /workspace/8.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/8.rom_ctrl_max_throughput_chk.2029491544
Short name T213
Test name
Test status
Simulation time 615447041 ps
CPU time 8.93 seconds
Started Feb 29 01:11:40 PM PST 24
Finished Feb 29 01:11:49 PM PST 24
Peak memory 210916 kb
Host smart-82573a50-d4aa-4daa-b7c0-7d35ff1265ef
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2029491544 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_max_throughput_chk.2029491544
Directory /workspace/8.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/8.rom_ctrl_smoke.2643064235
Short name T214
Test name
Test status
Simulation time 380028549 ps
CPU time 10.25 seconds
Started Feb 29 01:11:41 PM PST 24
Finished Feb 29 01:11:51 PM PST 24
Peak memory 213348 kb
Host smart-db63065f-7c53-4af9-b18f-45a73423dd2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2643064235 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_smoke.2643064235
Directory /workspace/8.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/8.rom_ctrl_stress_all.129928745
Short name T354
Test name
Test status
Simulation time 8020104433 ps
CPU time 34.45 seconds
Started Feb 29 01:11:40 PM PST 24
Finished Feb 29 01:12:14 PM PST 24
Peak memory 218660 kb
Host smart-f4635f31-6926-4b29-bfdf-ea482143183b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=129928745 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 8.rom_ctrl_stress_all.129928745
Directory /workspace/8.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/9.rom_ctrl_alert_test.1074977296
Short name T248
Test name
Test status
Simulation time 1245602200 ps
CPU time 9.46 seconds
Started Feb 29 01:11:42 PM PST 24
Finished Feb 29 01:11:51 PM PST 24
Peak memory 211052 kb
Host smart-9df4017f-05d3-430c-a304-3b2d3bdaf684
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1074977296 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_alert_test.1074977296
Directory /workspace/9.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/9.rom_ctrl_corrupt_sig_fatal_chk.79925451
Short name T31
Test name
Test status
Simulation time 10295549151 ps
CPU time 148.08 seconds
Started Feb 29 01:11:40 PM PST 24
Finished Feb 29 01:14:08 PM PST 24
Peak memory 212668 kb
Host smart-19675307-2aa5-4073-b4e5-14956fb75e18
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=79925451 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_
sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_cor
rupt_sig_fatal_chk.79925451
Directory /workspace/9.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/9.rom_ctrl_kmac_err_chk.800956801
Short name T295
Test name
Test status
Simulation time 3029446941 ps
CPU time 23.3 seconds
Started Feb 29 01:11:41 PM PST 24
Finished Feb 29 01:12:04 PM PST 24
Peak memory 211444 kb
Host smart-55ee84ac-0cac-4cc3-8e88-66aeeca66faa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=800956801 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_kmac_err_chk.800956801
Directory /workspace/9.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/9.rom_ctrl_max_throughput_chk.1932953957
Short name T47
Test name
Test status
Simulation time 694783666 ps
CPU time 9.76 seconds
Started Feb 29 01:11:40 PM PST 24
Finished Feb 29 01:11:49 PM PST 24
Peak memory 211024 kb
Host smart-32ca5bda-7539-4876-bf52-5e8628e56cc0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1932953957 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_max_throughput_chk.1932953957
Directory /workspace/9.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/9.rom_ctrl_smoke.1315142922
Short name T143
Test name
Test status
Simulation time 1082441047 ps
CPU time 16.94 seconds
Started Feb 29 01:11:41 PM PST 24
Finished Feb 29 01:11:59 PM PST 24
Peak memory 212716 kb
Host smart-a4002910-f3fb-4a50-9ff6-72b7fa77c76b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1315142922 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_smoke.1315142922
Directory /workspace/9.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/9.rom_ctrl_stress_all.3303980143
Short name T229
Test name
Test status
Simulation time 10964868656 ps
CPU time 111.5 seconds
Started Feb 29 01:11:38 PM PST 24
Finished Feb 29 01:13:30 PM PST 24
Peak memory 215704 kb
Host smart-89a76f9c-c7fc-40e8-bd0b-52c8807b71d5
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3303980143 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 9.rom_ctrl_stress_all.3303980143
Directory /workspace/9.rom_ctrl_stress_all/latest
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