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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
97.45 97.04 92.65 97.88 100.00 98.37 98.04 98.14


Total test records in report: 467
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T296 /workspace/coverage/default/17.rom_ctrl_kmac_err_chk.2371335580 Mar 03 02:32:09 PM PST 24 Mar 03 02:32:20 PM PST 24 261287516 ps
T297 /workspace/coverage/default/14.rom_ctrl_max_throughput_chk.272226634 Mar 03 02:31:51 PM PST 24 Mar 03 02:31:57 PM PST 24 455301052 ps
T34 /workspace/coverage/default/3.rom_ctrl_sec_cm.2651888456 Mar 03 02:31:27 PM PST 24 Mar 03 02:32:17 PM PST 24 611273504 ps
T298 /workspace/coverage/default/1.rom_ctrl_stress_all_with_rand_reset.3329923482 Mar 03 02:31:21 PM PST 24 Mar 03 04:06:56 PM PST 24 21799918274 ps
T299 /workspace/coverage/default/17.rom_ctrl_smoke.937754470 Mar 03 02:32:05 PM PST 24 Mar 03 02:32:27 PM PST 24 19130023309 ps
T300 /workspace/coverage/default/0.rom_ctrl_kmac_err_chk.204672325 Mar 03 02:31:16 PM PST 24 Mar 03 02:31:34 PM PST 24 1235328232 ps
T301 /workspace/coverage/default/47.rom_ctrl_stress_all.1217045495 Mar 03 02:33:21 PM PST 24 Mar 03 02:33:40 PM PST 24 1122177268 ps
T302 /workspace/coverage/default/24.rom_ctrl_corrupt_sig_fatal_chk.1263775782 Mar 03 02:32:25 PM PST 24 Mar 03 02:35:28 PM PST 24 7494273760 ps
T303 /workspace/coverage/default/49.rom_ctrl_corrupt_sig_fatal_chk.1570993261 Mar 03 02:33:26 PM PST 24 Mar 03 02:35:44 PM PST 24 4199446691 ps
T304 /workspace/coverage/default/45.rom_ctrl_max_throughput_chk.11098511 Mar 03 02:33:13 PM PST 24 Mar 03 02:33:21 PM PST 24 269309342 ps
T305 /workspace/coverage/default/15.rom_ctrl_stress_all_with_rand_reset.1686232771 Mar 03 02:32:01 PM PST 24 Mar 03 02:38:22 PM PST 24 20031078110 ps
T306 /workspace/coverage/default/44.rom_ctrl_kmac_err_chk.2149214760 Mar 03 02:33:12 PM PST 24 Mar 03 02:33:39 PM PST 24 9754584904 ps
T307 /workspace/coverage/default/39.rom_ctrl_kmac_err_chk.3575043604 Mar 03 02:33:03 PM PST 24 Mar 03 02:33:34 PM PST 24 3596093740 ps
T308 /workspace/coverage/default/31.rom_ctrl_stress_all.3941022043 Mar 03 02:32:46 PM PST 24 Mar 03 02:33:12 PM PST 24 528773067 ps
T309 /workspace/coverage/default/39.rom_ctrl_smoke.4223746422 Mar 03 02:33:00 PM PST 24 Mar 03 02:33:41 PM PST 24 9499123694 ps
T310 /workspace/coverage/default/26.rom_ctrl_alert_test.623988868 Mar 03 02:32:32 PM PST 24 Mar 03 02:32:39 PM PST 24 1603738052 ps
T311 /workspace/coverage/default/30.rom_ctrl_alert_test.426127116 Mar 03 02:32:39 PM PST 24 Mar 03 02:32:52 PM PST 24 1409142444 ps
T312 /workspace/coverage/default/25.rom_ctrl_kmac_err_chk.788787046 Mar 03 02:32:24 PM PST 24 Mar 03 02:33:00 PM PST 24 4256287252 ps
T313 /workspace/coverage/default/18.rom_ctrl_corrupt_sig_fatal_chk.3110736913 Mar 03 02:32:11 PM PST 24 Mar 03 02:36:11 PM PST 24 222889734188 ps
T314 /workspace/coverage/default/46.rom_ctrl_stress_all.1813963732 Mar 03 02:33:19 PM PST 24 Mar 03 02:33:36 PM PST 24 1246591144 ps
T35 /workspace/coverage/default/4.rom_ctrl_sec_cm.3066368411 Mar 03 02:31:29 PM PST 24 Mar 03 02:32:24 PM PST 24 2835885308 ps
T315 /workspace/coverage/default/26.rom_ctrl_corrupt_sig_fatal_chk.3841961622 Mar 03 02:32:31 PM PST 24 Mar 03 02:36:56 PM PST 24 31399342034 ps
T316 /workspace/coverage/default/37.rom_ctrl_alert_test.1834620129 Mar 03 02:33:00 PM PST 24 Mar 03 02:33:06 PM PST 24 1180742361 ps
T317 /workspace/coverage/default/23.rom_ctrl_stress_all_with_rand_reset.317157244 Mar 03 02:32:25 PM PST 24 Mar 03 04:17:13 PM PST 24 76657954673 ps
T318 /workspace/coverage/default/11.rom_ctrl_kmac_err_chk.4078564759 Mar 03 02:31:48 PM PST 24 Mar 03 02:32:13 PM PST 24 3006476318 ps
T319 /workspace/coverage/default/28.rom_ctrl_smoke.4165072593 Mar 03 02:32:30 PM PST 24 Mar 03 02:33:06 PM PST 24 20798997123 ps
T320 /workspace/coverage/default/21.rom_ctrl_smoke.1501913067 Mar 03 02:32:18 PM PST 24 Mar 03 02:32:49 PM PST 24 5769970756 ps
T321 /workspace/coverage/default/36.rom_ctrl_stress_all.1826290625 Mar 03 02:32:54 PM PST 24 Mar 03 02:33:47 PM PST 24 25563066662 ps
T322 /workspace/coverage/default/15.rom_ctrl_alert_test.617185340 Mar 03 02:31:58 PM PST 24 Mar 03 02:32:14 PM PST 24 28517584509 ps
T323 /workspace/coverage/default/19.rom_ctrl_kmac_err_chk.1948317283 Mar 03 02:32:19 PM PST 24 Mar 03 02:32:33 PM PST 24 2311854563 ps
T324 /workspace/coverage/default/49.rom_ctrl_max_throughput_chk.2065543864 Mar 03 02:33:25 PM PST 24 Mar 03 02:33:41 PM PST 24 2747813428 ps
T325 /workspace/coverage/default/9.rom_ctrl_alert_test.1245342766 Mar 03 02:31:40 PM PST 24 Mar 03 02:31:48 PM PST 24 2216478318 ps
T326 /workspace/coverage/default/5.rom_ctrl_alert_test.3481570840 Mar 03 02:31:33 PM PST 24 Mar 03 02:31:38 PM PST 24 361734471 ps
T327 /workspace/coverage/default/2.rom_ctrl_smoke.3635612762 Mar 03 02:31:20 PM PST 24 Mar 03 02:31:53 PM PST 24 3683502912 ps
T328 /workspace/coverage/default/45.rom_ctrl_kmac_err_chk.2416791017 Mar 03 02:33:10 PM PST 24 Mar 03 02:33:43 PM PST 24 14669565526 ps
T329 /workspace/coverage/default/12.rom_ctrl_stress_all.3051017243 Mar 03 02:31:46 PM PST 24 Mar 03 02:32:15 PM PST 24 4084835507 ps
T330 /workspace/coverage/default/46.rom_ctrl_stress_all_with_rand_reset.564929538 Mar 03 02:33:19 PM PST 24 Mar 03 03:17:56 PM PST 24 108806909221 ps
T331 /workspace/coverage/default/25.rom_ctrl_max_throughput_chk.1405143800 Mar 03 02:32:28 PM PST 24 Mar 03 02:32:37 PM PST 24 1265015928 ps
T332 /workspace/coverage/default/43.rom_ctrl_kmac_err_chk.2603659721 Mar 03 02:33:11 PM PST 24 Mar 03 02:33:21 PM PST 24 168765327 ps
T333 /workspace/coverage/default/21.rom_ctrl_kmac_err_chk.3510856641 Mar 03 02:32:20 PM PST 24 Mar 03 02:32:38 PM PST 24 1438685006 ps
T334 /workspace/coverage/default/10.rom_ctrl_alert_test.532956798 Mar 03 02:31:46 PM PST 24 Mar 03 02:31:50 PM PST 24 88452617 ps
T335 /workspace/coverage/default/24.rom_ctrl_smoke.1749987791 Mar 03 02:32:25 PM PST 24 Mar 03 02:32:34 PM PST 24 741161170 ps
T336 /workspace/coverage/default/23.rom_ctrl_alert_test.3102696214 Mar 03 02:32:28 PM PST 24 Mar 03 02:32:38 PM PST 24 902826823 ps
T337 /workspace/coverage/default/42.rom_ctrl_stress_all.1058076887 Mar 03 02:33:07 PM PST 24 Mar 03 02:33:44 PM PST 24 1735905515 ps
T338 /workspace/coverage/default/32.rom_ctrl_corrupt_sig_fatal_chk.3316392750 Mar 03 02:32:45 PM PST 24 Mar 03 02:34:32 PM PST 24 3657386436 ps
T339 /workspace/coverage/default/44.rom_ctrl_stress_all.1022981645 Mar 03 02:33:11 PM PST 24 Mar 03 02:33:31 PM PST 24 3502630277 ps
T340 /workspace/coverage/default/12.rom_ctrl_smoke.1285397457 Mar 03 02:31:47 PM PST 24 Mar 03 02:32:13 PM PST 24 14734483171 ps
T341 /workspace/coverage/default/23.rom_ctrl_max_throughput_chk.1766399918 Mar 03 02:32:24 PM PST 24 Mar 03 02:32:30 PM PST 24 195560590 ps
T342 /workspace/coverage/default/42.rom_ctrl_kmac_err_chk.398090132 Mar 03 02:33:07 PM PST 24 Mar 03 02:33:20 PM PST 24 1149514922 ps
T343 /workspace/coverage/default/13.rom_ctrl_kmac_err_chk.2179809872 Mar 03 02:31:52 PM PST 24 Mar 03 02:32:15 PM PST 24 2140580979 ps
T344 /workspace/coverage/default/14.rom_ctrl_kmac_err_chk.1042919786 Mar 03 02:31:55 PM PST 24 Mar 03 02:32:11 PM PST 24 2546082984 ps
T345 /workspace/coverage/default/47.rom_ctrl_max_throughput_chk.2947846689 Mar 03 02:33:18 PM PST 24 Mar 03 02:33:32 PM PST 24 4246081265 ps
T346 /workspace/coverage/default/45.rom_ctrl_stress_all.2366739742 Mar 03 02:33:11 PM PST 24 Mar 03 02:34:18 PM PST 24 7694303308 ps
T347 /workspace/coverage/default/49.rom_ctrl_alert_test.2058984634 Mar 03 02:33:26 PM PST 24 Mar 03 02:33:42 PM PST 24 18862526665 ps
T348 /workspace/coverage/default/16.rom_ctrl_stress_all_with_rand_reset.2047205538 Mar 03 02:32:03 PM PST 24 Mar 03 03:04:42 PM PST 24 451204302531 ps
T349 /workspace/coverage/default/49.rom_ctrl_stress_all.2738221266 Mar 03 02:33:25 PM PST 24 Mar 03 02:34:38 PM PST 24 67126376545 ps
T350 /workspace/coverage/default/19.rom_ctrl_smoke.3833701134 Mar 03 02:32:12 PM PST 24 Mar 03 02:32:27 PM PST 24 947106848 ps
T351 /workspace/coverage/default/30.rom_ctrl_stress_all_with_rand_reset.3750307227 Mar 03 02:32:39 PM PST 24 Mar 03 02:52:03 PM PST 24 122472340544 ps
T352 /workspace/coverage/default/1.rom_ctrl_max_throughput_chk.37080411 Mar 03 02:31:28 PM PST 24 Mar 03 02:31:39 PM PST 24 953921586 ps
T353 /workspace/coverage/default/13.rom_ctrl_corrupt_sig_fatal_chk.1445125677 Mar 03 02:31:53 PM PST 24 Mar 03 02:34:25 PM PST 24 29799689953 ps
T354 /workspace/coverage/default/20.rom_ctrl_max_throughput_chk.3374146440 Mar 03 02:32:19 PM PST 24 Mar 03 02:32:28 PM PST 24 1058565973 ps
T355 /workspace/coverage/default/28.rom_ctrl_max_throughput_chk.3334942928 Mar 03 02:32:32 PM PST 24 Mar 03 02:32:39 PM PST 24 1068660791 ps
T18 /workspace/coverage/default/17.rom_ctrl_stress_all_with_rand_reset.2079908316 Mar 03 02:32:11 PM PST 24 Mar 03 02:46:49 PM PST 24 251894049433 ps
T356 /workspace/coverage/default/28.rom_ctrl_alert_test.1559048175 Mar 03 02:32:30 PM PST 24 Mar 03 02:32:48 PM PST 24 8352384692 ps
T357 /workspace/coverage/default/10.rom_ctrl_smoke.2870893241 Mar 03 02:31:41 PM PST 24 Mar 03 02:32:19 PM PST 24 13148709400 ps
T358 /workspace/coverage/default/16.rom_ctrl_stress_all.899645101 Mar 03 02:32:01 PM PST 24 Mar 03 02:32:19 PM PST 24 3605217650 ps
T359 /workspace/coverage/default/25.rom_ctrl_smoke.357794629 Mar 03 02:32:25 PM PST 24 Mar 03 02:32:36 PM PST 24 757216086 ps
T360 /workspace/coverage/default/21.rom_ctrl_alert_test.3439460692 Mar 03 02:32:18 PM PST 24 Mar 03 02:32:33 PM PST 24 9306419430 ps
T361 /workspace/coverage/default/3.rom_ctrl_max_throughput_chk.4202846334 Mar 03 02:31:30 PM PST 24 Mar 03 02:31:44 PM PST 24 1446670498 ps
T362 /workspace/coverage/default/41.rom_ctrl_kmac_err_chk.778371623 Mar 03 02:33:07 PM PST 24 Mar 03 02:33:23 PM PST 24 948785947 ps
T363 /workspace/coverage/default/43.rom_ctrl_stress_all.3003531027 Mar 03 02:33:12 PM PST 24 Mar 03 02:33:31 PM PST 24 3391347172 ps
T364 /workspace/coverage/default/14.rom_ctrl_smoke.630675253 Mar 03 02:31:55 PM PST 24 Mar 03 02:32:12 PM PST 24 4151942358 ps
T56 /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_intg_err.1448810055 Mar 03 12:41:01 PM PST 24 Mar 03 12:42:17 PM PST 24 3141002871 ps
T60 /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_rw.4014540770 Mar 03 12:41:02 PM PST 24 Mar 03 12:41:07 PM PST 24 695975716 ps
T61 /workspace/coverage/cover_reg_top/19.rom_ctrl_same_csr_outstanding.856813360 Mar 03 12:41:19 PM PST 24 Mar 03 12:41:35 PM PST 24 2147360541 ps
T365 /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_mem_rw_with_rand_reset.63142634 Mar 03 12:40:59 PM PST 24 Mar 03 12:41:06 PM PST 24 295144425 ps
T66 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_hw_reset.1130654853 Mar 03 12:41:11 PM PST 24 Mar 03 12:41:19 PM PST 24 99227426 ps
T96 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_rw.971454388 Mar 03 12:40:48 PM PST 24 Mar 03 12:41:04 PM PST 24 5797124944 ps
T366 /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_partial_access.474441220 Mar 03 12:40:51 PM PST 24 Mar 03 12:41:05 PM PST 24 1798427799 ps
T367 /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_errors.1188905591 Mar 03 12:41:10 PM PST 24 Mar 03 12:41:25 PM PST 24 9024367712 ps
T97 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_aliasing.2977444531 Mar 03 12:40:48 PM PST 24 Mar 03 12:40:55 PM PST 24 532014423 ps
T368 /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_mem_rw_with_rand_reset.356546982 Mar 03 12:41:14 PM PST 24 Mar 03 12:41:30 PM PST 24 7448443145 ps
T369 /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_errors.1211478969 Mar 03 12:41:02 PM PST 24 Mar 03 12:41:18 PM PST 24 2926675612 ps
T370 /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_errors.2876386003 Mar 03 12:40:52 PM PST 24 Mar 03 12:41:04 PM PST 24 554819156 ps
T371 /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_errors.1006870971 Mar 03 12:40:59 PM PST 24 Mar 03 12:41:09 PM PST 24 1882267598 ps
T372 /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_mem_rw_with_rand_reset.3787457742 Mar 03 12:40:39 PM PST 24 Mar 03 12:40:53 PM PST 24 1698646083 ps
T373 /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_errors.3717834119 Mar 03 12:40:52 PM PST 24 Mar 03 12:41:05 PM PST 24 1059855812 ps
T67 /workspace/coverage/cover_reg_top/19.rom_ctrl_passthru_mem_tl_intg_err.3606094479 Mar 03 12:41:10 PM PST 24 Mar 03 12:41:52 PM PST 24 2266305337 ps
T93 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_rw.3035268967 Mar 03 12:40:37 PM PST 24 Mar 03 12:40:53 PM PST 24 3509939062 ps
T374 /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_errors.3340128280 Mar 03 12:41:02 PM PST 24 Mar 03 12:41:16 PM PST 24 1117944842 ps
T98 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_bit_bash.1927691437 Mar 03 12:40:54 PM PST 24 Mar 03 12:41:02 PM PST 24 1811239455 ps
T375 /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_partial_access.227600525 Mar 03 12:40:58 PM PST 24 Mar 03 12:41:17 PM PST 24 1803612771 ps
T376 /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_mem_rw_with_rand_reset.921214366 Mar 03 12:41:14 PM PST 24 Mar 03 12:41:18 PM PST 24 95732634 ps
T377 /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_walk.149731443 Mar 03 12:40:57 PM PST 24 Mar 03 12:41:01 PM PST 24 348143791 ps
T99 /workspace/coverage/cover_reg_top/15.rom_ctrl_passthru_mem_tl_intg_err.2774215333 Mar 03 12:41:33 PM PST 24 Mar 03 12:42:14 PM PST 24 14453111441 ps
T68 /workspace/coverage/cover_reg_top/9.rom_ctrl_passthru_mem_tl_intg_err.3611318339 Mar 03 12:41:38 PM PST 24 Mar 03 12:41:58 PM PST 24 378184762 ps
T94 /workspace/coverage/cover_reg_top/8.rom_ctrl_same_csr_outstanding.4137360709 Mar 03 12:41:32 PM PST 24 Mar 03 12:41:48 PM PST 24 3925090994 ps
T69 /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_rw.1678289556 Mar 03 12:41:10 PM PST 24 Mar 03 12:41:20 PM PST 24 1723983218 ps
T70 /workspace/coverage/cover_reg_top/6.rom_ctrl_same_csr_outstanding.4234051172 Mar 03 12:40:56 PM PST 24 Mar 03 12:41:07 PM PST 24 678044595 ps
T378 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_mem_rw_with_rand_reset.990708867 Mar 03 12:41:08 PM PST 24 Mar 03 12:41:16 PM PST 24 778670313 ps
T71 /workspace/coverage/cover_reg_top/11.rom_ctrl_passthru_mem_tl_intg_err.240522787 Mar 03 12:41:01 PM PST 24 Mar 03 12:41:29 PM PST 24 3152490741 ps
T379 /workspace/coverage/cover_reg_top/0.rom_ctrl_passthru_mem_tl_intg_err.915835061 Mar 03 12:40:55 PM PST 24 Mar 03 12:41:42 PM PST 24 5173935887 ps
T380 /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_rw.870143908 Mar 03 12:40:58 PM PST 24 Mar 03 12:41:13 PM PST 24 1960676231 ps
T381 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_bit_bash.1383554232 Mar 03 12:40:51 PM PST 24 Mar 03 12:41:05 PM PST 24 1426456069 ps
T57 /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_intg_err.1712279289 Mar 03 12:40:51 PM PST 24 Mar 03 12:42:01 PM PST 24 1198895583 ps
T382 /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_walk.2478208489 Mar 03 12:41:06 PM PST 24 Mar 03 12:41:19 PM PST 24 13772915731 ps
T383 /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_mem_rw_with_rand_reset.1576723907 Mar 03 12:41:03 PM PST 24 Mar 03 12:41:11 PM PST 24 634438912 ps
T95 /workspace/coverage/cover_reg_top/14.rom_ctrl_same_csr_outstanding.2293304871 Mar 03 12:41:49 PM PST 24 Mar 03 12:41:57 PM PST 24 595200988 ps
T58 /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_intg_err.2771381944 Mar 03 12:41:05 PM PST 24 Mar 03 12:42:14 PM PST 24 841707190 ps
T384 /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_errors.1962035134 Mar 03 12:41:16 PM PST 24 Mar 03 12:41:26 PM PST 24 10828744517 ps
T385 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_mem_rw_with_rand_reset.778946373 Mar 03 12:40:39 PM PST 24 Mar 03 12:40:51 PM PST 24 6779542725 ps
T386 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_aliasing.3103521211 Mar 03 12:40:47 PM PST 24 Mar 03 12:40:59 PM PST 24 3154263131 ps
T72 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_aliasing.3390456444 Mar 03 12:40:55 PM PST 24 Mar 03 12:41:11 PM PST 24 8066812917 ps
T73 /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_rw.1359198439 Mar 03 12:41:04 PM PST 24 Mar 03 12:41:10 PM PST 24 436312829 ps
T74 /workspace/coverage/cover_reg_top/18.rom_ctrl_passthru_mem_tl_intg_err.3849862535 Mar 03 12:41:01 PM PST 24 Mar 03 12:42:15 PM PST 24 36587440991 ps
T387 /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_rw.3016878979 Mar 03 12:41:32 PM PST 24 Mar 03 12:41:48 PM PST 24 2321818175 ps
T82 /workspace/coverage/cover_reg_top/6.rom_ctrl_passthru_mem_tl_intg_err.1832875808 Mar 03 12:40:44 PM PST 24 Mar 03 12:42:06 PM PST 24 35566214415 ps
T106 /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_intg_err.389394167 Mar 03 12:40:56 PM PST 24 Mar 03 12:41:43 PM PST 24 8198140038 ps
T388 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_hw_reset.4066731961 Mar 03 12:40:56 PM PST 24 Mar 03 12:41:10 PM PST 24 2794179777 ps
T389 /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_errors.3697660369 Mar 03 12:41:10 PM PST 24 Mar 03 12:41:22 PM PST 24 819497497 ps
T390 /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_errors.1042011021 Mar 03 12:40:55 PM PST 24 Mar 03 12:41:04 PM PST 24 532548043 ps
T83 /workspace/coverage/cover_reg_top/10.rom_ctrl_passthru_mem_tl_intg_err.2946676169 Mar 03 12:40:56 PM PST 24 Mar 03 12:42:07 PM PST 24 76549438724 ps
T84 /workspace/coverage/cover_reg_top/3.rom_ctrl_passthru_mem_tl_intg_err.4200948716 Mar 03 12:40:44 PM PST 24 Mar 03 12:41:56 PM PST 24 65168223588 ps
T391 /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_errors.4183355148 Mar 03 12:41:02 PM PST 24 Mar 03 12:41:20 PM PST 24 4083704507 ps
T392 /workspace/coverage/cover_reg_top/4.rom_ctrl_same_csr_outstanding.2078912547 Mar 03 12:40:57 PM PST 24 Mar 03 12:41:13 PM PST 24 8760404971 ps
T393 /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_errors.3378462225 Mar 03 12:41:26 PM PST 24 Mar 03 12:41:41 PM PST 24 452974624 ps
T394 /workspace/coverage/cover_reg_top/9.rom_ctrl_same_csr_outstanding.4119274517 Mar 03 12:41:02 PM PST 24 Mar 03 12:41:11 PM PST 24 2672569886 ps
T104 /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_intg_err.657297994 Mar 03 12:40:49 PM PST 24 Mar 03 12:42:04 PM PST 24 4962767114 ps
T395 /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_partial_access.2169352707 Mar 03 12:40:34 PM PST 24 Mar 03 12:40:46 PM PST 24 5465668536 ps
T396 /workspace/coverage/cover_reg_top/13.rom_ctrl_passthru_mem_tl_intg_err.1626088386 Mar 03 12:40:58 PM PST 24 Mar 03 12:41:57 PM PST 24 23531230929 ps
T107 /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_intg_err.3641935156 Mar 03 12:41:11 PM PST 24 Mar 03 12:42:29 PM PST 24 1759981147 ps
T87 /workspace/coverage/cover_reg_top/17.rom_ctrl_passthru_mem_tl_intg_err.2862932760 Mar 03 12:41:03 PM PST 24 Mar 03 12:42:32 PM PST 24 10393386210 ps
T113 /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_intg_err.496835779 Mar 03 12:40:57 PM PST 24 Mar 03 12:42:12 PM PST 24 667829275 ps
T397 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_aliasing.946130798 Mar 03 12:40:59 PM PST 24 Mar 03 12:41:16 PM PST 24 19827736310 ps
T398 /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_intg_err.3176412616 Mar 03 12:41:27 PM PST 24 Mar 03 12:42:05 PM PST 24 408631483 ps
T105 /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_intg_err.1542587316 Mar 03 12:41:03 PM PST 24 Mar 03 12:42:19 PM PST 24 1465242038 ps
T102 /workspace/coverage/cover_reg_top/7.rom_ctrl_passthru_mem_tl_intg_err.3589726459 Mar 03 12:41:14 PM PST 24 Mar 03 12:41:51 PM PST 24 13636447450 ps
T399 /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_rw.1931067677 Mar 03 12:41:03 PM PST 24 Mar 03 12:41:09 PM PST 24 370335867 ps
T400 /workspace/coverage/cover_reg_top/12.rom_ctrl_same_csr_outstanding.676927457 Mar 03 12:41:14 PM PST 24 Mar 03 12:41:27 PM PST 24 4003772417 ps
T401 /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_mem_rw_with_rand_reset.1555935681 Mar 03 12:41:15 PM PST 24 Mar 03 12:41:24 PM PST 24 4763154560 ps
T88 /workspace/coverage/cover_reg_top/8.rom_ctrl_passthru_mem_tl_intg_err.2982210753 Mar 03 12:40:58 PM PST 24 Mar 03 12:41:51 PM PST 24 12867960048 ps
T402 /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_errors.860555037 Mar 03 12:41:01 PM PST 24 Mar 03 12:41:07 PM PST 24 346288781 ps
T103 /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_intg_err.538542509 Mar 03 12:40:55 PM PST 24 Mar 03 12:42:09 PM PST 24 9107903020 ps
T403 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_hw_reset.2622781531 Mar 03 12:40:44 PM PST 24 Mar 03 12:41:03 PM PST 24 2179288698 ps
T404 /workspace/coverage/cover_reg_top/15.rom_ctrl_same_csr_outstanding.215030672 Mar 03 12:41:10 PM PST 24 Mar 03 12:41:23 PM PST 24 3116402937 ps
T405 /workspace/coverage/cover_reg_top/16.rom_ctrl_same_csr_outstanding.1828887491 Mar 03 12:40:59 PM PST 24 Mar 03 12:41:14 PM PST 24 3986754644 ps
T406 /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_rw.1298067173 Mar 03 12:40:58 PM PST 24 Mar 03 12:41:08 PM PST 24 3952690650 ps
T407 /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_errors.1616424788 Mar 03 12:41:00 PM PST 24 Mar 03 12:41:19 PM PST 24 7960538963 ps
T408 /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_mem_rw_with_rand_reset.1392603684 Mar 03 12:41:15 PM PST 24 Mar 03 12:41:29 PM PST 24 3497503361 ps
T409 /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_walk.191683145 Mar 03 12:40:42 PM PST 24 Mar 03 12:40:47 PM PST 24 86487915 ps
T410 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_rw.1129537127 Mar 03 12:40:45 PM PST 24 Mar 03 12:40:58 PM PST 24 1465294488 ps
T110 /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_intg_err.2485334258 Mar 03 12:41:02 PM PST 24 Mar 03 12:42:23 PM PST 24 22798152715 ps
T411 /workspace/coverage/cover_reg_top/5.rom_ctrl_same_csr_outstanding.1723607402 Mar 03 12:41:09 PM PST 24 Mar 03 12:41:17 PM PST 24 456816097 ps
T412 /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_mem_rw_with_rand_reset.2547138516 Mar 03 12:41:06 PM PST 24 Mar 03 12:41:23 PM PST 24 7716703608 ps
T413 /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_rw.2132611796 Mar 03 12:40:52 PM PST 24 Mar 03 12:41:13 PM PST 24 8236831157 ps
T414 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_bit_bash.2054296232 Mar 03 12:40:56 PM PST 24 Mar 03 12:41:01 PM PST 24 460723123 ps
T415 /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_mem_rw_with_rand_reset.1219630348 Mar 03 12:41:15 PM PST 24 Mar 03 12:41:27 PM PST 24 2500771247 ps
T416 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_hw_reset.3128078140 Mar 03 12:40:45 PM PST 24 Mar 03 12:41:02 PM PST 24 3452152875 ps
T417 /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_rw.4034877371 Mar 03 12:41:15 PM PST 24 Mar 03 12:41:30 PM PST 24 1880334494 ps
T418 /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_rw.1208665572 Mar 03 12:41:09 PM PST 24 Mar 03 12:41:24 PM PST 24 1946824071 ps
T108 /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_intg_err.902237952 Mar 03 12:41:26 PM PST 24 Mar 03 12:42:38 PM PST 24 1420971094 ps
T419 /workspace/coverage/cover_reg_top/3.rom_ctrl_same_csr_outstanding.3379604983 Mar 03 12:40:50 PM PST 24 Mar 03 12:41:03 PM PST 24 4431682215 ps
T420 /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_errors.1501958979 Mar 03 12:41:19 PM PST 24 Mar 03 12:41:34 PM PST 24 5445032841 ps
T421 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_mem_rw_with_rand_reset.2808217086 Mar 03 12:41:05 PM PST 24 Mar 03 12:41:11 PM PST 24 496681916 ps
T422 /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_errors.564563271 Mar 03 12:41:09 PM PST 24 Mar 03 12:41:28 PM PST 24 1925827145 ps
T423 /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_mem_rw_with_rand_reset.1280845191 Mar 03 12:41:06 PM PST 24 Mar 03 12:41:19 PM PST 24 1458085144 ps
T424 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_aliasing.3074014891 Mar 03 12:40:55 PM PST 24 Mar 03 12:41:01 PM PST 24 451282986 ps
T425 /workspace/coverage/cover_reg_top/4.rom_ctrl_passthru_mem_tl_intg_err.3345697219 Mar 03 12:40:41 PM PST 24 Mar 03 12:41:28 PM PST 24 8110604019 ps
T426 /workspace/coverage/cover_reg_top/13.rom_ctrl_same_csr_outstanding.2087774431 Mar 03 12:41:10 PM PST 24 Mar 03 12:41:28 PM PST 24 15371872075 ps
T427 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_mem_rw_with_rand_reset.3599325409 Mar 03 12:41:00 PM PST 24 Mar 03 12:41:06 PM PST 24 351237832 ps
T428 /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_errors.3305308576 Mar 03 12:41:01 PM PST 24 Mar 03 12:41:14 PM PST 24 4227395191 ps
T429 /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_walk.787193228 Mar 03 12:40:40 PM PST 24 Mar 03 12:40:56 PM PST 24 13054861630 ps
T430 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_bit_bash.2493211433 Mar 03 12:40:31 PM PST 24 Mar 03 12:40:37 PM PST 24 423278330 ps
T431 /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_mem_rw_with_rand_reset.1632674253 Mar 03 12:41:10 PM PST 24 Mar 03 12:41:18 PM PST 24 641757077 ps
T109 /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_intg_err.388362927 Mar 03 12:41:01 PM PST 24 Mar 03 12:41:46 PM PST 24 1546093678 ps
T432 /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_partial_access.2190572292 Mar 03 12:40:47 PM PST 24 Mar 03 12:40:59 PM PST 24 7832109628 ps
T433 /workspace/coverage/cover_reg_top/11.rom_ctrl_same_csr_outstanding.3554592808 Mar 03 12:41:03 PM PST 24 Mar 03 12:41:18 PM PST 24 2007686482 ps
T111 /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_intg_err.983795070 Mar 03 12:41:09 PM PST 24 Mar 03 12:41:50 PM PST 24 929516477 ps
T434 /workspace/coverage/cover_reg_top/5.rom_ctrl_passthru_mem_tl_intg_err.2094367982 Mar 03 12:40:54 PM PST 24 Mar 03 12:41:12 PM PST 24 1441333363 ps
T435 /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_rw.2348270252 Mar 03 12:41:10 PM PST 24 Mar 03 12:41:19 PM PST 24 5276616696 ps
T436 /workspace/coverage/cover_reg_top/10.rom_ctrl_same_csr_outstanding.2924868268 Mar 03 12:41:08 PM PST 24 Mar 03 12:41:21 PM PST 24 6186449374 ps
T437 /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_rw.1758224052 Mar 03 12:41:05 PM PST 24 Mar 03 12:41:09 PM PST 24 88360247 ps
T438 /workspace/coverage/cover_reg_top/18.rom_ctrl_same_csr_outstanding.4015904793 Mar 03 12:41:07 PM PST 24 Mar 03 12:41:22 PM PST 24 1839404529 ps
T439 /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_mem_rw_with_rand_reset.1036596044 Mar 03 12:41:00 PM PST 24 Mar 03 12:41:10 PM PST 24 1698952084 ps
T440 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_hw_reset.2525499121 Mar 03 12:40:50 PM PST 24 Mar 03 12:41:05 PM PST 24 4521574175 ps
T441 /workspace/coverage/cover_reg_top/17.rom_ctrl_same_csr_outstanding.2573214625 Mar 03 12:41:01 PM PST 24 Mar 03 12:41:13 PM PST 24 14797455427 ps
T442 /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_errors.2065889373 Mar 03 12:41:01 PM PST 24 Mar 03 12:41:12 PM PST 24 277013220 ps
T443 /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_walk.804359804 Mar 03 12:40:57 PM PST 24 Mar 03 12:41:09 PM PST 24 7389476700 ps
T444 /workspace/coverage/cover_reg_top/7.rom_ctrl_same_csr_outstanding.3423269161 Mar 03 12:41:01 PM PST 24 Mar 03 12:41:18 PM PST 24 6870144528 ps
T445 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_mem_rw_with_rand_reset.898078281 Mar 03 12:40:54 PM PST 24 Mar 03 12:41:08 PM PST 24 1630548521 ps
T446 /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_intg_err.2504293153 Mar 03 12:41:06 PM PST 24 Mar 03 12:42:22 PM PST 24 5981887885 ps
T447 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_bit_bash.903089870 Mar 03 12:40:49 PM PST 24 Mar 03 12:41:03 PM PST 24 1566394279 ps
T448 /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_errors.3284546547 Mar 03 12:41:15 PM PST 24 Mar 03 12:41:34 PM PST 24 7428022073 ps
T85 /workspace/coverage/cover_reg_top/16.rom_ctrl_passthru_mem_tl_intg_err.3877416182 Mar 03 12:41:14 PM PST 24 Mar 03 12:41:59 PM PST 24 3027127069 ps
T449 /workspace/coverage/cover_reg_top/2.rom_ctrl_passthru_mem_tl_intg_err.2282610934 Mar 03 12:40:50 PM PST 24 Mar 03 12:41:36 PM PST 24 11471589610 ps
T450 /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_intg_err.2865290606 Mar 03 12:40:59 PM PST 24 Mar 03 12:41:44 PM PST 24 8219768167 ps
T451 /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_intg_err.3380379767 Mar 03 12:41:16 PM PST 24 Mar 03 12:42:02 PM PST 24 3977651246 ps
T452 /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_intg_err.3905707158 Mar 03 12:41:05 PM PST 24 Mar 03 12:42:23 PM PST 24 1916786502 ps
T453 /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_partial_access.1760306942 Mar 03 12:40:53 PM PST 24 Mar 03 12:41:08 PM PST 24 1942095064 ps
T454 /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_mem_rw_with_rand_reset.1540667732 Mar 03 12:41:12 PM PST 24 Mar 03 12:41:23 PM PST 24 4192808218 ps
T455 /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_errors.2159269106 Mar 03 12:41:03 PM PST 24 Mar 03 12:41:23 PM PST 24 1926203735 ps
T456 /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_errors.3584504453 Mar 03 12:40:56 PM PST 24 Mar 03 12:41:14 PM PST 24 6628715682 ps
T457 /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_mem_rw_with_rand_reset.2176978583 Mar 03 12:41:02 PM PST 24 Mar 03 12:41:20 PM PST 24 33642444716 ps
T458 /workspace/coverage/cover_reg_top/1.rom_ctrl_passthru_mem_tl_intg_err.2290683679 Mar 03 12:41:01 PM PST 24 Mar 03 12:41:53 PM PST 24 3780495527 ps
T459 /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_mem_rw_with_rand_reset.2259797495 Mar 03 12:41:07 PM PST 24 Mar 03 12:41:12 PM PST 24 576609615 ps
T86 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_rw.3315355560 Mar 03 12:40:57 PM PST 24 Mar 03 12:41:07 PM PST 24 8479809739 ps
T112 /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_intg_err.3153051852 Mar 03 12:40:54 PM PST 24 Mar 03 12:42:03 PM PST 24 421093706 ps
T460 /workspace/coverage/cover_reg_top/1.rom_ctrl_same_csr_outstanding.2293481388 Mar 03 12:40:49 PM PST 24 Mar 03 12:41:01 PM PST 24 3978957175 ps
T461 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_rw.763115444 Mar 03 12:40:45 PM PST 24 Mar 03 12:40:51 PM PST 24 434533793 ps
T462 /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_rw.2655196808 Mar 03 12:41:03 PM PST 24 Mar 03 12:41:10 PM PST 24 1717642758 ps
T89 /workspace/coverage/cover_reg_top/14.rom_ctrl_passthru_mem_tl_intg_err.1775385073 Mar 03 12:41:09 PM PST 24 Mar 03 12:42:08 PM PST 24 7533522601 ps
T463 /workspace/coverage/cover_reg_top/12.rom_ctrl_passthru_mem_tl_intg_err.4243764110 Mar 03 12:41:00 PM PST 24 Mar 03 12:41:41 PM PST 24 4102882030 ps
T90 /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_rw.869876093 Mar 03 12:41:05 PM PST 24 Mar 03 12:41:09 PM PST 24 347484395 ps
T464 /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_intg_err.666716978 Mar 03 12:41:02 PM PST 24 Mar 03 12:41:39 PM PST 24 153360015 ps
T465 /workspace/coverage/cover_reg_top/2.rom_ctrl_same_csr_outstanding.2235155177 Mar 03 12:40:42 PM PST 24 Mar 03 12:40:56 PM PST 24 4325625754 ps
T466 /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_rw.385226939 Mar 03 12:40:56 PM PST 24 Mar 03 12:41:02 PM PST 24 974346101 ps
T467 /workspace/coverage/cover_reg_top/0.rom_ctrl_same_csr_outstanding.1146787297 Mar 03 12:40:51 PM PST 24 Mar 03 12:40:55 PM PST 24 362428559 ps

Test location /workspace/coverage/default/38.rom_ctrl_stress_all_with_rand_reset.3066261847
Short name T8
Test name
Test status
Simulation time 88718630952 ps
CPU time 1095.2 seconds
Started Mar 03 02:33:00 PM PST 24
Finished Mar 03 02:51:15 PM PST 24
Peak memory 229468 kb
Host smart-c31f73be-ae3c-4eac-a7e7-2e3a3ff7029e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3066261847 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_stress_all_with_rand_reset.3066261847
Directory /workspace/38.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/14.rom_ctrl_corrupt_sig_fatal_chk.2776018568
Short name T15
Test name
Test status
Simulation time 9845872322 ps
CPU time 143.34 seconds
Started Mar 03 02:31:52 PM PST 24
Finished Mar 03 02:34:16 PM PST 24
Peak memory 236396 kb
Host smart-bb071602-7ef2-4b18-bf5f-682f907012fa
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2776018568 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_
corrupt_sig_fatal_chk.2776018568
Directory /workspace/14.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/3.rom_ctrl_corrupt_sig_fatal_chk.430626609
Short name T28
Test name
Test status
Simulation time 5807976886 ps
CPU time 142.76 seconds
Started Mar 03 02:31:26 PM PST 24
Finished Mar 03 02:33:49 PM PST 24
Peak memory 236840 kb
Host smart-d196be53-4dde-4b33-ac76-72990b8a651c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=430626609 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_co
rrupt_sig_fatal_chk.430626609
Directory /workspace/3.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/31.rom_ctrl_stress_all_with_rand_reset.4018601582
Short name T16
Test name
Test status
Simulation time 262590939046 ps
CPU time 1476.64 seconds
Started Mar 03 02:32:48 PM PST 24
Finished Mar 03 02:57:25 PM PST 24
Peak memory 235784 kb
Host smart-62e198ad-4c71-4de6-8a1a-fb42316b27e6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4018601582 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_stress_all_with_rand_reset.4018601582
Directory /workspace/31.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_intg_err.657297994
Short name T104
Test name
Test status
Simulation time 4962767114 ps
CPU time 74.81 seconds
Started Mar 03 12:40:49 PM PST 24
Finished Mar 03 12:42:04 PM PST 24
Peak memory 212044 kb
Host smart-0cecec47-6d43-4aae-9f91-4ba4c435d470
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=657297994 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_tl_int
g_err.657297994
Directory /workspace/4.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/25.rom_ctrl_alert_test.2544894938
Short name T7
Test name
Test status
Simulation time 4447871334 ps
CPU time 17.14 seconds
Started Mar 03 02:32:39 PM PST 24
Finished Mar 03 02:32:56 PM PST 24
Peak memory 210932 kb
Host smart-1650cc5f-a1bf-48dc-86f0-ac08b5ae9932
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2544894938 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_alert_test.2544894938
Directory /workspace/25.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/0.rom_ctrl_sec_cm.2179666899
Short name T30
Test name
Test status
Simulation time 2629115236 ps
CPU time 109.31 seconds
Started Mar 03 02:31:16 PM PST 24
Finished Mar 03 02:33:06 PM PST 24
Peak memory 232316 kb
Host smart-74846087-38ba-4bd0-ba82-462293fbb903
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2179666899 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_sec_cm.2179666899
Directory /workspace/0.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_passthru_mem_tl_intg_err.3606094479
Short name T67
Test name
Test status
Simulation time 2266305337 ps
CPU time 41.85 seconds
Started Mar 03 12:41:10 PM PST 24
Finished Mar 03 12:41:52 PM PST 24
Peak memory 211204 kb
Host smart-688c5765-fd72-43ae-b8a4-1add1a1bb310
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3606094479 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_p
assthru_mem_tl_intg_err.3606094479
Directory /workspace/19.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_intg_err.902237952
Short name T108
Test name
Test status
Simulation time 1420971094 ps
CPU time 71.69 seconds
Started Mar 03 12:41:26 PM PST 24
Finished Mar 03 12:42:38 PM PST 24
Peak memory 213008 kb
Host smart-26e984ff-5f4b-4bad-a54b-c6600067e287
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=902237952 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_tl_int
g_err.902237952
Directory /workspace/9.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/47.rom_ctrl_kmac_err_chk.650872542
Short name T3
Test name
Test status
Simulation time 3535048876 ps
CPU time 28.09 seconds
Started Mar 03 02:33:28 PM PST 24
Finished Mar 03 02:33:56 PM PST 24
Peak memory 211364 kb
Host smart-f0ad895f-2c16-42ad-ab9a-23870c94c96f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=650872542 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_kmac_err_chk.650872542
Directory /workspace/47.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/10.rom_ctrl_kmac_err_chk.3619399692
Short name T260
Test name
Test status
Simulation time 692926722 ps
CPU time 9.69 seconds
Started Mar 03 02:31:48 PM PST 24
Finished Mar 03 02:31:58 PM PST 24
Peak memory 211416 kb
Host smart-a778f39c-8219-4cdf-bb40-7327d4127596
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3619399692 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_kmac_err_chk.3619399692
Directory /workspace/10.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_rw.3315355560
Short name T86
Test name
Test status
Simulation time 8479809739 ps
CPU time 10.16 seconds
Started Mar 03 12:40:57 PM PST 24
Finished Mar 03 12:41:07 PM PST 24
Peak memory 211156 kb
Host smart-5f669db9-6806-494d-b99a-0f1d2e8e9ef7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3315355560 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_rw.3315355560
Directory /workspace/1.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/default/11.rom_ctrl_smoke.40210325
Short name T10
Test name
Test status
Simulation time 3565119715 ps
CPU time 13.67 seconds
Started Mar 03 02:31:45 PM PST 24
Finished Mar 03 02:31:59 PM PST 24
Peak memory 213284 kb
Host smart-3d3310d4-1622-4dd1-9102-30a816cf1839
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=40210325 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_smoke.40210325
Directory /workspace/11.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/21.rom_ctrl_stress_all.4092146255
Short name T142
Test name
Test status
Simulation time 8554461873 ps
CPU time 28.63 seconds
Started Mar 03 02:32:18 PM PST 24
Finished Mar 03 02:32:47 PM PST 24
Peak memory 215468 kb
Host smart-6e33670f-cd35-40f8-bc3e-0130f7628490
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4092146255 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 21.rom_ctrl_stress_all.4092146255
Directory /workspace/21.rom_ctrl_stress_all/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_intg_err.538542509
Short name T103
Test name
Test status
Simulation time 9107903020 ps
CPU time 73.77 seconds
Started Mar 03 12:40:55 PM PST 24
Finished Mar 03 12:42:09 PM PST 24
Peak memory 211244 kb
Host smart-49f8ae8b-c2f2-4298-b33b-537bfff63d2e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=538542509 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_tl_int
g_err.538542509
Directory /workspace/0.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_intg_err.983795070
Short name T111
Test name
Test status
Simulation time 929516477 ps
CPU time 41.4 seconds
Started Mar 03 12:41:09 PM PST 24
Finished Mar 03 12:41:50 PM PST 24
Peak memory 211280 kb
Host smart-27bae317-c005-451b-a3d8-f90ddbe9e2a1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=983795070 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_tl_in
tg_err.983795070
Directory /workspace/10.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_passthru_mem_tl_intg_err.4243764110
Short name T463
Test name
Test status
Simulation time 4102882030 ps
CPU time 40.92 seconds
Started Mar 03 12:41:00 PM PST 24
Finished Mar 03 12:41:41 PM PST 24
Peak memory 211576 kb
Host smart-0ad0a4d0-d525-443c-b427-c3f72a1d8aad
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4243764110 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_p
assthru_mem_tl_intg_err.4243764110
Directory /workspace/12.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/default/10.rom_ctrl_max_throughput_chk.2091593265
Short name T91
Test name
Test status
Simulation time 4138134135 ps
CPU time 11.85 seconds
Started Mar 03 02:31:48 PM PST 24
Finished Mar 03 02:32:01 PM PST 24
Peak memory 210900 kb
Host smart-cb1767db-0d6d-431f-a3aa-d7b8203c2706
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2091593265 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_max_throughput_chk.2091593265
Directory /workspace/10.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_aliasing.3103521211
Short name T386
Test name
Test status
Simulation time 3154263131 ps
CPU time 11.93 seconds
Started Mar 03 12:40:47 PM PST 24
Finished Mar 03 12:40:59 PM PST 24
Peak memory 211144 kb
Host smart-89722417-eb5c-4964-95df-182d674e9fdc
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3103521211 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_alia
sing.3103521211
Directory /workspace/0.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_bit_bash.2054296232
Short name T414
Test name
Test status
Simulation time 460723123 ps
CPU time 4.68 seconds
Started Mar 03 12:40:56 PM PST 24
Finished Mar 03 12:41:01 PM PST 24
Peak memory 211060 kb
Host smart-17ef16f5-c9af-465e-a55c-8ab25d49f8c3
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2054296232 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_bit_
bash.2054296232
Directory /workspace/0.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_hw_reset.2622781531
Short name T403
Test name
Test status
Simulation time 2179288698 ps
CPU time 18.46 seconds
Started Mar 03 12:40:44 PM PST 24
Finished Mar 03 12:41:03 PM PST 24
Peak memory 211180 kb
Host smart-9ede9ac2-90ca-4a17-b493-dc9e45da5a6b
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2622781531 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_hw_r
eset.2622781531
Directory /workspace/0.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_mem_rw_with_rand_reset.3599325409
Short name T427
Test name
Test status
Simulation time 351237832 ps
CPU time 6.56 seconds
Started Mar 03 12:41:00 PM PST 24
Finished Mar 03 12:41:06 PM PST 24
Peak memory 213972 kb
Host smart-dde4fe47-cef3-404f-a64a-e2832bdc34fc
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3599325409 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 0.rom_ctrl_csr_mem_rw_with_rand_reset.3599325409
Directory /workspace/0.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_rw.3035268967
Short name T93
Test name
Test status
Simulation time 3509939062 ps
CPU time 15.44 seconds
Started Mar 03 12:40:37 PM PST 24
Finished Mar 03 12:40:53 PM PST 24
Peak memory 211164 kb
Host smart-35c51205-b520-4414-b45c-dc2aa50bcb4a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3035268967 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_rw.3035268967
Directory /workspace/0.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_partial_access.1760306942
Short name T453
Test name
Test status
Simulation time 1942095064 ps
CPU time 15.27 seconds
Started Mar 03 12:40:53 PM PST 24
Finished Mar 03 12:41:08 PM PST 24
Peak memory 210992 kb
Host smart-30b70e61-c82a-4fd3-874c-5a879bb33f76
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1760306942 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctr
l_mem_partial_access.1760306942
Directory /workspace/0.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_walk.149731443
Short name T377
Test name
Test status
Simulation time 348143791 ps
CPU time 4.05 seconds
Started Mar 03 12:40:57 PM PST 24
Finished Mar 03 12:41:01 PM PST 24
Peak memory 210984 kb
Host smart-1174b4e9-53f8-4ce7-982a-5b50fec3fa70
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=149731443 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_mem_walk.
149731443
Directory /workspace/0.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_passthru_mem_tl_intg_err.915835061
Short name T379
Test name
Test status
Simulation time 5173935887 ps
CPU time 47.29 seconds
Started Mar 03 12:40:55 PM PST 24
Finished Mar 03 12:41:42 PM PST 24
Peak memory 211296 kb
Host smart-de2f5eba-53e6-4ecf-bbba-b88a91c048ca
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=915835061 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_pas
sthru_mem_tl_intg_err.915835061
Directory /workspace/0.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_same_csr_outstanding.1146787297
Short name T467
Test name
Test status
Simulation time 362428559 ps
CPU time 4.32 seconds
Started Mar 03 12:40:51 PM PST 24
Finished Mar 03 12:40:55 PM PST 24
Peak memory 211080 kb
Host smart-f99fe062-55da-4127-b5ca-fd6e3a50ff90
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1146787297 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_c
trl_same_csr_outstanding.1146787297
Directory /workspace/0.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_errors.2065889373
Short name T442
Test name
Test status
Simulation time 277013220 ps
CPU time 10.01 seconds
Started Mar 03 12:41:01 PM PST 24
Finished Mar 03 12:41:12 PM PST 24
Peak memory 215224 kb
Host smart-87035e6d-ebd9-416d-b9fd-0a153480c813
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2065889373 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_tl_errors.2065889373
Directory /workspace/0.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_aliasing.3390456444
Short name T72
Test name
Test status
Simulation time 8066812917 ps
CPU time 16.3 seconds
Started Mar 03 12:40:55 PM PST 24
Finished Mar 03 12:41:11 PM PST 24
Peak memory 211184 kb
Host smart-638adbe4-8b7e-4e51-9c32-fbef02ed2a9b
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3390456444 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_alia
sing.3390456444
Directory /workspace/1.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_bit_bash.903089870
Short name T447
Test name
Test status
Simulation time 1566394279 ps
CPU time 13.66 seconds
Started Mar 03 12:40:49 PM PST 24
Finished Mar 03 12:41:03 PM PST 24
Peak memory 211052 kb
Host smart-df876c85-0a1e-40df-8492-cb7dc67e7b02
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=903089870 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_bit_b
ash.903089870
Directory /workspace/1.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_hw_reset.3128078140
Short name T416
Test name
Test status
Simulation time 3452152875 ps
CPU time 17.6 seconds
Started Mar 03 12:40:45 PM PST 24
Finished Mar 03 12:41:02 PM PST 24
Peak memory 211216 kb
Host smart-b63d149e-6da6-4e02-a56a-d000a6199492
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3128078140 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_hw_r
eset.3128078140
Directory /workspace/1.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_mem_rw_with_rand_reset.898078281
Short name T445
Test name
Test status
Simulation time 1630548521 ps
CPU time 13.29 seconds
Started Mar 03 12:40:54 PM PST 24
Finished Mar 03 12:41:08 PM PST 24
Peak memory 213828 kb
Host smart-68968482-3b6c-46d9-b267-eed4e253c7a6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=898078281 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 1.rom_ctrl_csr_mem_rw_with_rand_reset.898078281
Directory /workspace/1.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_partial_access.227600525
Short name T375
Test name
Test status
Simulation time 1803612771 ps
CPU time 14.51 seconds
Started Mar 03 12:40:58 PM PST 24
Finished Mar 03 12:41:17 PM PST 24
Peak memory 210988 kb
Host smart-23e6c67a-cae5-4bda-a60e-e4135c26c983
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=227600525 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl
_mem_partial_access.227600525
Directory /workspace/1.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_walk.787193228
Short name T429
Test name
Test status
Simulation time 13054861630 ps
CPU time 15.34 seconds
Started Mar 03 12:40:40 PM PST 24
Finished Mar 03 12:40:56 PM PST 24
Peak memory 211100 kb
Host smart-cc40c886-9720-48e9-ae6b-e55fa7298b2f
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=787193228 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_mem_walk.
787193228
Directory /workspace/1.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_passthru_mem_tl_intg_err.2290683679
Short name T458
Test name
Test status
Simulation time 3780495527 ps
CPU time 52.13 seconds
Started Mar 03 12:41:01 PM PST 24
Finished Mar 03 12:41:53 PM PST 24
Peak memory 211208 kb
Host smart-39531617-eda5-431d-97f2-c406a8ab5eb9
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2290683679 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_pa
ssthru_mem_tl_intg_err.2290683679
Directory /workspace/1.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_same_csr_outstanding.2293481388
Short name T460
Test name
Test status
Simulation time 3978957175 ps
CPU time 11.62 seconds
Started Mar 03 12:40:49 PM PST 24
Finished Mar 03 12:41:01 PM PST 24
Peak memory 211220 kb
Host smart-ef70a056-b8d5-45a5-8fac-fbe1da0cbe42
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2293481388 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_c
trl_same_csr_outstanding.2293481388
Directory /workspace/1.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_errors.2876386003
Short name T370
Test name
Test status
Simulation time 554819156 ps
CPU time 11.72 seconds
Started Mar 03 12:40:52 PM PST 24
Finished Mar 03 12:41:04 PM PST 24
Peak memory 215408 kb
Host smart-412f6390-e0a8-4005-beff-bbbcc90dde52
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2876386003 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_tl_errors.2876386003
Directory /workspace/1.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_intg_err.389394167
Short name T106
Test name
Test status
Simulation time 8198140038 ps
CPU time 46.83 seconds
Started Mar 03 12:40:56 PM PST 24
Finished Mar 03 12:41:43 PM PST 24
Peak memory 212160 kb
Host smart-6e5e5248-0bf8-46ba-b192-b17692abd30e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=389394167 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_tl_int
g_err.389394167
Directory /workspace/1.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_mem_rw_with_rand_reset.356546982
Short name T368
Test name
Test status
Simulation time 7448443145 ps
CPU time 15.93 seconds
Started Mar 03 12:41:14 PM PST 24
Finished Mar 03 12:41:30 PM PST 24
Peak memory 215924 kb
Host smart-903b84b7-9ecb-4e7e-9256-bc1bf4a34926
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=356546982 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 10.rom_ctrl_csr_mem_rw_with_rand_reset.356546982
Directory /workspace/10.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_rw.1298067173
Short name T406
Test name
Test status
Simulation time 3952690650 ps
CPU time 9.77 seconds
Started Mar 03 12:40:58 PM PST 24
Finished Mar 03 12:41:08 PM PST 24
Peak memory 211280 kb
Host smart-dc375836-3225-4f49-b7fb-8d427b91a023
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1298067173 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_csr_rw.1298067173
Directory /workspace/10.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_passthru_mem_tl_intg_err.2946676169
Short name T83
Test name
Test status
Simulation time 76549438724 ps
CPU time 70.83 seconds
Started Mar 03 12:40:56 PM PST 24
Finished Mar 03 12:42:07 PM PST 24
Peak memory 211252 kb
Host smart-5186059e-6468-475a-ae90-d140e81dbcdb
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2946676169 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_p
assthru_mem_tl_intg_err.2946676169
Directory /workspace/10.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_same_csr_outstanding.2924868268
Short name T436
Test name
Test status
Simulation time 6186449374 ps
CPU time 12.74 seconds
Started Mar 03 12:41:08 PM PST 24
Finished Mar 03 12:41:21 PM PST 24
Peak memory 211576 kb
Host smart-a5017d1a-cde1-4d32-a8ca-8399aff814f8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2924868268 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_
ctrl_same_csr_outstanding.2924868268
Directory /workspace/10.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_errors.4183355148
Short name T391
Test name
Test status
Simulation time 4083704507 ps
CPU time 17.63 seconds
Started Mar 03 12:41:02 PM PST 24
Finished Mar 03 12:41:20 PM PST 24
Peak memory 215592 kb
Host smart-dbb6db93-4088-438f-bcb6-57d55a56b2ab
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4183355148 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_tl_errors.4183355148
Directory /workspace/10.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_mem_rw_with_rand_reset.1576723907
Short name T383
Test name
Test status
Simulation time 634438912 ps
CPU time 8.56 seconds
Started Mar 03 12:41:03 PM PST 24
Finished Mar 03 12:41:11 PM PST 24
Peak memory 214116 kb
Host smart-f3be052e-f09c-4d47-92d8-53b47ef769c0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1576723907 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 11.rom_ctrl_csr_mem_rw_with_rand_reset.1576723907
Directory /workspace/11.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_rw.1678289556
Short name T69
Test name
Test status
Simulation time 1723983218 ps
CPU time 9.54 seconds
Started Mar 03 12:41:10 PM PST 24
Finished Mar 03 12:41:20 PM PST 24
Peak memory 210996 kb
Host smart-ee37b92d-2c3e-4d05-bdca-f7f3b1463a0e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1678289556 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_csr_rw.1678289556
Directory /workspace/11.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_passthru_mem_tl_intg_err.240522787
Short name T71
Test name
Test status
Simulation time 3152490741 ps
CPU time 28.52 seconds
Started Mar 03 12:41:01 PM PST 24
Finished Mar 03 12:41:29 PM PST 24
Peak memory 211256 kb
Host smart-953e2e32-a238-4b83-8dd0-f834a3586f1f
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=240522787 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_pa
ssthru_mem_tl_intg_err.240522787
Directory /workspace/11.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_same_csr_outstanding.3554592808
Short name T433
Test name
Test status
Simulation time 2007686482 ps
CPU time 15.31 seconds
Started Mar 03 12:41:03 PM PST 24
Finished Mar 03 12:41:18 PM PST 24
Peak memory 211212 kb
Host smart-9d3f1cd1-0bfa-4f5f-83e2-6d924a5de453
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3554592808 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_
ctrl_same_csr_outstanding.3554592808
Directory /workspace/11.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_errors.1616424788
Short name T407
Test name
Test status
Simulation time 7960538963 ps
CPU time 18.8 seconds
Started Mar 03 12:41:00 PM PST 24
Finished Mar 03 12:41:19 PM PST 24
Peak memory 217052 kb
Host smart-e3fcf345-5746-4ccf-8e7a-aea260eba6e3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1616424788 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_tl_errors.1616424788
Directory /workspace/11.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_intg_err.1542587316
Short name T105
Test name
Test status
Simulation time 1465242038 ps
CPU time 71.06 seconds
Started Mar 03 12:41:03 PM PST 24
Finished Mar 03 12:42:19 PM PST 24
Peak memory 211848 kb
Host smart-3f8093df-0e64-4c45-ac54-85931a95340c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1542587316 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_tl_i
ntg_err.1542587316
Directory /workspace/11.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_mem_rw_with_rand_reset.1280845191
Short name T423
Test name
Test status
Simulation time 1458085144 ps
CPU time 13.08 seconds
Started Mar 03 12:41:06 PM PST 24
Finished Mar 03 12:41:19 PM PST 24
Peak memory 216388 kb
Host smart-219b0fb4-416f-4c99-8011-720134908190
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1280845191 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 12.rom_ctrl_csr_mem_rw_with_rand_reset.1280845191
Directory /workspace/12.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_rw.1359198439
Short name T73
Test name
Test status
Simulation time 436312829 ps
CPU time 5.14 seconds
Started Mar 03 12:41:04 PM PST 24
Finished Mar 03 12:41:10 PM PST 24
Peak memory 211116 kb
Host smart-0974ecca-91be-4ccd-917e-e3b77f09ceab
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1359198439 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_csr_rw.1359198439
Directory /workspace/12.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_same_csr_outstanding.676927457
Short name T400
Test name
Test status
Simulation time 4003772417 ps
CPU time 12.41 seconds
Started Mar 03 12:41:14 PM PST 24
Finished Mar 03 12:41:27 PM PST 24
Peak memory 211216 kb
Host smart-62210a25-b157-4ff7-8739-e2b47cacec9c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=676927457 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_c
trl_same_csr_outstanding.676927457
Directory /workspace/12.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_errors.1962035134
Short name T384
Test name
Test status
Simulation time 10828744517 ps
CPU time 10.04 seconds
Started Mar 03 12:41:16 PM PST 24
Finished Mar 03 12:41:26 PM PST 24
Peak memory 215652 kb
Host smart-d1bd2c81-92b8-4590-9e0e-8c37a2807aa5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1962035134 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_tl_errors.1962035134
Directory /workspace/12.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_intg_err.2504293153
Short name T446
Test name
Test status
Simulation time 5981887885 ps
CPU time 76.17 seconds
Started Mar 03 12:41:06 PM PST 24
Finished Mar 03 12:42:22 PM PST 24
Peak memory 212228 kb
Host smart-f6ec0c9a-03c8-45e1-bc5c-be51c380ed8e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2504293153 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_tl_i
ntg_err.2504293153
Directory /workspace/12.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_mem_rw_with_rand_reset.1540667732
Short name T454
Test name
Test status
Simulation time 4192808218 ps
CPU time 11.31 seconds
Started Mar 03 12:41:12 PM PST 24
Finished Mar 03 12:41:23 PM PST 24
Peak memory 214748 kb
Host smart-4459c788-2efb-4011-876a-7c51723bab7d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1540667732 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 13.rom_ctrl_csr_mem_rw_with_rand_reset.1540667732
Directory /workspace/13.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_rw.3016878979
Short name T387
Test name
Test status
Simulation time 2321818175 ps
CPU time 11.42 seconds
Started Mar 03 12:41:32 PM PST 24
Finished Mar 03 12:41:48 PM PST 24
Peak memory 211192 kb
Host smart-05d6ec5e-760e-4a78-9f76-20d8379a6582
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3016878979 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_csr_rw.3016878979
Directory /workspace/13.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_passthru_mem_tl_intg_err.1626088386
Short name T396
Test name
Test status
Simulation time 23531230929 ps
CPU time 58.13 seconds
Started Mar 03 12:40:58 PM PST 24
Finished Mar 03 12:41:57 PM PST 24
Peak memory 211228 kb
Host smart-c6f0e5fb-5457-424d-8d2e-75292df16947
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1626088386 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_p
assthru_mem_tl_intg_err.1626088386
Directory /workspace/13.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_same_csr_outstanding.2087774431
Short name T426
Test name
Test status
Simulation time 15371872075 ps
CPU time 17.91 seconds
Started Mar 03 12:41:10 PM PST 24
Finished Mar 03 12:41:28 PM PST 24
Peak memory 211236 kb
Host smart-f976a005-6d08-492e-a2cf-addc02ce4293
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2087774431 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_
ctrl_same_csr_outstanding.2087774431
Directory /workspace/13.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_errors.3378462225
Short name T393
Test name
Test status
Simulation time 452974624 ps
CPU time 9.43 seconds
Started Mar 03 12:41:26 PM PST 24
Finished Mar 03 12:41:41 PM PST 24
Peak memory 214544 kb
Host smart-7dbb2158-5f42-4bc5-9c61-76c6eb4ed660
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3378462225 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_tl_errors.3378462225
Directory /workspace/13.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_intg_err.2485334258
Short name T110
Test name
Test status
Simulation time 22798152715 ps
CPU time 80.69 seconds
Started Mar 03 12:41:02 PM PST 24
Finished Mar 03 12:42:23 PM PST 24
Peak memory 211960 kb
Host smart-94ab4211-7494-49f3-815e-2c6f04940a87
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2485334258 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_tl_i
ntg_err.2485334258
Directory /workspace/13.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_mem_rw_with_rand_reset.2547138516
Short name T412
Test name
Test status
Simulation time 7716703608 ps
CPU time 16.25 seconds
Started Mar 03 12:41:06 PM PST 24
Finished Mar 03 12:41:23 PM PST 24
Peak memory 216280 kb
Host smart-cd2d1c67-d30e-461b-a943-fc5bf2c57c5e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2547138516 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 14.rom_ctrl_csr_mem_rw_with_rand_reset.2547138516
Directory /workspace/14.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_rw.1931067677
Short name T399
Test name
Test status
Simulation time 370335867 ps
CPU time 6.61 seconds
Started Mar 03 12:41:03 PM PST 24
Finished Mar 03 12:41:09 PM PST 24
Peak memory 211076 kb
Host smart-53e076e8-c302-4ed1-b0bf-a120c6d49182
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1931067677 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_csr_rw.1931067677
Directory /workspace/14.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_passthru_mem_tl_intg_err.1775385073
Short name T89
Test name
Test status
Simulation time 7533522601 ps
CPU time 59.43 seconds
Started Mar 03 12:41:09 PM PST 24
Finished Mar 03 12:42:08 PM PST 24
Peak memory 211260 kb
Host smart-44199a75-d618-47f5-8d00-2bbf4c7cfba5
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1775385073 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_p
assthru_mem_tl_intg_err.1775385073
Directory /workspace/14.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_same_csr_outstanding.2293304871
Short name T95
Test name
Test status
Simulation time 595200988 ps
CPU time 6.58 seconds
Started Mar 03 12:41:49 PM PST 24
Finished Mar 03 12:41:57 PM PST 24
Peak memory 211128 kb
Host smart-a0464e18-d309-40cd-9803-ea552e7ca2b3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2293304871 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_
ctrl_same_csr_outstanding.2293304871
Directory /workspace/14.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_errors.3305308576
Short name T428
Test name
Test status
Simulation time 4227395191 ps
CPU time 12.34 seconds
Started Mar 03 12:41:01 PM PST 24
Finished Mar 03 12:41:14 PM PST 24
Peak memory 215004 kb
Host smart-e28be56d-16ed-4889-953f-03625caebbf3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3305308576 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_tl_errors.3305308576
Directory /workspace/14.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_intg_err.666716978
Short name T464
Test name
Test status
Simulation time 153360015 ps
CPU time 37.21 seconds
Started Mar 03 12:41:02 PM PST 24
Finished Mar 03 12:41:39 PM PST 24
Peak memory 212664 kb
Host smart-35cb106e-db4b-46dc-bcd2-df6f4546f582
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=666716978 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_tl_in
tg_err.666716978
Directory /workspace/14.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_mem_rw_with_rand_reset.1632674253
Short name T431
Test name
Test status
Simulation time 641757077 ps
CPU time 8.46 seconds
Started Mar 03 12:41:10 PM PST 24
Finished Mar 03 12:41:18 PM PST 24
Peak memory 214980 kb
Host smart-c61ae3f7-663b-40c8-8f6c-d72232f4b461
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1632674253 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 15.rom_ctrl_csr_mem_rw_with_rand_reset.1632674253
Directory /workspace/15.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_rw.2348270252
Short name T435
Test name
Test status
Simulation time 5276616696 ps
CPU time 8.99 seconds
Started Mar 03 12:41:10 PM PST 24
Finished Mar 03 12:41:19 PM PST 24
Peak memory 211160 kb
Host smart-80016071-6fe7-4cb6-abe1-6761e8a3cdca
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2348270252 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_csr_rw.2348270252
Directory /workspace/15.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_passthru_mem_tl_intg_err.2774215333
Short name T99
Test name
Test status
Simulation time 14453111441 ps
CPU time 41.05 seconds
Started Mar 03 12:41:33 PM PST 24
Finished Mar 03 12:42:14 PM PST 24
Peak memory 211332 kb
Host smart-c21db30e-9312-4225-972b-c174c7f8243f
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2774215333 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_p
assthru_mem_tl_intg_err.2774215333
Directory /workspace/15.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_same_csr_outstanding.215030672
Short name T404
Test name
Test status
Simulation time 3116402937 ps
CPU time 13.54 seconds
Started Mar 03 12:41:10 PM PST 24
Finished Mar 03 12:41:23 PM PST 24
Peak memory 211232 kb
Host smart-ede0c053-98ae-41f5-ae21-bd6d32934352
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=215030672 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_c
trl_same_csr_outstanding.215030672
Directory /workspace/15.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_errors.1188905591
Short name T367
Test name
Test status
Simulation time 9024367712 ps
CPU time 9.44 seconds
Started Mar 03 12:41:10 PM PST 24
Finished Mar 03 12:41:25 PM PST 24
Peak memory 215652 kb
Host smart-496e59a3-3366-4277-9902-14eb906d2b73
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1188905591 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_tl_errors.1188905591
Directory /workspace/15.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_intg_err.1448810055
Short name T56
Test name
Test status
Simulation time 3141002871 ps
CPU time 76.09 seconds
Started Mar 03 12:41:01 PM PST 24
Finished Mar 03 12:42:17 PM PST 24
Peak memory 211968 kb
Host smart-88bd8476-f4a9-43ed-b461-5dc66f9bf5f5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1448810055 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_tl_i
ntg_err.1448810055
Directory /workspace/15.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_mem_rw_with_rand_reset.2176978583
Short name T457
Test name
Test status
Simulation time 33642444716 ps
CPU time 17.28 seconds
Started Mar 03 12:41:02 PM PST 24
Finished Mar 03 12:41:20 PM PST 24
Peak memory 215556 kb
Host smart-3ba86da5-4764-4c2e-832d-dbffbb46d97d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2176978583 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 16.rom_ctrl_csr_mem_rw_with_rand_reset.2176978583
Directory /workspace/16.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_rw.4034877371
Short name T417
Test name
Test status
Simulation time 1880334494 ps
CPU time 14.94 seconds
Started Mar 03 12:41:15 PM PST 24
Finished Mar 03 12:41:30 PM PST 24
Peak memory 211068 kb
Host smart-ee142456-b605-4870-8bfc-20a906468fe2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4034877371 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_csr_rw.4034877371
Directory /workspace/16.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_passthru_mem_tl_intg_err.3877416182
Short name T85
Test name
Test status
Simulation time 3027127069 ps
CPU time 45.45 seconds
Started Mar 03 12:41:14 PM PST 24
Finished Mar 03 12:41:59 PM PST 24
Peak memory 211168 kb
Host smart-c3fd079f-c3be-4e33-a963-ced11cd3ec25
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3877416182 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_p
assthru_mem_tl_intg_err.3877416182
Directory /workspace/16.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_same_csr_outstanding.1828887491
Short name T405
Test name
Test status
Simulation time 3986754644 ps
CPU time 15.55 seconds
Started Mar 03 12:40:59 PM PST 24
Finished Mar 03 12:41:14 PM PST 24
Peak memory 211252 kb
Host smart-36a98640-53ad-4f74-ba18-bc986ee84366
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1828887491 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_
ctrl_same_csr_outstanding.1828887491
Directory /workspace/16.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_errors.860555037
Short name T402
Test name
Test status
Simulation time 346288781 ps
CPU time 6.01 seconds
Started Mar 03 12:41:01 PM PST 24
Finished Mar 03 12:41:07 PM PST 24
Peak memory 215372 kb
Host smart-354c523c-1aba-4ebe-9c99-86b2d696dcc9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=860555037 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_tl_errors.860555037
Directory /workspace/16.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_intg_err.2771381944
Short name T58
Test name
Test status
Simulation time 841707190 ps
CPU time 68.44 seconds
Started Mar 03 12:41:05 PM PST 24
Finished Mar 03 12:42:14 PM PST 24
Peak memory 211044 kb
Host smart-c2d59a10-b630-4d31-9272-1e5bbe1f569b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2771381944 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_tl_i
ntg_err.2771381944
Directory /workspace/16.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_mem_rw_with_rand_reset.1036596044
Short name T439
Test name
Test status
Simulation time 1698952084 ps
CPU time 9.71 seconds
Started Mar 03 12:41:00 PM PST 24
Finished Mar 03 12:41:10 PM PST 24
Peak memory 214436 kb
Host smart-5c2b690a-76dc-4ef5-acc9-d3e36044fcac
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1036596044 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 17.rom_ctrl_csr_mem_rw_with_rand_reset.1036596044
Directory /workspace/17.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_rw.2655196808
Short name T462
Test name
Test status
Simulation time 1717642758 ps
CPU time 6.97 seconds
Started Mar 03 12:41:03 PM PST 24
Finished Mar 03 12:41:10 PM PST 24
Peak memory 211048 kb
Host smart-909417d6-35d3-41ec-8217-d89a10706d63
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2655196808 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_csr_rw.2655196808
Directory /workspace/17.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_passthru_mem_tl_intg_err.2862932760
Short name T87
Test name
Test status
Simulation time 10393386210 ps
CPU time 88.95 seconds
Started Mar 03 12:41:03 PM PST 24
Finished Mar 03 12:42:32 PM PST 24
Peak memory 211224 kb
Host smart-9eaa3f62-6772-4372-a502-640ce364c954
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2862932760 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_p
assthru_mem_tl_intg_err.2862932760
Directory /workspace/17.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_same_csr_outstanding.2573214625
Short name T441
Test name
Test status
Simulation time 14797455427 ps
CPU time 11.65 seconds
Started Mar 03 12:41:01 PM PST 24
Finished Mar 03 12:41:13 PM PST 24
Peak memory 211332 kb
Host smart-a086b04b-d7d1-43bc-9254-cf78b9b881c5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2573214625 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_
ctrl_same_csr_outstanding.2573214625
Directory /workspace/17.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_errors.564563271
Short name T422
Test name
Test status
Simulation time 1925827145 ps
CPU time 18.86 seconds
Started Mar 03 12:41:09 PM PST 24
Finished Mar 03 12:41:28 PM PST 24
Peak memory 216232 kb
Host smart-6d0a00eb-2865-400d-80cf-9a84bb6f362a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=564563271 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_tl_errors.564563271
Directory /workspace/17.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_intg_err.3641935156
Short name T107
Test name
Test status
Simulation time 1759981147 ps
CPU time 77.83 seconds
Started Mar 03 12:41:11 PM PST 24
Finished Mar 03 12:42:29 PM PST 24
Peak memory 212712 kb
Host smart-58ffc190-9931-436c-bae1-21be2320f429
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3641935156 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_tl_i
ntg_err.3641935156
Directory /workspace/17.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_mem_rw_with_rand_reset.2259797495
Short name T459
Test name
Test status
Simulation time 576609615 ps
CPU time 5.37 seconds
Started Mar 03 12:41:07 PM PST 24
Finished Mar 03 12:41:12 PM PST 24
Peak memory 215348 kb
Host smart-a8f095d2-8c24-44d7-8852-d6266bb77b0c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2259797495 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 18.rom_ctrl_csr_mem_rw_with_rand_reset.2259797495
Directory /workspace/18.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_rw.1208665572
Short name T418
Test name
Test status
Simulation time 1946824071 ps
CPU time 15.2 seconds
Started Mar 03 12:41:09 PM PST 24
Finished Mar 03 12:41:24 PM PST 24
Peak memory 211112 kb
Host smart-beca8330-cb83-4c47-bb5f-70d46537170c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1208665572 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_csr_rw.1208665572
Directory /workspace/18.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_passthru_mem_tl_intg_err.3849862535
Short name T74
Test name
Test status
Simulation time 36587440991 ps
CPU time 74.75 seconds
Started Mar 03 12:41:01 PM PST 24
Finished Mar 03 12:42:15 PM PST 24
Peak memory 211252 kb
Host smart-e1155f12-14f9-44f1-8b4c-2c40cac6dde7
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3849862535 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_p
assthru_mem_tl_intg_err.3849862535
Directory /workspace/18.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_same_csr_outstanding.4015904793
Short name T438
Test name
Test status
Simulation time 1839404529 ps
CPU time 14.6 seconds
Started Mar 03 12:41:07 PM PST 24
Finished Mar 03 12:41:22 PM PST 24
Peak memory 211116 kb
Host smart-046114a3-c939-4a8c-918f-db1c6753537d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4015904793 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_
ctrl_same_csr_outstanding.4015904793
Directory /workspace/18.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_errors.3340128280
Short name T374
Test name
Test status
Simulation time 1117944842 ps
CPU time 13.3 seconds
Started Mar 03 12:41:02 PM PST 24
Finished Mar 03 12:41:16 PM PST 24
Peak memory 215232 kb
Host smart-94ce6ede-4f2d-40ff-8e88-442c9d6ce261
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3340128280 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_tl_errors.3340128280
Directory /workspace/18.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_intg_err.3176412616
Short name T398
Test name
Test status
Simulation time 408631483 ps
CPU time 37.23 seconds
Started Mar 03 12:41:27 PM PST 24
Finished Mar 03 12:42:05 PM PST 24
Peak memory 211584 kb
Host smart-4f98ff64-3a8c-4345-93a5-48e1ffd6b2d6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3176412616 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_tl_i
ntg_err.3176412616
Directory /workspace/18.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_mem_rw_with_rand_reset.921214366
Short name T376
Test name
Test status
Simulation time 95732634 ps
CPU time 4.43 seconds
Started Mar 03 12:41:14 PM PST 24
Finished Mar 03 12:41:18 PM PST 24
Peak memory 211940 kb
Host smart-e1e0874e-60ab-4ba7-b55a-9adc6daaf4ff
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=921214366 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 19.rom_ctrl_csr_mem_rw_with_rand_reset.921214366
Directory /workspace/19.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_rw.869876093
Short name T90
Test name
Test status
Simulation time 347484395 ps
CPU time 4.28 seconds
Started Mar 03 12:41:05 PM PST 24
Finished Mar 03 12:41:09 PM PST 24
Peak memory 211012 kb
Host smart-9d976777-624f-4514-8664-fac7e2b43e41
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=869876093 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_csr_rw.869876093
Directory /workspace/19.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_same_csr_outstanding.856813360
Short name T61
Test name
Test status
Simulation time 2147360541 ps
CPU time 15.92 seconds
Started Mar 03 12:41:19 PM PST 24
Finished Mar 03 12:41:35 PM PST 24
Peak memory 211132 kb
Host smart-e539428a-2bbb-48c0-8101-f2be3e463132
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=856813360 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_c
trl_same_csr_outstanding.856813360
Directory /workspace/19.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_errors.1501958979
Short name T420
Test name
Test status
Simulation time 5445032841 ps
CPU time 14.22 seconds
Started Mar 03 12:41:19 PM PST 24
Finished Mar 03 12:41:34 PM PST 24
Peak memory 216064 kb
Host smart-1ac4aeac-d7e4-483f-8f22-fa5a16db1fc8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1501958979 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_tl_errors.1501958979
Directory /workspace/19.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_intg_err.3380379767
Short name T451
Test name
Test status
Simulation time 3977651246 ps
CPU time 46.21 seconds
Started Mar 03 12:41:16 PM PST 24
Finished Mar 03 12:42:02 PM PST 24
Peak memory 211728 kb
Host smart-02977fbd-b894-40c5-9319-b13af8979d9b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3380379767 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_tl_i
ntg_err.3380379767
Directory /workspace/19.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_aliasing.2977444531
Short name T97
Test name
Test status
Simulation time 532014423 ps
CPU time 7.6 seconds
Started Mar 03 12:40:48 PM PST 24
Finished Mar 03 12:40:55 PM PST 24
Peak memory 211044 kb
Host smart-4d901eb8-ff75-4c9e-a407-9f1ac8d19792
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2977444531 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_alia
sing.2977444531
Directory /workspace/2.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_bit_bash.1383554232
Short name T381
Test name
Test status
Simulation time 1426456069 ps
CPU time 8.98 seconds
Started Mar 03 12:40:51 PM PST 24
Finished Mar 03 12:41:05 PM PST 24
Peak memory 211064 kb
Host smart-db6815f3-a6ed-414c-a993-7f73a10eb55f
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1383554232 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_bit_
bash.1383554232
Directory /workspace/2.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_hw_reset.4066731961
Short name T388
Test name
Test status
Simulation time 2794179777 ps
CPU time 13.83 seconds
Started Mar 03 12:40:56 PM PST 24
Finished Mar 03 12:41:10 PM PST 24
Peak memory 211260 kb
Host smart-e64749dc-a033-4834-a2c1-c3830496fb4b
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4066731961 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_hw_r
eset.4066731961
Directory /workspace/2.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_mem_rw_with_rand_reset.778946373
Short name T385
Test name
Test status
Simulation time 6779542725 ps
CPU time 11.41 seconds
Started Mar 03 12:40:39 PM PST 24
Finished Mar 03 12:40:51 PM PST 24
Peak memory 213616 kb
Host smart-4458dd7b-e35f-42b4-83cd-7c5b3b0a8125
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=778946373 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 2.rom_ctrl_csr_mem_rw_with_rand_reset.778946373
Directory /workspace/2.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_rw.763115444
Short name T461
Test name
Test status
Simulation time 434533793 ps
CPU time 5.81 seconds
Started Mar 03 12:40:45 PM PST 24
Finished Mar 03 12:40:51 PM PST 24
Peak memory 211076 kb
Host smart-33752de9-71bd-41be-85fb-69087c2dffca
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=763115444 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_rw.763115444
Directory /workspace/2.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_partial_access.2190572292
Short name T432
Test name
Test status
Simulation time 7832109628 ps
CPU time 11.23 seconds
Started Mar 03 12:40:47 PM PST 24
Finished Mar 03 12:40:59 PM PST 24
Peak memory 211132 kb
Host smart-887c13d5-945c-4e02-b599-6b337968532b
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2190572292 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctr
l_mem_partial_access.2190572292
Directory /workspace/2.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_walk.191683145
Short name T409
Test name
Test status
Simulation time 86487915 ps
CPU time 4.15 seconds
Started Mar 03 12:40:42 PM PST 24
Finished Mar 03 12:40:47 PM PST 24
Peak memory 211000 kb
Host smart-967d0ad1-e745-4e8a-a05a-934830a65f8b
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=191683145 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_mem_walk.
191683145
Directory /workspace/2.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_passthru_mem_tl_intg_err.2282610934
Short name T449
Test name
Test status
Simulation time 11471589610 ps
CPU time 45.9 seconds
Started Mar 03 12:40:50 PM PST 24
Finished Mar 03 12:41:36 PM PST 24
Peak memory 211224 kb
Host smart-1d8c3d54-6ee4-4f6e-bbb7-da494598487a
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2282610934 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_pa
ssthru_mem_tl_intg_err.2282610934
Directory /workspace/2.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_same_csr_outstanding.2235155177
Short name T465
Test name
Test status
Simulation time 4325625754 ps
CPU time 14.14 seconds
Started Mar 03 12:40:42 PM PST 24
Finished Mar 03 12:40:56 PM PST 24
Peak memory 211252 kb
Host smart-996abfea-bcba-403a-ba0a-a04c165a9f85
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2235155177 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_c
trl_same_csr_outstanding.2235155177
Directory /workspace/2.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_errors.3717834119
Short name T373
Test name
Test status
Simulation time 1059855812 ps
CPU time 12.94 seconds
Started Mar 03 12:40:52 PM PST 24
Finished Mar 03 12:41:05 PM PST 24
Peak memory 216400 kb
Host smart-dfdf8f77-a6f9-476c-942b-0ef1e4c31575
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3717834119 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_tl_errors.3717834119
Directory /workspace/2.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_intg_err.1712279289
Short name T57
Test name
Test status
Simulation time 1198895583 ps
CPU time 70.13 seconds
Started Mar 03 12:40:51 PM PST 24
Finished Mar 03 12:42:01 PM PST 24
Peak memory 213116 kb
Host smart-6a439545-bca0-43e5-96cc-182e5dadf83f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1712279289 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_tl_in
tg_err.1712279289
Directory /workspace/2.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_aliasing.3074014891
Short name T424
Test name
Test status
Simulation time 451282986 ps
CPU time 6.25 seconds
Started Mar 03 12:40:55 PM PST 24
Finished Mar 03 12:41:01 PM PST 24
Peak memory 211052 kb
Host smart-43c4ac6a-c8c5-4231-b5be-eec4d6525415
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3074014891 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_alia
sing.3074014891
Directory /workspace/3.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_bit_bash.2493211433
Short name T430
Test name
Test status
Simulation time 423278330 ps
CPU time 5.93 seconds
Started Mar 03 12:40:31 PM PST 24
Finished Mar 03 12:40:37 PM PST 24
Peak memory 211056 kb
Host smart-06dfe386-68cc-41a5-9b5f-316f27498224
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2493211433 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_bit_
bash.2493211433
Directory /workspace/3.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_hw_reset.1130654853
Short name T66
Test name
Test status
Simulation time 99227426 ps
CPU time 7.62 seconds
Started Mar 03 12:41:11 PM PST 24
Finished Mar 03 12:41:19 PM PST 24
Peak memory 211064 kb
Host smart-3cf6c393-cdbe-4b3c-a78a-146408304116
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1130654853 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_hw_r
eset.1130654853
Directory /workspace/3.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_mem_rw_with_rand_reset.2808217086
Short name T421
Test name
Test status
Simulation time 496681916 ps
CPU time 5.28 seconds
Started Mar 03 12:41:05 PM PST 24
Finished Mar 03 12:41:11 PM PST 24
Peak memory 215376 kb
Host smart-ec4a9ef5-bb1f-4fde-8c22-638719f8b3e9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2808217086 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 3.rom_ctrl_csr_mem_rw_with_rand_reset.2808217086
Directory /workspace/3.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_rw.1129537127
Short name T410
Test name
Test status
Simulation time 1465294488 ps
CPU time 12.72 seconds
Started Mar 03 12:40:45 PM PST 24
Finished Mar 03 12:40:58 PM PST 24
Peak memory 211048 kb
Host smart-807cd111-a542-415f-b6f5-69608e9f0193
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1129537127 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_rw.1129537127
Directory /workspace/3.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_partial_access.474441220
Short name T366
Test name
Test status
Simulation time 1798427799 ps
CPU time 14.24 seconds
Started Mar 03 12:40:51 PM PST 24
Finished Mar 03 12:41:05 PM PST 24
Peak memory 210976 kb
Host smart-38eb6cba-e5ca-4174-9c6a-8aed5453ff33
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=474441220 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl
_mem_partial_access.474441220
Directory /workspace/3.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_walk.804359804
Short name T443
Test name
Test status
Simulation time 7389476700 ps
CPU time 10.99 seconds
Started Mar 03 12:40:57 PM PST 24
Finished Mar 03 12:41:09 PM PST 24
Peak memory 211044 kb
Host smart-81bc2f61-8575-4157-9258-6313ed29a73c
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=804359804 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_mem_walk.
804359804
Directory /workspace/3.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_passthru_mem_tl_intg_err.4200948716
Short name T84
Test name
Test status
Simulation time 65168223588 ps
CPU time 72.29 seconds
Started Mar 03 12:40:44 PM PST 24
Finished Mar 03 12:41:56 PM PST 24
Peak memory 211216 kb
Host smart-94265b49-5fd6-4b2f-b82b-505abd03e2b2
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4200948716 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_pa
ssthru_mem_tl_intg_err.4200948716
Directory /workspace/3.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_same_csr_outstanding.3379604983
Short name T419
Test name
Test status
Simulation time 4431682215 ps
CPU time 13.19 seconds
Started Mar 03 12:40:50 PM PST 24
Finished Mar 03 12:41:03 PM PST 24
Peak memory 211248 kb
Host smart-3dffdaa3-ef2b-4d1c-b2bc-04a864787882
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3379604983 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_c
trl_same_csr_outstanding.3379604983
Directory /workspace/3.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_errors.1042011021
Short name T390
Test name
Test status
Simulation time 532548043 ps
CPU time 8.28 seconds
Started Mar 03 12:40:55 PM PST 24
Finished Mar 03 12:41:04 PM PST 24
Peak memory 215288 kb
Host smart-8fae2b03-ddb3-42b3-8e19-7639392e7881
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1042011021 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_tl_errors.1042011021
Directory /workspace/3.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_intg_err.2865290606
Short name T450
Test name
Test status
Simulation time 8219768167 ps
CPU time 44.6 seconds
Started Mar 03 12:40:59 PM PST 24
Finished Mar 03 12:41:44 PM PST 24
Peak memory 211332 kb
Host smart-17181f18-8c73-4adf-a4e7-bea93cf9900a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2865290606 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_tl_in
tg_err.2865290606
Directory /workspace/3.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_aliasing.946130798
Short name T397
Test name
Test status
Simulation time 19827736310 ps
CPU time 16.51 seconds
Started Mar 03 12:40:59 PM PST 24
Finished Mar 03 12:41:16 PM PST 24
Peak memory 211180 kb
Host smart-242af8b5-e071-45eb-a55f-2b3674600fac
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=946130798 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_alias
ing.946130798
Directory /workspace/4.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_bit_bash.1927691437
Short name T98
Test name
Test status
Simulation time 1811239455 ps
CPU time 7.44 seconds
Started Mar 03 12:40:54 PM PST 24
Finished Mar 03 12:41:02 PM PST 24
Peak memory 211024 kb
Host smart-7c72dcd5-523e-4e72-a9ad-0c4e14b1ff3f
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1927691437 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_bit_
bash.1927691437
Directory /workspace/4.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_hw_reset.2525499121
Short name T440
Test name
Test status
Simulation time 4521574175 ps
CPU time 14.51 seconds
Started Mar 03 12:40:50 PM PST 24
Finished Mar 03 12:41:05 PM PST 24
Peak memory 211236 kb
Host smart-81eda5a5-1481-4cb3-879e-9afa0020c0c8
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2525499121 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_hw_r
eset.2525499121
Directory /workspace/4.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_mem_rw_with_rand_reset.990708867
Short name T378
Test name
Test status
Simulation time 778670313 ps
CPU time 7.52 seconds
Started Mar 03 12:41:08 PM PST 24
Finished Mar 03 12:41:16 PM PST 24
Peak memory 215236 kb
Host smart-5af29e36-6629-4fd7-a359-5ca7465f988c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=990708867 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 4.rom_ctrl_csr_mem_rw_with_rand_reset.990708867
Directory /workspace/4.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_rw.971454388
Short name T96
Test name
Test status
Simulation time 5797124944 ps
CPU time 15.8 seconds
Started Mar 03 12:40:48 PM PST 24
Finished Mar 03 12:41:04 PM PST 24
Peak memory 211180 kb
Host smart-bcaf9393-2269-4d5e-b0ee-0581be79742c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=971454388 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_rw.971454388
Directory /workspace/4.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_partial_access.2169352707
Short name T395
Test name
Test status
Simulation time 5465668536 ps
CPU time 11.92 seconds
Started Mar 03 12:40:34 PM PST 24
Finished Mar 03 12:40:46 PM PST 24
Peak memory 211040 kb
Host smart-49b255c5-e224-44c1-9d12-27fd58cf7eb9
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2169352707 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctr
l_mem_partial_access.2169352707
Directory /workspace/4.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_walk.2478208489
Short name T382
Test name
Test status
Simulation time 13772915731 ps
CPU time 12.92 seconds
Started Mar 03 12:41:06 PM PST 24
Finished Mar 03 12:41:19 PM PST 24
Peak memory 211124 kb
Host smart-f1c8a51b-fa43-452e-8d01-afd501e665e2
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2478208489 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_mem_walk
.2478208489
Directory /workspace/4.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_passthru_mem_tl_intg_err.3345697219
Short name T425
Test name
Test status
Simulation time 8110604019 ps
CPU time 46.5 seconds
Started Mar 03 12:40:41 PM PST 24
Finished Mar 03 12:41:28 PM PST 24
Peak memory 211208 kb
Host smart-6ebaa9fc-b8df-4c39-8cd2-3ebb11ade968
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3345697219 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_pa
ssthru_mem_tl_intg_err.3345697219
Directory /workspace/4.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_same_csr_outstanding.2078912547
Short name T392
Test name
Test status
Simulation time 8760404971 ps
CPU time 16.17 seconds
Started Mar 03 12:40:57 PM PST 24
Finished Mar 03 12:41:13 PM PST 24
Peak memory 211228 kb
Host smart-f4c47aed-ede8-49d1-8ef9-f6f5c9255175
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2078912547 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_c
trl_same_csr_outstanding.2078912547
Directory /workspace/4.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_errors.3697660369
Short name T389
Test name
Test status
Simulation time 819497497 ps
CPU time 11.54 seconds
Started Mar 03 12:41:10 PM PST 24
Finished Mar 03 12:41:22 PM PST 24
Peak memory 215588 kb
Host smart-edf94e22-f069-43b0-beaa-bcc0a9943717
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3697660369 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_tl_errors.3697660369
Directory /workspace/4.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_mem_rw_with_rand_reset.63142634
Short name T365
Test name
Test status
Simulation time 295144425 ps
CPU time 6.84 seconds
Started Mar 03 12:40:59 PM PST 24
Finished Mar 03 12:41:06 PM PST 24
Peak memory 215696 kb
Host smart-0208e84a-46b1-4cab-ab79-4b7610502c99
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=63142634 -assert nopostproc +UVM_TESTNAME=r
om_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 5.rom_ctrl_csr_mem_rw_with_rand_reset.63142634
Directory /workspace/5.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_rw.385226939
Short name T466
Test name
Test status
Simulation time 974346101 ps
CPU time 5.36 seconds
Started Mar 03 12:40:56 PM PST 24
Finished Mar 03 12:41:02 PM PST 24
Peak memory 211396 kb
Host smart-7be12426-9c1c-4ef2-8034-fec176c12181
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=385226939 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_csr_rw.385226939
Directory /workspace/5.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_passthru_mem_tl_intg_err.2094367982
Short name T434
Test name
Test status
Simulation time 1441333363 ps
CPU time 18.58 seconds
Started Mar 03 12:40:54 PM PST 24
Finished Mar 03 12:41:12 PM PST 24
Peak memory 211212 kb
Host smart-9a45513e-81a3-4e5e-99aa-3ba15fecc017
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2094367982 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_pa
ssthru_mem_tl_intg_err.2094367982
Directory /workspace/5.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_same_csr_outstanding.1723607402
Short name T411
Test name
Test status
Simulation time 456816097 ps
CPU time 7.16 seconds
Started Mar 03 12:41:09 PM PST 24
Finished Mar 03 12:41:17 PM PST 24
Peak memory 211132 kb
Host smart-bbb7981f-8437-4efa-af5c-ffd91d576f44
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1723607402 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_c
trl_same_csr_outstanding.1723607402
Directory /workspace/5.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_errors.1211478969
Short name T369
Test name
Test status
Simulation time 2926675612 ps
CPU time 16.34 seconds
Started Mar 03 12:41:02 PM PST 24
Finished Mar 03 12:41:18 PM PST 24
Peak memory 216380 kb
Host smart-a0484ff0-0014-4a4e-9c62-7db00a6ade20
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1211478969 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_tl_errors.1211478969
Directory /workspace/5.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_intg_err.388362927
Short name T109
Test name
Test status
Simulation time 1546093678 ps
CPU time 44.83 seconds
Started Mar 03 12:41:01 PM PST 24
Finished Mar 03 12:41:46 PM PST 24
Peak memory 211448 kb
Host smart-c2c818e8-5e01-4229-96ad-698306e447e8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=388362927 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_tl_int
g_err.388362927
Directory /workspace/5.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_mem_rw_with_rand_reset.1555935681
Short name T401
Test name
Test status
Simulation time 4763154560 ps
CPU time 9.24 seconds
Started Mar 03 12:41:15 PM PST 24
Finished Mar 03 12:41:24 PM PST 24
Peak memory 215368 kb
Host smart-77a529fc-a8b1-4c71-82bb-181537140627
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1555935681 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 6.rom_ctrl_csr_mem_rw_with_rand_reset.1555935681
Directory /workspace/6.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_rw.870143908
Short name T380
Test name
Test status
Simulation time 1960676231 ps
CPU time 15.15 seconds
Started Mar 03 12:40:58 PM PST 24
Finished Mar 03 12:41:13 PM PST 24
Peak memory 211156 kb
Host smart-78460d55-9171-42c8-b4d9-e0705f01e4b2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=870143908 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_csr_rw.870143908
Directory /workspace/6.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_passthru_mem_tl_intg_err.1832875808
Short name T82
Test name
Test status
Simulation time 35566214415 ps
CPU time 77.07 seconds
Started Mar 03 12:40:44 PM PST 24
Finished Mar 03 12:42:06 PM PST 24
Peak memory 211212 kb
Host smart-04255824-b438-470d-b6ef-233ad9ba58a7
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1832875808 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_pa
ssthru_mem_tl_intg_err.1832875808
Directory /workspace/6.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_same_csr_outstanding.4234051172
Short name T70
Test name
Test status
Simulation time 678044595 ps
CPU time 10.2 seconds
Started Mar 03 12:40:56 PM PST 24
Finished Mar 03 12:41:07 PM PST 24
Peak memory 211116 kb
Host smart-671db157-c4b0-479c-b384-ddf2ed67e2b4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4234051172 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_c
trl_same_csr_outstanding.4234051172
Directory /workspace/6.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_errors.2159269106
Short name T455
Test name
Test status
Simulation time 1926203735 ps
CPU time 19.55 seconds
Started Mar 03 12:41:03 PM PST 24
Finished Mar 03 12:41:23 PM PST 24
Peak memory 216580 kb
Host smart-762a85f2-f2d1-4d0d-95c2-3d162db1d3af
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2159269106 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_tl_errors.2159269106
Directory /workspace/6.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_intg_err.3153051852
Short name T112
Test name
Test status
Simulation time 421093706 ps
CPU time 69.76 seconds
Started Mar 03 12:40:54 PM PST 24
Finished Mar 03 12:42:03 PM PST 24
Peak memory 211124 kb
Host smart-a3f6d4eb-5765-4db8-b99a-549bf30a23dd
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3153051852 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_tl_in
tg_err.3153051852
Directory /workspace/6.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_mem_rw_with_rand_reset.3787457742
Short name T372
Test name
Test status
Simulation time 1698646083 ps
CPU time 14.11 seconds
Started Mar 03 12:40:39 PM PST 24
Finished Mar 03 12:40:53 PM PST 24
Peak memory 215196 kb
Host smart-702f976c-1a20-48a4-8c88-9e80cf0035ab
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3787457742 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 7.rom_ctrl_csr_mem_rw_with_rand_reset.3787457742
Directory /workspace/7.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_rw.2132611796
Short name T413
Test name
Test status
Simulation time 8236831157 ps
CPU time 15.44 seconds
Started Mar 03 12:40:52 PM PST 24
Finished Mar 03 12:41:13 PM PST 24
Peak memory 211192 kb
Host smart-a9ed330e-6d9c-4a56-ae6f-0e2709674aab
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2132611796 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_csr_rw.2132611796
Directory /workspace/7.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_passthru_mem_tl_intg_err.3589726459
Short name T102
Test name
Test status
Simulation time 13636447450 ps
CPU time 37.05 seconds
Started Mar 03 12:41:14 PM PST 24
Finished Mar 03 12:41:51 PM PST 24
Peak memory 211328 kb
Host smart-c38f6ebc-7720-4a96-a64f-a1c947182b69
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3589726459 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_pa
ssthru_mem_tl_intg_err.3589726459
Directory /workspace/7.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_same_csr_outstanding.3423269161
Short name T444
Test name
Test status
Simulation time 6870144528 ps
CPU time 16.37 seconds
Started Mar 03 12:41:01 PM PST 24
Finished Mar 03 12:41:18 PM PST 24
Peak memory 211192 kb
Host smart-12949531-a8f5-4bb6-9128-8585482bf342
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3423269161 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_c
trl_same_csr_outstanding.3423269161
Directory /workspace/7.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_errors.3584504453
Short name T456
Test name
Test status
Simulation time 6628715682 ps
CPU time 17.43 seconds
Started Mar 03 12:40:56 PM PST 24
Finished Mar 03 12:41:14 PM PST 24
Peak memory 215856 kb
Host smart-00dbd46f-2c95-4531-a178-4c0ae46dc424
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3584504453 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_tl_errors.3584504453
Directory /workspace/7.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_intg_err.496835779
Short name T113
Test name
Test status
Simulation time 667829275 ps
CPU time 74.92 seconds
Started Mar 03 12:40:57 PM PST 24
Finished Mar 03 12:42:12 PM PST 24
Peak memory 211908 kb
Host smart-eca43cde-d679-40a5-b649-d3d7be55bdd0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=496835779 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_tl_int
g_err.496835779
Directory /workspace/7.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_mem_rw_with_rand_reset.1392603684
Short name T408
Test name
Test status
Simulation time 3497503361 ps
CPU time 14.63 seconds
Started Mar 03 12:41:15 PM PST 24
Finished Mar 03 12:41:29 PM PST 24
Peak memory 212792 kb
Host smart-220431be-5de9-4b94-a6df-e35516c63000
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1392603684 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 8.rom_ctrl_csr_mem_rw_with_rand_reset.1392603684
Directory /workspace/8.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_rw.1758224052
Short name T437
Test name
Test status
Simulation time 88360247 ps
CPU time 4.21 seconds
Started Mar 03 12:41:05 PM PST 24
Finished Mar 03 12:41:09 PM PST 24
Peak memory 211152 kb
Host smart-cb1a35e9-5548-46e6-ab2c-ef624d460961
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1758224052 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_csr_rw.1758224052
Directory /workspace/8.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_passthru_mem_tl_intg_err.2982210753
Short name T88
Test name
Test status
Simulation time 12867960048 ps
CPU time 53.59 seconds
Started Mar 03 12:40:58 PM PST 24
Finished Mar 03 12:41:51 PM PST 24
Peak memory 211248 kb
Host smart-b767cdd2-87c5-462a-8cef-aef282a9b0f7
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2982210753 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_pa
ssthru_mem_tl_intg_err.2982210753
Directory /workspace/8.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_same_csr_outstanding.4137360709
Short name T94
Test name
Test status
Simulation time 3925090994 ps
CPU time 10.15 seconds
Started Mar 03 12:41:32 PM PST 24
Finished Mar 03 12:41:48 PM PST 24
Peak memory 211216 kb
Host smart-3855224c-af15-4870-8426-2401e1593e41
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4137360709 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_c
trl_same_csr_outstanding.4137360709
Directory /workspace/8.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_errors.1006870971
Short name T371
Test name
Test status
Simulation time 1882267598 ps
CPU time 9.63 seconds
Started Mar 03 12:40:59 PM PST 24
Finished Mar 03 12:41:09 PM PST 24
Peak memory 215172 kb
Host smart-17d448b9-b726-4873-98f5-d68e6b414968
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1006870971 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_tl_errors.1006870971
Directory /workspace/8.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_intg_err.3905707158
Short name T452
Test name
Test status
Simulation time 1916786502 ps
CPU time 78.47 seconds
Started Mar 03 12:41:05 PM PST 24
Finished Mar 03 12:42:23 PM PST 24
Peak memory 212888 kb
Host smart-d62f52ff-560c-49c4-9eb5-3add38218887
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3905707158 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_tl_in
tg_err.3905707158
Directory /workspace/8.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_mem_rw_with_rand_reset.1219630348
Short name T415
Test name
Test status
Simulation time 2500771247 ps
CPU time 12.07 seconds
Started Mar 03 12:41:15 PM PST 24
Finished Mar 03 12:41:27 PM PST 24
Peak memory 215040 kb
Host smart-33a9ef51-4ca2-49f7-b2bf-03da0ed5f705
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1219630348 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 9.rom_ctrl_csr_mem_rw_with_rand_reset.1219630348
Directory /workspace/9.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_rw.4014540770
Short name T60
Test name
Test status
Simulation time 695975716 ps
CPU time 5.36 seconds
Started Mar 03 12:41:02 PM PST 24
Finished Mar 03 12:41:07 PM PST 24
Peak memory 211068 kb
Host smart-648d1009-c5e7-49cd-a934-587067564e14
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4014540770 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_csr_rw.4014540770
Directory /workspace/9.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_passthru_mem_tl_intg_err.3611318339
Short name T68
Test name
Test status
Simulation time 378184762 ps
CPU time 19.38 seconds
Started Mar 03 12:41:38 PM PST 24
Finished Mar 03 12:41:58 PM PST 24
Peak memory 211212 kb
Host smart-72020013-272d-4619-9fce-f6177b6669e9
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3611318339 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_pa
ssthru_mem_tl_intg_err.3611318339
Directory /workspace/9.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_same_csr_outstanding.4119274517
Short name T394
Test name
Test status
Simulation time 2672569886 ps
CPU time 8.73 seconds
Started Mar 03 12:41:02 PM PST 24
Finished Mar 03 12:41:11 PM PST 24
Peak memory 211224 kb
Host smart-6671b635-1af3-4130-ac8a-f67619109e5a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4119274517 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_c
trl_same_csr_outstanding.4119274517
Directory /workspace/9.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_errors.3284546547
Short name T448
Test name
Test status
Simulation time 7428022073 ps
CPU time 19.03 seconds
Started Mar 03 12:41:15 PM PST 24
Finished Mar 03 12:41:34 PM PST 24
Peak memory 215760 kb
Host smart-5a21c77a-b473-4858-bf3e-6aa657986d8d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3284546547 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_tl_errors.3284546547
Directory /workspace/9.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/default/0.rom_ctrl_alert_test.3295507238
Short name T117
Test name
Test status
Simulation time 128606063 ps
CPU time 5.05 seconds
Started Mar 03 02:31:18 PM PST 24
Finished Mar 03 02:31:24 PM PST 24
Peak memory 210864 kb
Host smart-15a3a627-5a71-47cc-b934-95d11b8e8dc0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3295507238 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_alert_test.3295507238
Directory /workspace/0.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/0.rom_ctrl_corrupt_sig_fatal_chk.611319860
Short name T156
Test name
Test status
Simulation time 10800321499 ps
CPU time 105.5 seconds
Started Mar 03 02:31:16 PM PST 24
Finished Mar 03 02:33:01 PM PST 24
Peak memory 237492 kb
Host smart-424b15ea-c910-48dd-b668-097333fd138f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=611319860 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_co
rrupt_sig_fatal_chk.611319860
Directory /workspace/0.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/0.rom_ctrl_kmac_err_chk.204672325
Short name T300
Test name
Test status
Simulation time 1235328232 ps
CPU time 17.64 seconds
Started Mar 03 02:31:16 PM PST 24
Finished Mar 03 02:31:34 PM PST 24
Peak memory 212024 kb
Host smart-ce895eea-5c55-4211-bdcc-d4c245d86dcf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=204672325 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_kmac_err_chk.204672325
Directory /workspace/0.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/0.rom_ctrl_max_throughput_chk.917697765
Short name T199
Test name
Test status
Simulation time 451893578 ps
CPU time 5.72 seconds
Started Mar 03 02:31:27 PM PST 24
Finished Mar 03 02:31:33 PM PST 24
Peak memory 210780 kb
Host smart-5a9738ff-3064-4382-bded-8a71a988117d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=917697765 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_max_throughput_chk.917697765
Directory /workspace/0.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/0.rom_ctrl_smoke.4081910978
Short name T167
Test name
Test status
Simulation time 3738056301 ps
CPU time 28.65 seconds
Started Mar 03 02:31:15 PM PST 24
Finished Mar 03 02:31:44 PM PST 24
Peak memory 212612 kb
Host smart-0782ca7a-e07a-4315-87bf-5ba3a95f55ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4081910978 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_smoke.4081910978
Directory /workspace/0.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/0.rom_ctrl_stress_all.3546699998
Short name T208
Test name
Test status
Simulation time 6744388355 ps
CPU time 15.51 seconds
Started Mar 03 02:31:13 PM PST 24
Finished Mar 03 02:31:29 PM PST 24
Peak memory 211504 kb
Host smart-0bf438d9-bffe-4717-8d61-8760e833573d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3546699998 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 0.rom_ctrl_stress_all.3546699998
Directory /workspace/0.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/1.rom_ctrl_alert_test.3462796312
Short name T201
Test name
Test status
Simulation time 2105658891 ps
CPU time 17.21 seconds
Started Mar 03 02:31:20 PM PST 24
Finished Mar 03 02:31:38 PM PST 24
Peak memory 210956 kb
Host smart-7a2a6611-c35a-4d0a-b21e-83daa63730a8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3462796312 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_alert_test.3462796312
Directory /workspace/1.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/1.rom_ctrl_corrupt_sig_fatal_chk.3887296893
Short name T216
Test name
Test status
Simulation time 4702731724 ps
CPU time 92.5 seconds
Started Mar 03 02:31:16 PM PST 24
Finished Mar 03 02:32:49 PM PST 24
Peak memory 220244 kb
Host smart-c3667674-4a13-43d8-93c9-4d63e582b940
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3887296893 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_c
orrupt_sig_fatal_chk.3887296893
Directory /workspace/1.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/1.rom_ctrl_kmac_err_chk.3993076657
Short name T222
Test name
Test status
Simulation time 2657852091 ps
CPU time 26.26 seconds
Started Mar 03 02:31:16 PM PST 24
Finished Mar 03 02:31:43 PM PST 24
Peak memory 211540 kb
Host smart-81ad13e0-bbed-4b55-bbf2-d1c5619d1c52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3993076657 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_kmac_err_chk.3993076657
Directory /workspace/1.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/1.rom_ctrl_max_throughput_chk.37080411
Short name T352
Test name
Test status
Simulation time 953921586 ps
CPU time 10.53 seconds
Started Mar 03 02:31:28 PM PST 24
Finished Mar 03 02:31:39 PM PST 24
Peak memory 210776 kb
Host smart-2eeb2906-5c61-4657-bb91-89392d639258
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=37080411 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_max_throughput_chk.37080411
Directory /workspace/1.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/1.rom_ctrl_sec_cm.1472519051
Short name T31
Test name
Test status
Simulation time 1142171982 ps
CPU time 103.39 seconds
Started Mar 03 02:31:21 PM PST 24
Finished Mar 03 02:33:05 PM PST 24
Peak memory 229820 kb
Host smart-f72d5cd3-5b96-4395-b66b-7734f18732da
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1472519051 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_sec_cm.1472519051
Directory /workspace/1.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/1.rom_ctrl_smoke.4119985950
Short name T80
Test name
Test status
Simulation time 4204607858 ps
CPU time 41.63 seconds
Started Mar 03 02:31:15 PM PST 24
Finished Mar 03 02:31:57 PM PST 24
Peak memory 212588 kb
Host smart-2492fb24-d3dc-4e6e-b1a0-639e7bff5a75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4119985950 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_smoke.4119985950
Directory /workspace/1.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/1.rom_ctrl_stress_all.3921382185
Short name T19
Test name
Test status
Simulation time 8542418139 ps
CPU time 38.68 seconds
Started Mar 03 02:31:19 PM PST 24
Finished Mar 03 02:31:58 PM PST 24
Peak memory 213196 kb
Host smart-e3bab3d4-8d80-4131-aa3b-1d6d8a51e4c8
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3921382185 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 1.rom_ctrl_stress_all.3921382185
Directory /workspace/1.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/1.rom_ctrl_stress_all_with_rand_reset.3329923482
Short name T298
Test name
Test status
Simulation time 21799918274 ps
CPU time 5733.34 seconds
Started Mar 03 02:31:21 PM PST 24
Finished Mar 03 04:06:56 PM PST 24
Peak memory 230580 kb
Host smart-918d7981-433d-4743-a0db-3d6688314e89
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3329923482 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_stress_all_with_rand_reset.3329923482
Directory /workspace/1.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.rom_ctrl_alert_test.532956798
Short name T334
Test name
Test status
Simulation time 88452617 ps
CPU time 4.28 seconds
Started Mar 03 02:31:46 PM PST 24
Finished Mar 03 02:31:50 PM PST 24
Peak memory 210872 kb
Host smart-7c98b5af-5830-46aa-873e-f447b64bde96
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=532956798 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_alert_test.532956798
Directory /workspace/10.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/10.rom_ctrl_corrupt_sig_fatal_chk.4136566033
Short name T288
Test name
Test status
Simulation time 89295526937 ps
CPU time 190.99 seconds
Started Mar 03 02:31:48 PM PST 24
Finished Mar 03 02:35:00 PM PST 24
Peak memory 212240 kb
Host smart-25276842-62a5-485b-b2d7-83261c9bc5c3
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4136566033 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_
corrupt_sig_fatal_chk.4136566033
Directory /workspace/10.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/10.rom_ctrl_smoke.2870893241
Short name T357
Test name
Test status
Simulation time 13148709400 ps
CPU time 36.62 seconds
Started Mar 03 02:31:41 PM PST 24
Finished Mar 03 02:32:19 PM PST 24
Peak memory 213964 kb
Host smart-04ed00d7-47a4-4a79-b6ca-7d6d1eed2bd3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2870893241 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_smoke.2870893241
Directory /workspace/10.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/10.rom_ctrl_stress_all.2727236936
Short name T77
Test name
Test status
Simulation time 6899659385 ps
CPU time 33.59 seconds
Started Mar 03 02:31:46 PM PST 24
Finished Mar 03 02:32:20 PM PST 24
Peak memory 219072 kb
Host smart-a8b20063-cc49-4a62-b77a-533e238a14ef
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2727236936 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 10.rom_ctrl_stress_all.2727236936
Directory /workspace/10.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/10.rom_ctrl_stress_all_with_rand_reset.3320420737
Short name T50
Test name
Test status
Simulation time 110543253862 ps
CPU time 3321.84 seconds
Started Mar 03 02:31:47 PM PST 24
Finished Mar 03 03:27:10 PM PST 24
Peak memory 251900 kb
Host smart-43a88729-9889-4d57-bcb9-f259c68108e6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3320420737 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_stress_all_with_rand_reset.3320420737
Directory /workspace/10.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/11.rom_ctrl_alert_test.1647723801
Short name T279
Test name
Test status
Simulation time 10885572431 ps
CPU time 11.36 seconds
Started Mar 03 02:31:45 PM PST 24
Finished Mar 03 02:31:56 PM PST 24
Peak memory 210932 kb
Host smart-868648a8-7177-46fe-9723-6794fb176715
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1647723801 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_alert_test.1647723801
Directory /workspace/11.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/11.rom_ctrl_corrupt_sig_fatal_chk.2494455068
Short name T280
Test name
Test status
Simulation time 85372070481 ps
CPU time 209.3 seconds
Started Mar 03 02:31:46 PM PST 24
Finished Mar 03 02:35:15 PM PST 24
Peak memory 219420 kb
Host smart-41ed3f0c-59f7-4a68-9a50-04c47e700cbf
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2494455068 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_
corrupt_sig_fatal_chk.2494455068
Directory /workspace/11.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/11.rom_ctrl_kmac_err_chk.4078564759
Short name T318
Test name
Test status
Simulation time 3006476318 ps
CPU time 24.33 seconds
Started Mar 03 02:31:48 PM PST 24
Finished Mar 03 02:32:13 PM PST 24
Peak memory 211380 kb
Host smart-ba205833-904d-458e-9aa7-a36eb437576c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4078564759 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_kmac_err_chk.4078564759
Directory /workspace/11.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/11.rom_ctrl_max_throughput_chk.4225882403
Short name T128
Test name
Test status
Simulation time 386614348 ps
CPU time 5.5 seconds
Started Mar 03 02:31:45 PM PST 24
Finished Mar 03 02:31:51 PM PST 24
Peak memory 210800 kb
Host smart-7e3d6536-ee48-409a-bf89-6df3b0a46f57
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4225882403 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_max_throughput_chk.4225882403
Directory /workspace/11.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/11.rom_ctrl_stress_all.2086249361
Short name T252
Test name
Test status
Simulation time 145399325208 ps
CPU time 85.51 seconds
Started Mar 03 02:31:47 PM PST 24
Finished Mar 03 02:33:13 PM PST 24
Peak memory 213684 kb
Host smart-c17aadd9-b6ce-4fa1-9a8a-b778aadefe8d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2086249361 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 11.rom_ctrl_stress_all.2086249361
Directory /workspace/11.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/12.rom_ctrl_alert_test.2762942435
Short name T26
Test name
Test status
Simulation time 8596750678 ps
CPU time 9.99 seconds
Started Mar 03 02:31:48 PM PST 24
Finished Mar 03 02:31:58 PM PST 24
Peak memory 211028 kb
Host smart-c079e157-69ff-4d8d-bb0e-edc8b8b03ac0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2762942435 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_alert_test.2762942435
Directory /workspace/12.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/12.rom_ctrl_corrupt_sig_fatal_chk.3537962807
Short name T135
Test name
Test status
Simulation time 125663736365 ps
CPU time 155.31 seconds
Started Mar 03 02:31:48 PM PST 24
Finished Mar 03 02:34:24 PM PST 24
Peak memory 229460 kb
Host smart-8a358658-f9d8-4811-a3c7-860322d7cbdb
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3537962807 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_
corrupt_sig_fatal_chk.3537962807
Directory /workspace/12.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/12.rom_ctrl_kmac_err_chk.436534712
Short name T175
Test name
Test status
Simulation time 2191276303 ps
CPU time 23.59 seconds
Started Mar 03 02:31:47 PM PST 24
Finished Mar 03 02:32:11 PM PST 24
Peak memory 211468 kb
Host smart-eccb4806-95a0-4e93-b9bd-b80d62d1838b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=436534712 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_kmac_err_chk.436534712
Directory /workspace/12.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/12.rom_ctrl_max_throughput_chk.1994302672
Short name T126
Test name
Test status
Simulation time 716665865 ps
CPU time 9.89 seconds
Started Mar 03 02:31:46 PM PST 24
Finished Mar 03 02:31:57 PM PST 24
Peak memory 210792 kb
Host smart-96764a8c-5363-448c-bd0b-2632a015d9ed
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1994302672 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_max_throughput_chk.1994302672
Directory /workspace/12.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/12.rom_ctrl_smoke.1285397457
Short name T340
Test name
Test status
Simulation time 14734483171 ps
CPU time 25.93 seconds
Started Mar 03 02:31:47 PM PST 24
Finished Mar 03 02:32:13 PM PST 24
Peak memory 213632 kb
Host smart-f15df203-178a-4abc-b763-611366022134
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1285397457 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_smoke.1285397457
Directory /workspace/12.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/12.rom_ctrl_stress_all.3051017243
Short name T329
Test name
Test status
Simulation time 4084835507 ps
CPU time 28.53 seconds
Started Mar 03 02:31:46 PM PST 24
Finished Mar 03 02:32:15 PM PST 24
Peak memory 213132 kb
Host smart-7154d962-2bc4-45d7-b7bb-3269baf1b56c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3051017243 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 12.rom_ctrl_stress_all.3051017243
Directory /workspace/12.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/13.rom_ctrl_alert_test.534641543
Short name T225
Test name
Test status
Simulation time 4570605502 ps
CPU time 11.25 seconds
Started Mar 03 02:31:52 PM PST 24
Finished Mar 03 02:32:04 PM PST 24
Peak memory 210936 kb
Host smart-5814e896-1536-45a8-bd15-e86ddcd5ad24
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=534641543 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_alert_test.534641543
Directory /workspace/13.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/13.rom_ctrl_corrupt_sig_fatal_chk.1445125677
Short name T353
Test name
Test status
Simulation time 29799689953 ps
CPU time 152.46 seconds
Started Mar 03 02:31:53 PM PST 24
Finished Mar 03 02:34:25 PM PST 24
Peak memory 237632 kb
Host smart-d3af840d-1e91-4ebe-bfd9-c6728186f71b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1445125677 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_
corrupt_sig_fatal_chk.1445125677
Directory /workspace/13.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/13.rom_ctrl_kmac_err_chk.2179809872
Short name T343
Test name
Test status
Simulation time 2140580979 ps
CPU time 22.58 seconds
Started Mar 03 02:31:52 PM PST 24
Finished Mar 03 02:32:15 PM PST 24
Peak memory 211472 kb
Host smart-b1687264-056f-4398-809a-ec0ff34c14f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2179809872 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_kmac_err_chk.2179809872
Directory /workspace/13.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/13.rom_ctrl_max_throughput_chk.85827672
Short name T40
Test name
Test status
Simulation time 3593655113 ps
CPU time 10.95 seconds
Started Mar 03 02:31:55 PM PST 24
Finished Mar 03 02:32:06 PM PST 24
Peak memory 210776 kb
Host smart-ff8206cd-bd39-46a4-8a4f-4830c96cde4d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=85827672 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_max_throughput_chk.85827672
Directory /workspace/13.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/13.rom_ctrl_smoke.470524513
Short name T136
Test name
Test status
Simulation time 2540975843 ps
CPU time 28.1 seconds
Started Mar 03 02:31:46 PM PST 24
Finished Mar 03 02:32:14 PM PST 24
Peak memory 213032 kb
Host smart-0d49a1b8-67fb-45e4-978c-4edf7291bdfc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=470524513 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_smoke.470524513
Directory /workspace/13.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/13.rom_ctrl_stress_all.3145621453
Short name T133
Test name
Test status
Simulation time 10712953941 ps
CPU time 88.84 seconds
Started Mar 03 02:31:57 PM PST 24
Finished Mar 03 02:33:26 PM PST 24
Peak memory 215876 kb
Host smart-3ddf16d3-ffc3-4a02-b480-8813508a167f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3145621453 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 13.rom_ctrl_stress_all.3145621453
Directory /workspace/13.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/14.rom_ctrl_alert_test.3404503464
Short name T36
Test name
Test status
Simulation time 5073619973 ps
CPU time 11.98 seconds
Started Mar 03 02:31:53 PM PST 24
Finished Mar 03 02:32:05 PM PST 24
Peak memory 210656 kb
Host smart-b212dc1a-d478-4c00-8840-c4190cf1dd93
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3404503464 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_alert_test.3404503464
Directory /workspace/14.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/14.rom_ctrl_kmac_err_chk.1042919786
Short name T344
Test name
Test status
Simulation time 2546082984 ps
CPU time 15.71 seconds
Started Mar 03 02:31:55 PM PST 24
Finished Mar 03 02:32:11 PM PST 24
Peak memory 211408 kb
Host smart-d14cbdff-e514-4bea-9b61-109d91943997
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1042919786 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_kmac_err_chk.1042919786
Directory /workspace/14.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/14.rom_ctrl_max_throughput_chk.272226634
Short name T297
Test name
Test status
Simulation time 455301052 ps
CPU time 5.59 seconds
Started Mar 03 02:31:51 PM PST 24
Finished Mar 03 02:31:57 PM PST 24
Peak memory 210796 kb
Host smart-bae6df62-ade9-47b3-b227-fe5cbc5a58c9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=272226634 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_max_throughput_chk.272226634
Directory /workspace/14.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/14.rom_ctrl_smoke.630675253
Short name T364
Test name
Test status
Simulation time 4151942358 ps
CPU time 16.82 seconds
Started Mar 03 02:31:55 PM PST 24
Finished Mar 03 02:32:12 PM PST 24
Peak memory 212804 kb
Host smart-b8fb0110-a6b9-48bd-815d-285627910bf0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=630675253 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_smoke.630675253
Directory /workspace/14.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/14.rom_ctrl_stress_all.857737876
Short name T256
Test name
Test status
Simulation time 38495018163 ps
CPU time 77.51 seconds
Started Mar 03 02:31:53 PM PST 24
Finished Mar 03 02:33:10 PM PST 24
Peak memory 218740 kb
Host smart-25e1aaf3-844a-4227-b8dc-fb59c92d2461
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=857737876 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 14.rom_ctrl_stress_all.857737876
Directory /workspace/14.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/15.rom_ctrl_alert_test.617185340
Short name T322
Test name
Test status
Simulation time 28517584509 ps
CPU time 16.63 seconds
Started Mar 03 02:31:58 PM PST 24
Finished Mar 03 02:32:14 PM PST 24
Peak memory 211008 kb
Host smart-1cdbb7f4-7cc4-4c04-9cbd-541ee1c1d913
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=617185340 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_alert_test.617185340
Directory /workspace/15.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/15.rom_ctrl_corrupt_sig_fatal_chk.1071688099
Short name T44
Test name
Test status
Simulation time 16617385701 ps
CPU time 182.19 seconds
Started Mar 03 02:31:56 PM PST 24
Finished Mar 03 02:34:58 PM PST 24
Peak memory 236396 kb
Host smart-3465669e-0411-4294-83cb-7cc5dd09facf
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1071688099 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_
corrupt_sig_fatal_chk.1071688099
Directory /workspace/15.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/15.rom_ctrl_kmac_err_chk.2093820769
Short name T241
Test name
Test status
Simulation time 6218227252 ps
CPU time 19.11 seconds
Started Mar 03 02:31:57 PM PST 24
Finished Mar 03 02:32:16 PM PST 24
Peak memory 212064 kb
Host smart-5263a412-9b18-4b10-9cbd-294869e914b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2093820769 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_kmac_err_chk.2093820769
Directory /workspace/15.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/15.rom_ctrl_max_throughput_chk.1494502316
Short name T100
Test name
Test status
Simulation time 1869706134 ps
CPU time 10.63 seconds
Started Mar 03 02:31:58 PM PST 24
Finished Mar 03 02:32:08 PM PST 24
Peak memory 210736 kb
Host smart-4036db22-b36f-4015-aa61-2702f322afb0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1494502316 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_max_throughput_chk.1494502316
Directory /workspace/15.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/15.rom_ctrl_smoke.131874757
Short name T130
Test name
Test status
Simulation time 4747790635 ps
CPU time 16.6 seconds
Started Mar 03 02:31:57 PM PST 24
Finished Mar 03 02:32:14 PM PST 24
Peak memory 212424 kb
Host smart-f9bbb6d6-7f46-4507-a387-631a17a55c6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=131874757 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_smoke.131874757
Directory /workspace/15.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/15.rom_ctrl_stress_all.3781427510
Short name T282
Test name
Test status
Simulation time 6640405171 ps
CPU time 34 seconds
Started Mar 03 02:32:00 PM PST 24
Finished Mar 03 02:32:34 PM PST 24
Peak memory 219132 kb
Host smart-7601b84c-459d-4583-b934-54164e20988b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3781427510 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 15.rom_ctrl_stress_all.3781427510
Directory /workspace/15.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/15.rom_ctrl_stress_all_with_rand_reset.1686232771
Short name T305
Test name
Test status
Simulation time 20031078110 ps
CPU time 381.1 seconds
Started Mar 03 02:32:01 PM PST 24
Finished Mar 03 02:38:22 PM PST 24
Peak memory 227388 kb
Host smart-f6909017-3442-4334-a55d-675506eebc7d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1686232771 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_stress_all_with_rand_reset.1686232771
Directory /workspace/15.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/16.rom_ctrl_alert_test.1109514507
Short name T244
Test name
Test status
Simulation time 162268108 ps
CPU time 4.35 seconds
Started Mar 03 02:32:09 PM PST 24
Finished Mar 03 02:32:14 PM PST 24
Peak memory 210948 kb
Host smart-a1469371-a2c3-4416-b8c0-e3e429300545
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1109514507 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_alert_test.1109514507
Directory /workspace/16.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/16.rom_ctrl_corrupt_sig_fatal_chk.1122648691
Short name T240
Test name
Test status
Simulation time 215640066939 ps
CPU time 345.7 seconds
Started Mar 03 02:32:03 PM PST 24
Finished Mar 03 02:37:49 PM PST 24
Peak memory 220376 kb
Host smart-259e6223-0f3b-47de-8790-6733781848aa
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1122648691 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_
corrupt_sig_fatal_chk.1122648691
Directory /workspace/16.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/16.rom_ctrl_kmac_err_chk.2522009962
Short name T6
Test name
Test status
Simulation time 2271198814 ps
CPU time 23.43 seconds
Started Mar 03 02:32:09 PM PST 24
Finished Mar 03 02:32:33 PM PST 24
Peak memory 210988 kb
Host smart-8da10703-f015-4478-84e9-39721f857ca6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2522009962 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_kmac_err_chk.2522009962
Directory /workspace/16.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/16.rom_ctrl_max_throughput_chk.3337738215
Short name T271
Test name
Test status
Simulation time 11131405522 ps
CPU time 16.49 seconds
Started Mar 03 02:32:03 PM PST 24
Finished Mar 03 02:32:20 PM PST 24
Peak memory 210864 kb
Host smart-226a577b-c657-4e2c-a710-97069ba7bb3d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3337738215 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_max_throughput_chk.3337738215
Directory /workspace/16.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/16.rom_ctrl_smoke.3076506389
Short name T164
Test name
Test status
Simulation time 11907643933 ps
CPU time 32.72 seconds
Started Mar 03 02:32:01 PM PST 24
Finished Mar 03 02:32:34 PM PST 24
Peak memory 213880 kb
Host smart-8413dfaa-f618-45a5-8a5c-0aa1d0fb4e05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3076506389 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_smoke.3076506389
Directory /workspace/16.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/16.rom_ctrl_stress_all.899645101
Short name T358
Test name
Test status
Simulation time 3605217650 ps
CPU time 17.48 seconds
Started Mar 03 02:32:01 PM PST 24
Finished Mar 03 02:32:19 PM PST 24
Peak memory 210964 kb
Host smart-810b83ab-12c1-4191-b2cd-a3c2f8850ea4
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=899645101 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 16.rom_ctrl_stress_all.899645101
Directory /workspace/16.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/16.rom_ctrl_stress_all_with_rand_reset.2047205538
Short name T348
Test name
Test status
Simulation time 451204302531 ps
CPU time 1958.45 seconds
Started Mar 03 02:32:03 PM PST 24
Finished Mar 03 03:04:42 PM PST 24
Peak memory 235592 kb
Host smart-9173d215-caa0-49f4-80d8-f87c19a7c7a1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2047205538 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_stress_all_with_rand_reset.2047205538
Directory /workspace/16.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/17.rom_ctrl_alert_test.1828621729
Short name T284
Test name
Test status
Simulation time 1280913654 ps
CPU time 11.73 seconds
Started Mar 03 02:32:10 PM PST 24
Finished Mar 03 02:32:22 PM PST 24
Peak memory 210944 kb
Host smart-28283030-a744-47b7-b77b-0b6362a952e1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1828621729 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_alert_test.1828621729
Directory /workspace/17.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/17.rom_ctrl_corrupt_sig_fatal_chk.4069153749
Short name T13
Test name
Test status
Simulation time 23499646162 ps
CPU time 115.95 seconds
Started Mar 03 02:32:02 PM PST 24
Finished Mar 03 02:33:58 PM PST 24
Peak memory 224632 kb
Host smart-a0112d81-ef77-4d5a-8196-1f5b8f54f65c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4069153749 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_
corrupt_sig_fatal_chk.4069153749
Directory /workspace/17.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/17.rom_ctrl_kmac_err_chk.2371335580
Short name T296
Test name
Test status
Simulation time 261287516 ps
CPU time 11.13 seconds
Started Mar 03 02:32:09 PM PST 24
Finished Mar 03 02:32:20 PM PST 24
Peak memory 211348 kb
Host smart-c2eee440-530a-415c-b82b-d40895147d1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2371335580 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_kmac_err_chk.2371335580
Directory /workspace/17.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/17.rom_ctrl_max_throughput_chk.1894968006
Short name T267
Test name
Test status
Simulation time 8564565216 ps
CPU time 17.22 seconds
Started Mar 03 02:32:03 PM PST 24
Finished Mar 03 02:32:21 PM PST 24
Peak memory 210900 kb
Host smart-f1a4febb-c602-4ab9-b75f-26fd0e560bcd
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1894968006 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_max_throughput_chk.1894968006
Directory /workspace/17.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/17.rom_ctrl_smoke.937754470
Short name T299
Test name
Test status
Simulation time 19130023309 ps
CPU time 22.07 seconds
Started Mar 03 02:32:05 PM PST 24
Finished Mar 03 02:32:27 PM PST 24
Peak memory 219100 kb
Host smart-59d9aec2-0ec3-4d41-92d9-02201f45683f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=937754470 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_smoke.937754470
Directory /workspace/17.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/17.rom_ctrl_stress_all.3628492254
Short name T81
Test name
Test status
Simulation time 1819887081 ps
CPU time 30.07 seconds
Started Mar 03 02:32:03 PM PST 24
Finished Mar 03 02:32:33 PM PST 24
Peak memory 211588 kb
Host smart-7ed5772d-41e3-45e9-afae-9a7be75851fd
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3628492254 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 17.rom_ctrl_stress_all.3628492254
Directory /workspace/17.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/17.rom_ctrl_stress_all_with_rand_reset.2079908316
Short name T18
Test name
Test status
Simulation time 251894049433 ps
CPU time 877.82 seconds
Started Mar 03 02:32:11 PM PST 24
Finished Mar 03 02:46:49 PM PST 24
Peak memory 230108 kb
Host smart-d9cacc46-821c-46bd-94a4-4bf72bcfb8d4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2079908316 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_stress_all_with_rand_reset.2079908316
Directory /workspace/17.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/18.rom_ctrl_alert_test.129331998
Short name T212
Test name
Test status
Simulation time 171922184 ps
CPU time 4.44 seconds
Started Mar 03 02:32:13 PM PST 24
Finished Mar 03 02:32:18 PM PST 24
Peak memory 210928 kb
Host smart-213f3b25-e79e-450c-97e5-192eb081b3d2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=129331998 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_alert_test.129331998
Directory /workspace/18.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/18.rom_ctrl_corrupt_sig_fatal_chk.3110736913
Short name T313
Test name
Test status
Simulation time 222889734188 ps
CPU time 239.77 seconds
Started Mar 03 02:32:11 PM PST 24
Finished Mar 03 02:36:11 PM PST 24
Peak memory 241144 kb
Host smart-2a63b1e1-1955-450e-ba55-924e43ac9bcd
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3110736913 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_
corrupt_sig_fatal_chk.3110736913
Directory /workspace/18.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/18.rom_ctrl_kmac_err_chk.1496150448
Short name T186
Test name
Test status
Simulation time 681843984 ps
CPU time 13.7 seconds
Started Mar 03 02:32:12 PM PST 24
Finished Mar 03 02:32:25 PM PST 24
Peak memory 211476 kb
Host smart-bea0d00a-6811-441b-82f7-958241f55239
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1496150448 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_kmac_err_chk.1496150448
Directory /workspace/18.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/18.rom_ctrl_max_throughput_chk.1592286207
Short name T200
Test name
Test status
Simulation time 373404931 ps
CPU time 5.47 seconds
Started Mar 03 02:32:14 PM PST 24
Finished Mar 03 02:32:19 PM PST 24
Peak memory 210712 kb
Host smart-8935fa19-97a2-4516-943b-c7599e9640a4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1592286207 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_max_throughput_chk.1592286207
Directory /workspace/18.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/18.rom_ctrl_smoke.1925942165
Short name T276
Test name
Test status
Simulation time 16946096575 ps
CPU time 35.14 seconds
Started Mar 03 02:32:12 PM PST 24
Finished Mar 03 02:32:48 PM PST 24
Peak memory 212952 kb
Host smart-867a4e77-e75c-4c7b-973c-487acec0cc80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1925942165 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_smoke.1925942165
Directory /workspace/18.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/18.rom_ctrl_stress_all.2090392056
Short name T160
Test name
Test status
Simulation time 15217737221 ps
CPU time 69.73 seconds
Started Mar 03 02:32:12 PM PST 24
Finished Mar 03 02:33:21 PM PST 24
Peak memory 215920 kb
Host smart-b9c59a3d-463e-44fb-964c-e6b2db204034
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2090392056 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 18.rom_ctrl_stress_all.2090392056
Directory /workspace/18.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/19.rom_ctrl_alert_test.3420626710
Short name T158
Test name
Test status
Simulation time 1680305006 ps
CPU time 13.74 seconds
Started Mar 03 02:32:19 PM PST 24
Finished Mar 03 02:32:33 PM PST 24
Peak memory 210872 kb
Host smart-a4450c86-f22a-4e24-832e-952d113d084c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3420626710 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_alert_test.3420626710
Directory /workspace/19.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/19.rom_ctrl_corrupt_sig_fatal_chk.3816545986
Short name T118
Test name
Test status
Simulation time 44480838695 ps
CPU time 408.38 seconds
Started Mar 03 02:32:18 PM PST 24
Finished Mar 03 02:39:06 PM PST 24
Peak memory 228244 kb
Host smart-c6ce04c4-c29a-43bf-a969-5b2f9962c297
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3816545986 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_
corrupt_sig_fatal_chk.3816545986
Directory /workspace/19.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/19.rom_ctrl_kmac_err_chk.1948317283
Short name T323
Test name
Test status
Simulation time 2311854563 ps
CPU time 14.01 seconds
Started Mar 03 02:32:19 PM PST 24
Finished Mar 03 02:32:33 PM PST 24
Peak memory 211416 kb
Host smart-12789b12-1d77-4b69-b6ca-93e4bac60d15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1948317283 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_kmac_err_chk.1948317283
Directory /workspace/19.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/19.rom_ctrl_max_throughput_chk.4066662718
Short name T234
Test name
Test status
Simulation time 1860440713 ps
CPU time 15.98 seconds
Started Mar 03 02:32:09 PM PST 24
Finished Mar 03 02:32:26 PM PST 24
Peak memory 210772 kb
Host smart-af4f2b6c-a9b3-49b3-b2e5-a8adc483f10f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4066662718 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_max_throughput_chk.4066662718
Directory /workspace/19.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/19.rom_ctrl_smoke.3833701134
Short name T350
Test name
Test status
Simulation time 947106848 ps
CPU time 15.19 seconds
Started Mar 03 02:32:12 PM PST 24
Finished Mar 03 02:32:27 PM PST 24
Peak memory 212208 kb
Host smart-8b16dab0-0fa6-478d-8ab2-6eb73431d888
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3833701134 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_smoke.3833701134
Directory /workspace/19.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/19.rom_ctrl_stress_all.3317444368
Short name T146
Test name
Test status
Simulation time 1425998893 ps
CPU time 13.98 seconds
Started Mar 03 02:32:11 PM PST 24
Finished Mar 03 02:32:25 PM PST 24
Peak memory 211112 kb
Host smart-4c14e0a6-1a2f-4740-99d7-8a726a4280bb
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3317444368 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 19.rom_ctrl_stress_all.3317444368
Directory /workspace/19.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/2.rom_ctrl_alert_test.1176832598
Short name T194
Test name
Test status
Simulation time 7033963425 ps
CPU time 15.57 seconds
Started Mar 03 02:31:29 PM PST 24
Finished Mar 03 02:31:45 PM PST 24
Peak memory 210984 kb
Host smart-355e9d95-ccb9-4c57-9f83-64e313aed04c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1176832598 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_alert_test.1176832598
Directory /workspace/2.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/2.rom_ctrl_corrupt_sig_fatal_chk.1712734049
Short name T171
Test name
Test status
Simulation time 2203486351 ps
CPU time 137.14 seconds
Started Mar 03 02:31:21 PM PST 24
Finished Mar 03 02:33:38 PM PST 24
Peak memory 236176 kb
Host smart-2caeffa4-642a-42da-a90c-bc59abedb277
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1712734049 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_c
orrupt_sig_fatal_chk.1712734049
Directory /workspace/2.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/2.rom_ctrl_kmac_err_chk.2538154683
Short name T154
Test name
Test status
Simulation time 1643253161 ps
CPU time 19.41 seconds
Started Mar 03 02:31:21 PM PST 24
Finished Mar 03 02:31:41 PM PST 24
Peak memory 211412 kb
Host smart-e69f6e8d-952f-4bf5-bb2c-d5aec70bb342
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2538154683 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_kmac_err_chk.2538154683
Directory /workspace/2.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/2.rom_ctrl_max_throughput_chk.1369985447
Short name T169
Test name
Test status
Simulation time 316245112 ps
CPU time 7.67 seconds
Started Mar 03 02:31:20 PM PST 24
Finished Mar 03 02:31:28 PM PST 24
Peak memory 210812 kb
Host smart-659726ed-68d9-4baf-9244-b657020b6e84
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1369985447 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_max_throughput_chk.1369985447
Directory /workspace/2.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/2.rom_ctrl_sec_cm.3614314387
Short name T32
Test name
Test status
Simulation time 3227748880 ps
CPU time 60.84 seconds
Started Mar 03 02:31:27 PM PST 24
Finished Mar 03 02:32:28 PM PST 24
Peak memory 231852 kb
Host smart-5ccad85d-4b5b-4528-a222-bec89322328f
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3614314387 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_sec_cm.3614314387
Directory /workspace/2.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/2.rom_ctrl_smoke.3635612762
Short name T327
Test name
Test status
Simulation time 3683502912 ps
CPU time 32.86 seconds
Started Mar 03 02:31:20 PM PST 24
Finished Mar 03 02:31:53 PM PST 24
Peak memory 213180 kb
Host smart-8dc26dee-0912-47cb-b1f1-ba0725072996
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3635612762 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_smoke.3635612762
Directory /workspace/2.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/2.rom_ctrl_stress_all.1094539173
Short name T59
Test name
Test status
Simulation time 13541315482 ps
CPU time 57.14 seconds
Started Mar 03 02:31:19 PM PST 24
Finished Mar 03 02:32:16 PM PST 24
Peak memory 219096 kb
Host smart-2de0d73a-7535-4d8a-b79f-e7ec56add740
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1094539173 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 2.rom_ctrl_stress_all.1094539173
Directory /workspace/2.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/20.rom_ctrl_alert_test.2430458725
Short name T246
Test name
Test status
Simulation time 1184992003 ps
CPU time 11.8 seconds
Started Mar 03 02:32:21 PM PST 24
Finished Mar 03 02:32:33 PM PST 24
Peak memory 210920 kb
Host smart-81fb60e4-e5f4-4aad-88be-35a0cac2d6cb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2430458725 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_alert_test.2430458725
Directory /workspace/20.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/20.rom_ctrl_corrupt_sig_fatal_chk.4059885731
Short name T45
Test name
Test status
Simulation time 3780560884 ps
CPU time 108.11 seconds
Started Mar 03 02:32:18 PM PST 24
Finished Mar 03 02:34:06 PM PST 24
Peak memory 228272 kb
Host smart-894e8a3a-59b6-4831-8ca3-ca1ed07b915a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4059885731 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_
corrupt_sig_fatal_chk.4059885731
Directory /workspace/20.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/20.rom_ctrl_kmac_err_chk.2086000088
Short name T147
Test name
Test status
Simulation time 11307131077 ps
CPU time 18.64 seconds
Started Mar 03 02:32:20 PM PST 24
Finished Mar 03 02:32:38 PM PST 24
Peak memory 212472 kb
Host smart-c3fffa9b-c605-4b8c-92a1-625a30be3cd4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2086000088 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_kmac_err_chk.2086000088
Directory /workspace/20.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/20.rom_ctrl_max_throughput_chk.3374146440
Short name T354
Test name
Test status
Simulation time 1058565973 ps
CPU time 9.61 seconds
Started Mar 03 02:32:19 PM PST 24
Finished Mar 03 02:32:28 PM PST 24
Peak memory 210804 kb
Host smart-1496e6f5-df0b-44b1-affe-ce4560e34a0f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3374146440 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_max_throughput_chk.3374146440
Directory /workspace/20.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/20.rom_ctrl_smoke.568316482
Short name T41
Test name
Test status
Simulation time 7987705712 ps
CPU time 33.62 seconds
Started Mar 03 02:32:20 PM PST 24
Finished Mar 03 02:32:53 PM PST 24
Peak memory 213088 kb
Host smart-e973c6f1-95b4-40ab-83ba-1a1bd405cf39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=568316482 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_smoke.568316482
Directory /workspace/20.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/20.rom_ctrl_stress_all.3553668460
Short name T223
Test name
Test status
Simulation time 1603819972 ps
CPU time 9.44 seconds
Started Mar 03 02:32:19 PM PST 24
Finished Mar 03 02:32:28 PM PST 24
Peak memory 210768 kb
Host smart-a25664cb-b4e9-4ae5-96ac-c94d2f6d8a63
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3553668460 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 20.rom_ctrl_stress_all.3553668460
Directory /workspace/20.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/20.rom_ctrl_stress_all_with_rand_reset.722712571
Short name T55
Test name
Test status
Simulation time 57280030385 ps
CPU time 775.44 seconds
Started Mar 03 02:32:20 PM PST 24
Finished Mar 03 02:45:15 PM PST 24
Peak memory 228908 kb
Host smart-9afb7507-93de-4916-95a8-a8cce28dc6a1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=722712571 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_stress_all_with_rand_reset.722712571
Directory /workspace/20.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/21.rom_ctrl_alert_test.3439460692
Short name T360
Test name
Test status
Simulation time 9306419430 ps
CPU time 15.71 seconds
Started Mar 03 02:32:18 PM PST 24
Finished Mar 03 02:32:33 PM PST 24
Peak memory 210916 kb
Host smart-f70dbe1f-0aba-41d3-9ad7-51ace9ea01f3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3439460692 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_alert_test.3439460692
Directory /workspace/21.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/21.rom_ctrl_corrupt_sig_fatal_chk.4276721730
Short name T197
Test name
Test status
Simulation time 62364783732 ps
CPU time 306.81 seconds
Started Mar 03 02:32:17 PM PST 24
Finished Mar 03 02:37:24 PM PST 24
Peak memory 212888 kb
Host smart-a18de3c6-6080-44b4-9a98-afabaaa1ca38
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4276721730 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_
corrupt_sig_fatal_chk.4276721730
Directory /workspace/21.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/21.rom_ctrl_kmac_err_chk.3510856641
Short name T333
Test name
Test status
Simulation time 1438685006 ps
CPU time 18.46 seconds
Started Mar 03 02:32:20 PM PST 24
Finished Mar 03 02:32:38 PM PST 24
Peak memory 211284 kb
Host smart-aca3046f-9149-46dc-9055-638842d9fff3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3510856641 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_kmac_err_chk.3510856641
Directory /workspace/21.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/21.rom_ctrl_max_throughput_chk.3880256976
Short name T242
Test name
Test status
Simulation time 4075808003 ps
CPU time 16.96 seconds
Started Mar 03 02:32:19 PM PST 24
Finished Mar 03 02:32:36 PM PST 24
Peak memory 210904 kb
Host smart-1a1de7ea-1a18-4e81-b78b-3158e003a187
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3880256976 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_max_throughput_chk.3880256976
Directory /workspace/21.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/21.rom_ctrl_smoke.1501913067
Short name T320
Test name
Test status
Simulation time 5769970756 ps
CPU time 30.61 seconds
Started Mar 03 02:32:18 PM PST 24
Finished Mar 03 02:32:49 PM PST 24
Peak memory 213284 kb
Host smart-0fe1d79a-e956-4aff-a69e-ca5ef2ce35c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1501913067 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_smoke.1501913067
Directory /workspace/21.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/22.rom_ctrl_alert_test.418972047
Short name T62
Test name
Test status
Simulation time 85644397 ps
CPU time 4.38 seconds
Started Mar 03 02:32:39 PM PST 24
Finished Mar 03 02:32:44 PM PST 24
Peak memory 210952 kb
Host smart-48a70224-46a2-4ae6-8dc2-7c89546c3ea9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=418972047 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_alert_test.418972047
Directory /workspace/22.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/22.rom_ctrl_corrupt_sig_fatal_chk.4082038478
Short name T263
Test name
Test status
Simulation time 44770565772 ps
CPU time 440.89 seconds
Started Mar 03 02:32:18 PM PST 24
Finished Mar 03 02:39:39 PM PST 24
Peak memory 219424 kb
Host smart-84cd3134-1d02-4437-a537-fdf424f3f6dc
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4082038478 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_
corrupt_sig_fatal_chk.4082038478
Directory /workspace/22.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/22.rom_ctrl_kmac_err_chk.3006013633
Short name T293
Test name
Test status
Simulation time 5920037773 ps
CPU time 18.91 seconds
Started Mar 03 02:32:39 PM PST 24
Finished Mar 03 02:32:58 PM PST 24
Peak memory 211660 kb
Host smart-c4c9194b-11ac-4d59-99a8-5a2f871b814b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3006013633 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_kmac_err_chk.3006013633
Directory /workspace/22.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/22.rom_ctrl_max_throughput_chk.287518581
Short name T198
Test name
Test status
Simulation time 16946077823 ps
CPU time 12.99 seconds
Started Mar 03 02:32:19 PM PST 24
Finished Mar 03 02:32:32 PM PST 24
Peak memory 210840 kb
Host smart-98e4ed1e-0357-4bc3-ad59-9e55db30c766
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=287518581 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_max_throughput_chk.287518581
Directory /workspace/22.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/22.rom_ctrl_smoke.628191219
Short name T277
Test name
Test status
Simulation time 7429374491 ps
CPU time 31.67 seconds
Started Mar 03 02:32:18 PM PST 24
Finished Mar 03 02:32:50 PM PST 24
Peak memory 214156 kb
Host smart-9e6eb145-251a-464c-a0f7-1d146abfdf96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=628191219 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_smoke.628191219
Directory /workspace/22.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/22.rom_ctrl_stress_all.4205943599
Short name T1
Test name
Test status
Simulation time 6672804194 ps
CPU time 33.77 seconds
Started Mar 03 02:32:18 PM PST 24
Finished Mar 03 02:32:52 PM PST 24
Peak memory 219112 kb
Host smart-5f8d8314-03de-40c6-91b5-c0ef11eb0f7c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4205943599 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 22.rom_ctrl_stress_all.4205943599
Directory /workspace/22.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/22.rom_ctrl_stress_all_with_rand_reset.3163065521
Short name T51
Test name
Test status
Simulation time 84631413848 ps
CPU time 775.28 seconds
Started Mar 03 02:32:24 PM PST 24
Finished Mar 03 02:45:19 PM PST 24
Peak memory 235520 kb
Host smart-dea894dd-db8c-4e26-8078-623804ce5de1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3163065521 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_stress_all_with_rand_reset.3163065521
Directory /workspace/22.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/23.rom_ctrl_alert_test.3102696214
Short name T336
Test name
Test status
Simulation time 902826823 ps
CPU time 10.03 seconds
Started Mar 03 02:32:28 PM PST 24
Finished Mar 03 02:32:38 PM PST 24
Peak memory 211156 kb
Host smart-4e858358-6e05-4a5f-b6e0-5e8876b9d95d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3102696214 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_alert_test.3102696214
Directory /workspace/23.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/23.rom_ctrl_corrupt_sig_fatal_chk.83423646
Short name T281
Test name
Test status
Simulation time 419641020525 ps
CPU time 242.39 seconds
Started Mar 03 02:32:28 PM PST 24
Finished Mar 03 02:36:31 PM PST 24
Peak memory 237444 kb
Host smart-baff2e2d-7304-4598-9e1e-a3aa8744050f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=83423646 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_
sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_co
rrupt_sig_fatal_chk.83423646
Directory /workspace/23.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/23.rom_ctrl_kmac_err_chk.28775656
Short name T185
Test name
Test status
Simulation time 168167173 ps
CPU time 9.56 seconds
Started Mar 03 02:32:36 PM PST 24
Finished Mar 03 02:32:46 PM PST 24
Peak memory 211428 kb
Host smart-08eafcc7-1258-4a0b-b61f-083c2958290a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=28775656 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_kmac_err_chk.28775656
Directory /workspace/23.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/23.rom_ctrl_max_throughput_chk.1766399918
Short name T341
Test name
Test status
Simulation time 195560590 ps
CPU time 5.88 seconds
Started Mar 03 02:32:24 PM PST 24
Finished Mar 03 02:32:30 PM PST 24
Peak memory 210824 kb
Host smart-0a6847da-409d-42ed-ab5b-e8364efc6ef7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1766399918 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_max_throughput_chk.1766399918
Directory /workspace/23.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/23.rom_ctrl_smoke.4279582027
Short name T148
Test name
Test status
Simulation time 6892853507 ps
CPU time 21.49 seconds
Started Mar 03 02:32:24 PM PST 24
Finished Mar 03 02:32:46 PM PST 24
Peak memory 213964 kb
Host smart-d6fe99cf-184c-4217-9c20-93593a6ff243
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4279582027 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_smoke.4279582027
Directory /workspace/23.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/23.rom_ctrl_stress_all.3394728346
Short name T155
Test name
Test status
Simulation time 8604653389 ps
CPU time 39.47 seconds
Started Mar 03 02:32:24 PM PST 24
Finished Mar 03 02:33:03 PM PST 24
Peak memory 215616 kb
Host smart-b5c1696e-d2f9-463c-9e8e-d49102b372b2
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3394728346 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 23.rom_ctrl_stress_all.3394728346
Directory /workspace/23.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/23.rom_ctrl_stress_all_with_rand_reset.317157244
Short name T317
Test name
Test status
Simulation time 76657954673 ps
CPU time 6287.15 seconds
Started Mar 03 02:32:25 PM PST 24
Finished Mar 03 04:17:13 PM PST 24
Peak memory 238344 kb
Host smart-99b06cb6-147c-498c-a960-62d73874dc89
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=317157244 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_stress_all_with_rand_reset.317157244
Directory /workspace/23.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/24.rom_ctrl_alert_test.2866884091
Short name T21
Test name
Test status
Simulation time 596576760 ps
CPU time 8.13 seconds
Started Mar 03 02:32:39 PM PST 24
Finished Mar 03 02:32:47 PM PST 24
Peak memory 210924 kb
Host smart-bc34a9e5-eb6e-41d8-ae7a-7ef5ff61d979
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2866884091 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_alert_test.2866884091
Directory /workspace/24.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/24.rom_ctrl_corrupt_sig_fatal_chk.1263775782
Short name T302
Test name
Test status
Simulation time 7494273760 ps
CPU time 182.4 seconds
Started Mar 03 02:32:25 PM PST 24
Finished Mar 03 02:35:28 PM PST 24
Peak memory 236772 kb
Host smart-02df03a4-4254-418c-9e4a-84ac2511c0a4
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1263775782 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_
corrupt_sig_fatal_chk.1263775782
Directory /workspace/24.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/24.rom_ctrl_kmac_err_chk.2255430432
Short name T122
Test name
Test status
Simulation time 3944419081 ps
CPU time 32.69 seconds
Started Mar 03 02:32:24 PM PST 24
Finished Mar 03 02:32:57 PM PST 24
Peak memory 211492 kb
Host smart-86710476-f425-4cc8-a287-ce9e7cdd5ff2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2255430432 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_kmac_err_chk.2255430432
Directory /workspace/24.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/24.rom_ctrl_max_throughput_chk.2176403253
Short name T227
Test name
Test status
Simulation time 349395440 ps
CPU time 5.43 seconds
Started Mar 03 02:32:23 PM PST 24
Finished Mar 03 02:32:29 PM PST 24
Peak memory 210768 kb
Host smart-3db44f1a-4d26-4069-8f38-4ac0fd5c5821
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2176403253 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_max_throughput_chk.2176403253
Directory /workspace/24.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/24.rom_ctrl_smoke.1749987791
Short name T335
Test name
Test status
Simulation time 741161170 ps
CPU time 9.8 seconds
Started Mar 03 02:32:25 PM PST 24
Finished Mar 03 02:32:34 PM PST 24
Peak memory 213336 kb
Host smart-91c7c630-1592-400d-844a-d629115ee1b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1749987791 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_smoke.1749987791
Directory /workspace/24.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/24.rom_ctrl_stress_all.1892787884
Short name T138
Test name
Test status
Simulation time 6666079041 ps
CPU time 44.37 seconds
Started Mar 03 02:32:39 PM PST 24
Finished Mar 03 02:33:24 PM PST 24
Peak memory 213780 kb
Host smart-fa532db0-4437-4879-b8a0-37a70551ce2b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1892787884 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 24.rom_ctrl_stress_all.1892787884
Directory /workspace/24.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/25.rom_ctrl_corrupt_sig_fatal_chk.1945652247
Short name T29
Test name
Test status
Simulation time 2329522287 ps
CPU time 99.57 seconds
Started Mar 03 02:32:28 PM PST 24
Finished Mar 03 02:34:08 PM PST 24
Peak memory 212280 kb
Host smart-13dcaa05-c7ac-470e-90b9-73600fb6acd2
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1945652247 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_
corrupt_sig_fatal_chk.1945652247
Directory /workspace/25.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/25.rom_ctrl_kmac_err_chk.788787046
Short name T312
Test name
Test status
Simulation time 4256287252 ps
CPU time 36.57 seconds
Started Mar 03 02:32:24 PM PST 24
Finished Mar 03 02:33:00 PM PST 24
Peak memory 211480 kb
Host smart-92b66158-2402-4d71-a5c9-0047cb4e1180
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=788787046 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_kmac_err_chk.788787046
Directory /workspace/25.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/25.rom_ctrl_max_throughput_chk.1405143800
Short name T331
Test name
Test status
Simulation time 1265015928 ps
CPU time 9.5 seconds
Started Mar 03 02:32:28 PM PST 24
Finished Mar 03 02:32:37 PM PST 24
Peak memory 210824 kb
Host smart-9c781a85-4549-4fc5-b6ae-34aad36cd12e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1405143800 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_max_throughput_chk.1405143800
Directory /workspace/25.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/25.rom_ctrl_smoke.357794629
Short name T359
Test name
Test status
Simulation time 757216086 ps
CPU time 10.25 seconds
Started Mar 03 02:32:25 PM PST 24
Finished Mar 03 02:32:36 PM PST 24
Peak memory 212992 kb
Host smart-d0f27f8e-aee4-4610-8ec1-fa79eac3f093
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=357794629 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_smoke.357794629
Directory /workspace/25.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/25.rom_ctrl_stress_all.725359320
Short name T291
Test name
Test status
Simulation time 2564663110 ps
CPU time 25.93 seconds
Started Mar 03 02:32:26 PM PST 24
Finished Mar 03 02:32:52 PM PST 24
Peak memory 219136 kb
Host smart-159705b7-feb0-4bdd-94f4-e5caf3e33e9f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=725359320 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 25.rom_ctrl_stress_all.725359320
Directory /workspace/25.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/26.rom_ctrl_alert_test.623988868
Short name T310
Test name
Test status
Simulation time 1603738052 ps
CPU time 6.3 seconds
Started Mar 03 02:32:32 PM PST 24
Finished Mar 03 02:32:39 PM PST 24
Peak memory 210920 kb
Host smart-09ed2753-b1f0-45d3-9740-072379900ecb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=623988868 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_alert_test.623988868
Directory /workspace/26.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/26.rom_ctrl_corrupt_sig_fatal_chk.3841961622
Short name T315
Test name
Test status
Simulation time 31399342034 ps
CPU time 264.91 seconds
Started Mar 03 02:32:31 PM PST 24
Finished Mar 03 02:36:56 PM PST 24
Peak memory 220064 kb
Host smart-ca67d84f-5e7f-4b81-9a9a-a38417c3a2de
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3841961622 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_
corrupt_sig_fatal_chk.3841961622
Directory /workspace/26.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/26.rom_ctrl_kmac_err_chk.2720938772
Short name T162
Test name
Test status
Simulation time 12021186832 ps
CPU time 21.75 seconds
Started Mar 03 02:32:30 PM PST 24
Finished Mar 03 02:32:52 PM PST 24
Peak memory 212420 kb
Host smart-d9977a17-c90d-4892-80ec-6822e6da270f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2720938772 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_kmac_err_chk.2720938772
Directory /workspace/26.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/26.rom_ctrl_max_throughput_chk.2465303912
Short name T270
Test name
Test status
Simulation time 807068681 ps
CPU time 10.38 seconds
Started Mar 03 02:32:24 PM PST 24
Finished Mar 03 02:32:34 PM PST 24
Peak memory 210836 kb
Host smart-2950ab7e-623c-4fcd-9ae9-f604948cfb83
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2465303912 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_max_throughput_chk.2465303912
Directory /workspace/26.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/26.rom_ctrl_smoke.1312726486
Short name T262
Test name
Test status
Simulation time 16145909537 ps
CPU time 37.66 seconds
Started Mar 03 02:32:28 PM PST 24
Finished Mar 03 02:33:05 PM PST 24
Peak memory 212956 kb
Host smart-f7e14830-5e98-4b7b-b683-3e2300c3377c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1312726486 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_smoke.1312726486
Directory /workspace/26.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/26.rom_ctrl_stress_all.3491280871
Short name T189
Test name
Test status
Simulation time 21742846803 ps
CPU time 50.34 seconds
Started Mar 03 02:32:28 PM PST 24
Finished Mar 03 02:33:19 PM PST 24
Peak memory 216704 kb
Host smart-6855865d-1a81-499e-954d-0e3ad45e66a2
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3491280871 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 26.rom_ctrl_stress_all.3491280871
Directory /workspace/26.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/27.rom_ctrl_alert_test.2993739867
Short name T129
Test name
Test status
Simulation time 171367632 ps
CPU time 4.23 seconds
Started Mar 03 02:32:33 PM PST 24
Finished Mar 03 02:32:37 PM PST 24
Peak memory 210924 kb
Host smart-07a9dd31-1aec-40e7-9fa5-4a911607f1f7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2993739867 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_alert_test.2993739867
Directory /workspace/27.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/27.rom_ctrl_corrupt_sig_fatal_chk.3131873101
Short name T151
Test name
Test status
Simulation time 41702257926 ps
CPU time 318 seconds
Started Mar 03 02:32:39 PM PST 24
Finished Mar 03 02:37:57 PM PST 24
Peak memory 211528 kb
Host smart-2eee85d4-a3b5-4a40-a359-010456034933
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3131873101 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_
corrupt_sig_fatal_chk.3131873101
Directory /workspace/27.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/27.rom_ctrl_kmac_err_chk.3260005680
Short name T230
Test name
Test status
Simulation time 9806619346 ps
CPU time 24.83 seconds
Started Mar 03 02:32:31 PM PST 24
Finished Mar 03 02:32:56 PM PST 24
Peak memory 211908 kb
Host smart-95192e2f-d61f-4a56-bb42-802004fe25b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3260005680 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_kmac_err_chk.3260005680
Directory /workspace/27.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/27.rom_ctrl_max_throughput_chk.2078817783
Short name T173
Test name
Test status
Simulation time 752643528 ps
CPU time 9.63 seconds
Started Mar 03 02:32:30 PM PST 24
Finished Mar 03 02:32:40 PM PST 24
Peak memory 210744 kb
Host smart-3ddbce7b-6b30-4733-b660-b998f1374eda
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2078817783 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_max_throughput_chk.2078817783
Directory /workspace/27.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/27.rom_ctrl_smoke.3621643672
Short name T233
Test name
Test status
Simulation time 14716967632 ps
CPU time 31.11 seconds
Started Mar 03 02:32:30 PM PST 24
Finished Mar 03 02:33:01 PM PST 24
Peak memory 213632 kb
Host smart-e3482067-e39a-437d-84b1-09851dd5fe3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3621643672 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_smoke.3621643672
Directory /workspace/27.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/27.rom_ctrl_stress_all.4288537198
Short name T75
Test name
Test status
Simulation time 24137106600 ps
CPU time 107.27 seconds
Started Mar 03 02:32:33 PM PST 24
Finished Mar 03 02:34:21 PM PST 24
Peak memory 219072 kb
Host smart-e1bc3bfc-0447-4538-9656-85e967101ba4
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4288537198 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 27.rom_ctrl_stress_all.4288537198
Directory /workspace/27.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/28.rom_ctrl_alert_test.1559048175
Short name T356
Test name
Test status
Simulation time 8352384692 ps
CPU time 17.89 seconds
Started Mar 03 02:32:30 PM PST 24
Finished Mar 03 02:32:48 PM PST 24
Peak memory 211004 kb
Host smart-b497482b-52a0-4c88-a0e3-b749dc4e8a80
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1559048175 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_alert_test.1559048175
Directory /workspace/28.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/28.rom_ctrl_corrupt_sig_fatal_chk.1773410243
Short name T157
Test name
Test status
Simulation time 88424622215 ps
CPU time 414.68 seconds
Started Mar 03 02:32:32 PM PST 24
Finished Mar 03 02:39:27 PM PST 24
Peak memory 236752 kb
Host smart-2c9aa1b4-de2d-4bde-aa26-02bd7ea2babb
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1773410243 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_
corrupt_sig_fatal_chk.1773410243
Directory /workspace/28.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/28.rom_ctrl_kmac_err_chk.3850673323
Short name T123
Test name
Test status
Simulation time 5195321590 ps
CPU time 35.95 seconds
Started Mar 03 02:32:30 PM PST 24
Finished Mar 03 02:33:06 PM PST 24
Peak memory 211652 kb
Host smart-45ebffbe-ba6f-4ab1-b6e7-8fad7a7ca1e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3850673323 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_kmac_err_chk.3850673323
Directory /workspace/28.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/28.rom_ctrl_max_throughput_chk.3334942928
Short name T355
Test name
Test status
Simulation time 1068660791 ps
CPU time 7.43 seconds
Started Mar 03 02:32:32 PM PST 24
Finished Mar 03 02:32:39 PM PST 24
Peak memory 210804 kb
Host smart-4e81131b-6007-4cce-b975-86c8453308c5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3334942928 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_max_throughput_chk.3334942928
Directory /workspace/28.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/28.rom_ctrl_smoke.4165072593
Short name T319
Test name
Test status
Simulation time 20798997123 ps
CPU time 35.58 seconds
Started Mar 03 02:32:30 PM PST 24
Finished Mar 03 02:33:06 PM PST 24
Peak memory 219136 kb
Host smart-152bd7c1-46fc-4194-b7f8-dda9fd3bb926
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4165072593 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_smoke.4165072593
Directory /workspace/28.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/28.rom_ctrl_stress_all.1473577396
Short name T145
Test name
Test status
Simulation time 8327404119 ps
CPU time 27.66 seconds
Started Mar 03 02:32:32 PM PST 24
Finished Mar 03 02:32:59 PM PST 24
Peak memory 212888 kb
Host smart-dd3fa0eb-f294-4923-9eec-448685115a19
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1473577396 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 28.rom_ctrl_stress_all.1473577396
Directory /workspace/28.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/29.rom_ctrl_alert_test.2788474423
Short name T250
Test name
Test status
Simulation time 2028968495 ps
CPU time 11.18 seconds
Started Mar 03 02:32:38 PM PST 24
Finished Mar 03 02:32:50 PM PST 24
Peak memory 210952 kb
Host smart-5e8e8b17-3e1b-4d15-98ee-a989ee75951c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2788474423 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_alert_test.2788474423
Directory /workspace/29.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/29.rom_ctrl_corrupt_sig_fatal_chk.3612629264
Short name T46
Test name
Test status
Simulation time 23243247042 ps
CPU time 257.66 seconds
Started Mar 03 02:32:33 PM PST 24
Finished Mar 03 02:36:50 PM PST 24
Peak memory 236344 kb
Host smart-9ef9f217-dad1-45e9-a4f6-8613ccf2655b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3612629264 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_
corrupt_sig_fatal_chk.3612629264
Directory /workspace/29.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/29.rom_ctrl_kmac_err_chk.3808559504
Short name T22
Test name
Test status
Simulation time 14864127221 ps
CPU time 23.61 seconds
Started Mar 03 02:32:38 PM PST 24
Finished Mar 03 02:33:01 PM PST 24
Peak memory 212176 kb
Host smart-25b76e17-536d-43e3-9279-9e0652022d1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3808559504 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_kmac_err_chk.3808559504
Directory /workspace/29.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/29.rom_ctrl_max_throughput_chk.3359806487
Short name T140
Test name
Test status
Simulation time 1335666292 ps
CPU time 12.44 seconds
Started Mar 03 02:32:31 PM PST 24
Finished Mar 03 02:32:43 PM PST 24
Peak memory 210728 kb
Host smart-a14b142b-0b3e-49b5-bd8f-e43331fc2a9a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3359806487 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_max_throughput_chk.3359806487
Directory /workspace/29.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/29.rom_ctrl_smoke.3548980117
Short name T33
Test name
Test status
Simulation time 1207384829 ps
CPU time 10.05 seconds
Started Mar 03 02:32:30 PM PST 24
Finished Mar 03 02:32:40 PM PST 24
Peak memory 213176 kb
Host smart-490038bb-7cd2-4042-af0b-823f1ed7d1f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3548980117 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_smoke.3548980117
Directory /workspace/29.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/29.rom_ctrl_stress_all.1051013433
Short name T285
Test name
Test status
Simulation time 24692801795 ps
CPU time 73.41 seconds
Started Mar 03 02:32:31 PM PST 24
Finished Mar 03 02:33:45 PM PST 24
Peak memory 216104 kb
Host smart-83f21f47-9785-4cd8-9a82-32ee423762ce
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1051013433 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 29.rom_ctrl_stress_all.1051013433
Directory /workspace/29.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/29.rom_ctrl_stress_all_with_rand_reset.563973885
Short name T54
Test name
Test status
Simulation time 16458325341 ps
CPU time 657.18 seconds
Started Mar 03 02:32:39 PM PST 24
Finished Mar 03 02:43:37 PM PST 24
Peak memory 227360 kb
Host smart-0eae7de8-cfde-4163-9991-55123006dcba
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=563973885 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_stress_all_with_rand_reset.563973885
Directory /workspace/29.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.rom_ctrl_alert_test.2168285609
Short name T259
Test name
Test status
Simulation time 2461582380 ps
CPU time 8.67 seconds
Started Mar 03 02:31:29 PM PST 24
Finished Mar 03 02:31:38 PM PST 24
Peak memory 211012 kb
Host smart-b51b3770-419a-41ab-bfc2-da7ba3df6b3b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2168285609 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_alert_test.2168285609
Directory /workspace/3.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/3.rom_ctrl_kmac_err_chk.3200298832
Short name T178
Test name
Test status
Simulation time 1069089173 ps
CPU time 16.98 seconds
Started Mar 03 02:31:27 PM PST 24
Finished Mar 03 02:31:44 PM PST 24
Peak memory 211348 kb
Host smart-2f118695-3b22-441c-b17c-44a2661f70ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3200298832 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_kmac_err_chk.3200298832
Directory /workspace/3.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/3.rom_ctrl_max_throughput_chk.4202846334
Short name T361
Test name
Test status
Simulation time 1446670498 ps
CPU time 13.66 seconds
Started Mar 03 02:31:30 PM PST 24
Finished Mar 03 02:31:44 PM PST 24
Peak memory 210816 kb
Host smart-f0ce9c2d-135b-4ff1-95a2-2ed45ff78096
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4202846334 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_max_throughput_chk.4202846334
Directory /workspace/3.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/3.rom_ctrl_sec_cm.2651888456
Short name T34
Test name
Test status
Simulation time 611273504 ps
CPU time 49.36 seconds
Started Mar 03 02:31:27 PM PST 24
Finished Mar 03 02:32:17 PM PST 24
Peak memory 230816 kb
Host smart-4b0a6496-78c5-4779-82bd-af4abeaa0ab6
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2651888456 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_sec_cm.2651888456
Directory /workspace/3.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/3.rom_ctrl_smoke.2635461876
Short name T177
Test name
Test status
Simulation time 4053035663 ps
CPU time 33.9 seconds
Started Mar 03 02:31:27 PM PST 24
Finished Mar 03 02:32:01 PM PST 24
Peak memory 213120 kb
Host smart-d006ef63-bbb8-4669-902a-193206747a85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2635461876 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_smoke.2635461876
Directory /workspace/3.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/3.rom_ctrl_stress_all.1767046904
Short name T78
Test name
Test status
Simulation time 1638387212 ps
CPU time 7.27 seconds
Started Mar 03 02:31:28 PM PST 24
Finished Mar 03 02:31:35 PM PST 24
Peak memory 210880 kb
Host smart-3e6251fc-ba91-458f-a7b5-8e281df24eb0
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1767046904 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 3.rom_ctrl_stress_all.1767046904
Directory /workspace/3.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/30.rom_ctrl_alert_test.426127116
Short name T311
Test name
Test status
Simulation time 1409142444 ps
CPU time 12.78 seconds
Started Mar 03 02:32:39 PM PST 24
Finished Mar 03 02:32:52 PM PST 24
Peak memory 210924 kb
Host smart-a444b7b2-b704-4cac-ad91-8f58dde2ec8b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=426127116 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_alert_test.426127116
Directory /workspace/30.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/30.rom_ctrl_corrupt_sig_fatal_chk.4217293601
Short name T9
Test name
Test status
Simulation time 46231557995 ps
CPU time 390.51 seconds
Started Mar 03 02:32:37 PM PST 24
Finished Mar 03 02:39:08 PM PST 24
Peak memory 224332 kb
Host smart-80660fe3-e4ab-4f13-96a6-7bc90a4ec64e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4217293601 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_
corrupt_sig_fatal_chk.4217293601
Directory /workspace/30.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/30.rom_ctrl_kmac_err_chk.3464024078
Short name T23
Test name
Test status
Simulation time 17427316551 ps
CPU time 24.97 seconds
Started Mar 03 02:32:37 PM PST 24
Finished Mar 03 02:33:02 PM PST 24
Peak memory 212320 kb
Host smart-d0f35c61-819c-45f0-ba40-8c1b3532bb42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3464024078 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_kmac_err_chk.3464024078
Directory /workspace/30.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/30.rom_ctrl_max_throughput_chk.3869059640
Short name T174
Test name
Test status
Simulation time 1470708493 ps
CPU time 13.81 seconds
Started Mar 03 02:32:38 PM PST 24
Finished Mar 03 02:32:53 PM PST 24
Peak memory 210800 kb
Host smart-001989c2-febb-4e84-b7e7-9b8424700f3d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3869059640 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_max_throughput_chk.3869059640
Directory /workspace/30.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/30.rom_ctrl_smoke.3566703575
Short name T219
Test name
Test status
Simulation time 1811642616 ps
CPU time 20.79 seconds
Started Mar 03 02:32:40 PM PST 24
Finished Mar 03 02:33:01 PM PST 24
Peak memory 212708 kb
Host smart-b5aed1e8-e182-4dea-9297-e6c6a38f5c9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3566703575 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_smoke.3566703575
Directory /workspace/30.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/30.rom_ctrl_stress_all.1076674411
Short name T132
Test name
Test status
Simulation time 5569277910 ps
CPU time 28 seconds
Started Mar 03 02:32:38 PM PST 24
Finished Mar 03 02:33:06 PM PST 24
Peak memory 219056 kb
Host smart-8aacdf2e-50a3-4a74-896a-c07f615ee90d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1076674411 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 30.rom_ctrl_stress_all.1076674411
Directory /workspace/30.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/30.rom_ctrl_stress_all_with_rand_reset.3750307227
Short name T351
Test name
Test status
Simulation time 122472340544 ps
CPU time 1162.84 seconds
Started Mar 03 02:32:39 PM PST 24
Finished Mar 03 02:52:03 PM PST 24
Peak memory 235576 kb
Host smart-270e914e-3214-4ca3-a91a-3751727e5853
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3750307227 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_stress_all_with_rand_reset.3750307227
Directory /workspace/30.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.rom_ctrl_alert_test.128377115
Short name T139
Test name
Test status
Simulation time 1169566840 ps
CPU time 11.47 seconds
Started Mar 03 02:32:45 PM PST 24
Finished Mar 03 02:32:57 PM PST 24
Peak memory 210860 kb
Host smart-fcd30ed0-8636-4712-927f-b39249bf1289
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=128377115 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_alert_test.128377115
Directory /workspace/31.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/31.rom_ctrl_corrupt_sig_fatal_chk.1426927503
Short name T25
Test name
Test status
Simulation time 6183168811 ps
CPU time 131.42 seconds
Started Mar 03 02:32:44 PM PST 24
Finished Mar 03 02:34:57 PM PST 24
Peak memory 237664 kb
Host smart-1bd3b425-7f6c-4db5-8d59-3c165c37dbaa
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1426927503 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_
corrupt_sig_fatal_chk.1426927503
Directory /workspace/31.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/31.rom_ctrl_kmac_err_chk.1705846149
Short name T42
Test name
Test status
Simulation time 22288067751 ps
CPU time 19.66 seconds
Started Mar 03 02:32:45 PM PST 24
Finished Mar 03 02:33:05 PM PST 24
Peak memory 211612 kb
Host smart-28de3c94-1d1c-4847-aedd-d2891d994d06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1705846149 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_kmac_err_chk.1705846149
Directory /workspace/31.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/31.rom_ctrl_max_throughput_chk.3545619243
Short name T273
Test name
Test status
Simulation time 6899659176 ps
CPU time 10.56 seconds
Started Mar 03 02:32:45 PM PST 24
Finished Mar 03 02:32:56 PM PST 24
Peak memory 210868 kb
Host smart-84e1aa4c-ba4f-4c59-a314-e779468a0efb
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3545619243 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_max_throughput_chk.3545619243
Directory /workspace/31.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/31.rom_ctrl_smoke.38413707
Short name T229
Test name
Test status
Simulation time 3970676113 ps
CPU time 22.08 seconds
Started Mar 03 02:32:40 PM PST 24
Finished Mar 03 02:33:02 PM PST 24
Peak memory 212700 kb
Host smart-c9c41525-3a37-4e3a-8d79-e762677b1e6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=38413707 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_smoke.38413707
Directory /workspace/31.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/31.rom_ctrl_stress_all.3941022043
Short name T308
Test name
Test status
Simulation time 528773067 ps
CPU time 26.4 seconds
Started Mar 03 02:32:46 PM PST 24
Finished Mar 03 02:33:12 PM PST 24
Peak memory 219068 kb
Host smart-bbf76d9b-ebbc-43bb-8808-3225d6891ec6
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3941022043 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 31.rom_ctrl_stress_all.3941022043
Directory /workspace/31.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/32.rom_ctrl_alert_test.4116250110
Short name T63
Test name
Test status
Simulation time 657489800 ps
CPU time 8.54 seconds
Started Mar 03 02:32:47 PM PST 24
Finished Mar 03 02:32:56 PM PST 24
Peak memory 210944 kb
Host smart-164e6413-f987-44e2-802f-3a82fbac10a4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4116250110 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_alert_test.4116250110
Directory /workspace/32.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/32.rom_ctrl_corrupt_sig_fatal_chk.3316392750
Short name T338
Test name
Test status
Simulation time 3657386436 ps
CPU time 107.11 seconds
Started Mar 03 02:32:45 PM PST 24
Finished Mar 03 02:34:32 PM PST 24
Peak memory 224872 kb
Host smart-5dee5f4c-15a9-4ef3-b52d-70925be45d13
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3316392750 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_
corrupt_sig_fatal_chk.3316392750
Directory /workspace/32.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/32.rom_ctrl_kmac_err_chk.3750824220
Short name T191
Test name
Test status
Simulation time 8173799990 ps
CPU time 32.54 seconds
Started Mar 03 02:32:46 PM PST 24
Finished Mar 03 02:33:19 PM PST 24
Peak memory 211988 kb
Host smart-40028d27-6dc3-4888-9630-5a37c0f38ed0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3750824220 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_kmac_err_chk.3750824220
Directory /workspace/32.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/32.rom_ctrl_max_throughput_chk.1156247198
Short name T278
Test name
Test status
Simulation time 5311089575 ps
CPU time 13.63 seconds
Started Mar 03 02:32:50 PM PST 24
Finished Mar 03 02:33:04 PM PST 24
Peak memory 210904 kb
Host smart-037aad92-26a9-4660-8567-41fe19a91fec
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1156247198 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_max_throughput_chk.1156247198
Directory /workspace/32.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/32.rom_ctrl_smoke.518789701
Short name T287
Test name
Test status
Simulation time 12961276941 ps
CPU time 39.1 seconds
Started Mar 03 02:32:46 PM PST 24
Finished Mar 03 02:33:25 PM PST 24
Peak memory 213976 kb
Host smart-0ceac69a-c754-406d-8e2b-dd255423415f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=518789701 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_smoke.518789701
Directory /workspace/32.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/32.rom_ctrl_stress_all.1798687052
Short name T92
Test name
Test status
Simulation time 646637365 ps
CPU time 34.08 seconds
Started Mar 03 02:32:48 PM PST 24
Finished Mar 03 02:33:22 PM PST 24
Peak memory 218948 kb
Host smart-55d278e3-5290-4443-9833-da34d38dd2c7
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1798687052 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 32.rom_ctrl_stress_all.1798687052
Directory /workspace/32.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/33.rom_ctrl_alert_test.3525743829
Short name T131
Test name
Test status
Simulation time 2356433590 ps
CPU time 12.98 seconds
Started Mar 03 02:32:54 PM PST 24
Finished Mar 03 02:33:07 PM PST 24
Peak memory 211016 kb
Host smart-b4f458b0-2ce3-4776-9248-cc3cadc431ba
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3525743829 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_alert_test.3525743829
Directory /workspace/33.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/33.rom_ctrl_corrupt_sig_fatal_chk.1582074704
Short name T266
Test name
Test status
Simulation time 52857036435 ps
CPU time 295.99 seconds
Started Mar 03 02:32:48 PM PST 24
Finished Mar 03 02:37:44 PM PST 24
Peak memory 212472 kb
Host smart-bdee950a-d60f-49c7-a813-e39054a58a77
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1582074704 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_
corrupt_sig_fatal_chk.1582074704
Directory /workspace/33.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/33.rom_ctrl_kmac_err_chk.3811154494
Short name T196
Test name
Test status
Simulation time 16401581769 ps
CPU time 33.64 seconds
Started Mar 03 02:32:48 PM PST 24
Finished Mar 03 02:33:22 PM PST 24
Peak memory 211708 kb
Host smart-778f6a74-9328-4387-98b3-93f31bc2ef8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3811154494 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_kmac_err_chk.3811154494
Directory /workspace/33.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/33.rom_ctrl_max_throughput_chk.3602354038
Short name T283
Test name
Test status
Simulation time 3607567779 ps
CPU time 16.35 seconds
Started Mar 03 02:32:48 PM PST 24
Finished Mar 03 02:33:04 PM PST 24
Peak memory 210900 kb
Host smart-4f4a1687-84ed-4cfe-82c5-b984930129be
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3602354038 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_max_throughput_chk.3602354038
Directory /workspace/33.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/33.rom_ctrl_smoke.2381385589
Short name T168
Test name
Test status
Simulation time 3561940272 ps
CPU time 21.08 seconds
Started Mar 03 02:32:44 PM PST 24
Finished Mar 03 02:33:06 PM PST 24
Peak memory 213088 kb
Host smart-0c5cfce9-0887-407c-868d-f186b5eecab6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2381385589 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_smoke.2381385589
Directory /workspace/33.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/33.rom_ctrl_stress_all.1733925501
Short name T190
Test name
Test status
Simulation time 5416440098 ps
CPU time 16.05 seconds
Started Mar 03 02:32:54 PM PST 24
Finished Mar 03 02:33:10 PM PST 24
Peak memory 210824 kb
Host smart-3d23e0f9-1103-43b4-8764-5c731f7405f3
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1733925501 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 33.rom_ctrl_stress_all.1733925501
Directory /workspace/33.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/34.rom_ctrl_alert_test.3054400498
Short name T217
Test name
Test status
Simulation time 423710281 ps
CPU time 7.19 seconds
Started Mar 03 02:32:52 PM PST 24
Finished Mar 03 02:33:00 PM PST 24
Peak memory 210960 kb
Host smart-87c091f9-d41b-4e4a-8f83-044c89d5e598
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3054400498 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_alert_test.3054400498
Directory /workspace/34.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/34.rom_ctrl_corrupt_sig_fatal_chk.726715356
Short name T48
Test name
Test status
Simulation time 8293369866 ps
CPU time 91.47 seconds
Started Mar 03 02:32:55 PM PST 24
Finished Mar 03 02:34:27 PM PST 24
Peak memory 228080 kb
Host smart-79fdc407-789f-4390-b659-6a38102f7d73
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=726715356 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_c
orrupt_sig_fatal_chk.726715356
Directory /workspace/34.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/34.rom_ctrl_kmac_err_chk.1575168743
Short name T265
Test name
Test status
Simulation time 2305567182 ps
CPU time 23.04 seconds
Started Mar 03 02:32:54 PM PST 24
Finished Mar 03 02:33:18 PM PST 24
Peak memory 211404 kb
Host smart-90707d9b-0e09-4bf7-bbc3-8c0b1f13d6fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1575168743 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_kmac_err_chk.1575168743
Directory /workspace/34.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/34.rom_ctrl_max_throughput_chk.2139967103
Short name T172
Test name
Test status
Simulation time 2049411476 ps
CPU time 16.96 seconds
Started Mar 03 02:32:51 PM PST 24
Finished Mar 03 02:33:08 PM PST 24
Peak memory 210796 kb
Host smart-d0226db7-7f20-435c-9227-705958d06c02
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2139967103 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_max_throughput_chk.2139967103
Directory /workspace/34.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/34.rom_ctrl_smoke.1417754085
Short name T150
Test name
Test status
Simulation time 6436859206 ps
CPU time 33.86 seconds
Started Mar 03 02:32:46 PM PST 24
Finished Mar 03 02:33:20 PM PST 24
Peak memory 214140 kb
Host smart-231579ae-25c0-4261-9cea-a8348ad02e9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1417754085 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_smoke.1417754085
Directory /workspace/34.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/34.rom_ctrl_stress_all.2598122823
Short name T249
Test name
Test status
Simulation time 5624645930 ps
CPU time 11.95 seconds
Started Mar 03 02:32:47 PM PST 24
Finished Mar 03 02:32:59 PM PST 24
Peak memory 210828 kb
Host smart-f2eb8c8d-844e-49ab-90e8-40d1f3ca6260
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2598122823 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 34.rom_ctrl_stress_all.2598122823
Directory /workspace/34.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/35.rom_ctrl_alert_test.3602366118
Short name T292
Test name
Test status
Simulation time 168152191 ps
CPU time 4.22 seconds
Started Mar 03 02:32:54 PM PST 24
Finished Mar 03 02:32:59 PM PST 24
Peak memory 210868 kb
Host smart-3f5da355-226e-4199-8653-0cdf5cdcb84a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3602366118 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_alert_test.3602366118
Directory /workspace/35.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/35.rom_ctrl_corrupt_sig_fatal_chk.4000488662
Short name T295
Test name
Test status
Simulation time 508674601925 ps
CPU time 485.26 seconds
Started Mar 03 02:32:54 PM PST 24
Finished Mar 03 02:41:00 PM PST 24
Peak memory 224552 kb
Host smart-e5e8dff3-bd1a-4b7e-9292-22f3600bc1f0
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4000488662 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_
corrupt_sig_fatal_chk.4000488662
Directory /workspace/35.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/35.rom_ctrl_kmac_err_chk.1641022053
Short name T220
Test name
Test status
Simulation time 5602128627 ps
CPU time 19.48 seconds
Started Mar 03 02:32:52 PM PST 24
Finished Mar 03 02:33:12 PM PST 24
Peak memory 211756 kb
Host smart-8fa30ad2-3c8c-478c-bb7c-2b01c757c0bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1641022053 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_kmac_err_chk.1641022053
Directory /workspace/35.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/35.rom_ctrl_max_throughput_chk.1265523870
Short name T5
Test name
Test status
Simulation time 4280874275 ps
CPU time 11.9 seconds
Started Mar 03 02:32:54 PM PST 24
Finished Mar 03 02:33:07 PM PST 24
Peak memory 210812 kb
Host smart-8a9dae2f-a79c-4a4a-a300-13e24d06a6ac
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1265523870 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_max_throughput_chk.1265523870
Directory /workspace/35.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/35.rom_ctrl_smoke.1529160132
Short name T153
Test name
Test status
Simulation time 22792035012 ps
CPU time 32.19 seconds
Started Mar 03 02:32:55 PM PST 24
Finished Mar 03 02:33:28 PM PST 24
Peak memory 213788 kb
Host smart-8787e2d8-5765-402f-badd-a10a4b368c99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1529160132 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_smoke.1529160132
Directory /workspace/35.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/35.rom_ctrl_stress_all.1221960195
Short name T149
Test name
Test status
Simulation time 1346234402 ps
CPU time 17.81 seconds
Started Mar 03 02:32:53 PM PST 24
Finished Mar 03 02:33:12 PM PST 24
Peak memory 210756 kb
Host smart-c9eb9fa6-7578-4eee-b95b-aae73cf24d59
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1221960195 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 35.rom_ctrl_stress_all.1221960195
Directory /workspace/35.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/36.rom_ctrl_alert_test.446390219
Short name T176
Test name
Test status
Simulation time 171758195 ps
CPU time 4.39 seconds
Started Mar 03 02:32:52 PM PST 24
Finished Mar 03 02:32:57 PM PST 24
Peak memory 210960 kb
Host smart-448a87db-efaf-4dcd-b317-97ce4490d65d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=446390219 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_alert_test.446390219
Directory /workspace/36.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/36.rom_ctrl_corrupt_sig_fatal_chk.196019568
Short name T274
Test name
Test status
Simulation time 249230942603 ps
CPU time 522.87 seconds
Started Mar 03 02:32:51 PM PST 24
Finished Mar 03 02:41:34 PM PST 24
Peak memory 229460 kb
Host smart-ec604b09-0715-4ef7-ba6b-cc8cfe3ffe36
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=196019568 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_c
orrupt_sig_fatal_chk.196019568
Directory /workspace/36.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/36.rom_ctrl_kmac_err_chk.2952493066
Short name T290
Test name
Test status
Simulation time 17037170923 ps
CPU time 33.16 seconds
Started Mar 03 02:32:53 PM PST 24
Finished Mar 03 02:33:27 PM PST 24
Peak memory 213308 kb
Host smart-1999f7db-e1f6-4f6f-bb5a-a7f3924af09f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2952493066 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_kmac_err_chk.2952493066
Directory /workspace/36.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/36.rom_ctrl_max_throughput_chk.1686254571
Short name T143
Test name
Test status
Simulation time 958339661 ps
CPU time 11.02 seconds
Started Mar 03 02:32:53 PM PST 24
Finished Mar 03 02:33:05 PM PST 24
Peak memory 210808 kb
Host smart-bff46ff5-45a0-4b8c-b7f3-25254e707d5a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1686254571 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_max_throughput_chk.1686254571
Directory /workspace/36.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/36.rom_ctrl_smoke.3031651476
Short name T286
Test name
Test status
Simulation time 580494000 ps
CPU time 9.99 seconds
Started Mar 03 02:32:52 PM PST 24
Finished Mar 03 02:33:03 PM PST 24
Peak memory 212576 kb
Host smart-f78d322d-2bcf-4391-8f6e-e770e197a0da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3031651476 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_smoke.3031651476
Directory /workspace/36.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/36.rom_ctrl_stress_all.1826290625
Short name T321
Test name
Test status
Simulation time 25563066662 ps
CPU time 52.23 seconds
Started Mar 03 02:32:54 PM PST 24
Finished Mar 03 02:33:47 PM PST 24
Peak memory 219136 kb
Host smart-04d1f32b-8961-4256-bff7-5355e939f8f3
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1826290625 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 36.rom_ctrl_stress_all.1826290625
Directory /workspace/36.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/37.rom_ctrl_alert_test.1834620129
Short name T316
Test name
Test status
Simulation time 1180742361 ps
CPU time 5.45 seconds
Started Mar 03 02:33:00 PM PST 24
Finished Mar 03 02:33:06 PM PST 24
Peak memory 210928 kb
Host smart-497fe077-6d83-4d6f-b62d-3ed9375dc6a9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1834620129 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_alert_test.1834620129
Directory /workspace/37.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/37.rom_ctrl_corrupt_sig_fatal_chk.2405035586
Short name T257
Test name
Test status
Simulation time 336947900933 ps
CPU time 522.54 seconds
Started Mar 03 02:33:02 PM PST 24
Finished Mar 03 02:41:45 PM PST 24
Peak memory 234480 kb
Host smart-1d71d990-ada2-4604-b83c-be9b6cfa02c7
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2405035586 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_
corrupt_sig_fatal_chk.2405035586
Directory /workspace/37.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/37.rom_ctrl_kmac_err_chk.864251944
Short name T125
Test name
Test status
Simulation time 2631265931 ps
CPU time 25.09 seconds
Started Mar 03 02:33:01 PM PST 24
Finished Mar 03 02:33:26 PM PST 24
Peak memory 211476 kb
Host smart-d15ed4fb-9bcd-400a-9f8a-3a9b734ec9a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=864251944 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_kmac_err_chk.864251944
Directory /workspace/37.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/37.rom_ctrl_max_throughput_chk.3251756834
Short name T254
Test name
Test status
Simulation time 867228199 ps
CPU time 10.65 seconds
Started Mar 03 02:33:00 PM PST 24
Finished Mar 03 02:33:10 PM PST 24
Peak memory 210736 kb
Host smart-2102e65e-5b1d-4642-a9d5-8a5fdc7af157
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3251756834 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_max_throughput_chk.3251756834
Directory /workspace/37.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/37.rom_ctrl_smoke.2195527153
Short name T115
Test name
Test status
Simulation time 4097038734 ps
CPU time 34.76 seconds
Started Mar 03 02:33:01 PM PST 24
Finished Mar 03 02:33:36 PM PST 24
Peak memory 212684 kb
Host smart-2a2ec8e8-94f5-4d18-85c8-622e21ac49ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2195527153 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_smoke.2195527153
Directory /workspace/37.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/37.rom_ctrl_stress_all.759995138
Short name T245
Test name
Test status
Simulation time 3123525563 ps
CPU time 16.94 seconds
Started Mar 03 02:33:01 PM PST 24
Finished Mar 03 02:33:18 PM PST 24
Peak memory 211840 kb
Host smart-faac98f5-7d78-404b-ac0c-dd52e16c0263
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=759995138 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 37.rom_ctrl_stress_all.759995138
Directory /workspace/37.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/38.rom_ctrl_alert_test.1651439682
Short name T268
Test name
Test status
Simulation time 1852125274 ps
CPU time 14.97 seconds
Started Mar 03 02:32:59 PM PST 24
Finished Mar 03 02:33:14 PM PST 24
Peak memory 210956 kb
Host smart-daf23dba-ea83-487c-86ac-658794ab7c6d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1651439682 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_alert_test.1651439682
Directory /workspace/38.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/38.rom_ctrl_corrupt_sig_fatal_chk.368054497
Short name T210
Test name
Test status
Simulation time 14879071782 ps
CPU time 131.35 seconds
Started Mar 03 02:33:00 PM PST 24
Finished Mar 03 02:35:12 PM PST 24
Peak memory 239592 kb
Host smart-78732063-9b23-4fc1-9a5e-1da6502c5fbe
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=368054497 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_c
orrupt_sig_fatal_chk.368054497
Directory /workspace/38.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/38.rom_ctrl_kmac_err_chk.2692726284
Short name T163
Test name
Test status
Simulation time 663755332 ps
CPU time 9.45 seconds
Started Mar 03 02:33:00 PM PST 24
Finished Mar 03 02:33:10 PM PST 24
Peak memory 211704 kb
Host smart-72c04bf6-b1ff-4fa4-acc4-03e17b78d6f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2692726284 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_kmac_err_chk.2692726284
Directory /workspace/38.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/38.rom_ctrl_max_throughput_chk.3257091607
Short name T37
Test name
Test status
Simulation time 6222981086 ps
CPU time 11.55 seconds
Started Mar 03 02:33:00 PM PST 24
Finished Mar 03 02:33:11 PM PST 24
Peak memory 210872 kb
Host smart-746dd79f-2b02-4eb6-a71f-9ca4572afd14
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3257091607 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_max_throughput_chk.3257091607
Directory /workspace/38.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/38.rom_ctrl_smoke.2181410336
Short name T76
Test name
Test status
Simulation time 2679094536 ps
CPU time 28.64 seconds
Started Mar 03 02:33:01 PM PST 24
Finished Mar 03 02:33:30 PM PST 24
Peak memory 213016 kb
Host smart-db8a27ad-a924-42df-9181-9583bffa2ad4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2181410336 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_smoke.2181410336
Directory /workspace/38.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/38.rom_ctrl_stress_all.2578502626
Short name T20
Test name
Test status
Simulation time 4849655218 ps
CPU time 35 seconds
Started Mar 03 02:32:59 PM PST 24
Finished Mar 03 02:33:34 PM PST 24
Peak memory 212788 kb
Host smart-3a9bb1e8-f0c2-48b2-84fe-2ffdc9531adb
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2578502626 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 38.rom_ctrl_stress_all.2578502626
Directory /workspace/38.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/39.rom_ctrl_alert_test.3600965753
Short name T38
Test name
Test status
Simulation time 88933978 ps
CPU time 4.32 seconds
Started Mar 03 02:33:01 PM PST 24
Finished Mar 03 02:33:06 PM PST 24
Peak memory 210948 kb
Host smart-610f2e46-4b8d-4bd6-9ae9-cdd83db19d1c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3600965753 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_alert_test.3600965753
Directory /workspace/39.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/39.rom_ctrl_corrupt_sig_fatal_chk.1010353050
Short name T237
Test name
Test status
Simulation time 231864012543 ps
CPU time 279.36 seconds
Started Mar 03 02:33:00 PM PST 24
Finished Mar 03 02:37:40 PM PST 24
Peak memory 213216 kb
Host smart-e29aedc7-9e0b-4346-9410-10944bceb44d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1010353050 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_
corrupt_sig_fatal_chk.1010353050
Directory /workspace/39.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/39.rom_ctrl_kmac_err_chk.3575043604
Short name T307
Test name
Test status
Simulation time 3596093740 ps
CPU time 30.27 seconds
Started Mar 03 02:33:03 PM PST 24
Finished Mar 03 02:33:34 PM PST 24
Peak memory 211432 kb
Host smart-ca0a12a8-6db7-401e-a636-193b7bff011a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3575043604 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_kmac_err_chk.3575043604
Directory /workspace/39.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/39.rom_ctrl_max_throughput_chk.467579873
Short name T4
Test name
Test status
Simulation time 1635450481 ps
CPU time 14.12 seconds
Started Mar 03 02:33:01 PM PST 24
Finished Mar 03 02:33:16 PM PST 24
Peak memory 210804 kb
Host smart-9a6c58c8-e145-4312-8cf8-df64fd23e389
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=467579873 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_max_throughput_chk.467579873
Directory /workspace/39.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/39.rom_ctrl_smoke.4223746422
Short name T309
Test name
Test status
Simulation time 9499123694 ps
CPU time 41.14 seconds
Started Mar 03 02:33:00 PM PST 24
Finished Mar 03 02:33:41 PM PST 24
Peak memory 213864 kb
Host smart-db8ca4e3-5b7e-4bdc-bd39-780e8232260b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4223746422 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_smoke.4223746422
Directory /workspace/39.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/39.rom_ctrl_stress_all.370963299
Short name T182
Test name
Test status
Simulation time 6106970020 ps
CPU time 58.4 seconds
Started Mar 03 02:33:01 PM PST 24
Finished Mar 03 02:34:00 PM PST 24
Peak memory 216416 kb
Host smart-46f7b36a-0274-4a69-ae48-09a4d3d08265
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=370963299 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 39.rom_ctrl_stress_all.370963299
Directory /workspace/39.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/4.rom_ctrl_alert_test.1322647988
Short name T65
Test name
Test status
Simulation time 1914354031 ps
CPU time 15.53 seconds
Started Mar 03 02:31:27 PM PST 24
Finished Mar 03 02:31:43 PM PST 24
Peak memory 210868 kb
Host smart-b211232c-bcb6-4afc-8c22-c0a18376773a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1322647988 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_alert_test.1322647988
Directory /workspace/4.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/4.rom_ctrl_corrupt_sig_fatal_chk.3106545275
Short name T120
Test name
Test status
Simulation time 62172132888 ps
CPU time 181.22 seconds
Started Mar 03 02:31:28 PM PST 24
Finished Mar 03 02:34:30 PM PST 24
Peak memory 236276 kb
Host smart-f6600a65-0e47-4cbe-84cd-333b9a7ace9b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3106545275 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_c
orrupt_sig_fatal_chk.3106545275
Directory /workspace/4.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/4.rom_ctrl_kmac_err_chk.2842471091
Short name T253
Test name
Test status
Simulation time 170177523 ps
CPU time 9.5 seconds
Started Mar 03 02:31:27 PM PST 24
Finished Mar 03 02:31:37 PM PST 24
Peak memory 211636 kb
Host smart-e7fc71ec-13a0-4c8f-be5e-c9dc660a48a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2842471091 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_kmac_err_chk.2842471091
Directory /workspace/4.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/4.rom_ctrl_max_throughput_chk.4093701105
Short name T124
Test name
Test status
Simulation time 3326510304 ps
CPU time 10.73 seconds
Started Mar 03 02:31:28 PM PST 24
Finished Mar 03 02:31:39 PM PST 24
Peak memory 210884 kb
Host smart-578562ee-f0c9-40de-badf-cbc3651c4ac1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4093701105 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_max_throughput_chk.4093701105
Directory /workspace/4.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/4.rom_ctrl_sec_cm.3066368411
Short name T35
Test name
Test status
Simulation time 2835885308 ps
CPU time 54.06 seconds
Started Mar 03 02:31:29 PM PST 24
Finished Mar 03 02:32:24 PM PST 24
Peak memory 235844 kb
Host smart-9c141dd0-dff5-4cde-8120-50ab43fe5f15
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3066368411 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_sec_cm.3066368411
Directory /workspace/4.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/4.rom_ctrl_smoke.2084708655
Short name T221
Test name
Test status
Simulation time 10011768855 ps
CPU time 31.38 seconds
Started Mar 03 02:31:29 PM PST 24
Finished Mar 03 02:32:01 PM PST 24
Peak memory 213676 kb
Host smart-9585fd1e-0cda-4dbc-ba6c-602590656399
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2084708655 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_smoke.2084708655
Directory /workspace/4.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/4.rom_ctrl_stress_all.3425620825
Short name T43
Test name
Test status
Simulation time 1162185790 ps
CPU time 23.55 seconds
Started Mar 03 02:31:27 PM PST 24
Finished Mar 03 02:31:52 PM PST 24
Peak memory 219064 kb
Host smart-62194d12-045b-4187-9ad3-b09e34e54a60
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3425620825 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 4.rom_ctrl_stress_all.3425620825
Directory /workspace/4.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/4.rom_ctrl_stress_all_with_rand_reset.1993698340
Short name T49
Test name
Test status
Simulation time 18045492237 ps
CPU time 697.5 seconds
Started Mar 03 02:31:27 PM PST 24
Finished Mar 03 02:43:06 PM PST 24
Peak memory 231504 kb
Host smart-5bc6b7c7-ffa5-4cb9-980d-d097e1fc9962
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1993698340 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_stress_all_with_rand_reset.1993698340
Directory /workspace/4.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.rom_ctrl_alert_test.1890649025
Short name T211
Test name
Test status
Simulation time 4075461647 ps
CPU time 9.86 seconds
Started Mar 03 02:33:07 PM PST 24
Finished Mar 03 02:33:17 PM PST 24
Peak memory 211004 kb
Host smart-a358cc4c-c314-4dc4-ab45-7be398fa6d1d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1890649025 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_alert_test.1890649025
Directory /workspace/40.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/40.rom_ctrl_corrupt_sig_fatal_chk.3043935994
Short name T264
Test name
Test status
Simulation time 148475142287 ps
CPU time 351.82 seconds
Started Mar 03 02:33:09 PM PST 24
Finished Mar 03 02:39:01 PM PST 24
Peak memory 220456 kb
Host smart-2bb677d4-65ff-4024-b377-185f139a7539
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3043935994 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_
corrupt_sig_fatal_chk.3043935994
Directory /workspace/40.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/40.rom_ctrl_kmac_err_chk.1255753282
Short name T294
Test name
Test status
Simulation time 7190765470 ps
CPU time 30.52 seconds
Started Mar 03 02:33:06 PM PST 24
Finished Mar 03 02:33:37 PM PST 24
Peak memory 211732 kb
Host smart-752ba0ab-722e-4712-a637-83dbf02d3dd5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1255753282 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_kmac_err_chk.1255753282
Directory /workspace/40.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/40.rom_ctrl_max_throughput_chk.63643331
Short name T121
Test name
Test status
Simulation time 4074441071 ps
CPU time 17.24 seconds
Started Mar 03 02:33:07 PM PST 24
Finished Mar 03 02:33:25 PM PST 24
Peak memory 210776 kb
Host smart-5f61b479-99ba-4de1-9537-46ec6a842039
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=63643331 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_max_throughput_chk.63643331
Directory /workspace/40.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/40.rom_ctrl_smoke.2044557666
Short name T247
Test name
Test status
Simulation time 3697062474 ps
CPU time 28.68 seconds
Started Mar 03 02:32:59 PM PST 24
Finished Mar 03 02:33:28 PM PST 24
Peak memory 213108 kb
Host smart-dc7ca6d3-ac26-4fe8-bc7f-80315f8212f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2044557666 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_smoke.2044557666
Directory /workspace/40.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/40.rom_ctrl_stress_all.2653648200
Short name T183
Test name
Test status
Simulation time 4103464642 ps
CPU time 10.74 seconds
Started Mar 03 02:33:05 PM PST 24
Finished Mar 03 02:33:16 PM PST 24
Peak memory 210868 kb
Host smart-b14c3325-ea33-4d44-85b0-9865c4236ae4
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2653648200 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 40.rom_ctrl_stress_all.2653648200
Directory /workspace/40.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/41.rom_ctrl_alert_test.252758769
Short name T214
Test name
Test status
Simulation time 699738717 ps
CPU time 8.93 seconds
Started Mar 03 02:33:06 PM PST 24
Finished Mar 03 02:33:15 PM PST 24
Peak memory 210924 kb
Host smart-416156ad-06bf-45f0-bc0b-f337d131e156
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=252758769 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_alert_test.252758769
Directory /workspace/41.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/41.rom_ctrl_corrupt_sig_fatal_chk.191053896
Short name T188
Test name
Test status
Simulation time 44056266479 ps
CPU time 201.91 seconds
Started Mar 03 02:33:08 PM PST 24
Finished Mar 03 02:36:30 PM PST 24
Peak memory 224556 kb
Host smart-f9afef02-5030-4713-bdcd-beba3395ad57
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=191053896 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_c
orrupt_sig_fatal_chk.191053896
Directory /workspace/41.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/41.rom_ctrl_kmac_err_chk.778371623
Short name T362
Test name
Test status
Simulation time 948785947 ps
CPU time 15.59 seconds
Started Mar 03 02:33:07 PM PST 24
Finished Mar 03 02:33:23 PM PST 24
Peak memory 211504 kb
Host smart-a333cd6c-7dd8-4604-93ab-3d4afe5d6043
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=778371623 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_kmac_err_chk.778371623
Directory /workspace/41.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/41.rom_ctrl_max_throughput_chk.427379819
Short name T243
Test name
Test status
Simulation time 1396255602 ps
CPU time 7.68 seconds
Started Mar 03 02:33:08 PM PST 24
Finished Mar 03 02:33:15 PM PST 24
Peak memory 210768 kb
Host smart-603eace5-5eb6-45f3-bd1d-da71e6604e97
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=427379819 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_max_throughput_chk.427379819
Directory /workspace/41.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/41.rom_ctrl_smoke.4226753928
Short name T180
Test name
Test status
Simulation time 2675397673 ps
CPU time 28.06 seconds
Started Mar 03 02:33:08 PM PST 24
Finished Mar 03 02:33:36 PM PST 24
Peak memory 212792 kb
Host smart-e3f3b824-878b-4ef3-a0ba-8c2ec9fbb447
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4226753928 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_smoke.4226753928
Directory /workspace/41.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/41.rom_ctrl_stress_all.2424032880
Short name T236
Test name
Test status
Simulation time 3083268775 ps
CPU time 15.74 seconds
Started Mar 03 02:33:07 PM PST 24
Finished Mar 03 02:33:23 PM PST 24
Peak memory 210772 kb
Host smart-8bc1075c-b84e-470c-a2ae-07669aa93a8c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2424032880 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 41.rom_ctrl_stress_all.2424032880
Directory /workspace/41.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/42.rom_ctrl_alert_test.1287091442
Short name T47
Test name
Test status
Simulation time 171351445 ps
CPU time 4.28 seconds
Started Mar 03 02:33:14 PM PST 24
Finished Mar 03 02:33:18 PM PST 24
Peak memory 210936 kb
Host smart-9fcfcf46-d442-4382-bc29-5deccca1946c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1287091442 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_alert_test.1287091442
Directory /workspace/42.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/42.rom_ctrl_corrupt_sig_fatal_chk.204918225
Short name T159
Test name
Test status
Simulation time 49102699427 ps
CPU time 178.13 seconds
Started Mar 03 02:33:08 PM PST 24
Finished Mar 03 02:36:07 PM PST 24
Peak memory 236828 kb
Host smart-fe216598-8c2e-4ac6-a6b8-7c8d84c269ff
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=204918225 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_c
orrupt_sig_fatal_chk.204918225
Directory /workspace/42.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/42.rom_ctrl_kmac_err_chk.398090132
Short name T342
Test name
Test status
Simulation time 1149514922 ps
CPU time 12.49 seconds
Started Mar 03 02:33:07 PM PST 24
Finished Mar 03 02:33:20 PM PST 24
Peak memory 211360 kb
Host smart-5aea1e5d-49b8-476a-8a88-2dd9c8ba7235
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=398090132 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_kmac_err_chk.398090132
Directory /workspace/42.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/42.rom_ctrl_max_throughput_chk.829718978
Short name T203
Test name
Test status
Simulation time 298668626 ps
CPU time 7.21 seconds
Started Mar 03 02:33:06 PM PST 24
Finished Mar 03 02:33:14 PM PST 24
Peak memory 210744 kb
Host smart-7db2685f-63b2-4ee7-b06e-098a23f2c055
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=829718978 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_max_throughput_chk.829718978
Directory /workspace/42.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/42.rom_ctrl_smoke.833602892
Short name T192
Test name
Test status
Simulation time 2659099004 ps
CPU time 26.51 seconds
Started Mar 03 02:33:08 PM PST 24
Finished Mar 03 02:33:35 PM PST 24
Peak memory 212956 kb
Host smart-6794786b-8c2d-4217-9c68-2c4d6b413a77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=833602892 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_smoke.833602892
Directory /workspace/42.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/42.rom_ctrl_stress_all.1058076887
Short name T337
Test name
Test status
Simulation time 1735905515 ps
CPU time 36.28 seconds
Started Mar 03 02:33:07 PM PST 24
Finished Mar 03 02:33:44 PM PST 24
Peak memory 215300 kb
Host smart-dd3bd3df-bdac-4b7c-9bff-560820af57da
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1058076887 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 42.rom_ctrl_stress_all.1058076887
Directory /workspace/42.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/43.rom_ctrl_alert_test.3430272523
Short name T166
Test name
Test status
Simulation time 2718412481 ps
CPU time 12.54 seconds
Started Mar 03 02:33:13 PM PST 24
Finished Mar 03 02:33:26 PM PST 24
Peak memory 210924 kb
Host smart-ad7a8a1e-399c-4fcb-a5f4-484f0c04d585
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3430272523 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_alert_test.3430272523
Directory /workspace/43.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/43.rom_ctrl_corrupt_sig_fatal_chk.1903730251
Short name T165
Test name
Test status
Simulation time 42678141287 ps
CPU time 342.73 seconds
Started Mar 03 02:33:13 PM PST 24
Finished Mar 03 02:38:56 PM PST 24
Peak memory 228904 kb
Host smart-7adcf471-72d9-4f8d-8807-34aac949c633
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1903730251 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_
corrupt_sig_fatal_chk.1903730251
Directory /workspace/43.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/43.rom_ctrl_kmac_err_chk.2603659721
Short name T332
Test name
Test status
Simulation time 168765327 ps
CPU time 9.62 seconds
Started Mar 03 02:33:11 PM PST 24
Finished Mar 03 02:33:21 PM PST 24
Peak memory 211508 kb
Host smart-00048156-e2f1-422d-acaa-242ec4d39846
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2603659721 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_kmac_err_chk.2603659721
Directory /workspace/43.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/43.rom_ctrl_max_throughput_chk.1365531047
Short name T202
Test name
Test status
Simulation time 34792569182 ps
CPU time 17.28 seconds
Started Mar 03 02:33:11 PM PST 24
Finished Mar 03 02:33:28 PM PST 24
Peak memory 210900 kb
Host smart-4b0831f3-c46b-4a1c-9d5f-cee2dec4d7b7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1365531047 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_max_throughput_chk.1365531047
Directory /workspace/43.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/43.rom_ctrl_smoke.1486057052
Short name T255
Test name
Test status
Simulation time 4196491941 ps
CPU time 26.21 seconds
Started Mar 03 02:33:11 PM PST 24
Finished Mar 03 02:33:38 PM PST 24
Peak memory 212776 kb
Host smart-465ab6c9-2a19-4ab6-b618-ac9cb9778934
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1486057052 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_smoke.1486057052
Directory /workspace/43.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/43.rom_ctrl_stress_all.3003531027
Short name T363
Test name
Test status
Simulation time 3391347172 ps
CPU time 19.22 seconds
Started Mar 03 02:33:12 PM PST 24
Finished Mar 03 02:33:31 PM PST 24
Peak memory 211360 kb
Host smart-32656cdc-455f-4c2d-8110-bc52791f34b2
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3003531027 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 43.rom_ctrl_stress_all.3003531027
Directory /workspace/43.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/44.rom_ctrl_alert_test.1717591517
Short name T141
Test name
Test status
Simulation time 1777369617 ps
CPU time 15.34 seconds
Started Mar 03 02:33:11 PM PST 24
Finished Mar 03 02:33:26 PM PST 24
Peak memory 210960 kb
Host smart-035ab589-0725-4bd3-9226-9af4ba65f4e4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1717591517 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_alert_test.1717591517
Directory /workspace/44.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/44.rom_ctrl_corrupt_sig_fatal_chk.1189594130
Short name T226
Test name
Test status
Simulation time 13831917386 ps
CPU time 111.78 seconds
Started Mar 03 02:33:14 PM PST 24
Finished Mar 03 02:35:06 PM PST 24
Peak memory 229456 kb
Host smart-1096244a-e030-49c5-8adc-6a37353383e6
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1189594130 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_
corrupt_sig_fatal_chk.1189594130
Directory /workspace/44.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/44.rom_ctrl_kmac_err_chk.2149214760
Short name T306
Test name
Test status
Simulation time 9754584904 ps
CPU time 26.23 seconds
Started Mar 03 02:33:12 PM PST 24
Finished Mar 03 02:33:39 PM PST 24
Peak memory 211636 kb
Host smart-55fafef7-7f1f-4ed0-9362-b38c0d83a0f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2149214760 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_kmac_err_chk.2149214760
Directory /workspace/44.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/44.rom_ctrl_max_throughput_chk.1790990517
Short name T195
Test name
Test status
Simulation time 1153947218 ps
CPU time 12.9 seconds
Started Mar 03 02:33:13 PM PST 24
Finished Mar 03 02:33:26 PM PST 24
Peak memory 210764 kb
Host smart-8390bd37-cd64-42b7-99d4-8eaeba269410
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1790990517 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_max_throughput_chk.1790990517
Directory /workspace/44.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/44.rom_ctrl_smoke.2730796165
Short name T79
Test name
Test status
Simulation time 676991309 ps
CPU time 15.84 seconds
Started Mar 03 02:33:12 PM PST 24
Finished Mar 03 02:33:28 PM PST 24
Peak memory 212660 kb
Host smart-035e2f4e-af61-4c4e-b8e1-36a346db3fad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2730796165 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_smoke.2730796165
Directory /workspace/44.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/44.rom_ctrl_stress_all.1022981645
Short name T339
Test name
Test status
Simulation time 3502630277 ps
CPU time 20.31 seconds
Started Mar 03 02:33:11 PM PST 24
Finished Mar 03 02:33:31 PM PST 24
Peak memory 210696 kb
Host smart-6f2f8cd8-b51d-4f25-8d76-a60119beb612
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1022981645 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 44.rom_ctrl_stress_all.1022981645
Directory /workspace/44.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/45.rom_ctrl_alert_test.4208986653
Short name T64
Test name
Test status
Simulation time 2466244071 ps
CPU time 12.01 seconds
Started Mar 03 02:33:19 PM PST 24
Finished Mar 03 02:33:31 PM PST 24
Peak memory 210964 kb
Host smart-f6767f0e-d774-471b-9e4f-f333d233e163
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4208986653 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_alert_test.4208986653
Directory /workspace/45.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/45.rom_ctrl_corrupt_sig_fatal_chk.3171691673
Short name T184
Test name
Test status
Simulation time 14578880377 ps
CPU time 163.07 seconds
Started Mar 03 02:33:13 PM PST 24
Finished Mar 03 02:35:57 PM PST 24
Peak memory 237480 kb
Host smart-413b0775-16e9-4bab-b51b-2e5ebec22cf6
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3171691673 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_
corrupt_sig_fatal_chk.3171691673
Directory /workspace/45.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/45.rom_ctrl_kmac_err_chk.2416791017
Short name T328
Test name
Test status
Simulation time 14669565526 ps
CPU time 32.04 seconds
Started Mar 03 02:33:10 PM PST 24
Finished Mar 03 02:33:43 PM PST 24
Peak memory 211708 kb
Host smart-813d343b-f725-4b4d-9891-92a18c9c1410
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2416791017 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_kmac_err_chk.2416791017
Directory /workspace/45.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/45.rom_ctrl_max_throughput_chk.11098511
Short name T304
Test name
Test status
Simulation time 269309342 ps
CPU time 7.71 seconds
Started Mar 03 02:33:13 PM PST 24
Finished Mar 03 02:33:21 PM PST 24
Peak memory 210840 kb
Host smart-cc86863b-f1b5-45a8-b450-d4d09689a11f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=11098511 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_max_throughput_chk.11098511
Directory /workspace/45.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/45.rom_ctrl_smoke.2050576311
Short name T231
Test name
Test status
Simulation time 4300843246 ps
CPU time 34.9 seconds
Started Mar 03 02:33:14 PM PST 24
Finished Mar 03 02:33:49 PM PST 24
Peak memory 213068 kb
Host smart-7016c6b9-8999-4f7e-adc2-55ef0ec900cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2050576311 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_smoke.2050576311
Directory /workspace/45.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/45.rom_ctrl_stress_all.2366739742
Short name T346
Test name
Test status
Simulation time 7694303308 ps
CPU time 66.82 seconds
Started Mar 03 02:33:11 PM PST 24
Finished Mar 03 02:34:18 PM PST 24
Peak memory 215248 kb
Host smart-197e8ecf-fdf7-404c-804d-86f3b6fb54e4
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2366739742 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 45.rom_ctrl_stress_all.2366739742
Directory /workspace/45.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/46.rom_ctrl_alert_test.3475150795
Short name T213
Test name
Test status
Simulation time 3953613816 ps
CPU time 15.81 seconds
Started Mar 03 02:33:19 PM PST 24
Finished Mar 03 02:33:35 PM PST 24
Peak memory 211028 kb
Host smart-ef56a431-2759-4403-a6e1-5696ad58bcf8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3475150795 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_alert_test.3475150795
Directory /workspace/46.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/46.rom_ctrl_corrupt_sig_fatal_chk.3449407778
Short name T170
Test name
Test status
Simulation time 58840507482 ps
CPU time 534.04 seconds
Started Mar 03 02:33:20 PM PST 24
Finished Mar 03 02:42:15 PM PST 24
Peak memory 212268 kb
Host smart-56b96269-9779-40a5-b763-ab6b8a191f86
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3449407778 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_
corrupt_sig_fatal_chk.3449407778
Directory /workspace/46.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/46.rom_ctrl_kmac_err_chk.2147785092
Short name T24
Test name
Test status
Simulation time 168384908 ps
CPU time 9.47 seconds
Started Mar 03 02:33:18 PM PST 24
Finished Mar 03 02:33:28 PM PST 24
Peak memory 211348 kb
Host smart-2891bee4-e12a-41b0-928a-d04af88889ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2147785092 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_kmac_err_chk.2147785092
Directory /workspace/46.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/46.rom_ctrl_max_throughput_chk.1182324366
Short name T275
Test name
Test status
Simulation time 4225335530 ps
CPU time 18.4 seconds
Started Mar 03 02:33:18 PM PST 24
Finished Mar 03 02:33:37 PM PST 24
Peak memory 211060 kb
Host smart-8c8b39b5-87f3-487b-a373-266f58421940
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1182324366 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_max_throughput_chk.1182324366
Directory /workspace/46.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/46.rom_ctrl_smoke.2108800448
Short name T12
Test name
Test status
Simulation time 7227716052 ps
CPU time 21.53 seconds
Started Mar 03 02:33:20 PM PST 24
Finished Mar 03 02:33:42 PM PST 24
Peak memory 214004 kb
Host smart-9cac03b3-bcd0-43fc-bbfc-e1db7d6e8493
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2108800448 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_smoke.2108800448
Directory /workspace/46.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/46.rom_ctrl_stress_all.1813963732
Short name T314
Test name
Test status
Simulation time 1246591144 ps
CPU time 17.27 seconds
Started Mar 03 02:33:19 PM PST 24
Finished Mar 03 02:33:36 PM PST 24
Peak memory 211780 kb
Host smart-78206457-93fe-4725-9639-abaaf74e00f0
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1813963732 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 46.rom_ctrl_stress_all.1813963732
Directory /workspace/46.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/46.rom_ctrl_stress_all_with_rand_reset.564929538
Short name T330
Test name
Test status
Simulation time 108806909221 ps
CPU time 2676.91 seconds
Started Mar 03 02:33:19 PM PST 24
Finished Mar 03 03:17:56 PM PST 24
Peak memory 234604 kb
Host smart-11c928fe-7c73-4b7c-8586-10fd9beb0676
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=564929538 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_stress_all_with_rand_reset.564929538
Directory /workspace/46.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.rom_ctrl_alert_test.2069925036
Short name T11
Test name
Test status
Simulation time 1911753401 ps
CPU time 10.01 seconds
Started Mar 03 02:33:26 PM PST 24
Finished Mar 03 02:33:36 PM PST 24
Peak memory 210940 kb
Host smart-5adfea0c-d236-44cc-9a03-0750d4080cb3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2069925036 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_alert_test.2069925036
Directory /workspace/47.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/47.rom_ctrl_corrupt_sig_fatal_chk.3977912687
Short name T238
Test name
Test status
Simulation time 67202647136 ps
CPU time 263.57 seconds
Started Mar 03 02:33:24 PM PST 24
Finished Mar 03 02:37:47 PM PST 24
Peak memory 236336 kb
Host smart-50c7c99a-afd2-4aed-a603-707a62745bc7
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3977912687 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_
corrupt_sig_fatal_chk.3977912687
Directory /workspace/47.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/47.rom_ctrl_max_throughput_chk.2947846689
Short name T345
Test name
Test status
Simulation time 4246081265 ps
CPU time 14.07 seconds
Started Mar 03 02:33:18 PM PST 24
Finished Mar 03 02:33:32 PM PST 24
Peak memory 210876 kb
Host smart-1ac421b3-187e-4da9-9a65-68f06c88657c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2947846689 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_max_throughput_chk.2947846689
Directory /workspace/47.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/47.rom_ctrl_smoke.228591797
Short name T204
Test name
Test status
Simulation time 6187121673 ps
CPU time 19.04 seconds
Started Mar 03 02:33:19 PM PST 24
Finished Mar 03 02:33:38 PM PST 24
Peak memory 212544 kb
Host smart-dd49be72-8930-4c31-ab0c-22df1fd200a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=228591797 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_smoke.228591797
Directory /workspace/47.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/47.rom_ctrl_stress_all.1217045495
Short name T301
Test name
Test status
Simulation time 1122177268 ps
CPU time 18.81 seconds
Started Mar 03 02:33:21 PM PST 24
Finished Mar 03 02:33:40 PM PST 24
Peak memory 213244 kb
Host smart-996b6b75-1b61-413c-9583-572e5a50c1aa
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1217045495 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 47.rom_ctrl_stress_all.1217045495
Directory /workspace/47.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/48.rom_ctrl_alert_test.2888028216
Short name T235
Test name
Test status
Simulation time 8344664554 ps
CPU time 16.23 seconds
Started Mar 03 02:33:26 PM PST 24
Finished Mar 03 02:33:43 PM PST 24
Peak memory 210924 kb
Host smart-3739f49a-3a0b-4367-8e6e-744b1646f5c3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2888028216 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_alert_test.2888028216
Directory /workspace/48.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/48.rom_ctrl_corrupt_sig_fatal_chk.649741040
Short name T239
Test name
Test status
Simulation time 13356709355 ps
CPU time 169.73 seconds
Started Mar 03 02:33:27 PM PST 24
Finished Mar 03 02:36:17 PM PST 24
Peak memory 219660 kb
Host smart-3bd2e895-ae88-40c8-a00c-b44329dec3b5
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=649741040 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_c
orrupt_sig_fatal_chk.649741040
Directory /workspace/48.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/48.rom_ctrl_kmac_err_chk.1239366508
Short name T205
Test name
Test status
Simulation time 10562703216 ps
CPU time 24.97 seconds
Started Mar 03 02:33:26 PM PST 24
Finished Mar 03 02:33:52 PM PST 24
Peak memory 212200 kb
Host smart-47c72621-3b48-4c87-811f-beb87ce91a69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1239366508 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_kmac_err_chk.1239366508
Directory /workspace/48.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/48.rom_ctrl_max_throughput_chk.3637344628
Short name T14
Test name
Test status
Simulation time 1881370666 ps
CPU time 10.64 seconds
Started Mar 03 02:33:29 PM PST 24
Finished Mar 03 02:33:40 PM PST 24
Peak memory 210840 kb
Host smart-ef3e87d8-9bb1-4137-adfc-dbf3bab6ee8d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3637344628 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_max_throughput_chk.3637344628
Directory /workspace/48.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/48.rom_ctrl_smoke.921904469
Short name T206
Test name
Test status
Simulation time 40711729006 ps
CPU time 30.89 seconds
Started Mar 03 02:33:28 PM PST 24
Finished Mar 03 02:33:59 PM PST 24
Peak memory 213376 kb
Host smart-a45a4aa4-9999-4e75-b949-20a4d0d6f44f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=921904469 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_smoke.921904469
Directory /workspace/48.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/48.rom_ctrl_stress_all.1737783573
Short name T116
Test name
Test status
Simulation time 9654254496 ps
CPU time 27.28 seconds
Started Mar 03 02:33:25 PM PST 24
Finished Mar 03 02:33:53 PM PST 24
Peak memory 214244 kb
Host smart-4eb5d7d0-0626-4cf4-9aea-e51adb3171dd
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1737783573 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 48.rom_ctrl_stress_all.1737783573
Directory /workspace/48.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/48.rom_ctrl_stress_all_with_rand_reset.321846964
Short name T53
Test name
Test status
Simulation time 244500699857 ps
CPU time 2833.33 seconds
Started Mar 03 02:33:28 PM PST 24
Finished Mar 03 03:20:42 PM PST 24
Peak memory 251936 kb
Host smart-58fe91e4-f556-4ead-aaf9-ee9b33673b73
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=321846964 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_stress_all_with_rand_reset.321846964
Directory /workspace/48.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/49.rom_ctrl_alert_test.2058984634
Short name T347
Test name
Test status
Simulation time 18862526665 ps
CPU time 15.79 seconds
Started Mar 03 02:33:26 PM PST 24
Finished Mar 03 02:33:42 PM PST 24
Peak memory 211032 kb
Host smart-8a16ed54-445b-4d9c-b5c8-845b81e83a0a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2058984634 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_alert_test.2058984634
Directory /workspace/49.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/49.rom_ctrl_corrupt_sig_fatal_chk.1570993261
Short name T303
Test name
Test status
Simulation time 4199446691 ps
CPU time 136.6 seconds
Started Mar 03 02:33:26 PM PST 24
Finished Mar 03 02:35:44 PM PST 24
Peak memory 232744 kb
Host smart-7a1b7f1c-cec6-4b32-a374-363adfab1ad3
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1570993261 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_
corrupt_sig_fatal_chk.1570993261
Directory /workspace/49.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/49.rom_ctrl_kmac_err_chk.1406573996
Short name T161
Test name
Test status
Simulation time 1276672663 ps
CPU time 9.62 seconds
Started Mar 03 02:33:28 PM PST 24
Finished Mar 03 02:33:38 PM PST 24
Peak memory 210928 kb
Host smart-90df52d8-c409-4fce-a7ce-f08d116d8a5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1406573996 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_kmac_err_chk.1406573996
Directory /workspace/49.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/49.rom_ctrl_max_throughput_chk.2065543864
Short name T324
Test name
Test status
Simulation time 2747813428 ps
CPU time 15.71 seconds
Started Mar 03 02:33:25 PM PST 24
Finished Mar 03 02:33:41 PM PST 24
Peak memory 210884 kb
Host smart-216b268c-d00d-4018-8f2c-586ad63acda0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2065543864 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_max_throughput_chk.2065543864
Directory /workspace/49.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/49.rom_ctrl_smoke.3436069784
Short name T232
Test name
Test status
Simulation time 3793260006 ps
CPU time 23.64 seconds
Started Mar 03 02:33:24 PM PST 24
Finished Mar 03 02:33:48 PM PST 24
Peak memory 212392 kb
Host smart-dd103154-eb76-45c8-9a1a-491abe8653eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3436069784 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_smoke.3436069784
Directory /workspace/49.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/49.rom_ctrl_stress_all.2738221266
Short name T349
Test name
Test status
Simulation time 67126376545 ps
CPU time 72.62 seconds
Started Mar 03 02:33:25 PM PST 24
Finished Mar 03 02:34:38 PM PST 24
Peak memory 218420 kb
Host smart-8f176b0e-5f99-4f56-bff3-a69b54b4402f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2738221266 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 49.rom_ctrl_stress_all.2738221266
Directory /workspace/49.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/49.rom_ctrl_stress_all_with_rand_reset.1466345835
Short name T17
Test name
Test status
Simulation time 94571800187 ps
CPU time 977.72 seconds
Started Mar 03 02:33:29 PM PST 24
Finished Mar 03 02:49:48 PM PST 24
Peak memory 235596 kb
Host smart-37e79a72-85eb-47c2-b400-de9578ae619f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1466345835 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_stress_all_with_rand_reset.1466345835
Directory /workspace/49.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.rom_ctrl_alert_test.3481570840
Short name T326
Test name
Test status
Simulation time 361734471 ps
CPU time 4.26 seconds
Started Mar 03 02:31:33 PM PST 24
Finished Mar 03 02:31:38 PM PST 24
Peak memory 210956 kb
Host smart-c2c78095-49ee-4883-9560-33d7c3a78aa2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3481570840 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_alert_test.3481570840
Directory /workspace/5.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/5.rom_ctrl_corrupt_sig_fatal_chk.739589425
Short name T179
Test name
Test status
Simulation time 84697794054 ps
CPU time 253.44 seconds
Started Mar 03 02:31:34 PM PST 24
Finished Mar 03 02:35:47 PM PST 24
Peak memory 234512 kb
Host smart-474f59f5-c919-4113-af58-5d827ecbd43b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=739589425 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_co
rrupt_sig_fatal_chk.739589425
Directory /workspace/5.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/5.rom_ctrl_kmac_err_chk.3446449451
Short name T2
Test name
Test status
Simulation time 4992378828 ps
CPU time 17.84 seconds
Started Mar 03 02:31:34 PM PST 24
Finished Mar 03 02:31:52 PM PST 24
Peak memory 211828 kb
Host smart-12c961c5-131a-43e9-9e26-0a57dbd30982
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3446449451 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_kmac_err_chk.3446449451
Directory /workspace/5.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/5.rom_ctrl_max_throughput_chk.813249688
Short name T187
Test name
Test status
Simulation time 13238415474 ps
CPU time 12.57 seconds
Started Mar 03 02:31:34 PM PST 24
Finished Mar 03 02:31:46 PM PST 24
Peak memory 210904 kb
Host smart-3824fdbc-1cc8-4d90-a5bf-48c62f91da28
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=813249688 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_max_throughput_chk.813249688
Directory /workspace/5.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/5.rom_ctrl_smoke.2899923914
Short name T224
Test name
Test status
Simulation time 15241037890 ps
CPU time 32.25 seconds
Started Mar 03 02:31:34 PM PST 24
Finished Mar 03 02:32:07 PM PST 24
Peak memory 213568 kb
Host smart-90b89427-5d4c-4d52-8566-3d26a541a452
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2899923914 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_smoke.2899923914
Directory /workspace/5.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/5.rom_ctrl_stress_all.7654255
Short name T251
Test name
Test status
Simulation time 39712736543 ps
CPU time 66.85 seconds
Started Mar 03 02:31:34 PM PST 24
Finished Mar 03 02:32:41 PM PST 24
Peak memory 219116 kb
Host smart-b2e9d705-acbe-40fd-a0c4-bfe96447d874
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=7654255 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UV
M_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 5.rom_ctrl_stress_all.7654255
Directory /workspace/5.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/5.rom_ctrl_stress_all_with_rand_reset.2807865763
Short name T52
Test name
Test status
Simulation time 70683548495 ps
CPU time 10596.5 seconds
Started Mar 03 02:31:32 PM PST 24
Finished Mar 03 05:28:10 PM PST 24
Peak memory 243752 kb
Host smart-9425aa0c-fb76-4957-b87a-787e9a00e3b9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2807865763 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_stress_all_with_rand_reset.2807865763
Directory /workspace/5.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.rom_ctrl_alert_test.2232032587
Short name T181
Test name
Test status
Simulation time 1506432606 ps
CPU time 12.95 seconds
Started Mar 03 02:31:31 PM PST 24
Finished Mar 03 02:31:44 PM PST 24
Peak memory 210936 kb
Host smart-4573f7b4-8329-4d5a-9928-edfc70d65167
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2232032587 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_alert_test.2232032587
Directory /workspace/6.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/6.rom_ctrl_corrupt_sig_fatal_chk.1646990805
Short name T272
Test name
Test status
Simulation time 41640250814 ps
CPU time 411.73 seconds
Started Mar 03 02:31:32 PM PST 24
Finished Mar 03 02:38:24 PM PST 24
Peak memory 237448 kb
Host smart-efa9a96d-8f0f-4d7f-b1f1-8bd5c0506f33
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1646990805 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_c
orrupt_sig_fatal_chk.1646990805
Directory /workspace/6.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/6.rom_ctrl_kmac_err_chk.4097549352
Short name T134
Test name
Test status
Simulation time 2070961190 ps
CPU time 13.23 seconds
Started Mar 03 02:31:34 PM PST 24
Finished Mar 03 02:31:48 PM PST 24
Peak memory 211336 kb
Host smart-ce9524ea-214f-4ca2-8a6a-44ad666a0941
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4097549352 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_kmac_err_chk.4097549352
Directory /workspace/6.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/6.rom_ctrl_max_throughput_chk.946551487
Short name T127
Test name
Test status
Simulation time 11705352945 ps
CPU time 14 seconds
Started Mar 03 02:31:32 PM PST 24
Finished Mar 03 02:31:46 PM PST 24
Peak memory 210856 kb
Host smart-c24cc5bf-0f13-43e0-a3f0-8a0c52b3ade8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=946551487 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_max_throughput_chk.946551487
Directory /workspace/6.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/6.rom_ctrl_smoke.1264379525
Short name T119
Test name
Test status
Simulation time 1212353659 ps
CPU time 10.16 seconds
Started Mar 03 02:31:32 PM PST 24
Finished Mar 03 02:31:42 PM PST 24
Peak memory 212796 kb
Host smart-83d09928-95c6-4237-8c80-5184eed301d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1264379525 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_smoke.1264379525
Directory /workspace/6.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/6.rom_ctrl_stress_all.2497457529
Short name T101
Test name
Test status
Simulation time 1667908770 ps
CPU time 18.58 seconds
Started Mar 03 02:31:32 PM PST 24
Finished Mar 03 02:31:51 PM PST 24
Peak memory 211196 kb
Host smart-144c920e-ad5e-4455-9439-ba3c4c1a1968
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2497457529 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 6.rom_ctrl_stress_all.2497457529
Directory /workspace/6.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/7.rom_ctrl_alert_test.1451468594
Short name T261
Test name
Test status
Simulation time 1753441927 ps
CPU time 7.7 seconds
Started Mar 03 02:31:38 PM PST 24
Finished Mar 03 02:31:46 PM PST 24
Peak memory 210932 kb
Host smart-b29b7fe5-98c2-47b1-837a-a5b15b776162
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1451468594 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_alert_test.1451468594
Directory /workspace/7.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/7.rom_ctrl_corrupt_sig_fatal_chk.1693390889
Short name T27
Test name
Test status
Simulation time 204815768997 ps
CPU time 337.38 seconds
Started Mar 03 02:31:35 PM PST 24
Finished Mar 03 02:37:12 PM PST 24
Peak memory 238656 kb
Host smart-51951fc3-ded1-4dea-929a-48703ca36c40
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1693390889 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_c
orrupt_sig_fatal_chk.1693390889
Directory /workspace/7.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/7.rom_ctrl_kmac_err_chk.1230108738
Short name T289
Test name
Test status
Simulation time 3436295017 ps
CPU time 14.76 seconds
Started Mar 03 02:31:38 PM PST 24
Finished Mar 03 02:31:54 PM PST 24
Peak memory 211360 kb
Host smart-db05746e-9ddf-4341-8a98-372c2755af31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1230108738 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_kmac_err_chk.1230108738
Directory /workspace/7.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/7.rom_ctrl_max_throughput_chk.1886692872
Short name T193
Test name
Test status
Simulation time 1478709934 ps
CPU time 13.9 seconds
Started Mar 03 02:31:32 PM PST 24
Finished Mar 03 02:31:46 PM PST 24
Peak memory 210848 kb
Host smart-88dd9081-9575-4be1-8a8b-cecb5b035e65
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1886692872 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_max_throughput_chk.1886692872
Directory /workspace/7.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/7.rom_ctrl_smoke.2573272485
Short name T258
Test name
Test status
Simulation time 16530571082 ps
CPU time 31.97 seconds
Started Mar 03 02:31:34 PM PST 24
Finished Mar 03 02:32:06 PM PST 24
Peak memory 213800 kb
Host smart-3d9cd6fc-f979-4c6f-926c-4571aa1050c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2573272485 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_smoke.2573272485
Directory /workspace/7.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/7.rom_ctrl_stress_all.534535208
Short name T152
Test name
Test status
Simulation time 435967470 ps
CPU time 23.73 seconds
Started Mar 03 02:31:33 PM PST 24
Finished Mar 03 02:31:57 PM PST 24
Peak memory 216016 kb
Host smart-f0d2933d-0026-4a3a-875c-34b2fe8f2a70
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=534535208 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 7.rom_ctrl_stress_all.534535208
Directory /workspace/7.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/8.rom_ctrl_alert_test.4214736305
Short name T207
Test name
Test status
Simulation time 5919894795 ps
CPU time 11.03 seconds
Started Mar 03 02:31:39 PM PST 24
Finished Mar 03 02:31:51 PM PST 24
Peak memory 210888 kb
Host smart-b46b85b9-2fe6-4a25-a7f4-73c1142a1c9e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4214736305 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_alert_test.4214736305
Directory /workspace/8.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/8.rom_ctrl_corrupt_sig_fatal_chk.1330354930
Short name T248
Test name
Test status
Simulation time 37175268030 ps
CPU time 114.31 seconds
Started Mar 03 02:31:39 PM PST 24
Finished Mar 03 02:33:35 PM PST 24
Peak memory 239968 kb
Host smart-c680461c-4123-412f-a606-e415efe346da
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1330354930 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_c
orrupt_sig_fatal_chk.1330354930
Directory /workspace/8.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/8.rom_ctrl_kmac_err_chk.1574521459
Short name T218
Test name
Test status
Simulation time 2913695376 ps
CPU time 26.62 seconds
Started Mar 03 02:31:39 PM PST 24
Finished Mar 03 02:32:06 PM PST 24
Peak memory 211672 kb
Host smart-e3683b1b-b5b4-4c1d-b3b1-1e3e0a9a2edc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1574521459 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_kmac_err_chk.1574521459
Directory /workspace/8.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/8.rom_ctrl_max_throughput_chk.4025431215
Short name T39
Test name
Test status
Simulation time 7861778969 ps
CPU time 17.2 seconds
Started Mar 03 02:31:38 PM PST 24
Finished Mar 03 02:31:56 PM PST 24
Peak memory 210884 kb
Host smart-5570ab3f-c030-4028-acde-31ac2196b21b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4025431215 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_max_throughput_chk.4025431215
Directory /workspace/8.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/8.rom_ctrl_smoke.3465296763
Short name T114
Test name
Test status
Simulation time 2169248944 ps
CPU time 16.1 seconds
Started Mar 03 02:31:48 PM PST 24
Finished Mar 03 02:32:04 PM PST 24
Peak memory 213384 kb
Host smart-d41eb223-093c-458a-810b-833d694327bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3465296763 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_smoke.3465296763
Directory /workspace/8.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/8.rom_ctrl_stress_all.2729465478
Short name T137
Test name
Test status
Simulation time 222797255 ps
CPU time 6.17 seconds
Started Mar 03 02:31:40 PM PST 24
Finished Mar 03 02:31:47 PM PST 24
Peak memory 210912 kb
Host smart-b9bfdc25-4fbf-43e2-b0f9-fb69b927cd1c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2729465478 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 8.rom_ctrl_stress_all.2729465478
Directory /workspace/8.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/9.rom_ctrl_alert_test.1245342766
Short name T325
Test name
Test status
Simulation time 2216478318 ps
CPU time 7.83 seconds
Started Mar 03 02:31:40 PM PST 24
Finished Mar 03 02:31:48 PM PST 24
Peak memory 210980 kb
Host smart-3a37441c-eced-4420-b8c6-d4c2e920ca50
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1245342766 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_alert_test.1245342766
Directory /workspace/9.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/9.rom_ctrl_corrupt_sig_fatal_chk.1018492205
Short name T215
Test name
Test status
Simulation time 2530872675 ps
CPU time 95.87 seconds
Started Mar 03 02:31:40 PM PST 24
Finished Mar 03 02:33:16 PM PST 24
Peak memory 212292 kb
Host smart-b90b20de-6fd6-43c4-a0e6-77ba976e0a2d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1018492205 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_c
orrupt_sig_fatal_chk.1018492205
Directory /workspace/9.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/9.rom_ctrl_kmac_err_chk.2945043966
Short name T228
Test name
Test status
Simulation time 1935750485 ps
CPU time 22.03 seconds
Started Mar 03 02:31:39 PM PST 24
Finished Mar 03 02:32:02 PM PST 24
Peak memory 211480 kb
Host smart-2fb004c9-cbc2-4e80-8f95-5c162a33f396
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2945043966 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_kmac_err_chk.2945043966
Directory /workspace/9.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/9.rom_ctrl_max_throughput_chk.2955962813
Short name T144
Test name
Test status
Simulation time 185985270 ps
CPU time 5.44 seconds
Started Mar 03 02:31:39 PM PST 24
Finished Mar 03 02:31:44 PM PST 24
Peak memory 210808 kb
Host smart-51539489-af92-455e-984a-b3ffbdde5521
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2955962813 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_max_throughput_chk.2955962813
Directory /workspace/9.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/9.rom_ctrl_smoke.2640075371
Short name T209
Test name
Test status
Simulation time 363431093 ps
CPU time 9.76 seconds
Started Mar 03 02:31:40 PM PST 24
Finished Mar 03 02:31:50 PM PST 24
Peak memory 212824 kb
Host smart-3e4595d9-a917-4f77-a8dc-e788664b6f64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2640075371 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_smoke.2640075371
Directory /workspace/9.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/9.rom_ctrl_stress_all.2661490858
Short name T269
Test name
Test status
Simulation time 60938141746 ps
CPU time 44.93 seconds
Started Mar 03 02:31:41 PM PST 24
Finished Mar 03 02:32:26 PM PST 24
Peak memory 216320 kb
Host smart-ab5f7ce8-eee9-4144-b87a-d79217805b7e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2661490858 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 9.rom_ctrl_stress_all.2661490858
Directory /workspace/9.rom_ctrl_stress_all/latest
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