| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
| 97.43 | 97.04 | 92.65 | 97.88 | 100.00 | 98.37 | 97.89 | 98.14 |
| T294 | /workspace/coverage/default/24.rom_ctrl_alert_test.2385368631 | Mar 05 01:51:37 PM PST 24 | Mar 05 01:51:48 PM PST 24 | 911355160 ps | ||
| T295 | /workspace/coverage/default/16.rom_ctrl_smoke.1162451848 | Mar 05 01:51:18 PM PST 24 | Mar 05 01:51:33 PM PST 24 | 724804313 ps | ||
| T296 | /workspace/coverage/default/4.rom_ctrl_alert_test.2922486577 | Mar 05 01:51:03 PM PST 24 | Mar 05 01:51:12 PM PST 24 | 2669120566 ps | ||
| T297 | /workspace/coverage/default/39.rom_ctrl_smoke.2989806082 | Mar 05 01:51:37 PM PST 24 | Mar 05 01:51:52 PM PST 24 | 516460991 ps | ||
| T298 | /workspace/coverage/default/14.rom_ctrl_kmac_err_chk.3677869184 | Mar 05 01:51:09 PM PST 24 | Mar 05 01:51:30 PM PST 24 | 7289040006 ps | ||
| T299 | /workspace/coverage/default/48.rom_ctrl_smoke.68977554 | Mar 05 01:51:54 PM PST 24 | Mar 05 01:52:16 PM PST 24 | 2599235189 ps | ||
| T300 | /workspace/coverage/default/22.rom_ctrl_stress_all.1424317845 | Mar 05 01:51:21 PM PST 24 | Mar 05 01:51:40 PM PST 24 | 3709107368 ps | ||
| T301 | /workspace/coverage/default/22.rom_ctrl_alert_test.1123460596 | Mar 05 01:51:28 PM PST 24 | Mar 05 01:51:41 PM PST 24 | 5973987697 ps | ||
| T302 | /workspace/coverage/default/21.rom_ctrl_max_throughput_chk.2063248228 | Mar 05 01:51:28 PM PST 24 | Mar 05 01:51:40 PM PST 24 | 2495593076 ps | ||
| T303 | /workspace/coverage/default/32.rom_ctrl_smoke.4243430737 | Mar 05 01:51:48 PM PST 24 | Mar 05 01:52:19 PM PST 24 | 4321101619 ps | ||
| T304 | /workspace/coverage/default/27.rom_ctrl_kmac_err_chk.781788054 | Mar 05 01:51:36 PM PST 24 | Mar 05 01:52:08 PM PST 24 | 16033956295 ps | ||
| T305 | /workspace/coverage/default/24.rom_ctrl_max_throughput_chk.3072576959 | Mar 05 01:51:33 PM PST 24 | Mar 05 01:51:46 PM PST 24 | 4974853213 ps | ||
| T306 | /workspace/coverage/default/32.rom_ctrl_stress_all.3663609888 | Mar 05 01:51:48 PM PST 24 | Mar 05 01:52:30 PM PST 24 | 84578141241 ps | ||
| T307 | /workspace/coverage/default/14.rom_ctrl_stress_all.2954433744 | Mar 05 01:51:24 PM PST 24 | Mar 05 01:52:43 PM PST 24 | 9227079186 ps | ||
| T308 | /workspace/coverage/default/3.rom_ctrl_max_throughput_chk.579188566 | Mar 05 01:51:14 PM PST 24 | Mar 05 01:51:27 PM PST 24 | 1195458034 ps | ||
| T309 | /workspace/coverage/default/33.rom_ctrl_corrupt_sig_fatal_chk.1978876019 | Mar 05 01:51:37 PM PST 24 | Mar 05 01:54:54 PM PST 24 | 11108596204 ps | ||
| T310 | /workspace/coverage/default/33.rom_ctrl_max_throughput_chk.981306401 | Mar 05 01:51:42 PM PST 24 | Mar 05 01:51:57 PM PST 24 | 1770703862 ps | ||
| T311 | /workspace/coverage/default/6.rom_ctrl_kmac_err_chk.3994418595 | Mar 05 01:51:07 PM PST 24 | Mar 05 01:51:28 PM PST 24 | 7161545428 ps | ||
| T312 | /workspace/coverage/default/24.rom_ctrl_stress_all.3913491233 | Mar 05 01:51:25 PM PST 24 | Mar 05 01:51:51 PM PST 24 | 6231574790 ps | ||
| T313 | /workspace/coverage/default/30.rom_ctrl_max_throughput_chk.3532897144 | Mar 05 01:51:44 PM PST 24 | Mar 05 01:51:53 PM PST 24 | 457756307 ps | ||
| T314 | /workspace/coverage/default/5.rom_ctrl_kmac_err_chk.1722561193 | Mar 05 01:51:05 PM PST 24 | Mar 05 01:51:14 PM PST 24 | 348326774 ps | ||
| T315 | /workspace/coverage/default/34.rom_ctrl_corrupt_sig_fatal_chk.905337811 | Mar 05 01:51:38 PM PST 24 | Mar 05 01:55:31 PM PST 24 | 87897511567 ps | ||
| T316 | /workspace/coverage/default/44.rom_ctrl_corrupt_sig_fatal_chk.2273896462 | Mar 05 01:51:54 PM PST 24 | Mar 05 01:53:56 PM PST 24 | 14073026034 ps | ||
| T317 | /workspace/coverage/default/37.rom_ctrl_corrupt_sig_fatal_chk.1816323230 | Mar 05 01:51:56 PM PST 24 | Mar 05 01:55:00 PM PST 24 | 142439972507 ps | ||
| T318 | /workspace/coverage/default/3.rom_ctrl_kmac_err_chk.3730829866 | Mar 05 01:51:08 PM PST 24 | Mar 05 01:51:27 PM PST 24 | 2738372823 ps | ||
| T319 | /workspace/coverage/default/23.rom_ctrl_corrupt_sig_fatal_chk.1306070835 | Mar 05 01:51:35 PM PST 24 | Mar 05 01:59:05 PM PST 24 | 790081328881 ps | ||
| T320 | /workspace/coverage/default/1.rom_ctrl_kmac_err_chk.3630048332 | Mar 05 01:50:58 PM PST 24 | Mar 05 01:51:20 PM PST 24 | 23570224031 ps | ||
| T321 | /workspace/coverage/default/25.rom_ctrl_max_throughput_chk.4043877517 | Mar 05 01:51:43 PM PST 24 | Mar 05 01:51:52 PM PST 24 | 1645433528 ps | ||
| T35 | /workspace/coverage/default/1.rom_ctrl_sec_cm.640757694 | Mar 05 01:51:02 PM PST 24 | Mar 05 01:52:52 PM PST 24 | 2181849914 ps | ||
| T322 | /workspace/coverage/default/40.rom_ctrl_max_throughput_chk.4264881062 | Mar 05 01:51:46 PM PST 24 | Mar 05 01:51:52 PM PST 24 | 185025485 ps | ||
| T323 | /workspace/coverage/default/2.rom_ctrl_kmac_err_chk.3458466327 | Mar 05 01:51:06 PM PST 24 | Mar 05 01:51:16 PM PST 24 | 1839813824 ps | ||
| T36 | /workspace/coverage/default/4.rom_ctrl_sec_cm.3795954008 | Mar 05 01:51:14 PM PST 24 | Mar 05 01:53:00 PM PST 24 | 1105659601 ps | ||
| T324 | /workspace/coverage/default/46.rom_ctrl_smoke.3940580093 | Mar 05 01:51:54 PM PST 24 | Mar 05 01:52:14 PM PST 24 | 1742690820 ps | ||
| T325 | /workspace/coverage/default/18.rom_ctrl_max_throughput_chk.962707614 | Mar 05 01:51:35 PM PST 24 | Mar 05 01:51:41 PM PST 24 | 98914235 ps | ||
| T326 | /workspace/coverage/default/35.rom_ctrl_stress_all_with_rand_reset.2250906252 | Mar 05 01:51:48 PM PST 24 | Mar 05 02:23:21 PM PST 24 | 671864256028 ps | ||
| T327 | /workspace/coverage/default/12.rom_ctrl_kmac_err_chk.3384003688 | Mar 05 01:51:22 PM PST 24 | Mar 05 01:51:31 PM PST 24 | 694415224 ps | ||
| T328 | /workspace/coverage/default/12.rom_ctrl_max_throughput_chk.3607861086 | Mar 05 01:51:26 PM PST 24 | Mar 05 01:51:36 PM PST 24 | 1495228568 ps | ||
| T329 | /workspace/coverage/default/16.rom_ctrl_kmac_err_chk.3429941101 | Mar 05 01:51:32 PM PST 24 | Mar 05 01:51:57 PM PST 24 | 13394466325 ps | ||
| T330 | /workspace/coverage/default/0.rom_ctrl_kmac_err_chk.1349837760 | Mar 05 01:51:04 PM PST 24 | Mar 05 01:51:32 PM PST 24 | 2943289342 ps | ||
| T331 | /workspace/coverage/default/25.rom_ctrl_stress_all.3494971204 | Mar 05 01:51:48 PM PST 24 | Mar 05 01:52:59 PM PST 24 | 35758860675 ps | ||
| T332 | /workspace/coverage/default/48.rom_ctrl_kmac_err_chk.856411753 | Mar 05 01:51:54 PM PST 24 | Mar 05 01:52:29 PM PST 24 | 4662869399 ps | ||
| T333 | /workspace/coverage/default/27.rom_ctrl_alert_test.1052742637 | Mar 05 01:51:28 PM PST 24 | Mar 05 01:51:37 PM PST 24 | 3545433152 ps | ||
| T334 | /workspace/coverage/default/26.rom_ctrl_alert_test.1550416101 | Mar 05 01:51:42 PM PST 24 | Mar 05 01:51:57 PM PST 24 | 6715308359 ps | ||
| T335 | /workspace/coverage/default/36.rom_ctrl_max_throughput_chk.491855528 | Mar 05 01:51:36 PM PST 24 | Mar 05 01:51:43 PM PST 24 | 271224463 ps | ||
| T336 | /workspace/coverage/default/17.rom_ctrl_smoke.2149213787 | Mar 05 01:51:28 PM PST 24 | Mar 05 01:51:50 PM PST 24 | 1959727552 ps | ||
| T337 | /workspace/coverage/default/10.rom_ctrl_alert_test.4252679599 | Mar 05 01:51:19 PM PST 24 | Mar 05 01:51:35 PM PST 24 | 7347836053 ps | ||
| T338 | /workspace/coverage/default/43.rom_ctrl_stress_all.1457795005 | Mar 05 01:51:58 PM PST 24 | Mar 05 01:52:17 PM PST 24 | 3996543649 ps | ||
| T339 | /workspace/coverage/default/31.rom_ctrl_alert_test.68998248 | Mar 05 01:51:40 PM PST 24 | Mar 05 01:51:46 PM PST 24 | 347653026 ps | ||
| T340 | /workspace/coverage/default/49.rom_ctrl_stress_all.559235212 | Mar 05 01:51:50 PM PST 24 | Mar 05 01:52:08 PM PST 24 | 1153232524 ps | ||
| T341 | /workspace/coverage/default/41.rom_ctrl_kmac_err_chk.466729569 | Mar 05 01:51:35 PM PST 24 | Mar 05 01:51:45 PM PST 24 | 594379720 ps | ||
| T342 | /workspace/coverage/default/10.rom_ctrl_corrupt_sig_fatal_chk.2974327859 | Mar 05 01:51:35 PM PST 24 | Mar 05 01:55:38 PM PST 24 | 59114970205 ps | ||
| T343 | /workspace/coverage/default/40.rom_ctrl_alert_test.864033151 | Mar 05 01:51:38 PM PST 24 | Mar 05 01:51:49 PM PST 24 | 4401044823 ps | ||
| T344 | /workspace/coverage/default/17.rom_ctrl_kmac_err_chk.2102975161 | Mar 05 01:51:25 PM PST 24 | Mar 05 01:51:46 PM PST 24 | 1833152653 ps | ||
| T345 | /workspace/coverage/default/41.rom_ctrl_stress_all.1938325282 | Mar 05 01:51:48 PM PST 24 | Mar 05 01:52:19 PM PST 24 | 2866970810 ps | ||
| T346 | /workspace/coverage/default/45.rom_ctrl_alert_test.2135420880 | Mar 05 01:51:47 PM PST 24 | Mar 05 01:52:04 PM PST 24 | 4034745360 ps | ||
| T347 | /workspace/coverage/default/6.rom_ctrl_smoke.1590334153 | Mar 05 01:51:23 PM PST 24 | Mar 05 01:51:33 PM PST 24 | 381146357 ps | ||
| T348 | /workspace/coverage/default/41.rom_ctrl_max_throughput_chk.47687011 | Mar 05 01:51:43 PM PST 24 | Mar 05 01:51:55 PM PST 24 | 1161442218 ps | ||
| T349 | /workspace/coverage/default/19.rom_ctrl_stress_all_with_rand_reset.2682891766 | Mar 05 01:51:24 PM PST 24 | Mar 05 02:08:56 PM PST 24 | 14333892154 ps | ||
| T350 | /workspace/coverage/default/23.rom_ctrl_kmac_err_chk.3268339285 | Mar 05 01:51:38 PM PST 24 | Mar 05 01:51:48 PM PST 24 | 171843205 ps | ||
| T351 | /workspace/coverage/default/12.rom_ctrl_corrupt_sig_fatal_chk.4229372990 | Mar 05 01:51:11 PM PST 24 | Mar 05 01:52:08 PM PST 24 | 4013727952 ps | ||
| T352 | /workspace/coverage/default/9.rom_ctrl_stress_all.379497400 | Mar 05 01:51:29 PM PST 24 | Mar 05 01:52:17 PM PST 24 | 13230109451 ps | ||
| T353 | /workspace/coverage/default/41.rom_ctrl_alert_test.3974652864 | Mar 05 01:51:45 PM PST 24 | Mar 05 01:51:49 PM PST 24 | 334067228 ps | ||
| T354 | /workspace/coverage/default/28.rom_ctrl_kmac_err_chk.3245471849 | Mar 05 01:51:24 PM PST 24 | Mar 05 01:51:33 PM PST 24 | 334148509 ps | ||
| T355 | /workspace/coverage/default/8.rom_ctrl_max_throughput_chk.2493410851 | Mar 05 01:51:14 PM PST 24 | Mar 05 01:51:28 PM PST 24 | 1399669700 ps | ||
| T356 | /workspace/coverage/default/5.rom_ctrl_smoke.2736647539 | Mar 05 01:51:22 PM PST 24 | Mar 05 01:51:52 PM PST 24 | 5039088118 ps | ||
| T357 | /workspace/coverage/default/26.rom_ctrl_stress_all.2097247170 | Mar 05 01:51:32 PM PST 24 | Mar 05 01:52:11 PM PST 24 | 14776760155 ps | ||
| T358 | /workspace/coverage/default/8.rom_ctrl_alert_test.1819203552 | Mar 05 01:51:23 PM PST 24 | Mar 05 01:51:34 PM PST 24 | 4884587715 ps | ||
| T359 | /workspace/coverage/default/9.rom_ctrl_smoke.614883272 | Mar 05 01:50:55 PM PST 24 | Mar 05 01:51:14 PM PST 24 | 3710082627 ps | ||
| T360 | /workspace/coverage/default/48.rom_ctrl_corrupt_sig_fatal_chk.2489163008 | Mar 05 01:51:48 PM PST 24 | Mar 05 01:54:37 PM PST 24 | 64040229402 ps | ||
| T361 | /workspace/coverage/default/0.rom_ctrl_smoke.1684589333 | Mar 05 01:51:08 PM PST 24 | Mar 05 01:51:29 PM PST 24 | 1770642443 ps | ||
| T362 | /workspace/coverage/default/18.rom_ctrl_smoke.1225185599 | Mar 05 01:51:29 PM PST 24 | Mar 05 01:51:52 PM PST 24 | 6497826124 ps | ||
| T363 | /workspace/coverage/default/3.rom_ctrl_smoke.1652354378 | Mar 05 01:51:20 PM PST 24 | Mar 05 01:51:41 PM PST 24 | 7243099683 ps | ||
| T364 | /workspace/coverage/default/29.rom_ctrl_corrupt_sig_fatal_chk.341880616 | Mar 05 01:51:31 PM PST 24 | Mar 05 01:53:02 PM PST 24 | 1654651024 ps | ||
| T365 | /workspace/coverage/default/21.rom_ctrl_smoke.2087878617 | Mar 05 01:51:37 PM PST 24 | Mar 05 01:51:59 PM PST 24 | 30128460246 ps | ||
| T366 | /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_errors.1802147369 | Mar 05 12:43:30 PM PST 24 | Mar 05 12:43:43 PM PST 24 | 638358327 ps | ||
| T367 | /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_partial_access.3285578176 | Mar 05 12:43:18 PM PST 24 | Mar 05 12:43:32 PM PST 24 | 9854199804 ps | ||
| T58 | /workspace/coverage/cover_reg_top/6.rom_ctrl_same_csr_outstanding.1522298514 | Mar 05 12:43:33 PM PST 24 | Mar 05 12:43:39 PM PST 24 | 291182206 ps | ||
| T368 | /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_partial_access.1689763886 | Mar 05 12:43:39 PM PST 24 | Mar 05 12:43:53 PM PST 24 | 2949444117 ps | ||
| T59 | /workspace/coverage/cover_reg_top/6.rom_ctrl_passthru_mem_tl_intg_err.233962704 | Mar 05 12:43:21 PM PST 24 | Mar 05 12:43:56 PM PST 24 | 22104820626 ps | ||
| T54 | /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_intg_err.3765259612 | Mar 05 12:43:21 PM PST 24 | Mar 05 12:44:01 PM PST 24 | 2223353054 ps | ||
| T64 | /workspace/coverage/cover_reg_top/12.rom_ctrl_passthru_mem_tl_intg_err.1031426562 | Mar 05 12:43:24 PM PST 24 | Mar 05 12:44:30 PM PST 24 | 34969308094 ps | ||
| T90 | /workspace/coverage/cover_reg_top/3.rom_ctrl_same_csr_outstanding.2559046275 | Mar 05 12:43:24 PM PST 24 | Mar 05 12:43:40 PM PST 24 | 4219719684 ps | ||
| T91 | /workspace/coverage/cover_reg_top/11.rom_ctrl_same_csr_outstanding.1269862096 | Mar 05 12:43:38 PM PST 24 | Mar 05 12:43:44 PM PST 24 | 366464021 ps | ||
| T369 | /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_walk.3018942324 | Mar 05 12:43:24 PM PST 24 | Mar 05 12:43:39 PM PST 24 | 1770288568 ps | ||
| T65 | /workspace/coverage/cover_reg_top/3.rom_ctrl_passthru_mem_tl_intg_err.658213155 | Mar 05 12:43:23 PM PST 24 | Mar 05 12:43:52 PM PST 24 | 2707237867 ps | ||
| T92 | /workspace/coverage/cover_reg_top/10.rom_ctrl_same_csr_outstanding.1478349102 | Mar 05 12:43:29 PM PST 24 | Mar 05 12:43:36 PM PST 24 | 1343785231 ps | ||
| T370 | /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_errors.409791529 | Mar 05 12:43:24 PM PST 24 | Mar 05 12:43:40 PM PST 24 | 5619930637 ps | ||
| T371 | /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_bit_bash.2513554226 | Mar 05 12:43:07 PM PST 24 | Mar 05 12:43:17 PM PST 24 | 1121702162 ps | ||
| T66 | /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_rw.3129830287 | Mar 05 12:43:28 PM PST 24 | Mar 05 12:43:32 PM PST 24 | 555102265 ps | ||
| T372 | /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_bit_bash.3902940883 | Mar 05 12:43:21 PM PST 24 | Mar 05 12:43:38 PM PST 24 | 3926004745 ps | ||
| T373 | /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_mem_rw_with_rand_reset.3824062761 | Mar 05 12:43:30 PM PST 24 | Mar 05 12:43:38 PM PST 24 | 605542656 ps | ||
| T374 | /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_mem_rw_with_rand_reset.2145881798 | Mar 05 12:43:25 PM PST 24 | Mar 05 12:43:34 PM PST 24 | 2448431583 ps | ||
| T375 | /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_partial_access.4130353215 | Mar 05 12:43:39 PM PST 24 | Mar 05 12:43:54 PM PST 24 | 4488930479 ps | ||
| T93 | /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_rw.2036932267 | Mar 05 12:43:46 PM PST 24 | Mar 05 12:43:57 PM PST 24 | 1146836569 ps | ||
| T55 | /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_intg_err.2089487821 | Mar 05 12:43:37 PM PST 24 | Mar 05 12:44:48 PM PST 24 | 1788790876 ps | ||
| T56 | /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_intg_err.2825306501 | Mar 05 12:43:45 PM PST 24 | Mar 05 12:44:54 PM PST 24 | 381651878 ps | ||
| T94 | /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_rw.3154251654 | Mar 05 12:43:33 PM PST 24 | Mar 05 12:43:49 PM PST 24 | 4017754200 ps | ||
| T376 | /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_mem_rw_with_rand_reset.2577996621 | Mar 05 12:43:31 PM PST 24 | Mar 05 12:43:44 PM PST 24 | 1516487712 ps | ||
| T101 | /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_intg_err.2493041660 | Mar 05 12:43:23 PM PST 24 | Mar 05 12:44:43 PM PST 24 | 1939118497 ps | ||
| T377 | /workspace/coverage/cover_reg_top/9.rom_ctrl_passthru_mem_tl_intg_err.3501262995 | Mar 05 12:43:33 PM PST 24 | Mar 05 12:45:15 PM PST 24 | 12569933160 ps | ||
| T378 | /workspace/coverage/cover_reg_top/15.rom_ctrl_same_csr_outstanding.1521678417 | Mar 05 12:43:34 PM PST 24 | Mar 05 12:43:46 PM PST 24 | 1232750791 ps | ||
| T379 | /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_mem_rw_with_rand_reset.4260119977 | Mar 05 12:43:47 PM PST 24 | Mar 05 12:43:54 PM PST 24 | 297373322 ps | ||
| T380 | /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_mem_rw_with_rand_reset.4273176203 | Mar 05 12:43:35 PM PST 24 | Mar 05 12:43:47 PM PST 24 | 1111703997 ps | ||
| T67 | /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_rw.1268272074 | Mar 05 12:43:13 PM PST 24 | Mar 05 12:43:22 PM PST 24 | 737716265 ps | ||
| T68 | /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_rw.2067929143 | Mar 05 12:43:12 PM PST 24 | Mar 05 12:43:24 PM PST 24 | 5249543754 ps | ||
| T381 | /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_errors.1317382044 | Mar 05 12:43:35 PM PST 24 | Mar 05 12:43:51 PM PST 24 | 1872397162 ps | ||
| T382 | /workspace/coverage/cover_reg_top/12.rom_ctrl_same_csr_outstanding.1324774955 | Mar 05 12:43:42 PM PST 24 | Mar 05 12:43:56 PM PST 24 | 1093919275 ps | ||
| T383 | /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_mem_rw_with_rand_reset.60871344 | Mar 05 12:43:46 PM PST 24 | Mar 05 12:43:56 PM PST 24 | 1673190040 ps | ||
| T384 | /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_rw.1171022563 | Mar 05 12:43:46 PM PST 24 | Mar 05 12:43:55 PM PST 24 | 2940138317 ps | ||
| T385 | /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_mem_rw_with_rand_reset.3049255006 | Mar 05 12:43:25 PM PST 24 | Mar 05 12:43:39 PM PST 24 | 1642051926 ps | ||
| T386 | /workspace/coverage/cover_reg_top/11.rom_ctrl_passthru_mem_tl_intg_err.1894707564 | Mar 05 12:43:28 PM PST 24 | Mar 05 12:43:58 PM PST 24 | 6974095802 ps | ||
| T97 | /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_intg_err.936832224 | Mar 05 12:43:20 PM PST 24 | Mar 05 12:44:39 PM PST 24 | 7967811843 ps | ||
| T69 | /workspace/coverage/cover_reg_top/5.rom_ctrl_same_csr_outstanding.3950037854 | Mar 05 12:43:17 PM PST 24 | Mar 05 12:43:22 PM PST 24 | 333059791 ps | ||
| T70 | /workspace/coverage/cover_reg_top/1.rom_ctrl_passthru_mem_tl_intg_err.4148384378 | Mar 05 12:43:26 PM PST 24 | Mar 05 12:44:47 PM PST 24 | 34142568326 ps | ||
| T387 | /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_errors.4003457217 | Mar 05 12:43:29 PM PST 24 | Mar 05 12:43:48 PM PST 24 | 4438830505 ps | ||
| T388 | /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_mem_rw_with_rand_reset.2275730406 | Mar 05 12:43:24 PM PST 24 | Mar 05 12:43:33 PM PST 24 | 1401918798 ps | ||
| T99 | /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_intg_err.171835632 | Mar 05 12:43:43 PM PST 24 | Mar 05 12:44:30 PM PST 24 | 7583613253 ps | ||
| T71 | /workspace/coverage/cover_reg_top/0.rom_ctrl_same_csr_outstanding.3178617786 | Mar 05 12:43:23 PM PST 24 | Mar 05 12:43:37 PM PST 24 | 1607493143 ps | ||
| T389 | /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_rw.3305296360 | Mar 05 12:43:25 PM PST 24 | Mar 05 12:43:36 PM PST 24 | 1148770225 ps | ||
| T104 | /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_intg_err.4154479168 | Mar 05 12:43:39 PM PST 24 | Mar 05 12:44:54 PM PST 24 | 5743393882 ps | ||
| T102 | /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_intg_err.549608073 | Mar 05 12:43:31 PM PST 24 | Mar 05 12:44:46 PM PST 24 | 495699480 ps | ||
| T79 | /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_aliasing.640052759 | Mar 05 12:43:15 PM PST 24 | Mar 05 12:43:24 PM PST 24 | 576833251 ps | ||
| T390 | /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_errors.2958425270 | Mar 05 12:43:37 PM PST 24 | Mar 05 12:43:49 PM PST 24 | 2818146097 ps | ||
| T391 | /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_partial_access.2903784649 | Mar 05 12:43:23 PM PST 24 | Mar 05 12:43:32 PM PST 24 | 3124754637 ps | ||
| T392 | /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_rw.3571810247 | Mar 05 12:43:18 PM PST 24 | Mar 05 12:43:29 PM PST 24 | 1283020274 ps | ||
| T393 | /workspace/coverage/cover_reg_top/0.rom_ctrl_passthru_mem_tl_intg_err.1752081830 | Mar 05 12:43:26 PM PST 24 | Mar 05 12:43:44 PM PST 24 | 376111276 ps | ||
| T394 | /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_hw_reset.738380020 | Mar 05 12:43:20 PM PST 24 | Mar 05 12:43:37 PM PST 24 | 3087924205 ps | ||
| T395 | /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_errors.3989518467 | Mar 05 12:43:25 PM PST 24 | Mar 05 12:43:37 PM PST 24 | 2205792186 ps | ||
| T396 | /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_intg_err.3728284891 | Mar 05 12:43:47 PM PST 24 | Mar 05 12:44:31 PM PST 24 | 4634178858 ps | ||
| T397 | /workspace/coverage/cover_reg_top/8.rom_ctrl_same_csr_outstanding.2570072206 | Mar 05 12:43:57 PM PST 24 | Mar 05 12:44:03 PM PST 24 | 774937775 ps | ||
| T98 | /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_intg_err.3548516812 | Mar 05 12:43:33 PM PST 24 | Mar 05 12:44:16 PM PST 24 | 6287289412 ps | ||
| T398 | /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_rw.3350949127 | Mar 05 12:43:44 PM PST 24 | Mar 05 12:43:57 PM PST 24 | 2994129397 ps | ||
| T399 | /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_errors.2228644479 | Mar 05 12:43:35 PM PST 24 | Mar 05 12:43:51 PM PST 24 | 2038819942 ps | ||
| T80 | /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_aliasing.2254074907 | Mar 05 12:43:22 PM PST 24 | Mar 05 12:43:32 PM PST 24 | 743474746 ps | ||
| T400 | /workspace/coverage/cover_reg_top/13.rom_ctrl_same_csr_outstanding.2742941360 | Mar 05 12:43:46 PM PST 24 | Mar 05 12:43:59 PM PST 24 | 2785457782 ps | ||
| T81 | /workspace/coverage/cover_reg_top/18.rom_ctrl_passthru_mem_tl_intg_err.2554008889 | Mar 05 12:43:31 PM PST 24 | Mar 05 12:44:09 PM PST 24 | 6762419980 ps | ||
| T82 | /workspace/coverage/cover_reg_top/7.rom_ctrl_passthru_mem_tl_intg_err.3013445177 | Mar 05 12:43:28 PM PST 24 | Mar 05 12:43:57 PM PST 24 | 3154380472 ps | ||
| T88 | /workspace/coverage/cover_reg_top/19.rom_ctrl_passthru_mem_tl_intg_err.906671930 | Mar 05 12:43:45 PM PST 24 | Mar 05 12:44:12 PM PST 24 | 1863685453 ps | ||
| T401 | /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_hw_reset.2884003076 | Mar 05 12:43:33 PM PST 24 | Mar 05 12:43:49 PM PST 24 | 1361942996 ps | ||
| T402 | /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_errors.691310909 | Mar 05 12:43:44 PM PST 24 | Mar 05 12:43:52 PM PST 24 | 442406464 ps | ||
| T403 | /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_mem_rw_with_rand_reset.2158138871 | Mar 05 12:43:30 PM PST 24 | Mar 05 12:43:40 PM PST 24 | 2984305597 ps | ||
| T404 | /workspace/coverage/cover_reg_top/16.rom_ctrl_passthru_mem_tl_intg_err.18973819 | Mar 05 12:43:22 PM PST 24 | Mar 05 12:44:53 PM PST 24 | 15208477368 ps | ||
| T405 | /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_bit_bash.501465375 | Mar 05 12:43:11 PM PST 24 | Mar 05 12:43:21 PM PST 24 | 951539136 ps | ||
| T406 | /workspace/coverage/cover_reg_top/10.rom_ctrl_passthru_mem_tl_intg_err.238248189 | Mar 05 12:43:37 PM PST 24 | Mar 05 12:43:56 PM PST 24 | 913958781 ps | ||
| T407 | /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_rw.4152527697 | Mar 05 12:43:50 PM PST 24 | Mar 05 12:44:04 PM PST 24 | 1858139329 ps | ||
| T408 | /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_hw_reset.610381008 | Mar 05 12:43:30 PM PST 24 | Mar 05 12:43:50 PM PST 24 | 2186543194 ps | ||
| T105 | /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_intg_err.627787823 | Mar 05 12:43:16 PM PST 24 | Mar 05 12:43:59 PM PST 24 | 2123096421 ps | ||
| T100 | /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_intg_err.1481740085 | Mar 05 12:43:21 PM PST 24 | Mar 05 12:44:10 PM PST 24 | 1959983117 ps | ||
| T409 | /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_mem_rw_with_rand_reset.2360986160 | Mar 05 12:43:18 PM PST 24 | Mar 05 12:43:29 PM PST 24 | 1757028347 ps | ||
| T83 | /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_aliasing.3461072096 | Mar 05 12:43:15 PM PST 24 | Mar 05 12:43:20 PM PST 24 | 333300760 ps | ||
| T410 | /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_hw_reset.2896399785 | Mar 05 12:43:37 PM PST 24 | Mar 05 12:43:47 PM PST 24 | 758606866 ps | ||
| T411 | /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_rw.2063821165 | Mar 05 12:43:42 PM PST 24 | Mar 05 12:43:54 PM PST 24 | 2607246307 ps | ||
| T84 | /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_rw.1048496116 | Mar 05 12:43:46 PM PST 24 | Mar 05 12:44:02 PM PST 24 | 4146634457 ps | ||
| T412 | /workspace/coverage/cover_reg_top/16.rom_ctrl_same_csr_outstanding.1246618166 | Mar 05 12:43:48 PM PST 24 | Mar 05 12:44:02 PM PST 24 | 5020784875 ps | ||
| T413 | /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_errors.1274149865 | Mar 05 12:43:38 PM PST 24 | Mar 05 12:43:51 PM PST 24 | 902594769 ps | ||
| T414 | /workspace/coverage/cover_reg_top/4.rom_ctrl_passthru_mem_tl_intg_err.3248460500 | Mar 05 12:43:37 PM PST 24 | Mar 05 12:45:11 PM PST 24 | 46398827069 ps | ||
| T415 | /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_partial_access.809554703 | Mar 05 12:43:05 PM PST 24 | Mar 05 12:43:14 PM PST 24 | 8777769222 ps | ||
| T416 | /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_rw.313901707 | Mar 05 12:43:36 PM PST 24 | Mar 05 12:43:40 PM PST 24 | 86522342 ps | ||
| T107 | /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_intg_err.4158471263 | Mar 05 12:43:23 PM PST 24 | Mar 05 12:44:33 PM PST 24 | 2658294762 ps | ||
| T417 | /workspace/coverage/cover_reg_top/19.rom_ctrl_same_csr_outstanding.3930649434 | Mar 05 12:43:55 PM PST 24 | Mar 05 12:44:11 PM PST 24 | 9553177314 ps | ||
| T418 | /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_errors.3272650660 | Mar 05 12:43:17 PM PST 24 | Mar 05 12:43:36 PM PST 24 | 3278632032 ps | ||
| T419 | /workspace/coverage/cover_reg_top/7.rom_ctrl_same_csr_outstanding.3118190207 | Mar 05 12:43:23 PM PST 24 | Mar 05 12:43:34 PM PST 24 | 5170360523 ps | ||
| T420 | /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_mem_rw_with_rand_reset.54110456 | Mar 05 12:43:26 PM PST 24 | Mar 05 12:43:35 PM PST 24 | 713930523 ps | ||
| T421 | /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_errors.1749902907 | Mar 05 12:43:48 PM PST 24 | Mar 05 12:44:05 PM PST 24 | 8770656169 ps | ||
| T422 | /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_errors.1657668194 | Mar 05 12:43:45 PM PST 24 | Mar 05 12:43:57 PM PST 24 | 2046092959 ps | ||
| T423 | /workspace/coverage/cover_reg_top/9.rom_ctrl_same_csr_outstanding.2847126879 | Mar 05 12:43:27 PM PST 24 | Mar 05 12:43:39 PM PST 24 | 9420299575 ps | ||
| T424 | /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_intg_err.607218728 | Mar 05 12:43:38 PM PST 24 | Mar 05 12:44:21 PM PST 24 | 1205968764 ps | ||
| T425 | /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_mem_rw_with_rand_reset.1378485578 | Mar 05 12:43:52 PM PST 24 | Mar 05 12:44:08 PM PST 24 | 6594423531 ps | ||
| T426 | /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_bit_bash.1112399288 | Mar 05 12:43:17 PM PST 24 | Mar 05 12:43:28 PM PST 24 | 8836022821 ps | ||
| T85 | /workspace/coverage/cover_reg_top/2.rom_ctrl_passthru_mem_tl_intg_err.3623591997 | Mar 05 12:43:36 PM PST 24 | Mar 05 12:45:08 PM PST 24 | 40978573347 ps | ||
| T86 | /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_rw.2000005816 | Mar 05 12:43:39 PM PST 24 | Mar 05 12:43:52 PM PST 24 | 8947766472 ps | ||
| T427 | /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_aliasing.1704525991 | Mar 05 12:43:39 PM PST 24 | Mar 05 12:43:44 PM PST 24 | 498023251 ps | ||
| T428 | /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_errors.4214131018 | Mar 05 12:43:27 PM PST 24 | Mar 05 12:43:41 PM PST 24 | 15901093924 ps | ||
| T429 | /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_mem_rw_with_rand_reset.3894039292 | Mar 05 12:43:40 PM PST 24 | Mar 05 12:43:55 PM PST 24 | 3366214626 ps | ||
| T103 | /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_intg_err.3136943940 | Mar 05 12:43:36 PM PST 24 | Mar 05 12:44:45 PM PST 24 | 1670833000 ps | ||
| T430 | /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_walk.85832686 | Mar 05 12:43:30 PM PST 24 | Mar 05 12:43:46 PM PST 24 | 7571945880 ps | ||
| T431 | /workspace/coverage/cover_reg_top/4.rom_ctrl_same_csr_outstanding.3070446703 | Mar 05 12:43:16 PM PST 24 | Mar 05 12:43:24 PM PST 24 | 3764830820 ps | ||
| T432 | /workspace/coverage/cover_reg_top/1.rom_ctrl_same_csr_outstanding.2010688706 | Mar 05 12:43:26 PM PST 24 | Mar 05 12:43:40 PM PST 24 | 2848261125 ps | ||
| T433 | /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_hw_reset.1967725269 | Mar 05 12:43:21 PM PST 24 | Mar 05 12:43:32 PM PST 24 | 2392970421 ps | ||
| T434 | /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_walk.924289094 | Mar 05 12:43:36 PM PST 24 | Mar 05 12:43:41 PM PST 24 | 168079601 ps | ||
| T435 | /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_errors.1176204678 | Mar 05 12:43:44 PM PST 24 | Mar 05 12:43:55 PM PST 24 | 2838454935 ps | ||
| T436 | /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_mem_rw_with_rand_reset.993955400 | Mar 05 12:44:02 PM PST 24 | Mar 05 12:44:16 PM PST 24 | 1832859405 ps | ||
| T437 | /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_mem_rw_with_rand_reset.2674506202 | Mar 05 12:43:29 PM PST 24 | Mar 05 12:43:35 PM PST 24 | 103469579 ps | ||
| T106 | /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_intg_err.1749101649 | Mar 05 12:43:27 PM PST 24 | Mar 05 12:44:42 PM PST 24 | 1101851108 ps | ||
| T438 | /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_walk.3742121670 | Mar 05 12:43:24 PM PST 24 | Mar 05 12:43:37 PM PST 24 | 1615408371 ps | ||
| T439 | /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_intg_err.3782448043 | Mar 05 12:43:36 PM PST 24 | Mar 05 12:44:15 PM PST 24 | 226602936 ps | ||
| T440 | /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_rw.1493530044 | Mar 05 12:43:41 PM PST 24 | Mar 05 12:43:52 PM PST 24 | 1119904911 ps | ||
| T441 | /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_walk.2560073817 | Mar 05 12:43:32 PM PST 24 | Mar 05 12:43:40 PM PST 24 | 1403711726 ps | ||
| T442 | /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_mem_rw_with_rand_reset.574226630 | Mar 05 12:43:24 PM PST 24 | Mar 05 12:43:38 PM PST 24 | 1637075989 ps | ||
| T443 | /workspace/coverage/cover_reg_top/8.rom_ctrl_passthru_mem_tl_intg_err.2660747704 | Mar 05 12:43:39 PM PST 24 | Mar 05 12:44:15 PM PST 24 | 5291773825 ps | ||
| T444 | /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_errors.2130694738 | Mar 05 12:43:33 PM PST 24 | Mar 05 12:43:39 PM PST 24 | 297735245 ps | ||
| T445 | /workspace/coverage/cover_reg_top/2.rom_ctrl_same_csr_outstanding.1877352740 | Mar 05 12:43:34 PM PST 24 | Mar 05 12:43:47 PM PST 24 | 454958047 ps | ||
| T446 | /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_intg_err.1242475880 | Mar 05 12:43:31 PM PST 24 | Mar 05 12:44:45 PM PST 24 | 4425331552 ps | ||
| T447 | /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_errors.2347823147 | Mar 05 12:43:26 PM PST 24 | Mar 05 12:43:35 PM PST 24 | 163618235 ps | ||
| T448 | /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_rw.3143920681 | Mar 05 12:43:34 PM PST 24 | Mar 05 12:43:39 PM PST 24 | 88927700 ps | ||
| T449 | /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_errors.4062555858 | Mar 05 12:43:42 PM PST 24 | Mar 05 12:43:49 PM PST 24 | 210765059 ps | ||
| T450 | /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_rw.1047283206 | Mar 05 12:43:21 PM PST 24 | Mar 05 12:43:31 PM PST 24 | 4139295143 ps | ||
| T451 | /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_mem_rw_with_rand_reset.591549392 | Mar 05 12:43:41 PM PST 24 | Mar 05 12:43:50 PM PST 24 | 2996311145 ps | ||
| T87 | /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_aliasing.1242873041 | Mar 05 12:43:23 PM PST 24 | Mar 05 12:43:29 PM PST 24 | 2193368342 ps | ||
| T452 | /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_errors.2905494142 | Mar 05 12:43:38 PM PST 24 | Mar 05 12:43:47 PM PST 24 | 6154672325 ps | ||
| T453 | /workspace/coverage/cover_reg_top/14.rom_ctrl_same_csr_outstanding.782970370 | Mar 05 12:43:34 PM PST 24 | Mar 05 12:43:41 PM PST 24 | 98540801 ps | ||
| T454 | /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_errors.157772309 | Mar 05 12:43:45 PM PST 24 | Mar 05 12:44:04 PM PST 24 | 2146227038 ps | ||
| T455 | /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_mem_rw_with_rand_reset.3494503017 | Mar 05 12:43:37 PM PST 24 | Mar 05 12:43:49 PM PST 24 | 2536797475 ps | ||
| T108 | /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_intg_err.2192662999 | Mar 05 12:43:36 PM PST 24 | Mar 05 12:44:53 PM PST 24 | 1706538082 ps | ||
| T89 | /workspace/coverage/cover_reg_top/5.rom_ctrl_passthru_mem_tl_intg_err.2341659233 | Mar 05 12:43:25 PM PST 24 | Mar 05 12:43:52 PM PST 24 | 1995439650 ps | ||
| T456 | /workspace/coverage/cover_reg_top/14.rom_ctrl_passthru_mem_tl_intg_err.753475972 | Mar 05 12:43:39 PM PST 24 | Mar 05 12:44:22 PM PST 24 | 3974070059 ps | ||
| T457 | /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_rw.3358973522 | Mar 05 12:43:34 PM PST 24 | Mar 05 12:43:41 PM PST 24 | 663079506 ps | ||
| T458 | /workspace/coverage/cover_reg_top/17.rom_ctrl_passthru_mem_tl_intg_err.778774878 | Mar 05 12:43:44 PM PST 24 | Mar 05 12:44:35 PM PST 24 | 14437448484 ps | ||
| T459 | /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_mem_rw_with_rand_reset.3978569452 | Mar 05 12:43:55 PM PST 24 | Mar 05 12:44:10 PM PST 24 | 8596580776 ps | ||
| T460 | /workspace/coverage/cover_reg_top/18.rom_ctrl_same_csr_outstanding.3144190437 | Mar 05 12:43:28 PM PST 24 | Mar 05 12:43:32 PM PST 24 | 347840403 ps | ||
| T461 | /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_rw.1150250159 | Mar 05 12:43:49 PM PST 24 | Mar 05 12:44:00 PM PST 24 | 1055892415 ps | ||
| T462 | /workspace/coverage/cover_reg_top/15.rom_ctrl_passthru_mem_tl_intg_err.1864018712 | Mar 05 12:43:22 PM PST 24 | Mar 05 12:43:42 PM PST 24 | 379331223 ps | ||
| T463 | /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_rw.544663575 | Mar 05 12:43:44 PM PST 24 | Mar 05 12:43:51 PM PST 24 | 332685012 ps | ||
| T464 | /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_bit_bash.1507329042 | Mar 05 12:43:23 PM PST 24 | Mar 05 12:43:34 PM PST 24 | 982972434 ps | ||
| T465 | /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_intg_err.2113055777 | Mar 05 12:43:42 PM PST 24 | Mar 05 12:44:22 PM PST 24 | 1449725762 ps | ||
| T466 | /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_errors.218260930 | Mar 05 12:43:33 PM PST 24 | Mar 05 12:43:51 PM PST 24 | 2754758743 ps | ||
| T467 | /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_mem_rw_with_rand_reset.3230077316 | Mar 05 12:43:36 PM PST 24 | Mar 05 12:43:43 PM PST 24 | 1393571311 ps | ||
| T468 | /workspace/coverage/cover_reg_top/13.rom_ctrl_passthru_mem_tl_intg_err.1624901097 | Mar 05 12:43:36 PM PST 24 | Mar 05 12:44:16 PM PST 24 | 13877655154 ps | ||
| T469 | /workspace/coverage/cover_reg_top/17.rom_ctrl_same_csr_outstanding.2561761824 | Mar 05 12:43:45 PM PST 24 | Mar 05 12:43:49 PM PST 24 | 396697145 ps |
| Test location | /workspace/coverage/default/7.rom_ctrl_stress_all_with_rand_reset.1076994866 |
| Short name | T5 |
| Test name | |
| Test status | |
| Simulation time | 43171376485 ps |
| CPU time | 1164.61 seconds |
| Started | Mar 05 01:51:17 PM PST 24 |
| Finished | Mar 05 02:10:42 PM PST 24 |
| Peak memory | 233028 kb |
| Host | smart-9e1bf74b-4dba-40b2-9121-f9c21313b790 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1076994866 -assert nop ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_stress_all_with_rand_reset.1076994866 |
| Directory | /workspace/7.rom_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/3.rom_ctrl_corrupt_sig_fatal_chk.687302498 |
| Short name | T20 |
| Test name | |
| Test status | |
| Simulation time | 54598496543 ps |
| CPU time | 191.32 seconds |
| Started | Mar 05 01:51:12 PM PST 24 |
| Finished | Mar 05 01:54:23 PM PST 24 |
| Peak memory | 237364 kb |
| Host | smart-ce787bda-6774-4118-896a-704b3237cfdb |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=687302498 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt _sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_co rrupt_sig_fatal_chk.687302498 |
| Directory | /workspace/3.rom_ctrl_corrupt_sig_fatal_chk/latest |
| Test location | /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_intg_err.936832224 |
| Short name | T97 |
| Test name | |
| Test status | |
| Simulation time | 7967811843 ps |
| CPU time | 78.64 seconds |
| Started | Mar 05 12:43:20 PM PST 24 |
| Finished | Mar 05 12:44:39 PM PST 24 |
| Peak memory | 210900 kb |
| Host | smart-39d6969f-82f2-4b84-9953-f6c9c0d50c66 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=936832224 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_tl_int g_err.936832224 |
| Directory | /workspace/1.rom_ctrl_tl_intg_err/latest |
| Test location | /workspace/coverage/default/0.rom_ctrl_sec_cm.1952320706 |
| Short name | T30 |
| Test name | |
| Test status | |
| Simulation time | 4525643999 ps |
| CPU time | 109.58 seconds |
| Started | Mar 05 01:51:06 PM PST 24 |
| Finished | Mar 05 01:52:56 PM PST 24 |
| Peak memory | 232560 kb |
| Host | smart-6a6e9534-550f-4998-bc36-03a0e36c53be |
| User | root |
| Command | /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1952320706 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_sec_cm.1952320706 |
| Directory | /workspace/0.rom_ctrl_sec_cm/latest |
| Test location | /workspace/coverage/default/26.rom_ctrl_corrupt_sig_fatal_chk.4243858338 |
| Short name | T3 |
| Test name | |
| Test status | |
| Simulation time | 16443203454 ps |
| CPU time | 143.85 seconds |
| Started | Mar 05 01:51:37 PM PST 24 |
| Finished | Mar 05 01:54:01 PM PST 24 |
| Peak memory | 237392 kb |
| Host | smart-fc677af1-4a26-4e3c-b2dd-a2e23e6fa5a2 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4243858338 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_ corrupt_sig_fatal_chk.4243858338 |
| Directory | /workspace/26.rom_ctrl_corrupt_sig_fatal_chk/latest |
| Test location | /workspace/coverage/cover_reg_top/12.rom_ctrl_passthru_mem_tl_intg_err.1031426562 |
| Short name | T64 |
| Test name | |
| Test status | |
| Simulation time | 34969308094 ps |
| CPU time | 65.06 seconds |
| Started | Mar 05 12:43:24 PM PST 24 |
| Finished | Mar 05 12:44:30 PM PST 24 |
| Peak memory | 210936 kb |
| Host | smart-994a5af7-1da7-4478-8a78-23f922a4c89b |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1031426562 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_p assthru_mem_tl_intg_err.1031426562 |
| Directory | /workspace/12.rom_ctrl_passthru_mem_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_intg_err.1481740085 |
| Short name | T100 |
| Test name | |
| Test status | |
| Simulation time | 1959983117 ps |
| CPU time | 48.28 seconds |
| Started | Mar 05 12:43:21 PM PST 24 |
| Finished | Mar 05 12:44:10 PM PST 24 |
| Peak memory | 211128 kb |
| Host | smart-90c14074-da81-42db-86f3-0986f408e571 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1481740085 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_tl_in tg_err.1481740085 |
| Directory | /workspace/0.rom_ctrl_tl_intg_err/latest |
| Test location | /workspace/coverage/default/13.rom_ctrl_alert_test.2878395703 |
| Short name | T34 |
| Test name | |
| Test status | |
| Simulation time | 3071220009 ps |
| CPU time | 13.57 seconds |
| Started | Mar 05 01:51:20 PM PST 24 |
| Finished | Mar 05 01:51:34 PM PST 24 |
| Peak memory | 210996 kb |
| Host | smart-4032172d-4df0-4160-80ef-053856e396c3 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2878395703 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_alert_test.2878395703 |
| Directory | /workspace/13.rom_ctrl_alert_test/latest |
| Test location | /workspace/coverage/default/11.rom_ctrl_kmac_err_chk.2520106129 |
| Short name | T24 |
| Test name | |
| Test status | |
| Simulation time | 11481392879 ps |
| CPU time | 28.41 seconds |
| Started | Mar 05 01:51:10 PM PST 24 |
| Finished | Mar 05 01:51:38 PM PST 24 |
| Peak memory | 211636 kb |
| Host | smart-2a4f71bc-b72b-4fe5-b371-21f218600fb4 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2520106129 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_kmac_err_chk.2520106129 |
| Directory | /workspace/11.rom_ctrl_kmac_err_chk/latest |
| Test location | /workspace/coverage/default/10.rom_ctrl_kmac_err_chk.159408848 |
| Short name | T269 |
| Test name | |
| Test status | |
| Simulation time | 327528684 ps |
| CPU time | 9.54 seconds |
| Started | Mar 05 01:51:11 PM PST 24 |
| Finished | Mar 05 01:51:21 PM PST 24 |
| Peak memory | 210828 kb |
| Host | smart-42a39315-1cad-446e-b620-d442e821ae15 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=159408848 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_kmac_err_chk.159408848 |
| Directory | /workspace/10.rom_ctrl_kmac_err_chk/latest |
| Test location | /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_intg_err.3136943940 |
| Short name | T103 |
| Test name | |
| Test status | |
| Simulation time | 1670833000 ps |
| CPU time | 68.97 seconds |
| Started | Mar 05 12:43:36 PM PST 24 |
| Finished | Mar 05 12:44:45 PM PST 24 |
| Peak memory | 212356 kb |
| Host | smart-217576c2-0fc5-40a1-80a1-9262a0c0c881 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3136943940 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_tl_i ntg_err.3136943940 |
| Directory | /workspace/14.rom_ctrl_tl_intg_err/latest |
| Test location | /workspace/coverage/default/20.rom_ctrl_smoke.1321318560 |
| Short name | T15 |
| Test name | |
| Test status | |
| Simulation time | 750518542 ps |
| CPU time | 10.16 seconds |
| Started | Mar 05 01:51:35 PM PST 24 |
| Finished | Mar 05 01:51:45 PM PST 24 |
| Peak memory | 212884 kb |
| Host | smart-35526b34-a8ce-4d18-9067-d37745f6e629 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1321318560 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_smoke.1321318560 |
| Directory | /workspace/20.rom_ctrl_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/0.rom_ctrl_passthru_mem_tl_intg_err.1752081830 |
| Short name | T393 |
| Test name | |
| Test status | |
| Simulation time | 376111276 ps |
| CPU time | 18.74 seconds |
| Started | Mar 05 12:43:26 PM PST 24 |
| Finished | Mar 05 12:43:44 PM PST 24 |
| Peak memory | 210872 kb |
| Host | smart-8eb077cd-54af-4a07-84e0-9f1a31bb3eb6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1752081830 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_pa ssthru_mem_tl_intg_err.1752081830 |
| Directory | /workspace/0.rom_ctrl_passthru_mem_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_intg_err.4154479168 |
| Short name | T104 |
| Test name | |
| Test status | |
| Simulation time | 5743393882 ps |
| CPU time | 75.27 seconds |
| Started | Mar 05 12:43:39 PM PST 24 |
| Finished | Mar 05 12:44:54 PM PST 24 |
| Peak memory | 210972 kb |
| Host | smart-e0715904-3c7d-4024-a34f-c0da2cc184d2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4154479168 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_tl_in tg_err.4154479168 |
| Directory | /workspace/3.rom_ctrl_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_aliasing.1704525991 |
| Short name | T427 |
| Test name | |
| Test status | |
| Simulation time | 498023251 ps |
| CPU time | 4.94 seconds |
| Started | Mar 05 12:43:39 PM PST 24 |
| Finished | Mar 05 12:43:44 PM PST 24 |
| Peak memory | 210728 kb |
| Host | smart-3329ce87-8481-4a5e-8440-9efa6acde576 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1704525991 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_alia sing.1704525991 |
| Directory | /workspace/0.rom_ctrl_csr_aliasing/latest |
| Test location | /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_bit_bash.1507329042 |
| Short name | T464 |
| Test name | |
| Test status | |
| Simulation time | 982972434 ps |
| CPU time | 9.93 seconds |
| Started | Mar 05 12:43:23 PM PST 24 |
| Finished | Mar 05 12:43:34 PM PST 24 |
| Peak memory | 210728 kb |
| Host | smart-3eebcbba-3eb6-42ec-a734-6c8f8f34987a |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1507329042 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_bit_ bash.1507329042 |
| Directory | /workspace/0.rom_ctrl_csr_bit_bash/latest |
| Test location | /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_hw_reset.610381008 |
| Short name | T408 |
| Test name | |
| Test status | |
| Simulation time | 2186543194 ps |
| CPU time | 19.87 seconds |
| Started | Mar 05 12:43:30 PM PST 24 |
| Finished | Mar 05 12:43:50 PM PST 24 |
| Peak memory | 210868 kb |
| Host | smart-b27f4f21-db7d-48b2-9064-75347e0bb5cf |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=610381008 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_hw_re set.610381008 |
| Directory | /workspace/0.rom_ctrl_csr_hw_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_mem_rw_with_rand_reset.4273176203 |
| Short name | T380 |
| Test name | |
| Test status | |
| Simulation time | 1111703997 ps |
| CPU time | 11.37 seconds |
| Started | Mar 05 12:43:35 PM PST 24 |
| Finished | Mar 05 12:43:47 PM PST 24 |
| Peak memory | 215148 kb |
| Host | smart-34824757-d188-4688-af76-83773ec76521 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4273176203 -assert nopostproc +UVM_TESTNAME =rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_mem_rw_with_rand_reset.4273176203 |
| Directory | /workspace/0.rom_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_rw.3571810247 |
| Short name | T392 |
| Test name | |
| Test status | |
| Simulation time | 1283020274 ps |
| CPU time | 10.05 seconds |
| Started | Mar 05 12:43:18 PM PST 24 |
| Finished | Mar 05 12:43:29 PM PST 24 |
| Peak memory | 210772 kb |
| Host | smart-6f070c39-c98d-4995-8512-0f5e1053a7b2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3571810247 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_rw.3571810247 |
| Directory | /workspace/0.rom_ctrl_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_partial_access.4130353215 |
| Short name | T375 |
| Test name | |
| Test status | |
| Simulation time | 4488930479 ps |
| CPU time | 10.59 seconds |
| Started | Mar 05 12:43:39 PM PST 24 |
| Finished | Mar 05 12:43:54 PM PST 24 |
| Peak memory | 210848 kb |
| Host | smart-71169ccd-4ad8-4588-99f8-a6fab72aec48 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4130353215 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom _ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctr l_mem_partial_access.4130353215 |
| Directory | /workspace/0.rom_ctrl_mem_partial_access/latest |
| Test location | /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_walk.3742121670 |
| Short name | T438 |
| Test name | |
| Test status | |
| Simulation time | 1615408371 ps |
| CPU time | 12.89 seconds |
| Started | Mar 05 12:43:24 PM PST 24 |
| Finished | Mar 05 12:43:37 PM PST 24 |
| Peak memory | 210668 kb |
| Host | smart-8b3f3a12-b150-4c6f-b708-a286e8162696 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3742121670 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_mem_walk .3742121670 |
| Directory | /workspace/0.rom_ctrl_mem_walk/latest |
| Test location | /workspace/coverage/cover_reg_top/0.rom_ctrl_same_csr_outstanding.3178617786 |
| Short name | T71 |
| Test name | |
| Test status | |
| Simulation time | 1607493143 ps |
| CPU time | 13.38 seconds |
| Started | Mar 05 12:43:23 PM PST 24 |
| Finished | Mar 05 12:43:37 PM PST 24 |
| Peak memory | 210796 kb |
| Host | smart-319fffeb-4d2e-4f17-b5c4-78ddc2729cfc |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3178617786 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_c trl_same_csr_outstanding.3178617786 |
| Directory | /workspace/0.rom_ctrl_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_errors.4003457217 |
| Short name | T387 |
| Test name | |
| Test status | |
| Simulation time | 4438830505 ps |
| CPU time | 13.53 seconds |
| Started | Mar 05 12:43:29 PM PST 24 |
| Finished | Mar 05 12:43:48 PM PST 24 |
| Peak memory | 215404 kb |
| Host | smart-4686a53d-971a-424f-a374-654a9f3f531a |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4003457217 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_tl_errors.4003457217 |
| Directory | /workspace/0.rom_ctrl_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_aliasing.2254074907 |
| Short name | T80 |
| Test name | |
| Test status | |
| Simulation time | 743474746 ps |
| CPU time | 8.93 seconds |
| Started | Mar 05 12:43:22 PM PST 24 |
| Finished | Mar 05 12:43:32 PM PST 24 |
| Peak memory | 210724 kb |
| Host | smart-339dfe9a-cd63-4c21-9154-c3dd1e81a399 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2254074907 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_alia sing.2254074907 |
| Directory | /workspace/1.rom_ctrl_csr_aliasing/latest |
| Test location | /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_bit_bash.3902940883 |
| Short name | T372 |
| Test name | |
| Test status | |
| Simulation time | 3926004745 ps |
| CPU time | 15.98 seconds |
| Started | Mar 05 12:43:21 PM PST 24 |
| Finished | Mar 05 12:43:38 PM PST 24 |
| Peak memory | 210936 kb |
| Host | smart-7dc1f7bd-fac4-4b96-8672-6e7f8d24b253 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3902940883 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_bit_ bash.3902940883 |
| Directory | /workspace/1.rom_ctrl_csr_bit_bash/latest |
| Test location | /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_hw_reset.2896399785 |
| Short name | T410 |
| Test name | |
| Test status | |
| Simulation time | 758606866 ps |
| CPU time | 10.44 seconds |
| Started | Mar 05 12:43:37 PM PST 24 |
| Finished | Mar 05 12:43:47 PM PST 24 |
| Peak memory | 210652 kb |
| Host | smart-8264a9bf-b5ee-4331-8322-63ec9737340a |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2896399785 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_hw_r eset.2896399785 |
| Directory | /workspace/1.rom_ctrl_csr_hw_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_mem_rw_with_rand_reset.2360986160 |
| Short name | T409 |
| Test name | |
| Test status | |
| Simulation time | 1757028347 ps |
| CPU time | 9.82 seconds |
| Started | Mar 05 12:43:18 PM PST 24 |
| Finished | Mar 05 12:43:29 PM PST 24 |
| Peak memory | 214248 kb |
| Host | smart-a918833c-2fa1-49c0-8268-e9a073947f7e |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2360986160 -assert nopostproc +UVM_TESTNAME =rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_mem_rw_with_rand_reset.2360986160 |
| Directory | /workspace/1.rom_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_rw.1047283206 |
| Short name | T450 |
| Test name | |
| Test status | |
| Simulation time | 4139295143 ps |
| CPU time | 9.08 seconds |
| Started | Mar 05 12:43:21 PM PST 24 |
| Finished | Mar 05 12:43:31 PM PST 24 |
| Peak memory | 210916 kb |
| Host | smart-f9344036-93ed-4fa3-9bb0-e41d8c9c3e95 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1047283206 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_rw.1047283206 |
| Directory | /workspace/1.rom_ctrl_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_partial_access.809554703 |
| Short name | T415 |
| Test name | |
| Test status | |
| Simulation time | 8777769222 ps |
| CPU time | 8.89 seconds |
| Started | Mar 05 12:43:05 PM PST 24 |
| Finished | Mar 05 12:43:14 PM PST 24 |
| Peak memory | 210796 kb |
| Host | smart-cd54d8cc-4588-49fa-a6a4-1bf140abd805 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=809554703 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl _mem_partial_access.809554703 |
| Directory | /workspace/1.rom_ctrl_mem_partial_access/latest |
| Test location | /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_walk.85832686 |
| Short name | T430 |
| Test name | |
| Test status | |
| Simulation time | 7571945880 ps |
| CPU time | 15.88 seconds |
| Started | Mar 05 12:43:30 PM PST 24 |
| Finished | Mar 05 12:43:46 PM PST 24 |
| Peak memory | 210808 kb |
| Host | smart-8ffdc544-d801-4937-b9ad-a20589f18c4f |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85832686 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_mem_walk.85832686 |
| Directory | /workspace/1.rom_ctrl_mem_walk/latest |
| Test location | /workspace/coverage/cover_reg_top/1.rom_ctrl_passthru_mem_tl_intg_err.4148384378 |
| Short name | T70 |
| Test name | |
| Test status | |
| Simulation time | 34142568326 ps |
| CPU time | 81.17 seconds |
| Started | Mar 05 12:43:26 PM PST 24 |
| Finished | Mar 05 12:44:47 PM PST 24 |
| Peak memory | 210924 kb |
| Host | smart-55fd8dd6-faaa-4067-9ca7-11a72c3cd4c0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4148384378 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_pa ssthru_mem_tl_intg_err.4148384378 |
| Directory | /workspace/1.rom_ctrl_passthru_mem_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/1.rom_ctrl_same_csr_outstanding.2010688706 |
| Short name | T432 |
| Test name | |
| Test status | |
| Simulation time | 2848261125 ps |
| CPU time | 13.57 seconds |
| Started | Mar 05 12:43:26 PM PST 24 |
| Finished | Mar 05 12:43:40 PM PST 24 |
| Peak memory | 210928 kb |
| Host | smart-cb8d2d9b-9d55-4a7f-97dc-867d00cae42a |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2010688706 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_c trl_same_csr_outstanding.2010688706 |
| Directory | /workspace/1.rom_ctrl_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_errors.3989518467 |
| Short name | T395 |
| Test name | |
| Test status | |
| Simulation time | 2205792186 ps |
| CPU time | 11.8 seconds |
| Started | Mar 05 12:43:25 PM PST 24 |
| Finished | Mar 05 12:43:37 PM PST 24 |
| Peak memory | 215232 kb |
| Host | smart-a6053ba2-dbb1-452a-bdde-4b52d5de70c1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3989518467 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_tl_errors.3989518467 |
| Directory | /workspace/1.rom_ctrl_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_mem_rw_with_rand_reset.2275730406 |
| Short name | T388 |
| Test name | |
| Test status | |
| Simulation time | 1401918798 ps |
| CPU time | 9.01 seconds |
| Started | Mar 05 12:43:24 PM PST 24 |
| Finished | Mar 05 12:43:33 PM PST 24 |
| Peak memory | 213032 kb |
| Host | smart-830ea63b-f8e8-4d8c-9b73-a2c52403d74e |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2275730406 -assert nopostproc +UVM_TESTNAME =rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_csr_mem_rw_with_rand_reset.2275730406 |
| Directory | /workspace/10.rom_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_rw.3143920681 |
| Short name | T448 |
| Test name | |
| Test status | |
| Simulation time | 88927700 ps |
| CPU time | 4.18 seconds |
| Started | Mar 05 12:43:34 PM PST 24 |
| Finished | Mar 05 12:43:39 PM PST 24 |
| Peak memory | 210700 kb |
| Host | smart-5cb73c3c-cee0-49fa-8d31-f471d0cabf80 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3143920681 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_csr_rw.3143920681 |
| Directory | /workspace/10.rom_ctrl_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/10.rom_ctrl_passthru_mem_tl_intg_err.238248189 |
| Short name | T406 |
| Test name | |
| Test status | |
| Simulation time | 913958781 ps |
| CPU time | 18.49 seconds |
| Started | Mar 05 12:43:37 PM PST 24 |
| Finished | Mar 05 12:43:56 PM PST 24 |
| Peak memory | 210820 kb |
| Host | smart-516c602c-ca37-45e1-9922-6f546f152f81 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=238248189 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl _common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_pa ssthru_mem_tl_intg_err.238248189 |
| Directory | /workspace/10.rom_ctrl_passthru_mem_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/10.rom_ctrl_same_csr_outstanding.1478349102 |
| Short name | T92 |
| Test name | |
| Test status | |
| Simulation time | 1343785231 ps |
| CPU time | 7.42 seconds |
| Started | Mar 05 12:43:29 PM PST 24 |
| Finished | Mar 05 12:43:36 PM PST 24 |
| Peak memory | 210800 kb |
| Host | smart-67c1ab6f-f900-4168-ac91-cb54ca874c18 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1478349102 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ ctrl_same_csr_outstanding.1478349102 |
| Directory | /workspace/10.rom_ctrl_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_errors.1657668194 |
| Short name | T422 |
| Test name | |
| Test status | |
| Simulation time | 2046092959 ps |
| CPU time | 11.34 seconds |
| Started | Mar 05 12:43:45 PM PST 24 |
| Finished | Mar 05 12:43:57 PM PST 24 |
| Peak memory | 215224 kb |
| Host | smart-bcf26b92-9ce8-489a-99a1-ae89f9408c25 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1657668194 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_tl_errors.1657668194 |
| Directory | /workspace/10.rom_ctrl_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_intg_err.3728284891 |
| Short name | T396 |
| Test name | |
| Test status | |
| Simulation time | 4634178858 ps |
| CPU time | 43.87 seconds |
| Started | Mar 05 12:43:47 PM PST 24 |
| Finished | Mar 05 12:44:31 PM PST 24 |
| Peak memory | 210920 kb |
| Host | smart-98ae9f53-471c-4fdf-bbd7-ef520ab64adc |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3728284891 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_tl_i ntg_err.3728284891 |
| Directory | /workspace/10.rom_ctrl_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_mem_rw_with_rand_reset.3978569452 |
| Short name | T459 |
| Test name | |
| Test status | |
| Simulation time | 8596580776 ps |
| CPU time | 15.18 seconds |
| Started | Mar 05 12:43:55 PM PST 24 |
| Finished | Mar 05 12:44:10 PM PST 24 |
| Peak memory | 215340 kb |
| Host | smart-134d901d-4d03-43c5-af12-7bd8faf52192 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3978569452 -assert nopostproc +UVM_TESTNAME =rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_csr_mem_rw_with_rand_reset.3978569452 |
| Directory | /workspace/11.rom_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_rw.2036932267 |
| Short name | T93 |
| Test name | |
| Test status | |
| Simulation time | 1146836569 ps |
| CPU time | 11.29 seconds |
| Started | Mar 05 12:43:46 PM PST 24 |
| Finished | Mar 05 12:43:57 PM PST 24 |
| Peak memory | 210748 kb |
| Host | smart-d59b63ba-9f2d-48ee-ba18-a21ea4e7d8ae |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2036932267 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_csr_rw.2036932267 |
| Directory | /workspace/11.rom_ctrl_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/11.rom_ctrl_passthru_mem_tl_intg_err.1894707564 |
| Short name | T386 |
| Test name | |
| Test status | |
| Simulation time | 6974095802 ps |
| CPU time | 30.02 seconds |
| Started | Mar 05 12:43:28 PM PST 24 |
| Finished | Mar 05 12:43:58 PM PST 24 |
| Peak memory | 210912 kb |
| Host | smart-799cc2da-2645-40e4-be54-ff1dbe5144a0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1894707564 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_p assthru_mem_tl_intg_err.1894707564 |
| Directory | /workspace/11.rom_ctrl_passthru_mem_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/11.rom_ctrl_same_csr_outstanding.1269862096 |
| Short name | T91 |
| Test name | |
| Test status | |
| Simulation time | 366464021 ps |
| CPU time | 6.09 seconds |
| Started | Mar 05 12:43:38 PM PST 24 |
| Finished | Mar 05 12:43:44 PM PST 24 |
| Peak memory | 210716 kb |
| Host | smart-8ca8ff46-69ac-4b6b-ade1-6e0fa39ce7d4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1269862096 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ ctrl_same_csr_outstanding.1269862096 |
| Directory | /workspace/11.rom_ctrl_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_errors.218260930 |
| Short name | T466 |
| Test name | |
| Test status | |
| Simulation time | 2754758743 ps |
| CPU time | 17.76 seconds |
| Started | Mar 05 12:43:33 PM PST 24 |
| Finished | Mar 05 12:43:51 PM PST 24 |
| Peak memory | 215416 kb |
| Host | smart-958faf50-6fe0-48fb-8063-a9c933da0229 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=218260930 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_tl_errors.218260930 |
| Directory | /workspace/11.rom_ctrl_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_intg_err.2113055777 |
| Short name | T465 |
| Test name | |
| Test status | |
| Simulation time | 1449725762 ps |
| CPU time | 40.49 seconds |
| Started | Mar 05 12:43:42 PM PST 24 |
| Finished | Mar 05 12:44:22 PM PST 24 |
| Peak memory | 211104 kb |
| Host | smart-30045035-9c55-469d-b90b-e9cde5ca1f8c |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2113055777 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_tl_i ntg_err.2113055777 |
| Directory | /workspace/11.rom_ctrl_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_mem_rw_with_rand_reset.574226630 |
| Short name | T442 |
| Test name | |
| Test status | |
| Simulation time | 1637075989 ps |
| CPU time | 13.85 seconds |
| Started | Mar 05 12:43:24 PM PST 24 |
| Finished | Mar 05 12:43:38 PM PST 24 |
| Peak memory | 213936 kb |
| Host | smart-0b88a44e-5367-4056-8de7-d7b1310addb1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=574226630 -assert nopostproc +UVM_TESTNAME= rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_csr_mem_rw_with_rand_reset.574226630 |
| Directory | /workspace/12.rom_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_rw.2063821165 |
| Short name | T411 |
| Test name | |
| Test status | |
| Simulation time | 2607246307 ps |
| CPU time | 11.69 seconds |
| Started | Mar 05 12:43:42 PM PST 24 |
| Finished | Mar 05 12:43:54 PM PST 24 |
| Peak memory | 210924 kb |
| Host | smart-0215d8c1-e650-42a9-ab5b-ab8a73b6b95b |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2063821165 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_csr_rw.2063821165 |
| Directory | /workspace/12.rom_ctrl_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/12.rom_ctrl_same_csr_outstanding.1324774955 |
| Short name | T382 |
| Test name | |
| Test status | |
| Simulation time | 1093919275 ps |
| CPU time | 13.25 seconds |
| Started | Mar 05 12:43:42 PM PST 24 |
| Finished | Mar 05 12:43:56 PM PST 24 |
| Peak memory | 210796 kb |
| Host | smart-f331ccb0-5434-457d-bf59-f8bdd94bfaaf |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1324774955 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ ctrl_same_csr_outstanding.1324774955 |
| Directory | /workspace/12.rom_ctrl_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_errors.409791529 |
| Short name | T370 |
| Test name | |
| Test status | |
| Simulation time | 5619930637 ps |
| CPU time | 15.56 seconds |
| Started | Mar 05 12:43:24 PM PST 24 |
| Finished | Mar 05 12:43:40 PM PST 24 |
| Peak memory | 215580 kb |
| Host | smart-6b569d30-b27f-4f58-bd2a-b846f1efbfba |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=409791529 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_tl_errors.409791529 |
| Directory | /workspace/12.rom_ctrl_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_intg_err.549608073 |
| Short name | T102 |
| Test name | |
| Test status | |
| Simulation time | 495699480 ps |
| CPU time | 75.37 seconds |
| Started | Mar 05 12:43:31 PM PST 24 |
| Finished | Mar 05 12:44:46 PM PST 24 |
| Peak memory | 212608 kb |
| Host | smart-33495cc7-71b9-40a5-9f5e-6bdc6990225f |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=549608073 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_tl_in tg_err.549608073 |
| Directory | /workspace/12.rom_ctrl_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_mem_rw_with_rand_reset.2145881798 |
| Short name | T374 |
| Test name | |
| Test status | |
| Simulation time | 2448431583 ps |
| CPU time | 8.62 seconds |
| Started | Mar 05 12:43:25 PM PST 24 |
| Finished | Mar 05 12:43:34 PM PST 24 |
| Peak memory | 214544 kb |
| Host | smart-1b846ad3-a76a-49b9-86a8-d28a310e4e49 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2145881798 -assert nopostproc +UVM_TESTNAME =rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_csr_mem_rw_with_rand_reset.2145881798 |
| Directory | /workspace/13.rom_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_rw.2000005816 |
| Short name | T86 |
| Test name | |
| Test status | |
| Simulation time | 8947766472 ps |
| CPU time | 13.35 seconds |
| Started | Mar 05 12:43:39 PM PST 24 |
| Finished | Mar 05 12:43:52 PM PST 24 |
| Peak memory | 210920 kb |
| Host | smart-e59b39fb-c9ad-43fc-8b73-174bc837f61e |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2000005816 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_csr_rw.2000005816 |
| Directory | /workspace/13.rom_ctrl_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/13.rom_ctrl_passthru_mem_tl_intg_err.1624901097 |
| Short name | T468 |
| Test name | |
| Test status | |
| Simulation time | 13877655154 ps |
| CPU time | 39.55 seconds |
| Started | Mar 05 12:43:36 PM PST 24 |
| Finished | Mar 05 12:44:16 PM PST 24 |
| Peak memory | 210860 kb |
| Host | smart-508243ca-1b8c-4edf-b3da-ec47f9293359 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1624901097 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_p assthru_mem_tl_intg_err.1624901097 |
| Directory | /workspace/13.rom_ctrl_passthru_mem_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/13.rom_ctrl_same_csr_outstanding.2742941360 |
| Short name | T400 |
| Test name | |
| Test status | |
| Simulation time | 2785457782 ps |
| CPU time | 12.95 seconds |
| Started | Mar 05 12:43:46 PM PST 24 |
| Finished | Mar 05 12:43:59 PM PST 24 |
| Peak memory | 210924 kb |
| Host | smart-9fc486d6-63d2-4353-8486-8d2203e56cc4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2742941360 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ ctrl_same_csr_outstanding.2742941360 |
| Directory | /workspace/13.rom_ctrl_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_errors.4062555858 |
| Short name | T449 |
| Test name | |
| Test status | |
| Simulation time | 210765059 ps |
| CPU time | 7.69 seconds |
| Started | Mar 05 12:43:42 PM PST 24 |
| Finished | Mar 05 12:43:49 PM PST 24 |
| Peak memory | 213912 kb |
| Host | smart-c95525a6-5953-433b-9222-298d2107e09a |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4062555858 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_tl_errors.4062555858 |
| Directory | /workspace/13.rom_ctrl_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_intg_err.3548516812 |
| Short name | T98 |
| Test name | |
| Test status | |
| Simulation time | 6287289412 ps |
| CPU time | 43.27 seconds |
| Started | Mar 05 12:43:33 PM PST 24 |
| Finished | Mar 05 12:44:16 PM PST 24 |
| Peak memory | 211388 kb |
| Host | smart-4bd95acc-f0d1-4b8f-8177-bf7611e2b29f |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3548516812 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_tl_i ntg_err.3548516812 |
| Directory | /workspace/13.rom_ctrl_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_mem_rw_with_rand_reset.60871344 |
| Short name | T383 |
| Test name | |
| Test status | |
| Simulation time | 1673190040 ps |
| CPU time | 10.36 seconds |
| Started | Mar 05 12:43:46 PM PST 24 |
| Finished | Mar 05 12:43:56 PM PST 24 |
| Peak memory | 214476 kb |
| Host | smart-8ebc9745-790e-4ff1-83f9-cfdffeb992aa |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=60871344 -assert nopostproc +UVM_TESTNAME=r om_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb - cm_log /dev/null -cm_name 14.rom_ctrl_csr_mem_rw_with_rand_reset.60871344 |
| Directory | /workspace/14.rom_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_rw.3358973522 |
| Short name | T457 |
| Test name | |
| Test status | |
| Simulation time | 663079506 ps |
| CPU time | 6.33 seconds |
| Started | Mar 05 12:43:34 PM PST 24 |
| Finished | Mar 05 12:43:41 PM PST 24 |
| Peak memory | 210748 kb |
| Host | smart-4c213259-1c86-43af-bfb5-6b03eae1d11c |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3358973522 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_csr_rw.3358973522 |
| Directory | /workspace/14.rom_ctrl_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/14.rom_ctrl_passthru_mem_tl_intg_err.753475972 |
| Short name | T456 |
| Test name | |
| Test status | |
| Simulation time | 3974070059 ps |
| CPU time | 41.75 seconds |
| Started | Mar 05 12:43:39 PM PST 24 |
| Finished | Mar 05 12:44:22 PM PST 24 |
| Peak memory | 210852 kb |
| Host | smart-c7df1278-8ab1-4d7a-b28f-35376b76acb2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=753475972 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl _common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_pa ssthru_mem_tl_intg_err.753475972 |
| Directory | /workspace/14.rom_ctrl_passthru_mem_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/14.rom_ctrl_same_csr_outstanding.782970370 |
| Short name | T453 |
| Test name | |
| Test status | |
| Simulation time | 98540801 ps |
| CPU time | 6.2 seconds |
| Started | Mar 05 12:43:34 PM PST 24 |
| Finished | Mar 05 12:43:41 PM PST 24 |
| Peak memory | 210744 kb |
| Host | smart-b189e61d-436b-4680-b447-2015eec9a00e |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=782970370 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_c trl_same_csr_outstanding.782970370 |
| Directory | /workspace/14.rom_ctrl_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_errors.4214131018 |
| Short name | T428 |
| Test name | |
| Test status | |
| Simulation time | 15901093924 ps |
| CPU time | 14.39 seconds |
| Started | Mar 05 12:43:27 PM PST 24 |
| Finished | Mar 05 12:43:41 PM PST 24 |
| Peak memory | 215356 kb |
| Host | smart-1aa8536e-d82a-4eba-b8d5-452b05b59ba5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4214131018 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_tl_errors.4214131018 |
| Directory | /workspace/14.rom_ctrl_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_mem_rw_with_rand_reset.4260119977 |
| Short name | T379 |
| Test name | |
| Test status | |
| Simulation time | 297373322 ps |
| CPU time | 6.69 seconds |
| Started | Mar 05 12:43:47 PM PST 24 |
| Finished | Mar 05 12:43:54 PM PST 24 |
| Peak memory | 219032 kb |
| Host | smart-3db013c0-0fd8-4aa4-b82e-1e40d17c2f72 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4260119977 -assert nopostproc +UVM_TESTNAME =rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_csr_mem_rw_with_rand_reset.4260119977 |
| Directory | /workspace/15.rom_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_rw.313901707 |
| Short name | T416 |
| Test name | |
| Test status | |
| Simulation time | 86522342 ps |
| CPU time | 4.1 seconds |
| Started | Mar 05 12:43:36 PM PST 24 |
| Finished | Mar 05 12:43:40 PM PST 24 |
| Peak memory | 210672 kb |
| Host | smart-356bcf57-6c71-40be-a119-3f467168fde3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=313901707 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_csr_rw.313901707 |
| Directory | /workspace/15.rom_ctrl_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/15.rom_ctrl_passthru_mem_tl_intg_err.1864018712 |
| Short name | T462 |
| Test name | |
| Test status | |
| Simulation time | 379331223 ps |
| CPU time | 18.65 seconds |
| Started | Mar 05 12:43:22 PM PST 24 |
| Finished | Mar 05 12:43:42 PM PST 24 |
| Peak memory | 210808 kb |
| Host | smart-3e02d25d-7a6e-4abb-98e0-1dd63bc2d7ae |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1864018712 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_p assthru_mem_tl_intg_err.1864018712 |
| Directory | /workspace/15.rom_ctrl_passthru_mem_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/15.rom_ctrl_same_csr_outstanding.1521678417 |
| Short name | T378 |
| Test name | |
| Test status | |
| Simulation time | 1232750791 ps |
| CPU time | 11.68 seconds |
| Started | Mar 05 12:43:34 PM PST 24 |
| Finished | Mar 05 12:43:46 PM PST 24 |
| Peak memory | 210812 kb |
| Host | smart-e718de3d-4013-4802-9191-bcd41c690253 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1521678417 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ ctrl_same_csr_outstanding.1521678417 |
| Directory | /workspace/15.rom_ctrl_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_errors.2228644479 |
| Short name | T399 |
| Test name | |
| Test status | |
| Simulation time | 2038819942 ps |
| CPU time | 15.92 seconds |
| Started | Mar 05 12:43:35 PM PST 24 |
| Finished | Mar 05 12:43:51 PM PST 24 |
| Peak memory | 214672 kb |
| Host | smart-27461369-258f-40d3-89cd-384340b2958c |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2228644479 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_tl_errors.2228644479 |
| Directory | /workspace/15.rom_ctrl_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_intg_err.3782448043 |
| Short name | T439 |
| Test name | |
| Test status | |
| Simulation time | 226602936 ps |
| CPU time | 38.24 seconds |
| Started | Mar 05 12:43:36 PM PST 24 |
| Finished | Mar 05 12:44:15 PM PST 24 |
| Peak memory | 211132 kb |
| Host | smart-ca87f351-b5a6-48d2-be96-0568db9a3e49 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3782448043 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_tl_i ntg_err.3782448043 |
| Directory | /workspace/15.rom_ctrl_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_mem_rw_with_rand_reset.3824062761 |
| Short name | T373 |
| Test name | |
| Test status | |
| Simulation time | 605542656 ps |
| CPU time | 8.59 seconds |
| Started | Mar 05 12:43:30 PM PST 24 |
| Finished | Mar 05 12:43:38 PM PST 24 |
| Peak memory | 214404 kb |
| Host | smart-3683ef69-19dd-493f-bdb0-d12e680cc260 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3824062761 -assert nopostproc +UVM_TESTNAME =rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_csr_mem_rw_with_rand_reset.3824062761 |
| Directory | /workspace/16.rom_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_rw.3350949127 |
| Short name | T398 |
| Test name | |
| Test status | |
| Simulation time | 2994129397 ps |
| CPU time | 13.06 seconds |
| Started | Mar 05 12:43:44 PM PST 24 |
| Finished | Mar 05 12:43:57 PM PST 24 |
| Peak memory | 210876 kb |
| Host | smart-508defc9-49bc-4c85-9e7a-61f1cbb51451 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3350949127 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_csr_rw.3350949127 |
| Directory | /workspace/16.rom_ctrl_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/16.rom_ctrl_passthru_mem_tl_intg_err.18973819 |
| Short name | T404 |
| Test name | |
| Test status | |
| Simulation time | 15208477368 ps |
| CPU time | 90.45 seconds |
| Started | Mar 05 12:43:22 PM PST 24 |
| Finished | Mar 05 12:44:53 PM PST 24 |
| Peak memory | 210956 kb |
| Host | smart-a5c5215a-02af-4100-9907-8d69ce81c8f8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18973819 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_pas sthru_mem_tl_intg_err.18973819 |
| Directory | /workspace/16.rom_ctrl_passthru_mem_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/16.rom_ctrl_same_csr_outstanding.1246618166 |
| Short name | T412 |
| Test name | |
| Test status | |
| Simulation time | 5020784875 ps |
| CPU time | 13.69 seconds |
| Started | Mar 05 12:43:48 PM PST 24 |
| Finished | Mar 05 12:44:02 PM PST 24 |
| Peak memory | 210984 kb |
| Host | smart-b2e7f094-f282-406f-9263-4c3fe4e16078 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1246618166 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ ctrl_same_csr_outstanding.1246618166 |
| Directory | /workspace/16.rom_ctrl_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_errors.1274149865 |
| Short name | T413 |
| Test name | |
| Test status | |
| Simulation time | 902594769 ps |
| CPU time | 13.66 seconds |
| Started | Mar 05 12:43:38 PM PST 24 |
| Finished | Mar 05 12:43:51 PM PST 24 |
| Peak memory | 215204 kb |
| Host | smart-c8452f7a-ca55-4c49-b4aa-3dfe7a9dc533 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1274149865 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_tl_errors.1274149865 |
| Directory | /workspace/16.rom_ctrl_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_intg_err.1749101649 |
| Short name | T106 |
| Test name | |
| Test status | |
| Simulation time | 1101851108 ps |
| CPU time | 74.43 seconds |
| Started | Mar 05 12:43:27 PM PST 24 |
| Finished | Mar 05 12:44:42 PM PST 24 |
| Peak memory | 210748 kb |
| Host | smart-157f1ed6-c265-4c18-aefc-f19d69c70546 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1749101649 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_tl_i ntg_err.1749101649 |
| Directory | /workspace/16.rom_ctrl_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_mem_rw_with_rand_reset.3230077316 |
| Short name | T467 |
| Test name | |
| Test status | |
| Simulation time | 1393571311 ps |
| CPU time | 7.23 seconds |
| Started | Mar 05 12:43:36 PM PST 24 |
| Finished | Mar 05 12:43:43 PM PST 24 |
| Peak memory | 214796 kb |
| Host | smart-2ea71684-90bf-423a-b04b-17af5153dd02 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3230077316 -assert nopostproc +UVM_TESTNAME =rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_csr_mem_rw_with_rand_reset.3230077316 |
| Directory | /workspace/17.rom_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_rw.1493530044 |
| Short name | T440 |
| Test name | |
| Test status | |
| Simulation time | 1119904911 ps |
| CPU time | 10.79 seconds |
| Started | Mar 05 12:43:41 PM PST 24 |
| Finished | Mar 05 12:43:52 PM PST 24 |
| Peak memory | 210748 kb |
| Host | smart-4f27c0a0-d761-44a5-8b19-b9ea15dca929 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1493530044 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_csr_rw.1493530044 |
| Directory | /workspace/17.rom_ctrl_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/17.rom_ctrl_passthru_mem_tl_intg_err.778774878 |
| Short name | T458 |
| Test name | |
| Test status | |
| Simulation time | 14437448484 ps |
| CPU time | 50.43 seconds |
| Started | Mar 05 12:43:44 PM PST 24 |
| Finished | Mar 05 12:44:35 PM PST 24 |
| Peak memory | 211968 kb |
| Host | smart-41affa2b-992e-48de-932a-d2bb06e3f803 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=778774878 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl _common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_pa ssthru_mem_tl_intg_err.778774878 |
| Directory | /workspace/17.rom_ctrl_passthru_mem_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/17.rom_ctrl_same_csr_outstanding.2561761824 |
| Short name | T469 |
| Test name | |
| Test status | |
| Simulation time | 396697145 ps |
| CPU time | 4.23 seconds |
| Started | Mar 05 12:43:45 PM PST 24 |
| Finished | Mar 05 12:43:49 PM PST 24 |
| Peak memory | 210744 kb |
| Host | smart-d7ac3e73-3ee8-44d3-a4e4-43a22b67d957 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2561761824 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ ctrl_same_csr_outstanding.2561761824 |
| Directory | /workspace/17.rom_ctrl_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_errors.2958425270 |
| Short name | T390 |
| Test name | |
| Test status | |
| Simulation time | 2818146097 ps |
| CPU time | 11.45 seconds |
| Started | Mar 05 12:43:37 PM PST 24 |
| Finished | Mar 05 12:43:49 PM PST 24 |
| Peak memory | 215088 kb |
| Host | smart-0ab5ef76-262b-473a-98ca-4880f6d569e6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2958425270 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_tl_errors.2958425270 |
| Directory | /workspace/17.rom_ctrl_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_intg_err.2825306501 |
| Short name | T56 |
| Test name | |
| Test status | |
| Simulation time | 381651878 ps |
| CPU time | 69.28 seconds |
| Started | Mar 05 12:43:45 PM PST 24 |
| Finished | Mar 05 12:44:54 PM PST 24 |
| Peak memory | 210852 kb |
| Host | smart-738a2923-92aa-4e08-8680-9e9914fee83c |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2825306501 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_tl_i ntg_err.2825306501 |
| Directory | /workspace/17.rom_ctrl_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_mem_rw_with_rand_reset.1378485578 |
| Short name | T425 |
| Test name | |
| Test status | |
| Simulation time | 6594423531 ps |
| CPU time | 15.37 seconds |
| Started | Mar 05 12:43:52 PM PST 24 |
| Finished | Mar 05 12:44:08 PM PST 24 |
| Peak memory | 219084 kb |
| Host | smart-021d37f8-aaa6-4a82-bf93-b9b83f94f30b |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1378485578 -assert nopostproc +UVM_TESTNAME =rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_csr_mem_rw_with_rand_reset.1378485578 |
| Directory | /workspace/18.rom_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_rw.3305296360 |
| Short name | T389 |
| Test name | |
| Test status | |
| Simulation time | 1148770225 ps |
| CPU time | 11.26 seconds |
| Started | Mar 05 12:43:25 PM PST 24 |
| Finished | Mar 05 12:43:36 PM PST 24 |
| Peak memory | 210748 kb |
| Host | smart-3295d0f8-906c-4880-9159-a27671ced826 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3305296360 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_csr_rw.3305296360 |
| Directory | /workspace/18.rom_ctrl_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/18.rom_ctrl_passthru_mem_tl_intg_err.2554008889 |
| Short name | T81 |
| Test name | |
| Test status | |
| Simulation time | 6762419980 ps |
| CPU time | 38.06 seconds |
| Started | Mar 05 12:43:31 PM PST 24 |
| Finished | Mar 05 12:44:09 PM PST 24 |
| Peak memory | 210932 kb |
| Host | smart-6f1ca47d-8b44-4236-aa0d-262fde3ddb28 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2554008889 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_p assthru_mem_tl_intg_err.2554008889 |
| Directory | /workspace/18.rom_ctrl_passthru_mem_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/18.rom_ctrl_same_csr_outstanding.3144190437 |
| Short name | T460 |
| Test name | |
| Test status | |
| Simulation time | 347840403 ps |
| CPU time | 4.26 seconds |
| Started | Mar 05 12:43:28 PM PST 24 |
| Finished | Mar 05 12:43:32 PM PST 24 |
| Peak memory | 210760 kb |
| Host | smart-dfda4193-fb56-432b-8138-0dbae2a50885 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3144190437 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ ctrl_same_csr_outstanding.3144190437 |
| Directory | /workspace/18.rom_ctrl_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_errors.1176204678 |
| Short name | T435 |
| Test name | |
| Test status | |
| Simulation time | 2838454935 ps |
| CPU time | 10.45 seconds |
| Started | Mar 05 12:43:44 PM PST 24 |
| Finished | Mar 05 12:43:55 PM PST 24 |
| Peak memory | 214808 kb |
| Host | smart-fbe0c07c-e128-49f5-a30a-e62e387a52fb |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1176204678 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_tl_errors.1176204678 |
| Directory | /workspace/18.rom_ctrl_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_intg_err.627787823 |
| Short name | T105 |
| Test name | |
| Test status | |
| Simulation time | 2123096421 ps |
| CPU time | 41.72 seconds |
| Started | Mar 05 12:43:16 PM PST 24 |
| Finished | Mar 05 12:43:59 PM PST 24 |
| Peak memory | 211172 kb |
| Host | smart-f7db2d0b-e1f7-415c-a668-fe39e59c33d2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=627787823 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_tl_in tg_err.627787823 |
| Directory | /workspace/18.rom_ctrl_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_mem_rw_with_rand_reset.993955400 |
| Short name | T436 |
| Test name | |
| Test status | |
| Simulation time | 1832859405 ps |
| CPU time | 13.92 seconds |
| Started | Mar 05 12:44:02 PM PST 24 |
| Finished | Mar 05 12:44:16 PM PST 24 |
| Peak memory | 214040 kb |
| Host | smart-88862b7c-4621-48ad-9c84-b8bfdcaf6ba9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=993955400 -assert nopostproc +UVM_TESTNAME= rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_csr_mem_rw_with_rand_reset.993955400 |
| Directory | /workspace/19.rom_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_rw.1048496116 |
| Short name | T84 |
| Test name | |
| Test status | |
| Simulation time | 4146634457 ps |
| CPU time | 15.9 seconds |
| Started | Mar 05 12:43:46 PM PST 24 |
| Finished | Mar 05 12:44:02 PM PST 24 |
| Peak memory | 210952 kb |
| Host | smart-d8ffc26f-5889-476b-9256-0d5cc50cd422 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1048496116 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_csr_rw.1048496116 |
| Directory | /workspace/19.rom_ctrl_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/19.rom_ctrl_passthru_mem_tl_intg_err.906671930 |
| Short name | T88 |
| Test name | |
| Test status | |
| Simulation time | 1863685453 ps |
| CPU time | 26.97 seconds |
| Started | Mar 05 12:43:45 PM PST 24 |
| Finished | Mar 05 12:44:12 PM PST 24 |
| Peak memory | 210780 kb |
| Host | smart-ed3dcb38-c291-405d-bed4-fbf8eaae56db |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=906671930 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl _common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_pa ssthru_mem_tl_intg_err.906671930 |
| Directory | /workspace/19.rom_ctrl_passthru_mem_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/19.rom_ctrl_same_csr_outstanding.3930649434 |
| Short name | T417 |
| Test name | |
| Test status | |
| Simulation time | 9553177314 ps |
| CPU time | 15.96 seconds |
| Started | Mar 05 12:43:55 PM PST 24 |
| Finished | Mar 05 12:44:11 PM PST 24 |
| Peak memory | 210916 kb |
| Host | smart-7a53a757-0b19-4295-855a-53512f472aaf |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3930649434 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ ctrl_same_csr_outstanding.3930649434 |
| Directory | /workspace/19.rom_ctrl_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_errors.1749902907 |
| Short name | T421 |
| Test name | |
| Test status | |
| Simulation time | 8770656169 ps |
| CPU time | 17.62 seconds |
| Started | Mar 05 12:43:48 PM PST 24 |
| Finished | Mar 05 12:44:05 PM PST 24 |
| Peak memory | 215164 kb |
| Host | smart-bb1095b2-e496-4eae-904f-b18809f6a22c |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1749902907 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_tl_errors.1749902907 |
| Directory | /workspace/19.rom_ctrl_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_intg_err.171835632 |
| Short name | T99 |
| Test name | |
| Test status | |
| Simulation time | 7583613253 ps |
| CPU time | 46.81 seconds |
| Started | Mar 05 12:43:43 PM PST 24 |
| Finished | Mar 05 12:44:30 PM PST 24 |
| Peak memory | 211448 kb |
| Host | smart-9517a6da-0dc3-4afa-b4a4-4e8e85588740 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=171835632 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_tl_in tg_err.171835632 |
| Directory | /workspace/19.rom_ctrl_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_aliasing.1242873041 |
| Short name | T87 |
| Test name | |
| Test status | |
| Simulation time | 2193368342 ps |
| CPU time | 6.22 seconds |
| Started | Mar 05 12:43:23 PM PST 24 |
| Finished | Mar 05 12:43:29 PM PST 24 |
| Peak memory | 210856 kb |
| Host | smart-0934e763-8982-4a1f-b841-e649522be8c1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1242873041 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_alia sing.1242873041 |
| Directory | /workspace/2.rom_ctrl_csr_aliasing/latest |
| Test location | /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_bit_bash.501465375 |
| Short name | T405 |
| Test name | |
| Test status | |
| Simulation time | 951539136 ps |
| CPU time | 10.04 seconds |
| Started | Mar 05 12:43:11 PM PST 24 |
| Finished | Mar 05 12:43:21 PM PST 24 |
| Peak memory | 210724 kb |
| Host | smart-98a0e0f8-cd3f-403e-b18f-7584319e1dc0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=501465375 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_bit_b ash.501465375 |
| Directory | /workspace/2.rom_ctrl_csr_bit_bash/latest |
| Test location | /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_hw_reset.1967725269 |
| Short name | T433 |
| Test name | |
| Test status | |
| Simulation time | 2392970421 ps |
| CPU time | 9.99 seconds |
| Started | Mar 05 12:43:21 PM PST 24 |
| Finished | Mar 05 12:43:32 PM PST 24 |
| Peak memory | 210848 kb |
| Host | smart-f49428e9-e60c-4f68-8197-bb3a0746a25c |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1967725269 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_hw_r eset.1967725269 |
| Directory | /workspace/2.rom_ctrl_csr_hw_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_mem_rw_with_rand_reset.54110456 |
| Short name | T420 |
| Test name | |
| Test status | |
| Simulation time | 713930523 ps |
| CPU time | 9.1 seconds |
| Started | Mar 05 12:43:26 PM PST 24 |
| Finished | Mar 05 12:43:35 PM PST 24 |
| Peak memory | 214456 kb |
| Host | smart-8e819016-1eac-47f6-a483-d387224f2a9e |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=54110456 -assert nopostproc +UVM_TESTNAME=r om_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb - cm_log /dev/null -cm_name 2.rom_ctrl_csr_mem_rw_with_rand_reset.54110456 |
| Directory | /workspace/2.rom_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_rw.1268272074 |
| Short name | T67 |
| Test name | |
| Test status | |
| Simulation time | 737716265 ps |
| CPU time | 8.79 seconds |
| Started | Mar 05 12:43:13 PM PST 24 |
| Finished | Mar 05 12:43:22 PM PST 24 |
| Peak memory | 210748 kb |
| Host | smart-f82a7a5a-e88d-4e30-9914-d6146f6ddfe6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1268272074 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_rw.1268272074 |
| Directory | /workspace/2.rom_ctrl_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_partial_access.2903784649 |
| Short name | T391 |
| Test name | |
| Test status | |
| Simulation time | 3124754637 ps |
| CPU time | 8.76 seconds |
| Started | Mar 05 12:43:23 PM PST 24 |
| Finished | Mar 05 12:43:32 PM PST 24 |
| Peak memory | 210812 kb |
| Host | smart-8dd43f90-db4f-4f58-92b3-f6fbab1b0341 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2903784649 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom _ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctr l_mem_partial_access.2903784649 |
| Directory | /workspace/2.rom_ctrl_mem_partial_access/latest |
| Test location | /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_walk.924289094 |
| Short name | T434 |
| Test name | |
| Test status | |
| Simulation time | 168079601 ps |
| CPU time | 4.15 seconds |
| Started | Mar 05 12:43:36 PM PST 24 |
| Finished | Mar 05 12:43:41 PM PST 24 |
| Peak memory | 210676 kb |
| Host | smart-26b25905-3a66-4252-adaf-da21aa995dd8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=924289094 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_mem_walk. 924289094 |
| Directory | /workspace/2.rom_ctrl_mem_walk/latest |
| Test location | /workspace/coverage/cover_reg_top/2.rom_ctrl_passthru_mem_tl_intg_err.3623591997 |
| Short name | T85 |
| Test name | |
| Test status | |
| Simulation time | 40978573347 ps |
| CPU time | 91.61 seconds |
| Started | Mar 05 12:43:36 PM PST 24 |
| Finished | Mar 05 12:45:08 PM PST 24 |
| Peak memory | 210852 kb |
| Host | smart-23ff1c64-cf4d-4ac1-b8f1-0e16a80c301d |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3623591997 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_pa ssthru_mem_tl_intg_err.3623591997 |
| Directory | /workspace/2.rom_ctrl_passthru_mem_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/2.rom_ctrl_same_csr_outstanding.1877352740 |
| Short name | T445 |
| Test name | |
| Test status | |
| Simulation time | 454958047 ps |
| CPU time | 7.21 seconds |
| Started | Mar 05 12:43:34 PM PST 24 |
| Finished | Mar 05 12:43:47 PM PST 24 |
| Peak memory | 210720 kb |
| Host | smart-98df3d42-c70d-4190-8f7c-3b7b853fb0d8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1877352740 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_c trl_same_csr_outstanding.1877352740 |
| Directory | /workspace/2.rom_ctrl_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_errors.1802147369 |
| Short name | T366 |
| Test name | |
| Test status | |
| Simulation time | 638358327 ps |
| CPU time | 12.96 seconds |
| Started | Mar 05 12:43:30 PM PST 24 |
| Finished | Mar 05 12:43:43 PM PST 24 |
| Peak memory | 215280 kb |
| Host | smart-79b5f2bd-4dd8-4b70-b48c-f26b40dd54ad |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1802147369 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_tl_errors.1802147369 |
| Directory | /workspace/2.rom_ctrl_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_intg_err.1242475880 |
| Short name | T446 |
| Test name | |
| Test status | |
| Simulation time | 4425331552 ps |
| CPU time | 73.69 seconds |
| Started | Mar 05 12:43:31 PM PST 24 |
| Finished | Mar 05 12:44:45 PM PST 24 |
| Peak memory | 212876 kb |
| Host | smart-dcf80ec1-92c1-4197-8e59-80c86080ffc4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1242475880 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_tl_in tg_err.1242475880 |
| Directory | /workspace/2.rom_ctrl_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_aliasing.3461072096 |
| Short name | T83 |
| Test name | |
| Test status | |
| Simulation time | 333300760 ps |
| CPU time | 4.22 seconds |
| Started | Mar 05 12:43:15 PM PST 24 |
| Finished | Mar 05 12:43:20 PM PST 24 |
| Peak memory | 210644 kb |
| Host | smart-a572cad8-0fe0-49f9-94c8-595b4d127f14 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3461072096 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_alia sing.3461072096 |
| Directory | /workspace/3.rom_ctrl_csr_aliasing/latest |
| Test location | /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_bit_bash.1112399288 |
| Short name | T426 |
| Test name | |
| Test status | |
| Simulation time | 8836022821 ps |
| CPU time | 10.46 seconds |
| Started | Mar 05 12:43:17 PM PST 24 |
| Finished | Mar 05 12:43:28 PM PST 24 |
| Peak memory | 210764 kb |
| Host | smart-1fb00414-a7a2-4eae-8b6b-64fe44cd2d72 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1112399288 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_bit_ bash.1112399288 |
| Directory | /workspace/3.rom_ctrl_csr_bit_bash/latest |
| Test location | /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_hw_reset.2884003076 |
| Short name | T401 |
| Test name | |
| Test status | |
| Simulation time | 1361942996 ps |
| CPU time | 15.79 seconds |
| Started | Mar 05 12:43:33 PM PST 24 |
| Finished | Mar 05 12:43:49 PM PST 24 |
| Peak memory | 210660 kb |
| Host | smart-be0cebef-2e8f-42ad-b0a7-9a72b7e90c44 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2884003076 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_hw_r eset.2884003076 |
| Directory | /workspace/3.rom_ctrl_csr_hw_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_mem_rw_with_rand_reset.2674506202 |
| Short name | T437 |
| Test name | |
| Test status | |
| Simulation time | 103469579 ps |
| CPU time | 5.35 seconds |
| Started | Mar 05 12:43:29 PM PST 24 |
| Finished | Mar 05 12:43:35 PM PST 24 |
| Peak memory | 214868 kb |
| Host | smart-78d8e92e-b59f-49fe-9e1c-971eb48bbab5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2674506202 -assert nopostproc +UVM_TESTNAME =rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_mem_rw_with_rand_reset.2674506202 |
| Directory | /workspace/3.rom_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_rw.2067929143 |
| Short name | T68 |
| Test name | |
| Test status | |
| Simulation time | 5249543754 ps |
| CPU time | 11.48 seconds |
| Started | Mar 05 12:43:12 PM PST 24 |
| Finished | Mar 05 12:43:24 PM PST 24 |
| Peak memory | 210792 kb |
| Host | smart-42ee6411-6a48-4cb2-b204-01b4ed4624b4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2067929143 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_rw.2067929143 |
| Directory | /workspace/3.rom_ctrl_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_partial_access.1689763886 |
| Short name | T368 |
| Test name | |
| Test status | |
| Simulation time | 2949444117 ps |
| CPU time | 12.87 seconds |
| Started | Mar 05 12:43:39 PM PST 24 |
| Finished | Mar 05 12:43:53 PM PST 24 |
| Peak memory | 210720 kb |
| Host | smart-63dc4930-47c8-461f-854f-52d910901410 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1689763886 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom _ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctr l_mem_partial_access.1689763886 |
| Directory | /workspace/3.rom_ctrl_mem_partial_access/latest |
| Test location | /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_walk.2560073817 |
| Short name | T441 |
| Test name | |
| Test status | |
| Simulation time | 1403711726 ps |
| CPU time | 8.35 seconds |
| Started | Mar 05 12:43:32 PM PST 24 |
| Finished | Mar 05 12:43:40 PM PST 24 |
| Peak memory | 210724 kb |
| Host | smart-eeb287df-8f4a-4283-8c9f-e2995134bfdf |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2560073817 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_mem_walk .2560073817 |
| Directory | /workspace/3.rom_ctrl_mem_walk/latest |
| Test location | /workspace/coverage/cover_reg_top/3.rom_ctrl_passthru_mem_tl_intg_err.658213155 |
| Short name | T65 |
| Test name | |
| Test status | |
| Simulation time | 2707237867 ps |
| CPU time | 27.65 seconds |
| Started | Mar 05 12:43:23 PM PST 24 |
| Finished | Mar 05 12:43:52 PM PST 24 |
| Peak memory | 210848 kb |
| Host | smart-a04d11f8-a620-4d8f-948e-e11ea72ea648 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=658213155 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl _common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_pas sthru_mem_tl_intg_err.658213155 |
| Directory | /workspace/3.rom_ctrl_passthru_mem_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/3.rom_ctrl_same_csr_outstanding.2559046275 |
| Short name | T90 |
| Test name | |
| Test status | |
| Simulation time | 4219719684 ps |
| CPU time | 15.91 seconds |
| Started | Mar 05 12:43:24 PM PST 24 |
| Finished | Mar 05 12:43:40 PM PST 24 |
| Peak memory | 210848 kb |
| Host | smart-2aea0e65-b8d9-4137-834f-1719349d6581 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2559046275 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_c trl_same_csr_outstanding.2559046275 |
| Directory | /workspace/3.rom_ctrl_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_errors.691310909 |
| Short name | T402 |
| Test name | |
| Test status | |
| Simulation time | 442406464 ps |
| CPU time | 8.23 seconds |
| Started | Mar 05 12:43:44 PM PST 24 |
| Finished | Mar 05 12:43:52 PM PST 24 |
| Peak memory | 214456 kb |
| Host | smart-8d9a50fb-8598-45e0-bf4c-4897f40ef607 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=691310909 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_tl_errors.691310909 |
| Directory | /workspace/3.rom_ctrl_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_aliasing.640052759 |
| Short name | T79 |
| Test name | |
| Test status | |
| Simulation time | 576833251 ps |
| CPU time | 7.63 seconds |
| Started | Mar 05 12:43:15 PM PST 24 |
| Finished | Mar 05 12:43:24 PM PST 24 |
| Peak memory | 210660 kb |
| Host | smart-93194013-6af0-4d33-94f4-77e0032e1cab |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=640052759 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_alias ing.640052759 |
| Directory | /workspace/4.rom_ctrl_csr_aliasing/latest |
| Test location | /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_bit_bash.2513554226 |
| Short name | T371 |
| Test name | |
| Test status | |
| Simulation time | 1121702162 ps |
| CPU time | 9.36 seconds |
| Started | Mar 05 12:43:07 PM PST 24 |
| Finished | Mar 05 12:43:17 PM PST 24 |
| Peak memory | 210736 kb |
| Host | smart-bde49d75-4f2e-4fd3-9a77-f1ac1b4c273b |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2513554226 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_bit_ bash.2513554226 |
| Directory | /workspace/4.rom_ctrl_csr_bit_bash/latest |
| Test location | /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_hw_reset.738380020 |
| Short name | T394 |
| Test name | |
| Test status | |
| Simulation time | 3087924205 ps |
| CPU time | 16.4 seconds |
| Started | Mar 05 12:43:20 PM PST 24 |
| Finished | Mar 05 12:43:37 PM PST 24 |
| Peak memory | 210768 kb |
| Host | smart-b1dc6bf1-4268-4d55-9f7f-50bb23576755 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=738380020 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_hw_re set.738380020 |
| Directory | /workspace/4.rom_ctrl_csr_hw_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_mem_rw_with_rand_reset.3049255006 |
| Short name | T385 |
| Test name | |
| Test status | |
| Simulation time | 1642051926 ps |
| CPU time | 13.48 seconds |
| Started | Mar 05 12:43:25 PM PST 24 |
| Finished | Mar 05 12:43:39 PM PST 24 |
| Peak memory | 213880 kb |
| Host | smart-9c5db1bc-387c-4970-a78c-a694af682ced |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3049255006 -assert nopostproc +UVM_TESTNAME =rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_mem_rw_with_rand_reset.3049255006 |
| Directory | /workspace/4.rom_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_rw.3129830287 |
| Short name | T66 |
| Test name | |
| Test status | |
| Simulation time | 555102265 ps |
| CPU time | 4.04 seconds |
| Started | Mar 05 12:43:28 PM PST 24 |
| Finished | Mar 05 12:43:32 PM PST 24 |
| Peak memory | 210760 kb |
| Host | smart-b477eb42-fd55-44c4-9c49-b9b8b0eaf73d |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3129830287 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_rw.3129830287 |
| Directory | /workspace/4.rom_ctrl_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_partial_access.3285578176 |
| Short name | T367 |
| Test name | |
| Test status | |
| Simulation time | 9854199804 ps |
| CPU time | 13.86 seconds |
| Started | Mar 05 12:43:18 PM PST 24 |
| Finished | Mar 05 12:43:32 PM PST 24 |
| Peak memory | 210716 kb |
| Host | smart-0f2cfc10-02f0-4611-8bfe-8facb8856d85 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3285578176 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom _ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctr l_mem_partial_access.3285578176 |
| Directory | /workspace/4.rom_ctrl_mem_partial_access/latest |
| Test location | /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_walk.3018942324 |
| Short name | T369 |
| Test name | |
| Test status | |
| Simulation time | 1770288568 ps |
| CPU time | 14.39 seconds |
| Started | Mar 05 12:43:24 PM PST 24 |
| Finished | Mar 05 12:43:39 PM PST 24 |
| Peak memory | 210580 kb |
| Host | smart-e1abc093-d3ae-4ac3-892b-742872861e51 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3018942324 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_mem_walk .3018942324 |
| Directory | /workspace/4.rom_ctrl_mem_walk/latest |
| Test location | /workspace/coverage/cover_reg_top/4.rom_ctrl_passthru_mem_tl_intg_err.3248460500 |
| Short name | T414 |
| Test name | |
| Test status | |
| Simulation time | 46398827069 ps |
| CPU time | 93.87 seconds |
| Started | Mar 05 12:43:37 PM PST 24 |
| Finished | Mar 05 12:45:11 PM PST 24 |
| Peak memory | 210940 kb |
| Host | smart-fd3a58c2-8d40-4ea3-a6a7-becbc9b07296 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3248460500 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_pa ssthru_mem_tl_intg_err.3248460500 |
| Directory | /workspace/4.rom_ctrl_passthru_mem_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/4.rom_ctrl_same_csr_outstanding.3070446703 |
| Short name | T431 |
| Test name | |
| Test status | |
| Simulation time | 3764830820 ps |
| CPU time | 7.57 seconds |
| Started | Mar 05 12:43:16 PM PST 24 |
| Finished | Mar 05 12:43:24 PM PST 24 |
| Peak memory | 210840 kb |
| Host | smart-7366ff66-b567-4d6a-9116-a76b7ca8d15f |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3070446703 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_c trl_same_csr_outstanding.3070446703 |
| Directory | /workspace/4.rom_ctrl_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_errors.2130694738 |
| Short name | T444 |
| Test name | |
| Test status | |
| Simulation time | 297735245 ps |
| CPU time | 6.43 seconds |
| Started | Mar 05 12:43:33 PM PST 24 |
| Finished | Mar 05 12:43:39 PM PST 24 |
| Peak memory | 214688 kb |
| Host | smart-7d5e5c5c-e9a4-443a-ac21-02e9126d424a |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2130694738 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_tl_errors.2130694738 |
| Directory | /workspace/4.rom_ctrl_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_intg_err.4158471263 |
| Short name | T107 |
| Test name | |
| Test status | |
| Simulation time | 2658294762 ps |
| CPU time | 69.41 seconds |
| Started | Mar 05 12:43:23 PM PST 24 |
| Finished | Mar 05 12:44:33 PM PST 24 |
| Peak memory | 210860 kb |
| Host | smart-e907a093-4854-4330-b5bd-bc9f8fc45f15 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4158471263 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_tl_in tg_err.4158471263 |
| Directory | /workspace/4.rom_ctrl_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_mem_rw_with_rand_reset.3894039292 |
| Short name | T429 |
| Test name | |
| Test status | |
| Simulation time | 3366214626 ps |
| CPU time | 14.95 seconds |
| Started | Mar 05 12:43:40 PM PST 24 |
| Finished | Mar 05 12:43:55 PM PST 24 |
| Peak memory | 215256 kb |
| Host | smart-1112ca00-a02b-4ceb-8ea3-6142cf6cc639 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3894039292 -assert nopostproc +UVM_TESTNAME =rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_csr_mem_rw_with_rand_reset.3894039292 |
| Directory | /workspace/5.rom_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_rw.1150250159 |
| Short name | T461 |
| Test name | |
| Test status | |
| Simulation time | 1055892415 ps |
| CPU time | 10.48 seconds |
| Started | Mar 05 12:43:49 PM PST 24 |
| Finished | Mar 05 12:44:00 PM PST 24 |
| Peak memory | 210652 kb |
| Host | smart-414ce7fa-d5c5-407d-b149-c7eba5f290bf |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1150250159 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_csr_rw.1150250159 |
| Directory | /workspace/5.rom_ctrl_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/5.rom_ctrl_passthru_mem_tl_intg_err.2341659233 |
| Short name | T89 |
| Test name | |
| Test status | |
| Simulation time | 1995439650 ps |
| CPU time | 26.83 seconds |
| Started | Mar 05 12:43:25 PM PST 24 |
| Finished | Mar 05 12:43:52 PM PST 24 |
| Peak memory | 210812 kb |
| Host | smart-91bbbe99-29cd-4850-880a-17fe210ff0e9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2341659233 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_pa ssthru_mem_tl_intg_err.2341659233 |
| Directory | /workspace/5.rom_ctrl_passthru_mem_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/5.rom_ctrl_same_csr_outstanding.3950037854 |
| Short name | T69 |
| Test name | |
| Test status | |
| Simulation time | 333059791 ps |
| CPU time | 4.29 seconds |
| Started | Mar 05 12:43:17 PM PST 24 |
| Finished | Mar 05 12:43:22 PM PST 24 |
| Peak memory | 210760 kb |
| Host | smart-bb0bb5fe-1e36-41b7-ab0a-297611820417 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3950037854 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_c trl_same_csr_outstanding.3950037854 |
| Directory | /workspace/5.rom_ctrl_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_errors.3272650660 |
| Short name | T418 |
| Test name | |
| Test status | |
| Simulation time | 3278632032 ps |
| CPU time | 17.91 seconds |
| Started | Mar 05 12:43:17 PM PST 24 |
| Finished | Mar 05 12:43:36 PM PST 24 |
| Peak memory | 215276 kb |
| Host | smart-dba4aa79-d1dd-4644-a2f0-ed23bfe37963 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3272650660 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_tl_errors.3272650660 |
| Directory | /workspace/5.rom_ctrl_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_intg_err.2493041660 |
| Short name | T101 |
| Test name | |
| Test status | |
| Simulation time | 1939118497 ps |
| CPU time | 80.19 seconds |
| Started | Mar 05 12:43:23 PM PST 24 |
| Finished | Mar 05 12:44:43 PM PST 24 |
| Peak memory | 210840 kb |
| Host | smart-574ca96d-47fa-4f3d-982e-f25c27227ccc |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2493041660 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_tl_in tg_err.2493041660 |
| Directory | /workspace/5.rom_ctrl_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_mem_rw_with_rand_reset.591549392 |
| Short name | T451 |
| Test name | |
| Test status | |
| Simulation time | 2996311145 ps |
| CPU time | 8.96 seconds |
| Started | Mar 05 12:43:41 PM PST 24 |
| Finished | Mar 05 12:43:50 PM PST 24 |
| Peak memory | 213744 kb |
| Host | smart-6692bebd-f061-4a72-b719-ce00afcd0b0c |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=591549392 -assert nopostproc +UVM_TESTNAME= rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_csr_mem_rw_with_rand_reset.591549392 |
| Directory | /workspace/6.rom_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_rw.1171022563 |
| Short name | T384 |
| Test name | |
| Test status | |
| Simulation time | 2940138317 ps |
| CPU time | 8.84 seconds |
| Started | Mar 05 12:43:46 PM PST 24 |
| Finished | Mar 05 12:43:55 PM PST 24 |
| Peak memory | 210872 kb |
| Host | smart-5eebe3ae-0c00-40c1-b527-4bcdbaf42678 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1171022563 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_csr_rw.1171022563 |
| Directory | /workspace/6.rom_ctrl_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/6.rom_ctrl_passthru_mem_tl_intg_err.233962704 |
| Short name | T59 |
| Test name | |
| Test status | |
| Simulation time | 22104820626 ps |
| CPU time | 34.61 seconds |
| Started | Mar 05 12:43:21 PM PST 24 |
| Finished | Mar 05 12:43:56 PM PST 24 |
| Peak memory | 210952 kb |
| Host | smart-0a9a24da-a1b2-4bde-94b5-eb7210e28bd3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=233962704 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl _common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_pas sthru_mem_tl_intg_err.233962704 |
| Directory | /workspace/6.rom_ctrl_passthru_mem_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/6.rom_ctrl_same_csr_outstanding.1522298514 |
| Short name | T58 |
| Test name | |
| Test status | |
| Simulation time | 291182206 ps |
| CPU time | 6.32 seconds |
| Started | Mar 05 12:43:33 PM PST 24 |
| Finished | Mar 05 12:43:39 PM PST 24 |
| Peak memory | 210880 kb |
| Host | smart-cce9e9c8-0950-4b78-9e1c-0352ba2a9b85 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1522298514 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_c trl_same_csr_outstanding.1522298514 |
| Directory | /workspace/6.rom_ctrl_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_errors.2905494142 |
| Short name | T452 |
| Test name | |
| Test status | |
| Simulation time | 6154672325 ps |
| CPU time | 8.61 seconds |
| Started | Mar 05 12:43:38 PM PST 24 |
| Finished | Mar 05 12:43:47 PM PST 24 |
| Peak memory | 215416 kb |
| Host | smart-f99482d0-5e31-4522-9568-55b3900b3b10 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2905494142 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_tl_errors.2905494142 |
| Directory | /workspace/6.rom_ctrl_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_intg_err.3765259612 |
| Short name | T54 |
| Test name | |
| Test status | |
| Simulation time | 2223353054 ps |
| CPU time | 39.1 seconds |
| Started | Mar 05 12:43:21 PM PST 24 |
| Finished | Mar 05 12:44:01 PM PST 24 |
| Peak memory | 211496 kb |
| Host | smart-60726cc7-a263-4abb-8d83-20fc7ad22b76 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3765259612 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_tl_in tg_err.3765259612 |
| Directory | /workspace/6.rom_ctrl_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_mem_rw_with_rand_reset.3494503017 |
| Short name | T455 |
| Test name | |
| Test status | |
| Simulation time | 2536797475 ps |
| CPU time | 11.88 seconds |
| Started | Mar 05 12:43:37 PM PST 24 |
| Finished | Mar 05 12:43:49 PM PST 24 |
| Peak memory | 212496 kb |
| Host | smart-fdcb84dd-2580-404c-acf1-5454a98064cc |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3494503017 -assert nopostproc +UVM_TESTNAME =rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_csr_mem_rw_with_rand_reset.3494503017 |
| Directory | /workspace/7.rom_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_rw.544663575 |
| Short name | T463 |
| Test name | |
| Test status | |
| Simulation time | 332685012 ps |
| CPU time | 6.43 seconds |
| Started | Mar 05 12:43:44 PM PST 24 |
| Finished | Mar 05 12:43:51 PM PST 24 |
| Peak memory | 210752 kb |
| Host | smart-16444690-24dc-4917-9337-9fe4065d77a1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=544663575 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_csr_rw.544663575 |
| Directory | /workspace/7.rom_ctrl_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/7.rom_ctrl_passthru_mem_tl_intg_err.3013445177 |
| Short name | T82 |
| Test name | |
| Test status | |
| Simulation time | 3154380472 ps |
| CPU time | 28.21 seconds |
| Started | Mar 05 12:43:28 PM PST 24 |
| Finished | Mar 05 12:43:57 PM PST 24 |
| Peak memory | 210940 kb |
| Host | smart-8cb7ee41-429e-4af9-8d56-ac8c75ffe5c2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3013445177 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_pa ssthru_mem_tl_intg_err.3013445177 |
| Directory | /workspace/7.rom_ctrl_passthru_mem_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/7.rom_ctrl_same_csr_outstanding.3118190207 |
| Short name | T419 |
| Test name | |
| Test status | |
| Simulation time | 5170360523 ps |
| CPU time | 11.02 seconds |
| Started | Mar 05 12:43:23 PM PST 24 |
| Finished | Mar 05 12:43:34 PM PST 24 |
| Peak memory | 210824 kb |
| Host | smart-5c7707d9-08f5-4511-8a19-d7a584f0de08 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3118190207 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_c trl_same_csr_outstanding.3118190207 |
| Directory | /workspace/7.rom_ctrl_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_errors.1317382044 |
| Short name | T381 |
| Test name | |
| Test status | |
| Simulation time | 1872397162 ps |
| CPU time | 16.22 seconds |
| Started | Mar 05 12:43:35 PM PST 24 |
| Finished | Mar 05 12:43:51 PM PST 24 |
| Peak memory | 213880 kb |
| Host | smart-f5fcd2aa-7ee9-42ba-a939-4110f418c5a0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1317382044 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_tl_errors.1317382044 |
| Directory | /workspace/7.rom_ctrl_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_intg_err.607218728 |
| Short name | T424 |
| Test name | |
| Test status | |
| Simulation time | 1205968764 ps |
| CPU time | 43.09 seconds |
| Started | Mar 05 12:43:38 PM PST 24 |
| Finished | Mar 05 12:44:21 PM PST 24 |
| Peak memory | 212228 kb |
| Host | smart-4e2a13ca-03e0-4006-bdb5-d28c26be6637 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=607218728 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_tl_int g_err.607218728 |
| Directory | /workspace/7.rom_ctrl_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_mem_rw_with_rand_reset.2577996621 |
| Short name | T376 |
| Test name | |
| Test status | |
| Simulation time | 1516487712 ps |
| CPU time | 13.38 seconds |
| Started | Mar 05 12:43:31 PM PST 24 |
| Finished | Mar 05 12:43:44 PM PST 24 |
| Peak memory | 214256 kb |
| Host | smart-7d37644b-dca0-467f-a227-14de97aaf94f |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2577996621 -assert nopostproc +UVM_TESTNAME =rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_csr_mem_rw_with_rand_reset.2577996621 |
| Directory | /workspace/8.rom_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_rw.3154251654 |
| Short name | T94 |
| Test name | |
| Test status | |
| Simulation time | 4017754200 ps |
| CPU time | 15.46 seconds |
| Started | Mar 05 12:43:33 PM PST 24 |
| Finished | Mar 05 12:43:49 PM PST 24 |
| Peak memory | 210896 kb |
| Host | smart-8121ae76-9a7c-49ef-b0ca-421d29ca75d7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3154251654 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_csr_rw.3154251654 |
| Directory | /workspace/8.rom_ctrl_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/8.rom_ctrl_passthru_mem_tl_intg_err.2660747704 |
| Short name | T443 |
| Test name | |
| Test status | |
| Simulation time | 5291773825 ps |
| CPU time | 34.82 seconds |
| Started | Mar 05 12:43:39 PM PST 24 |
| Finished | Mar 05 12:44:15 PM PST 24 |
| Peak memory | 210928 kb |
| Host | smart-8577610c-c4ed-4cd6-801d-549ab352f1bd |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2660747704 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_pa ssthru_mem_tl_intg_err.2660747704 |
| Directory | /workspace/8.rom_ctrl_passthru_mem_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/8.rom_ctrl_same_csr_outstanding.2570072206 |
| Short name | T397 |
| Test name | |
| Test status | |
| Simulation time | 774937775 ps |
| CPU time | 5.03 seconds |
| Started | Mar 05 12:43:57 PM PST 24 |
| Finished | Mar 05 12:44:03 PM PST 24 |
| Peak memory | 210640 kb |
| Host | smart-16611068-89e3-452f-9e35-a67d955051c7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2570072206 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_c trl_same_csr_outstanding.2570072206 |
| Directory | /workspace/8.rom_ctrl_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_errors.157772309 |
| Short name | T454 |
| Test name | |
| Test status | |
| Simulation time | 2146227038 ps |
| CPU time | 19.7 seconds |
| Started | Mar 05 12:43:45 PM PST 24 |
| Finished | Mar 05 12:44:04 PM PST 24 |
| Peak memory | 215100 kb |
| Host | smart-1574da8b-bf96-4dd8-a43b-626b69bc9235 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=157772309 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_tl_errors.157772309 |
| Directory | /workspace/8.rom_ctrl_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_intg_err.2089487821 |
| Short name | T55 |
| Test name | |
| Test status | |
| Simulation time | 1788790876 ps |
| CPU time | 70.52 seconds |
| Started | Mar 05 12:43:37 PM PST 24 |
| Finished | Mar 05 12:44:48 PM PST 24 |
| Peak memory | 210796 kb |
| Host | smart-9422cfaf-8122-4587-91be-889df9a58f28 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2089487821 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_tl_in tg_err.2089487821 |
| Directory | /workspace/8.rom_ctrl_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_mem_rw_with_rand_reset.2158138871 |
| Short name | T403 |
| Test name | |
| Test status | |
| Simulation time | 2984305597 ps |
| CPU time | 9.49 seconds |
| Started | Mar 05 12:43:30 PM PST 24 |
| Finished | Mar 05 12:43:40 PM PST 24 |
| Peak memory | 214504 kb |
| Host | smart-4f20d389-b512-4e0a-af47-962d3f4f719a |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2158138871 -assert nopostproc +UVM_TESTNAME =rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_csr_mem_rw_with_rand_reset.2158138871 |
| Directory | /workspace/9.rom_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_rw.4152527697 |
| Short name | T407 |
| Test name | |
| Test status | |
| Simulation time | 1858139329 ps |
| CPU time | 14.31 seconds |
| Started | Mar 05 12:43:50 PM PST 24 |
| Finished | Mar 05 12:44:04 PM PST 24 |
| Peak memory | 210748 kb |
| Host | smart-35e3c9f5-d578-4ea0-bbfd-135d09e4e116 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4152527697 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_csr_rw.4152527697 |
| Directory | /workspace/9.rom_ctrl_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/9.rom_ctrl_passthru_mem_tl_intg_err.3501262995 |
| Short name | T377 |
| Test name | |
| Test status | |
| Simulation time | 12569933160 ps |
| CPU time | 101.13 seconds |
| Started | Mar 05 12:43:33 PM PST 24 |
| Finished | Mar 05 12:45:15 PM PST 24 |
| Peak memory | 210932 kb |
| Host | smart-130f7973-5c22-4ee0-b201-f18e4a11ed12 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3501262995 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_pa ssthru_mem_tl_intg_err.3501262995 |
| Directory | /workspace/9.rom_ctrl_passthru_mem_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/9.rom_ctrl_same_csr_outstanding.2847126879 |
| Short name | T423 |
| Test name | |
| Test status | |
| Simulation time | 9420299575 ps |
| CPU time | 11.85 seconds |
| Started | Mar 05 12:43:27 PM PST 24 |
| Finished | Mar 05 12:43:39 PM PST 24 |
| Peak memory | 210900 kb |
| Host | smart-5b18cdf6-b779-486f-a8b2-5f65382e7c03 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2847126879 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_c trl_same_csr_outstanding.2847126879 |
| Directory | /workspace/9.rom_ctrl_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_errors.2347823147 |
| Short name | T447 |
| Test name | |
| Test status | |
| Simulation time | 163618235 ps |
| CPU time | 8.76 seconds |
| Started | Mar 05 12:43:26 PM PST 24 |
| Finished | Mar 05 12:43:35 PM PST 24 |
| Peak memory | 213976 kb |
| Host | smart-a7f3c64a-ed70-4dc4-a87b-5f9d548199bb |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2347823147 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_tl_errors.2347823147 |
| Directory | /workspace/9.rom_ctrl_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_intg_err.2192662999 |
| Short name | T108 |
| Test name | |
| Test status | |
| Simulation time | 1706538082 ps |
| CPU time | 76.06 seconds |
| Started | Mar 05 12:43:36 PM PST 24 |
| Finished | Mar 05 12:44:53 PM PST 24 |
| Peak memory | 210800 kb |
| Host | smart-231d8c34-bea9-4e97-94ad-7e879ca85c8b |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2192662999 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_tl_in tg_err.2192662999 |
| Directory | /workspace/9.rom_ctrl_tl_intg_err/latest |
| Test location | /workspace/coverage/default/0.rom_ctrl_alert_test.252832356 |
| Short name | T191 |
| Test name | |
| Test status | |
| Simulation time | 1160212837 ps |
| CPU time | 8.41 seconds |
| Started | Mar 05 01:51:06 PM PST 24 |
| Finished | Mar 05 01:51:14 PM PST 24 |
| Peak memory | 211044 kb |
| Host | smart-a98f2a57-6999-470b-825a-46323c17fc2f |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=252832356 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_alert_test.252832356 |
| Directory | /workspace/0.rom_ctrl_alert_test/latest |
| Test location | /workspace/coverage/default/0.rom_ctrl_corrupt_sig_fatal_chk.1736852120 |
| Short name | T29 |
| Test name | |
| Test status | |
| Simulation time | 35696395444 ps |
| CPU time | 191.05 seconds |
| Started | Mar 05 01:51:07 PM PST 24 |
| Finished | Mar 05 01:54:18 PM PST 24 |
| Peak memory | 224564 kb |
| Host | smart-529ac46a-4603-4eaf-870e-b958bf9053fa |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1736852120 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_c orrupt_sig_fatal_chk.1736852120 |
| Directory | /workspace/0.rom_ctrl_corrupt_sig_fatal_chk/latest |
| Test location | /workspace/coverage/default/0.rom_ctrl_kmac_err_chk.1349837760 |
| Short name | T330 |
| Test name | |
| Test status | |
| Simulation time | 2943289342 ps |
| CPU time | 28.23 seconds |
| Started | Mar 05 01:51:04 PM PST 24 |
| Finished | Mar 05 01:51:32 PM PST 24 |
| Peak memory | 211392 kb |
| Host | smart-0bd688cb-097c-4aa0-a197-3c47e8a9ccc6 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1349837760 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_kmac_err_chk.1349837760 |
| Directory | /workspace/0.rom_ctrl_kmac_err_chk/latest |
| Test location | /workspace/coverage/default/0.rom_ctrl_max_throughput_chk.2574531003 |
| Short name | T168 |
| Test name | |
| Test status | |
| Simulation time | 2207724419 ps |
| CPU time | 17.21 seconds |
| Started | Mar 05 01:50:59 PM PST 24 |
| Finished | Mar 05 01:51:16 PM PST 24 |
| Peak memory | 210940 kb |
| Host | smart-0d70ee6f-fc23-4db6-ae03-7593a234da1f |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2574531003 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_max_throughput_chk.2574531003 |
| Directory | /workspace/0.rom_ctrl_max_throughput_chk/latest |
| Test location | /workspace/coverage/default/0.rom_ctrl_smoke.1684589333 |
| Short name | T361 |
| Test name | |
| Test status | |
| Simulation time | 1770642443 ps |
| CPU time | 21.06 seconds |
| Started | Mar 05 01:51:08 PM PST 24 |
| Finished | Mar 05 01:51:29 PM PST 24 |
| Peak memory | 213324 kb |
| Host | smart-4e17503d-bdc3-433d-b250-cf449f863979 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1684589333 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_smoke.1684589333 |
| Directory | /workspace/0.rom_ctrl_smoke/latest |
| Test location | /workspace/coverage/default/0.rom_ctrl_stress_all.2060852959 |
| Short name | T181 |
| Test name | |
| Test status | |
| Simulation time | 5561511678 ps |
| CPU time | 32.53 seconds |
| Started | Mar 05 01:51:14 PM PST 24 |
| Finished | Mar 05 01:51:46 PM PST 24 |
| Peak memory | 213340 kb |
| Host | smart-fbab7312-0095-4310-981a-6514deea9ae9 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2060852959 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm _name 0.rom_ctrl_stress_all.2060852959 |
| Directory | /workspace/0.rom_ctrl_stress_all/latest |
| Test location | /workspace/coverage/default/0.rom_ctrl_stress_all_with_rand_reset.2094171504 |
| Short name | T53 |
| Test name | |
| Test status | |
| Simulation time | 112322271059 ps |
| CPU time | 3010.52 seconds |
| Started | Mar 05 01:51:04 PM PST 24 |
| Finished | Mar 05 02:41:15 PM PST 24 |
| Peak memory | 235576 kb |
| Host | smart-4fab04a5-08f5-468c-b794-34dfeaef9515 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2094171504 -assert nop ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_stress_all_with_rand_reset.2094171504 |
| Directory | /workspace/0.rom_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/1.rom_ctrl_alert_test.2618000507 |
| Short name | T164 |
| Test name | |
| Test status | |
| Simulation time | 2720443287 ps |
| CPU time | 11.55 seconds |
| Started | Mar 05 01:51:02 PM PST 24 |
| Finished | Mar 05 01:51:14 PM PST 24 |
| Peak memory | 210936 kb |
| Host | smart-6ac82801-4194-45b0-a0dc-06715d4968c4 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2618000507 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_alert_test.2618000507 |
| Directory | /workspace/1.rom_ctrl_alert_test/latest |
| Test location | /workspace/coverage/default/1.rom_ctrl_corrupt_sig_fatal_chk.1527563425 |
| Short name | T176 |
| Test name | |
| Test status | |
| Simulation time | 46013255450 ps |
| CPU time | 135.39 seconds |
| Started | Mar 05 01:51:06 PM PST 24 |
| Finished | Mar 05 01:53:22 PM PST 24 |
| Peak memory | 227212 kb |
| Host | smart-870bfcef-2166-406b-bd5b-887dae44cada |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1527563425 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_c orrupt_sig_fatal_chk.1527563425 |
| Directory | /workspace/1.rom_ctrl_corrupt_sig_fatal_chk/latest |
| Test location | /workspace/coverage/default/1.rom_ctrl_kmac_err_chk.3630048332 |
| Short name | T320 |
| Test name | |
| Test status | |
| Simulation time | 23570224031 ps |
| CPU time | 21.4 seconds |
| Started | Mar 05 01:50:58 PM PST 24 |
| Finished | Mar 05 01:51:20 PM PST 24 |
| Peak memory | 211652 kb |
| Host | smart-50fbdff2-2713-4e92-a0ef-3158280eb50c |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3630048332 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_kmac_err_chk.3630048332 |
| Directory | /workspace/1.rom_ctrl_kmac_err_chk/latest |
| Test location | /workspace/coverage/default/1.rom_ctrl_max_throughput_chk.3367016468 |
| Short name | T40 |
| Test name | |
| Test status | |
| Simulation time | 11226131901 ps |
| CPU time | 13.6 seconds |
| Started | Mar 05 01:51:08 PM PST 24 |
| Finished | Mar 05 01:51:21 PM PST 24 |
| Peak memory | 210852 kb |
| Host | smart-5dc1c008-3158-4a27-a73b-2f106060ccc9 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3367016468 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_max_throughput_chk.3367016468 |
| Directory | /workspace/1.rom_ctrl_max_throughput_chk/latest |
| Test location | /workspace/coverage/default/1.rom_ctrl_sec_cm.640757694 |
| Short name | T35 |
| Test name | |
| Test status | |
| Simulation time | 2181849914 ps |
| CPU time | 110.23 seconds |
| Started | Mar 05 01:51:02 PM PST 24 |
| Finished | Mar 05 01:52:52 PM PST 24 |
| Peak memory | 232300 kb |
| Host | smart-9d10b344-ab61-4906-b321-f852ac7881d2 |
| User | root |
| Command | /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=640757694 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_sec_cm.640757694 |
| Directory | /workspace/1.rom_ctrl_sec_cm/latest |
| Test location | /workspace/coverage/default/1.rom_ctrl_smoke.1014678335 |
| Short name | T207 |
| Test name | |
| Test status | |
| Simulation time | 1273116938 ps |
| CPU time | 9.87 seconds |
| Started | Mar 05 01:51:08 PM PST 24 |
| Finished | Mar 05 01:51:18 PM PST 24 |
| Peak memory | 212624 kb |
| Host | smart-6e5a0662-ff28-4c5d-877b-5e3396b3ccf6 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1014678335 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_smoke.1014678335 |
| Directory | /workspace/1.rom_ctrl_smoke/latest |
| Test location | /workspace/coverage/default/1.rom_ctrl_stress_all.904574331 |
| Short name | T4 |
| Test name | |
| Test status | |
| Simulation time | 1478369656 ps |
| CPU time | 15.48 seconds |
| Started | Mar 05 01:51:14 PM PST 24 |
| Finished | Mar 05 01:51:29 PM PST 24 |
| Peak memory | 211392 kb |
| Host | smart-b39ce4f5-ea6d-452d-9e88-0da6de1e9bce |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=904574331 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test + UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 1.rom_ctrl_stress_all.904574331 |
| Directory | /workspace/1.rom_ctrl_stress_all/latest |
| Test location | /workspace/coverage/default/10.rom_ctrl_alert_test.4252679599 |
| Short name | T337 |
| Test name | |
| Test status | |
| Simulation time | 7347836053 ps |
| CPU time | 15.51 seconds |
| Started | Mar 05 01:51:19 PM PST 24 |
| Finished | Mar 05 01:51:35 PM PST 24 |
| Peak memory | 210972 kb |
| Host | smart-08b541c0-9777-4f73-8593-78c288e29238 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4252679599 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_alert_test.4252679599 |
| Directory | /workspace/10.rom_ctrl_alert_test/latest |
| Test location | /workspace/coverage/default/10.rom_ctrl_corrupt_sig_fatal_chk.2974327859 |
| Short name | T342 |
| Test name | |
| Test status | |
| Simulation time | 59114970205 ps |
| CPU time | 243.3 seconds |
| Started | Mar 05 01:51:35 PM PST 24 |
| Finished | Mar 05 01:55:38 PM PST 24 |
| Peak memory | 237472 kb |
| Host | smart-3e74053f-11bf-4d84-9083-26425b561dd4 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2974327859 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_ corrupt_sig_fatal_chk.2974327859 |
| Directory | /workspace/10.rom_ctrl_corrupt_sig_fatal_chk/latest |
| Test location | /workspace/coverage/default/10.rom_ctrl_max_throughput_chk.3056973613 |
| Short name | T203 |
| Test name | |
| Test status | |
| Simulation time | 3645106275 ps |
| CPU time | 10.66 seconds |
| Started | Mar 05 01:51:07 PM PST 24 |
| Finished | Mar 05 01:51:17 PM PST 24 |
| Peak memory | 210864 kb |
| Host | smart-c6eef9f7-a942-470b-93c7-bca736269189 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3056973613 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_max_throughput_chk.3056973613 |
| Directory | /workspace/10.rom_ctrl_max_throughput_chk/latest |
| Test location | /workspace/coverage/default/10.rom_ctrl_smoke.2008915014 |
| Short name | T21 |
| Test name | |
| Test status | |
| Simulation time | 3897158227 ps |
| CPU time | 37.58 seconds |
| Started | Mar 05 01:51:17 PM PST 24 |
| Finished | Mar 05 01:51:55 PM PST 24 |
| Peak memory | 212692 kb |
| Host | smart-3ad4f633-9365-4fe8-a7e4-9e5858449334 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2008915014 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_smoke.2008915014 |
| Directory | /workspace/10.rom_ctrl_smoke/latest |
| Test location | /workspace/coverage/default/10.rom_ctrl_stress_all.2500835709 |
| Short name | T6 |
| Test name | |
| Test status | |
| Simulation time | 451807642 ps |
| CPU time | 10.45 seconds |
| Started | Mar 05 01:51:04 PM PST 24 |
| Finished | Mar 05 01:51:14 PM PST 24 |
| Peak memory | 210900 kb |
| Host | smart-ef37d86c-8392-437f-a6ee-f98113539841 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2500835709 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm _name 10.rom_ctrl_stress_all.2500835709 |
| Directory | /workspace/10.rom_ctrl_stress_all/latest |
| Test location | /workspace/coverage/default/11.rom_ctrl_alert_test.3115624934 |
| Short name | T139 |
| Test name | |
| Test status | |
| Simulation time | 5192080429 ps |
| CPU time | 11.01 seconds |
| Started | Mar 05 01:51:11 PM PST 24 |
| Finished | Mar 05 01:51:22 PM PST 24 |
| Peak memory | 211016 kb |
| Host | smart-332f8dc9-ca7d-48c4-b6d2-b5de82435dc4 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3115624934 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_alert_test.3115624934 |
| Directory | /workspace/11.rom_ctrl_alert_test/latest |
| Test location | /workspace/coverage/default/11.rom_ctrl_corrupt_sig_fatal_chk.2990222373 |
| Short name | T230 |
| Test name | |
| Test status | |
| Simulation time | 35621525433 ps |
| CPU time | 268.6 seconds |
| Started | Mar 05 01:51:10 PM PST 24 |
| Finished | Mar 05 01:55:39 PM PST 24 |
| Peak memory | 236492 kb |
| Host | smart-1a8f67ce-d155-42d1-985c-3e3c678a7fc8 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2990222373 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_ corrupt_sig_fatal_chk.2990222373 |
| Directory | /workspace/11.rom_ctrl_corrupt_sig_fatal_chk/latest |
| Test location | /workspace/coverage/default/11.rom_ctrl_max_throughput_chk.536324567 |
| Short name | T189 |
| Test name | |
| Test status | |
| Simulation time | 869301574 ps |
| CPU time | 10.67 seconds |
| Started | Mar 05 01:51:08 PM PST 24 |
| Finished | Mar 05 01:51:19 PM PST 24 |
| Peak memory | 210840 kb |
| Host | smart-2edb06b3-29a0-4f41-9f48-4af98f8fd74b |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=536324567 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_max_throughput_chk.536324567 |
| Directory | /workspace/11.rom_ctrl_max_throughput_chk/latest |
| Test location | /workspace/coverage/default/11.rom_ctrl_smoke.2384663273 |
| Short name | T241 |
| Test name | |
| Test status | |
| Simulation time | 396174435 ps |
| CPU time | 10.51 seconds |
| Started | Mar 05 01:51:26 PM PST 24 |
| Finished | Mar 05 01:51:36 PM PST 24 |
| Peak memory | 213044 kb |
| Host | smart-aad15144-9f11-4eb7-8aea-8c956b5b3fa2 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2384663273 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_smoke.2384663273 |
| Directory | /workspace/11.rom_ctrl_smoke/latest |
| Test location | /workspace/coverage/default/11.rom_ctrl_stress_all.1038822587 |
| Short name | T95 |
| Test name | |
| Test status | |
| Simulation time | 14393267623 ps |
| CPU time | 113.13 seconds |
| Started | Mar 05 01:51:10 PM PST 24 |
| Finished | Mar 05 01:53:03 PM PST 24 |
| Peak memory | 219116 kb |
| Host | smart-5b5a191c-bc42-44ce-b0f4-df6a5fa3bab2 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1038822587 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm _name 11.rom_ctrl_stress_all.1038822587 |
| Directory | /workspace/11.rom_ctrl_stress_all/latest |
| Test location | /workspace/coverage/default/12.rom_ctrl_alert_test.1126968882 |
| Short name | T61 |
| Test name | |
| Test status | |
| Simulation time | 2398797829 ps |
| CPU time | 11.48 seconds |
| Started | Mar 05 01:51:30 PM PST 24 |
| Finished | Mar 05 01:51:41 PM PST 24 |
| Peak memory | 210996 kb |
| Host | smart-291af0dc-1b29-49f3-9b3c-0151ef3af755 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1126968882 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_alert_test.1126968882 |
| Directory | /workspace/12.rom_ctrl_alert_test/latest |
| Test location | /workspace/coverage/default/12.rom_ctrl_corrupt_sig_fatal_chk.4229372990 |
| Short name | T351 |
| Test name | |
| Test status | |
| Simulation time | 4013727952 ps |
| CPU time | 56.59 seconds |
| Started | Mar 05 01:51:11 PM PST 24 |
| Finished | Mar 05 01:52:08 PM PST 24 |
| Peak memory | 236208 kb |
| Host | smart-dcbb11be-8917-45d6-9e55-f1974db23477 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4229372990 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_ corrupt_sig_fatal_chk.4229372990 |
| Directory | /workspace/12.rom_ctrl_corrupt_sig_fatal_chk/latest |
| Test location | /workspace/coverage/default/12.rom_ctrl_kmac_err_chk.3384003688 |
| Short name | T327 |
| Test name | |
| Test status | |
| Simulation time | 694415224 ps |
| CPU time | 9.48 seconds |
| Started | Mar 05 01:51:22 PM PST 24 |
| Finished | Mar 05 01:51:31 PM PST 24 |
| Peak memory | 211984 kb |
| Host | smart-92d809a0-35c7-48f6-8c34-07e7ef4f3495 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3384003688 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_kmac_err_chk.3384003688 |
| Directory | /workspace/12.rom_ctrl_kmac_err_chk/latest |
| Test location | /workspace/coverage/default/12.rom_ctrl_max_throughput_chk.3607861086 |
| Short name | T328 |
| Test name | |
| Test status | |
| Simulation time | 1495228568 ps |
| CPU time | 9.62 seconds |
| Started | Mar 05 01:51:26 PM PST 24 |
| Finished | Mar 05 01:51:36 PM PST 24 |
| Peak memory | 210756 kb |
| Host | smart-a8b3a799-d64d-4dc4-90c4-892031ee507a |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3607861086 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_max_throughput_chk.3607861086 |
| Directory | /workspace/12.rom_ctrl_max_throughput_chk/latest |
| Test location | /workspace/coverage/default/12.rom_ctrl_smoke.3618504081 |
| Short name | T188 |
| Test name | |
| Test status | |
| Simulation time | 4287285925 ps |
| CPU time | 16.52 seconds |
| Started | Mar 05 01:51:30 PM PST 24 |
| Finished | Mar 05 01:51:46 PM PST 24 |
| Peak memory | 213484 kb |
| Host | smart-961d429e-017d-4830-b288-26b843a25482 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3618504081 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_smoke.3618504081 |
| Directory | /workspace/12.rom_ctrl_smoke/latest |
| Test location | /workspace/coverage/default/12.rom_ctrl_stress_all.2936800206 |
| Short name | T75 |
| Test name | |
| Test status | |
| Simulation time | 457017389 ps |
| CPU time | 9.05 seconds |
| Started | Mar 05 01:51:11 PM PST 24 |
| Finished | Mar 05 01:51:20 PM PST 24 |
| Peak memory | 210864 kb |
| Host | smart-3812777b-2b68-4de7-a816-6fd7166bf274 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2936800206 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm _name 12.rom_ctrl_stress_all.2936800206 |
| Directory | /workspace/12.rom_ctrl_stress_all/latest |
| Test location | /workspace/coverage/default/12.rom_ctrl_stress_all_with_rand_reset.4276839944 |
| Short name | T50 |
| Test name | |
| Test status | |
| Simulation time | 12167544223 ps |
| CPU time | 1156.06 seconds |
| Started | Mar 05 01:51:33 PM PST 24 |
| Finished | Mar 05 02:10:50 PM PST 24 |
| Peak memory | 227408 kb |
| Host | smart-0c564c3c-39b2-4a88-ac9e-1e89e2dd1fe2 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4276839944 -assert nop ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_stress_all_with_rand_reset.4276839944 |
| Directory | /workspace/12.rom_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/13.rom_ctrl_corrupt_sig_fatal_chk.4163759079 |
| Short name | T155 |
| Test name | |
| Test status | |
| Simulation time | 4400115960 ps |
| CPU time | 131.65 seconds |
| Started | Mar 05 01:51:15 PM PST 24 |
| Finished | Mar 05 01:53:27 PM PST 24 |
| Peak memory | 212260 kb |
| Host | smart-8d169036-1057-4048-920e-d026976fdad5 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4163759079 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_ corrupt_sig_fatal_chk.4163759079 |
| Directory | /workspace/13.rom_ctrl_corrupt_sig_fatal_chk/latest |
| Test location | /workspace/coverage/default/13.rom_ctrl_kmac_err_chk.1159576401 |
| Short name | T270 |
| Test name | |
| Test status | |
| Simulation time | 2806119584 ps |
| CPU time | 26.12 seconds |
| Started | Mar 05 01:51:19 PM PST 24 |
| Finished | Mar 05 01:51:45 PM PST 24 |
| Peak memory | 211332 kb |
| Host | smart-59905132-6ced-4452-8c29-f28f292ce346 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1159576401 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_kmac_err_chk.1159576401 |
| Directory | /workspace/13.rom_ctrl_kmac_err_chk/latest |
| Test location | /workspace/coverage/default/13.rom_ctrl_max_throughput_chk.2468719403 |
| Short name | T208 |
| Test name | |
| Test status | |
| Simulation time | 8175046760 ps |
| CPU time | 16.72 seconds |
| Started | Mar 05 01:51:25 PM PST 24 |
| Finished | Mar 05 01:51:42 PM PST 24 |
| Peak memory | 210824 kb |
| Host | smart-1e7240bd-2a4f-426a-b7f8-eca61bbc239b |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2468719403 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_max_throughput_chk.2468719403 |
| Directory | /workspace/13.rom_ctrl_max_throughput_chk/latest |
| Test location | /workspace/coverage/default/13.rom_ctrl_smoke.3370204160 |
| Short name | T201 |
| Test name | |
| Test status | |
| Simulation time | 8218856608 ps |
| CPU time | 27.96 seconds |
| Started | Mar 05 01:51:15 PM PST 24 |
| Finished | Mar 05 01:51:43 PM PST 24 |
| Peak memory | 213756 kb |
| Host | smart-ca65e9e0-ad48-4153-881e-b8ab29041f69 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3370204160 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_smoke.3370204160 |
| Directory | /workspace/13.rom_ctrl_smoke/latest |
| Test location | /workspace/coverage/default/13.rom_ctrl_stress_all.2945052684 |
| Short name | T72 |
| Test name | |
| Test status | |
| Simulation time | 20124377317 ps |
| CPU time | 54.16 seconds |
| Started | Mar 05 01:51:09 PM PST 24 |
| Finished | Mar 05 01:52:04 PM PST 24 |
| Peak memory | 213616 kb |
| Host | smart-e8f2883a-4852-466e-8ed0-26bb1e12381b |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2945052684 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm _name 13.rom_ctrl_stress_all.2945052684 |
| Directory | /workspace/13.rom_ctrl_stress_all/latest |
| Test location | /workspace/coverage/default/14.rom_ctrl_alert_test.1941446085 |
| Short name | T112 |
| Test name | |
| Test status | |
| Simulation time | 2061053934 ps |
| CPU time | 6.25 seconds |
| Started | Mar 05 01:51:33 PM PST 24 |
| Finished | Mar 05 01:51:39 PM PST 24 |
| Peak memory | 210932 kb |
| Host | smart-d4d29c0d-2514-4615-bb5e-3edbafc98d47 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1941446085 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_alert_test.1941446085 |
| Directory | /workspace/14.rom_ctrl_alert_test/latest |
| Test location | /workspace/coverage/default/14.rom_ctrl_corrupt_sig_fatal_chk.2738825311 |
| Short name | T142 |
| Test name | |
| Test status | |
| Simulation time | 77386326876 ps |
| CPU time | 351.61 seconds |
| Started | Mar 05 01:51:29 PM PST 24 |
| Finished | Mar 05 01:57:26 PM PST 24 |
| Peak memory | 230444 kb |
| Host | smart-ac68f727-6246-4dc2-ac13-9bdd92865c5b |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2738825311 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_ corrupt_sig_fatal_chk.2738825311 |
| Directory | /workspace/14.rom_ctrl_corrupt_sig_fatal_chk/latest |
| Test location | /workspace/coverage/default/14.rom_ctrl_kmac_err_chk.3677869184 |
| Short name | T298 |
| Test name | |
| Test status | |
| Simulation time | 7289040006 ps |
| CPU time | 21.09 seconds |
| Started | Mar 05 01:51:09 PM PST 24 |
| Finished | Mar 05 01:51:30 PM PST 24 |
| Peak memory | 211976 kb |
| Host | smart-21d764ab-6384-4a80-9794-013aa19f7af4 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3677869184 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_kmac_err_chk.3677869184 |
| Directory | /workspace/14.rom_ctrl_kmac_err_chk/latest |
| Test location | /workspace/coverage/default/14.rom_ctrl_max_throughput_chk.1263034958 |
| Short name | T131 |
| Test name | |
| Test status | |
| Simulation time | 99394747 ps |
| CPU time | 5.79 seconds |
| Started | Mar 05 01:51:23 PM PST 24 |
| Finished | Mar 05 01:51:29 PM PST 24 |
| Peak memory | 210780 kb |
| Host | smart-411b5606-7a49-4cbd-a3ae-ba79b6bf75dd |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1263034958 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_max_throughput_chk.1263034958 |
| Directory | /workspace/14.rom_ctrl_max_throughput_chk/latest |
| Test location | /workspace/coverage/default/14.rom_ctrl_smoke.2014260636 |
| Short name | T280 |
| Test name | |
| Test status | |
| Simulation time | 28392036050 ps |
| CPU time | 42.55 seconds |
| Started | Mar 05 01:51:25 PM PST 24 |
| Finished | Mar 05 01:52:08 PM PST 24 |
| Peak memory | 219072 kb |
| Host | smart-f25c9d97-4fa1-494b-bbb9-d49d8422b73c |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2014260636 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_smoke.2014260636 |
| Directory | /workspace/14.rom_ctrl_smoke/latest |
| Test location | /workspace/coverage/default/14.rom_ctrl_stress_all.2954433744 |
| Short name | T307 |
| Test name | |
| Test status | |
| Simulation time | 9227079186 ps |
| CPU time | 79 seconds |
| Started | Mar 05 01:51:24 PM PST 24 |
| Finished | Mar 05 01:52:43 PM PST 24 |
| Peak memory | 219136 kb |
| Host | smart-f117ea33-88d8-48c0-99c7-ba04b409116c |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2954433744 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm _name 14.rom_ctrl_stress_all.2954433744 |
| Directory | /workspace/14.rom_ctrl_stress_all/latest |
| Test location | /workspace/coverage/default/15.rom_ctrl_alert_test.130020631 |
| Short name | T8 |
| Test name | |
| Test status | |
| Simulation time | 8325165421 ps |
| CPU time | 15.82 seconds |
| Started | Mar 05 01:51:22 PM PST 24 |
| Finished | Mar 05 01:51:38 PM PST 24 |
| Peak memory | 210988 kb |
| Host | smart-e8eb2389-96c6-49eb-b21c-ad1f72504584 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=130020631 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_alert_test.130020631 |
| Directory | /workspace/15.rom_ctrl_alert_test/latest |
| Test location | /workspace/coverage/default/15.rom_ctrl_corrupt_sig_fatal_chk.36454360 |
| Short name | T28 |
| Test name | |
| Test status | |
| Simulation time | 12355612196 ps |
| CPU time | 157.05 seconds |
| Started | Mar 05 01:51:29 PM PST 24 |
| Finished | Mar 05 01:54:07 PM PST 24 |
| Peak memory | 229236 kb |
| Host | smart-e3201b92-47d3-4872-8451-024a22b775ed |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36454360 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_ sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_co rrupt_sig_fatal_chk.36454360 |
| Directory | /workspace/15.rom_ctrl_corrupt_sig_fatal_chk/latest |
| Test location | /workspace/coverage/default/15.rom_ctrl_kmac_err_chk.3088363530 |
| Short name | T219 |
| Test name | |
| Test status | |
| Simulation time | 1783181381 ps |
| CPU time | 19.93 seconds |
| Started | Mar 05 01:51:33 PM PST 24 |
| Finished | Mar 05 01:51:54 PM PST 24 |
| Peak memory | 210812 kb |
| Host | smart-f0889dc2-da34-47ca-95c2-b5383cc64454 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3088363530 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_kmac_err_chk.3088363530 |
| Directory | /workspace/15.rom_ctrl_kmac_err_chk/latest |
| Test location | /workspace/coverage/default/15.rom_ctrl_max_throughput_chk.3026358058 |
| Short name | T2 |
| Test name | |
| Test status | |
| Simulation time | 1171393684 ps |
| CPU time | 11.91 seconds |
| Started | Mar 05 01:51:36 PM PST 24 |
| Finished | Mar 05 01:51:49 PM PST 24 |
| Peak memory | 210796 kb |
| Host | smart-8df2fcd4-f715-48b6-9c21-0c55b1624a5c |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3026358058 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_max_throughput_chk.3026358058 |
| Directory | /workspace/15.rom_ctrl_max_throughput_chk/latest |
| Test location | /workspace/coverage/default/15.rom_ctrl_smoke.127155161 |
| Short name | T157 |
| Test name | |
| Test status | |
| Simulation time | 5238130616 ps |
| CPU time | 28.92 seconds |
| Started | Mar 05 01:51:34 PM PST 24 |
| Finished | Mar 05 01:52:03 PM PST 24 |
| Peak memory | 213236 kb |
| Host | smart-78517e64-7e37-4bb4-af18-8051e6521b22 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=127155161 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_smoke.127155161 |
| Directory | /workspace/15.rom_ctrl_smoke/latest |
| Test location | /workspace/coverage/default/15.rom_ctrl_stress_all.1032954271 |
| Short name | T282 |
| Test name | |
| Test status | |
| Simulation time | 3252131034 ps |
| CPU time | 44.98 seconds |
| Started | Mar 05 01:51:36 PM PST 24 |
| Finished | Mar 05 01:52:21 PM PST 24 |
| Peak memory | 214508 kb |
| Host | smart-4b620d96-036b-4c75-b670-0f3300a9a431 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1032954271 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm _name 15.rom_ctrl_stress_all.1032954271 |
| Directory | /workspace/15.rom_ctrl_stress_all/latest |
| Test location | /workspace/coverage/default/16.rom_ctrl_alert_test.2696185533 |
| Short name | T120 |
| Test name | |
| Test status | |
| Simulation time | 1988963488 ps |
| CPU time | 14.63 seconds |
| Started | Mar 05 01:51:33 PM PST 24 |
| Finished | Mar 05 01:51:48 PM PST 24 |
| Peak memory | 210820 kb |
| Host | smart-0c460529-ac3d-4141-ac31-344636c75e82 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2696185533 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_alert_test.2696185533 |
| Directory | /workspace/16.rom_ctrl_alert_test/latest |
| Test location | /workspace/coverage/default/16.rom_ctrl_corrupt_sig_fatal_chk.2698514960 |
| Short name | T252 |
| Test name | |
| Test status | |
| Simulation time | 34059879151 ps |
| CPU time | 256.72 seconds |
| Started | Mar 05 01:51:26 PM PST 24 |
| Finished | Mar 05 01:55:43 PM PST 24 |
| Peak memory | 212232 kb |
| Host | smart-a9a684d1-f1e7-4aca-9c6b-04eabcae8373 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2698514960 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_ corrupt_sig_fatal_chk.2698514960 |
| Directory | /workspace/16.rom_ctrl_corrupt_sig_fatal_chk/latest |
| Test location | /workspace/coverage/default/16.rom_ctrl_kmac_err_chk.3429941101 |
| Short name | T329 |
| Test name | |
| Test status | |
| Simulation time | 13394466325 ps |
| CPU time | 25.19 seconds |
| Started | Mar 05 01:51:32 PM PST 24 |
| Finished | Mar 05 01:51:57 PM PST 24 |
| Peak memory | 211828 kb |
| Host | smart-1111552b-6401-4f68-a679-4979dc17fb64 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3429941101 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_kmac_err_chk.3429941101 |
| Directory | /workspace/16.rom_ctrl_kmac_err_chk/latest |
| Test location | /workspace/coverage/default/16.rom_ctrl_max_throughput_chk.4170580359 |
| Short name | T182 |
| Test name | |
| Test status | |
| Simulation time | 1948922380 ps |
| CPU time | 16.34 seconds |
| Started | Mar 05 01:51:28 PM PST 24 |
| Finished | Mar 05 01:51:45 PM PST 24 |
| Peak memory | 210832 kb |
| Host | smart-26ca849f-8c88-4d95-8ef7-956cff7debcf |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=4170580359 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_max_throughput_chk.4170580359 |
| Directory | /workspace/16.rom_ctrl_max_throughput_chk/latest |
| Test location | /workspace/coverage/default/16.rom_ctrl_smoke.1162451848 |
| Short name | T295 |
| Test name | |
| Test status | |
| Simulation time | 724804313 ps |
| CPU time | 9.75 seconds |
| Started | Mar 05 01:51:18 PM PST 24 |
| Finished | Mar 05 01:51:33 PM PST 24 |
| Peak memory | 213072 kb |
| Host | smart-7c9d7559-a201-44c3-9197-57ea45a91fa8 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1162451848 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_smoke.1162451848 |
| Directory | /workspace/16.rom_ctrl_smoke/latest |
| Test location | /workspace/coverage/default/16.rom_ctrl_stress_all.3048245749 |
| Short name | T243 |
| Test name | |
| Test status | |
| Simulation time | 850476797 ps |
| CPU time | 12.12 seconds |
| Started | Mar 05 01:51:29 PM PST 24 |
| Finished | Mar 05 01:51:41 PM PST 24 |
| Peak memory | 210760 kb |
| Host | smart-53ceb141-3389-4597-93b8-18f809a2ce25 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3048245749 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm _name 16.rom_ctrl_stress_all.3048245749 |
| Directory | /workspace/16.rom_ctrl_stress_all/latest |
| Test location | /workspace/coverage/default/16.rom_ctrl_stress_all_with_rand_reset.2121238267 |
| Short name | T47 |
| Test name | |
| Test status | |
| Simulation time | 402811210019 ps |
| CPU time | 1653.69 seconds |
| Started | Mar 05 01:51:30 PM PST 24 |
| Finished | Mar 05 02:19:04 PM PST 24 |
| Peak memory | 237268 kb |
| Host | smart-1d56996a-24b7-41ff-b517-3ac231a06b43 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2121238267 -assert nop ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_stress_all_with_rand_reset.2121238267 |
| Directory | /workspace/16.rom_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/17.rom_ctrl_alert_test.2188284103 |
| Short name | T113 |
| Test name | |
| Test status | |
| Simulation time | 208037604 ps |
| CPU time | 5.71 seconds |
| Started | Mar 05 01:51:30 PM PST 24 |
| Finished | Mar 05 01:51:36 PM PST 24 |
| Peak memory | 210896 kb |
| Host | smart-12a90123-a982-46fa-9f26-e29048c1728b |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2188284103 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_alert_test.2188284103 |
| Directory | /workspace/17.rom_ctrl_alert_test/latest |
| Test location | /workspace/coverage/default/17.rom_ctrl_corrupt_sig_fatal_chk.2274303081 |
| Short name | T233 |
| Test name | |
| Test status | |
| Simulation time | 15579900840 ps |
| CPU time | 170.29 seconds |
| Started | Mar 05 01:51:35 PM PST 24 |
| Finished | Mar 05 01:54:25 PM PST 24 |
| Peak memory | 213324 kb |
| Host | smart-ce43ba82-1f0a-416f-8c69-4127b1647785 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2274303081 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_ corrupt_sig_fatal_chk.2274303081 |
| Directory | /workspace/17.rom_ctrl_corrupt_sig_fatal_chk/latest |
| Test location | /workspace/coverage/default/17.rom_ctrl_kmac_err_chk.2102975161 |
| Short name | T344 |
| Test name | |
| Test status | |
| Simulation time | 1833152653 ps |
| CPU time | 20.97 seconds |
| Started | Mar 05 01:51:25 PM PST 24 |
| Finished | Mar 05 01:51:46 PM PST 24 |
| Peak memory | 211552 kb |
| Host | smart-63ce4170-1d79-4e76-a459-e6055e8f8604 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2102975161 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_kmac_err_chk.2102975161 |
| Directory | /workspace/17.rom_ctrl_kmac_err_chk/latest |
| Test location | /workspace/coverage/default/17.rom_ctrl_max_throughput_chk.575683067 |
| Short name | T215 |
| Test name | |
| Test status | |
| Simulation time | 460613872 ps |
| CPU time | 8.71 seconds |
| Started | Mar 05 01:51:37 PM PST 24 |
| Finished | Mar 05 01:51:46 PM PST 24 |
| Peak memory | 210812 kb |
| Host | smart-b433e01c-a192-4b1b-bff9-02186bac2a3c |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=575683067 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_max_throughput_chk.575683067 |
| Directory | /workspace/17.rom_ctrl_max_throughput_chk/latest |
| Test location | /workspace/coverage/default/17.rom_ctrl_smoke.2149213787 |
| Short name | T336 |
| Test name | |
| Test status | |
| Simulation time | 1959727552 ps |
| CPU time | 21.84 seconds |
| Started | Mar 05 01:51:28 PM PST 24 |
| Finished | Mar 05 01:51:50 PM PST 24 |
| Peak memory | 212460 kb |
| Host | smart-b491cb58-d4d3-449b-a387-172c31c5fcb2 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2149213787 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_smoke.2149213787 |
| Directory | /workspace/17.rom_ctrl_smoke/latest |
| Test location | /workspace/coverage/default/17.rom_ctrl_stress_all.1906839372 |
| Short name | T232 |
| Test name | |
| Test status | |
| Simulation time | 6058544258 ps |
| CPU time | 57.38 seconds |
| Started | Mar 05 01:51:34 PM PST 24 |
| Finished | Mar 05 01:52:31 PM PST 24 |
| Peak memory | 212844 kb |
| Host | smart-0844de92-11ef-410d-8e3c-b7301cf23f93 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1906839372 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm _name 17.rom_ctrl_stress_all.1906839372 |
| Directory | /workspace/17.rom_ctrl_stress_all/latest |
| Test location | /workspace/coverage/default/18.rom_ctrl_alert_test.1774542101 |
| Short name | T231 |
| Test name | |
| Test status | |
| Simulation time | 85838503 ps |
| CPU time | 4.48 seconds |
| Started | Mar 05 01:51:33 PM PST 24 |
| Finished | Mar 05 01:51:37 PM PST 24 |
| Peak memory | 210856 kb |
| Host | smart-f681e275-4e38-4fa9-a0d8-73aa3eddfff6 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1774542101 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_alert_test.1774542101 |
| Directory | /workspace/18.rom_ctrl_alert_test/latest |
| Test location | /workspace/coverage/default/18.rom_ctrl_corrupt_sig_fatal_chk.417948539 |
| Short name | T151 |
| Test name | |
| Test status | |
| Simulation time | 398442735002 ps |
| CPU time | 214.65 seconds |
| Started | Mar 05 01:51:34 PM PST 24 |
| Finished | Mar 05 01:55:09 PM PST 24 |
| Peak memory | 225668 kb |
| Host | smart-7f61140b-4181-44f6-99c8-925143010783 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=417948539 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt _sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_c orrupt_sig_fatal_chk.417948539 |
| Directory | /workspace/18.rom_ctrl_corrupt_sig_fatal_chk/latest |
| Test location | /workspace/coverage/default/18.rom_ctrl_kmac_err_chk.767369600 |
| Short name | T124 |
| Test name | |
| Test status | |
| Simulation time | 2124801632 ps |
| CPU time | 18.74 seconds |
| Started | Mar 05 01:51:26 PM PST 24 |
| Finished | Mar 05 01:51:45 PM PST 24 |
| Peak memory | 211476 kb |
| Host | smart-d2bc1c67-38db-46d4-a5b5-c722b4a10fdf |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=767369600 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_kmac_err_chk.767369600 |
| Directory | /workspace/18.rom_ctrl_kmac_err_chk/latest |
| Test location | /workspace/coverage/default/18.rom_ctrl_max_throughput_chk.962707614 |
| Short name | T325 |
| Test name | |
| Test status | |
| Simulation time | 98914235 ps |
| CPU time | 5.58 seconds |
| Started | Mar 05 01:51:35 PM PST 24 |
| Finished | Mar 05 01:51:41 PM PST 24 |
| Peak memory | 210736 kb |
| Host | smart-99c5d444-996d-4729-8bc8-cd6156d5280d |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=962707614 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_max_throughput_chk.962707614 |
| Directory | /workspace/18.rom_ctrl_max_throughput_chk/latest |
| Test location | /workspace/coverage/default/18.rom_ctrl_smoke.1225185599 |
| Short name | T362 |
| Test name | |
| Test status | |
| Simulation time | 6497826124 ps |
| CPU time | 22.38 seconds |
| Started | Mar 05 01:51:29 PM PST 24 |
| Finished | Mar 05 01:51:52 PM PST 24 |
| Peak memory | 212920 kb |
| Host | smart-55bb02d9-5a78-4a6e-af7c-7cef3a5d3296 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1225185599 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_smoke.1225185599 |
| Directory | /workspace/18.rom_ctrl_smoke/latest |
| Test location | /workspace/coverage/default/18.rom_ctrl_stress_all.216340288 |
| Short name | T194 |
| Test name | |
| Test status | |
| Simulation time | 373550072 ps |
| CPU time | 22.81 seconds |
| Started | Mar 05 01:51:18 PM PST 24 |
| Finished | Mar 05 01:51:41 PM PST 24 |
| Peak memory | 215612 kb |
| Host | smart-05dc159f-8351-47e9-a51e-ebbda3a3a1ec |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=216340288 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test + UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 18.rom_ctrl_stress_all.216340288 |
| Directory | /workspace/18.rom_ctrl_stress_all/latest |
| Test location | /workspace/coverage/default/19.rom_ctrl_alert_test.4110502147 |
| Short name | T7 |
| Test name | |
| Test status | |
| Simulation time | 4977082872 ps |
| CPU time | 11.85 seconds |
| Started | Mar 05 01:51:32 PM PST 24 |
| Finished | Mar 05 01:51:44 PM PST 24 |
| Peak memory | 210928 kb |
| Host | smart-05e692cd-ce5e-4d0e-a2d5-4a87329e31e5 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4110502147 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_alert_test.4110502147 |
| Directory | /workspace/19.rom_ctrl_alert_test/latest |
| Test location | /workspace/coverage/default/19.rom_ctrl_corrupt_sig_fatal_chk.3044478858 |
| Short name | T44 |
| Test name | |
| Test status | |
| Simulation time | 70817126185 ps |
| CPU time | 366.12 seconds |
| Started | Mar 05 01:51:26 PM PST 24 |
| Finished | Mar 05 01:57:32 PM PST 24 |
| Peak memory | 240028 kb |
| Host | smart-03f186b9-c086-45d0-b782-86f19ac3621c |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3044478858 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_ corrupt_sig_fatal_chk.3044478858 |
| Directory | /workspace/19.rom_ctrl_corrupt_sig_fatal_chk/latest |
| Test location | /workspace/coverage/default/19.rom_ctrl_kmac_err_chk.2356709173 |
| Short name | T285 |
| Test name | |
| Test status | |
| Simulation time | 3098907160 ps |
| CPU time | 25.26 seconds |
| Started | Mar 05 01:51:30 PM PST 24 |
| Finished | Mar 05 01:51:55 PM PST 24 |
| Peak memory | 211444 kb |
| Host | smart-06a3f5d8-6482-43ee-b567-0773a19d99f4 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2356709173 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_kmac_err_chk.2356709173 |
| Directory | /workspace/19.rom_ctrl_kmac_err_chk/latest |
| Test location | /workspace/coverage/default/19.rom_ctrl_max_throughput_chk.378782417 |
| Short name | T249 |
| Test name | |
| Test status | |
| Simulation time | 2152309796 ps |
| CPU time | 17.13 seconds |
| Started | Mar 05 01:51:22 PM PST 24 |
| Finished | Mar 05 01:51:39 PM PST 24 |
| Peak memory | 210900 kb |
| Host | smart-3dfe8026-546e-4300-8ee8-080cd68f0d73 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=378782417 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_max_throughput_chk.378782417 |
| Directory | /workspace/19.rom_ctrl_max_throughput_chk/latest |
| Test location | /workspace/coverage/default/19.rom_ctrl_smoke.1880365901 |
| Short name | T115 |
| Test name | |
| Test status | |
| Simulation time | 8710127387 ps |
| CPU time | 35.42 seconds |
| Started | Mar 05 01:51:35 PM PST 24 |
| Finished | Mar 05 01:52:11 PM PST 24 |
| Peak memory | 213516 kb |
| Host | smart-f89873dd-94f4-43df-960c-c8988ad37bd3 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1880365901 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_smoke.1880365901 |
| Directory | /workspace/19.rom_ctrl_smoke/latest |
| Test location | /workspace/coverage/default/19.rom_ctrl_stress_all.2205640850 |
| Short name | T291 |
| Test name | |
| Test status | |
| Simulation time | 1404339727 ps |
| CPU time | 25.26 seconds |
| Started | Mar 05 01:51:22 PM PST 24 |
| Finished | Mar 05 01:51:47 PM PST 24 |
| Peak memory | 210892 kb |
| Host | smart-58bab28c-00f5-409c-8b3b-d5a5f3c59b18 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2205640850 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm _name 19.rom_ctrl_stress_all.2205640850 |
| Directory | /workspace/19.rom_ctrl_stress_all/latest |
| Test location | /workspace/coverage/default/19.rom_ctrl_stress_all_with_rand_reset.2682891766 |
| Short name | T349 |
| Test name | |
| Test status | |
| Simulation time | 14333892154 ps |
| CPU time | 1051.72 seconds |
| Started | Mar 05 01:51:24 PM PST 24 |
| Finished | Mar 05 02:08:56 PM PST 24 |
| Peak memory | 226608 kb |
| Host | smart-96fdadcd-6267-4892-afe2-8c64dd138142 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2682891766 -assert nop ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_stress_all_with_rand_reset.2682891766 |
| Directory | /workspace/19.rom_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/2.rom_ctrl_alert_test.973541244 |
| Short name | T137 |
| Test name | |
| Test status | |
| Simulation time | 2909839951 ps |
| CPU time | 9.03 seconds |
| Started | Mar 05 01:51:17 PM PST 24 |
| Finished | Mar 05 01:51:26 PM PST 24 |
| Peak memory | 210880 kb |
| Host | smart-0998f3c3-57a3-4a45-9499-1acfd164b4a2 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=973541244 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_alert_test.973541244 |
| Directory | /workspace/2.rom_ctrl_alert_test/latest |
| Test location | /workspace/coverage/default/2.rom_ctrl_corrupt_sig_fatal_chk.1403978878 |
| Short name | T284 |
| Test name | |
| Test status | |
| Simulation time | 6343151446 ps |
| CPU time | 95.36 seconds |
| Started | Mar 05 01:51:06 PM PST 24 |
| Finished | Mar 05 01:52:41 PM PST 24 |
| Peak memory | 237668 kb |
| Host | smart-cf0bc58f-e617-4b67-a3c1-f2f3e0bfd69d |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1403978878 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_c orrupt_sig_fatal_chk.1403978878 |
| Directory | /workspace/2.rom_ctrl_corrupt_sig_fatal_chk/latest |
| Test location | /workspace/coverage/default/2.rom_ctrl_kmac_err_chk.3458466327 |
| Short name | T323 |
| Test name | |
| Test status | |
| Simulation time | 1839813824 ps |
| CPU time | 9.6 seconds |
| Started | Mar 05 01:51:06 PM PST 24 |
| Finished | Mar 05 01:51:16 PM PST 24 |
| Peak memory | 211440 kb |
| Host | smart-2649e1d4-fa65-4e1a-9610-6448b8cde9be |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3458466327 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_kmac_err_chk.3458466327 |
| Directory | /workspace/2.rom_ctrl_kmac_err_chk/latest |
| Test location | /workspace/coverage/default/2.rom_ctrl_max_throughput_chk.2214419516 |
| Short name | T136 |
| Test name | |
| Test status | |
| Simulation time | 6970971456 ps |
| CPU time | 15.51 seconds |
| Started | Mar 05 01:51:05 PM PST 24 |
| Finished | Mar 05 01:51:21 PM PST 24 |
| Peak memory | 210852 kb |
| Host | smart-e7bc5d45-caca-4a70-93aa-ad442927b1dd |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2214419516 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_max_throughput_chk.2214419516 |
| Directory | /workspace/2.rom_ctrl_max_throughput_chk/latest |
| Test location | /workspace/coverage/default/2.rom_ctrl_sec_cm.3555847487 |
| Short name | T31 |
| Test name | |
| Test status | |
| Simulation time | 10353809263 ps |
| CPU time | 105.28 seconds |
| Started | Mar 05 01:51:13 PM PST 24 |
| Finished | Mar 05 01:52:59 PM PST 24 |
| Peak memory | 232700 kb |
| Host | smart-2a84f60d-9152-4532-931e-3695812ec1bd |
| User | root |
| Command | /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3555847487 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_sec_cm.3555847487 |
| Directory | /workspace/2.rom_ctrl_sec_cm/latest |
| Test location | /workspace/coverage/default/2.rom_ctrl_smoke.3307409965 |
| Short name | T217 |
| Test name | |
| Test status | |
| Simulation time | 367868682 ps |
| CPU time | 10.29 seconds |
| Started | Mar 05 01:50:59 PM PST 24 |
| Finished | Mar 05 01:51:09 PM PST 24 |
| Peak memory | 213040 kb |
| Host | smart-490c6383-cf6e-4cfa-af71-8a52a4a6cb1f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3307409965 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_smoke.3307409965 |
| Directory | /workspace/2.rom_ctrl_smoke/latest |
| Test location | /workspace/coverage/default/2.rom_ctrl_stress_all.2958206082 |
| Short name | T73 |
| Test name | |
| Test status | |
| Simulation time | 8334986084 ps |
| CPU time | 25.7 seconds |
| Started | Mar 05 01:51:00 PM PST 24 |
| Finished | Mar 05 01:51:26 PM PST 24 |
| Peak memory | 214532 kb |
| Host | smart-331bb49a-dbe7-4d69-b442-f00968225b98 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2958206082 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm _name 2.rom_ctrl_stress_all.2958206082 |
| Directory | /workspace/2.rom_ctrl_stress_all/latest |
| Test location | /workspace/coverage/default/20.rom_ctrl_alert_test.2264429260 |
| Short name | T57 |
| Test name | |
| Test status | |
| Simulation time | 18474430312 ps |
| CPU time | 15.14 seconds |
| Started | Mar 05 01:51:34 PM PST 24 |
| Finished | Mar 05 01:51:49 PM PST 24 |
| Peak memory | 211020 kb |
| Host | smart-28529b66-e980-4172-a39b-a212d038e29a |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2264429260 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_alert_test.2264429260 |
| Directory | /workspace/20.rom_ctrl_alert_test/latest |
| Test location | /workspace/coverage/default/20.rom_ctrl_corrupt_sig_fatal_chk.755322321 |
| Short name | T255 |
| Test name | |
| Test status | |
| Simulation time | 2027020095 ps |
| CPU time | 112.01 seconds |
| Started | Mar 05 01:51:25 PM PST 24 |
| Finished | Mar 05 01:53:17 PM PST 24 |
| Peak memory | 213188 kb |
| Host | smart-20e50432-296f-460a-843e-340aa5669ef3 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=755322321 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt _sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_c orrupt_sig_fatal_chk.755322321 |
| Directory | /workspace/20.rom_ctrl_corrupt_sig_fatal_chk/latest |
| Test location | /workspace/coverage/default/20.rom_ctrl_kmac_err_chk.3951658160 |
| Short name | T266 |
| Test name | |
| Test status | |
| Simulation time | 902976663 ps |
| CPU time | 15.98 seconds |
| Started | Mar 05 01:51:24 PM PST 24 |
| Finished | Mar 05 01:51:40 PM PST 24 |
| Peak memory | 211336 kb |
| Host | smart-0cfc7e98-1896-41f5-833d-1c4dcd2b9107 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3951658160 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_kmac_err_chk.3951658160 |
| Directory | /workspace/20.rom_ctrl_kmac_err_chk/latest |
| Test location | /workspace/coverage/default/20.rom_ctrl_max_throughput_chk.3724301091 |
| Short name | T288 |
| Test name | |
| Test status | |
| Simulation time | 1116335429 ps |
| CPU time | 11.97 seconds |
| Started | Mar 05 01:51:26 PM PST 24 |
| Finished | Mar 05 01:51:38 PM PST 24 |
| Peak memory | 210812 kb |
| Host | smart-32433d64-7058-4540-bca9-ac0803f225d6 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3724301091 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_max_throughput_chk.3724301091 |
| Directory | /workspace/20.rom_ctrl_max_throughput_chk/latest |
| Test location | /workspace/coverage/default/20.rom_ctrl_stress_all.3724424876 |
| Short name | T254 |
| Test name | |
| Test status | |
| Simulation time | 6757590487 ps |
| CPU time | 32.49 seconds |
| Started | Mar 05 01:51:24 PM PST 24 |
| Finished | Mar 05 01:51:56 PM PST 24 |
| Peak memory | 212888 kb |
| Host | smart-5aeb0b9c-2d0f-4fc1-bfe9-8516e0b1248e |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3724424876 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm _name 20.rom_ctrl_stress_all.3724424876 |
| Directory | /workspace/20.rom_ctrl_stress_all/latest |
| Test location | /workspace/coverage/default/21.rom_ctrl_alert_test.3117279978 |
| Short name | T290 |
| Test name | |
| Test status | |
| Simulation time | 3070239249 ps |
| CPU time | 9.15 seconds |
| Started | Mar 05 01:51:30 PM PST 24 |
| Finished | Mar 05 01:51:39 PM PST 24 |
| Peak memory | 210920 kb |
| Host | smart-a3634c4a-b1d5-492e-a435-06dfdd528620 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3117279978 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_alert_test.3117279978 |
| Directory | /workspace/21.rom_ctrl_alert_test/latest |
| Test location | /workspace/coverage/default/21.rom_ctrl_corrupt_sig_fatal_chk.1691196586 |
| Short name | T193 |
| Test name | |
| Test status | |
| Simulation time | 149193062341 ps |
| CPU time | 355.91 seconds |
| Started | Mar 05 01:51:19 PM PST 24 |
| Finished | Mar 05 01:57:15 PM PST 24 |
| Peak memory | 236012 kb |
| Host | smart-81ed993a-bbe2-40fd-b49f-a70eaaaebac4 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1691196586 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_ corrupt_sig_fatal_chk.1691196586 |
| Directory | /workspace/21.rom_ctrl_corrupt_sig_fatal_chk/latest |
| Test location | /workspace/coverage/default/21.rom_ctrl_kmac_err_chk.1760170183 |
| Short name | T196 |
| Test name | |
| Test status | |
| Simulation time | 29566176484 ps |
| CPU time | 28.59 seconds |
| Started | Mar 05 01:51:35 PM PST 24 |
| Finished | Mar 05 01:52:04 PM PST 24 |
| Peak memory | 211716 kb |
| Host | smart-b70e0421-b10e-4f33-abcc-2a73dc7790fb |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1760170183 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_kmac_err_chk.1760170183 |
| Directory | /workspace/21.rom_ctrl_kmac_err_chk/latest |
| Test location | /workspace/coverage/default/21.rom_ctrl_max_throughput_chk.2063248228 |
| Short name | T302 |
| Test name | |
| Test status | |
| Simulation time | 2495593076 ps |
| CPU time | 12.6 seconds |
| Started | Mar 05 01:51:28 PM PST 24 |
| Finished | Mar 05 01:51:40 PM PST 24 |
| Peak memory | 210812 kb |
| Host | smart-510779de-35ee-46c7-b485-633c26b8fc3a |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2063248228 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_max_throughput_chk.2063248228 |
| Directory | /workspace/21.rom_ctrl_max_throughput_chk/latest |
| Test location | /workspace/coverage/default/21.rom_ctrl_smoke.2087878617 |
| Short name | T365 |
| Test name | |
| Test status | |
| Simulation time | 30128460246 ps |
| CPU time | 21.27 seconds |
| Started | Mar 05 01:51:37 PM PST 24 |
| Finished | Mar 05 01:51:59 PM PST 24 |
| Peak memory | 213432 kb |
| Host | smart-03655e9c-c04e-4f08-a17c-3fa870944b94 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2087878617 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_smoke.2087878617 |
| Directory | /workspace/21.rom_ctrl_smoke/latest |
| Test location | /workspace/coverage/default/21.rom_ctrl_stress_all.631118899 |
| Short name | T41 |
| Test name | |
| Test status | |
| Simulation time | 18205508314 ps |
| CPU time | 61.98 seconds |
| Started | Mar 05 01:51:32 PM PST 24 |
| Finished | Mar 05 01:52:34 PM PST 24 |
| Peak memory | 215044 kb |
| Host | smart-5f3ca802-9fe2-4580-b1e4-f235db23bde4 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=631118899 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test + UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 21.rom_ctrl_stress_all.631118899 |
| Directory | /workspace/21.rom_ctrl_stress_all/latest |
| Test location | /workspace/coverage/default/22.rom_ctrl_alert_test.1123460596 |
| Short name | T301 |
| Test name | |
| Test status | |
| Simulation time | 5973987697 ps |
| CPU time | 13.28 seconds |
| Started | Mar 05 01:51:28 PM PST 24 |
| Finished | Mar 05 01:51:41 PM PST 24 |
| Peak memory | 210992 kb |
| Host | smart-fba6b2a5-cd63-4031-9738-a8e817e12baa |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1123460596 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_alert_test.1123460596 |
| Directory | /workspace/22.rom_ctrl_alert_test/latest |
| Test location | /workspace/coverage/default/22.rom_ctrl_corrupt_sig_fatal_chk.2663389531 |
| Short name | T179 |
| Test name | |
| Test status | |
| Simulation time | 1428086313 ps |
| CPU time | 87.46 seconds |
| Started | Mar 05 01:51:25 PM PST 24 |
| Finished | Mar 05 01:52:52 PM PST 24 |
| Peak memory | 237236 kb |
| Host | smart-c848325a-2e4c-48f9-9f61-b6cee7321129 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2663389531 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_ corrupt_sig_fatal_chk.2663389531 |
| Directory | /workspace/22.rom_ctrl_corrupt_sig_fatal_chk/latest |
| Test location | /workspace/coverage/default/22.rom_ctrl_kmac_err_chk.3904366961 |
| Short name | T246 |
| Test name | |
| Test status | |
| Simulation time | 11196838065 ps |
| CPU time | 25.51 seconds |
| Started | Mar 05 01:51:34 PM PST 24 |
| Finished | Mar 05 01:52:00 PM PST 24 |
| Peak memory | 212312 kb |
| Host | smart-c69e4568-4862-4a42-96a4-f2b44a0a5b55 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3904366961 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_kmac_err_chk.3904366961 |
| Directory | /workspace/22.rom_ctrl_kmac_err_chk/latest |
| Test location | /workspace/coverage/default/22.rom_ctrl_max_throughput_chk.51039343 |
| Short name | T146 |
| Test name | |
| Test status | |
| Simulation time | 98588381 ps |
| CPU time | 5.94 seconds |
| Started | Mar 05 01:51:37 PM PST 24 |
| Finished | Mar 05 01:51:43 PM PST 24 |
| Peak memory | 210828 kb |
| Host | smart-a31ac495-10f7-4d12-9570-7dcf9627038f |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=51039343 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_max_throughput_chk.51039343 |
| Directory | /workspace/22.rom_ctrl_max_throughput_chk/latest |
| Test location | /workspace/coverage/default/22.rom_ctrl_smoke.3850827457 |
| Short name | T60 |
| Test name | |
| Test status | |
| Simulation time | 13355702813 ps |
| CPU time | 31.55 seconds |
| Started | Mar 05 01:51:28 PM PST 24 |
| Finished | Mar 05 01:51:59 PM PST 24 |
| Peak memory | 213592 kb |
| Host | smart-85c43354-1de4-4112-8b07-83c92bef7443 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3850827457 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_smoke.3850827457 |
| Directory | /workspace/22.rom_ctrl_smoke/latest |
| Test location | /workspace/coverage/default/22.rom_ctrl_stress_all.1424317845 |
| Short name | T300 |
| Test name | |
| Test status | |
| Simulation time | 3709107368 ps |
| CPU time | 19.21 seconds |
| Started | Mar 05 01:51:21 PM PST 24 |
| Finished | Mar 05 01:51:40 PM PST 24 |
| Peak memory | 211784 kb |
| Host | smart-4549a61f-c105-4882-972e-8cf610005f97 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1424317845 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm _name 22.rom_ctrl_stress_all.1424317845 |
| Directory | /workspace/22.rom_ctrl_stress_all/latest |
| Test location | /workspace/coverage/default/23.rom_ctrl_alert_test.1228604433 |
| Short name | T125 |
| Test name | |
| Test status | |
| Simulation time | 3134996402 ps |
| CPU time | 15.42 seconds |
| Started | Mar 05 01:51:45 PM PST 24 |
| Finished | Mar 05 01:52:01 PM PST 24 |
| Peak memory | 210996 kb |
| Host | smart-e84413bf-651c-4c2e-965b-09c76c0fba97 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1228604433 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_alert_test.1228604433 |
| Directory | /workspace/23.rom_ctrl_alert_test/latest |
| Test location | /workspace/coverage/default/23.rom_ctrl_corrupt_sig_fatal_chk.1306070835 |
| Short name | T319 |
| Test name | |
| Test status | |
| Simulation time | 790081328881 ps |
| CPU time | 450.15 seconds |
| Started | Mar 05 01:51:35 PM PST 24 |
| Finished | Mar 05 01:59:05 PM PST 24 |
| Peak memory | 234576 kb |
| Host | smart-e236c90b-9984-4532-b435-4a2aafc30d09 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1306070835 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_ corrupt_sig_fatal_chk.1306070835 |
| Directory | /workspace/23.rom_ctrl_corrupt_sig_fatal_chk/latest |
| Test location | /workspace/coverage/default/23.rom_ctrl_kmac_err_chk.3268339285 |
| Short name | T350 |
| Test name | |
| Test status | |
| Simulation time | 171843205 ps |
| CPU time | 9.43 seconds |
| Started | Mar 05 01:51:38 PM PST 24 |
| Finished | Mar 05 01:51:48 PM PST 24 |
| Peak memory | 211360 kb |
| Host | smart-2abdbfc6-6f75-4661-a901-30bf9b288539 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3268339285 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_kmac_err_chk.3268339285 |
| Directory | /workspace/23.rom_ctrl_kmac_err_chk/latest |
| Test location | /workspace/coverage/default/23.rom_ctrl_max_throughput_chk.2670060029 |
| Short name | T141 |
| Test name | |
| Test status | |
| Simulation time | 207883292 ps |
| CPU time | 5.24 seconds |
| Started | Mar 05 01:51:27 PM PST 24 |
| Finished | Mar 05 01:51:32 PM PST 24 |
| Peak memory | 210800 kb |
| Host | smart-27fa2c07-2d97-4d9a-a6d1-758d11e74060 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2670060029 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_max_throughput_chk.2670060029 |
| Directory | /workspace/23.rom_ctrl_max_throughput_chk/latest |
| Test location | /workspace/coverage/default/23.rom_ctrl_smoke.702785785 |
| Short name | T192 |
| Test name | |
| Test status | |
| Simulation time | 11328156095 ps |
| CPU time | 20.86 seconds |
| Started | Mar 05 01:51:32 PM PST 24 |
| Finished | Mar 05 01:51:53 PM PST 24 |
| Peak memory | 219044 kb |
| Host | smart-fe841237-77ba-4eb9-b34b-5fd16c7f9d7a |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=702785785 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_smoke.702785785 |
| Directory | /workspace/23.rom_ctrl_smoke/latest |
| Test location | /workspace/coverage/default/23.rom_ctrl_stress_all.2421304998 |
| Short name | T160 |
| Test name | |
| Test status | |
| Simulation time | 2392584032 ps |
| CPU time | 26.35 seconds |
| Started | Mar 05 01:51:33 PM PST 24 |
| Finished | Mar 05 01:52:00 PM PST 24 |
| Peak memory | 212508 kb |
| Host | smart-2650aa1d-6fb7-46a0-a9ec-b9cb3059706c |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2421304998 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm _name 23.rom_ctrl_stress_all.2421304998 |
| Directory | /workspace/23.rom_ctrl_stress_all/latest |
| Test location | /workspace/coverage/default/24.rom_ctrl_alert_test.2385368631 |
| Short name | T294 |
| Test name | |
| Test status | |
| Simulation time | 911355160 ps |
| CPU time | 10.18 seconds |
| Started | Mar 05 01:51:37 PM PST 24 |
| Finished | Mar 05 01:51:48 PM PST 24 |
| Peak memory | 210952 kb |
| Host | smart-881ce964-d36e-45ec-9823-b73a873dfa57 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2385368631 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_alert_test.2385368631 |
| Directory | /workspace/24.rom_ctrl_alert_test/latest |
| Test location | /workspace/coverage/default/24.rom_ctrl_corrupt_sig_fatal_chk.900480601 |
| Short name | T261 |
| Test name | |
| Test status | |
| Simulation time | 2646784326 ps |
| CPU time | 137.64 seconds |
| Started | Mar 05 01:51:35 PM PST 24 |
| Finished | Mar 05 01:53:53 PM PST 24 |
| Peak memory | 238524 kb |
| Host | smart-a59a89fe-e507-43d6-8f21-714b1aae4980 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=900480601 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt _sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_c orrupt_sig_fatal_chk.900480601 |
| Directory | /workspace/24.rom_ctrl_corrupt_sig_fatal_chk/latest |
| Test location | /workspace/coverage/default/24.rom_ctrl_kmac_err_chk.1813283782 |
| Short name | T271 |
| Test name | |
| Test status | |
| Simulation time | 1646012652 ps |
| CPU time | 12.39 seconds |
| Started | Mar 05 01:51:45 PM PST 24 |
| Finished | Mar 05 01:51:58 PM PST 24 |
| Peak memory | 210900 kb |
| Host | smart-d622277c-2936-4f9d-a488-faf62dd82a8a |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1813283782 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_kmac_err_chk.1813283782 |
| Directory | /workspace/24.rom_ctrl_kmac_err_chk/latest |
| Test location | /workspace/coverage/default/24.rom_ctrl_max_throughput_chk.3072576959 |
| Short name | T305 |
| Test name | |
| Test status | |
| Simulation time | 4974853213 ps |
| CPU time | 12.76 seconds |
| Started | Mar 05 01:51:33 PM PST 24 |
| Finished | Mar 05 01:51:46 PM PST 24 |
| Peak memory | 210864 kb |
| Host | smart-f5df2ab0-ec08-40af-8ba9-54a992de2ca7 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3072576959 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_max_throughput_chk.3072576959 |
| Directory | /workspace/24.rom_ctrl_max_throughput_chk/latest |
| Test location | /workspace/coverage/default/24.rom_ctrl_smoke.2213771003 |
| Short name | T220 |
| Test name | |
| Test status | |
| Simulation time | 843111194 ps |
| CPU time | 15.64 seconds |
| Started | Mar 05 01:51:35 PM PST 24 |
| Finished | Mar 05 01:51:51 PM PST 24 |
| Peak memory | 213192 kb |
| Host | smart-cce581b1-e5ce-46b4-9f69-bd96ae76af25 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2213771003 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_smoke.2213771003 |
| Directory | /workspace/24.rom_ctrl_smoke/latest |
| Test location | /workspace/coverage/default/24.rom_ctrl_stress_all.3913491233 |
| Short name | T312 |
| Test name | |
| Test status | |
| Simulation time | 6231574790 ps |
| CPU time | 26.02 seconds |
| Started | Mar 05 01:51:25 PM PST 24 |
| Finished | Mar 05 01:51:51 PM PST 24 |
| Peak memory | 216000 kb |
| Host | smart-e5096eac-4d40-42e3-8a0e-74a16cfb2d82 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3913491233 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm _name 24.rom_ctrl_stress_all.3913491233 |
| Directory | /workspace/24.rom_ctrl_stress_all/latest |
| Test location | /workspace/coverage/default/24.rom_ctrl_stress_all_with_rand_reset.2051253312 |
| Short name | T51 |
| Test name | |
| Test status | |
| Simulation time | 163868144050 ps |
| CPU time | 6569.31 seconds |
| Started | Mar 05 01:51:35 PM PST 24 |
| Finished | Mar 05 03:41:05 PM PST 24 |
| Peak memory | 265508 kb |
| Host | smart-4afc5aa7-6702-41e6-ac56-b7c1adb9d0e4 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2051253312 -assert nop ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_stress_all_with_rand_reset.2051253312 |
| Directory | /workspace/24.rom_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/25.rom_ctrl_alert_test.1711874770 |
| Short name | T62 |
| Test name | |
| Test status | |
| Simulation time | 998609516 ps |
| CPU time | 6.67 seconds |
| Started | Mar 05 01:51:37 PM PST 24 |
| Finished | Mar 05 01:51:44 PM PST 24 |
| Peak memory | 210932 kb |
| Host | smart-0160cb7e-d407-4dac-b38c-7e4c5406d7ea |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1711874770 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_alert_test.1711874770 |
| Directory | /workspace/25.rom_ctrl_alert_test/latest |
| Test location | /workspace/coverage/default/25.rom_ctrl_corrupt_sig_fatal_chk.3186556973 |
| Short name | T39 |
| Test name | |
| Test status | |
| Simulation time | 14109997367 ps |
| CPU time | 139.13 seconds |
| Started | Mar 05 01:51:31 PM PST 24 |
| Finished | Mar 05 01:53:50 PM PST 24 |
| Peak memory | 213256 kb |
| Host | smart-015c3d26-5393-4e34-b7dc-73173e0e4d15 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3186556973 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_ corrupt_sig_fatal_chk.3186556973 |
| Directory | /workspace/25.rom_ctrl_corrupt_sig_fatal_chk/latest |
| Test location | /workspace/coverage/default/25.rom_ctrl_kmac_err_chk.1762227330 |
| Short name | T19 |
| Test name | |
| Test status | |
| Simulation time | 995923106 ps |
| CPU time | 16.56 seconds |
| Started | Mar 05 01:51:34 PM PST 24 |
| Finished | Mar 05 01:51:51 PM PST 24 |
| Peak memory | 211408 kb |
| Host | smart-898645ce-5c82-4f1c-b391-572123c803e5 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1762227330 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_kmac_err_chk.1762227330 |
| Directory | /workspace/25.rom_ctrl_kmac_err_chk/latest |
| Test location | /workspace/coverage/default/25.rom_ctrl_max_throughput_chk.4043877517 |
| Short name | T321 |
| Test name | |
| Test status | |
| Simulation time | 1645433528 ps |
| CPU time | 8.16 seconds |
| Started | Mar 05 01:51:43 PM PST 24 |
| Finished | Mar 05 01:51:52 PM PST 24 |
| Peak memory | 210800 kb |
| Host | smart-f5904fb9-5500-4b85-afbd-9758e4d04650 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=4043877517 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_max_throughput_chk.4043877517 |
| Directory | /workspace/25.rom_ctrl_max_throughput_chk/latest |
| Test location | /workspace/coverage/default/25.rom_ctrl_smoke.3044369934 |
| Short name | T187 |
| Test name | |
| Test status | |
| Simulation time | 4653098257 ps |
| CPU time | 25.87 seconds |
| Started | Mar 05 01:51:36 PM PST 24 |
| Finished | Mar 05 01:52:02 PM PST 24 |
| Peak memory | 213340 kb |
| Host | smart-c097a492-827a-41e9-9cae-0292eed0aba7 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3044369934 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_smoke.3044369934 |
| Directory | /workspace/25.rom_ctrl_smoke/latest |
| Test location | /workspace/coverage/default/25.rom_ctrl_stress_all.3494971204 |
| Short name | T331 |
| Test name | |
| Test status | |
| Simulation time | 35758860675 ps |
| CPU time | 71.1 seconds |
| Started | Mar 05 01:51:48 PM PST 24 |
| Finished | Mar 05 01:52:59 PM PST 24 |
| Peak memory | 219136 kb |
| Host | smart-5aa422c7-90f1-44f3-aa03-2e4deb161968 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3494971204 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm _name 25.rom_ctrl_stress_all.3494971204 |
| Directory | /workspace/25.rom_ctrl_stress_all/latest |
| Test location | /workspace/coverage/default/25.rom_ctrl_stress_all_with_rand_reset.1069587981 |
| Short name | T11 |
| Test name | |
| Test status | |
| Simulation time | 363041573061 ps |
| CPU time | 3758.8 seconds |
| Started | Mar 05 01:51:31 PM PST 24 |
| Finished | Mar 05 02:54:11 PM PST 24 |
| Peak memory | 235592 kb |
| Host | smart-b8414ebc-8a8d-4c70-9cef-e4206b9ee2c2 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1069587981 -assert nop ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_stress_all_with_rand_reset.1069587981 |
| Directory | /workspace/25.rom_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/26.rom_ctrl_alert_test.1550416101 |
| Short name | T334 |
| Test name | |
| Test status | |
| Simulation time | 6715308359 ps |
| CPU time | 14.95 seconds |
| Started | Mar 05 01:51:42 PM PST 24 |
| Finished | Mar 05 01:51:57 PM PST 24 |
| Peak memory | 210976 kb |
| Host | smart-6e6cfee2-fa5e-4fcb-bb13-0a96925ce490 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1550416101 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_alert_test.1550416101 |
| Directory | /workspace/26.rom_ctrl_alert_test/latest |
| Test location | /workspace/coverage/default/26.rom_ctrl_kmac_err_chk.2519817644 |
| Short name | T226 |
| Test name | |
| Test status | |
| Simulation time | 1181678314 ps |
| CPU time | 16.87 seconds |
| Started | Mar 05 01:51:46 PM PST 24 |
| Finished | Mar 05 01:52:03 PM PST 24 |
| Peak memory | 211352 kb |
| Host | smart-1e664526-b850-4ae1-b96b-e13a59362111 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2519817644 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_kmac_err_chk.2519817644 |
| Directory | /workspace/26.rom_ctrl_kmac_err_chk/latest |
| Test location | /workspace/coverage/default/26.rom_ctrl_max_throughput_chk.3937859991 |
| Short name | T276 |
| Test name | |
| Test status | |
| Simulation time | 3690351816 ps |
| CPU time | 11.33 seconds |
| Started | Mar 05 01:52:00 PM PST 24 |
| Finished | Mar 05 01:52:11 PM PST 24 |
| Peak memory | 210864 kb |
| Host | smart-44f4ea17-500d-4e82-a0ae-8ccd3a756ed4 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3937859991 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_max_throughput_chk.3937859991 |
| Directory | /workspace/26.rom_ctrl_max_throughput_chk/latest |
| Test location | /workspace/coverage/default/26.rom_ctrl_smoke.3320947867 |
| Short name | T218 |
| Test name | |
| Test status | |
| Simulation time | 8531446331 ps |
| CPU time | 26.34 seconds |
| Started | Mar 05 01:51:33 PM PST 24 |
| Finished | Mar 05 01:51:59 PM PST 24 |
| Peak memory | 213156 kb |
| Host | smart-7df74a8f-ebac-4adc-a7e5-038d8674c8cf |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3320947867 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_smoke.3320947867 |
| Directory | /workspace/26.rom_ctrl_smoke/latest |
| Test location | /workspace/coverage/default/26.rom_ctrl_stress_all.2097247170 |
| Short name | T357 |
| Test name | |
| Test status | |
| Simulation time | 14776760155 ps |
| CPU time | 38.33 seconds |
| Started | Mar 05 01:51:32 PM PST 24 |
| Finished | Mar 05 01:52:11 PM PST 24 |
| Peak memory | 215096 kb |
| Host | smart-b8066d77-8b5e-498e-b6d7-5852f6754745 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2097247170 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm _name 26.rom_ctrl_stress_all.2097247170 |
| Directory | /workspace/26.rom_ctrl_stress_all/latest |
| Test location | /workspace/coverage/default/26.rom_ctrl_stress_all_with_rand_reset.3729496638 |
| Short name | T228 |
| Test name | |
| Test status | |
| Simulation time | 30251934314 ps |
| CPU time | 4023.04 seconds |
| Started | Mar 05 01:51:35 PM PST 24 |
| Finished | Mar 05 02:58:39 PM PST 24 |
| Peak memory | 233528 kb |
| Host | smart-f67339f1-0010-4ffc-8711-f1a503dbf5b4 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3729496638 -assert nop ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_stress_all_with_rand_reset.3729496638 |
| Directory | /workspace/26.rom_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/27.rom_ctrl_alert_test.1052742637 |
| Short name | T333 |
| Test name | |
| Test status | |
| Simulation time | 3545433152 ps |
| CPU time | 9.86 seconds |
| Started | Mar 05 01:51:28 PM PST 24 |
| Finished | Mar 05 01:51:37 PM PST 24 |
| Peak memory | 210976 kb |
| Host | smart-92d9fc94-b153-43f9-bc73-913976ed38ff |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1052742637 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_alert_test.1052742637 |
| Directory | /workspace/27.rom_ctrl_alert_test/latest |
| Test location | /workspace/coverage/default/27.rom_ctrl_corrupt_sig_fatal_chk.1972151118 |
| Short name | T287 |
| Test name | |
| Test status | |
| Simulation time | 114164609551 ps |
| CPU time | 253.82 seconds |
| Started | Mar 05 01:51:37 PM PST 24 |
| Finished | Mar 05 01:55:51 PM PST 24 |
| Peak memory | 228332 kb |
| Host | smart-94c9330a-78e3-4db6-8900-559309e9c9f4 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1972151118 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_ corrupt_sig_fatal_chk.1972151118 |
| Directory | /workspace/27.rom_ctrl_corrupt_sig_fatal_chk/latest |
| Test location | /workspace/coverage/default/27.rom_ctrl_kmac_err_chk.781788054 |
| Short name | T304 |
| Test name | |
| Test status | |
| Simulation time | 16033956295 ps |
| CPU time | 32.04 seconds |
| Started | Mar 05 01:51:36 PM PST 24 |
| Finished | Mar 05 01:52:08 PM PST 24 |
| Peak memory | 211800 kb |
| Host | smart-1dacedf1-6825-4a5c-b19b-fd3a05dd9606 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=781788054 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_kmac_err_chk.781788054 |
| Directory | /workspace/27.rom_ctrl_kmac_err_chk/latest |
| Test location | /workspace/coverage/default/27.rom_ctrl_max_throughput_chk.4082168765 |
| Short name | T128 |
| Test name | |
| Test status | |
| Simulation time | 1735365242 ps |
| CPU time | 15.21 seconds |
| Started | Mar 05 01:51:26 PM PST 24 |
| Finished | Mar 05 01:51:41 PM PST 24 |
| Peak memory | 210624 kb |
| Host | smart-76298cbf-911f-42a6-803d-f5f5ba0a8c5a |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=4082168765 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_max_throughput_chk.4082168765 |
| Directory | /workspace/27.rom_ctrl_max_throughput_chk/latest |
| Test location | /workspace/coverage/default/27.rom_ctrl_smoke.2504028192 |
| Short name | T186 |
| Test name | |
| Test status | |
| Simulation time | 14018132072 ps |
| CPU time | 29.48 seconds |
| Started | Mar 05 01:51:29 PM PST 24 |
| Finished | Mar 05 01:51:58 PM PST 24 |
| Peak memory | 213440 kb |
| Host | smart-1ba7ead1-5aa8-4223-9c00-9343161be4e6 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2504028192 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_smoke.2504028192 |
| Directory | /workspace/27.rom_ctrl_smoke/latest |
| Test location | /workspace/coverage/default/27.rom_ctrl_stress_all.626916478 |
| Short name | T199 |
| Test name | |
| Test status | |
| Simulation time | 2257388877 ps |
| CPU time | 25.28 seconds |
| Started | Mar 05 01:51:37 PM PST 24 |
| Finished | Mar 05 01:52:03 PM PST 24 |
| Peak memory | 213996 kb |
| Host | smart-278166c0-50de-42f8-b14f-be2436adeb68 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=626916478 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test + UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 27.rom_ctrl_stress_all.626916478 |
| Directory | /workspace/27.rom_ctrl_stress_all/latest |
| Test location | /workspace/coverage/default/28.rom_ctrl_alert_test.917595750 |
| Short name | T184 |
| Test name | |
| Test status | |
| Simulation time | 6915303688 ps |
| CPU time | 14.6 seconds |
| Started | Mar 05 01:51:39 PM PST 24 |
| Finished | Mar 05 01:51:54 PM PST 24 |
| Peak memory | 211104 kb |
| Host | smart-f1b9f8e8-7e6b-4cbe-9a1c-332bc7e2386f |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=917595750 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_alert_test.917595750 |
| Directory | /workspace/28.rom_ctrl_alert_test/latest |
| Test location | /workspace/coverage/default/28.rom_ctrl_corrupt_sig_fatal_chk.3228275590 |
| Short name | T180 |
| Test name | |
| Test status | |
| Simulation time | 214891211367 ps |
| CPU time | 543.8 seconds |
| Started | Mar 05 01:51:26 PM PST 24 |
| Finished | Mar 05 02:00:30 PM PST 24 |
| Peak memory | 212268 kb |
| Host | smart-34a40fa3-c88f-4be1-af60-37c4e0e06db8 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3228275590 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_ corrupt_sig_fatal_chk.3228275590 |
| Directory | /workspace/28.rom_ctrl_corrupt_sig_fatal_chk/latest |
| Test location | /workspace/coverage/default/28.rom_ctrl_kmac_err_chk.3245471849 |
| Short name | T354 |
| Test name | |
| Test status | |
| Simulation time | 334148509 ps |
| CPU time | 9.67 seconds |
| Started | Mar 05 01:51:24 PM PST 24 |
| Finished | Mar 05 01:51:33 PM PST 24 |
| Peak memory | 211416 kb |
| Host | smart-52307b0a-3946-4f4c-9a20-436e4728ef30 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3245471849 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_kmac_err_chk.3245471849 |
| Directory | /workspace/28.rom_ctrl_kmac_err_chk/latest |
| Test location | /workspace/coverage/default/28.rom_ctrl_max_throughput_chk.1996105610 |
| Short name | T197 |
| Test name | |
| Test status | |
| Simulation time | 101481011 ps |
| CPU time | 5.5 seconds |
| Started | Mar 05 01:51:31 PM PST 24 |
| Finished | Mar 05 01:51:37 PM PST 24 |
| Peak memory | 210780 kb |
| Host | smart-4280885b-daab-43d9-89bd-83e24a64409e |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1996105610 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_max_throughput_chk.1996105610 |
| Directory | /workspace/28.rom_ctrl_max_throughput_chk/latest |
| Test location | /workspace/coverage/default/28.rom_ctrl_smoke.336867547 |
| Short name | T154 |
| Test name | |
| Test status | |
| Simulation time | 10587422273 ps |
| CPU time | 24.85 seconds |
| Started | Mar 05 01:51:25 PM PST 24 |
| Finished | Mar 05 01:51:50 PM PST 24 |
| Peak memory | 213104 kb |
| Host | smart-a24d2c77-96b5-40c5-b522-aa1087cec6d4 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=336867547 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_smoke.336867547 |
| Directory | /workspace/28.rom_ctrl_smoke/latest |
| Test location | /workspace/coverage/default/28.rom_ctrl_stress_all.193110631 |
| Short name | T9 |
| Test name | |
| Test status | |
| Simulation time | 1420169620 ps |
| CPU time | 19.54 seconds |
| Started | Mar 05 01:51:37 PM PST 24 |
| Finished | Mar 05 01:51:57 PM PST 24 |
| Peak memory | 218992 kb |
| Host | smart-f45db1e8-0a81-4c0b-8f9d-2e40162a543b |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=193110631 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test + UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 28.rom_ctrl_stress_all.193110631 |
| Directory | /workspace/28.rom_ctrl_stress_all/latest |
| Test location | /workspace/coverage/default/29.rom_ctrl_alert_test.2684999816 |
| Short name | T33 |
| Test name | |
| Test status | |
| Simulation time | 85612313 ps |
| CPU time | 4.37 seconds |
| Started | Mar 05 01:51:36 PM PST 24 |
| Finished | Mar 05 01:51:41 PM PST 24 |
| Peak memory | 210964 kb |
| Host | smart-a906003d-8e9f-44ae-b060-4d93fd286594 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2684999816 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_alert_test.2684999816 |
| Directory | /workspace/29.rom_ctrl_alert_test/latest |
| Test location | /workspace/coverage/default/29.rom_ctrl_corrupt_sig_fatal_chk.341880616 |
| Short name | T364 |
| Test name | |
| Test status | |
| Simulation time | 1654651024 ps |
| CPU time | 91.04 seconds |
| Started | Mar 05 01:51:31 PM PST 24 |
| Finished | Mar 05 01:53:02 PM PST 24 |
| Peak memory | 213216 kb |
| Host | smart-71fb4953-b3f3-4c45-a21e-9e960d1beec5 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=341880616 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt _sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_c orrupt_sig_fatal_chk.341880616 |
| Directory | /workspace/29.rom_ctrl_corrupt_sig_fatal_chk/latest |
| Test location | /workspace/coverage/default/29.rom_ctrl_kmac_err_chk.1011016242 |
| Short name | T23 |
| Test name | |
| Test status | |
| Simulation time | 7340982458 ps |
| CPU time | 31.11 seconds |
| Started | Mar 05 01:51:32 PM PST 24 |
| Finished | Mar 05 01:52:03 PM PST 24 |
| Peak memory | 212012 kb |
| Host | smart-2fd99905-cb72-43ed-99bd-5b1e1979804c |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1011016242 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_kmac_err_chk.1011016242 |
| Directory | /workspace/29.rom_ctrl_kmac_err_chk/latest |
| Test location | /workspace/coverage/default/29.rom_ctrl_max_throughput_chk.902497624 |
| Short name | T274 |
| Test name | |
| Test status | |
| Simulation time | 5246551120 ps |
| CPU time | 17.19 seconds |
| Started | Mar 05 01:51:40 PM PST 24 |
| Finished | Mar 05 01:51:58 PM PST 24 |
| Peak memory | 210940 kb |
| Host | smart-b4f18fcd-e1c2-4061-a66b-5dffa2f6aa9a |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=902497624 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_max_throughput_chk.902497624 |
| Directory | /workspace/29.rom_ctrl_max_throughput_chk/latest |
| Test location | /workspace/coverage/default/29.rom_ctrl_smoke.106333460 |
| Short name | T138 |
| Test name | |
| Test status | |
| Simulation time | 3250467665 ps |
| CPU time | 28.94 seconds |
| Started | Mar 05 01:51:50 PM PST 24 |
| Finished | Mar 05 01:52:20 PM PST 24 |
| Peak memory | 212536 kb |
| Host | smart-67a0f076-dca8-429b-abe7-471046f2d88d |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=106333460 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_smoke.106333460 |
| Directory | /workspace/29.rom_ctrl_smoke/latest |
| Test location | /workspace/coverage/default/29.rom_ctrl_stress_all.3355911647 |
| Short name | T277 |
| Test name | |
| Test status | |
| Simulation time | 1310292000 ps |
| CPU time | 33.78 seconds |
| Started | Mar 05 01:51:34 PM PST 24 |
| Finished | Mar 05 01:52:08 PM PST 24 |
| Peak memory | 215052 kb |
| Host | smart-048289ef-fe99-4a8d-8493-9ddcec8d0700 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3355911647 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm _name 29.rom_ctrl_stress_all.3355911647 |
| Directory | /workspace/29.rom_ctrl_stress_all/latest |
| Test location | /workspace/coverage/default/3.rom_ctrl_alert_test.1955110645 |
| Short name | T200 |
| Test name | |
| Test status | |
| Simulation time | 1868550212 ps |
| CPU time | 7.05 seconds |
| Started | Mar 05 01:51:27 PM PST 24 |
| Finished | Mar 05 01:51:35 PM PST 24 |
| Peak memory | 210880 kb |
| Host | smart-c3780d02-e78d-4903-8657-7617335ee3f4 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1955110645 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_alert_test.1955110645 |
| Directory | /workspace/3.rom_ctrl_alert_test/latest |
| Test location | /workspace/coverage/default/3.rom_ctrl_kmac_err_chk.3730829866 |
| Short name | T318 |
| Test name | |
| Test status | |
| Simulation time | 2738372823 ps |
| CPU time | 18.58 seconds |
| Started | Mar 05 01:51:08 PM PST 24 |
| Finished | Mar 05 01:51:27 PM PST 24 |
| Peak memory | 211392 kb |
| Host | smart-7c470fb4-aa05-4147-b7a4-58549501722a |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3730829866 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_kmac_err_chk.3730829866 |
| Directory | /workspace/3.rom_ctrl_kmac_err_chk/latest |
| Test location | /workspace/coverage/default/3.rom_ctrl_max_throughput_chk.579188566 |
| Short name | T308 |
| Test name | |
| Test status | |
| Simulation time | 1195458034 ps |
| CPU time | 12.63 seconds |
| Started | Mar 05 01:51:14 PM PST 24 |
| Finished | Mar 05 01:51:27 PM PST 24 |
| Peak memory | 210788 kb |
| Host | smart-0cfa5b62-6496-4190-b87d-ee6a79e258b8 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=579188566 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_max_throughput_chk.579188566 |
| Directory | /workspace/3.rom_ctrl_max_throughput_chk/latest |
| Test location | /workspace/coverage/default/3.rom_ctrl_sec_cm.2305396144 |
| Short name | T32 |
| Test name | |
| Test status | |
| Simulation time | 2758927133 ps |
| CPU time | 55.92 seconds |
| Started | Mar 05 01:51:04 PM PST 24 |
| Finished | Mar 05 01:52:00 PM PST 24 |
| Peak memory | 235288 kb |
| Host | smart-c0159a05-9264-4ccc-b710-95ac70b9c55a |
| User | root |
| Command | /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2305396144 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_sec_cm.2305396144 |
| Directory | /workspace/3.rom_ctrl_sec_cm/latest |
| Test location | /workspace/coverage/default/3.rom_ctrl_smoke.1652354378 |
| Short name | T363 |
| Test name | |
| Test status | |
| Simulation time | 7243099683 ps |
| CPU time | 20.38 seconds |
| Started | Mar 05 01:51:20 PM PST 24 |
| Finished | Mar 05 01:51:41 PM PST 24 |
| Peak memory | 212444 kb |
| Host | smart-af1033d4-c440-4c84-93ff-b8cb8a301820 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1652354378 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_smoke.1652354378 |
| Directory | /workspace/3.rom_ctrl_smoke/latest |
| Test location | /workspace/coverage/default/3.rom_ctrl_stress_all.93274888 |
| Short name | T195 |
| Test name | |
| Test status | |
| Simulation time | 5729276804 ps |
| CPU time | 78.6 seconds |
| Started | Mar 05 01:51:13 PM PST 24 |
| Finished | Mar 05 01:52:31 PM PST 24 |
| Peak memory | 216308 kb |
| Host | smart-f017116a-7671-4fcf-9467-8c8374f369b4 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=93274888 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +U VM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n ame 3.rom_ctrl_stress_all.93274888 |
| Directory | /workspace/3.rom_ctrl_stress_all/latest |
| Test location | /workspace/coverage/default/3.rom_ctrl_stress_all_with_rand_reset.3844843760 |
| Short name | T293 |
| Test name | |
| Test status | |
| Simulation time | 38803801791 ps |
| CPU time | 1049.36 seconds |
| Started | Mar 05 01:51:11 PM PST 24 |
| Finished | Mar 05 02:08:41 PM PST 24 |
| Peak memory | 235528 kb |
| Host | smart-6e8f4a13-2f63-4863-8ffc-3cc5ca955853 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3844843760 -assert nop ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_stress_all_with_rand_reset.3844843760 |
| Directory | /workspace/3.rom_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/30.rom_ctrl_alert_test.2405985445 |
| Short name | T118 |
| Test name | |
| Test status | |
| Simulation time | 2754685571 ps |
| CPU time | 12.05 seconds |
| Started | Mar 05 01:51:44 PM PST 24 |
| Finished | Mar 05 01:51:57 PM PST 24 |
| Peak memory | 211020 kb |
| Host | smart-9f6453d9-7e93-4b88-a356-cefa6e229189 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2405985445 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_alert_test.2405985445 |
| Directory | /workspace/30.rom_ctrl_alert_test/latest |
| Test location | /workspace/coverage/default/30.rom_ctrl_corrupt_sig_fatal_chk.2009018543 |
| Short name | T212 |
| Test name | |
| Test status | |
| Simulation time | 15798383734 ps |
| CPU time | 266.94 seconds |
| Started | Mar 05 01:51:40 PM PST 24 |
| Finished | Mar 05 01:56:08 PM PST 24 |
| Peak memory | 228224 kb |
| Host | smart-ba2a7633-c9f6-4552-9d9d-321fec174516 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2009018543 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_ corrupt_sig_fatal_chk.2009018543 |
| Directory | /workspace/30.rom_ctrl_corrupt_sig_fatal_chk/latest |
| Test location | /workspace/coverage/default/30.rom_ctrl_kmac_err_chk.341358546 |
| Short name | T42 |
| Test name | |
| Test status | |
| Simulation time | 3102362162 ps |
| CPU time | 14.32 seconds |
| Started | Mar 05 01:51:36 PM PST 24 |
| Finished | Mar 05 01:51:51 PM PST 24 |
| Peak memory | 211696 kb |
| Host | smart-cb5ed433-091d-4c6f-ac1e-4e95f8cfc576 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=341358546 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_kmac_err_chk.341358546 |
| Directory | /workspace/30.rom_ctrl_kmac_err_chk/latest |
| Test location | /workspace/coverage/default/30.rom_ctrl_max_throughput_chk.3532897144 |
| Short name | T313 |
| Test name | |
| Test status | |
| Simulation time | 457756307 ps |
| CPU time | 8.19 seconds |
| Started | Mar 05 01:51:44 PM PST 24 |
| Finished | Mar 05 01:51:53 PM PST 24 |
| Peak memory | 210796 kb |
| Host | smart-86c47fcc-adae-4955-b37e-7ca5a8aa16a6 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3532897144 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_max_throughput_chk.3532897144 |
| Directory | /workspace/30.rom_ctrl_max_throughput_chk/latest |
| Test location | /workspace/coverage/default/30.rom_ctrl_smoke.897665342 |
| Short name | T130 |
| Test name | |
| Test status | |
| Simulation time | 10205644335 ps |
| CPU time | 20.98 seconds |
| Started | Mar 05 01:51:27 PM PST 24 |
| Finished | Mar 05 01:51:48 PM PST 24 |
| Peak memory | 213968 kb |
| Host | smart-eaa04088-6835-4c34-9875-02e0dcd2529d |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=897665342 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_smoke.897665342 |
| Directory | /workspace/30.rom_ctrl_smoke/latest |
| Test location | /workspace/coverage/default/30.rom_ctrl_stress_all.2623811375 |
| Short name | T133 |
| Test name | |
| Test status | |
| Simulation time | 6186227058 ps |
| CPU time | 54.03 seconds |
| Started | Mar 05 01:51:52 PM PST 24 |
| Finished | Mar 05 01:52:47 PM PST 24 |
| Peak memory | 219124 kb |
| Host | smart-21e27a63-0b0c-4080-8e77-a2b71890d274 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2623811375 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm _name 30.rom_ctrl_stress_all.2623811375 |
| Directory | /workspace/30.rom_ctrl_stress_all/latest |
| Test location | /workspace/coverage/default/30.rom_ctrl_stress_all_with_rand_reset.1495537458 |
| Short name | T96 |
| Test name | |
| Test status | |
| Simulation time | 73486107258 ps |
| CPU time | 8734.93 seconds |
| Started | Mar 05 01:51:36 PM PST 24 |
| Finished | Mar 05 04:17:12 PM PST 24 |
| Peak memory | 235028 kb |
| Host | smart-713456c3-648c-4909-9339-bb992cab7303 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1495537458 -assert nop ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_stress_all_with_rand_reset.1495537458 |
| Directory | /workspace/30.rom_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/31.rom_ctrl_alert_test.68998248 |
| Short name | T339 |
| Test name | |
| Test status | |
| Simulation time | 347653026 ps |
| CPU time | 4.06 seconds |
| Started | Mar 05 01:51:40 PM PST 24 |
| Finished | Mar 05 01:51:46 PM PST 24 |
| Peak memory | 210936 kb |
| Host | smart-e0e45f0f-99c5-46bc-93af-a5e649cce766 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=68998248 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_alert_test.68998248 |
| Directory | /workspace/31.rom_ctrl_alert_test/latest |
| Test location | /workspace/coverage/default/31.rom_ctrl_corrupt_sig_fatal_chk.1398513988 |
| Short name | T162 |
| Test name | |
| Test status | |
| Simulation time | 107493245374 ps |
| CPU time | 161.05 seconds |
| Started | Mar 05 01:51:51 PM PST 24 |
| Finished | Mar 05 01:54:32 PM PST 24 |
| Peak memory | 239716 kb |
| Host | smart-9d244d64-c61b-4ecb-86ce-6a9ac6d75ca9 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1398513988 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_ corrupt_sig_fatal_chk.1398513988 |
| Directory | /workspace/31.rom_ctrl_corrupt_sig_fatal_chk/latest |
| Test location | /workspace/coverage/default/31.rom_ctrl_kmac_err_chk.2806206565 |
| Short name | T268 |
| Test name | |
| Test status | |
| Simulation time | 3765247212 ps |
| CPU time | 21.07 seconds |
| Started | Mar 05 01:51:41 PM PST 24 |
| Finished | Mar 05 01:52:03 PM PST 24 |
| Peak memory | 210936 kb |
| Host | smart-74f5bee5-eed0-4321-a56c-c56eef549edd |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2806206565 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_kmac_err_chk.2806206565 |
| Directory | /workspace/31.rom_ctrl_kmac_err_chk/latest |
| Test location | /workspace/coverage/default/31.rom_ctrl_max_throughput_chk.3460589669 |
| Short name | T258 |
| Test name | |
| Test status | |
| Simulation time | 1113218057 ps |
| CPU time | 12.27 seconds |
| Started | Mar 05 01:51:37 PM PST 24 |
| Finished | Mar 05 01:51:50 PM PST 24 |
| Peak memory | 210820 kb |
| Host | smart-6a180dc5-1bd7-493c-bfaa-e48b9ac7a268 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3460589669 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_max_throughput_chk.3460589669 |
| Directory | /workspace/31.rom_ctrl_max_throughput_chk/latest |
| Test location | /workspace/coverage/default/31.rom_ctrl_smoke.3985511286 |
| Short name | T38 |
| Test name | |
| Test status | |
| Simulation time | 1790012832 ps |
| CPU time | 13.03 seconds |
| Started | Mar 05 01:51:34 PM PST 24 |
| Finished | Mar 05 01:51:47 PM PST 24 |
| Peak memory | 212732 kb |
| Host | smart-cffa0fcd-696b-432d-a49c-0030774d918b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3985511286 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_smoke.3985511286 |
| Directory | /workspace/31.rom_ctrl_smoke/latest |
| Test location | /workspace/coverage/default/31.rom_ctrl_stress_all.32284961 |
| Short name | T224 |
| Test name | |
| Test status | |
| Simulation time | 286437439 ps |
| CPU time | 16.55 seconds |
| Started | Mar 05 01:51:45 PM PST 24 |
| Finished | Mar 05 01:52:07 PM PST 24 |
| Peak memory | 213304 kb |
| Host | smart-23c64d1a-e2e4-42fb-aabf-726b9d3381f5 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32284961 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +U VM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n ame 31.rom_ctrl_stress_all.32284961 |
| Directory | /workspace/31.rom_ctrl_stress_all/latest |
| Test location | /workspace/coverage/default/32.rom_ctrl_alert_test.347312392 |
| Short name | T240 |
| Test name | |
| Test status | |
| Simulation time | 6818722140 ps |
| CPU time | 14.51 seconds |
| Started | Mar 05 01:51:52 PM PST 24 |
| Finished | Mar 05 01:52:07 PM PST 24 |
| Peak memory | 211020 kb |
| Host | smart-6389626c-efab-49c1-8bc6-5d2791827404 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=347312392 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_alert_test.347312392 |
| Directory | /workspace/32.rom_ctrl_alert_test/latest |
| Test location | /workspace/coverage/default/32.rom_ctrl_corrupt_sig_fatal_chk.1268311830 |
| Short name | T204 |
| Test name | |
| Test status | |
| Simulation time | 28060992344 ps |
| CPU time | 251.71 seconds |
| Started | Mar 05 01:51:36 PM PST 24 |
| Finished | Mar 05 01:55:49 PM PST 24 |
| Peak memory | 230440 kb |
| Host | smart-867449f7-0b2b-4cef-afed-f5d45aafbdd3 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1268311830 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_ corrupt_sig_fatal_chk.1268311830 |
| Directory | /workspace/32.rom_ctrl_corrupt_sig_fatal_chk/latest |
| Test location | /workspace/coverage/default/32.rom_ctrl_kmac_err_chk.3797721602 |
| Short name | T289 |
| Test name | |
| Test status | |
| Simulation time | 16947584971 ps |
| CPU time | 34.95 seconds |
| Started | Mar 05 01:51:50 PM PST 24 |
| Finished | Mar 05 01:52:25 PM PST 24 |
| Peak memory | 211796 kb |
| Host | smart-aebd4e06-b275-4a86-9b76-45198da0d519 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3797721602 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_kmac_err_chk.3797721602 |
| Directory | /workspace/32.rom_ctrl_kmac_err_chk/latest |
| Test location | /workspace/coverage/default/32.rom_ctrl_max_throughput_chk.2212063890 |
| Short name | T257 |
| Test name | |
| Test status | |
| Simulation time | 1267379214 ps |
| CPU time | 13.11 seconds |
| Started | Mar 05 01:51:37 PM PST 24 |
| Finished | Mar 05 01:51:51 PM PST 24 |
| Peak memory | 210788 kb |
| Host | smart-d8d56a03-559c-4376-8992-9cd2912bd58e |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2212063890 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_max_throughput_chk.2212063890 |
| Directory | /workspace/32.rom_ctrl_max_throughput_chk/latest |
| Test location | /workspace/coverage/default/32.rom_ctrl_smoke.4243430737 |
| Short name | T303 |
| Test name | |
| Test status | |
| Simulation time | 4321101619 ps |
| CPU time | 30.14 seconds |
| Started | Mar 05 01:51:48 PM PST 24 |
| Finished | Mar 05 01:52:19 PM PST 24 |
| Peak memory | 213360 kb |
| Host | smart-670a9a8b-7733-45f8-b7f3-0cb12a90fd3a |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4243430737 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_smoke.4243430737 |
| Directory | /workspace/32.rom_ctrl_smoke/latest |
| Test location | /workspace/coverage/default/32.rom_ctrl_stress_all.3663609888 |
| Short name | T306 |
| Test name | |
| Test status | |
| Simulation time | 84578141241 ps |
| CPU time | 42.05 seconds |
| Started | Mar 05 01:51:48 PM PST 24 |
| Finished | Mar 05 01:52:30 PM PST 24 |
| Peak memory | 213892 kb |
| Host | smart-2fa3230d-0b65-423c-852f-215b4cf904cc |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3663609888 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm _name 32.rom_ctrl_stress_all.3663609888 |
| Directory | /workspace/32.rom_ctrl_stress_all/latest |
| Test location | /workspace/coverage/default/33.rom_ctrl_alert_test.1325460547 |
| Short name | T156 |
| Test name | |
| Test status | |
| Simulation time | 3199013018 ps |
| CPU time | 13.56 seconds |
| Started | Mar 05 01:52:00 PM PST 24 |
| Finished | Mar 05 01:52:14 PM PST 24 |
| Peak memory | 211020 kb |
| Host | smart-b6ea2c60-dec3-4210-89ed-47da24d166ca |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1325460547 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_alert_test.1325460547 |
| Directory | /workspace/33.rom_ctrl_alert_test/latest |
| Test location | /workspace/coverage/default/33.rom_ctrl_corrupt_sig_fatal_chk.1978876019 |
| Short name | T309 |
| Test name | |
| Test status | |
| Simulation time | 11108596204 ps |
| CPU time | 191.44 seconds |
| Started | Mar 05 01:51:37 PM PST 24 |
| Finished | Mar 05 01:54:54 PM PST 24 |
| Peak memory | 219376 kb |
| Host | smart-8858bbb0-36ed-466c-be40-87d33d565343 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1978876019 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_ corrupt_sig_fatal_chk.1978876019 |
| Directory | /workspace/33.rom_ctrl_corrupt_sig_fatal_chk/latest |
| Test location | /workspace/coverage/default/33.rom_ctrl_kmac_err_chk.1165805623 |
| Short name | T210 |
| Test name | |
| Test status | |
| Simulation time | 10560964906 ps |
| CPU time | 18.67 seconds |
| Started | Mar 05 01:51:38 PM PST 24 |
| Finished | Mar 05 01:51:57 PM PST 24 |
| Peak memory | 212200 kb |
| Host | smart-ebbc6937-953f-425a-81b8-f7052b66e2a1 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1165805623 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_kmac_err_chk.1165805623 |
| Directory | /workspace/33.rom_ctrl_kmac_err_chk/latest |
| Test location | /workspace/coverage/default/33.rom_ctrl_max_throughput_chk.981306401 |
| Short name | T310 |
| Test name | |
| Test status | |
| Simulation time | 1770703862 ps |
| CPU time | 15.51 seconds |
| Started | Mar 05 01:51:42 PM PST 24 |
| Finished | Mar 05 01:51:57 PM PST 24 |
| Peak memory | 210856 kb |
| Host | smart-4109cb37-694b-4417-862c-0def0919ac22 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=981306401 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_max_throughput_chk.981306401 |
| Directory | /workspace/33.rom_ctrl_max_throughput_chk/latest |
| Test location | /workspace/coverage/default/33.rom_ctrl_smoke.1181811441 |
| Short name | T37 |
| Test name | |
| Test status | |
| Simulation time | 182930495 ps |
| CPU time | 9.8 seconds |
| Started | Mar 05 01:51:48 PM PST 24 |
| Finished | Mar 05 01:51:58 PM PST 24 |
| Peak memory | 212552 kb |
| Host | smart-0eb4a774-529e-45a6-8ca0-29dbfb1df0fa |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1181811441 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_smoke.1181811441 |
| Directory | /workspace/33.rom_ctrl_smoke/latest |
| Test location | /workspace/coverage/default/33.rom_ctrl_stress_all.3889165894 |
| Short name | T147 |
| Test name | |
| Test status | |
| Simulation time | 20182889356 ps |
| CPU time | 60.58 seconds |
| Started | Mar 05 01:51:36 PM PST 24 |
| Finished | Mar 05 01:52:37 PM PST 24 |
| Peak memory | 218476 kb |
| Host | smart-2cb3417b-33c5-4289-877d-bfbe89613a97 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3889165894 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm _name 33.rom_ctrl_stress_all.3889165894 |
| Directory | /workspace/33.rom_ctrl_stress_all/latest |
| Test location | /workspace/coverage/default/33.rom_ctrl_stress_all_with_rand_reset.2525099582 |
| Short name | T223 |
| Test name | |
| Test status | |
| Simulation time | 53327068824 ps |
| CPU time | 554.44 seconds |
| Started | Mar 05 01:51:49 PM PST 24 |
| Finished | Mar 05 02:01:05 PM PST 24 |
| Peak memory | 235580 kb |
| Host | smart-3dd2b29c-62f9-42ca-b32c-f137618b61bf |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2525099582 -assert nop ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_stress_all_with_rand_reset.2525099582 |
| Directory | /workspace/33.rom_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/34.rom_ctrl_alert_test.1440300068 |
| Short name | T259 |
| Test name | |
| Test status | |
| Simulation time | 88120936 ps |
| CPU time | 4.25 seconds |
| Started | Mar 05 01:51:39 PM PST 24 |
| Finished | Mar 05 01:51:44 PM PST 24 |
| Peak memory | 210920 kb |
| Host | smart-ed2acd41-94bc-49bf-9ad1-8a1130215ecc |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1440300068 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_alert_test.1440300068 |
| Directory | /workspace/34.rom_ctrl_alert_test/latest |
| Test location | /workspace/coverage/default/34.rom_ctrl_corrupt_sig_fatal_chk.905337811 |
| Short name | T315 |
| Test name | |
| Test status | |
| Simulation time | 87897511567 ps |
| CPU time | 232.74 seconds |
| Started | Mar 05 01:51:38 PM PST 24 |
| Finished | Mar 05 01:55:31 PM PST 24 |
| Peak memory | 237368 kb |
| Host | smart-42efaa87-7558-41ec-9121-54119cfa7da4 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=905337811 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt _sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_c orrupt_sig_fatal_chk.905337811 |
| Directory | /workspace/34.rom_ctrl_corrupt_sig_fatal_chk/latest |
| Test location | /workspace/coverage/default/34.rom_ctrl_kmac_err_chk.365823060 |
| Short name | T244 |
| Test name | |
| Test status | |
| Simulation time | 922906010 ps |
| CPU time | 9.25 seconds |
| Started | Mar 05 01:51:43 PM PST 24 |
| Finished | Mar 05 01:51:53 PM PST 24 |
| Peak memory | 211324 kb |
| Host | smart-7750463d-d918-4a6d-be14-6522350049eb |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=365823060 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_kmac_err_chk.365823060 |
| Directory | /workspace/34.rom_ctrl_kmac_err_chk/latest |
| Test location | /workspace/coverage/default/34.rom_ctrl_max_throughput_chk.1087617783 |
| Short name | T148 |
| Test name | |
| Test status | |
| Simulation time | 16552489096 ps |
| CPU time | 16.77 seconds |
| Started | Mar 05 01:51:34 PM PST 24 |
| Finished | Mar 05 01:51:51 PM PST 24 |
| Peak memory | 210840 kb |
| Host | smart-48cc48dc-137e-4b5c-81a9-5d43d598c60b |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1087617783 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_max_throughput_chk.1087617783 |
| Directory | /workspace/34.rom_ctrl_max_throughput_chk/latest |
| Test location | /workspace/coverage/default/34.rom_ctrl_smoke.190200919 |
| Short name | T185 |
| Test name | |
| Test status | |
| Simulation time | 2373592216 ps |
| CPU time | 19.28 seconds |
| Started | Mar 05 01:51:29 PM PST 24 |
| Finished | Mar 05 01:51:48 PM PST 24 |
| Peak memory | 211812 kb |
| Host | smart-327638e8-f111-4d2f-954e-f9b4ced45ffd |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=190200919 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_smoke.190200919 |
| Directory | /workspace/34.rom_ctrl_smoke/latest |
| Test location | /workspace/coverage/default/34.rom_ctrl_stress_all.2977367090 |
| Short name | T234 |
| Test name | |
| Test status | |
| Simulation time | 195612945 ps |
| CPU time | 6.77 seconds |
| Started | Mar 05 01:51:38 PM PST 24 |
| Finished | Mar 05 01:51:45 PM PST 24 |
| Peak memory | 210732 kb |
| Host | smart-cdd250cc-cb91-4a17-97fb-afc5d3cbd205 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2977367090 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm _name 34.rom_ctrl_stress_all.2977367090 |
| Directory | /workspace/34.rom_ctrl_stress_all/latest |
| Test location | /workspace/coverage/default/35.rom_ctrl_alert_test.823693710 |
| Short name | T225 |
| Test name | |
| Test status | |
| Simulation time | 1740646794 ps |
| CPU time | 14.31 seconds |
| Started | Mar 05 01:51:37 PM PST 24 |
| Finished | Mar 05 01:51:52 PM PST 24 |
| Peak memory | 210896 kb |
| Host | smart-074285bf-6664-4a35-8b51-bc9d2e80425a |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=823693710 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_alert_test.823693710 |
| Directory | /workspace/35.rom_ctrl_alert_test/latest |
| Test location | /workspace/coverage/default/35.rom_ctrl_corrupt_sig_fatal_chk.1566087834 |
| Short name | T25 |
| Test name | |
| Test status | |
| Simulation time | 13388953388 ps |
| CPU time | 118.03 seconds |
| Started | Mar 05 01:51:47 PM PST 24 |
| Finished | Mar 05 01:53:46 PM PST 24 |
| Peak memory | 239560 kb |
| Host | smart-bcd8db6c-51fd-4c82-a361-ecbe1ee13362 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1566087834 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_ corrupt_sig_fatal_chk.1566087834 |
| Directory | /workspace/35.rom_ctrl_corrupt_sig_fatal_chk/latest |
| Test location | /workspace/coverage/default/35.rom_ctrl_kmac_err_chk.1075087120 |
| Short name | T149 |
| Test name | |
| Test status | |
| Simulation time | 1830454722 ps |
| CPU time | 20.12 seconds |
| Started | Mar 05 01:51:36 PM PST 24 |
| Finished | Mar 05 01:51:56 PM PST 24 |
| Peak memory | 213508 kb |
| Host | smart-fb52edbc-ec90-4bc5-8b8b-400954cf14c7 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1075087120 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_kmac_err_chk.1075087120 |
| Directory | /workspace/35.rom_ctrl_kmac_err_chk/latest |
| Test location | /workspace/coverage/default/35.rom_ctrl_max_throughput_chk.21962946 |
| Short name | T264 |
| Test name | |
| Test status | |
| Simulation time | 4130485319 ps |
| CPU time | 9.51 seconds |
| Started | Mar 05 01:51:35 PM PST 24 |
| Finished | Mar 05 01:51:45 PM PST 24 |
| Peak memory | 210836 kb |
| Host | smart-755d6b26-7a5c-4d40-a496-6b292ff9180c |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=21962946 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_max_throughput_chk.21962946 |
| Directory | /workspace/35.rom_ctrl_max_throughput_chk/latest |
| Test location | /workspace/coverage/default/35.rom_ctrl_smoke.4261261197 |
| Short name | T227 |
| Test name | |
| Test status | |
| Simulation time | 1347414192 ps |
| CPU time | 21.18 seconds |
| Started | Mar 05 01:51:41 PM PST 24 |
| Finished | Mar 05 01:52:03 PM PST 24 |
| Peak memory | 212700 kb |
| Host | smart-1492d90b-e1af-4ff5-972b-c51b631cf4be |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4261261197 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_smoke.4261261197 |
| Directory | /workspace/35.rom_ctrl_smoke/latest |
| Test location | /workspace/coverage/default/35.rom_ctrl_stress_all.3196517099 |
| Short name | T171 |
| Test name | |
| Test status | |
| Simulation time | 15214955399 ps |
| CPU time | 93.82 seconds |
| Started | Mar 05 01:51:34 PM PST 24 |
| Finished | Mar 05 01:53:08 PM PST 24 |
| Peak memory | 219096 kb |
| Host | smart-d42e1881-0bf5-4759-9749-41344942aad7 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3196517099 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm _name 35.rom_ctrl_stress_all.3196517099 |
| Directory | /workspace/35.rom_ctrl_stress_all/latest |
| Test location | /workspace/coverage/default/35.rom_ctrl_stress_all_with_rand_reset.2250906252 |
| Short name | T326 |
| Test name | |
| Test status | |
| Simulation time | 671864256028 ps |
| CPU time | 1892.63 seconds |
| Started | Mar 05 01:51:48 PM PST 24 |
| Finished | Mar 05 02:23:21 PM PST 24 |
| Peak memory | 237216 kb |
| Host | smart-b3034a91-4aee-413b-abb5-622b89fa04d7 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2250906252 -assert nop ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_stress_all_with_rand_reset.2250906252 |
| Directory | /workspace/35.rom_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/36.rom_ctrl_alert_test.3268360233 |
| Short name | T170 |
| Test name | |
| Test status | |
| Simulation time | 2981581657 ps |
| CPU time | 9.01 seconds |
| Started | Mar 05 01:51:51 PM PST 24 |
| Finished | Mar 05 01:52:00 PM PST 24 |
| Peak memory | 210996 kb |
| Host | smart-efce5c15-d20f-4823-b550-972320ed410f |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3268360233 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_alert_test.3268360233 |
| Directory | /workspace/36.rom_ctrl_alert_test/latest |
| Test location | /workspace/coverage/default/36.rom_ctrl_corrupt_sig_fatal_chk.1616835615 |
| Short name | T281 |
| Test name | |
| Test status | |
| Simulation time | 27917947014 ps |
| CPU time | 321.94 seconds |
| Started | Mar 05 01:51:51 PM PST 24 |
| Finished | Mar 05 01:57:13 PM PST 24 |
| Peak memory | 229332 kb |
| Host | smart-9516cd1e-7b21-4760-8688-0dc2e044054d |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1616835615 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_ corrupt_sig_fatal_chk.1616835615 |
| Directory | /workspace/36.rom_ctrl_corrupt_sig_fatal_chk/latest |
| Test location | /workspace/coverage/default/36.rom_ctrl_kmac_err_chk.2380438864 |
| Short name | T17 |
| Test name | |
| Test status | |
| Simulation time | 173809762 ps |
| CPU time | 9.72 seconds |
| Started | Mar 05 01:51:36 PM PST 24 |
| Finished | Mar 05 01:51:46 PM PST 24 |
| Peak memory | 211324 kb |
| Host | smart-60e35c43-e5c8-4922-8453-0e5c1061d57e |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2380438864 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_kmac_err_chk.2380438864 |
| Directory | /workspace/36.rom_ctrl_kmac_err_chk/latest |
| Test location | /workspace/coverage/default/36.rom_ctrl_max_throughput_chk.491855528 |
| Short name | T335 |
| Test name | |
| Test status | |
| Simulation time | 271224463 ps |
| CPU time | 6.13 seconds |
| Started | Mar 05 01:51:36 PM PST 24 |
| Finished | Mar 05 01:51:43 PM PST 24 |
| Peak memory | 210776 kb |
| Host | smart-07cdbd96-cc21-45b0-aa65-8acf015b3362 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=491855528 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_max_throughput_chk.491855528 |
| Directory | /workspace/36.rom_ctrl_max_throughput_chk/latest |
| Test location | /workspace/coverage/default/36.rom_ctrl_smoke.1940912703 |
| Short name | T272 |
| Test name | |
| Test status | |
| Simulation time | 745945344 ps |
| CPU time | 10.06 seconds |
| Started | Mar 05 01:51:42 PM PST 24 |
| Finished | Mar 05 01:51:52 PM PST 24 |
| Peak memory | 212896 kb |
| Host | smart-be148531-da4a-4130-8ec3-6e74d22d1913 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1940912703 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_smoke.1940912703 |
| Directory | /workspace/36.rom_ctrl_smoke/latest |
| Test location | /workspace/coverage/default/36.rom_ctrl_stress_all.2436121547 |
| Short name | T109 |
| Test name | |
| Test status | |
| Simulation time | 308556358 ps |
| CPU time | 7.76 seconds |
| Started | Mar 05 01:51:56 PM PST 24 |
| Finished | Mar 05 01:52:05 PM PST 24 |
| Peak memory | 210876 kb |
| Host | smart-f65334f9-3d61-4a38-8895-9d35e6613f94 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2436121547 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm _name 36.rom_ctrl_stress_all.2436121547 |
| Directory | /workspace/36.rom_ctrl_stress_all/latest |
| Test location | /workspace/coverage/default/37.rom_ctrl_alert_test.3643637464 |
| Short name | T161 |
| Test name | |
| Test status | |
| Simulation time | 171380400 ps |
| CPU time | 4.23 seconds |
| Started | Mar 05 01:51:34 PM PST 24 |
| Finished | Mar 05 01:51:38 PM PST 24 |
| Peak memory | 210964 kb |
| Host | smart-2aaa3098-ce14-47d1-a9b9-23138c1ab275 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3643637464 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_alert_test.3643637464 |
| Directory | /workspace/37.rom_ctrl_alert_test/latest |
| Test location | /workspace/coverage/default/37.rom_ctrl_corrupt_sig_fatal_chk.1816323230 |
| Short name | T317 |
| Test name | |
| Test status | |
| Simulation time | 142439972507 ps |
| CPU time | 183.69 seconds |
| Started | Mar 05 01:51:56 PM PST 24 |
| Finished | Mar 05 01:55:00 PM PST 24 |
| Peak memory | 233372 kb |
| Host | smart-2b59a3f2-c67c-46e6-b9de-f674ddbb95a4 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1816323230 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_ corrupt_sig_fatal_chk.1816323230 |
| Directory | /workspace/37.rom_ctrl_corrupt_sig_fatal_chk/latest |
| Test location | /workspace/coverage/default/37.rom_ctrl_kmac_err_chk.4277874875 |
| Short name | T177 |
| Test name | |
| Test status | |
| Simulation time | 12330618040 ps |
| CPU time | 26.69 seconds |
| Started | Mar 05 01:51:36 PM PST 24 |
| Finished | Mar 05 01:52:03 PM PST 24 |
| Peak memory | 211820 kb |
| Host | smart-18bc4547-6d79-40b8-811a-23927d028ffa |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4277874875 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_kmac_err_chk.4277874875 |
| Directory | /workspace/37.rom_ctrl_kmac_err_chk/latest |
| Test location | /workspace/coverage/default/37.rom_ctrl_max_throughput_chk.1815369063 |
| Short name | T135 |
| Test name | |
| Test status | |
| Simulation time | 1713915007 ps |
| CPU time | 15.56 seconds |
| Started | Mar 05 01:51:37 PM PST 24 |
| Finished | Mar 05 01:51:53 PM PST 24 |
| Peak memory | 210856 kb |
| Host | smart-a663c76e-626d-4963-8188-9f38b073e4d8 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1815369063 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_max_throughput_chk.1815369063 |
| Directory | /workspace/37.rom_ctrl_max_throughput_chk/latest |
| Test location | /workspace/coverage/default/37.rom_ctrl_smoke.2616779270 |
| Short name | T111 |
| Test name | |
| Test status | |
| Simulation time | 370109891 ps |
| CPU time | 9.65 seconds |
| Started | Mar 05 01:51:27 PM PST 24 |
| Finished | Mar 05 01:51:36 PM PST 24 |
| Peak memory | 212908 kb |
| Host | smart-20645eec-0473-4551-9f90-b7d2bc481293 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2616779270 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_smoke.2616779270 |
| Directory | /workspace/37.rom_ctrl_smoke/latest |
| Test location | /workspace/coverage/default/37.rom_ctrl_stress_all.3671625978 |
| Short name | T172 |
| Test name | |
| Test status | |
| Simulation time | 11896913148 ps |
| CPU time | 70.48 seconds |
| Started | Mar 05 01:51:46 PM PST 24 |
| Finished | Mar 05 01:52:56 PM PST 24 |
| Peak memory | 219128 kb |
| Host | smart-10cd9ce7-1004-4f78-915c-7f86db58b949 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3671625978 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm _name 37.rom_ctrl_stress_all.3671625978 |
| Directory | /workspace/37.rom_ctrl_stress_all/latest |
| Test location | /workspace/coverage/default/38.rom_ctrl_alert_test.3956019174 |
| Short name | T265 |
| Test name | |
| Test status | |
| Simulation time | 984697135 ps |
| CPU time | 10.28 seconds |
| Started | Mar 05 01:51:36 PM PST 24 |
| Finished | Mar 05 01:51:47 PM PST 24 |
| Peak memory | 210956 kb |
| Host | smart-9a8d2e1e-d621-4f0a-962c-193d7f955727 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3956019174 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_alert_test.3956019174 |
| Directory | /workspace/38.rom_ctrl_alert_test/latest |
| Test location | /workspace/coverage/default/38.rom_ctrl_corrupt_sig_fatal_chk.3136340481 |
| Short name | T237 |
| Test name | |
| Test status | |
| Simulation time | 41071064359 ps |
| CPU time | 227.8 seconds |
| Started | Mar 05 01:51:52 PM PST 24 |
| Finished | Mar 05 01:55:40 PM PST 24 |
| Peak memory | 236516 kb |
| Host | smart-0b1c8ae0-4d1a-4544-a950-028db4d7a4e4 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3136340481 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_ corrupt_sig_fatal_chk.3136340481 |
| Directory | /workspace/38.rom_ctrl_corrupt_sig_fatal_chk/latest |
| Test location | /workspace/coverage/default/38.rom_ctrl_kmac_err_chk.2610683277 |
| Short name | T121 |
| Test name | |
| Test status | |
| Simulation time | 19117991879 ps |
| CPU time | 34.67 seconds |
| Started | Mar 05 01:51:39 PM PST 24 |
| Finished | Mar 05 01:52:14 PM PST 24 |
| Peak memory | 211680 kb |
| Host | smart-d1a0b184-1b2f-4ab2-996a-7f20cd0aa8bd |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2610683277 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_kmac_err_chk.2610683277 |
| Directory | /workspace/38.rom_ctrl_kmac_err_chk/latest |
| Test location | /workspace/coverage/default/38.rom_ctrl_max_throughput_chk.1846083770 |
| Short name | T278 |
| Test name | |
| Test status | |
| Simulation time | 815382023 ps |
| CPU time | 5.49 seconds |
| Started | Mar 05 01:51:57 PM PST 24 |
| Finished | Mar 05 01:52:03 PM PST 24 |
| Peak memory | 210856 kb |
| Host | smart-6d51a8dc-c5f7-4aef-bc63-f475c84d499e |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1846083770 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_max_throughput_chk.1846083770 |
| Directory | /workspace/38.rom_ctrl_max_throughput_chk/latest |
| Test location | /workspace/coverage/default/38.rom_ctrl_smoke.1812180046 |
| Short name | T76 |
| Test name | |
| Test status | |
| Simulation time | 1239069430 ps |
| CPU time | 12.18 seconds |
| Started | Mar 05 01:51:45 PM PST 24 |
| Finished | Mar 05 01:51:58 PM PST 24 |
| Peak memory | 212184 kb |
| Host | smart-1e518f47-8748-4cb5-9c2a-84ed6fb0912d |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1812180046 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_smoke.1812180046 |
| Directory | /workspace/38.rom_ctrl_smoke/latest |
| Test location | /workspace/coverage/default/38.rom_ctrl_stress_all.330996601 |
| Short name | T158 |
| Test name | |
| Test status | |
| Simulation time | 10734765221 ps |
| CPU time | 18.71 seconds |
| Started | Mar 05 01:51:40 PM PST 24 |
| Finished | Mar 05 01:51:59 PM PST 24 |
| Peak memory | 211100 kb |
| Host | smart-58eae804-771b-4019-b5d5-11f489286ea6 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=330996601 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test + UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 38.rom_ctrl_stress_all.330996601 |
| Directory | /workspace/38.rom_ctrl_stress_all/latest |
| Test location | /workspace/coverage/default/38.rom_ctrl_stress_all_with_rand_reset.263334347 |
| Short name | T48 |
| Test name | |
| Test status | |
| Simulation time | 45262521580 ps |
| CPU time | 475.96 seconds |
| Started | Mar 05 01:51:36 PM PST 24 |
| Finished | Mar 05 01:59:32 PM PST 24 |
| Peak memory | 235552 kb |
| Host | smart-1139e30f-388d-41b6-9b7b-9cf832f723d7 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=263334347 -assert nopo stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera ge/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_stress_all_with_rand_reset.263334347 |
| Directory | /workspace/38.rom_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/39.rom_ctrl_alert_test.3631428052 |
| Short name | T117 |
| Test name | |
| Test status | |
| Simulation time | 334260797 ps |
| CPU time | 4.44 seconds |
| Started | Mar 05 01:51:36 PM PST 24 |
| Finished | Mar 05 01:51:41 PM PST 24 |
| Peak memory | 210932 kb |
| Host | smart-02faed06-e305-43a5-983a-e11bfa5bb142 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3631428052 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_alert_test.3631428052 |
| Directory | /workspace/39.rom_ctrl_alert_test/latest |
| Test location | /workspace/coverage/default/39.rom_ctrl_corrupt_sig_fatal_chk.3859220533 |
| Short name | T279 |
| Test name | |
| Test status | |
| Simulation time | 41605443322 ps |
| CPU time | 246.17 seconds |
| Started | Mar 05 01:51:41 PM PST 24 |
| Finished | Mar 05 01:55:48 PM PST 24 |
| Peak memory | 239940 kb |
| Host | smart-ca832d4d-a738-42c0-808c-ff30014148ce |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3859220533 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_ corrupt_sig_fatal_chk.3859220533 |
| Directory | /workspace/39.rom_ctrl_corrupt_sig_fatal_chk/latest |
| Test location | /workspace/coverage/default/39.rom_ctrl_kmac_err_chk.2410183402 |
| Short name | T222 |
| Test name | |
| Test status | |
| Simulation time | 8779548417 ps |
| CPU time | 24.06 seconds |
| Started | Mar 05 01:51:33 PM PST 24 |
| Finished | Mar 05 01:51:57 PM PST 24 |
| Peak memory | 211696 kb |
| Host | smart-8129acba-10f7-4b9a-8520-b74472527672 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2410183402 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_kmac_err_chk.2410183402 |
| Directory | /workspace/39.rom_ctrl_kmac_err_chk/latest |
| Test location | /workspace/coverage/default/39.rom_ctrl_max_throughput_chk.4133740061 |
| Short name | T236 |
| Test name | |
| Test status | |
| Simulation time | 557378399 ps |
| CPU time | 9.3 seconds |
| Started | Mar 05 01:51:49 PM PST 24 |
| Finished | Mar 05 01:51:59 PM PST 24 |
| Peak memory | 210832 kb |
| Host | smart-d5a0f171-95ae-4c4b-8277-022c5fdcfa18 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=4133740061 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_max_throughput_chk.4133740061 |
| Directory | /workspace/39.rom_ctrl_max_throughput_chk/latest |
| Test location | /workspace/coverage/default/39.rom_ctrl_smoke.2989806082 |
| Short name | T297 |
| Test name | |
| Test status | |
| Simulation time | 516460991 ps |
| CPU time | 14.52 seconds |
| Started | Mar 05 01:51:37 PM PST 24 |
| Finished | Mar 05 01:51:52 PM PST 24 |
| Peak memory | 212000 kb |
| Host | smart-3f19dcf8-bc55-4384-b326-517bb79f5de5 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2989806082 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_smoke.2989806082 |
| Directory | /workspace/39.rom_ctrl_smoke/latest |
| Test location | /workspace/coverage/default/39.rom_ctrl_stress_all.1091466417 |
| Short name | T110 |
| Test name | |
| Test status | |
| Simulation time | 14718547921 ps |
| CPU time | 46.3 seconds |
| Started | Mar 05 01:51:37 PM PST 24 |
| Finished | Mar 05 01:52:24 PM PST 24 |
| Peak memory | 219116 kb |
| Host | smart-0fff8d2e-2119-424e-8eda-acd2db966867 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1091466417 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm _name 39.rom_ctrl_stress_all.1091466417 |
| Directory | /workspace/39.rom_ctrl_stress_all/latest |
| Test location | /workspace/coverage/default/39.rom_ctrl_stress_all_with_rand_reset.2836829927 |
| Short name | T52 |
| Test name | |
| Test status | |
| Simulation time | 87910260671 ps |
| CPU time | 841 seconds |
| Started | Mar 05 01:51:46 PM PST 24 |
| Finished | Mar 05 02:05:47 PM PST 24 |
| Peak memory | 235580 kb |
| Host | smart-5693f607-e613-40a0-8e34-ecc209b1758b |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2836829927 -assert nop ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_stress_all_with_rand_reset.2836829927 |
| Directory | /workspace/39.rom_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/4.rom_ctrl_alert_test.2922486577 |
| Short name | T296 |
| Test name | |
| Test status | |
| Simulation time | 2669120566 ps |
| CPU time | 8.72 seconds |
| Started | Mar 05 01:51:03 PM PST 24 |
| Finished | Mar 05 01:51:12 PM PST 24 |
| Peak memory | 211020 kb |
| Host | smart-5a04d075-4640-44bc-9abb-b2b82c6a270a |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2922486577 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_alert_test.2922486577 |
| Directory | /workspace/4.rom_ctrl_alert_test/latest |
| Test location | /workspace/coverage/default/4.rom_ctrl_corrupt_sig_fatal_chk.217059486 |
| Short name | T27 |
| Test name | |
| Test status | |
| Simulation time | 9897620196 ps |
| CPU time | 139.65 seconds |
| Started | Mar 05 01:51:01 PM PST 24 |
| Finished | Mar 05 01:53:21 PM PST 24 |
| Peak memory | 219368 kb |
| Host | smart-799a2347-2c7c-4787-bcdc-a94e23dd647c |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=217059486 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt _sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_co rrupt_sig_fatal_chk.217059486 |
| Directory | /workspace/4.rom_ctrl_corrupt_sig_fatal_chk/latest |
| Test location | /workspace/coverage/default/4.rom_ctrl_kmac_err_chk.2734456706 |
| Short name | T216 |
| Test name | |
| Test status | |
| Simulation time | 5776127876 ps |
| CPU time | 26.54 seconds |
| Started | Mar 05 01:51:05 PM PST 24 |
| Finished | Mar 05 01:51:32 PM PST 24 |
| Peak memory | 211136 kb |
| Host | smart-69d06eb8-1885-41ea-a778-bea08d51b0b8 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2734456706 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_kmac_err_chk.2734456706 |
| Directory | /workspace/4.rom_ctrl_kmac_err_chk/latest |
| Test location | /workspace/coverage/default/4.rom_ctrl_max_throughput_chk.513665 |
| Short name | T143 |
| Test name | |
| Test status | |
| Simulation time | 99208132 ps |
| CPU time | 5.77 seconds |
| Started | Mar 05 01:51:29 PM PST 24 |
| Finished | Mar 05 01:51:35 PM PST 24 |
| Peak memory | 210696 kb |
| Host | smart-4937597c-f59b-40db-ad0c-d5520afef41f |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=513665 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_max_throughput_chk.513665 |
| Directory | /workspace/4.rom_ctrl_max_throughput_chk/latest |
| Test location | /workspace/coverage/default/4.rom_ctrl_sec_cm.3795954008 |
| Short name | T36 |
| Test name | |
| Test status | |
| Simulation time | 1105659601 ps |
| CPU time | 105.15 seconds |
| Started | Mar 05 01:51:14 PM PST 24 |
| Finished | Mar 05 01:53:00 PM PST 24 |
| Peak memory | 237464 kb |
| Host | smart-cd1c3c0c-e6be-4737-8244-73c618622d0b |
| User | root |
| Command | /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3795954008 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_sec_cm.3795954008 |
| Directory | /workspace/4.rom_ctrl_sec_cm/latest |
| Test location | /workspace/coverage/default/4.rom_ctrl_smoke.1816362125 |
| Short name | T77 |
| Test name | |
| Test status | |
| Simulation time | 886558201 ps |
| CPU time | 10.11 seconds |
| Started | Mar 05 01:51:17 PM PST 24 |
| Finished | Mar 05 01:51:27 PM PST 24 |
| Peak memory | 212852 kb |
| Host | smart-843a4b4a-8f2a-40e7-8bfd-38100bf7b9ea |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1816362125 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_smoke.1816362125 |
| Directory | /workspace/4.rom_ctrl_smoke/latest |
| Test location | /workspace/coverage/default/4.rom_ctrl_stress_all.1067786791 |
| Short name | T248 |
| Test name | |
| Test status | |
| Simulation time | 3050011862 ps |
| CPU time | 16.48 seconds |
| Started | Mar 05 01:51:19 PM PST 24 |
| Finished | Mar 05 01:51:36 PM PST 24 |
| Peak memory | 211576 kb |
| Host | smart-561c0d4a-afd8-4080-ab57-82840c513a9c |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1067786791 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm _name 4.rom_ctrl_stress_all.1067786791 |
| Directory | /workspace/4.rom_ctrl_stress_all/latest |
| Test location | /workspace/coverage/default/40.rom_ctrl_alert_test.864033151 |
| Short name | T343 |
| Test name | |
| Test status | |
| Simulation time | 4401044823 ps |
| CPU time | 11.03 seconds |
| Started | Mar 05 01:51:38 PM PST 24 |
| Finished | Mar 05 01:51:49 PM PST 24 |
| Peak memory | 210988 kb |
| Host | smart-50c7e1bc-f134-41e9-95e8-c431db947302 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=864033151 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_alert_test.864033151 |
| Directory | /workspace/40.rom_ctrl_alert_test/latest |
| Test location | /workspace/coverage/default/40.rom_ctrl_corrupt_sig_fatal_chk.2906198940 |
| Short name | T46 |
| Test name | |
| Test status | |
| Simulation time | 19931845140 ps |
| CPU time | 202.98 seconds |
| Started | Mar 05 01:51:55 PM PST 24 |
| Finished | Mar 05 01:55:19 PM PST 24 |
| Peak memory | 228744 kb |
| Host | smart-150cbf2b-d715-4ce1-b328-6d5b92a4c406 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2906198940 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_ corrupt_sig_fatal_chk.2906198940 |
| Directory | /workspace/40.rom_ctrl_corrupt_sig_fatal_chk/latest |
| Test location | /workspace/coverage/default/40.rom_ctrl_kmac_err_chk.4032439276 |
| Short name | T144 |
| Test name | |
| Test status | |
| Simulation time | 17953982623 ps |
| CPU time | 32.78 seconds |
| Started | Mar 05 01:51:37 PM PST 24 |
| Finished | Mar 05 01:52:10 PM PST 24 |
| Peak memory | 211808 kb |
| Host | smart-3a4779cf-2387-46aa-954a-e6436345edec |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4032439276 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_kmac_err_chk.4032439276 |
| Directory | /workspace/40.rom_ctrl_kmac_err_chk/latest |
| Test location | /workspace/coverage/default/40.rom_ctrl_max_throughput_chk.4264881062 |
| Short name | T322 |
| Test name | |
| Test status | |
| Simulation time | 185025485 ps |
| CPU time | 5.25 seconds |
| Started | Mar 05 01:51:46 PM PST 24 |
| Finished | Mar 05 01:51:52 PM PST 24 |
| Peak memory | 210788 kb |
| Host | smart-da56dd9e-9869-40e9-9bb6-038d9bd5db85 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=4264881062 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_max_throughput_chk.4264881062 |
| Directory | /workspace/40.rom_ctrl_max_throughput_chk/latest |
| Test location | /workspace/coverage/default/40.rom_ctrl_smoke.2343789721 |
| Short name | T190 |
| Test name | |
| Test status | |
| Simulation time | 754031868 ps |
| CPU time | 10.31 seconds |
| Started | Mar 05 01:51:56 PM PST 24 |
| Finished | Mar 05 01:52:07 PM PST 24 |
| Peak memory | 213480 kb |
| Host | smart-64379198-c613-45b2-a48f-516d0efc1bd8 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2343789721 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_smoke.2343789721 |
| Directory | /workspace/40.rom_ctrl_smoke/latest |
| Test location | /workspace/coverage/default/40.rom_ctrl_stress_all.847333276 |
| Short name | T116 |
| Test name | |
| Test status | |
| Simulation time | 7446437023 ps |
| CPU time | 18.18 seconds |
| Started | Mar 05 01:51:47 PM PST 24 |
| Finished | Mar 05 01:52:05 PM PST 24 |
| Peak memory | 210824 kb |
| Host | smart-6f233233-c074-4016-9e36-d40822ef8753 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=847333276 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test + UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 40.rom_ctrl_stress_all.847333276 |
| Directory | /workspace/40.rom_ctrl_stress_all/latest |
| Test location | /workspace/coverage/default/41.rom_ctrl_alert_test.3974652864 |
| Short name | T353 |
| Test name | |
| Test status | |
| Simulation time | 334067228 ps |
| CPU time | 4.35 seconds |
| Started | Mar 05 01:51:45 PM PST 24 |
| Finished | Mar 05 01:51:49 PM PST 24 |
| Peak memory | 210760 kb |
| Host | smart-719be116-9e70-4e6b-a5c0-0474c27bc248 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3974652864 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_alert_test.3974652864 |
| Directory | /workspace/41.rom_ctrl_alert_test/latest |
| Test location | /workspace/coverage/default/41.rom_ctrl_corrupt_sig_fatal_chk.1760366891 |
| Short name | T256 |
| Test name | |
| Test status | |
| Simulation time | 65445661358 ps |
| CPU time | 201.76 seconds |
| Started | Mar 05 01:51:52 PM PST 24 |
| Finished | Mar 05 01:55:14 PM PST 24 |
| Peak memory | 236532 kb |
| Host | smart-5f8267b1-f029-4e12-9b77-617d7c53a74a |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1760366891 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_ corrupt_sig_fatal_chk.1760366891 |
| Directory | /workspace/41.rom_ctrl_corrupt_sig_fatal_chk/latest |
| Test location | /workspace/coverage/default/41.rom_ctrl_kmac_err_chk.466729569 |
| Short name | T341 |
| Test name | |
| Test status | |
| Simulation time | 594379720 ps |
| CPU time | 9.57 seconds |
| Started | Mar 05 01:51:35 PM PST 24 |
| Finished | Mar 05 01:51:45 PM PST 24 |
| Peak memory | 210940 kb |
| Host | smart-7b50f7e9-65ed-497b-90ba-52d68c85dfc7 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=466729569 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_kmac_err_chk.466729569 |
| Directory | /workspace/41.rom_ctrl_kmac_err_chk/latest |
| Test location | /workspace/coverage/default/41.rom_ctrl_max_throughput_chk.47687011 |
| Short name | T348 |
| Test name | |
| Test status | |
| Simulation time | 1161442218 ps |
| CPU time | 11.94 seconds |
| Started | Mar 05 01:51:43 PM PST 24 |
| Finished | Mar 05 01:51:55 PM PST 24 |
| Peak memory | 210812 kb |
| Host | smart-0a821df0-dc40-41cd-99e9-aabc4941466a |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=47687011 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_max_throughput_chk.47687011 |
| Directory | /workspace/41.rom_ctrl_max_throughput_chk/latest |
| Test location | /workspace/coverage/default/41.rom_ctrl_smoke.3368434878 |
| Short name | T122 |
| Test name | |
| Test status | |
| Simulation time | 290567207 ps |
| CPU time | 11.49 seconds |
| Started | Mar 05 01:51:49 PM PST 24 |
| Finished | Mar 05 01:52:01 PM PST 24 |
| Peak memory | 212784 kb |
| Host | smart-fb744e28-9d4d-4c9b-a618-d80feefc3930 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3368434878 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_smoke.3368434878 |
| Directory | /workspace/41.rom_ctrl_smoke/latest |
| Test location | /workspace/coverage/default/41.rom_ctrl_stress_all.1938325282 |
| Short name | T345 |
| Test name | |
| Test status | |
| Simulation time | 2866970810 ps |
| CPU time | 30.23 seconds |
| Started | Mar 05 01:51:48 PM PST 24 |
| Finished | Mar 05 01:52:19 PM PST 24 |
| Peak memory | 214256 kb |
| Host | smart-8ae360e8-a286-49f4-8af3-407bdb1d6aa0 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1938325282 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm _name 41.rom_ctrl_stress_all.1938325282 |
| Directory | /workspace/41.rom_ctrl_stress_all/latest |
| Test location | /workspace/coverage/default/41.rom_ctrl_stress_all_with_rand_reset.3065283327 |
| Short name | T13 |
| Test name | |
| Test status | |
| Simulation time | 58710945645 ps |
| CPU time | 1080.74 seconds |
| Started | Mar 05 01:51:45 PM PST 24 |
| Finished | Mar 05 02:09:46 PM PST 24 |
| Peak memory | 231140 kb |
| Host | smart-318ca0a7-761e-4de3-af6b-1aed038ba8df |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3065283327 -assert nop ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_stress_all_with_rand_reset.3065283327 |
| Directory | /workspace/41.rom_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/42.rom_ctrl_alert_test.587546566 |
| Short name | T238 |
| Test name | |
| Test status | |
| Simulation time | 8533066449 ps |
| CPU time | 16.87 seconds |
| Started | Mar 05 01:51:47 PM PST 24 |
| Finished | Mar 05 01:52:04 PM PST 24 |
| Peak memory | 210964 kb |
| Host | smart-015ed596-dac2-4129-bd85-fc8f4ebd76a3 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=587546566 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_alert_test.587546566 |
| Directory | /workspace/42.rom_ctrl_alert_test/latest |
| Test location | /workspace/coverage/default/42.rom_ctrl_corrupt_sig_fatal_chk.2918043733 |
| Short name | T178 |
| Test name | |
| Test status | |
| Simulation time | 93092889814 ps |
| CPU time | 359.58 seconds |
| Started | Mar 05 01:51:59 PM PST 24 |
| Finished | Mar 05 01:57:58 PM PST 24 |
| Peak memory | 227856 kb |
| Host | smart-d1ed6cb8-2e77-46b9-b6a0-22a38b463a35 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2918043733 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_ corrupt_sig_fatal_chk.2918043733 |
| Directory | /workspace/42.rom_ctrl_corrupt_sig_fatal_chk/latest |
| Test location | /workspace/coverage/default/42.rom_ctrl_kmac_err_chk.1543603405 |
| Short name | T119 |
| Test name | |
| Test status | |
| Simulation time | 5939361134 ps |
| CPU time | 18.83 seconds |
| Started | Mar 05 01:51:37 PM PST 24 |
| Finished | Mar 05 01:51:56 PM PST 24 |
| Peak memory | 211900 kb |
| Host | smart-fd5bcae9-d697-4943-9d6e-10ed1f28125e |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1543603405 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_kmac_err_chk.1543603405 |
| Directory | /workspace/42.rom_ctrl_kmac_err_chk/latest |
| Test location | /workspace/coverage/default/42.rom_ctrl_max_throughput_chk.4109224418 |
| Short name | T127 |
| Test name | |
| Test status | |
| Simulation time | 189788003 ps |
| CPU time | 5.59 seconds |
| Started | Mar 05 01:51:45 PM PST 24 |
| Finished | Mar 05 01:51:51 PM PST 24 |
| Peak memory | 210828 kb |
| Host | smart-a0e9edf2-68ff-4f96-8d96-e2f4a1c20edb |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=4109224418 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_max_throughput_chk.4109224418 |
| Directory | /workspace/42.rom_ctrl_max_throughput_chk/latest |
| Test location | /workspace/coverage/default/42.rom_ctrl_smoke.1245359842 |
| Short name | T10 |
| Test name | |
| Test status | |
| Simulation time | 66984569623 ps |
| CPU time | 29.6 seconds |
| Started | Mar 05 01:51:50 PM PST 24 |
| Finished | Mar 05 01:52:20 PM PST 24 |
| Peak memory | 213528 kb |
| Host | smart-4244c9c4-cd56-42ae-92ee-165175059327 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1245359842 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_smoke.1245359842 |
| Directory | /workspace/42.rom_ctrl_smoke/latest |
| Test location | /workspace/coverage/default/42.rom_ctrl_stress_all.3629777643 |
| Short name | T239 |
| Test name | |
| Test status | |
| Simulation time | 396344223 ps |
| CPU time | 22.25 seconds |
| Started | Mar 05 01:51:34 PM PST 24 |
| Finished | Mar 05 01:51:57 PM PST 24 |
| Peak memory | 214884 kb |
| Host | smart-7b992be8-afee-49b5-9f1c-9628da0fb97a |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3629777643 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm _name 42.rom_ctrl_stress_all.3629777643 |
| Directory | /workspace/42.rom_ctrl_stress_all/latest |
| Test location | /workspace/coverage/default/42.rom_ctrl_stress_all_with_rand_reset.2134591778 |
| Short name | T253 |
| Test name | |
| Test status | |
| Simulation time | 343228279348 ps |
| CPU time | 3605.41 seconds |
| Started | Mar 05 01:51:36 PM PST 24 |
| Finished | Mar 05 02:51:43 PM PST 24 |
| Peak memory | 247484 kb |
| Host | smart-865f7155-1b07-4daf-835c-2dc0da7f3751 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2134591778 -assert nop ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_stress_all_with_rand_reset.2134591778 |
| Directory | /workspace/42.rom_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/43.rom_ctrl_alert_test.3177203146 |
| Short name | T214 |
| Test name | |
| Test status | |
| Simulation time | 2056143723 ps |
| CPU time | 16.19 seconds |
| Started | Mar 05 01:51:56 PM PST 24 |
| Finished | Mar 05 01:52:13 PM PST 24 |
| Peak memory | 210892 kb |
| Host | smart-85753fa7-0459-41f5-adda-be0a7f5aacf6 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3177203146 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_alert_test.3177203146 |
| Directory | /workspace/43.rom_ctrl_alert_test/latest |
| Test location | /workspace/coverage/default/43.rom_ctrl_corrupt_sig_fatal_chk.1732460591 |
| Short name | T263 |
| Test name | |
| Test status | |
| Simulation time | 82064867759 ps |
| CPU time | 237.03 seconds |
| Started | Mar 05 01:51:45 PM PST 24 |
| Finished | Mar 05 01:55:42 PM PST 24 |
| Peak memory | 228508 kb |
| Host | smart-4f981993-a914-4334-a84a-5e69501ee2a0 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1732460591 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_ corrupt_sig_fatal_chk.1732460591 |
| Directory | /workspace/43.rom_ctrl_corrupt_sig_fatal_chk/latest |
| Test location | /workspace/coverage/default/43.rom_ctrl_kmac_err_chk.3123281074 |
| Short name | T173 |
| Test name | |
| Test status | |
| Simulation time | 975750722 ps |
| CPU time | 9.46 seconds |
| Started | Mar 05 01:51:37 PM PST 24 |
| Finished | Mar 05 01:51:52 PM PST 24 |
| Peak memory | 210916 kb |
| Host | smart-d663d23f-315b-401d-b70c-08e957d0f49a |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3123281074 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_kmac_err_chk.3123281074 |
| Directory | /workspace/43.rom_ctrl_kmac_err_chk/latest |
| Test location | /workspace/coverage/default/43.rom_ctrl_max_throughput_chk.3750415005 |
| Short name | T1 |
| Test name | |
| Test status | |
| Simulation time | 444228455 ps |
| CPU time | 5.48 seconds |
| Started | Mar 05 01:51:46 PM PST 24 |
| Finished | Mar 05 01:51:52 PM PST 24 |
| Peak memory | 210836 kb |
| Host | smart-e1481ebd-0ade-4764-b112-666b2ad20914 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3750415005 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_max_throughput_chk.3750415005 |
| Directory | /workspace/43.rom_ctrl_max_throughput_chk/latest |
| Test location | /workspace/coverage/default/43.rom_ctrl_smoke.2074437234 |
| Short name | T202 |
| Test name | |
| Test status | |
| Simulation time | 35687854770 ps |
| CPU time | 26.4 seconds |
| Started | Mar 05 01:51:37 PM PST 24 |
| Finished | Mar 05 01:52:04 PM PST 24 |
| Peak memory | 219128 kb |
| Host | smart-9899f252-703d-46b0-8c6e-d380afd84310 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2074437234 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_smoke.2074437234 |
| Directory | /workspace/43.rom_ctrl_smoke/latest |
| Test location | /workspace/coverage/default/43.rom_ctrl_stress_all.1457795005 |
| Short name | T338 |
| Test name | |
| Test status | |
| Simulation time | 3996543649 ps |
| CPU time | 18.55 seconds |
| Started | Mar 05 01:51:58 PM PST 24 |
| Finished | Mar 05 01:52:17 PM PST 24 |
| Peak memory | 210824 kb |
| Host | smart-1a615325-da24-499a-8e3a-398b97401b83 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1457795005 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm _name 43.rom_ctrl_stress_all.1457795005 |
| Directory | /workspace/43.rom_ctrl_stress_all/latest |
| Test location | /workspace/coverage/default/43.rom_ctrl_stress_all_with_rand_reset.773467924 |
| Short name | T12 |
| Test name | |
| Test status | |
| Simulation time | 83024665439 ps |
| CPU time | 807.34 seconds |
| Started | Mar 05 01:51:44 PM PST 24 |
| Finished | Mar 05 02:05:12 PM PST 24 |
| Peak memory | 231508 kb |
| Host | smart-f4cf1794-f397-4ee0-b2c3-d84ade784c2a |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=773467924 -assert nopo stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera ge/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_stress_all_with_rand_reset.773467924 |
| Directory | /workspace/43.rom_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/44.rom_ctrl_alert_test.2427599043 |
| Short name | T262 |
| Test name | |
| Test status | |
| Simulation time | 1142545383 ps |
| CPU time | 10.35 seconds |
| Started | Mar 05 01:51:51 PM PST 24 |
| Finished | Mar 05 01:52:02 PM PST 24 |
| Peak memory | 210988 kb |
| Host | smart-7c7415fc-6b0e-493d-9f2e-c8de317b6177 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2427599043 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_alert_test.2427599043 |
| Directory | /workspace/44.rom_ctrl_alert_test/latest |
| Test location | /workspace/coverage/default/44.rom_ctrl_corrupt_sig_fatal_chk.2273896462 |
| Short name | T316 |
| Test name | |
| Test status | |
| Simulation time | 14073026034 ps |
| CPU time | 121.49 seconds |
| Started | Mar 05 01:51:54 PM PST 24 |
| Finished | Mar 05 01:53:56 PM PST 24 |
| Peak memory | 236636 kb |
| Host | smart-829e8b44-5b20-4bd0-a17b-286da2daeb8b |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2273896462 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_ corrupt_sig_fatal_chk.2273896462 |
| Directory | /workspace/44.rom_ctrl_corrupt_sig_fatal_chk/latest |
| Test location | /workspace/coverage/default/44.rom_ctrl_kmac_err_chk.2904187160 |
| Short name | T22 |
| Test name | |
| Test status | |
| Simulation time | 11047455959 ps |
| CPU time | 26.29 seconds |
| Started | Mar 05 01:51:47 PM PST 24 |
| Finished | Mar 05 01:52:14 PM PST 24 |
| Peak memory | 211696 kb |
| Host | smart-4d0baa5e-5300-48a3-b427-7c0d676a3e70 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2904187160 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_kmac_err_chk.2904187160 |
| Directory | /workspace/44.rom_ctrl_kmac_err_chk/latest |
| Test location | /workspace/coverage/default/44.rom_ctrl_max_throughput_chk.304553380 |
| Short name | T63 |
| Test name | |
| Test status | |
| Simulation time | 1508442738 ps |
| CPU time | 5.61 seconds |
| Started | Mar 05 01:52:00 PM PST 24 |
| Finished | Mar 05 01:52:06 PM PST 24 |
| Peak memory | 210832 kb |
| Host | smart-6ff74e8d-abfb-4b87-9f00-f190e921b4b9 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=304553380 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_max_throughput_chk.304553380 |
| Directory | /workspace/44.rom_ctrl_max_throughput_chk/latest |
| Test location | /workspace/coverage/default/44.rom_ctrl_smoke.927535032 |
| Short name | T114 |
| Test name | |
| Test status | |
| Simulation time | 8415465608 ps |
| CPU time | 34.64 seconds |
| Started | Mar 05 01:51:47 PM PST 24 |
| Finished | Mar 05 01:52:22 PM PST 24 |
| Peak memory | 213432 kb |
| Host | smart-6c965aee-22d1-42a2-ba4c-d6f60a2eebaf |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=927535032 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_smoke.927535032 |
| Directory | /workspace/44.rom_ctrl_smoke/latest |
| Test location | /workspace/coverage/default/44.rom_ctrl_stress_all.4192700256 |
| Short name | T167 |
| Test name | |
| Test status | |
| Simulation time | 3878940095 ps |
| CPU time | 24.05 seconds |
| Started | Mar 05 01:51:36 PM PST 24 |
| Finished | Mar 05 01:52:01 PM PST 24 |
| Peak memory | 213616 kb |
| Host | smart-64f8abc5-d03d-47c1-bcf8-31f50ca3f9ea |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4192700256 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm _name 44.rom_ctrl_stress_all.4192700256 |
| Directory | /workspace/44.rom_ctrl_stress_all/latest |
| Test location | /workspace/coverage/default/45.rom_ctrl_alert_test.2135420880 |
| Short name | T346 |
| Test name | |
| Test status | |
| Simulation time | 4034745360 ps |
| CPU time | 16.44 seconds |
| Started | Mar 05 01:51:47 PM PST 24 |
| Finished | Mar 05 01:52:04 PM PST 24 |
| Peak memory | 210976 kb |
| Host | smart-7d20149d-1c57-4efc-a0d1-6a1e5b51bd55 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2135420880 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_alert_test.2135420880 |
| Directory | /workspace/45.rom_ctrl_alert_test/latest |
| Test location | /workspace/coverage/default/45.rom_ctrl_corrupt_sig_fatal_chk.2807760130 |
| Short name | T153 |
| Test name | |
| Test status | |
| Simulation time | 22180964178 ps |
| CPU time | 215.1 seconds |
| Started | Mar 05 01:51:49 PM PST 24 |
| Finished | Mar 05 01:55:24 PM PST 24 |
| Peak memory | 224252 kb |
| Host | smart-8582463f-ae58-40e6-86b8-ff51862c21bf |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2807760130 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_ corrupt_sig_fatal_chk.2807760130 |
| Directory | /workspace/45.rom_ctrl_corrupt_sig_fatal_chk/latest |
| Test location | /workspace/coverage/default/45.rom_ctrl_kmac_err_chk.1611364986 |
| Short name | T213 |
| Test name | |
| Test status | |
| Simulation time | 15063197748 ps |
| CPU time | 31.23 seconds |
| Started | Mar 05 01:51:35 PM PST 24 |
| Finished | Mar 05 01:52:07 PM PST 24 |
| Peak memory | 211892 kb |
| Host | smart-e9b9fb4e-5f48-4c64-888b-6f919291c3a4 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1611364986 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_kmac_err_chk.1611364986 |
| Directory | /workspace/45.rom_ctrl_kmac_err_chk/latest |
| Test location | /workspace/coverage/default/45.rom_ctrl_max_throughput_chk.27544445 |
| Short name | T206 |
| Test name | |
| Test status | |
| Simulation time | 185731170 ps |
| CPU time | 5.49 seconds |
| Started | Mar 05 01:51:55 PM PST 24 |
| Finished | Mar 05 01:52:01 PM PST 24 |
| Peak memory | 210800 kb |
| Host | smart-0abb4cf7-b807-4864-8b69-482321a43c5f |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=27544445 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_max_throughput_chk.27544445 |
| Directory | /workspace/45.rom_ctrl_max_throughput_chk/latest |
| Test location | /workspace/coverage/default/45.rom_ctrl_smoke.4140441832 |
| Short name | T78 |
| Test name | |
| Test status | |
| Simulation time | 14278409071 ps |
| CPU time | 34.72 seconds |
| Started | Mar 05 01:51:56 PM PST 24 |
| Finished | Mar 05 01:52:31 PM PST 24 |
| Peak memory | 214112 kb |
| Host | smart-2db22c3d-290a-4aa5-ba01-aa4d050fc162 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4140441832 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_smoke.4140441832 |
| Directory | /workspace/45.rom_ctrl_smoke/latest |
| Test location | /workspace/coverage/default/45.rom_ctrl_stress_all.1684107309 |
| Short name | T221 |
| Test name | |
| Test status | |
| Simulation time | 6771168029 ps |
| CPU time | 64.95 seconds |
| Started | Mar 05 01:51:54 PM PST 24 |
| Finished | Mar 05 01:52:59 PM PST 24 |
| Peak memory | 215736 kb |
| Host | smart-9b2952dc-868f-4ff9-98bd-7a3226bfcb0b |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1684107309 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm _name 45.rom_ctrl_stress_all.1684107309 |
| Directory | /workspace/45.rom_ctrl_stress_all/latest |
| Test location | /workspace/coverage/default/46.rom_ctrl_alert_test.2667829751 |
| Short name | T163 |
| Test name | |
| Test status | |
| Simulation time | 4931477138 ps |
| CPU time | 11.58 seconds |
| Started | Mar 05 01:52:00 PM PST 24 |
| Finished | Mar 05 01:52:12 PM PST 24 |
| Peak memory | 211020 kb |
| Host | smart-078e498d-7a92-45df-a370-ec96a6de70cb |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2667829751 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_alert_test.2667829751 |
| Directory | /workspace/46.rom_ctrl_alert_test/latest |
| Test location | /workspace/coverage/default/46.rom_ctrl_corrupt_sig_fatal_chk.1594192083 |
| Short name | T198 |
| Test name | |
| Test status | |
| Simulation time | 59922545004 ps |
| CPU time | 255.16 seconds |
| Started | Mar 05 01:51:40 PM PST 24 |
| Finished | Mar 05 01:55:55 PM PST 24 |
| Peak memory | 236448 kb |
| Host | smart-ac376d3e-3eba-4fcb-87d4-cd54bb97919b |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1594192083 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_ corrupt_sig_fatal_chk.1594192083 |
| Directory | /workspace/46.rom_ctrl_corrupt_sig_fatal_chk/latest |
| Test location | /workspace/coverage/default/46.rom_ctrl_kmac_err_chk.2361161792 |
| Short name | T129 |
| Test name | |
| Test status | |
| Simulation time | 3004831678 ps |
| CPU time | 19.57 seconds |
| Started | Mar 05 01:51:55 PM PST 24 |
| Finished | Mar 05 01:52:15 PM PST 24 |
| Peak memory | 211356 kb |
| Host | smart-59d64d41-d9df-4027-99ee-d1cdb118d95b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2361161792 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_kmac_err_chk.2361161792 |
| Directory | /workspace/46.rom_ctrl_kmac_err_chk/latest |
| Test location | /workspace/coverage/default/46.rom_ctrl_max_throughput_chk.129634863 |
| Short name | T134 |
| Test name | |
| Test status | |
| Simulation time | 2050491260 ps |
| CPU time | 17.31 seconds |
| Started | Mar 05 01:51:47 PM PST 24 |
| Finished | Mar 05 01:52:05 PM PST 24 |
| Peak memory | 210780 kb |
| Host | smart-db2eae0d-b8ff-4d4a-8b1d-a19c4b850026 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=129634863 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_max_throughput_chk.129634863 |
| Directory | /workspace/46.rom_ctrl_max_throughput_chk/latest |
| Test location | /workspace/coverage/default/46.rom_ctrl_smoke.3940580093 |
| Short name | T324 |
| Test name | |
| Test status | |
| Simulation time | 1742690820 ps |
| CPU time | 18.77 seconds |
| Started | Mar 05 01:51:54 PM PST 24 |
| Finished | Mar 05 01:52:14 PM PST 24 |
| Peak memory | 213392 kb |
| Host | smart-c01f155a-6c5a-457f-8429-f25416deaff2 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3940580093 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_smoke.3940580093 |
| Directory | /workspace/46.rom_ctrl_smoke/latest |
| Test location | /workspace/coverage/default/46.rom_ctrl_stress_all.3220507343 |
| Short name | T242 |
| Test name | |
| Test status | |
| Simulation time | 231335143 ps |
| CPU time | 7.38 seconds |
| Started | Mar 05 01:51:41 PM PST 24 |
| Finished | Mar 05 01:51:49 PM PST 24 |
| Peak memory | 210840 kb |
| Host | smart-61652165-d651-4ff8-b59e-f5e440406eb4 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3220507343 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm _name 46.rom_ctrl_stress_all.3220507343 |
| Directory | /workspace/46.rom_ctrl_stress_all/latest |
| Test location | /workspace/coverage/default/46.rom_ctrl_stress_all_with_rand_reset.2712299606 |
| Short name | T49 |
| Test name | |
| Test status | |
| Simulation time | 14017977103 ps |
| CPU time | 587.14 seconds |
| Started | Mar 05 01:51:59 PM PST 24 |
| Finished | Mar 05 02:01:46 PM PST 24 |
| Peak memory | 221788 kb |
| Host | smart-262df067-f632-4c53-9b02-f4b528f75a9e |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2712299606 -assert nop ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_stress_all_with_rand_reset.2712299606 |
| Directory | /workspace/46.rom_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/47.rom_ctrl_alert_test.2639548492 |
| Short name | T126 |
| Test name | |
| Test status | |
| Simulation time | 3076809183 ps |
| CPU time | 9.39 seconds |
| Started | Mar 05 01:51:56 PM PST 24 |
| Finished | Mar 05 01:52:07 PM PST 24 |
| Peak memory | 210992 kb |
| Host | smart-3463be09-fa14-4bee-9adb-b80cb1c51df4 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2639548492 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_alert_test.2639548492 |
| Directory | /workspace/47.rom_ctrl_alert_test/latest |
| Test location | /workspace/coverage/default/47.rom_ctrl_corrupt_sig_fatal_chk.2302710367 |
| Short name | T26 |
| Test name | |
| Test status | |
| Simulation time | 3094959096 ps |
| CPU time | 78.77 seconds |
| Started | Mar 05 01:51:54 PM PST 24 |
| Finished | Mar 05 01:53:13 PM PST 24 |
| Peak memory | 219376 kb |
| Host | smart-968a342d-a749-4186-94f3-7ad8e008e05b |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2302710367 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_ corrupt_sig_fatal_chk.2302710367 |
| Directory | /workspace/47.rom_ctrl_corrupt_sig_fatal_chk/latest |
| Test location | /workspace/coverage/default/47.rom_ctrl_kmac_err_chk.3393904094 |
| Short name | T247 |
| Test name | |
| Test status | |
| Simulation time | 3675253259 ps |
| CPU time | 30.76 seconds |
| Started | Mar 05 01:52:00 PM PST 24 |
| Finished | Mar 05 01:52:31 PM PST 24 |
| Peak memory | 211900 kb |
| Host | smart-4f9e5414-6c88-42b5-bf77-68b95615b494 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3393904094 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_kmac_err_chk.3393904094 |
| Directory | /workspace/47.rom_ctrl_kmac_err_chk/latest |
| Test location | /workspace/coverage/default/47.rom_ctrl_max_throughput_chk.620528257 |
| Short name | T159 |
| Test name | |
| Test status | |
| Simulation time | 30955072593 ps |
| CPU time | 19.06 seconds |
| Started | Mar 05 01:51:53 PM PST 24 |
| Finished | Mar 05 01:52:13 PM PST 24 |
| Peak memory | 210892 kb |
| Host | smart-8a42958c-8186-4454-bace-550296be2c0c |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=620528257 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_max_throughput_chk.620528257 |
| Directory | /workspace/47.rom_ctrl_max_throughput_chk/latest |
| Test location | /workspace/coverage/default/47.rom_ctrl_smoke.745415147 |
| Short name | T267 |
| Test name | |
| Test status | |
| Simulation time | 4115828040 ps |
| CPU time | 34.59 seconds |
| Started | Mar 05 01:51:51 PM PST 24 |
| Finished | Mar 05 01:52:26 PM PST 24 |
| Peak memory | 212596 kb |
| Host | smart-c0b5bb2c-6b33-42cd-b1ec-351fb8d34edb |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=745415147 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_smoke.745415147 |
| Directory | /workspace/47.rom_ctrl_smoke/latest |
| Test location | /workspace/coverage/default/47.rom_ctrl_stress_all.640528658 |
| Short name | T165 |
| Test name | |
| Test status | |
| Simulation time | 2662138056 ps |
| CPU time | 24.27 seconds |
| Started | Mar 05 01:51:57 PM PST 24 |
| Finished | Mar 05 01:52:22 PM PST 24 |
| Peak memory | 212908 kb |
| Host | smart-e21fa769-b001-4448-a055-16145185cb89 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=640528658 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test + UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 47.rom_ctrl_stress_all.640528658 |
| Directory | /workspace/47.rom_ctrl_stress_all/latest |
| Test location | /workspace/coverage/default/47.rom_ctrl_stress_all_with_rand_reset.2887231348 |
| Short name | T275 |
| Test name | |
| Test status | |
| Simulation time | 95011979360 ps |
| CPU time | 1011.61 seconds |
| Started | Mar 05 01:51:47 PM PST 24 |
| Finished | Mar 05 02:08:39 PM PST 24 |
| Peak memory | 235588 kb |
| Host | smart-3f74040d-7c1d-4b83-a0aa-25908187fdd2 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2887231348 -assert nop ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_stress_all_with_rand_reset.2887231348 |
| Directory | /workspace/47.rom_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/48.rom_ctrl_alert_test.2854923054 |
| Short name | T175 |
| Test name | |
| Test status | |
| Simulation time | 3048035224 ps |
| CPU time | 9.33 seconds |
| Started | Mar 05 01:51:52 PM PST 24 |
| Finished | Mar 05 01:52:02 PM PST 24 |
| Peak memory | 210968 kb |
| Host | smart-b7104495-ec6d-49f8-a119-2a8e13766c47 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2854923054 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_alert_test.2854923054 |
| Directory | /workspace/48.rom_ctrl_alert_test/latest |
| Test location | /workspace/coverage/default/48.rom_ctrl_corrupt_sig_fatal_chk.2489163008 |
| Short name | T360 |
| Test name | |
| Test status | |
| Simulation time | 64040229402 ps |
| CPU time | 168.47 seconds |
| Started | Mar 05 01:51:48 PM PST 24 |
| Finished | Mar 05 01:54:37 PM PST 24 |
| Peak memory | 237860 kb |
| Host | smart-e5280bc3-2a55-40dd-b612-1f43a645eb5c |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2489163008 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_ corrupt_sig_fatal_chk.2489163008 |
| Directory | /workspace/48.rom_ctrl_corrupt_sig_fatal_chk/latest |
| Test location | /workspace/coverage/default/48.rom_ctrl_kmac_err_chk.856411753 |
| Short name | T332 |
| Test name | |
| Test status | |
| Simulation time | 4662869399 ps |
| CPU time | 34.63 seconds |
| Started | Mar 05 01:51:54 PM PST 24 |
| Finished | Mar 05 01:52:29 PM PST 24 |
| Peak memory | 211856 kb |
| Host | smart-a9c62eb5-07e5-4f71-b31b-0061353ad850 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=856411753 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_kmac_err_chk.856411753 |
| Directory | /workspace/48.rom_ctrl_kmac_err_chk/latest |
| Test location | /workspace/coverage/default/48.rom_ctrl_max_throughput_chk.3974054320 |
| Short name | T260 |
| Test name | |
| Test status | |
| Simulation time | 1438108450 ps |
| CPU time | 14.23 seconds |
| Started | Mar 05 01:51:51 PM PST 24 |
| Finished | Mar 05 01:52:06 PM PST 24 |
| Peak memory | 210732 kb |
| Host | smart-6d660bb3-fab4-4724-bbba-0bb582dc0d1c |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3974054320 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_max_throughput_chk.3974054320 |
| Directory | /workspace/48.rom_ctrl_max_throughput_chk/latest |
| Test location | /workspace/coverage/default/48.rom_ctrl_smoke.68977554 |
| Short name | T299 |
| Test name | |
| Test status | |
| Simulation time | 2599235189 ps |
| CPU time | 21.82 seconds |
| Started | Mar 05 01:51:54 PM PST 24 |
| Finished | Mar 05 01:52:16 PM PST 24 |
| Peak memory | 212716 kb |
| Host | smart-7a78e5fe-a816-4f82-85c0-b8d280bad70b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=68977554 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_smoke.68977554 |
| Directory | /workspace/48.rom_ctrl_smoke/latest |
| Test location | /workspace/coverage/default/48.rom_ctrl_stress_all.2516847568 |
| Short name | T74 |
| Test name | |
| Test status | |
| Simulation time | 1695422491 ps |
| CPU time | 28.26 seconds |
| Started | Mar 05 01:51:54 PM PST 24 |
| Finished | Mar 05 01:52:23 PM PST 24 |
| Peak memory | 215148 kb |
| Host | smart-30a14697-8dcc-4b7e-b85c-7ef079e7a987 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2516847568 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm _name 48.rom_ctrl_stress_all.2516847568 |
| Directory | /workspace/48.rom_ctrl_stress_all/latest |
| Test location | /workspace/coverage/default/49.rom_ctrl_alert_test.4199320653 |
| Short name | T43 |
| Test name | |
| Test status | |
| Simulation time | 2282679037 ps |
| CPU time | 5.8 seconds |
| Started | Mar 05 01:51:55 PM PST 24 |
| Finished | Mar 05 01:52:01 PM PST 24 |
| Peak memory | 210988 kb |
| Host | smart-bc153b50-c0e1-49bc-a79f-c8aa52632ff5 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4199320653 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_alert_test.4199320653 |
| Directory | /workspace/49.rom_ctrl_alert_test/latest |
| Test location | /workspace/coverage/default/49.rom_ctrl_corrupt_sig_fatal_chk.1567242604 |
| Short name | T45 |
| Test name | |
| Test status | |
| Simulation time | 43767356671 ps |
| CPU time | 232.63 seconds |
| Started | Mar 05 01:51:54 PM PST 24 |
| Finished | Mar 05 01:55:46 PM PST 24 |
| Peak memory | 219388 kb |
| Host | smart-47e9ad64-bf00-4bb6-a1c4-4693b85c2432 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1567242604 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_ corrupt_sig_fatal_chk.1567242604 |
| Directory | /workspace/49.rom_ctrl_corrupt_sig_fatal_chk/latest |
| Test location | /workspace/coverage/default/49.rom_ctrl_kmac_err_chk.1217125689 |
| Short name | T174 |
| Test name | |
| Test status | |
| Simulation time | 9974584074 ps |
| CPU time | 24.31 seconds |
| Started | Mar 05 01:51:52 PM PST 24 |
| Finished | Mar 05 01:52:17 PM PST 24 |
| Peak memory | 211540 kb |
| Host | smart-18495f94-a157-4698-80cb-6006beb8206f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1217125689 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_kmac_err_chk.1217125689 |
| Directory | /workspace/49.rom_ctrl_kmac_err_chk/latest |
| Test location | /workspace/coverage/default/49.rom_ctrl_max_throughput_chk.1314329212 |
| Short name | T286 |
| Test name | |
| Test status | |
| Simulation time | 16268046937 ps |
| CPU time | 17.62 seconds |
| Started | Mar 05 01:51:54 PM PST 24 |
| Finished | Mar 05 01:52:12 PM PST 24 |
| Peak memory | 210824 kb |
| Host | smart-fcd3fb2d-abb0-46d9-9947-b4df663ba92b |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1314329212 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_max_throughput_chk.1314329212 |
| Directory | /workspace/49.rom_ctrl_max_throughput_chk/latest |
| Test location | /workspace/coverage/default/49.rom_ctrl_smoke.2179704702 |
| Short name | T209 |
| Test name | |
| Test status | |
| Simulation time | 1076504879 ps |
| CPU time | 17.32 seconds |
| Started | Mar 05 01:51:59 PM PST 24 |
| Finished | Mar 05 01:52:16 PM PST 24 |
| Peak memory | 212404 kb |
| Host | smart-fb17e558-1961-42d3-a735-5247316edec8 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2179704702 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_smoke.2179704702 |
| Directory | /workspace/49.rom_ctrl_smoke/latest |
| Test location | /workspace/coverage/default/49.rom_ctrl_stress_all.559235212 |
| Short name | T340 |
| Test name | |
| Test status | |
| Simulation time | 1153232524 ps |
| CPU time | 17.39 seconds |
| Started | Mar 05 01:51:50 PM PST 24 |
| Finished | Mar 05 01:52:08 PM PST 24 |
| Peak memory | 212680 kb |
| Host | smart-b34bf7fb-3393-43af-85fc-1fb0eb084df2 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=559235212 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test + UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 49.rom_ctrl_stress_all.559235212 |
| Directory | /workspace/49.rom_ctrl_stress_all/latest |
| Test location | /workspace/coverage/default/5.rom_ctrl_alert_test.3462871681 |
| Short name | T152 |
| Test name | |
| Test status | |
| Simulation time | 500962639 ps |
| CPU time | 7.52 seconds |
| Started | Mar 05 01:51:13 PM PST 24 |
| Finished | Mar 05 01:51:21 PM PST 24 |
| Peak memory | 210892 kb |
| Host | smart-417d1ecf-a168-43cb-b4a0-1b25dffe1fcf |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3462871681 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_alert_test.3462871681 |
| Directory | /workspace/5.rom_ctrl_alert_test/latest |
| Test location | /workspace/coverage/default/5.rom_ctrl_corrupt_sig_fatal_chk.762813352 |
| Short name | T229 |
| Test name | |
| Test status | |
| Simulation time | 19382817700 ps |
| CPU time | 148.33 seconds |
| Started | Mar 05 01:51:07 PM PST 24 |
| Finished | Mar 05 01:53:35 PM PST 24 |
| Peak memory | 237428 kb |
| Host | smart-88de0132-b0e4-483c-9709-1d1271b704ba |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=762813352 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt _sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_co rrupt_sig_fatal_chk.762813352 |
| Directory | /workspace/5.rom_ctrl_corrupt_sig_fatal_chk/latest |
| Test location | /workspace/coverage/default/5.rom_ctrl_kmac_err_chk.1722561193 |
| Short name | T314 |
| Test name | |
| Test status | |
| Simulation time | 348326774 ps |
| CPU time | 9.34 seconds |
| Started | Mar 05 01:51:05 PM PST 24 |
| Finished | Mar 05 01:51:14 PM PST 24 |
| Peak memory | 211508 kb |
| Host | smart-2ebe044c-3bca-45ce-892e-1476cdbdbb66 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1722561193 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_kmac_err_chk.1722561193 |
| Directory | /workspace/5.rom_ctrl_kmac_err_chk/latest |
| Test location | /workspace/coverage/default/5.rom_ctrl_max_throughput_chk.2063178107 |
| Short name | T16 |
| Test name | |
| Test status | |
| Simulation time | 7514765927 ps |
| CPU time | 13.28 seconds |
| Started | Mar 05 01:51:05 PM PST 24 |
| Finished | Mar 05 01:51:18 PM PST 24 |
| Peak memory | 210896 kb |
| Host | smart-4b3fa3df-a2b2-4a93-ab8b-64f6e0209a0b |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2063178107 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_max_throughput_chk.2063178107 |
| Directory | /workspace/5.rom_ctrl_max_throughput_chk/latest |
| Test location | /workspace/coverage/default/5.rom_ctrl_smoke.2736647539 |
| Short name | T356 |
| Test name | |
| Test status | |
| Simulation time | 5039088118 ps |
| CPU time | 29.49 seconds |
| Started | Mar 05 01:51:22 PM PST 24 |
| Finished | Mar 05 01:51:52 PM PST 24 |
| Peak memory | 212824 kb |
| Host | smart-98671311-aac5-4791-8048-48eed8004605 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2736647539 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_smoke.2736647539 |
| Directory | /workspace/5.rom_ctrl_smoke/latest |
| Test location | /workspace/coverage/default/5.rom_ctrl_stress_all.3038703175 |
| Short name | T140 |
| Test name | |
| Test status | |
| Simulation time | 1768363725 ps |
| CPU time | 19.33 seconds |
| Started | Mar 05 01:51:24 PM PST 24 |
| Finished | Mar 05 01:51:44 PM PST 24 |
| Peak memory | 213000 kb |
| Host | smart-ff836de2-970c-469d-9a1d-3f0259f46417 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3038703175 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm _name 5.rom_ctrl_stress_all.3038703175 |
| Directory | /workspace/5.rom_ctrl_stress_all/latest |
| Test location | /workspace/coverage/default/6.rom_ctrl_alert_test.101619871 |
| Short name | T251 |
| Test name | |
| Test status | |
| Simulation time | 522476644 ps |
| CPU time | 5.26 seconds |
| Started | Mar 05 01:51:18 PM PST 24 |
| Finished | Mar 05 01:51:24 PM PST 24 |
| Peak memory | 210904 kb |
| Host | smart-90e7ce1e-2717-4355-9c92-1d629caac6c2 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=101619871 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_alert_test.101619871 |
| Directory | /workspace/6.rom_ctrl_alert_test/latest |
| Test location | /workspace/coverage/default/6.rom_ctrl_corrupt_sig_fatal_chk.1133577175 |
| Short name | T150 |
| Test name | |
| Test status | |
| Simulation time | 5306852266 ps |
| CPU time | 84.82 seconds |
| Started | Mar 05 01:51:17 PM PST 24 |
| Finished | Mar 05 01:52:42 PM PST 24 |
| Peak memory | 232648 kb |
| Host | smart-3c206d84-1a03-4943-8aa6-97553e7a13df |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1133577175 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_c orrupt_sig_fatal_chk.1133577175 |
| Directory | /workspace/6.rom_ctrl_corrupt_sig_fatal_chk/latest |
| Test location | /workspace/coverage/default/6.rom_ctrl_kmac_err_chk.3994418595 |
| Short name | T311 |
| Test name | |
| Test status | |
| Simulation time | 7161545428 ps |
| CPU time | 20.61 seconds |
| Started | Mar 05 01:51:07 PM PST 24 |
| Finished | Mar 05 01:51:28 PM PST 24 |
| Peak memory | 211740 kb |
| Host | smart-71230294-53e1-4c53-85de-35b8a97b69a8 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3994418595 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_kmac_err_chk.3994418595 |
| Directory | /workspace/6.rom_ctrl_kmac_err_chk/latest |
| Test location | /workspace/coverage/default/6.rom_ctrl_max_throughput_chk.179699472 |
| Short name | T205 |
| Test name | |
| Test status | |
| Simulation time | 7414497646 ps |
| CPU time | 16.45 seconds |
| Started | Mar 05 01:51:00 PM PST 24 |
| Finished | Mar 05 01:51:17 PM PST 24 |
| Peak memory | 210868 kb |
| Host | smart-16c65ab1-1d38-41d9-9367-4b997f7f1c29 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=179699472 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_max_throughput_chk.179699472 |
| Directory | /workspace/6.rom_ctrl_max_throughput_chk/latest |
| Test location | /workspace/coverage/default/6.rom_ctrl_smoke.1590334153 |
| Short name | T347 |
| Test name | |
| Test status | |
| Simulation time | 381146357 ps |
| CPU time | 10.13 seconds |
| Started | Mar 05 01:51:23 PM PST 24 |
| Finished | Mar 05 01:51:33 PM PST 24 |
| Peak memory | 212988 kb |
| Host | smart-8e008e94-262e-4f30-88df-30e6602e2769 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1590334153 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_smoke.1590334153 |
| Directory | /workspace/6.rom_ctrl_smoke/latest |
| Test location | /workspace/coverage/default/6.rom_ctrl_stress_all.3484586773 |
| Short name | T132 |
| Test name | |
| Test status | |
| Simulation time | 9948171858 ps |
| CPU time | 86.74 seconds |
| Started | Mar 05 01:51:00 PM PST 24 |
| Finished | Mar 05 01:52:27 PM PST 24 |
| Peak memory | 215392 kb |
| Host | smart-618137dd-ccc2-4c86-83a1-c419fe699e36 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3484586773 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm _name 6.rom_ctrl_stress_all.3484586773 |
| Directory | /workspace/6.rom_ctrl_stress_all/latest |
| Test location | /workspace/coverage/default/7.rom_ctrl_alert_test.1685441559 |
| Short name | T273 |
| Test name | |
| Test status | |
| Simulation time | 2473157182 ps |
| CPU time | 11.81 seconds |
| Started | Mar 05 01:51:24 PM PST 24 |
| Finished | Mar 05 01:51:36 PM PST 24 |
| Peak memory | 210892 kb |
| Host | smart-b1a55060-49c2-44bc-bb90-e560dc7fcdd0 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1685441559 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_alert_test.1685441559 |
| Directory | /workspace/7.rom_ctrl_alert_test/latest |
| Test location | /workspace/coverage/default/7.rom_ctrl_corrupt_sig_fatal_chk.1167706296 |
| Short name | T211 |
| Test name | |
| Test status | |
| Simulation time | 157569803625 ps |
| CPU time | 447.96 seconds |
| Started | Mar 05 01:50:58 PM PST 24 |
| Finished | Mar 05 01:58:26 PM PST 24 |
| Peak memory | 224452 kb |
| Host | smart-bae66334-0964-4aab-b625-691b45bbccf9 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1167706296 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_c orrupt_sig_fatal_chk.1167706296 |
| Directory | /workspace/7.rom_ctrl_corrupt_sig_fatal_chk/latest |
| Test location | /workspace/coverage/default/7.rom_ctrl_kmac_err_chk.1758858852 |
| Short name | T18 |
| Test name | |
| Test status | |
| Simulation time | 640155812 ps |
| CPU time | 9.73 seconds |
| Started | Mar 05 01:51:08 PM PST 24 |
| Finished | Mar 05 01:51:18 PM PST 24 |
| Peak memory | 211584 kb |
| Host | smart-599adee3-c351-472a-b446-a0d1d912208f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1758858852 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_kmac_err_chk.1758858852 |
| Directory | /workspace/7.rom_ctrl_kmac_err_chk/latest |
| Test location | /workspace/coverage/default/7.rom_ctrl_max_throughput_chk.521964484 |
| Short name | T183 |
| Test name | |
| Test status | |
| Simulation time | 97211918 ps |
| CPU time | 5.71 seconds |
| Started | Mar 05 01:51:20 PM PST 24 |
| Finished | Mar 05 01:51:26 PM PST 24 |
| Peak memory | 210812 kb |
| Host | smart-3dcf6871-997a-4220-902a-cabfe2e012b3 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=521964484 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_max_throughput_chk.521964484 |
| Directory | /workspace/7.rom_ctrl_max_throughput_chk/latest |
| Test location | /workspace/coverage/default/7.rom_ctrl_smoke.3814164949 |
| Short name | T14 |
| Test name | |
| Test status | |
| Simulation time | 193447452 ps |
| CPU time | 10.48 seconds |
| Started | Mar 05 01:51:20 PM PST 24 |
| Finished | Mar 05 01:51:31 PM PST 24 |
| Peak memory | 212856 kb |
| Host | smart-5f9489b6-a3c6-4614-9af3-ce1a7b0996ce |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3814164949 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_smoke.3814164949 |
| Directory | /workspace/7.rom_ctrl_smoke/latest |
| Test location | /workspace/coverage/default/7.rom_ctrl_stress_all.759398181 |
| Short name | T235 |
| Test name | |
| Test status | |
| Simulation time | 477298563 ps |
| CPU time | 25.11 seconds |
| Started | Mar 05 01:51:20 PM PST 24 |
| Finished | Mar 05 01:51:45 PM PST 24 |
| Peak memory | 216172 kb |
| Host | smart-6d9c1310-4a91-4f0a-a6b4-05320f63a079 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=759398181 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test + UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 7.rom_ctrl_stress_all.759398181 |
| Directory | /workspace/7.rom_ctrl_stress_all/latest |
| Test location | /workspace/coverage/default/8.rom_ctrl_alert_test.1819203552 |
| Short name | T358 |
| Test name | |
| Test status | |
| Simulation time | 4884587715 ps |
| CPU time | 11.73 seconds |
| Started | Mar 05 01:51:23 PM PST 24 |
| Finished | Mar 05 01:51:34 PM PST 24 |
| Peak memory | 210932 kb |
| Host | smart-7ab5869e-ba84-466f-b063-ef4e57cc286d |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1819203552 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_alert_test.1819203552 |
| Directory | /workspace/8.rom_ctrl_alert_test/latest |
| Test location | /workspace/coverage/default/8.rom_ctrl_corrupt_sig_fatal_chk.2876448063 |
| Short name | T166 |
| Test name | |
| Test status | |
| Simulation time | 62071136762 ps |
| CPU time | 324.9 seconds |
| Started | Mar 05 01:51:20 PM PST 24 |
| Finished | Mar 05 01:56:45 PM PST 24 |
| Peak memory | 228196 kb |
| Host | smart-1e03a948-3429-433d-ae25-79eb6b1c1362 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2876448063 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_c orrupt_sig_fatal_chk.2876448063 |
| Directory | /workspace/8.rom_ctrl_corrupt_sig_fatal_chk/latest |
| Test location | /workspace/coverage/default/8.rom_ctrl_kmac_err_chk.648961884 |
| Short name | T250 |
| Test name | |
| Test status | |
| Simulation time | 3905298765 ps |
| CPU time | 32.23 seconds |
| Started | Mar 05 01:51:24 PM PST 24 |
| Finished | Mar 05 01:51:56 PM PST 24 |
| Peak memory | 211460 kb |
| Host | smart-b0f62881-f401-4bf8-915b-7db6e15e4caa |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=648961884 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_kmac_err_chk.648961884 |
| Directory | /workspace/8.rom_ctrl_kmac_err_chk/latest |
| Test location | /workspace/coverage/default/8.rom_ctrl_max_throughput_chk.2493410851 |
| Short name | T355 |
| Test name | |
| Test status | |
| Simulation time | 1399669700 ps |
| CPU time | 13.18 seconds |
| Started | Mar 05 01:51:14 PM PST 24 |
| Finished | Mar 05 01:51:28 PM PST 24 |
| Peak memory | 210796 kb |
| Host | smart-b3de8668-859e-4717-9577-01435163a546 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2493410851 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_max_throughput_chk.2493410851 |
| Directory | /workspace/8.rom_ctrl_max_throughput_chk/latest |
| Test location | /workspace/coverage/default/8.rom_ctrl_smoke.1880850027 |
| Short name | T292 |
| Test name | |
| Test status | |
| Simulation time | 14502339732 ps |
| CPU time | 30.64 seconds |
| Started | Mar 05 01:51:04 PM PST 24 |
| Finished | Mar 05 01:51:34 PM PST 24 |
| Peak memory | 219028 kb |
| Host | smart-9bc3b996-c221-4cfe-bfa8-2bf36588d4de |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1880850027 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_smoke.1880850027 |
| Directory | /workspace/8.rom_ctrl_smoke/latest |
| Test location | /workspace/coverage/default/8.rom_ctrl_stress_all.2393217688 |
| Short name | T245 |
| Test name | |
| Test status | |
| Simulation time | 887029510 ps |
| CPU time | 31.4 seconds |
| Started | Mar 05 01:51:09 PM PST 24 |
| Finished | Mar 05 01:51:40 PM PST 24 |
| Peak memory | 216060 kb |
| Host | smart-5b7048cf-523b-4ed2-8a45-d7096e74ce5f |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2393217688 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm _name 8.rom_ctrl_stress_all.2393217688 |
| Directory | /workspace/8.rom_ctrl_stress_all/latest |
| Test location | /workspace/coverage/default/9.rom_ctrl_alert_test.1292345448 |
| Short name | T123 |
| Test name | |
| Test status | |
| Simulation time | 249543170 ps |
| CPU time | 6.19 seconds |
| Started | Mar 05 01:51:16 PM PST 24 |
| Finished | Mar 05 01:51:22 PM PST 24 |
| Peak memory | 211036 kb |
| Host | smart-01d2977a-5a9e-46cf-b31c-2b149f7b0811 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1292345448 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_alert_test.1292345448 |
| Directory | /workspace/9.rom_ctrl_alert_test/latest |
| Test location | /workspace/coverage/default/9.rom_ctrl_corrupt_sig_fatal_chk.1174620319 |
| Short name | T169 |
| Test name | |
| Test status | |
| Simulation time | 2477514662 ps |
| CPU time | 80.85 seconds |
| Started | Mar 05 01:51:04 PM PST 24 |
| Finished | Mar 05 01:52:25 PM PST 24 |
| Peak memory | 236104 kb |
| Host | smart-d1e5d239-b8ee-4e8c-ab2e-e63cdd95d087 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1174620319 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_c orrupt_sig_fatal_chk.1174620319 |
| Directory | /workspace/9.rom_ctrl_corrupt_sig_fatal_chk/latest |
| Test location | /workspace/coverage/default/9.rom_ctrl_kmac_err_chk.354789496 |
| Short name | T145 |
| Test name | |
| Test status | |
| Simulation time | 3755894220 ps |
| CPU time | 30.81 seconds |
| Started | Mar 05 01:51:07 PM PST 24 |
| Finished | Mar 05 01:51:38 PM PST 24 |
| Peak memory | 211556 kb |
| Host | smart-c8d0e64c-7065-4b61-939f-2291b4feb8a7 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=354789496 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_kmac_err_chk.354789496 |
| Directory | /workspace/9.rom_ctrl_kmac_err_chk/latest |
| Test location | /workspace/coverage/default/9.rom_ctrl_max_throughput_chk.49968101 |
| Short name | T283 |
| Test name | |
| Test status | |
| Simulation time | 1501689034 ps |
| CPU time | 14.7 seconds |
| Started | Mar 05 01:51:19 PM PST 24 |
| Finished | Mar 05 01:51:34 PM PST 24 |
| Peak memory | 210692 kb |
| Host | smart-e5b683e1-0c18-4f74-93bc-bf1bddf1dc0c |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=49968101 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_max_throughput_chk.49968101 |
| Directory | /workspace/9.rom_ctrl_max_throughput_chk/latest |
| Test location | /workspace/coverage/default/9.rom_ctrl_smoke.614883272 |
| Short name | T359 |
| Test name | |
| Test status | |
| Simulation time | 3710082627 ps |
| CPU time | 18.73 seconds |
| Started | Mar 05 01:50:55 PM PST 24 |
| Finished | Mar 05 01:51:14 PM PST 24 |
| Peak memory | 213064 kb |
| Host | smart-df29b2dd-4c28-4d65-9fc4-04722d35f91d |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=614883272 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_smoke.614883272 |
| Directory | /workspace/9.rom_ctrl_smoke/latest |
| Test location | /workspace/coverage/default/9.rom_ctrl_stress_all.379497400 |
| Short name | T352 |
| Test name | |
| Test status | |
| Simulation time | 13230109451 ps |
| CPU time | 42.42 seconds |
| Started | Mar 05 01:51:29 PM PST 24 |
| Finished | Mar 05 01:52:17 PM PST 24 |
| Peak memory | 219124 kb |
| Host | smart-88369321-0174-4c7a-9adc-a3ba0cb2547c |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=379497400 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test + UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 9.rom_ctrl_stress_all.379497400 |
| Directory | /workspace/9.rom_ctrl_stress_all/latest |
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