Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
97.59 97.04 92.80 97.88 100.00 98.69 97.89 98.84


Total test records in report: 463
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T297 /workspace/coverage/default/39.rom_ctrl_alert_test.312271879 Mar 07 12:55:53 PM PST 24 Mar 07 12:56:09 PM PST 24 4120403179 ps
T298 /workspace/coverage/default/21.rom_ctrl_max_throughput_chk.1148632409 Mar 07 12:55:46 PM PST 24 Mar 07 12:56:00 PM PST 24 2850274611 ps
T299 /workspace/coverage/default/40.rom_ctrl_alert_test.283770598 Mar 07 12:55:48 PM PST 24 Mar 07 12:55:57 PM PST 24 2901760231 ps
T300 /workspace/coverage/default/45.rom_ctrl_smoke.2026624927 Mar 07 12:55:52 PM PST 24 Mar 07 12:56:05 PM PST 24 1999992384 ps
T301 /workspace/coverage/default/9.rom_ctrl_stress_all.1668414411 Mar 07 12:55:28 PM PST 24 Mar 07 12:55:49 PM PST 24 1115348900 ps
T302 /workspace/coverage/default/38.rom_ctrl_alert_test.944936983 Mar 07 12:55:41 PM PST 24 Mar 07 12:55:56 PM PST 24 7495683658 ps
T303 /workspace/coverage/default/11.rom_ctrl_corrupt_sig_fatal_chk.1457936970 Mar 07 12:55:24 PM PST 24 Mar 07 01:01:31 PM PST 24 115315406829 ps
T304 /workspace/coverage/default/10.rom_ctrl_max_throughput_chk.738916101 Mar 07 12:55:13 PM PST 24 Mar 07 12:55:22 PM PST 24 1912346073 ps
T305 /workspace/coverage/default/40.rom_ctrl_kmac_err_chk.1961420742 Mar 07 12:55:47 PM PST 24 Mar 07 12:55:59 PM PST 24 2753550152 ps
T306 /workspace/coverage/default/26.rom_ctrl_corrupt_sig_fatal_chk.3862030347 Mar 07 12:55:40 PM PST 24 Mar 07 12:57:46 PM PST 24 3140385537 ps
T307 /workspace/coverage/default/45.rom_ctrl_corrupt_sig_fatal_chk.3212676229 Mar 07 12:56:07 PM PST 24 Mar 07 12:58:01 PM PST 24 6783520665 ps
T308 /workspace/coverage/default/45.rom_ctrl_alert_test.3734268638 Mar 07 12:55:48 PM PST 24 Mar 07 12:56:02 PM PST 24 1575844018 ps
T309 /workspace/coverage/default/31.rom_ctrl_stress_all.950418433 Mar 07 12:55:29 PM PST 24 Mar 07 12:55:43 PM PST 24 1019143971 ps
T310 /workspace/coverage/default/14.rom_ctrl_stress_all.4093341755 Mar 07 12:55:16 PM PST 24 Mar 07 12:55:37 PM PST 24 7856316592 ps
T311 /workspace/coverage/default/43.rom_ctrl_stress_all.2004950526 Mar 07 12:55:53 PM PST 24 Mar 07 12:56:44 PM PST 24 56842216322 ps
T312 /workspace/coverage/default/9.rom_ctrl_kmac_err_chk.258771633 Mar 07 12:55:14 PM PST 24 Mar 07 12:55:35 PM PST 24 21649329332 ps
T313 /workspace/coverage/default/41.rom_ctrl_corrupt_sig_fatal_chk.3080125010 Mar 07 12:55:45 PM PST 24 Mar 07 01:02:17 PM PST 24 147701275204 ps
T314 /workspace/coverage/default/12.rom_ctrl_alert_test.2552613280 Mar 07 12:55:36 PM PST 24 Mar 07 12:55:41 PM PST 24 346901981 ps
T315 /workspace/coverage/default/19.rom_ctrl_max_throughput_chk.594328237 Mar 07 12:55:20 PM PST 24 Mar 07 12:55:26 PM PST 24 390814622 ps
T316 /workspace/coverage/default/37.rom_ctrl_max_throughput_chk.1352253995 Mar 07 12:55:35 PM PST 24 Mar 07 12:55:51 PM PST 24 10388988266 ps
T317 /workspace/coverage/default/32.rom_ctrl_smoke.2428231555 Mar 07 12:55:45 PM PST 24 Mar 07 12:56:16 PM PST 24 3526883677 ps
T318 /workspace/coverage/default/6.rom_ctrl_alert_test.2511296960 Mar 07 12:55:24 PM PST 24 Mar 07 12:55:29 PM PST 24 553547592 ps
T319 /workspace/coverage/default/36.rom_ctrl_kmac_err_chk.379406186 Mar 07 12:55:50 PM PST 24 Mar 07 12:56:05 PM PST 24 1021341540 ps
T320 /workspace/coverage/default/49.rom_ctrl_max_throughput_chk.3043080574 Mar 07 12:55:48 PM PST 24 Mar 07 12:56:00 PM PST 24 1148415223 ps
T40 /workspace/coverage/default/3.rom_ctrl_sec_cm.1835366044 Mar 07 12:55:15 PM PST 24 Mar 07 12:56:16 PM PST 24 5097068449 ps
T321 /workspace/coverage/default/30.rom_ctrl_kmac_err_chk.1370848671 Mar 07 12:55:31 PM PST 24 Mar 07 12:55:49 PM PST 24 2634480302 ps
T322 /workspace/coverage/default/26.rom_ctrl_alert_test.4000958763 Mar 07 12:55:29 PM PST 24 Mar 07 12:55:41 PM PST 24 3779849219 ps
T323 /workspace/coverage/default/45.rom_ctrl_max_throughput_chk.1661828627 Mar 07 12:55:42 PM PST 24 Mar 07 12:55:53 PM PST 24 3799409041 ps
T324 /workspace/coverage/default/41.rom_ctrl_alert_test.227006862 Mar 07 12:55:43 PM PST 24 Mar 07 12:55:50 PM PST 24 462889963 ps
T325 /workspace/coverage/default/45.rom_ctrl_kmac_err_chk.561466436 Mar 07 12:55:47 PM PST 24 Mar 07 12:56:20 PM PST 24 7624242948 ps
T326 /workspace/coverage/default/11.rom_ctrl_max_throughput_chk.2692862465 Mar 07 12:55:26 PM PST 24 Mar 07 12:55:41 PM PST 24 6147636072 ps
T327 /workspace/coverage/default/30.rom_ctrl_smoke.4041282992 Mar 07 12:55:30 PM PST 24 Mar 07 12:56:00 PM PST 24 9950441724 ps
T328 /workspace/coverage/default/2.rom_ctrl_max_throughput_chk.2679331987 Mar 07 12:54:59 PM PST 24 Mar 07 12:55:16 PM PST 24 2028539707 ps
T329 /workspace/coverage/default/31.rom_ctrl_kmac_err_chk.1016643002 Mar 07 12:55:19 PM PST 24 Mar 07 12:55:54 PM PST 24 4183553131 ps
T330 /workspace/coverage/default/28.rom_ctrl_stress_all.3149399144 Mar 07 12:56:05 PM PST 24 Mar 07 12:56:59 PM PST 24 5444940104 ps
T331 /workspace/coverage/default/1.rom_ctrl_max_throughput_chk.2948340418 Mar 07 12:55:16 PM PST 24 Mar 07 12:55:29 PM PST 24 879912591 ps
T332 /workspace/coverage/default/2.rom_ctrl_corrupt_sig_fatal_chk.146523283 Mar 07 12:55:14 PM PST 24 Mar 07 12:56:35 PM PST 24 5689793872 ps
T333 /workspace/coverage/default/38.rom_ctrl_corrupt_sig_fatal_chk.607139180 Mar 07 12:55:45 PM PST 24 Mar 07 12:59:50 PM PST 24 17454738883 ps
T334 /workspace/coverage/default/12.rom_ctrl_max_throughput_chk.3807272008 Mar 07 12:55:25 PM PST 24 Mar 07 12:55:35 PM PST 24 7859286690 ps
T335 /workspace/coverage/default/20.rom_ctrl_smoke.363600811 Mar 07 12:55:36 PM PST 24 Mar 07 12:56:13 PM PST 24 17523916010 ps
T336 /workspace/coverage/default/7.rom_ctrl_max_throughput_chk.3650284533 Mar 07 12:55:23 PM PST 24 Mar 07 12:55:31 PM PST 24 354502221 ps
T337 /workspace/coverage/default/35.rom_ctrl_kmac_err_chk.1021951772 Mar 07 12:55:53 PM PST 24 Mar 07 12:56:17 PM PST 24 2093874731 ps
T338 /workspace/coverage/default/7.rom_ctrl_alert_test.3098167344 Mar 07 12:55:00 PM PST 24 Mar 07 12:55:10 PM PST 24 3253119874 ps
T339 /workspace/coverage/default/28.rom_ctrl_stress_all_with_rand_reset.1524383793 Mar 07 12:55:44 PM PST 24 Mar 07 01:22:16 PM PST 24 42599159572 ps
T340 /workspace/coverage/default/17.rom_ctrl_stress_all.2534180947 Mar 07 12:55:24 PM PST 24 Mar 07 12:56:22 PM PST 24 24807494213 ps
T341 /workspace/coverage/default/47.rom_ctrl_kmac_err_chk.860272986 Mar 07 12:55:44 PM PST 24 Mar 07 12:56:15 PM PST 24 19486913023 ps
T342 /workspace/coverage/default/38.rom_ctrl_kmac_err_chk.1849494550 Mar 07 12:55:32 PM PST 24 Mar 07 12:55:56 PM PST 24 1559168874 ps
T343 /workspace/coverage/default/31.rom_ctrl_smoke.3706187758 Mar 07 12:55:37 PM PST 24 Mar 07 12:56:12 PM PST 24 9696497011 ps
T344 /workspace/coverage/default/4.rom_ctrl_alert_test.403272093 Mar 07 12:55:10 PM PST 24 Mar 07 12:55:25 PM PST 24 1700847436 ps
T345 /workspace/coverage/default/3.rom_ctrl_stress_all.2285321671 Mar 07 12:55:17 PM PST 24 Mar 07 12:56:16 PM PST 24 21681888164 ps
T346 /workspace/coverage/default/22.rom_ctrl_max_throughput_chk.3288503896 Mar 07 12:55:30 PM PST 24 Mar 07 12:55:37 PM PST 24 1300256604 ps
T347 /workspace/coverage/default/35.rom_ctrl_stress_all.4254737057 Mar 07 12:55:43 PM PST 24 Mar 07 12:56:40 PM PST 24 5601171879 ps
T348 /workspace/coverage/default/3.rom_ctrl_corrupt_sig_fatal_chk.2075535876 Mar 07 12:55:04 PM PST 24 Mar 07 12:56:47 PM PST 24 6105975926 ps
T349 /workspace/coverage/default/45.rom_ctrl_stress_all.2852589544 Mar 07 12:55:49 PM PST 24 Mar 07 12:56:21 PM PST 24 4476006251 ps
T350 /workspace/coverage/default/48.rom_ctrl_smoke.3643554970 Mar 07 12:55:48 PM PST 24 Mar 07 12:56:01 PM PST 24 907373340 ps
T351 /workspace/coverage/default/29.rom_ctrl_stress_all.3733572564 Mar 07 12:55:34 PM PST 24 Mar 07 12:56:41 PM PST 24 29029396682 ps
T352 /workspace/coverage/default/8.rom_ctrl_stress_all.3972293530 Mar 07 12:55:12 PM PST 24 Mar 07 12:55:44 PM PST 24 3750211366 ps
T353 /workspace/coverage/default/42.rom_ctrl_stress_all_with_rand_reset.102690929 Mar 07 12:56:03 PM PST 24 Mar 07 01:14:16 PM PST 24 109297483840 ps
T354 /workspace/coverage/default/2.rom_ctrl_alert_test.1725432544 Mar 07 12:55:02 PM PST 24 Mar 07 12:55:12 PM PST 24 659469154 ps
T355 /workspace/coverage/default/46.rom_ctrl_max_throughput_chk.1474968554 Mar 07 12:56:02 PM PST 24 Mar 07 12:56:14 PM PST 24 2188766918 ps
T356 /workspace/coverage/default/36.rom_ctrl_stress_all.605814360 Mar 07 12:55:40 PM PST 24 Mar 07 12:55:51 PM PST 24 1458220624 ps
T357 /workspace/coverage/default/30.rom_ctrl_corrupt_sig_fatal_chk.2877702917 Mar 07 12:56:13 PM PST 24 Mar 07 12:57:46 PM PST 24 6216378763 ps
T358 /workspace/coverage/default/2.rom_ctrl_smoke.3596786263 Mar 07 12:55:26 PM PST 24 Mar 07 12:55:47 PM PST 24 7910172844 ps
T359 /workspace/coverage/default/22.rom_ctrl_corrupt_sig_fatal_chk.804354866 Mar 07 12:55:50 PM PST 24 Mar 07 01:02:13 PM PST 24 395130586765 ps
T360 /workspace/coverage/default/13.rom_ctrl_corrupt_sig_fatal_chk.2438819639 Mar 07 12:55:17 PM PST 24 Mar 07 12:59:11 PM PST 24 123728827539 ps
T361 /workspace/coverage/default/49.rom_ctrl_alert_test.1478954703 Mar 07 12:55:46 PM PST 24 Mar 07 12:55:56 PM PST 24 1751565649 ps
T362 /workspace/coverage/default/5.rom_ctrl_stress_all.3875411033 Mar 07 12:55:26 PM PST 24 Mar 07 12:56:09 PM PST 24 3833650255 ps
T363 /workspace/coverage/default/4.rom_ctrl_smoke.1428831057 Mar 07 12:55:15 PM PST 24 Mar 07 12:55:27 PM PST 24 404634825 ps
T70 /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_mem_rw_with_rand_reset.599508992 Mar 07 12:54:17 PM PST 24 Mar 07 12:54:32 PM PST 24 1891372112 ps
T71 /workspace/coverage/cover_reg_top/7.rom_ctrl_same_csr_outstanding.3182380126 Mar 07 12:54:26 PM PST 24 Mar 07 12:54:31 PM PST 24 921297609 ps
T72 /workspace/coverage/cover_reg_top/9.rom_ctrl_same_csr_outstanding.1412304311 Mar 07 12:54:08 PM PST 24 Mar 07 12:54:12 PM PST 24 89316522 ps
T66 /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_intg_err.1411147140 Mar 07 12:54:17 PM PST 24 Mar 07 12:55:35 PM PST 24 9916747227 ps
T67 /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_intg_err.811711505 Mar 07 12:53:56 PM PST 24 Mar 07 12:55:17 PM PST 24 17186995036 ps
T79 /workspace/coverage/cover_reg_top/4.rom_ctrl_same_csr_outstanding.3014934720 Mar 07 12:54:01 PM PST 24 Mar 07 12:54:10 PM PST 24 892321608 ps
T80 /workspace/coverage/cover_reg_top/4.rom_ctrl_passthru_mem_tl_intg_err.2121540801 Mar 07 12:54:17 PM PST 24 Mar 07 12:54:46 PM PST 24 1135937492 ps
T104 /workspace/coverage/cover_reg_top/1.rom_ctrl_passthru_mem_tl_intg_err.736497615 Mar 07 12:53:59 PM PST 24 Mar 07 12:55:04 PM PST 24 12868655042 ps
T364 /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_walk.3369990545 Mar 07 12:54:00 PM PST 24 Mar 07 12:54:12 PM PST 24 4111501669 ps
T105 /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_rw.675340355 Mar 07 12:54:08 PM PST 24 Mar 07 12:54:13 PM PST 24 167759387 ps
T365 /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_mem_rw_with_rand_reset.4090020969 Mar 07 12:54:00 PM PST 24 Mar 07 12:54:13 PM PST 24 5908822022 ps
T107 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_rw.221037665 Mar 07 12:54:25 PM PST 24 Mar 07 12:54:34 PM PST 24 861383353 ps
T81 /workspace/coverage/cover_reg_top/3.rom_ctrl_passthru_mem_tl_intg_err.1948260616 Mar 07 12:54:13 PM PST 24 Mar 07 12:54:58 PM PST 24 19686619877 ps
T366 /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_mem_rw_with_rand_reset.4270873008 Mar 07 12:54:15 PM PST 24 Mar 07 12:54:20 PM PST 24 195953440 ps
T367 /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_errors.1584859337 Mar 07 12:54:12 PM PST 24 Mar 07 12:54:28 PM PST 24 1482480591 ps
T82 /workspace/coverage/cover_reg_top/7.rom_ctrl_passthru_mem_tl_intg_err.2528757297 Mar 07 12:54:24 PM PST 24 Mar 07 12:54:52 PM PST 24 1358105881 ps
T106 /workspace/coverage/cover_reg_top/8.rom_ctrl_same_csr_outstanding.216119673 Mar 07 12:54:22 PM PST 24 Mar 07 12:54:27 PM PST 24 94076753 ps
T368 /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_errors.2508976033 Mar 07 12:54:16 PM PST 24 Mar 07 12:54:24 PM PST 24 85623716 ps
T83 /workspace/coverage/cover_reg_top/10.rom_ctrl_passthru_mem_tl_intg_err.2406904343 Mar 07 12:54:09 PM PST 24 Mar 07 12:54:37 PM PST 24 2347113041 ps
T68 /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_intg_err.1179768740 Mar 07 12:54:26 PM PST 24 Mar 07 12:55:06 PM PST 24 6878776825 ps
T84 /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_rw.825751840 Mar 07 12:54:04 PM PST 24 Mar 07 12:54:15 PM PST 24 1026693890 ps
T85 /workspace/coverage/cover_reg_top/17.rom_ctrl_same_csr_outstanding.1577151937 Mar 07 12:54:32 PM PST 24 Mar 07 12:54:46 PM PST 24 7018077947 ps
T369 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_hw_reset.2540090249 Mar 07 12:54:00 PM PST 24 Mar 07 12:54:17 PM PST 24 1315631351 ps
T370 /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_rw.2811880237 Mar 07 12:54:12 PM PST 24 Mar 07 12:54:26 PM PST 24 1723074730 ps
T371 /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_mem_rw_with_rand_reset.3732472122 Mar 07 12:54:16 PM PST 24 Mar 07 12:54:27 PM PST 24 4084849423 ps
T372 /workspace/coverage/cover_reg_top/14.rom_ctrl_passthru_mem_tl_intg_err.3562773259 Mar 07 12:54:14 PM PST 24 Mar 07 12:55:18 PM PST 24 7967805534 ps
T124 /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_intg_err.3551921920 Mar 07 12:54:01 PM PST 24 Mar 07 12:55:11 PM PST 24 863498281 ps
T373 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_rw.4021607887 Mar 07 12:53:55 PM PST 24 Mar 07 12:54:08 PM PST 24 1791291688 ps
T86 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_hw_reset.1502970645 Mar 07 12:54:02 PM PST 24 Mar 07 12:54:10 PM PST 24 93444617 ps
T374 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_mem_rw_with_rand_reset.307651548 Mar 07 12:53:47 PM PST 24 Mar 07 12:54:05 PM PST 24 4141469428 ps
T375 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_rw.2692770038 Mar 07 12:53:55 PM PST 24 Mar 07 12:54:03 PM PST 24 1031536560 ps
T376 /workspace/coverage/cover_reg_top/18.rom_ctrl_same_csr_outstanding.2343988132 Mar 07 12:54:24 PM PST 24 Mar 07 12:54:32 PM PST 24 4604075284 ps
T377 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_mem_rw_with_rand_reset.2953941091 Mar 07 12:54:12 PM PST 24 Mar 07 12:54:27 PM PST 24 5744180696 ps
T378 /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_mem_rw_with_rand_reset.300257165 Mar 07 12:54:11 PM PST 24 Mar 07 12:54:18 PM PST 24 525485865 ps
T379 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_bit_bash.597638606 Mar 07 12:53:53 PM PST 24 Mar 07 12:54:03 PM PST 24 3741775846 ps
T380 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_hw_reset.376383017 Mar 07 12:54:10 PM PST 24 Mar 07 12:54:25 PM PST 24 1572832651 ps
T381 /workspace/coverage/cover_reg_top/2.rom_ctrl_same_csr_outstanding.3703824775 Mar 07 12:53:57 PM PST 24 Mar 07 12:54:06 PM PST 24 769278024 ps
T382 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_bit_bash.3120878345 Mar 07 12:54:14 PM PST 24 Mar 07 12:54:28 PM PST 24 3235259816 ps
T383 /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_errors.1859223017 Mar 07 12:54:02 PM PST 24 Mar 07 12:54:24 PM PST 24 10063250840 ps
T384 /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_rw.539929623 Mar 07 12:54:19 PM PST 24 Mar 07 12:54:30 PM PST 24 2229238198 ps
T92 /workspace/coverage/cover_reg_top/8.rom_ctrl_passthru_mem_tl_intg_err.1499121772 Mar 07 12:54:15 PM PST 24 Mar 07 12:54:44 PM PST 24 4135389820 ps
T93 /workspace/coverage/cover_reg_top/5.rom_ctrl_passthru_mem_tl_intg_err.3649808556 Mar 07 12:54:12 PM PST 24 Mar 07 12:54:41 PM PST 24 3900967352 ps
T385 /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_mem_rw_with_rand_reset.4117675375 Mar 07 12:54:20 PM PST 24 Mar 07 12:54:24 PM PST 24 175393204 ps
T386 /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_mem_rw_with_rand_reset.3790143074 Mar 07 12:54:02 PM PST 24 Mar 07 12:54:14 PM PST 24 4035037480 ps
T387 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_hw_reset.4267883392 Mar 07 12:54:18 PM PST 24 Mar 07 12:54:35 PM PST 24 2028986201 ps
T94 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_aliasing.570893389 Mar 07 12:54:04 PM PST 24 Mar 07 12:54:21 PM PST 24 4275029413 ps
T388 /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_partial_access.957610698 Mar 07 12:54:02 PM PST 24 Mar 07 12:54:11 PM PST 24 2460928259 ps
T389 /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_rw.615280463 Mar 07 12:54:11 PM PST 24 Mar 07 12:54:26 PM PST 24 7729006467 ps
T112 /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_intg_err.1943813377 Mar 07 12:54:20 PM PST 24 Mar 07 12:55:36 PM PST 24 6925361313 ps
T120 /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_intg_err.2103256265 Mar 07 12:54:31 PM PST 24 Mar 07 12:55:10 PM PST 24 2549917767 ps
T390 /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_errors.3020201035 Mar 07 12:54:03 PM PST 24 Mar 07 12:54:11 PM PST 24 830952860 ps
T391 /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_errors.4093856325 Mar 07 12:54:29 PM PST 24 Mar 07 12:54:44 PM PST 24 1230613609 ps
T95 /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_rw.1377826743 Mar 07 12:53:52 PM PST 24 Mar 07 12:54:08 PM PST 24 4145448173 ps
T392 /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_errors.496040446 Mar 07 12:54:11 PM PST 24 Mar 07 12:54:26 PM PST 24 1381807542 ps
T393 /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_rw.1184915767 Mar 07 12:54:07 PM PST 24 Mar 07 12:54:19 PM PST 24 15942152735 ps
T394 /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_errors.1147151218 Mar 07 12:54:33 PM PST 24 Mar 07 12:54:41 PM PST 24 606226683 ps
T395 /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_mem_rw_with_rand_reset.4132576009 Mar 07 12:54:15 PM PST 24 Mar 07 12:54:30 PM PST 24 1895361012 ps
T96 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_aliasing.564433747 Mar 07 12:54:19 PM PST 24 Mar 07 12:54:33 PM PST 24 16832137385 ps
T100 /workspace/coverage/cover_reg_top/11.rom_ctrl_passthru_mem_tl_intg_err.1167633461 Mar 07 12:53:58 PM PST 24 Mar 07 12:54:17 PM PST 24 1388093337 ps
T396 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_aliasing.2529736444 Mar 07 12:54:01 PM PST 24 Mar 07 12:54:12 PM PST 24 1841345108 ps
T397 /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_mem_rw_with_rand_reset.1432879229 Mar 07 12:54:23 PM PST 24 Mar 07 12:54:28 PM PST 24 415009682 ps
T97 /workspace/coverage/cover_reg_top/17.rom_ctrl_passthru_mem_tl_intg_err.1320118462 Mar 07 12:54:10 PM PST 24 Mar 07 12:54:29 PM PST 24 763772940 ps
T398 /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_partial_access.1463669366 Mar 07 12:54:13 PM PST 24 Mar 07 12:54:28 PM PST 24 19328192614 ps
T399 /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_mem_rw_with_rand_reset.2013518496 Mar 07 12:54:17 PM PST 24 Mar 07 12:54:28 PM PST 24 2432556620 ps
T400 /workspace/coverage/cover_reg_top/13.rom_ctrl_same_csr_outstanding.3042865425 Mar 07 12:54:05 PM PST 24 Mar 07 12:54:19 PM PST 24 6348711316 ps
T115 /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_intg_err.526328090 Mar 07 12:53:54 PM PST 24 Mar 07 12:55:09 PM PST 24 1302324852 ps
T111 /workspace/coverage/cover_reg_top/16.rom_ctrl_passthru_mem_tl_intg_err.2161215948 Mar 07 12:54:02 PM PST 24 Mar 07 12:55:36 PM PST 24 44472336602 ps
T121 /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_intg_err.502024685 Mar 07 12:53:59 PM PST 24 Mar 07 12:55:18 PM PST 24 1743865522 ps
T401 /workspace/coverage/cover_reg_top/12.rom_ctrl_same_csr_outstanding.588753901 Mar 07 12:54:07 PM PST 24 Mar 07 12:54:17 PM PST 24 876509017 ps
T402 /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_errors.65631179 Mar 07 12:54:32 PM PST 24 Mar 07 12:54:47 PM PST 24 3048582920 ps
T403 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_aliasing.3890508473 Mar 07 12:54:15 PM PST 24 Mar 07 12:54:27 PM PST 24 5131426450 ps
T404 /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_walk.1449720777 Mar 07 12:53:50 PM PST 24 Mar 07 12:54:00 PM PST 24 1798307927 ps
T405 /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_intg_err.2469561488 Mar 07 12:54:18 PM PST 24 Mar 07 12:55:03 PM PST 24 32446016520 ps
T406 /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_mem_rw_with_rand_reset.317246215 Mar 07 12:54:22 PM PST 24 Mar 07 12:54:38 PM PST 24 3894281855 ps
T407 /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_errors.3077090878 Mar 07 12:54:18 PM PST 24 Mar 07 12:54:32 PM PST 24 6250053702 ps
T408 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_bit_bash.1980455412 Mar 07 12:53:50 PM PST 24 Mar 07 12:54:00 PM PST 24 17111299464 ps
T409 /workspace/coverage/cover_reg_top/19.rom_ctrl_same_csr_outstanding.1615295271 Mar 07 12:54:23 PM PST 24 Mar 07 12:54:31 PM PST 24 2673005007 ps
T116 /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_intg_err.249078310 Mar 07 12:54:26 PM PST 24 Mar 07 12:55:35 PM PST 24 1891720630 ps
T117 /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_intg_err.588024059 Mar 07 12:54:01 PM PST 24 Mar 07 12:54:41 PM PST 24 2613908181 ps
T410 /workspace/coverage/cover_reg_top/18.rom_ctrl_passthru_mem_tl_intg_err.3320434710 Mar 07 12:54:25 PM PST 24 Mar 07 12:55:14 PM PST 24 4151174730 ps
T411 /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_mem_rw_with_rand_reset.25376578 Mar 07 12:54:02 PM PST 24 Mar 07 12:54:15 PM PST 24 1253637702 ps
T412 /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_walk.3498185305 Mar 07 12:54:22 PM PST 24 Mar 07 12:54:37 PM PST 24 1916459006 ps
T413 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_mem_rw_with_rand_reset.1733753778 Mar 07 12:54:01 PM PST 24 Mar 07 12:54:13 PM PST 24 1161558073 ps
T414 /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_errors.2599932593 Mar 07 12:54:33 PM PST 24 Mar 07 12:54:48 PM PST 24 23192376461 ps
T101 /workspace/coverage/cover_reg_top/9.rom_ctrl_passthru_mem_tl_intg_err.1520498373 Mar 07 12:54:18 PM PST 24 Mar 07 12:55:07 PM PST 24 12444873961 ps
T102 /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_rw.4087017932 Mar 07 12:53:59 PM PST 24 Mar 07 12:54:06 PM PST 24 2880971310 ps
T415 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_bit_bash.1900327560 Mar 07 12:54:00 PM PST 24 Mar 07 12:54:04 PM PST 24 348330882 ps
T416 /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_rw.3672837215 Mar 07 12:54:19 PM PST 24 Mar 07 12:54:28 PM PST 24 830491350 ps
T98 /workspace/coverage/cover_reg_top/15.rom_ctrl_passthru_mem_tl_intg_err.1167632558 Mar 07 12:54:00 PM PST 24 Mar 07 12:55:15 PM PST 24 7706406039 ps
T417 /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_rw.3134171497 Mar 07 12:54:08 PM PST 24 Mar 07 12:54:20 PM PST 24 1268918028 ps
T418 /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_partial_access.1666493734 Mar 07 12:54:15 PM PST 24 Mar 07 12:54:19 PM PST 24 348025307 ps
T419 /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_walk.4015660722 Mar 07 12:54:02 PM PST 24 Mar 07 12:54:13 PM PST 24 4452578900 ps
T420 /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_partial_access.3711119742 Mar 07 12:54:12 PM PST 24 Mar 07 12:54:27 PM PST 24 2228309977 ps
T421 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_hw_reset.2379257411 Mar 07 12:54:27 PM PST 24 Mar 07 12:54:44 PM PST 24 1400371356 ps
T422 /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_walk.671224117 Mar 07 12:54:01 PM PST 24 Mar 07 12:54:13 PM PST 24 2383384825 ps
T113 /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_intg_err.1449628295 Mar 07 12:53:59 PM PST 24 Mar 07 12:54:37 PM PST 24 386628969 ps
T423 /workspace/coverage/cover_reg_top/6.rom_ctrl_passthru_mem_tl_intg_err.3199548960 Mar 07 12:54:18 PM PST 24 Mar 07 12:55:02 PM PST 24 2613043629 ps
T424 /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_mem_rw_with_rand_reset.1558619042 Mar 07 12:54:32 PM PST 24 Mar 07 12:54:38 PM PST 24 1684570217 ps
T425 /workspace/coverage/cover_reg_top/0.rom_ctrl_same_csr_outstanding.2185282691 Mar 07 12:54:11 PM PST 24 Mar 07 12:54:26 PM PST 24 1655570543 ps
T122 /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_intg_err.3140423747 Mar 07 12:54:03 PM PST 24 Mar 07 12:55:21 PM PST 24 7056134331 ps
T426 /workspace/coverage/cover_reg_top/5.rom_ctrl_same_csr_outstanding.3901689222 Mar 07 12:54:10 PM PST 24 Mar 07 12:54:14 PM PST 24 416965701 ps
T427 /workspace/coverage/cover_reg_top/12.rom_ctrl_passthru_mem_tl_intg_err.2349032273 Mar 07 12:54:14 PM PST 24 Mar 07 12:54:55 PM PST 24 15189850378 ps
T428 /workspace/coverage/cover_reg_top/14.rom_ctrl_same_csr_outstanding.521507714 Mar 07 12:54:07 PM PST 24 Mar 07 12:54:11 PM PST 24 689532861 ps
T429 /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_errors.765388452 Mar 07 12:54:04 PM PST 24 Mar 07 12:54:16 PM PST 24 717383917 ps
T430 /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_rw.3409523992 Mar 07 12:54:15 PM PST 24 Mar 07 12:54:28 PM PST 24 5536525211 ps
T431 /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_rw.665714107 Mar 07 12:54:02 PM PST 24 Mar 07 12:54:07 PM PST 24 1655818928 ps
T99 /workspace/coverage/cover_reg_top/2.rom_ctrl_passthru_mem_tl_intg_err.3702608316 Mar 07 12:54:14 PM PST 24 Mar 07 12:54:42 PM PST 24 1082833294 ps
T432 /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_errors.1776070622 Mar 07 12:53:50 PM PST 24 Mar 07 12:54:05 PM PST 24 5478978923 ps
T433 /workspace/coverage/cover_reg_top/15.rom_ctrl_same_csr_outstanding.1409625461 Mar 07 12:54:22 PM PST 24 Mar 07 12:54:32 PM PST 24 534623119 ps
T118 /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_intg_err.1092543675 Mar 07 12:54:18 PM PST 24 Mar 07 12:55:00 PM PST 24 1109394559 ps
T434 /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_errors.1100977534 Mar 07 12:54:09 PM PST 24 Mar 07 12:54:22 PM PST 24 4506895340 ps
T435 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_rw.485085541 Mar 07 12:54:02 PM PST 24 Mar 07 12:54:17 PM PST 24 6895355003 ps
T436 /workspace/coverage/cover_reg_top/3.rom_ctrl_same_csr_outstanding.986773022 Mar 07 12:54:18 PM PST 24 Mar 07 12:54:30 PM PST 24 6911124179 ps
T437 /workspace/coverage/cover_reg_top/6.rom_ctrl_same_csr_outstanding.360230557 Mar 07 12:54:13 PM PST 24 Mar 07 12:54:25 PM PST 24 1308685346 ps
T114 /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_intg_err.1320848082 Mar 07 12:54:09 PM PST 24 Mar 07 12:55:24 PM PST 24 7712670463 ps
T438 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_mem_rw_with_rand_reset.421296712 Mar 07 12:54:02 PM PST 24 Mar 07 12:54:20 PM PST 24 11254185784 ps
T439 /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_errors.3589115688 Mar 07 12:54:17 PM PST 24 Mar 07 12:54:30 PM PST 24 2731364367 ps
T440 /workspace/coverage/cover_reg_top/1.rom_ctrl_same_csr_outstanding.2260311125 Mar 07 12:54:12 PM PST 24 Mar 07 12:54:25 PM PST 24 1316682651 ps
T441 /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_errors.4142878758 Mar 07 12:54:03 PM PST 24 Mar 07 12:54:21 PM PST 24 1523013575 ps
T442 /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_rw.4095825247 Mar 07 12:54:16 PM PST 24 Mar 07 12:54:23 PM PST 24 2827525594 ps
T443 /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_rw.3966213864 Mar 07 12:54:12 PM PST 24 Mar 07 12:54:24 PM PST 24 8247559040 ps
T444 /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_mem_rw_with_rand_reset.3072739428 Mar 07 12:54:25 PM PST 24 Mar 07 12:54:37 PM PST 24 1791653933 ps
T445 /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_errors.3933845687 Mar 07 12:54:02 PM PST 24 Mar 07 12:54:12 PM PST 24 150427966 ps
T103 /workspace/coverage/cover_reg_top/13.rom_ctrl_passthru_mem_tl_intg_err.657009202 Mar 07 12:54:10 PM PST 24 Mar 07 12:54:59 PM PST 24 5379852745 ps
T446 /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_mem_rw_with_rand_reset.551847028 Mar 07 12:54:23 PM PST 24 Mar 07 12:54:39 PM PST 24 7509210199 ps
T447 /workspace/coverage/cover_reg_top/11.rom_ctrl_same_csr_outstanding.1821008253 Mar 07 12:54:01 PM PST 24 Mar 07 12:54:13 PM PST 24 4267159144 ps
T448 /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_errors.1790070550 Mar 07 12:54:07 PM PST 24 Mar 07 12:54:27 PM PST 24 19249122775 ps
T449 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_aliasing.292195657 Mar 07 12:54:12 PM PST 24 Mar 07 12:54:19 PM PST 24 2043821287 ps
T450 /workspace/coverage/cover_reg_top/16.rom_ctrl_same_csr_outstanding.1020317938 Mar 07 12:54:05 PM PST 24 Mar 07 12:54:23 PM PST 24 26393088473 ps
T123 /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_intg_err.1925282603 Mar 07 12:53:57 PM PST 24 Mar 07 12:55:10 PM PST 24 2673538878 ps
T451 /workspace/coverage/cover_reg_top/10.rom_ctrl_same_csr_outstanding.3958002903 Mar 07 12:53:54 PM PST 24 Mar 07 12:54:10 PM PST 24 15086201178 ps
T452 /workspace/coverage/cover_reg_top/19.rom_ctrl_passthru_mem_tl_intg_err.1242673666 Mar 07 12:54:25 PM PST 24 Mar 07 12:55:29 PM PST 24 44425078396 ps
T453 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_bit_bash.893760631 Mar 07 12:54:12 PM PST 24 Mar 07 12:54:28 PM PST 24 1700719917 ps
T454 /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_rw.2292512433 Mar 07 12:54:00 PM PST 24 Mar 07 12:54:11 PM PST 24 3485296831 ps
T455 /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_intg_err.3535564876 Mar 07 12:54:30 PM PST 24 Mar 07 12:55:47 PM PST 24 3036571242 ps
T456 /workspace/coverage/cover_reg_top/0.rom_ctrl_passthru_mem_tl_intg_err.1776888355 Mar 07 12:54:01 PM PST 24 Mar 07 12:54:28 PM PST 24 1386519785 ps
T457 /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_intg_err.2608742154 Mar 07 12:54:16 PM PST 24 Mar 07 12:55:01 PM PST 24 1904425042 ps
T119 /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_intg_err.2067310059 Mar 07 12:54:03 PM PST 24 Mar 07 12:55:21 PM PST 24 2137673333 ps
T458 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_mem_rw_with_rand_reset.364057190 Mar 07 12:54:12 PM PST 24 Mar 07 12:54:23 PM PST 24 7666162713 ps
T459 /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_partial_access.3538051283 Mar 07 12:54:07 PM PST 24 Mar 07 12:54:17 PM PST 24 2664045847 ps
T460 /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_errors.1335803988 Mar 07 12:53:58 PM PST 24 Mar 07 12:54:13 PM PST 24 5664209052 ps
T461 /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_errors.888793802 Mar 07 12:54:00 PM PST 24 Mar 07 12:54:17 PM PST 24 5934764126 ps
T125 /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_intg_err.2241226060 Mar 07 12:54:00 PM PST 24 Mar 07 12:55:14 PM PST 24 3619762564 ps
T462 /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_errors.2993695173 Mar 07 12:54:20 PM PST 24 Mar 07 12:54:28 PM PST 24 85646803 ps
T463 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_rw.3187748532 Mar 07 12:54:19 PM PST 24 Mar 07 12:54:23 PM PST 24 85614088 ps

Test location /workspace/coverage/default/7.rom_ctrl_corrupt_sig_fatal_chk.2142337404
Short name T2
Test name
Test status
Simulation time 21053403245 ps
CPU time 274.7 seconds
Started Mar 07 12:55:14 PM PST 24
Finished Mar 07 12:59:49 PM PST 24
Peak memory 233752 kb
Host smart-61477061-d0d2-475a-9fa9-7e7a74e31fbf
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2142337404 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_c
orrupt_sig_fatal_chk.2142337404
Directory /workspace/7.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/39.rom_ctrl_stress_all_with_rand_reset.1197639201
Short name T15
Test name
Test status
Simulation time 21851548052 ps
CPU time 2980.81 seconds
Started Mar 07 12:55:45 PM PST 24
Finished Mar 07 01:45:37 PM PST 24
Peak memory 234012 kb
Host smart-015c52c4-cd31-4195-97f0-64fd7468b397
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1197639201 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_stress_all_with_rand_reset.1197639201
Directory /workspace/39.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.rom_ctrl_smoke.540287804
Short name T11
Test name
Test status
Simulation time 3040534462 ps
CPU time 34.72 seconds
Started Mar 07 12:55:36 PM PST 24
Finished Mar 07 12:56:12 PM PST 24
Peak memory 213528 kb
Host smart-aa506c2e-95c6-4056-a630-62771553246a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=540287804 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_smoke.540287804
Directory /workspace/46.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/36.rom_ctrl_max_throughput_chk.51582476
Short name T43
Test name
Test status
Simulation time 2432226195 ps
CPU time 12.58 seconds
Started Mar 07 12:55:46 PM PST 24
Finished Mar 07 12:55:59 PM PST 24
Peak memory 210808 kb
Host smart-1b518061-92a1-409d-854f-44a91e20a1d3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=51582476 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_max_throughput_chk.51582476
Directory /workspace/36.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/23.rom_ctrl_alert_test.4095089876
Short name T1
Test name
Test status
Simulation time 88297866 ps
CPU time 4.35 seconds
Started Mar 07 12:55:40 PM PST 24
Finished Mar 07 12:55:47 PM PST 24
Peak memory 210828 kb
Host smart-df074246-d519-41e0-91c0-3d2f0406b8eb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4095089876 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_alert_test.4095089876
Directory /workspace/23.rom_ctrl_alert_test/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_intg_err.811711505
Short name T67
Test name
Test status
Simulation time 17186995036 ps
CPU time 80.03 seconds
Started Mar 07 12:53:56 PM PST 24
Finished Mar 07 12:55:17 PM PST 24
Peak memory 212884 kb
Host smart-ecd5532c-17de-468f-b3d8-2378ba5cba14
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=811711505 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_tl_int
g_err.811711505
Directory /workspace/6.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/24.rom_ctrl_corrupt_sig_fatal_chk.1455080811
Short name T30
Test name
Test status
Simulation time 32048246500 ps
CPU time 230.6 seconds
Started Mar 07 12:55:25 PM PST 24
Finished Mar 07 12:59:15 PM PST 24
Peak memory 224600 kb
Host smart-3d311641-28e0-4aeb-9db8-97910bb7b1c9
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1455080811 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_
corrupt_sig_fatal_chk.1455080811
Directory /workspace/24.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/43.rom_ctrl_corrupt_sig_fatal_chk.1824651447
Short name T14
Test name
Test status
Simulation time 101905504689 ps
CPU time 347.15 seconds
Started Mar 07 12:56:06 PM PST 24
Finished Mar 07 01:01:53 PM PST 24
Peak memory 224616 kb
Host smart-8fccf207-2f14-47bc-9ba2-b6df6dd5e1f4
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1824651447 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_
corrupt_sig_fatal_chk.1824651447
Directory /workspace/43.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/34.rom_ctrl_stress_all.3041788876
Short name T22
Test name
Test status
Simulation time 10457437131 ps
CPU time 66.88 seconds
Started Mar 07 12:55:39 PM PST 24
Finished Mar 07 12:56:46 PM PST 24
Peak memory 219064 kb
Host smart-9777bb93-c6e7-464d-a4f5-d5f62cd990c9
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3041788876 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 34.rom_ctrl_stress_all.3041788876
Directory /workspace/34.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/0.rom_ctrl_sec_cm.895600876
Short name T36
Test name
Test status
Simulation time 6386302035 ps
CPU time 109.28 seconds
Started Mar 07 12:55:15 PM PST 24
Finished Mar 07 12:57:06 PM PST 24
Peak memory 234636 kb
Host smart-288b7d36-4d48-4623-ae6a-ec583c21579f
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=895600876 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_sec_cm.895600876
Directory /workspace/0.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_passthru_mem_tl_intg_err.2121540801
Short name T80
Test name
Test status
Simulation time 1135937492 ps
CPU time 28.08 seconds
Started Mar 07 12:54:17 PM PST 24
Finished Mar 07 12:54:46 PM PST 24
Peak memory 210808 kb
Host smart-b91b57ea-6198-4a3c-a758-e8c69e1c644d
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2121540801 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_pa
ssthru_mem_tl_intg_err.2121540801
Directory /workspace/4.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_intg_err.2067310059
Short name T119
Test name
Test status
Simulation time 2137673333 ps
CPU time 77.91 seconds
Started Mar 07 12:54:03 PM PST 24
Finished Mar 07 12:55:21 PM PST 24
Peak memory 212504 kb
Host smart-6070e5ce-2cb6-4eb6-97e4-7c0bde3568e7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2067310059 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_tl_in
tg_err.2067310059
Directory /workspace/3.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/44.rom_ctrl_max_throughput_chk.3478890438
Short name T147
Test name
Test status
Simulation time 7094134515 ps
CPU time 17.2 seconds
Started Mar 07 12:55:34 PM PST 24
Finished Mar 07 12:55:54 PM PST 24
Peak memory 210812 kb
Host smart-950b0613-8bde-4e3a-bd40-452079ab54a4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3478890438 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_max_throughput_chk.3478890438
Directory /workspace/44.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/15.rom_ctrl_stress_all_with_rand_reset.1038603924
Short name T16
Test name
Test status
Simulation time 57417715166 ps
CPU time 2218.72 seconds
Started Mar 07 12:55:39 PM PST 24
Finished Mar 07 01:32:38 PM PST 24
Peak memory 243684 kb
Host smart-bc9060f5-e946-477e-8130-7c6a1ecdc173
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1038603924 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_stress_all_with_rand_reset.1038603924
Directory /workspace/15.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.rom_ctrl_kmac_err_chk.2629350292
Short name T73
Test name
Test status
Simulation time 4647832826 ps
CPU time 23.12 seconds
Started Mar 07 12:55:33 PM PST 24
Finished Mar 07 12:55:58 PM PST 24
Peak memory 211676 kb
Host smart-e3ab3a67-3e6e-4ee2-ab0e-36cbca0ab888
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2629350292 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_kmac_err_chk.2629350292
Directory /workspace/20.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/1.rom_ctrl_kmac_err_chk.218042717
Short name T271
Test name
Test status
Simulation time 1191948297 ps
CPU time 9.25 seconds
Started Mar 07 12:55:09 PM PST 24
Finished Mar 07 12:55:19 PM PST 24
Peak memory 211372 kb
Host smart-1ee32f15-9b4a-4e82-8340-9d6cf0b00321
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=218042717 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_kmac_err_chk.218042717
Directory /workspace/1.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/32.rom_ctrl_kmac_err_chk.691383379
Short name T9
Test name
Test status
Simulation time 2279781913 ps
CPU time 16.77 seconds
Started Mar 07 12:55:37 PM PST 24
Finished Mar 07 12:55:54 PM PST 24
Peak memory 211396 kb
Host smart-81269c15-043b-4994-93b9-02eee1b7b3ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=691383379 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_kmac_err_chk.691383379
Directory /workspace/32.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_intg_err.2241226060
Short name T125
Test name
Test status
Simulation time 3619762564 ps
CPU time 73.15 seconds
Started Mar 07 12:54:00 PM PST 24
Finished Mar 07 12:55:14 PM PST 24
Peak memory 210928 kb
Host smart-0e6edeeb-d955-4933-b125-66f7596ce284
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2241226060 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_tl_i
ntg_err.2241226060
Directory /workspace/14.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_passthru_mem_tl_intg_err.2406904343
Short name T83
Test name
Test status
Simulation time 2347113041 ps
CPU time 27.62 seconds
Started Mar 07 12:54:09 PM PST 24
Finished Mar 07 12:54:37 PM PST 24
Peak memory 211008 kb
Host smart-2e5dcd2c-3429-45e8-8456-84ecaac2765d
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2406904343 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_p
assthru_mem_tl_intg_err.2406904343
Directory /workspace/10.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/default/14.rom_ctrl_corrupt_sig_fatal_chk.3926482213
Short name T59
Test name
Test status
Simulation time 37122508808 ps
CPU time 196.56 seconds
Started Mar 07 12:55:13 PM PST 24
Finished Mar 07 12:58:30 PM PST 24
Peak memory 236380 kb
Host smart-91bd5381-756b-4a32-8ad2-ccb14b6f1dc0
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3926482213 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_
corrupt_sig_fatal_chk.3926482213
Directory /workspace/14.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_aliasing.564433747
Short name T96
Test name
Test status
Simulation time 16832137385 ps
CPU time 14.22 seconds
Started Mar 07 12:54:19 PM PST 24
Finished Mar 07 12:54:33 PM PST 24
Peak memory 210812 kb
Host smart-6defefff-fdf2-423c-870b-2470e9d53fd4
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=564433747 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_alias
ing.564433747
Directory /workspace/0.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_bit_bash.1980455412
Short name T408
Test name
Test status
Simulation time 17111299464 ps
CPU time 10.42 seconds
Started Mar 07 12:53:50 PM PST 24
Finished Mar 07 12:54:00 PM PST 24
Peak memory 210896 kb
Host smart-6160b2ae-c3dc-464e-9315-cd9ed857b83d
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1980455412 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_bit_
bash.1980455412
Directory /workspace/0.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_hw_reset.2379257411
Short name T421
Test name
Test status
Simulation time 1400371356 ps
CPU time 16.15 seconds
Started Mar 07 12:54:27 PM PST 24
Finished Mar 07 12:54:44 PM PST 24
Peak memory 210712 kb
Host smart-cc105731-bbae-451c-9004-c1de41227e7c
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2379257411 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_hw_r
eset.2379257411
Directory /workspace/0.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_mem_rw_with_rand_reset.307651548
Short name T374
Test name
Test status
Simulation time 4141469428 ps
CPU time 16.59 seconds
Started Mar 07 12:53:47 PM PST 24
Finished Mar 07 12:54:05 PM PST 24
Peak memory 216088 kb
Host smart-30c70eb9-4096-4e24-9e04-99abf39924d1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=307651548 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 0.rom_ctrl_csr_mem_rw_with_rand_reset.307651548
Directory /workspace/0.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_rw.4021607887
Short name T373
Test name
Test status
Simulation time 1791291688 ps
CPU time 13 seconds
Started Mar 07 12:53:55 PM PST 24
Finished Mar 07 12:54:08 PM PST 24
Peak memory 210684 kb
Host smart-31771653-bca6-4f80-9c96-9cd9e741c7b5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4021607887 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_rw.4021607887
Directory /workspace/0.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_partial_access.1463669366
Short name T398
Test name
Test status
Simulation time 19328192614 ps
CPU time 13.47 seconds
Started Mar 07 12:54:13 PM PST 24
Finished Mar 07 12:54:28 PM PST 24
Peak memory 210756 kb
Host smart-815b8a21-c96e-48d7-ad4f-caea2e5cbc08
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1463669366 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctr
l_mem_partial_access.1463669366
Directory /workspace/0.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_walk.3498185305
Short name T412
Test name
Test status
Simulation time 1916459006 ps
CPU time 15 seconds
Started Mar 07 12:54:22 PM PST 24
Finished Mar 07 12:54:37 PM PST 24
Peak memory 210676 kb
Host smart-f6673caa-86fd-46b7-9aa1-88af664ce22c
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3498185305 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_mem_walk
.3498185305
Directory /workspace/0.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_passthru_mem_tl_intg_err.1776888355
Short name T456
Test name
Test status
Simulation time 1386519785 ps
CPU time 26.79 seconds
Started Mar 07 12:54:01 PM PST 24
Finished Mar 07 12:54:28 PM PST 24
Peak memory 210868 kb
Host smart-36fe4e25-e372-4475-9a17-fdc64efd98ed
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1776888355 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_pa
ssthru_mem_tl_intg_err.1776888355
Directory /workspace/0.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_same_csr_outstanding.2185282691
Short name T425
Test name
Test status
Simulation time 1655570543 ps
CPU time 14.6 seconds
Started Mar 07 12:54:11 PM PST 24
Finished Mar 07 12:54:26 PM PST 24
Peak memory 210776 kb
Host smart-8a5a9b13-c068-4794-98a9-90652c4ec394
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2185282691 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_c
trl_same_csr_outstanding.2185282691
Directory /workspace/0.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_errors.3933845687
Short name T445
Test name
Test status
Simulation time 150427966 ps
CPU time 9.88 seconds
Started Mar 07 12:54:02 PM PST 24
Finished Mar 07 12:54:12 PM PST 24
Peak memory 214832 kb
Host smart-dd7b9303-f9f3-4990-aac1-a0bae476187e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3933845687 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_tl_errors.3933845687
Directory /workspace/0.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_intg_err.1925282603
Short name T123
Test name
Test status
Simulation time 2673538878 ps
CPU time 72.24 seconds
Started Mar 07 12:53:57 PM PST 24
Finished Mar 07 12:55:10 PM PST 24
Peak memory 211752 kb
Host smart-35024ffc-008a-44c0-a7a6-26e4d014ae3d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1925282603 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_tl_in
tg_err.1925282603
Directory /workspace/0.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_aliasing.3890508473
Short name T403
Test name
Test status
Simulation time 5131426450 ps
CPU time 11.21 seconds
Started Mar 07 12:54:15 PM PST 24
Finished Mar 07 12:54:27 PM PST 24
Peak memory 210752 kb
Host smart-f307f6f4-871f-4051-b1b7-83c489160273
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3890508473 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_alia
sing.3890508473
Directory /workspace/1.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_bit_bash.3120878345
Short name T382
Test name
Test status
Simulation time 3235259816 ps
CPU time 13.57 seconds
Started Mar 07 12:54:14 PM PST 24
Finished Mar 07 12:54:28 PM PST 24
Peak memory 210868 kb
Host smart-a04c0776-d2e1-4e8d-8901-f7f7db6cb393
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3120878345 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_bit_
bash.3120878345
Directory /workspace/1.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_hw_reset.2540090249
Short name T369
Test name
Test status
Simulation time 1315631351 ps
CPU time 14.86 seconds
Started Mar 07 12:54:00 PM PST 24
Finished Mar 07 12:54:17 PM PST 24
Peak memory 210744 kb
Host smart-1888281f-bbb3-486e-95da-e363a5010721
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2540090249 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_hw_r
eset.2540090249
Directory /workspace/1.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_mem_rw_with_rand_reset.421296712
Short name T438
Test name
Test status
Simulation time 11254185784 ps
CPU time 17.14 seconds
Started Mar 07 12:54:02 PM PST 24
Finished Mar 07 12:54:20 PM PST 24
Peak memory 215048 kb
Host smart-dd0c3530-959e-4406-9e19-bdb98a2d3ba8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=421296712 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 1.rom_ctrl_csr_mem_rw_with_rand_reset.421296712
Directory /workspace/1.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_rw.485085541
Short name T435
Test name
Test status
Simulation time 6895355003 ps
CPU time 14.35 seconds
Started Mar 07 12:54:02 PM PST 24
Finished Mar 07 12:54:17 PM PST 24
Peak memory 210720 kb
Host smart-e8d0a86a-e90b-4271-b414-169bca1f6a29
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=485085541 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_rw.485085541
Directory /workspace/1.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_partial_access.1666493734
Short name T418
Test name
Test status
Simulation time 348025307 ps
CPU time 4.07 seconds
Started Mar 07 12:54:15 PM PST 24
Finished Mar 07 12:54:19 PM PST 24
Peak memory 210712 kb
Host smart-b20f18b9-07b4-4943-aeb3-425b829b71ad
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1666493734 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctr
l_mem_partial_access.1666493734
Directory /workspace/1.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_walk.1449720777
Short name T404
Test name
Test status
Simulation time 1798307927 ps
CPU time 9.84 seconds
Started Mar 07 12:53:50 PM PST 24
Finished Mar 07 12:54:00 PM PST 24
Peak memory 210652 kb
Host smart-cc7084da-44e4-403c-8470-ba0b3739813a
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1449720777 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_mem_walk
.1449720777
Directory /workspace/1.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_passthru_mem_tl_intg_err.736497615
Short name T104
Test name
Test status
Simulation time 12868655042 ps
CPU time 65.03 seconds
Started Mar 07 12:53:59 PM PST 24
Finished Mar 07 12:55:04 PM PST 24
Peak memory 210936 kb
Host smart-7f01c663-d196-4e61-90ad-316f3d295397
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=736497615 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_pas
sthru_mem_tl_intg_err.736497615
Directory /workspace/1.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_same_csr_outstanding.2260311125
Short name T440
Test name
Test status
Simulation time 1316682651 ps
CPU time 12.29 seconds
Started Mar 07 12:54:12 PM PST 24
Finished Mar 07 12:54:25 PM PST 24
Peak memory 210756 kb
Host smart-d35af45a-8a42-427a-bb5d-6bde0ab83d74
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2260311125 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_c
trl_same_csr_outstanding.2260311125
Directory /workspace/1.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_errors.888793802
Short name T461
Test name
Test status
Simulation time 5934764126 ps
CPU time 16.26 seconds
Started Mar 07 12:54:00 PM PST 24
Finished Mar 07 12:54:17 PM PST 24
Peak memory 215164 kb
Host smart-1a5e07f8-532e-4337-8269-a8c0d9c92712
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=888793802 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_tl_errors.888793802
Directory /workspace/1.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_intg_err.1320848082
Short name T114
Test name
Test status
Simulation time 7712670463 ps
CPU time 75.38 seconds
Started Mar 07 12:54:09 PM PST 24
Finished Mar 07 12:55:24 PM PST 24
Peak memory 211936 kb
Host smart-510fe338-242c-440e-b4d3-1d11c7fd578b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1320848082 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_tl_in
tg_err.1320848082
Directory /workspace/1.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_mem_rw_with_rand_reset.3790143074
Short name T386
Test name
Test status
Simulation time 4035037480 ps
CPU time 11.08 seconds
Started Mar 07 12:54:02 PM PST 24
Finished Mar 07 12:54:14 PM PST 24
Peak memory 215512 kb
Host smart-b1b4e7ea-a20c-483b-857a-3d7aa1df7ea9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3790143074 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 10.rom_ctrl_csr_mem_rw_with_rand_reset.3790143074
Directory /workspace/10.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_rw.3134171497
Short name T417
Test name
Test status
Simulation time 1268918028 ps
CPU time 11.54 seconds
Started Mar 07 12:54:08 PM PST 24
Finished Mar 07 12:54:20 PM PST 24
Peak memory 210744 kb
Host smart-f9c7d831-8dd8-411f-8357-929830084268
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3134171497 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_csr_rw.3134171497
Directory /workspace/10.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_same_csr_outstanding.3958002903
Short name T451
Test name
Test status
Simulation time 15086201178 ps
CPU time 16.21 seconds
Started Mar 07 12:53:54 PM PST 24
Finished Mar 07 12:54:10 PM PST 24
Peak memory 210908 kb
Host smart-649d3173-38fb-406e-a28c-9cedbac9067e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3958002903 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_
ctrl_same_csr_outstanding.3958002903
Directory /workspace/10.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_errors.496040446
Short name T392
Test name
Test status
Simulation time 1381807542 ps
CPU time 14.89 seconds
Started Mar 07 12:54:11 PM PST 24
Finished Mar 07 12:54:26 PM PST 24
Peak memory 214976 kb
Host smart-1e333286-6bea-4d9d-92bf-18e048add6e1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=496040446 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_tl_errors.496040446
Directory /workspace/10.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_intg_err.3535564876
Short name T455
Test name
Test status
Simulation time 3036571242 ps
CPU time 76.72 seconds
Started Mar 07 12:54:30 PM PST 24
Finished Mar 07 12:55:47 PM PST 24
Peak memory 211632 kb
Host smart-03cbd531-45d1-4ca2-8764-ec71dc9723f3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3535564876 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_tl_i
ntg_err.3535564876
Directory /workspace/10.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_mem_rw_with_rand_reset.3732472122
Short name T371
Test name
Test status
Simulation time 4084849423 ps
CPU time 10.39 seconds
Started Mar 07 12:54:16 PM PST 24
Finished Mar 07 12:54:27 PM PST 24
Peak memory 212444 kb
Host smart-2b3acf21-960d-4359-a1f4-0657add2e252
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3732472122 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 11.rom_ctrl_csr_mem_rw_with_rand_reset.3732472122
Directory /workspace/11.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_rw.615280463
Short name T389
Test name
Test status
Simulation time 7729006467 ps
CPU time 15.22 seconds
Started Mar 07 12:54:11 PM PST 24
Finished Mar 07 12:54:26 PM PST 24
Peak memory 210868 kb
Host smart-eb4a6d04-50fc-4487-988f-e60d1abe15e8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=615280463 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_csr_rw.615280463
Directory /workspace/11.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_passthru_mem_tl_intg_err.1167633461
Short name T100
Test name
Test status
Simulation time 1388093337 ps
CPU time 18.7 seconds
Started Mar 07 12:53:58 PM PST 24
Finished Mar 07 12:54:17 PM PST 24
Peak memory 210796 kb
Host smart-99a2c31e-400c-4bb6-b14d-d0c004ad7208
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1167633461 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_p
assthru_mem_tl_intg_err.1167633461
Directory /workspace/11.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_same_csr_outstanding.1821008253
Short name T447
Test name
Test status
Simulation time 4267159144 ps
CPU time 11.52 seconds
Started Mar 07 12:54:01 PM PST 24
Finished Mar 07 12:54:13 PM PST 24
Peak memory 210924 kb
Host smart-01743404-ae6c-439b-a13c-61b0911ead1d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1821008253 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_
ctrl_same_csr_outstanding.1821008253
Directory /workspace/11.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_errors.2599932593
Short name T414
Test name
Test status
Simulation time 23192376461 ps
CPU time 14.73 seconds
Started Mar 07 12:54:33 PM PST 24
Finished Mar 07 12:54:48 PM PST 24
Peak memory 216496 kb
Host smart-8c0b8548-521f-4500-86dc-e75317e0330a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2599932593 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_tl_errors.2599932593
Directory /workspace/11.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_intg_err.1449628295
Short name T113
Test name
Test status
Simulation time 386628969 ps
CPU time 37.67 seconds
Started Mar 07 12:53:59 PM PST 24
Finished Mar 07 12:54:37 PM PST 24
Peak memory 210804 kb
Host smart-5bd0bad5-3296-43b7-89e8-963544053b2d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1449628295 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_tl_i
ntg_err.1449628295
Directory /workspace/11.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_mem_rw_with_rand_reset.3072739428
Short name T444
Test name
Test status
Simulation time 1791653933 ps
CPU time 12.38 seconds
Started Mar 07 12:54:25 PM PST 24
Finished Mar 07 12:54:37 PM PST 24
Peak memory 212884 kb
Host smart-dccbae80-49ec-4c1b-ba03-4a9656176eb2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3072739428 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 12.rom_ctrl_csr_mem_rw_with_rand_reset.3072739428
Directory /workspace/12.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_rw.2292512433
Short name T454
Test name
Test status
Simulation time 3485296831 ps
CPU time 9.84 seconds
Started Mar 07 12:54:00 PM PST 24
Finished Mar 07 12:54:11 PM PST 24
Peak memory 210872 kb
Host smart-ef2166fb-8f54-4ac3-81c7-5c9cad76cdba
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2292512433 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_csr_rw.2292512433
Directory /workspace/12.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_passthru_mem_tl_intg_err.2349032273
Short name T427
Test name
Test status
Simulation time 15189850378 ps
CPU time 40.12 seconds
Started Mar 07 12:54:14 PM PST 24
Finished Mar 07 12:54:55 PM PST 24
Peak memory 210924 kb
Host smart-ef3d73b9-9408-4318-adbe-3b4ab95edc60
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2349032273 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_p
assthru_mem_tl_intg_err.2349032273
Directory /workspace/12.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_same_csr_outstanding.588753901
Short name T401
Test name
Test status
Simulation time 876509017 ps
CPU time 10.16 seconds
Started Mar 07 12:54:07 PM PST 24
Finished Mar 07 12:54:17 PM PST 24
Peak memory 210804 kb
Host smart-fec6e963-6fde-4bdf-adc7-1a7deba9f21c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=588753901 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_c
trl_same_csr_outstanding.588753901
Directory /workspace/12.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_errors.4093856325
Short name T391
Test name
Test status
Simulation time 1230613609 ps
CPU time 14.93 seconds
Started Mar 07 12:54:29 PM PST 24
Finished Mar 07 12:54:44 PM PST 24
Peak memory 215128 kb
Host smart-6fc6a86a-15aa-4523-98ac-14fab48cd760
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4093856325 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_tl_errors.4093856325
Directory /workspace/12.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_intg_err.2103256265
Short name T120
Test name
Test status
Simulation time 2549917767 ps
CPU time 39.31 seconds
Started Mar 07 12:54:31 PM PST 24
Finished Mar 07 12:55:10 PM PST 24
Peak memory 210936 kb
Host smart-7a31219f-73a3-48ee-b314-82ee664fb856
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2103256265 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_tl_i
ntg_err.2103256265
Directory /workspace/12.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_mem_rw_with_rand_reset.4090020969
Short name T365
Test name
Test status
Simulation time 5908822022 ps
CPU time 13.36 seconds
Started Mar 07 12:54:00 PM PST 24
Finished Mar 07 12:54:13 PM PST 24
Peak memory 213588 kb
Host smart-3daac867-fa4f-4bf2-aace-01a24dd409d4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4090020969 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 13.rom_ctrl_csr_mem_rw_with_rand_reset.4090020969
Directory /workspace/13.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_rw.1377826743
Short name T95
Test name
Test status
Simulation time 4145448173 ps
CPU time 15.8 seconds
Started Mar 07 12:53:52 PM PST 24
Finished Mar 07 12:54:08 PM PST 24
Peak memory 210812 kb
Host smart-0b709d92-2e63-448a-a30a-bf0fc6f3ed2d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1377826743 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_csr_rw.1377826743
Directory /workspace/13.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_passthru_mem_tl_intg_err.657009202
Short name T103
Test name
Test status
Simulation time 5379852745 ps
CPU time 49.22 seconds
Started Mar 07 12:54:10 PM PST 24
Finished Mar 07 12:54:59 PM PST 24
Peak memory 211000 kb
Host smart-f3f7dccb-19de-45c7-b1d0-bae1ac1e994a
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=657009202 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_pa
ssthru_mem_tl_intg_err.657009202
Directory /workspace/13.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_same_csr_outstanding.3042865425
Short name T400
Test name
Test status
Simulation time 6348711316 ps
CPU time 13.08 seconds
Started Mar 07 12:54:05 PM PST 24
Finished Mar 07 12:54:19 PM PST 24
Peak memory 210856 kb
Host smart-46740543-97c4-4769-a5b3-2331239129b4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3042865425 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_
ctrl_same_csr_outstanding.3042865425
Directory /workspace/13.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_errors.1147151218
Short name T394
Test name
Test status
Simulation time 606226683 ps
CPU time 8.18 seconds
Started Mar 07 12:54:33 PM PST 24
Finished Mar 07 12:54:41 PM PST 24
Peak memory 215040 kb
Host smart-2ea58d44-0ff3-4621-8e09-d1316759d792
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1147151218 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_tl_errors.1147151218
Directory /workspace/13.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_intg_err.526328090
Short name T115
Test name
Test status
Simulation time 1302324852 ps
CPU time 75.37 seconds
Started Mar 07 12:53:54 PM PST 24
Finished Mar 07 12:55:09 PM PST 24
Peak memory 212332 kb
Host smart-9608f48b-b94d-45ae-b8b2-32fd4c853d84
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=526328090 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_tl_in
tg_err.526328090
Directory /workspace/13.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_mem_rw_with_rand_reset.317246215
Short name T406
Test name
Test status
Simulation time 3894281855 ps
CPU time 15.45 seconds
Started Mar 07 12:54:22 PM PST 24
Finished Mar 07 12:54:38 PM PST 24
Peak memory 213700 kb
Host smart-4995f786-130e-46e0-ba4f-a319ee40425b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=317246215 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 14.rom_ctrl_csr_mem_rw_with_rand_reset.317246215
Directory /workspace/14.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_rw.665714107
Short name T431
Test name
Test status
Simulation time 1655818928 ps
CPU time 4.21 seconds
Started Mar 07 12:54:02 PM PST 24
Finished Mar 07 12:54:07 PM PST 24
Peak memory 210752 kb
Host smart-15e4231b-fb67-4d62-8ed8-1bf2ece86b64
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=665714107 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_csr_rw.665714107
Directory /workspace/14.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_passthru_mem_tl_intg_err.3562773259
Short name T372
Test name
Test status
Simulation time 7967805534 ps
CPU time 64.6 seconds
Started Mar 07 12:54:14 PM PST 24
Finished Mar 07 12:55:18 PM PST 24
Peak memory 211004 kb
Host smart-22a16726-6706-41e5-be14-1f698e505cad
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3562773259 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_p
assthru_mem_tl_intg_err.3562773259
Directory /workspace/14.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_same_csr_outstanding.521507714
Short name T428
Test name
Test status
Simulation time 689532861 ps
CPU time 4.18 seconds
Started Mar 07 12:54:07 PM PST 24
Finished Mar 07 12:54:11 PM PST 24
Peak memory 210632 kb
Host smart-110d4e37-201d-4d38-bdd0-b5d38709d0f2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=521507714 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_c
trl_same_csr_outstanding.521507714
Directory /workspace/14.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_errors.1859223017
Short name T383
Test name
Test status
Simulation time 10063250840 ps
CPU time 21.29 seconds
Started Mar 07 12:54:02 PM PST 24
Finished Mar 07 12:54:24 PM PST 24
Peak memory 215628 kb
Host smart-d6a75515-8adb-401f-81b4-41118c30a1a0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1859223017 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_tl_errors.1859223017
Directory /workspace/14.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_mem_rw_with_rand_reset.4132576009
Short name T395
Test name
Test status
Simulation time 1895361012 ps
CPU time 14.92 seconds
Started Mar 07 12:54:15 PM PST 24
Finished Mar 07 12:54:30 PM PST 24
Peak memory 214536 kb
Host smart-e9f29a3b-ccda-46ac-8665-4004a75a7817
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4132576009 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 15.rom_ctrl_csr_mem_rw_with_rand_reset.4132576009
Directory /workspace/15.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_rw.4087017932
Short name T102
Test name
Test status
Simulation time 2880971310 ps
CPU time 6.24 seconds
Started Mar 07 12:53:59 PM PST 24
Finished Mar 07 12:54:06 PM PST 24
Peak memory 210892 kb
Host smart-1c7df6ae-ba2b-49c6-b940-ee717ec3f145
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4087017932 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_csr_rw.4087017932
Directory /workspace/15.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_passthru_mem_tl_intg_err.1167632558
Short name T98
Test name
Test status
Simulation time 7706406039 ps
CPU time 73.61 seconds
Started Mar 07 12:54:00 PM PST 24
Finished Mar 07 12:55:15 PM PST 24
Peak memory 210768 kb
Host smart-03553ea6-97bd-4742-ac05-73ca550374fc
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1167632558 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_p
assthru_mem_tl_intg_err.1167632558
Directory /workspace/15.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_same_csr_outstanding.1409625461
Short name T433
Test name
Test status
Simulation time 534623119 ps
CPU time 9.14 seconds
Started Mar 07 12:54:22 PM PST 24
Finished Mar 07 12:54:32 PM PST 24
Peak memory 210692 kb
Host smart-216c7538-03e3-4bb8-b55b-c839de4f73a3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1409625461 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_
ctrl_same_csr_outstanding.1409625461
Directory /workspace/15.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_errors.2508976033
Short name T368
Test name
Test status
Simulation time 85623716 ps
CPU time 6.72 seconds
Started Mar 07 12:54:16 PM PST 24
Finished Mar 07 12:54:24 PM PST 24
Peak memory 214956 kb
Host smart-b2d74c2d-542b-4df6-b6bb-d4a969125756
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2508976033 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_tl_errors.2508976033
Directory /workspace/15.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_intg_err.249078310
Short name T116
Test name
Test status
Simulation time 1891720630 ps
CPU time 68.56 seconds
Started Mar 07 12:54:26 PM PST 24
Finished Mar 07 12:55:35 PM PST 24
Peak memory 210764 kb
Host smart-ec3fed48-56f3-4d2e-9511-4974ed85396f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=249078310 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_tl_in
tg_err.249078310
Directory /workspace/15.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_mem_rw_with_rand_reset.1432879229
Short name T397
Test name
Test status
Simulation time 415009682 ps
CPU time 5.14 seconds
Started Mar 07 12:54:23 PM PST 24
Finished Mar 07 12:54:28 PM PST 24
Peak memory 214780 kb
Host smart-9edf4ee7-bca3-41a7-9901-8b248a2ba3d4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1432879229 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 16.rom_ctrl_csr_mem_rw_with_rand_reset.1432879229
Directory /workspace/16.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_rw.539929623
Short name T384
Test name
Test status
Simulation time 2229238198 ps
CPU time 11.54 seconds
Started Mar 07 12:54:19 PM PST 24
Finished Mar 07 12:54:30 PM PST 24
Peak memory 210928 kb
Host smart-0b8b57c9-832f-4eca-a3d7-c858bbcdee60
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=539929623 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_csr_rw.539929623
Directory /workspace/16.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_passthru_mem_tl_intg_err.2161215948
Short name T111
Test name
Test status
Simulation time 44472336602 ps
CPU time 92.69 seconds
Started Mar 07 12:54:02 PM PST 24
Finished Mar 07 12:55:36 PM PST 24
Peak memory 210936 kb
Host smart-52d9709e-7ea3-446d-9eaa-d463a7174ce9
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2161215948 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_p
assthru_mem_tl_intg_err.2161215948
Directory /workspace/16.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_same_csr_outstanding.1020317938
Short name T450
Test name
Test status
Simulation time 26393088473 ps
CPU time 17.64 seconds
Started Mar 07 12:54:05 PM PST 24
Finished Mar 07 12:54:23 PM PST 24
Peak memory 210936 kb
Host smart-7b962a0c-e5e4-4304-aa2c-6fc513fc63f7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1020317938 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_
ctrl_same_csr_outstanding.1020317938
Directory /workspace/16.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_errors.1100977534
Short name T434
Test name
Test status
Simulation time 4506895340 ps
CPU time 13.33 seconds
Started Mar 07 12:54:09 PM PST 24
Finished Mar 07 12:54:22 PM PST 24
Peak memory 215436 kb
Host smart-0cf7fe01-e94a-41d3-886b-b001251e5f3e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1100977534 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_tl_errors.1100977534
Directory /workspace/16.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_intg_err.1092543675
Short name T118
Test name
Test status
Simulation time 1109394559 ps
CPU time 41.96 seconds
Started Mar 07 12:54:18 PM PST 24
Finished Mar 07 12:55:00 PM PST 24
Peak memory 212076 kb
Host smart-ad20e071-6e24-406e-b475-636192ccab9f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1092543675 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_tl_i
ntg_err.1092543675
Directory /workspace/16.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_mem_rw_with_rand_reset.551847028
Short name T446
Test name
Test status
Simulation time 7509210199 ps
CPU time 15.68 seconds
Started Mar 07 12:54:23 PM PST 24
Finished Mar 07 12:54:39 PM PST 24
Peak memory 212904 kb
Host smart-67d9a4f1-8337-4f70-adaa-3149f0c24b85
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=551847028 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 17.rom_ctrl_csr_mem_rw_with_rand_reset.551847028
Directory /workspace/17.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_rw.3672837215
Short name T416
Test name
Test status
Simulation time 830491350 ps
CPU time 9.47 seconds
Started Mar 07 12:54:19 PM PST 24
Finished Mar 07 12:54:28 PM PST 24
Peak memory 210728 kb
Host smart-2e02181f-0ed7-4b09-8710-5557834aab0d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3672837215 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_csr_rw.3672837215
Directory /workspace/17.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_passthru_mem_tl_intg_err.1320118462
Short name T97
Test name
Test status
Simulation time 763772940 ps
CPU time 18.72 seconds
Started Mar 07 12:54:10 PM PST 24
Finished Mar 07 12:54:29 PM PST 24
Peak memory 210744 kb
Host smart-561c901c-e185-4bb0-b464-8f6c16e161c0
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1320118462 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_p
assthru_mem_tl_intg_err.1320118462
Directory /workspace/17.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_same_csr_outstanding.1577151937
Short name T85
Test name
Test status
Simulation time 7018077947 ps
CPU time 14.45 seconds
Started Mar 07 12:54:32 PM PST 24
Finished Mar 07 12:54:46 PM PST 24
Peak memory 210924 kb
Host smart-50849a2a-21dd-4649-bfab-7e65ddf29f51
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1577151937 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_
ctrl_same_csr_outstanding.1577151937
Directory /workspace/17.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_errors.65631179
Short name T402
Test name
Test status
Simulation time 3048582920 ps
CPU time 15.2 seconds
Started Mar 07 12:54:32 PM PST 24
Finished Mar 07 12:54:47 PM PST 24
Peak memory 214788 kb
Host smart-147dbd65-a225-435f-8eec-a8929c05f1e0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=65631179 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_tl_errors.65631179
Directory /workspace/17.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_intg_err.2608742154
Short name T457
Test name
Test status
Simulation time 1904425042 ps
CPU time 39.56 seconds
Started Mar 07 12:54:16 PM PST 24
Finished Mar 07 12:55:01 PM PST 24
Peak memory 212380 kb
Host smart-86958e1d-9691-4c49-80ef-7636e9546731
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2608742154 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_tl_i
ntg_err.2608742154
Directory /workspace/17.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_mem_rw_with_rand_reset.4270873008
Short name T366
Test name
Test status
Simulation time 195953440 ps
CPU time 4.76 seconds
Started Mar 07 12:54:15 PM PST 24
Finished Mar 07 12:54:20 PM PST 24
Peak memory 213724 kb
Host smart-94506433-ec33-4886-8df7-9bd08e2dd591
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4270873008 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 18.rom_ctrl_csr_mem_rw_with_rand_reset.4270873008
Directory /workspace/18.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_rw.4095825247
Short name T442
Test name
Test status
Simulation time 2827525594 ps
CPU time 7.25 seconds
Started Mar 07 12:54:16 PM PST 24
Finished Mar 07 12:54:23 PM PST 24
Peak memory 210868 kb
Host smart-f500b788-3c11-4bba-8e3d-0613e473241e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4095825247 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_csr_rw.4095825247
Directory /workspace/18.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_passthru_mem_tl_intg_err.3320434710
Short name T410
Test name
Test status
Simulation time 4151174730 ps
CPU time 43.34 seconds
Started Mar 07 12:54:25 PM PST 24
Finished Mar 07 12:55:14 PM PST 24
Peak memory 210904 kb
Host smart-5dc5629e-8712-4063-84ff-70d56d33c1d3
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3320434710 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_p
assthru_mem_tl_intg_err.3320434710
Directory /workspace/18.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_same_csr_outstanding.2343988132
Short name T376
Test name
Test status
Simulation time 4604075284 ps
CPU time 7.16 seconds
Started Mar 07 12:54:24 PM PST 24
Finished Mar 07 12:54:32 PM PST 24
Peak memory 210924 kb
Host smart-0ecd61cc-e74a-4115-a7eb-ec07e19a42fd
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2343988132 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_
ctrl_same_csr_outstanding.2343988132
Directory /workspace/18.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_errors.1335803988
Short name T460
Test name
Test status
Simulation time 5664209052 ps
CPU time 14.49 seconds
Started Mar 07 12:53:58 PM PST 24
Finished Mar 07 12:54:13 PM PST 24
Peak memory 215372 kb
Host smart-186178e4-487b-424c-9e83-513d763eb174
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1335803988 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_tl_errors.1335803988
Directory /workspace/18.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_intg_err.1179768740
Short name T68
Test name
Test status
Simulation time 6878776825 ps
CPU time 39.83 seconds
Started Mar 07 12:54:26 PM PST 24
Finished Mar 07 12:55:06 PM PST 24
Peak memory 211736 kb
Host smart-6d09c2c2-2f23-4f40-850b-c7fbe5b3c34b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1179768740 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_tl_i
ntg_err.1179768740
Directory /workspace/18.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_mem_rw_with_rand_reset.300257165
Short name T378
Test name
Test status
Simulation time 525485865 ps
CPU time 6.71 seconds
Started Mar 07 12:54:11 PM PST 24
Finished Mar 07 12:54:18 PM PST 24
Peak memory 214608 kb
Host smart-0d991f21-e562-47de-ae96-b39154f0b4d0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=300257165 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 19.rom_ctrl_csr_mem_rw_with_rand_reset.300257165
Directory /workspace/19.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_rw.1184915767
Short name T393
Test name
Test status
Simulation time 15942152735 ps
CPU time 11.89 seconds
Started Mar 07 12:54:07 PM PST 24
Finished Mar 07 12:54:19 PM PST 24
Peak memory 210916 kb
Host smart-cc873a94-7908-4133-82b7-e82714ba0e73
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1184915767 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_csr_rw.1184915767
Directory /workspace/19.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_passthru_mem_tl_intg_err.1242673666
Short name T452
Test name
Test status
Simulation time 44425078396 ps
CPU time 64.44 seconds
Started Mar 07 12:54:25 PM PST 24
Finished Mar 07 12:55:29 PM PST 24
Peak memory 210888 kb
Host smart-c4e6d637-cdcc-4887-a796-f00964c33ca0
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1242673666 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_p
assthru_mem_tl_intg_err.1242673666
Directory /workspace/19.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_same_csr_outstanding.1615295271
Short name T409
Test name
Test status
Simulation time 2673005007 ps
CPU time 8.19 seconds
Started Mar 07 12:54:23 PM PST 24
Finished Mar 07 12:54:31 PM PST 24
Peak memory 210920 kb
Host smart-134aa0a4-caa2-415f-adde-df1db4fdeacd
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1615295271 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_
ctrl_same_csr_outstanding.1615295271
Directory /workspace/19.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_errors.1584859337
Short name T367
Test name
Test status
Simulation time 1482480591 ps
CPU time 16.14 seconds
Started Mar 07 12:54:12 PM PST 24
Finished Mar 07 12:54:28 PM PST 24
Peak memory 214828 kb
Host smart-60534ded-02cf-4fca-be42-5e1336e5f6ef
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1584859337 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_tl_errors.1584859337
Directory /workspace/19.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_intg_err.1411147140
Short name T66
Test name
Test status
Simulation time 9916747227 ps
CPU time 78.59 seconds
Started Mar 07 12:54:17 PM PST 24
Finished Mar 07 12:55:35 PM PST 24
Peak memory 210916 kb
Host smart-65e018f2-25f9-43a0-9632-b1b30166f7fd
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1411147140 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_tl_i
ntg_err.1411147140
Directory /workspace/19.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_aliasing.2529736444
Short name T396
Test name
Test status
Simulation time 1841345108 ps
CPU time 9.4 seconds
Started Mar 07 12:54:01 PM PST 24
Finished Mar 07 12:54:12 PM PST 24
Peak memory 210628 kb
Host smart-815aa857-d41f-4715-a58a-eba96731f0cd
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2529736444 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_alia
sing.2529736444
Directory /workspace/2.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_bit_bash.597638606
Short name T379
Test name
Test status
Simulation time 3741775846 ps
CPU time 9.72 seconds
Started Mar 07 12:53:53 PM PST 24
Finished Mar 07 12:54:03 PM PST 24
Peak memory 210860 kb
Host smart-1436b0b6-c423-4df0-8fb8-34a4d8186e0f
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=597638606 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_bit_b
ash.597638606
Directory /workspace/2.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_hw_reset.1502970645
Short name T86
Test name
Test status
Simulation time 93444617 ps
CPU time 7.33 seconds
Started Mar 07 12:54:02 PM PST 24
Finished Mar 07 12:54:10 PM PST 24
Peak memory 210744 kb
Host smart-12ab5440-c57c-431e-9885-0d7d762f52fc
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1502970645 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_hw_r
eset.1502970645
Directory /workspace/2.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_mem_rw_with_rand_reset.1733753778
Short name T413
Test name
Test status
Simulation time 1161558073 ps
CPU time 11.65 seconds
Started Mar 07 12:54:01 PM PST 24
Finished Mar 07 12:54:13 PM PST 24
Peak memory 216076 kb
Host smart-f7f799f9-e536-4bd8-baa8-1bcbbedd10b3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1733753778 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 2.rom_ctrl_csr_mem_rw_with_rand_reset.1733753778
Directory /workspace/2.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_rw.2692770038
Short name T375
Test name
Test status
Simulation time 1031536560 ps
CPU time 7.24 seconds
Started Mar 07 12:53:55 PM PST 24
Finished Mar 07 12:54:03 PM PST 24
Peak memory 210748 kb
Host smart-9b5fb2a7-6663-46c3-9287-10153cced552
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2692770038 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_rw.2692770038
Directory /workspace/2.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_partial_access.3711119742
Short name T420
Test name
Test status
Simulation time 2228309977 ps
CPU time 14.99 seconds
Started Mar 07 12:54:12 PM PST 24
Finished Mar 07 12:54:27 PM PST 24
Peak memory 210700 kb
Host smart-6cdbdf82-0f55-45b0-8f52-4314fb200670
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3711119742 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctr
l_mem_partial_access.3711119742
Directory /workspace/2.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_walk.3369990545
Short name T364
Test name
Test status
Simulation time 4111501669 ps
CPU time 10.71 seconds
Started Mar 07 12:54:00 PM PST 24
Finished Mar 07 12:54:12 PM PST 24
Peak memory 210720 kb
Host smart-a0e0354d-7820-4503-ba8f-1697ca50313d
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3369990545 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_mem_walk
.3369990545
Directory /workspace/2.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_passthru_mem_tl_intg_err.3702608316
Short name T99
Test name
Test status
Simulation time 1082833294 ps
CPU time 27.45 seconds
Started Mar 07 12:54:14 PM PST 24
Finished Mar 07 12:54:42 PM PST 24
Peak memory 210808 kb
Host smart-bcf45722-4efe-4e38-964e-ac6e86d0203c
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3702608316 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_pa
ssthru_mem_tl_intg_err.3702608316
Directory /workspace/2.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_same_csr_outstanding.3703824775
Short name T381
Test name
Test status
Simulation time 769278024 ps
CPU time 8.77 seconds
Started Mar 07 12:53:57 PM PST 24
Finished Mar 07 12:54:06 PM PST 24
Peak memory 210884 kb
Host smart-ba924e65-ec38-498e-8d82-7cfe1668f2e2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3703824775 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_c
trl_same_csr_outstanding.3703824775
Directory /workspace/2.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_errors.4142878758
Short name T441
Test name
Test status
Simulation time 1523013575 ps
CPU time 18.02 seconds
Started Mar 07 12:54:03 PM PST 24
Finished Mar 07 12:54:21 PM PST 24
Peak memory 215116 kb
Host smart-825c3c2d-2b87-4937-8845-05f858854b10
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4142878758 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_tl_errors.4142878758
Directory /workspace/2.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_intg_err.3551921920
Short name T124
Test name
Test status
Simulation time 863498281 ps
CPU time 68.96 seconds
Started Mar 07 12:54:01 PM PST 24
Finished Mar 07 12:55:11 PM PST 24
Peak memory 210808 kb
Host smart-2dcdf129-73b9-44b1-82fd-706e2e305ff9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3551921920 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_tl_in
tg_err.3551921920
Directory /workspace/2.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_aliasing.570893389
Short name T94
Test name
Test status
Simulation time 4275029413 ps
CPU time 16.32 seconds
Started Mar 07 12:54:04 PM PST 24
Finished Mar 07 12:54:21 PM PST 24
Peak memory 210860 kb
Host smart-cfac0658-0ca3-4bd5-80e0-4e9466c93a20
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=570893389 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_alias
ing.570893389
Directory /workspace/3.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_bit_bash.893760631
Short name T453
Test name
Test status
Simulation time 1700719917 ps
CPU time 15.35 seconds
Started Mar 07 12:54:12 PM PST 24
Finished Mar 07 12:54:28 PM PST 24
Peak memory 210644 kb
Host smart-bc2664c4-06ce-44ba-b743-ced3b39ee35e
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=893760631 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_bit_b
ash.893760631
Directory /workspace/3.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_hw_reset.376383017
Short name T380
Test name
Test status
Simulation time 1572832651 ps
CPU time 14.85 seconds
Started Mar 07 12:54:10 PM PST 24
Finished Mar 07 12:54:25 PM PST 24
Peak memory 210724 kb
Host smart-a065b294-7d4b-4b7c-a5d1-2bd72296e7b4
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=376383017 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_hw_re
set.376383017
Directory /workspace/3.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_mem_rw_with_rand_reset.2953941091
Short name T377
Test name
Test status
Simulation time 5744180696 ps
CPU time 14.28 seconds
Started Mar 07 12:54:12 PM PST 24
Finished Mar 07 12:54:27 PM PST 24
Peak memory 215844 kb
Host smart-509f3e41-d1ec-4837-b820-7ff33d73cf0d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2953941091 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 3.rom_ctrl_csr_mem_rw_with_rand_reset.2953941091
Directory /workspace/3.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_rw.221037665
Short name T107
Test name
Test status
Simulation time 861383353 ps
CPU time 9.56 seconds
Started Mar 07 12:54:25 PM PST 24
Finished Mar 07 12:54:34 PM PST 24
Peak memory 210656 kb
Host smart-e63eeec4-7fd8-43ea-954b-28236401ceea
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=221037665 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_rw.221037665
Directory /workspace/3.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_partial_access.957610698
Short name T388
Test name
Test status
Simulation time 2460928259 ps
CPU time 8.13 seconds
Started Mar 07 12:54:02 PM PST 24
Finished Mar 07 12:54:11 PM PST 24
Peak memory 210792 kb
Host smart-608feac2-34d6-45e5-9030-325fac3e6166
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=957610698 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl
_mem_partial_access.957610698
Directory /workspace/3.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_walk.4015660722
Short name T419
Test name
Test status
Simulation time 4452578900 ps
CPU time 10.3 seconds
Started Mar 07 12:54:02 PM PST 24
Finished Mar 07 12:54:13 PM PST 24
Peak memory 210712 kb
Host smart-6c3e7ae3-9fdc-4ceb-ba60-1819e794904b
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4015660722 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_mem_walk
.4015660722
Directory /workspace/3.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_passthru_mem_tl_intg_err.1948260616
Short name T81
Test name
Test status
Simulation time 19686619877 ps
CPU time 44.11 seconds
Started Mar 07 12:54:13 PM PST 24
Finished Mar 07 12:54:58 PM PST 24
Peak memory 210888 kb
Host smart-4bf0f4c0-65ed-409e-8703-374c0de33e58
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1948260616 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_pa
ssthru_mem_tl_intg_err.1948260616
Directory /workspace/3.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_same_csr_outstanding.986773022
Short name T436
Test name
Test status
Simulation time 6911124179 ps
CPU time 12.01 seconds
Started Mar 07 12:54:18 PM PST 24
Finished Mar 07 12:54:30 PM PST 24
Peak memory 210996 kb
Host smart-7bdc1d82-d1ee-43d1-834f-596f7857aa42
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=986773022 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ct
rl_same_csr_outstanding.986773022
Directory /workspace/3.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_errors.1776070622
Short name T432
Test name
Test status
Simulation time 5478978923 ps
CPU time 14.96 seconds
Started Mar 07 12:53:50 PM PST 24
Finished Mar 07 12:54:05 PM PST 24
Peak memory 215100 kb
Host smart-5b8d472f-4aa6-482f-a490-352aa6a4211c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1776070622 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_tl_errors.1776070622
Directory /workspace/3.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_aliasing.292195657
Short name T449
Test name
Test status
Simulation time 2043821287 ps
CPU time 7.69 seconds
Started Mar 07 12:54:12 PM PST 24
Finished Mar 07 12:54:19 PM PST 24
Peak memory 210732 kb
Host smart-1a3e1bcd-4c35-49a9-85e2-9334491b3326
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=292195657 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_alias
ing.292195657
Directory /workspace/4.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_bit_bash.1900327560
Short name T415
Test name
Test status
Simulation time 348330882 ps
CPU time 4.57 seconds
Started Mar 07 12:54:00 PM PST 24
Finished Mar 07 12:54:04 PM PST 24
Peak memory 210728 kb
Host smart-2f09082d-b543-439e-b9d9-d0289f6e5528
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1900327560 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_bit_
bash.1900327560
Directory /workspace/4.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_hw_reset.4267883392
Short name T387
Test name
Test status
Simulation time 2028986201 ps
CPU time 17.48 seconds
Started Mar 07 12:54:18 PM PST 24
Finished Mar 07 12:54:35 PM PST 24
Peak memory 210744 kb
Host smart-f716006a-9774-418f-9adb-65c86eff44bf
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4267883392 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_hw_r
eset.4267883392
Directory /workspace/4.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_mem_rw_with_rand_reset.364057190
Short name T458
Test name
Test status
Simulation time 7666162713 ps
CPU time 10.68 seconds
Started Mar 07 12:54:12 PM PST 24
Finished Mar 07 12:54:23 PM PST 24
Peak memory 215216 kb
Host smart-16186c73-a685-420a-bd04-a86ec16a0539
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=364057190 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 4.rom_ctrl_csr_mem_rw_with_rand_reset.364057190
Directory /workspace/4.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_rw.3187748532
Short name T463
Test name
Test status
Simulation time 85614088 ps
CPU time 4.24 seconds
Started Mar 07 12:54:19 PM PST 24
Finished Mar 07 12:54:23 PM PST 24
Peak memory 210744 kb
Host smart-5ef11007-1454-4421-b595-15d0b30a3ed1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3187748532 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_rw.3187748532
Directory /workspace/4.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_partial_access.3538051283
Short name T459
Test name
Test status
Simulation time 2664045847 ps
CPU time 9.19 seconds
Started Mar 07 12:54:07 PM PST 24
Finished Mar 07 12:54:17 PM PST 24
Peak memory 210780 kb
Host smart-5cb024c2-ead1-450c-80e2-607700d0dd5d
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3538051283 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctr
l_mem_partial_access.3538051283
Directory /workspace/4.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_walk.671224117
Short name T422
Test name
Test status
Simulation time 2383384825 ps
CPU time 11.1 seconds
Started Mar 07 12:54:01 PM PST 24
Finished Mar 07 12:54:13 PM PST 24
Peak memory 210860 kb
Host smart-ede4bcfb-679f-4ad6-b6e0-7eea6c7f4dd9
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=671224117 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_mem_walk.
671224117
Directory /workspace/4.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_same_csr_outstanding.3014934720
Short name T79
Test name
Test status
Simulation time 892321608 ps
CPU time 7.35 seconds
Started Mar 07 12:54:01 PM PST 24
Finished Mar 07 12:54:10 PM PST 24
Peak memory 210796 kb
Host smart-b6eab90a-ccfa-4fe8-8748-631d9ff01964
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3014934720 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_c
trl_same_csr_outstanding.3014934720
Directory /workspace/4.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_errors.1790070550
Short name T448
Test name
Test status
Simulation time 19249122775 ps
CPU time 18.56 seconds
Started Mar 07 12:54:07 PM PST 24
Finished Mar 07 12:54:27 PM PST 24
Peak memory 215496 kb
Host smart-5c4bbb5c-697a-4232-b77c-bfee53fd02c7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1790070550 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_tl_errors.1790070550
Directory /workspace/4.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_intg_err.3140423747
Short name T122
Test name
Test status
Simulation time 7056134331 ps
CPU time 77.47 seconds
Started Mar 07 12:54:03 PM PST 24
Finished Mar 07 12:55:21 PM PST 24
Peak memory 213252 kb
Host smart-b73af0ce-e7ab-4951-ba73-764211c09dad
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3140423747 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_tl_in
tg_err.3140423747
Directory /workspace/4.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_mem_rw_with_rand_reset.2013518496
Short name T399
Test name
Test status
Simulation time 2432556620 ps
CPU time 10.37 seconds
Started Mar 07 12:54:17 PM PST 24
Finished Mar 07 12:54:28 PM PST 24
Peak memory 213624 kb
Host smart-72c296da-3fee-43af-bb23-ecd9049782ee
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2013518496 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 5.rom_ctrl_csr_mem_rw_with_rand_reset.2013518496
Directory /workspace/5.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_rw.2811880237
Short name T370
Test name
Test status
Simulation time 1723074730 ps
CPU time 14.51 seconds
Started Mar 07 12:54:12 PM PST 24
Finished Mar 07 12:54:26 PM PST 24
Peak memory 210728 kb
Host smart-3080c7a7-4800-4774-bf49-1f96b0e0d8ae
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2811880237 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_csr_rw.2811880237
Directory /workspace/5.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_passthru_mem_tl_intg_err.3649808556
Short name T93
Test name
Test status
Simulation time 3900967352 ps
CPU time 29.18 seconds
Started Mar 07 12:54:12 PM PST 24
Finished Mar 07 12:54:41 PM PST 24
Peak memory 210936 kb
Host smart-4a27818c-d10a-4510-bd93-034dbb62e634
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3649808556 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_pa
ssthru_mem_tl_intg_err.3649808556
Directory /workspace/5.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_same_csr_outstanding.3901689222
Short name T426
Test name
Test status
Simulation time 416965701 ps
CPU time 4.15 seconds
Started Mar 07 12:54:10 PM PST 24
Finished Mar 07 12:54:14 PM PST 24
Peak memory 210792 kb
Host smart-a45d0e3d-7fe1-4509-afe5-c74e744ebdc5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3901689222 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_c
trl_same_csr_outstanding.3901689222
Directory /workspace/5.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_errors.765388452
Short name T429
Test name
Test status
Simulation time 717383917 ps
CPU time 12.73 seconds
Started Mar 07 12:54:04 PM PST 24
Finished Mar 07 12:54:16 PM PST 24
Peak memory 215184 kb
Host smart-68912f8a-5f0e-44c5-afb0-b625e34220fd
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=765388452 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_tl_errors.765388452
Directory /workspace/5.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_intg_err.502024685
Short name T121
Test name
Test status
Simulation time 1743865522 ps
CPU time 79.47 seconds
Started Mar 07 12:53:59 PM PST 24
Finished Mar 07 12:55:18 PM PST 24
Peak memory 210788 kb
Host smart-1c75c98a-b7e7-4973-9de1-089446bd3a39
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=502024685 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_tl_int
g_err.502024685
Directory /workspace/5.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_mem_rw_with_rand_reset.599508992
Short name T70
Test name
Test status
Simulation time 1891372112 ps
CPU time 14.92 seconds
Started Mar 07 12:54:17 PM PST 24
Finished Mar 07 12:54:32 PM PST 24
Peak memory 215220 kb
Host smart-094f9a5a-7190-41f2-8270-536270542e94
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=599508992 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 6.rom_ctrl_csr_mem_rw_with_rand_reset.599508992
Directory /workspace/6.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_rw.3966213864
Short name T443
Test name
Test status
Simulation time 8247559040 ps
CPU time 11.83 seconds
Started Mar 07 12:54:12 PM PST 24
Finished Mar 07 12:54:24 PM PST 24
Peak memory 210888 kb
Host smart-e43baea8-38a0-424c-bbe4-7e0c283d76d5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3966213864 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_csr_rw.3966213864
Directory /workspace/6.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_passthru_mem_tl_intg_err.3199548960
Short name T423
Test name
Test status
Simulation time 2613043629 ps
CPU time 44.67 seconds
Started Mar 07 12:54:18 PM PST 24
Finished Mar 07 12:55:02 PM PST 24
Peak memory 210916 kb
Host smart-03275383-5273-4ef9-a71f-7e82dbf25f94
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3199548960 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_pa
ssthru_mem_tl_intg_err.3199548960
Directory /workspace/6.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_same_csr_outstanding.360230557
Short name T437
Test name
Test status
Simulation time 1308685346 ps
CPU time 11.83 seconds
Started Mar 07 12:54:13 PM PST 24
Finished Mar 07 12:54:25 PM PST 24
Peak memory 210696 kb
Host smart-b79ba6d3-1a29-4325-b915-8929f9e8afed
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=360230557 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ct
rl_same_csr_outstanding.360230557
Directory /workspace/6.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_errors.3589115688
Short name T439
Test name
Test status
Simulation time 2731364367 ps
CPU time 12.33 seconds
Started Mar 07 12:54:17 PM PST 24
Finished Mar 07 12:54:30 PM PST 24
Peak memory 215176 kb
Host smart-ee0c9ea9-c58a-462a-93c1-3ecc6eb8a297
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3589115688 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_tl_errors.3589115688
Directory /workspace/6.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_mem_rw_with_rand_reset.25376578
Short name T411
Test name
Test status
Simulation time 1253637702 ps
CPU time 12.55 seconds
Started Mar 07 12:54:02 PM PST 24
Finished Mar 07 12:54:15 PM PST 24
Peak memory 214836 kb
Host smart-ecc9c59e-7dfe-4702-ba3a-3f76a4a28af4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25376578 -assert nopostproc +UVM_TESTNAME=r
om_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 7.rom_ctrl_csr_mem_rw_with_rand_reset.25376578
Directory /workspace/7.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_rw.825751840
Short name T84
Test name
Test status
Simulation time 1026693890 ps
CPU time 10.63 seconds
Started Mar 07 12:54:04 PM PST 24
Finished Mar 07 12:54:15 PM PST 24
Peak memory 210744 kb
Host smart-8ecd9a5d-81d0-4107-9ae5-c4c9cb9b3147
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=825751840 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_csr_rw.825751840
Directory /workspace/7.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_passthru_mem_tl_intg_err.2528757297
Short name T82
Test name
Test status
Simulation time 1358105881 ps
CPU time 27.48 seconds
Started Mar 07 12:54:24 PM PST 24
Finished Mar 07 12:54:52 PM PST 24
Peak memory 210808 kb
Host smart-58884102-08f5-43f4-a4ec-cde9ec058573
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2528757297 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_pa
ssthru_mem_tl_intg_err.2528757297
Directory /workspace/7.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_same_csr_outstanding.3182380126
Short name T71
Test name
Test status
Simulation time 921297609 ps
CPU time 4.3 seconds
Started Mar 07 12:54:26 PM PST 24
Finished Mar 07 12:54:31 PM PST 24
Peak memory 210800 kb
Host smart-5f1bccbf-c777-47fc-9217-73221af48181
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3182380126 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_c
trl_same_csr_outstanding.3182380126
Directory /workspace/7.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_errors.3077090878
Short name T407
Test name
Test status
Simulation time 6250053702 ps
CPU time 14.77 seconds
Started Mar 07 12:54:18 PM PST 24
Finished Mar 07 12:54:32 PM PST 24
Peak memory 215492 kb
Host smart-7be75ddb-f5c9-4fe4-b79d-a791771ed43e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3077090878 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_tl_errors.3077090878
Directory /workspace/7.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_intg_err.1943813377
Short name T112
Test name
Test status
Simulation time 6925361313 ps
CPU time 75.56 seconds
Started Mar 07 12:54:20 PM PST 24
Finished Mar 07 12:55:36 PM PST 24
Peak memory 210996 kb
Host smart-6ed8db26-bb35-4a38-b2c4-75f854eea96b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1943813377 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_tl_in
tg_err.1943813377
Directory /workspace/7.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_mem_rw_with_rand_reset.1558619042
Short name T424
Test name
Test status
Simulation time 1684570217 ps
CPU time 6.55 seconds
Started Mar 07 12:54:32 PM PST 24
Finished Mar 07 12:54:38 PM PST 24
Peak memory 215300 kb
Host smart-9c4f2702-0bbd-40ed-a755-6a1f4bec2536
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1558619042 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 8.rom_ctrl_csr_mem_rw_with_rand_reset.1558619042
Directory /workspace/8.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_rw.675340355
Short name T105
Test name
Test status
Simulation time 167759387 ps
CPU time 5.3 seconds
Started Mar 07 12:54:08 PM PST 24
Finished Mar 07 12:54:13 PM PST 24
Peak memory 210760 kb
Host smart-3ac387bd-04a9-4d6c-b2cd-291a28fbfcc7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=675340355 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_csr_rw.675340355
Directory /workspace/8.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_passthru_mem_tl_intg_err.1499121772
Short name T92
Test name
Test status
Simulation time 4135389820 ps
CPU time 28.74 seconds
Started Mar 07 12:54:15 PM PST 24
Finished Mar 07 12:54:44 PM PST 24
Peak memory 210888 kb
Host smart-6f6ab430-23ac-4093-aad7-66ed8c8e6b65
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1499121772 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_pa
ssthru_mem_tl_intg_err.1499121772
Directory /workspace/8.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_same_csr_outstanding.216119673
Short name T106
Test name
Test status
Simulation time 94076753 ps
CPU time 4.38 seconds
Started Mar 07 12:54:22 PM PST 24
Finished Mar 07 12:54:27 PM PST 24
Peak memory 210808 kb
Host smart-7f069537-8683-40f2-9f84-c70a2fe1f404
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=216119673 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ct
rl_same_csr_outstanding.216119673
Directory /workspace/8.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_errors.2993695173
Short name T462
Test name
Test status
Simulation time 85646803 ps
CPU time 7.92 seconds
Started Mar 07 12:54:20 PM PST 24
Finished Mar 07 12:54:28 PM PST 24
Peak memory 215216 kb
Host smart-b3b9c834-d3f1-4f77-b259-d22e3b4f46b4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2993695173 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_tl_errors.2993695173
Directory /workspace/8.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_intg_err.2469561488
Short name T405
Test name
Test status
Simulation time 32446016520 ps
CPU time 44.81 seconds
Started Mar 07 12:54:18 PM PST 24
Finished Mar 07 12:55:03 PM PST 24
Peak memory 211840 kb
Host smart-e601697e-7b38-4cbd-8204-53094bbba5ad
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2469561488 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_tl_in
tg_err.2469561488
Directory /workspace/8.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_mem_rw_with_rand_reset.4117675375
Short name T385
Test name
Test status
Simulation time 175393204 ps
CPU time 4.53 seconds
Started Mar 07 12:54:20 PM PST 24
Finished Mar 07 12:54:24 PM PST 24
Peak memory 213632 kb
Host smart-ed3f5d79-33aa-487e-a3a2-15298478a2c0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4117675375 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 9.rom_ctrl_csr_mem_rw_with_rand_reset.4117675375
Directory /workspace/9.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_rw.3409523992
Short name T430
Test name
Test status
Simulation time 5536525211 ps
CPU time 12.3 seconds
Started Mar 07 12:54:15 PM PST 24
Finished Mar 07 12:54:28 PM PST 24
Peak memory 210864 kb
Host smart-f0c56863-25f5-4789-809c-62092cf67e33
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3409523992 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_csr_rw.3409523992
Directory /workspace/9.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_passthru_mem_tl_intg_err.1520498373
Short name T101
Test name
Test status
Simulation time 12444873961 ps
CPU time 48.06 seconds
Started Mar 07 12:54:18 PM PST 24
Finished Mar 07 12:55:07 PM PST 24
Peak memory 210888 kb
Host smart-2392cada-293d-4772-854f-53b0586c8357
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1520498373 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_pa
ssthru_mem_tl_intg_err.1520498373
Directory /workspace/9.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_same_csr_outstanding.1412304311
Short name T72
Test name
Test status
Simulation time 89316522 ps
CPU time 4.25 seconds
Started Mar 07 12:54:08 PM PST 24
Finished Mar 07 12:54:12 PM PST 24
Peak memory 210808 kb
Host smart-43f2cb4d-b550-48e3-aa3b-f142a30bfade
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1412304311 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_c
trl_same_csr_outstanding.1412304311
Directory /workspace/9.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_errors.3020201035
Short name T390
Test name
Test status
Simulation time 830952860 ps
CPU time 7.39 seconds
Started Mar 07 12:54:03 PM PST 24
Finished Mar 07 12:54:11 PM PST 24
Peak memory 215148 kb
Host smart-7db206f7-d6c6-4dcd-b386-557d5ff89172
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3020201035 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_tl_errors.3020201035
Directory /workspace/9.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_intg_err.588024059
Short name T117
Test name
Test status
Simulation time 2613908181 ps
CPU time 38.86 seconds
Started Mar 07 12:54:01 PM PST 24
Finished Mar 07 12:54:41 PM PST 24
Peak memory 210928 kb
Host smart-6b1dc974-4d06-418f-8c43-56760293d598
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=588024059 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_tl_int
g_err.588024059
Directory /workspace/9.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/0.rom_ctrl_alert_test.1362475558
Short name T168
Test name
Test status
Simulation time 296077828 ps
CPU time 5.69 seconds
Started Mar 07 12:55:21 PM PST 24
Finished Mar 07 12:55:27 PM PST 24
Peak memory 210856 kb
Host smart-61b31d95-0a38-4f71-93c4-22c20507e1be
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1362475558 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_alert_test.1362475558
Directory /workspace/0.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/0.rom_ctrl_corrupt_sig_fatal_chk.2750330578
Short name T32
Test name
Test status
Simulation time 34552203474 ps
CPU time 339.63 seconds
Started Mar 07 12:55:21 PM PST 24
Finished Mar 07 01:01:01 PM PST 24
Peak memory 236364 kb
Host smart-efcb8dc4-86f1-49a2-83a4-4a0d91643eae
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2750330578 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_c
orrupt_sig_fatal_chk.2750330578
Directory /workspace/0.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/0.rom_ctrl_kmac_err_chk.1956572546
Short name T193
Test name
Test status
Simulation time 3828422326 ps
CPU time 31.08 seconds
Started Mar 07 12:55:00 PM PST 24
Finished Mar 07 12:55:32 PM PST 24
Peak memory 211448 kb
Host smart-bbbebb8f-f04f-4c3f-ac4c-f03a6288d144
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1956572546 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_kmac_err_chk.1956572546
Directory /workspace/0.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/0.rom_ctrl_max_throughput_chk.3474287162
Short name T205
Test name
Test status
Simulation time 573737092 ps
CPU time 7.58 seconds
Started Mar 07 12:55:04 PM PST 24
Finished Mar 07 12:55:12 PM PST 24
Peak memory 210764 kb
Host smart-5ba36e07-5817-417a-8f20-45c9e76caa3c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3474287162 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_max_throughput_chk.3474287162
Directory /workspace/0.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/0.rom_ctrl_smoke.1151952515
Short name T89
Test name
Test status
Simulation time 4710777685 ps
CPU time 31.69 seconds
Started Mar 07 12:55:21 PM PST 24
Finished Mar 07 12:55:53 PM PST 24
Peak memory 219060 kb
Host smart-eabd5e66-3059-44a6-aa10-1d976533461e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1151952515 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_smoke.1151952515
Directory /workspace/0.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/0.rom_ctrl_stress_all.3875017775
Short name T130
Test name
Test status
Simulation time 30280493505 ps
CPU time 73.96 seconds
Started Mar 07 12:55:16 PM PST 24
Finished Mar 07 12:56:32 PM PST 24
Peak memory 219060 kb
Host smart-3556acbc-5a0d-4e9a-a1b7-d8ef7355285f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3875017775 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 0.rom_ctrl_stress_all.3875017775
Directory /workspace/0.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/1.rom_ctrl_alert_test.3374328753
Short name T198
Test name
Test status
Simulation time 1284650097 ps
CPU time 8.4 seconds
Started Mar 07 12:55:25 PM PST 24
Finished Mar 07 12:55:34 PM PST 24
Peak memory 210888 kb
Host smart-bbbe854d-5e34-438f-801f-aa3a4ad70aa6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3374328753 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_alert_test.3374328753
Directory /workspace/1.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/1.rom_ctrl_corrupt_sig_fatal_chk.2381029053
Short name T218
Test name
Test status
Simulation time 13177232488 ps
CPU time 156.52 seconds
Started Mar 07 12:55:09 PM PST 24
Finished Mar 07 12:57:46 PM PST 24
Peak memory 213120 kb
Host smart-fb1d16ba-45e0-4d38-a80d-7648b58849cb
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2381029053 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_c
orrupt_sig_fatal_chk.2381029053
Directory /workspace/1.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/1.rom_ctrl_max_throughput_chk.2948340418
Short name T331
Test name
Test status
Simulation time 879912591 ps
CPU time 11.11 seconds
Started Mar 07 12:55:16 PM PST 24
Finished Mar 07 12:55:29 PM PST 24
Peak memory 210716 kb
Host smart-8e1d0be1-f4ca-4aa9-94a8-d13c4d10da34
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2948340418 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_max_throughput_chk.2948340418
Directory /workspace/1.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/1.rom_ctrl_sec_cm.2308873197
Short name T34
Test name
Test status
Simulation time 1750190293 ps
CPU time 107.82 seconds
Started Mar 07 12:55:22 PM PST 24
Finished Mar 07 12:57:10 PM PST 24
Peak memory 236128 kb
Host smart-ae3d6306-eb49-4bf8-aae6-d12b164f7182
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2308873197 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_sec_cm.2308873197
Directory /workspace/1.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/1.rom_ctrl_smoke.1915020186
Short name T261
Test name
Test status
Simulation time 749220897 ps
CPU time 10.3 seconds
Started Mar 07 12:55:12 PM PST 24
Finished Mar 07 12:55:22 PM PST 24
Peak memory 212608 kb
Host smart-f833b771-509e-4eeb-8ce9-76fdb3674017
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1915020186 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_smoke.1915020186
Directory /workspace/1.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/1.rom_ctrl_stress_all.3986246931
Short name T31
Test name
Test status
Simulation time 47963394647 ps
CPU time 105.54 seconds
Started Mar 07 12:55:22 PM PST 24
Finished Mar 07 12:57:08 PM PST 24
Peak memory 219104 kb
Host smart-8a54c2cf-0d7d-469d-812f-e82750b4e274
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3986246931 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 1.rom_ctrl_stress_all.3986246931
Directory /workspace/1.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/10.rom_ctrl_alert_test.3754275157
Short name T157
Test name
Test status
Simulation time 2116111175 ps
CPU time 16.37 seconds
Started Mar 07 12:55:27 PM PST 24
Finished Mar 07 12:55:44 PM PST 24
Peak memory 210832 kb
Host smart-ce5f5ed9-0ecb-46a3-bbe6-c83fbc91e774
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3754275157 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_alert_test.3754275157
Directory /workspace/10.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/10.rom_ctrl_corrupt_sig_fatal_chk.4233179837
Short name T60
Test name
Test status
Simulation time 47348388994 ps
CPU time 218.46 seconds
Started Mar 07 12:55:11 PM PST 24
Finished Mar 07 12:58:49 PM PST 24
Peak memory 228272 kb
Host smart-2ca37110-5f32-4c44-bf71-d8a99bfff106
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4233179837 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_
corrupt_sig_fatal_chk.4233179837
Directory /workspace/10.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/10.rom_ctrl_kmac_err_chk.2985299060
Short name T158
Test name
Test status
Simulation time 179136616 ps
CPU time 10.46 seconds
Started Mar 07 12:55:19 PM PST 24
Finished Mar 07 12:55:30 PM PST 24
Peak memory 216128 kb
Host smart-c5c12f17-564c-47cf-8a0b-06914bb6e354
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2985299060 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_kmac_err_chk.2985299060
Directory /workspace/10.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/10.rom_ctrl_max_throughput_chk.738916101
Short name T304
Test name
Test status
Simulation time 1912346073 ps
CPU time 8.37 seconds
Started Mar 07 12:55:13 PM PST 24
Finished Mar 07 12:55:22 PM PST 24
Peak memory 210720 kb
Host smart-277c742a-aabb-4482-8c93-4966587ba307
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=738916101 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_max_throughput_chk.738916101
Directory /workspace/10.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/10.rom_ctrl_smoke.3910929542
Short name T200
Test name
Test status
Simulation time 260531353 ps
CPU time 10.18 seconds
Started Mar 07 12:55:15 PM PST 24
Finished Mar 07 12:55:27 PM PST 24
Peak memory 213300 kb
Host smart-3d47558c-13ab-4945-aed5-a408a168c3c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3910929542 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_smoke.3910929542
Directory /workspace/10.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/10.rom_ctrl_stress_all.3010507607
Short name T259
Test name
Test status
Simulation time 1189493163 ps
CPU time 21.94 seconds
Started Mar 07 12:55:21 PM PST 24
Finished Mar 07 12:55:44 PM PST 24
Peak memory 214656 kb
Host smart-69474d47-fe3b-4cdf-b200-f60ae8132037
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3010507607 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 10.rom_ctrl_stress_all.3010507607
Directory /workspace/10.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/10.rom_ctrl_stress_all_with_rand_reset.3334082523
Short name T17
Test name
Test status
Simulation time 76205236016 ps
CPU time 766.43 seconds
Started Mar 07 12:55:22 PM PST 24
Finished Mar 07 01:08:09 PM PST 24
Peak memory 235400 kb
Host smart-c251118e-023c-4526-ba62-9302d314a441
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3334082523 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_stress_all_with_rand_reset.3334082523
Directory /workspace/10.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/11.rom_ctrl_alert_test.3000548608
Short name T197
Test name
Test status
Simulation time 85550743 ps
CPU time 4.28 seconds
Started Mar 07 12:55:33 PM PST 24
Finished Mar 07 12:55:40 PM PST 24
Peak memory 210828 kb
Host smart-cf94de7c-73ba-400b-8dd7-f52dad654642
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3000548608 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_alert_test.3000548608
Directory /workspace/11.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/11.rom_ctrl_corrupt_sig_fatal_chk.1457936970
Short name T303
Test name
Test status
Simulation time 115315406829 ps
CPU time 366.99 seconds
Started Mar 07 12:55:24 PM PST 24
Finished Mar 07 01:01:31 PM PST 24
Peak memory 211072 kb
Host smart-87648646-2059-4253-b530-d76f5115a882
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1457936970 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_
corrupt_sig_fatal_chk.1457936970
Directory /workspace/11.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/11.rom_ctrl_kmac_err_chk.4062637334
Short name T155
Test name
Test status
Simulation time 2215500218 ps
CPU time 16.88 seconds
Started Mar 07 12:55:23 PM PST 24
Finished Mar 07 12:55:40 PM PST 24
Peak memory 211288 kb
Host smart-cd73740b-2511-409e-b274-ff267fe05d16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4062637334 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_kmac_err_chk.4062637334
Directory /workspace/11.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/11.rom_ctrl_max_throughput_chk.2692862465
Short name T326
Test name
Test status
Simulation time 6147636072 ps
CPU time 14.48 seconds
Started Mar 07 12:55:26 PM PST 24
Finished Mar 07 12:55:41 PM PST 24
Peak memory 210780 kb
Host smart-9c6911d8-7f7f-465d-9e43-945925c71ff9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2692862465 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_max_throughput_chk.2692862465
Directory /workspace/11.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/11.rom_ctrl_smoke.3100522061
Short name T91
Test name
Test status
Simulation time 13422584756 ps
CPU time 33.62 seconds
Started Mar 07 12:55:22 PM PST 24
Finished Mar 07 12:55:56 PM PST 24
Peak memory 219068 kb
Host smart-75959f11-3724-40bc-a359-6f93baea6ba6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3100522061 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_smoke.3100522061
Directory /workspace/11.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/11.rom_ctrl_stress_all.261585087
Short name T268
Test name
Test status
Simulation time 2010597934 ps
CPU time 34.64 seconds
Started Mar 07 12:55:28 PM PST 24
Finished Mar 07 12:56:05 PM PST 24
Peak memory 214320 kb
Host smart-60eba6e5-2576-4d8f-9e49-e65240a2764b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=261585087 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 11.rom_ctrl_stress_all.261585087
Directory /workspace/11.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/12.rom_ctrl_alert_test.2552613280
Short name T314
Test name
Test status
Simulation time 346901981 ps
CPU time 4.09 seconds
Started Mar 07 12:55:36 PM PST 24
Finished Mar 07 12:55:41 PM PST 24
Peak memory 210744 kb
Host smart-d3a86d9b-9af6-42b2-8b4d-67928b3b09cc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2552613280 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_alert_test.2552613280
Directory /workspace/12.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/12.rom_ctrl_corrupt_sig_fatal_chk.1808190021
Short name T257
Test name
Test status
Simulation time 3826799406 ps
CPU time 122.98 seconds
Started Mar 07 12:55:18 PM PST 24
Finished Mar 07 12:57:22 PM PST 24
Peak memory 235908 kb
Host smart-c65cb78d-e428-40aa-af10-cea59f4a2207
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1808190021 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_
corrupt_sig_fatal_chk.1808190021
Directory /workspace/12.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/12.rom_ctrl_kmac_err_chk.4010678318
Short name T273
Test name
Test status
Simulation time 21196228095 ps
CPU time 25.64 seconds
Started Mar 07 12:55:19 PM PST 24
Finished Mar 07 12:55:45 PM PST 24
Peak memory 211620 kb
Host smart-ea766d8a-192d-4b11-9842-45f12f1969fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4010678318 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_kmac_err_chk.4010678318
Directory /workspace/12.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/12.rom_ctrl_max_throughput_chk.3807272008
Short name T334
Test name
Test status
Simulation time 7859286690 ps
CPU time 10.53 seconds
Started Mar 07 12:55:25 PM PST 24
Finished Mar 07 12:55:35 PM PST 24
Peak memory 210788 kb
Host smart-b6fcc6d5-cc52-4ebd-bc87-b1ff5954ca23
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3807272008 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_max_throughput_chk.3807272008
Directory /workspace/12.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/12.rom_ctrl_smoke.2872223932
Short name T210
Test name
Test status
Simulation time 1706954581 ps
CPU time 14.8 seconds
Started Mar 07 12:55:28 PM PST 24
Finished Mar 07 12:55:44 PM PST 24
Peak memory 212644 kb
Host smart-decd8140-77d7-4c1e-8391-b581ac1c3c4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2872223932 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_smoke.2872223932
Directory /workspace/12.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/12.rom_ctrl_stress_all.2015615268
Short name T292
Test name
Test status
Simulation time 1634179222 ps
CPU time 20.47 seconds
Started Mar 07 12:55:25 PM PST 24
Finished Mar 07 12:55:52 PM PST 24
Peak memory 213152 kb
Host smart-0aa0c583-14af-4d27-b156-19d6ab50e1c7
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2015615268 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 12.rom_ctrl_stress_all.2015615268
Directory /workspace/12.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/13.rom_ctrl_alert_test.2423967231
Short name T37
Test name
Test status
Simulation time 1472444036 ps
CPU time 13.61 seconds
Started Mar 07 12:55:23 PM PST 24
Finished Mar 07 12:55:37 PM PST 24
Peak memory 210864 kb
Host smart-0dfa7326-6fd1-4827-befa-ae21134aaf9e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2423967231 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_alert_test.2423967231
Directory /workspace/13.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/13.rom_ctrl_corrupt_sig_fatal_chk.2438819639
Short name T360
Test name
Test status
Simulation time 123728827539 ps
CPU time 232.18 seconds
Started Mar 07 12:55:17 PM PST 24
Finished Mar 07 12:59:11 PM PST 24
Peak memory 225856 kb
Host smart-2d80d898-64e3-4291-a939-c33188399259
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2438819639 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_
corrupt_sig_fatal_chk.2438819639
Directory /workspace/13.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/13.rom_ctrl_kmac_err_chk.2172872436
Short name T192
Test name
Test status
Simulation time 1314168321 ps
CPU time 18.4 seconds
Started Mar 07 12:55:14 PM PST 24
Finished Mar 07 12:55:33 PM PST 24
Peak memory 211308 kb
Host smart-cf96dd35-f5f5-4ccc-afc6-e07db5dfcafd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2172872436 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_kmac_err_chk.2172872436
Directory /workspace/13.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/13.rom_ctrl_max_throughput_chk.2384593619
Short name T199
Test name
Test status
Simulation time 2273080125 ps
CPU time 8.85 seconds
Started Mar 07 12:55:23 PM PST 24
Finished Mar 07 12:55:32 PM PST 24
Peak memory 210892 kb
Host smart-9a307957-55a0-4708-aa91-8bd0aafe420d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2384593619 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_max_throughput_chk.2384593619
Directory /workspace/13.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/13.rom_ctrl_smoke.2625790508
Short name T183
Test name
Test status
Simulation time 69206678179 ps
CPU time 31.77 seconds
Started Mar 07 12:55:18 PM PST 24
Finished Mar 07 12:55:51 PM PST 24
Peak memory 213412 kb
Host smart-98bf4c57-bf52-4747-a292-98a2ea007e23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2625790508 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_smoke.2625790508
Directory /workspace/13.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/13.rom_ctrl_stress_all.604681785
Short name T293
Test name
Test status
Simulation time 28521775297 ps
CPU time 19.86 seconds
Started Mar 07 12:55:20 PM PST 24
Finished Mar 07 12:55:40 PM PST 24
Peak memory 214684 kb
Host smart-a323921a-43be-4588-a8e0-c81f9b7f2b84
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=604681785 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 13.rom_ctrl_stress_all.604681785
Directory /workspace/13.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/14.rom_ctrl_alert_test.3632624037
Short name T216
Test name
Test status
Simulation time 129316938 ps
CPU time 4.95 seconds
Started Mar 07 12:55:44 PM PST 24
Finished Mar 07 12:55:49 PM PST 24
Peak memory 210932 kb
Host smart-b50b0895-c042-4508-b2f3-67de91389f35
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3632624037 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_alert_test.3632624037
Directory /workspace/14.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/14.rom_ctrl_kmac_err_chk.2090919136
Short name T270
Test name
Test status
Simulation time 2304959720 ps
CPU time 17.12 seconds
Started Mar 07 12:55:30 PM PST 24
Finished Mar 07 12:55:49 PM PST 24
Peak memory 211444 kb
Host smart-61ff7624-e9be-4dc3-a804-3e761b0b0edf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2090919136 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_kmac_err_chk.2090919136
Directory /workspace/14.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/14.rom_ctrl_max_throughput_chk.2869533630
Short name T215
Test name
Test status
Simulation time 528117724 ps
CPU time 9.08 seconds
Started Mar 07 12:55:24 PM PST 24
Finished Mar 07 12:55:33 PM PST 24
Peak memory 210704 kb
Host smart-c793e5da-4848-41d3-bc96-d3d69506c0c6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2869533630 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_max_throughput_chk.2869533630
Directory /workspace/14.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/14.rom_ctrl_smoke.3882993207
Short name T134
Test name
Test status
Simulation time 2980991517 ps
CPU time 27.52 seconds
Started Mar 07 12:55:14 PM PST 24
Finished Mar 07 12:55:42 PM PST 24
Peak memory 212532 kb
Host smart-9ed0fa56-16ba-44c0-8571-9ccd2bf7e0e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3882993207 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_smoke.3882993207
Directory /workspace/14.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/14.rom_ctrl_stress_all.4093341755
Short name T310
Test name
Test status
Simulation time 7856316592 ps
CPU time 20.63 seconds
Started Mar 07 12:55:16 PM PST 24
Finished Mar 07 12:55:37 PM PST 24
Peak memory 213884 kb
Host smart-d06bc672-fa3c-4af7-8ff6-11003c4a0372
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4093341755 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 14.rom_ctrl_stress_all.4093341755
Directory /workspace/14.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/15.rom_ctrl_alert_test.4149572902
Short name T265
Test name
Test status
Simulation time 1084919354 ps
CPU time 11.22 seconds
Started Mar 07 12:55:17 PM PST 24
Finished Mar 07 12:55:30 PM PST 24
Peak memory 210928 kb
Host smart-86625408-17ba-4eff-8a67-e22472fddfd1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4149572902 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_alert_test.4149572902
Directory /workspace/15.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/15.rom_ctrl_corrupt_sig_fatal_chk.561678087
Short name T19
Test name
Test status
Simulation time 328373466061 ps
CPU time 304.29 seconds
Started Mar 07 12:55:28 PM PST 24
Finished Mar 07 01:00:35 PM PST 24
Peak memory 236148 kb
Host smart-3e736bdb-53ae-4cd2-bd66-37579c71f4d7
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=561678087 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_c
orrupt_sig_fatal_chk.561678087
Directory /workspace/15.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/15.rom_ctrl_kmac_err_chk.1316562564
Short name T29
Test name
Test status
Simulation time 168652318 ps
CPU time 9.51 seconds
Started Mar 07 12:55:31 PM PST 24
Finished Mar 07 12:55:44 PM PST 24
Peak memory 211496 kb
Host smart-34c25c97-469a-4d9d-84c4-bd126ff0d852
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1316562564 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_kmac_err_chk.1316562564
Directory /workspace/15.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/15.rom_ctrl_max_throughput_chk.3747665176
Short name T282
Test name
Test status
Simulation time 274987521 ps
CPU time 6.42 seconds
Started Mar 07 12:55:25 PM PST 24
Finished Mar 07 12:55:32 PM PST 24
Peak memory 210764 kb
Host smart-efc6d449-c271-4496-a7f1-a3b72887a7dd
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3747665176 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_max_throughput_chk.3747665176
Directory /workspace/15.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/15.rom_ctrl_smoke.842644610
Short name T133
Test name
Test status
Simulation time 2768937324 ps
CPU time 17.8 seconds
Started Mar 07 12:55:27 PM PST 24
Finished Mar 07 12:55:45 PM PST 24
Peak memory 212716 kb
Host smart-67316385-2ed0-419f-9f24-cc2a4032c145
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=842644610 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_smoke.842644610
Directory /workspace/15.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/15.rom_ctrl_stress_all.652819057
Short name T254
Test name
Test status
Simulation time 852101055 ps
CPU time 14.25 seconds
Started Mar 07 12:55:19 PM PST 24
Finished Mar 07 12:55:34 PM PST 24
Peak memory 211544 kb
Host smart-6afc8811-17af-4e60-9a86-690391ba2507
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=652819057 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 15.rom_ctrl_stress_all.652819057
Directory /workspace/15.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/16.rom_ctrl_alert_test.1869877424
Short name T78
Test name
Test status
Simulation time 6197185583 ps
CPU time 12.89 seconds
Started Mar 07 12:55:25 PM PST 24
Finished Mar 07 12:55:38 PM PST 24
Peak memory 210944 kb
Host smart-0a80d78c-7e49-4a9c-ade0-8f8afd142783
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1869877424 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_alert_test.1869877424
Directory /workspace/16.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/16.rom_ctrl_corrupt_sig_fatal_chk.4196704063
Short name T229
Test name
Test status
Simulation time 29004089990 ps
CPU time 298.41 seconds
Started Mar 07 12:55:19 PM PST 24
Finished Mar 07 01:00:18 PM PST 24
Peak memory 224164 kb
Host smart-3f148615-59a4-4a1a-b113-bf240fad6118
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4196704063 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_
corrupt_sig_fatal_chk.4196704063
Directory /workspace/16.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/16.rom_ctrl_kmac_err_chk.24318886
Short name T219
Test name
Test status
Simulation time 2955532879 ps
CPU time 26.84 seconds
Started Mar 07 12:55:30 PM PST 24
Finished Mar 07 12:55:59 PM PST 24
Peak memory 211428 kb
Host smart-f26f49bb-a408-43ed-85d7-20a27692ea94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=24318886 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_kmac_err_chk.24318886
Directory /workspace/16.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/16.rom_ctrl_max_throughput_chk.2505122141
Short name T25
Test name
Test status
Simulation time 28043126289 ps
CPU time 15.97 seconds
Started Mar 07 12:55:32 PM PST 24
Finished Mar 07 12:55:52 PM PST 24
Peak memory 210800 kb
Host smart-df5a38d3-6c53-41a8-8547-74f8b224071c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2505122141 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_max_throughput_chk.2505122141
Directory /workspace/16.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/16.rom_ctrl_smoke.2816014806
Short name T235
Test name
Test status
Simulation time 2513398175 ps
CPU time 33.06 seconds
Started Mar 07 12:55:32 PM PST 24
Finished Mar 07 12:56:09 PM PST 24
Peak memory 212436 kb
Host smart-ce2ab1d3-5b48-4aa0-af85-9226190b71bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2816014806 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_smoke.2816014806
Directory /workspace/16.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/16.rom_ctrl_stress_all.663633554
Short name T48
Test name
Test status
Simulation time 7314743309 ps
CPU time 59.83 seconds
Started Mar 07 12:55:10 PM PST 24
Finished Mar 07 12:56:10 PM PST 24
Peak memory 215952 kb
Host smart-b541da20-6503-48fa-b0f8-88d2684882d9
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=663633554 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 16.rom_ctrl_stress_all.663633554
Directory /workspace/16.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/17.rom_ctrl_alert_test.3353471266
Short name T289
Test name
Test status
Simulation time 396514942 ps
CPU time 4.16 seconds
Started Mar 07 12:55:33 PM PST 24
Finished Mar 07 12:55:39 PM PST 24
Peak memory 210792 kb
Host smart-5e23b074-2b81-4fe5-9c7c-d426c29f48eb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3353471266 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_alert_test.3353471266
Directory /workspace/17.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/17.rom_ctrl_corrupt_sig_fatal_chk.1378970460
Short name T7
Test name
Test status
Simulation time 56363263422 ps
CPU time 332.21 seconds
Started Mar 07 12:55:24 PM PST 24
Finished Mar 07 01:00:57 PM PST 24
Peak memory 228276 kb
Host smart-9d7b4ca2-4585-446f-8d23-02fd83eb400c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1378970460 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_
corrupt_sig_fatal_chk.1378970460
Directory /workspace/17.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/17.rom_ctrl_kmac_err_chk.2685439063
Short name T187
Test name
Test status
Simulation time 8917186105 ps
CPU time 22.9 seconds
Started Mar 07 12:55:20 PM PST 24
Finished Mar 07 12:55:43 PM PST 24
Peak memory 211764 kb
Host smart-1f82ab4d-b790-478d-b3cf-0088bcb9547a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2685439063 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_kmac_err_chk.2685439063
Directory /workspace/17.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/17.rom_ctrl_max_throughput_chk.3397214858
Short name T6
Test name
Test status
Simulation time 1434396150 ps
CPU time 13.77 seconds
Started Mar 07 12:55:33 PM PST 24
Finished Mar 07 12:55:49 PM PST 24
Peak memory 210720 kb
Host smart-991d5835-d0df-4299-a679-940236228196
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3397214858 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_max_throughput_chk.3397214858
Directory /workspace/17.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/17.rom_ctrl_smoke.3517569923
Short name T88
Test name
Test status
Simulation time 2243707823 ps
CPU time 26.62 seconds
Started Mar 07 12:55:20 PM PST 24
Finished Mar 07 12:55:47 PM PST 24
Peak memory 212860 kb
Host smart-cd9a8900-7ee0-4978-9098-94cc4baa5903
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3517569923 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_smoke.3517569923
Directory /workspace/17.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/17.rom_ctrl_stress_all.2534180947
Short name T340
Test name
Test status
Simulation time 24807494213 ps
CPU time 50.92 seconds
Started Mar 07 12:55:24 PM PST 24
Finished Mar 07 12:56:22 PM PST 24
Peak memory 216688 kb
Host smart-0b036c9d-6dfb-4bdd-a209-ca06ca05c8a0
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2534180947 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 17.rom_ctrl_stress_all.2534180947
Directory /workspace/17.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/18.rom_ctrl_alert_test.3399201953
Short name T143
Test name
Test status
Simulation time 1626824302 ps
CPU time 13.77 seconds
Started Mar 07 12:55:29 PM PST 24
Finished Mar 07 12:55:45 PM PST 24
Peak memory 210828 kb
Host smart-d6f604d7-0294-479c-bbe9-c53285eeba5b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3399201953 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_alert_test.3399201953
Directory /workspace/18.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/18.rom_ctrl_corrupt_sig_fatal_chk.82978998
Short name T220
Test name
Test status
Simulation time 66800675062 ps
CPU time 128.84 seconds
Started Mar 07 12:55:27 PM PST 24
Finished Mar 07 12:57:36 PM PST 24
Peak memory 237308 kb
Host smart-8ecaa836-8ce3-4bf1-8825-4996be455d0a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82978998 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_
sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_co
rrupt_sig_fatal_chk.82978998
Directory /workspace/18.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/18.rom_ctrl_kmac_err_chk.2494355088
Short name T249
Test name
Test status
Simulation time 3343509258 ps
CPU time 29.08 seconds
Started Mar 07 12:55:24 PM PST 24
Finished Mar 07 12:55:53 PM PST 24
Peak memory 211908 kb
Host smart-5677fb66-be61-469f-9ca5-d40b5c053316
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2494355088 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_kmac_err_chk.2494355088
Directory /workspace/18.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/18.rom_ctrl_max_throughput_chk.382247619
Short name T47
Test name
Test status
Simulation time 6290463834 ps
CPU time 12.68 seconds
Started Mar 07 12:55:28 PM PST 24
Finished Mar 07 12:55:43 PM PST 24
Peak memory 210808 kb
Host smart-7a7b887c-2736-4354-bb8d-3653a8d23c41
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=382247619 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_max_throughput_chk.382247619
Directory /workspace/18.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/18.rom_ctrl_smoke.1763743683
Short name T246
Test name
Test status
Simulation time 761006681 ps
CPU time 9.99 seconds
Started Mar 07 12:55:33 PM PST 24
Finished Mar 07 12:55:46 PM PST 24
Peak memory 213108 kb
Host smart-f79fc8cf-bf62-4863-bd41-67349c79b38a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1763743683 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_smoke.1763743683
Directory /workspace/18.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/18.rom_ctrl_stress_all.457507046
Short name T126
Test name
Test status
Simulation time 455802257 ps
CPU time 26.82 seconds
Started Mar 07 12:55:27 PM PST 24
Finished Mar 07 12:55:54 PM PST 24
Peak memory 214680 kb
Host smart-e3eb3dac-c615-4b69-b9f4-380f20bcd934
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=457507046 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 18.rom_ctrl_stress_all.457507046
Directory /workspace/18.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/19.rom_ctrl_alert_test.1853810521
Short name T77
Test name
Test status
Simulation time 1121104806 ps
CPU time 8.11 seconds
Started Mar 07 12:55:35 PM PST 24
Finished Mar 07 12:55:44 PM PST 24
Peak memory 210884 kb
Host smart-486d599a-67c1-4886-9ae1-d04010c81ca4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1853810521 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_alert_test.1853810521
Directory /workspace/19.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/19.rom_ctrl_corrupt_sig_fatal_chk.4020166519
Short name T190
Test name
Test status
Simulation time 2412923209 ps
CPU time 155.96 seconds
Started Mar 07 12:55:14 PM PST 24
Finished Mar 07 12:57:51 PM PST 24
Peak memory 232612 kb
Host smart-bbaf8679-5d59-404a-abd4-3fc712b6a652
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4020166519 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_
corrupt_sig_fatal_chk.4020166519
Directory /workspace/19.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/19.rom_ctrl_kmac_err_chk.1292615633
Short name T222
Test name
Test status
Simulation time 1878414823 ps
CPU time 20.87 seconds
Started Mar 07 12:55:32 PM PST 24
Finished Mar 07 12:55:56 PM PST 24
Peak memory 211396 kb
Host smart-e0979de1-79fe-4adc-b307-f383cb1877c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1292615633 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_kmac_err_chk.1292615633
Directory /workspace/19.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/19.rom_ctrl_max_throughput_chk.594328237
Short name T315
Test name
Test status
Simulation time 390814622 ps
CPU time 5.77 seconds
Started Mar 07 12:55:20 PM PST 24
Finished Mar 07 12:55:26 PM PST 24
Peak memory 210736 kb
Host smart-4d69b9f6-30cc-4b32-aa1f-7cd13ab3557e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=594328237 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_max_throughput_chk.594328237
Directory /workspace/19.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/19.rom_ctrl_smoke.1755019811
Short name T179
Test name
Test status
Simulation time 10893681579 ps
CPU time 32.61 seconds
Started Mar 07 12:55:26 PM PST 24
Finished Mar 07 12:55:58 PM PST 24
Peak memory 212652 kb
Host smart-337e4d23-eeeb-42df-b0ef-5212329e2674
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1755019811 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_smoke.1755019811
Directory /workspace/19.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/19.rom_ctrl_stress_all.2391495735
Short name T136
Test name
Test status
Simulation time 3835498264 ps
CPU time 24.54 seconds
Started Mar 07 12:55:30 PM PST 24
Finished Mar 07 12:55:56 PM PST 24
Peak memory 216124 kb
Host smart-327655f4-d952-4e4e-b627-57a0208dc785
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2391495735 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 19.rom_ctrl_stress_all.2391495735
Directory /workspace/19.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/2.rom_ctrl_alert_test.1725432544
Short name T354
Test name
Test status
Simulation time 659469154 ps
CPU time 9.11 seconds
Started Mar 07 12:55:02 PM PST 24
Finished Mar 07 12:55:12 PM PST 24
Peak memory 210888 kb
Host smart-0cdc3c19-099b-46a7-9a42-630c8c31f073
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1725432544 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_alert_test.1725432544
Directory /workspace/2.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/2.rom_ctrl_corrupt_sig_fatal_chk.146523283
Short name T332
Test name
Test status
Simulation time 5689793872 ps
CPU time 80.13 seconds
Started Mar 07 12:55:14 PM PST 24
Finished Mar 07 12:56:35 PM PST 24
Peak memory 211156 kb
Host smart-c4ea241e-5a41-45fc-9071-5a6f50bec4db
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=146523283 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_co
rrupt_sig_fatal_chk.146523283
Directory /workspace/2.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/2.rom_ctrl_kmac_err_chk.3900294494
Short name T221
Test name
Test status
Simulation time 857359321 ps
CPU time 15.29 seconds
Started Mar 07 12:55:17 PM PST 24
Finished Mar 07 12:55:34 PM PST 24
Peak memory 211340 kb
Host smart-341a5fd9-eda8-437f-bc7d-b7ad65cb14db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3900294494 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_kmac_err_chk.3900294494
Directory /workspace/2.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/2.rom_ctrl_max_throughput_chk.2679331987
Short name T328
Test name
Test status
Simulation time 2028539707 ps
CPU time 16.57 seconds
Started Mar 07 12:54:59 PM PST 24
Finished Mar 07 12:55:16 PM PST 24
Peak memory 210752 kb
Host smart-4497c125-093a-4aee-95d8-6d070064bb9e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2679331987 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_max_throughput_chk.2679331987
Directory /workspace/2.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/2.rom_ctrl_sec_cm.2077813960
Short name T39
Test name
Test status
Simulation time 1546069515 ps
CPU time 54.54 seconds
Started Mar 07 12:55:05 PM PST 24
Finished Mar 07 12:56:00 PM PST 24
Peak memory 230840 kb
Host smart-67c92e7c-bbe1-4651-89fa-e314cac03cf1
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2077813960 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_sec_cm.2077813960
Directory /workspace/2.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/2.rom_ctrl_smoke.3596786263
Short name T358
Test name
Test status
Simulation time 7910172844 ps
CPU time 20.71 seconds
Started Mar 07 12:55:26 PM PST 24
Finished Mar 07 12:55:47 PM PST 24
Peak memory 213488 kb
Host smart-e18799ae-a227-43ed-91ae-389db42897ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3596786263 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_smoke.3596786263
Directory /workspace/2.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/2.rom_ctrl_stress_all.380909118
Short name T129
Test name
Test status
Simulation time 13106921167 ps
CPU time 106.57 seconds
Started Mar 07 12:55:08 PM PST 24
Finished Mar 07 12:56:55 PM PST 24
Peak memory 216696 kb
Host smart-d01b1022-e4df-4fce-a139-aa4a713767de
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=380909118 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 2.rom_ctrl_stress_all.380909118
Directory /workspace/2.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/2.rom_ctrl_stress_all_with_rand_reset.2480313230
Short name T288
Test name
Test status
Simulation time 48248161134 ps
CPU time 472.38 seconds
Started Mar 07 12:55:18 PM PST 24
Finished Mar 07 01:03:12 PM PST 24
Peak memory 235560 kb
Host smart-f07988fa-b522-4fcb-8b61-754eb61d9cf5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2480313230 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_stress_all_with_rand_reset.2480313230
Directory /workspace/2.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.rom_ctrl_alert_test.586003793
Short name T159
Test name
Test status
Simulation time 383846766 ps
CPU time 6.45 seconds
Started Mar 07 12:55:18 PM PST 24
Finished Mar 07 12:55:26 PM PST 24
Peak memory 210852 kb
Host smart-71dda5e4-1d32-4e39-9ac3-f27e8a9040e4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=586003793 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_alert_test.586003793
Directory /workspace/20.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/20.rom_ctrl_corrupt_sig_fatal_chk.2078126033
Short name T142
Test name
Test status
Simulation time 2550472687 ps
CPU time 85.71 seconds
Started Mar 07 12:55:18 PM PST 24
Finished Mar 07 12:56:45 PM PST 24
Peak memory 212088 kb
Host smart-f18d3be3-53bf-4e0d-a7f8-ba2ac81cfeb5
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2078126033 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_
corrupt_sig_fatal_chk.2078126033
Directory /workspace/20.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/20.rom_ctrl_max_throughput_chk.3896141069
Short name T24
Test name
Test status
Simulation time 482887272 ps
CPU time 8.33 seconds
Started Mar 07 12:55:23 PM PST 24
Finished Mar 07 12:55:31 PM PST 24
Peak memory 210716 kb
Host smart-782dc414-dc86-4faf-bb01-9936ff0be52c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3896141069 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_max_throughput_chk.3896141069
Directory /workspace/20.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/20.rom_ctrl_smoke.363600811
Short name T335
Test name
Test status
Simulation time 17523916010 ps
CPU time 36.33 seconds
Started Mar 07 12:55:36 PM PST 24
Finished Mar 07 12:56:13 PM PST 24
Peak memory 213504 kb
Host smart-178d0b24-a068-4175-9804-38a36fe4d65c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=363600811 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_smoke.363600811
Directory /workspace/20.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/20.rom_ctrl_stress_all.1924589672
Short name T281
Test name
Test status
Simulation time 8369954903 ps
CPU time 97.13 seconds
Started Mar 07 12:55:27 PM PST 24
Finished Mar 07 12:57:05 PM PST 24
Peak memory 217112 kb
Host smart-d87031e0-aab7-4792-ba74-6be6e644fe02
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1924589672 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 20.rom_ctrl_stress_all.1924589672
Directory /workspace/20.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/21.rom_ctrl_alert_test.1826374911
Short name T76
Test name
Test status
Simulation time 1782300136 ps
CPU time 7.29 seconds
Started Mar 07 12:55:42 PM PST 24
Finished Mar 07 12:55:50 PM PST 24
Peak memory 210860 kb
Host smart-cfba6b4c-8824-4b4c-aaa4-8a738164c5bd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1826374911 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_alert_test.1826374911
Directory /workspace/21.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/21.rom_ctrl_corrupt_sig_fatal_chk.1972144311
Short name T184
Test name
Test status
Simulation time 86877228065 ps
CPU time 418.48 seconds
Started Mar 07 12:55:19 PM PST 24
Finished Mar 07 01:02:18 PM PST 24
Peak memory 224272 kb
Host smart-26274be4-55d6-4fe1-83bd-baa45e16743b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1972144311 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_
corrupt_sig_fatal_chk.1972144311
Directory /workspace/21.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/21.rom_ctrl_kmac_err_chk.505904294
Short name T240
Test name
Test status
Simulation time 2563265209 ps
CPU time 17.29 seconds
Started Mar 07 12:55:42 PM PST 24
Finished Mar 07 12:55:59 PM PST 24
Peak memory 211324 kb
Host smart-502e2db2-e060-4cd6-bea6-08feea5bd619
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=505904294 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_kmac_err_chk.505904294
Directory /workspace/21.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/21.rom_ctrl_max_throughput_chk.1148632409
Short name T298
Test name
Test status
Simulation time 2850274611 ps
CPU time 13.61 seconds
Started Mar 07 12:55:46 PM PST 24
Finished Mar 07 12:56:00 PM PST 24
Peak memory 210808 kb
Host smart-c0b27885-3374-4bf9-8757-ec4d8c26c9dc
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1148632409 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_max_throughput_chk.1148632409
Directory /workspace/21.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/21.rom_ctrl_smoke.658366435
Short name T214
Test name
Test status
Simulation time 2580556932 ps
CPU time 28.76 seconds
Started Mar 07 12:55:18 PM PST 24
Finished Mar 07 12:55:47 PM PST 24
Peak memory 212620 kb
Host smart-6896691d-be93-489a-a8ad-9d5632d8c415
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=658366435 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_smoke.658366435
Directory /workspace/21.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/21.rom_ctrl_stress_all.615663742
Short name T243
Test name
Test status
Simulation time 34268886939 ps
CPU time 83.71 seconds
Started Mar 07 12:55:42 PM PST 24
Finished Mar 07 12:57:05 PM PST 24
Peak memory 217456 kb
Host smart-fe2e60a6-86cf-45c1-82d0-398ec83a1142
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=615663742 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 21.rom_ctrl_stress_all.615663742
Directory /workspace/21.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/22.rom_ctrl_alert_test.1127622244
Short name T262
Test name
Test status
Simulation time 2521760813 ps
CPU time 11.65 seconds
Started Mar 07 12:55:39 PM PST 24
Finished Mar 07 12:55:50 PM PST 24
Peak memory 210896 kb
Host smart-b49df9ac-fcb6-40d0-9ae8-bec07a8f3d35
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1127622244 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_alert_test.1127622244
Directory /workspace/22.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/22.rom_ctrl_corrupt_sig_fatal_chk.804354866
Short name T359
Test name
Test status
Simulation time 395130586765 ps
CPU time 383.32 seconds
Started Mar 07 12:55:50 PM PST 24
Finished Mar 07 01:02:13 PM PST 24
Peak memory 239872 kb
Host smart-94664568-14eb-49e0-bbc6-e3024373d7d4
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=804354866 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_c
orrupt_sig_fatal_chk.804354866
Directory /workspace/22.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/22.rom_ctrl_kmac_err_chk.416519222
Short name T252
Test name
Test status
Simulation time 6514544119 ps
CPU time 28.52 seconds
Started Mar 07 12:55:30 PM PST 24
Finished Mar 07 12:56:00 PM PST 24
Peak memory 210912 kb
Host smart-02966729-9900-44a0-8e70-6715f300647f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=416519222 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_kmac_err_chk.416519222
Directory /workspace/22.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/22.rom_ctrl_max_throughput_chk.3288503896
Short name T346
Test name
Test status
Simulation time 1300256604 ps
CPU time 5.35 seconds
Started Mar 07 12:55:30 PM PST 24
Finished Mar 07 12:55:37 PM PST 24
Peak memory 210728 kb
Host smart-539e832f-e28b-46ca-a1ef-c57d4fd4d42f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3288503896 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_max_throughput_chk.3288503896
Directory /workspace/22.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/22.rom_ctrl_smoke.115685518
Short name T294
Test name
Test status
Simulation time 757110497 ps
CPU time 10.01 seconds
Started Mar 07 12:55:37 PM PST 24
Finished Mar 07 12:55:48 PM PST 24
Peak memory 213536 kb
Host smart-ffe76c74-1232-4f30-b9b0-b875a9a0ba56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=115685518 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_smoke.115685518
Directory /workspace/22.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/22.rom_ctrl_stress_all.3667007868
Short name T195
Test name
Test status
Simulation time 2455413302 ps
CPU time 38.22 seconds
Started Mar 07 12:55:33 PM PST 24
Finished Mar 07 12:56:14 PM PST 24
Peak memory 218948 kb
Host smart-873cd1a4-44e2-4321-8f01-5eca04fb1ae4
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3667007868 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 22.rom_ctrl_stress_all.3667007868
Directory /workspace/22.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/23.rom_ctrl_corrupt_sig_fatal_chk.3860821510
Short name T171
Test name
Test status
Simulation time 28111053638 ps
CPU time 125.01 seconds
Started Mar 07 12:55:32 PM PST 24
Finished Mar 07 12:57:40 PM PST 24
Peak memory 235552 kb
Host smart-69917f11-fbc6-418a-93c5-4279c5906e44
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3860821510 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_
corrupt_sig_fatal_chk.3860821510
Directory /workspace/23.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/23.rom_ctrl_kmac_err_chk.1815465228
Short name T172
Test name
Test status
Simulation time 692059234 ps
CPU time 9.22 seconds
Started Mar 07 12:55:37 PM PST 24
Finished Mar 07 12:55:47 PM PST 24
Peak memory 210928 kb
Host smart-274187bb-41cd-4853-9359-bc46d0d2ca32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1815465228 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_kmac_err_chk.1815465228
Directory /workspace/23.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/23.rom_ctrl_max_throughput_chk.1262587683
Short name T146
Test name
Test status
Simulation time 4134592270 ps
CPU time 11.41 seconds
Started Mar 07 12:55:28 PM PST 24
Finished Mar 07 12:55:42 PM PST 24
Peak memory 210796 kb
Host smart-ccb5f712-c898-4e04-9399-d60e7fce915f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1262587683 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_max_throughput_chk.1262587683
Directory /workspace/23.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/23.rom_ctrl_smoke.2872510994
Short name T18
Test name
Test status
Simulation time 4779790945 ps
CPU time 26.82 seconds
Started Mar 07 12:55:45 PM PST 24
Finished Mar 07 12:56:17 PM PST 24
Peak memory 213004 kb
Host smart-61e68b2e-c120-4571-85c5-f32d0620fffa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2872510994 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_smoke.2872510994
Directory /workspace/23.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/23.rom_ctrl_stress_all.1482068126
Short name T58
Test name
Test status
Simulation time 11276740533 ps
CPU time 61.61 seconds
Started Mar 07 12:55:32 PM PST 24
Finished Mar 07 12:56:37 PM PST 24
Peak memory 218996 kb
Host smart-9355e1a2-70a0-4e19-ab4d-adcb8cb87a0d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1482068126 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 23.rom_ctrl_stress_all.1482068126
Directory /workspace/23.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/24.rom_ctrl_alert_test.939887049
Short name T275
Test name
Test status
Simulation time 1631539988 ps
CPU time 13.61 seconds
Started Mar 07 12:55:41 PM PST 24
Finished Mar 07 12:55:54 PM PST 24
Peak memory 210800 kb
Host smart-6e14ecf4-72e3-4de5-a620-bf243b5d2418
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=939887049 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_alert_test.939887049
Directory /workspace/24.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/24.rom_ctrl_kmac_err_chk.310288401
Short name T277
Test name
Test status
Simulation time 5116959305 ps
CPU time 18.12 seconds
Started Mar 07 12:55:30 PM PST 24
Finished Mar 07 12:55:49 PM PST 24
Peak memory 211688 kb
Host smart-6de841a8-dbd7-4847-b4ea-8cdb53d80b76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=310288401 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_kmac_err_chk.310288401
Directory /workspace/24.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/24.rom_ctrl_max_throughput_chk.1223451557
Short name T176
Test name
Test status
Simulation time 428696213 ps
CPU time 8.1 seconds
Started Mar 07 12:55:38 PM PST 24
Finished Mar 07 12:55:46 PM PST 24
Peak memory 210748 kb
Host smart-1ce0bb75-ea52-4a42-9c57-d2799c2ace64
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1223451557 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_max_throughput_chk.1223451557
Directory /workspace/24.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/24.rom_ctrl_smoke.4118051663
Short name T255
Test name
Test status
Simulation time 6884902690 ps
CPU time 20.4 seconds
Started Mar 07 12:55:40 PM PST 24
Finished Mar 07 12:56:01 PM PST 24
Peak memory 213448 kb
Host smart-f7ec8482-40b5-433a-9d93-b4a12a8ff1e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4118051663 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_smoke.4118051663
Directory /workspace/24.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/24.rom_ctrl_stress_all.4092063721
Short name T3
Test name
Test status
Simulation time 728284102 ps
CPU time 12.26 seconds
Started Mar 07 12:55:28 PM PST 24
Finished Mar 07 12:55:41 PM PST 24
Peak memory 213476 kb
Host smart-62320947-7184-4a18-9070-5f1a6461f31f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4092063721 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 24.rom_ctrl_stress_all.4092063721
Directory /workspace/24.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/25.rom_ctrl_alert_test.2341320864
Short name T241
Test name
Test status
Simulation time 167765905 ps
CPU time 5.26 seconds
Started Mar 07 12:55:50 PM PST 24
Finished Mar 07 12:55:55 PM PST 24
Peak memory 210860 kb
Host smart-6cb3155d-54de-49b2-a155-023d8907d82b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2341320864 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_alert_test.2341320864
Directory /workspace/25.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/25.rom_ctrl_corrupt_sig_fatal_chk.2845102606
Short name T128
Test name
Test status
Simulation time 5541170296 ps
CPU time 112.95 seconds
Started Mar 07 12:55:29 PM PST 24
Finished Mar 07 12:57:24 PM PST 24
Peak memory 212272 kb
Host smart-a928827f-1a53-4654-a340-61069afc197d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2845102606 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_
corrupt_sig_fatal_chk.2845102606
Directory /workspace/25.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/25.rom_ctrl_kmac_err_chk.3575112468
Short name T233
Test name
Test status
Simulation time 175718434 ps
CPU time 9.32 seconds
Started Mar 07 12:55:42 PM PST 24
Finished Mar 07 12:55:51 PM PST 24
Peak memory 211336 kb
Host smart-feb98db8-e2bf-45fb-a150-dcc9ba1e5d81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3575112468 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_kmac_err_chk.3575112468
Directory /workspace/25.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/25.rom_ctrl_max_throughput_chk.2917761380
Short name T263
Test name
Test status
Simulation time 4025845278 ps
CPU time 17.18 seconds
Started Mar 07 12:55:25 PM PST 24
Finished Mar 07 12:55:42 PM PST 24
Peak memory 210788 kb
Host smart-3b613b14-42b0-42d3-aae7-8b421e769517
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2917761380 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_max_throughput_chk.2917761380
Directory /workspace/25.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/25.rom_ctrl_smoke.2329831836
Short name T90
Test name
Test status
Simulation time 9748554460 ps
CPU time 28.91 seconds
Started Mar 07 12:55:37 PM PST 24
Finished Mar 07 12:56:06 PM PST 24
Peak memory 212960 kb
Host smart-321750ac-80fc-47b4-b25d-ac7c78431234
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2329831836 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_smoke.2329831836
Directory /workspace/25.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/25.rom_ctrl_stress_all.2010135377
Short name T274
Test name
Test status
Simulation time 2407372737 ps
CPU time 17.15 seconds
Started Mar 07 12:55:32 PM PST 24
Finished Mar 07 12:55:52 PM PST 24
Peak memory 219048 kb
Host smart-96d4ae30-fc30-4ac7-8b1a-e4106c29a2d9
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2010135377 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 25.rom_ctrl_stress_all.2010135377
Directory /workspace/25.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/25.rom_ctrl_stress_all_with_rand_reset.3709618723
Short name T52
Test name
Test status
Simulation time 61533043440 ps
CPU time 544.96 seconds
Started Mar 07 12:55:35 PM PST 24
Finished Mar 07 01:04:42 PM PST 24
Peak memory 229104 kb
Host smart-85a4bec2-8e3d-4da4-b0b2-31ec98a99604
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3709618723 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_stress_all_with_rand_reset.3709618723
Directory /workspace/25.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/26.rom_ctrl_alert_test.4000958763
Short name T322
Test name
Test status
Simulation time 3779849219 ps
CPU time 10.59 seconds
Started Mar 07 12:55:29 PM PST 24
Finished Mar 07 12:55:41 PM PST 24
Peak memory 210912 kb
Host smart-6e0f8421-58f9-4801-aa09-21e32a4219b4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4000958763 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_alert_test.4000958763
Directory /workspace/26.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/26.rom_ctrl_corrupt_sig_fatal_chk.3862030347
Short name T306
Test name
Test status
Simulation time 3140385537 ps
CPU time 126.15 seconds
Started Mar 07 12:55:40 PM PST 24
Finished Mar 07 12:57:46 PM PST 24
Peak memory 237488 kb
Host smart-a8f975a4-4eb2-4352-95dd-3d4b92a6ebf8
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3862030347 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_
corrupt_sig_fatal_chk.3862030347
Directory /workspace/26.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/26.rom_ctrl_kmac_err_chk.1587215992
Short name T151
Test name
Test status
Simulation time 4204380517 ps
CPU time 21.89 seconds
Started Mar 07 12:55:30 PM PST 24
Finished Mar 07 12:55:54 PM PST 24
Peak memory 216412 kb
Host smart-aa9bed0a-f054-4d32-8f2e-67884cc3268f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1587215992 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_kmac_err_chk.1587215992
Directory /workspace/26.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/26.rom_ctrl_max_throughput_chk.2962929161
Short name T41
Test name
Test status
Simulation time 399197076 ps
CPU time 5.46 seconds
Started Mar 07 12:56:06 PM PST 24
Finished Mar 07 12:56:12 PM PST 24
Peak memory 210664 kb
Host smart-236f33ef-6ed6-4074-b2bc-83d531381e09
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2962929161 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_max_throughput_chk.2962929161
Directory /workspace/26.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/26.rom_ctrl_smoke.240984228
Short name T132
Test name
Test status
Simulation time 2889873719 ps
CPU time 15.62 seconds
Started Mar 07 12:55:39 PM PST 24
Finished Mar 07 12:55:55 PM PST 24
Peak memory 212640 kb
Host smart-e38146ce-8a29-40a3-8e8f-bea45c124341
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=240984228 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_smoke.240984228
Directory /workspace/26.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/26.rom_ctrl_stress_all.3314661825
Short name T239
Test name
Test status
Simulation time 5289482143 ps
CPU time 59.6 seconds
Started Mar 07 12:55:31 PM PST 24
Finished Mar 07 12:56:33 PM PST 24
Peak memory 215288 kb
Host smart-26f3c16d-ab95-4c37-aaf7-304aced59817
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3314661825 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 26.rom_ctrl_stress_all.3314661825
Directory /workspace/26.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/27.rom_ctrl_alert_test.615890841
Short name T202
Test name
Test status
Simulation time 10945346512 ps
CPU time 15.37 seconds
Started Mar 07 12:55:32 PM PST 24
Finished Mar 07 12:55:51 PM PST 24
Peak memory 210940 kb
Host smart-3cb58273-9146-4553-82a6-2494d27e2c4b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=615890841 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_alert_test.615890841
Directory /workspace/27.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/27.rom_ctrl_corrupt_sig_fatal_chk.4105279522
Short name T50
Test name
Test status
Simulation time 6412664499 ps
CPU time 122.07 seconds
Started Mar 07 12:55:25 PM PST 24
Finished Mar 07 12:57:27 PM PST 24
Peak memory 238124 kb
Host smart-b62cd6d0-41f2-4f01-ac56-ada719875f81
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4105279522 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_
corrupt_sig_fatal_chk.4105279522
Directory /workspace/27.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/27.rom_ctrl_kmac_err_chk.1418497852
Short name T148
Test name
Test status
Simulation time 1291793300 ps
CPU time 17.24 seconds
Started Mar 07 12:55:24 PM PST 24
Finished Mar 07 12:55:41 PM PST 24
Peak memory 211256 kb
Host smart-b65f582e-27f0-448c-abd4-3e6707875d52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1418497852 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_kmac_err_chk.1418497852
Directory /workspace/27.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/27.rom_ctrl_max_throughput_chk.1827983324
Short name T209
Test name
Test status
Simulation time 4908340728 ps
CPU time 13.07 seconds
Started Mar 07 12:55:31 PM PST 24
Finished Mar 07 12:55:50 PM PST 24
Peak memory 210800 kb
Host smart-269d93a4-07bd-4b7b-af6b-890b6d2a8fa2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1827983324 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_max_throughput_chk.1827983324
Directory /workspace/27.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/27.rom_ctrl_smoke.3218938169
Short name T224
Test name
Test status
Simulation time 1660551461 ps
CPU time 23.55 seconds
Started Mar 07 12:55:33 PM PST 24
Finished Mar 07 12:55:59 PM PST 24
Peak memory 212924 kb
Host smart-93fc04fe-968e-4f0a-9a6a-648633c00afc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3218938169 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_smoke.3218938169
Directory /workspace/27.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/27.rom_ctrl_stress_all.4073842349
Short name T203
Test name
Test status
Simulation time 2171551609 ps
CPU time 12.98 seconds
Started Mar 07 12:55:38 PM PST 24
Finished Mar 07 12:55:52 PM PST 24
Peak memory 210772 kb
Host smart-b3174540-967e-4996-a239-51b42a152ec7
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4073842349 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 27.rom_ctrl_stress_all.4073842349
Directory /workspace/27.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/28.rom_ctrl_alert_test.257510100
Short name T145
Test name
Test status
Simulation time 8443459220 ps
CPU time 16.01 seconds
Started Mar 07 12:55:26 PM PST 24
Finished Mar 07 12:55:42 PM PST 24
Peak memory 210928 kb
Host smart-00a7031f-0598-4114-9ba7-f9391f043965
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=257510100 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_alert_test.257510100
Directory /workspace/28.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/28.rom_ctrl_corrupt_sig_fatal_chk.2745893117
Short name T260
Test name
Test status
Simulation time 90725316635 ps
CPU time 178.27 seconds
Started Mar 07 12:55:32 PM PST 24
Finished Mar 07 12:58:34 PM PST 24
Peak memory 228124 kb
Host smart-9b9fb836-7d17-41df-b4cd-562bfc7028b7
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2745893117 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_
corrupt_sig_fatal_chk.2745893117
Directory /workspace/28.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/28.rom_ctrl_kmac_err_chk.433619500
Short name T144
Test name
Test status
Simulation time 6375989200 ps
CPU time 18.05 seconds
Started Mar 07 12:55:55 PM PST 24
Finished Mar 07 12:56:13 PM PST 24
Peak memory 212408 kb
Host smart-80d6c0c0-6881-4841-9c64-ca2c59241032
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=433619500 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_kmac_err_chk.433619500
Directory /workspace/28.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/28.rom_ctrl_max_throughput_chk.2743891224
Short name T4
Test name
Test status
Simulation time 457585205 ps
CPU time 5.37 seconds
Started Mar 07 12:55:40 PM PST 24
Finished Mar 07 12:55:45 PM PST 24
Peak memory 210732 kb
Host smart-042d026b-b3c9-4092-ab6e-a91caabe6ef3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2743891224 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_max_throughput_chk.2743891224
Directory /workspace/28.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/28.rom_ctrl_smoke.1463454850
Short name T42
Test name
Test status
Simulation time 7413386850 ps
CPU time 32.27 seconds
Started Mar 07 12:55:51 PM PST 24
Finished Mar 07 12:56:23 PM PST 24
Peak memory 213208 kb
Host smart-75768804-b1ff-4296-a63c-ee47921595fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1463454850 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_smoke.1463454850
Directory /workspace/28.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/28.rom_ctrl_stress_all.3149399144
Short name T330
Test name
Test status
Simulation time 5444940104 ps
CPU time 53.08 seconds
Started Mar 07 12:56:05 PM PST 24
Finished Mar 07 12:56:59 PM PST 24
Peak memory 212344 kb
Host smart-38541242-c06a-43e5-b397-c27f3d47a282
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3149399144 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 28.rom_ctrl_stress_all.3149399144
Directory /workspace/28.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/28.rom_ctrl_stress_all_with_rand_reset.1524383793
Short name T339
Test name
Test status
Simulation time 42599159572 ps
CPU time 1586.71 seconds
Started Mar 07 12:55:44 PM PST 24
Finished Mar 07 01:22:16 PM PST 24
Peak memory 235624 kb
Host smart-7bf4abd5-8c3e-4973-86ed-31b59da3838b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1524383793 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_stress_all_with_rand_reset.1524383793
Directory /workspace/28.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/29.rom_ctrl_alert_test.2401224850
Short name T173
Test name
Test status
Simulation time 662370599 ps
CPU time 5.31 seconds
Started Mar 07 12:55:45 PM PST 24
Finished Mar 07 12:55:51 PM PST 24
Peak memory 210844 kb
Host smart-72af7dd2-c831-4662-9e36-3e3b828e3108
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2401224850 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_alert_test.2401224850
Directory /workspace/29.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/29.rom_ctrl_corrupt_sig_fatal_chk.955106951
Short name T283
Test name
Test status
Simulation time 37421863612 ps
CPU time 145.86 seconds
Started Mar 07 12:55:46 PM PST 24
Finished Mar 07 12:58:13 PM PST 24
Peak memory 237476 kb
Host smart-e25ca276-abd4-4a08-8fc4-df38b2f72c5f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=955106951 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_c
orrupt_sig_fatal_chk.955106951
Directory /workspace/29.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/29.rom_ctrl_kmac_err_chk.3883572365
Short name T250
Test name
Test status
Simulation time 14635557728 ps
CPU time 30.08 seconds
Started Mar 07 12:55:33 PM PST 24
Finished Mar 07 12:56:06 PM PST 24
Peak memory 211768 kb
Host smart-12dd9a33-9a36-4d5b-ac92-54bb6665c926
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3883572365 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_kmac_err_chk.3883572365
Directory /workspace/29.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/29.rom_ctrl_max_throughput_chk.4262047957
Short name T245
Test name
Test status
Simulation time 1719657461 ps
CPU time 14.88 seconds
Started Mar 07 12:55:37 PM PST 24
Finished Mar 07 12:55:52 PM PST 24
Peak memory 210756 kb
Host smart-f3d78d18-6c91-4076-ab6d-9a4a6188755d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4262047957 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_max_throughput_chk.4262047957
Directory /workspace/29.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/29.rom_ctrl_smoke.3284824380
Short name T269
Test name
Test status
Simulation time 12772966738 ps
CPU time 18.46 seconds
Started Mar 07 12:55:40 PM PST 24
Finished Mar 07 12:55:59 PM PST 24
Peak memory 213360 kb
Host smart-274de062-2b12-4fe6-a30e-7270aabdf138
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3284824380 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_smoke.3284824380
Directory /workspace/29.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/29.rom_ctrl_stress_all.3733572564
Short name T351
Test name
Test status
Simulation time 29029396682 ps
CPU time 64.43 seconds
Started Mar 07 12:55:34 PM PST 24
Finished Mar 07 12:56:41 PM PST 24
Peak memory 216220 kb
Host smart-b7b0486d-159b-4eed-a6f0-afd542eb47de
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3733572564 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 29.rom_ctrl_stress_all.3733572564
Directory /workspace/29.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/29.rom_ctrl_stress_all_with_rand_reset.4150640074
Short name T53
Test name
Test status
Simulation time 51792294662 ps
CPU time 2685.6 seconds
Started Mar 07 12:55:45 PM PST 24
Finished Mar 07 01:40:32 PM PST 24
Peak memory 227296 kb
Host smart-a44941bd-31d9-4cd5-a579-e0e85244d940
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4150640074 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_stress_all_with_rand_reset.4150640074
Directory /workspace/29.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.rom_ctrl_alert_test.2399258974
Short name T181
Test name
Test status
Simulation time 6831579713 ps
CPU time 14.2 seconds
Started Mar 07 12:55:02 PM PST 24
Finished Mar 07 12:55:17 PM PST 24
Peak memory 210804 kb
Host smart-7fe51f49-b898-4f64-aa01-7f92d6edf8a9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2399258974 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_alert_test.2399258974
Directory /workspace/3.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/3.rom_ctrl_corrupt_sig_fatal_chk.2075535876
Short name T348
Test name
Test status
Simulation time 6105975926 ps
CPU time 102.88 seconds
Started Mar 07 12:55:04 PM PST 24
Finished Mar 07 12:56:47 PM PST 24
Peak memory 228628 kb
Host smart-6a9694e3-eea9-4900-b1a9-51cb4e13ba1d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2075535876 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_c
orrupt_sig_fatal_chk.2075535876
Directory /workspace/3.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/3.rom_ctrl_kmac_err_chk.2533497287
Short name T285
Test name
Test status
Simulation time 5920670154 ps
CPU time 19.49 seconds
Started Mar 07 12:55:31 PM PST 24
Finished Mar 07 12:55:54 PM PST 24
Peak memory 210912 kb
Host smart-4715bf33-564d-497a-bf54-86730bde97d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2533497287 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_kmac_err_chk.2533497287
Directory /workspace/3.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/3.rom_ctrl_max_throughput_chk.2666023005
Short name T191
Test name
Test status
Simulation time 15633581937 ps
CPU time 17.59 seconds
Started Mar 07 12:55:23 PM PST 24
Finished Mar 07 12:55:41 PM PST 24
Peak memory 210832 kb
Host smart-9f5a15ff-b240-432b-aee2-966060341d25
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2666023005 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_max_throughput_chk.2666023005
Directory /workspace/3.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/3.rom_ctrl_sec_cm.1835366044
Short name T40
Test name
Test status
Simulation time 5097068449 ps
CPU time 59.34 seconds
Started Mar 07 12:55:15 PM PST 24
Finished Mar 07 12:56:16 PM PST 24
Peak memory 236388 kb
Host smart-b1c2f1eb-03e2-41f2-aff0-08cfce33a774
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1835366044 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_sec_cm.1835366044
Directory /workspace/3.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/3.rom_ctrl_smoke.349483788
Short name T178
Test name
Test status
Simulation time 13501976489 ps
CPU time 29.7 seconds
Started Mar 07 12:55:11 PM PST 24
Finished Mar 07 12:55:41 PM PST 24
Peak memory 213396 kb
Host smart-ab33fee8-ebca-4a7d-b99d-d49bd5b657c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=349483788 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_smoke.349483788
Directory /workspace/3.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/3.rom_ctrl_stress_all.2285321671
Short name T345
Test name
Test status
Simulation time 21681888164 ps
CPU time 57.19 seconds
Started Mar 07 12:55:17 PM PST 24
Finished Mar 07 12:56:16 PM PST 24
Peak memory 218952 kb
Host smart-69850d15-8361-4b3f-a6e8-ecc7af68387f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2285321671 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 3.rom_ctrl_stress_all.2285321671
Directory /workspace/3.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/3.rom_ctrl_stress_all_with_rand_reset.893003853
Short name T56
Test name
Test status
Simulation time 132670819389 ps
CPU time 2992.79 seconds
Started Mar 07 12:55:20 PM PST 24
Finished Mar 07 01:45:14 PM PST 24
Peak memory 236200 kb
Host smart-d9c033c7-e5c6-4649-b157-d5a76d89418d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=893003853 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_stress_all_with_rand_reset.893003853
Directory /workspace/3.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.rom_ctrl_alert_test.251713715
Short name T248
Test name
Test status
Simulation time 3925623731 ps
CPU time 15.03 seconds
Started Mar 07 12:55:35 PM PST 24
Finished Mar 07 12:55:52 PM PST 24
Peak memory 210948 kb
Host smart-779f3a22-050a-43b9-83f4-2d8d4c650c45
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=251713715 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_alert_test.251713715
Directory /workspace/30.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/30.rom_ctrl_corrupt_sig_fatal_chk.2877702917
Short name T357
Test name
Test status
Simulation time 6216378763 ps
CPU time 92.18 seconds
Started Mar 07 12:56:13 PM PST 24
Finished Mar 07 12:57:46 PM PST 24
Peak memory 225140 kb
Host smart-c6b35413-9cac-40d6-9301-471840bcda3e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2877702917 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_
corrupt_sig_fatal_chk.2877702917
Directory /workspace/30.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/30.rom_ctrl_kmac_err_chk.1370848671
Short name T321
Test name
Test status
Simulation time 2634480302 ps
CPU time 14.26 seconds
Started Mar 07 12:55:31 PM PST 24
Finished Mar 07 12:55:49 PM PST 24
Peak memory 211296 kb
Host smart-35c58f1a-4e16-48e4-9b5c-b96f070c5ee1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1370848671 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_kmac_err_chk.1370848671
Directory /workspace/30.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/30.rom_ctrl_max_throughput_chk.3187130650
Short name T237
Test name
Test status
Simulation time 5715817123 ps
CPU time 12.39 seconds
Started Mar 07 12:55:43 PM PST 24
Finished Mar 07 12:55:55 PM PST 24
Peak memory 210796 kb
Host smart-5d672523-a8a9-4481-911b-1d0fb5ac5775
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3187130650 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_max_throughput_chk.3187130650
Directory /workspace/30.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/30.rom_ctrl_smoke.4041282992
Short name T327
Test name
Test status
Simulation time 9950441724 ps
CPU time 27.61 seconds
Started Mar 07 12:55:30 PM PST 24
Finished Mar 07 12:56:00 PM PST 24
Peak memory 213400 kb
Host smart-0045c215-7d04-4e77-b7e1-0d6e997b8e13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4041282992 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_smoke.4041282992
Directory /workspace/30.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/30.rom_ctrl_stress_all.3693233713
Short name T238
Test name
Test status
Simulation time 1065626421 ps
CPU time 18.75 seconds
Started Mar 07 12:55:40 PM PST 24
Finished Mar 07 12:55:59 PM PST 24
Peak memory 214296 kb
Host smart-8a602934-863e-437d-bb53-89393f9dd927
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3693233713 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 30.rom_ctrl_stress_all.3693233713
Directory /workspace/30.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/31.rom_ctrl_alert_test.95601920
Short name T287
Test name
Test status
Simulation time 347628408 ps
CPU time 4.24 seconds
Started Mar 07 12:55:33 PM PST 24
Finished Mar 07 12:55:40 PM PST 24
Peak memory 210844 kb
Host smart-eacb8260-733d-49c4-9ad0-15d30ef608fa
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=95601920 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_alert_test.95601920
Directory /workspace/31.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/31.rom_ctrl_corrupt_sig_fatal_chk.783569811
Short name T266
Test name
Test status
Simulation time 65524461032 ps
CPU time 370.33 seconds
Started Mar 07 12:55:37 PM PST 24
Finished Mar 07 01:01:48 PM PST 24
Peak memory 228428 kb
Host smart-165f86ec-af2b-4c94-8cae-41ac7d25db3a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=783569811 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_c
orrupt_sig_fatal_chk.783569811
Directory /workspace/31.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/31.rom_ctrl_kmac_err_chk.1016643002
Short name T329
Test name
Test status
Simulation time 4183553131 ps
CPU time 33.77 seconds
Started Mar 07 12:55:19 PM PST 24
Finished Mar 07 12:55:54 PM PST 24
Peak memory 211452 kb
Host smart-92f54aa1-af2c-4656-bad8-20a8230cdd44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1016643002 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_kmac_err_chk.1016643002
Directory /workspace/31.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/31.rom_ctrl_max_throughput_chk.1289769273
Short name T150
Test name
Test status
Simulation time 435883217 ps
CPU time 7.07 seconds
Started Mar 07 12:55:51 PM PST 24
Finished Mar 07 12:55:59 PM PST 24
Peak memory 210756 kb
Host smart-4b73af49-e0c9-4e97-a418-984a6c39af58
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1289769273 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_max_throughput_chk.1289769273
Directory /workspace/31.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/31.rom_ctrl_smoke.3706187758
Short name T343
Test name
Test status
Simulation time 9696497011 ps
CPU time 34.31 seconds
Started Mar 07 12:55:37 PM PST 24
Finished Mar 07 12:56:12 PM PST 24
Peak memory 212444 kb
Host smart-47a2b3f9-723e-4494-b66e-307feeb8d244
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3706187758 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_smoke.3706187758
Directory /workspace/31.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/31.rom_ctrl_stress_all.950418433
Short name T309
Test name
Test status
Simulation time 1019143971 ps
CPU time 12.28 seconds
Started Mar 07 12:55:29 PM PST 24
Finished Mar 07 12:55:43 PM PST 24
Peak memory 214612 kb
Host smart-e1788cbf-ff6e-4608-bc39-a9498a6dd22b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=950418433 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 31.rom_ctrl_stress_all.950418433
Directory /workspace/31.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/31.rom_ctrl_stress_all_with_rand_reset.2136214007
Short name T21
Test name
Test status
Simulation time 329323469520 ps
CPU time 2782.72 seconds
Started Mar 07 12:55:32 PM PST 24
Finished Mar 07 01:41:59 PM PST 24
Peak memory 243712 kb
Host smart-362afab3-fb94-40d5-8977-50bd8b3b08a6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2136214007 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_stress_all_with_rand_reset.2136214007
Directory /workspace/31.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.rom_ctrl_alert_test.4167959735
Short name T225
Test name
Test status
Simulation time 175472048 ps
CPU time 4.33 seconds
Started Mar 07 12:55:30 PM PST 24
Finished Mar 07 12:55:36 PM PST 24
Peak memory 210932 kb
Host smart-114bcaaa-fc9d-4bb5-9e70-53acfbb6f7a7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4167959735 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_alert_test.4167959735
Directory /workspace/32.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/32.rom_ctrl_corrupt_sig_fatal_chk.1683127192
Short name T226
Test name
Test status
Simulation time 496794199204 ps
CPU time 342.56 seconds
Started Mar 07 12:55:56 PM PST 24
Finished Mar 07 01:01:39 PM PST 24
Peak memory 212188 kb
Host smart-ae55140e-4958-4e3e-a321-ed88c0cc7a78
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1683127192 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_
corrupt_sig_fatal_chk.1683127192
Directory /workspace/32.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/32.rom_ctrl_max_throughput_chk.1541417631
Short name T166
Test name
Test status
Simulation time 3723987206 ps
CPU time 10.3 seconds
Started Mar 07 12:55:38 PM PST 24
Finished Mar 07 12:55:49 PM PST 24
Peak memory 210740 kb
Host smart-4d4d6f5b-1220-46d4-8228-9626cc4d993b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1541417631 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_max_throughput_chk.1541417631
Directory /workspace/32.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/32.rom_ctrl_smoke.2428231555
Short name T317
Test name
Test status
Simulation time 3526883677 ps
CPU time 30.94 seconds
Started Mar 07 12:55:45 PM PST 24
Finished Mar 07 12:56:16 PM PST 24
Peak memory 213132 kb
Host smart-8a3b997e-159a-4fe1-b32e-73be61178d27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2428231555 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_smoke.2428231555
Directory /workspace/32.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/32.rom_ctrl_stress_all.3825736683
Short name T64
Test name
Test status
Simulation time 941138112 ps
CPU time 25.08 seconds
Started Mar 07 12:55:51 PM PST 24
Finished Mar 07 12:56:17 PM PST 24
Peak memory 214508 kb
Host smart-a04af68c-eaf4-45cb-96d5-f2ee7ba05589
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3825736683 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 32.rom_ctrl_stress_all.3825736683
Directory /workspace/32.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/32.rom_ctrl_stress_all_with_rand_reset.1651419200
Short name T20
Test name
Test status
Simulation time 194550045088 ps
CPU time 1790.85 seconds
Started Mar 07 12:55:30 PM PST 24
Finished Mar 07 01:25:23 PM PST 24
Peak memory 238460 kb
Host smart-55a66192-d962-4a87-9823-43e617fbe4c9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1651419200 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_stress_all_with_rand_reset.1651419200
Directory /workspace/32.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.rom_ctrl_alert_test.2523679033
Short name T75
Test name
Test status
Simulation time 10852290579 ps
CPU time 14.31 seconds
Started Mar 07 12:55:35 PM PST 24
Finished Mar 07 12:55:51 PM PST 24
Peak memory 210912 kb
Host smart-48968818-b8fc-4855-abeb-4601b575285a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2523679033 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_alert_test.2523679033
Directory /workspace/33.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/33.rom_ctrl_corrupt_sig_fatal_chk.1031091556
Short name T162
Test name
Test status
Simulation time 30779928702 ps
CPU time 169.6 seconds
Started Mar 07 12:55:39 PM PST 24
Finished Mar 07 12:58:29 PM PST 24
Peak memory 236580 kb
Host smart-0260de22-2d54-48f8-af2b-a6760c9834b2
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1031091556 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_
corrupt_sig_fatal_chk.1031091556
Directory /workspace/33.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/33.rom_ctrl_kmac_err_chk.908431489
Short name T27
Test name
Test status
Simulation time 230111411 ps
CPU time 9.38 seconds
Started Mar 07 12:55:39 PM PST 24
Finished Mar 07 12:55:49 PM PST 24
Peak memory 211500 kb
Host smart-28d22b0d-8266-4859-9144-33958f3fe08a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=908431489 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_kmac_err_chk.908431489
Directory /workspace/33.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/33.rom_ctrl_max_throughput_chk.56547278
Short name T185
Test name
Test status
Simulation time 995727998 ps
CPU time 11.5 seconds
Started Mar 07 12:56:01 PM PST 24
Finished Mar 07 12:56:13 PM PST 24
Peak memory 210708 kb
Host smart-88d575fb-fbf1-4978-812e-4cf8400feafb
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=56547278 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_max_throughput_chk.56547278
Directory /workspace/33.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/33.rom_ctrl_smoke.216244994
Short name T242
Test name
Test status
Simulation time 2735353611 ps
CPU time 23.92 seconds
Started Mar 07 12:55:31 PM PST 24
Finished Mar 07 12:55:57 PM PST 24
Peak memory 213096 kb
Host smart-3898c5ed-195f-46ee-ba14-ec39eebb0309
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=216244994 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_smoke.216244994
Directory /workspace/33.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/33.rom_ctrl_stress_all.409596568
Short name T231
Test name
Test status
Simulation time 1405181806 ps
CPU time 14.92 seconds
Started Mar 07 12:55:31 PM PST 24
Finished Mar 07 12:55:50 PM PST 24
Peak memory 211240 kb
Host smart-4e5053aa-734d-48c8-b670-75a2aa7da7dd
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=409596568 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 33.rom_ctrl_stress_all.409596568
Directory /workspace/33.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/34.rom_ctrl_alert_test.1637312849
Short name T74
Test name
Test status
Simulation time 1525445963 ps
CPU time 12.39 seconds
Started Mar 07 12:55:42 PM PST 24
Finished Mar 07 12:55:54 PM PST 24
Peak memory 210872 kb
Host smart-99c4bd42-6841-472a-9fae-4134edc6c260
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1637312849 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_alert_test.1637312849
Directory /workspace/34.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/34.rom_ctrl_corrupt_sig_fatal_chk.2090156592
Short name T207
Test name
Test status
Simulation time 103062572966 ps
CPU time 228.93 seconds
Started Mar 07 12:55:32 PM PST 24
Finished Mar 07 12:59:25 PM PST 24
Peak memory 228680 kb
Host smart-49572a7a-9f28-4607-9145-a860f15e1420
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2090156592 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_
corrupt_sig_fatal_chk.2090156592
Directory /workspace/34.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/34.rom_ctrl_kmac_err_chk.3072296637
Short name T188
Test name
Test status
Simulation time 4819423960 ps
CPU time 23.21 seconds
Started Mar 07 12:55:57 PM PST 24
Finished Mar 07 12:56:21 PM PST 24
Peak memory 211940 kb
Host smart-276b7f36-e03d-469e-a2aa-cd1576f031d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3072296637 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_kmac_err_chk.3072296637
Directory /workspace/34.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/34.rom_ctrl_max_throughput_chk.2596771639
Short name T13
Test name
Test status
Simulation time 1976744952 ps
CPU time 15.84 seconds
Started Mar 07 12:55:36 PM PST 24
Finished Mar 07 12:55:53 PM PST 24
Peak memory 210752 kb
Host smart-be9bbc9d-4e55-4046-b4be-2ea96bad8bc7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2596771639 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_max_throughput_chk.2596771639
Directory /workspace/34.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/34.rom_ctrl_smoke.92967152
Short name T286
Test name
Test status
Simulation time 5136221243 ps
CPU time 21.49 seconds
Started Mar 07 12:55:54 PM PST 24
Finished Mar 07 12:56:15 PM PST 24
Peak memory 212768 kb
Host smart-1b5bb4bb-6fb8-4841-940b-1422aa3ede91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=92967152 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_smoke.92967152
Directory /workspace/34.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/35.rom_ctrl_alert_test.691395314
Short name T5
Test name
Test status
Simulation time 2212874076 ps
CPU time 16.17 seconds
Started Mar 07 12:55:41 PM PST 24
Finished Mar 07 12:55:57 PM PST 24
Peak memory 210776 kb
Host smart-1d3d9c2a-ebbb-4a5d-a8d6-552615a00346
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=691395314 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_alert_test.691395314
Directory /workspace/35.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/35.rom_ctrl_corrupt_sig_fatal_chk.1947399483
Short name T12
Test name
Test status
Simulation time 2741431363 ps
CPU time 94.33 seconds
Started Mar 07 12:55:44 PM PST 24
Finished Mar 07 12:57:18 PM PST 24
Peak memory 226064 kb
Host smart-830a1a71-eab4-408e-8751-733589c00eec
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1947399483 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_
corrupt_sig_fatal_chk.1947399483
Directory /workspace/35.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/35.rom_ctrl_kmac_err_chk.1021951772
Short name T337
Test name
Test status
Simulation time 2093874731 ps
CPU time 23.26 seconds
Started Mar 07 12:55:53 PM PST 24
Finished Mar 07 12:56:17 PM PST 24
Peak memory 211224 kb
Host smart-9b295360-b808-41b6-9329-b3f994bc4907
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1021951772 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_kmac_err_chk.1021951772
Directory /workspace/35.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/35.rom_ctrl_max_throughput_chk.976036549
Short name T295
Test name
Test status
Simulation time 1454294622 ps
CPU time 13.17 seconds
Started Mar 07 12:55:45 PM PST 24
Finished Mar 07 12:55:58 PM PST 24
Peak memory 210620 kb
Host smart-947061ad-49be-4e51-beb0-056c297e5fee
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=976036549 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_max_throughput_chk.976036549
Directory /workspace/35.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/35.rom_ctrl_smoke.4216728724
Short name T161
Test name
Test status
Simulation time 4262277009 ps
CPU time 35.36 seconds
Started Mar 07 12:55:50 PM PST 24
Finished Mar 07 12:56:26 PM PST 24
Peak memory 212564 kb
Host smart-1a4854ff-23c2-4191-a701-7c05db50e1f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4216728724 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_smoke.4216728724
Directory /workspace/35.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/35.rom_ctrl_stress_all.4254737057
Short name T347
Test name
Test status
Simulation time 5601171879 ps
CPU time 56.95 seconds
Started Mar 07 12:55:43 PM PST 24
Finished Mar 07 12:56:40 PM PST 24
Peak memory 219064 kb
Host smart-f75e11e8-f3b7-44cc-a118-9e60e33fadcc
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4254737057 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 35.rom_ctrl_stress_all.4254737057
Directory /workspace/35.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/36.rom_ctrl_alert_test.2845947311
Short name T170
Test name
Test status
Simulation time 263533133 ps
CPU time 6.25 seconds
Started Mar 07 12:55:44 PM PST 24
Finished Mar 07 12:55:51 PM PST 24
Peak memory 210872 kb
Host smart-fa9c835e-846c-4428-9005-887becadd800
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2845947311 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_alert_test.2845947311
Directory /workspace/36.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/36.rom_ctrl_corrupt_sig_fatal_chk.3366475921
Short name T204
Test name
Test status
Simulation time 258625663410 ps
CPU time 395.91 seconds
Started Mar 07 12:55:45 PM PST 24
Finished Mar 07 01:02:22 PM PST 24
Peak memory 213220 kb
Host smart-4ca92bc3-7c50-41ad-8c4b-13aa4d5e8844
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3366475921 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_
corrupt_sig_fatal_chk.3366475921
Directory /workspace/36.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/36.rom_ctrl_kmac_err_chk.379406186
Short name T319
Test name
Test status
Simulation time 1021341540 ps
CPU time 14.47 seconds
Started Mar 07 12:55:50 PM PST 24
Finished Mar 07 12:56:05 PM PST 24
Peak memory 211544 kb
Host smart-67beb055-9a5f-4c40-b555-67d5b04a3b96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=379406186 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_kmac_err_chk.379406186
Directory /workspace/36.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/36.rom_ctrl_smoke.3324336238
Short name T175
Test name
Test status
Simulation time 9606249077 ps
CPU time 30.04 seconds
Started Mar 07 12:55:54 PM PST 24
Finished Mar 07 12:56:24 PM PST 24
Peak memory 213472 kb
Host smart-244053e7-3eb2-4e30-81ec-47b04e66931f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3324336238 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_smoke.3324336238
Directory /workspace/36.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/36.rom_ctrl_stress_all.605814360
Short name T356
Test name
Test status
Simulation time 1458220624 ps
CPU time 10.2 seconds
Started Mar 07 12:55:40 PM PST 24
Finished Mar 07 12:55:51 PM PST 24
Peak memory 210800 kb
Host smart-e1a8b96c-a8a2-4304-b018-9a9092207fbb
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=605814360 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 36.rom_ctrl_stress_all.605814360
Directory /workspace/36.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/37.rom_ctrl_alert_test.177130508
Short name T163
Test name
Test status
Simulation time 4331589703 ps
CPU time 17.38 seconds
Started Mar 07 12:55:34 PM PST 24
Finished Mar 07 12:55:53 PM PST 24
Peak memory 211028 kb
Host smart-a80de98d-adc1-454b-a0b9-7030af4a3a2d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=177130508 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_alert_test.177130508
Directory /workspace/37.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/37.rom_ctrl_corrupt_sig_fatal_chk.3521155043
Short name T251
Test name
Test status
Simulation time 12188346565 ps
CPU time 217.16 seconds
Started Mar 07 12:55:47 PM PST 24
Finished Mar 07 12:59:27 PM PST 24
Peak memory 227668 kb
Host smart-e25e730b-87bc-45f7-993f-f51243a22233
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3521155043 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_
corrupt_sig_fatal_chk.3521155043
Directory /workspace/37.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/37.rom_ctrl_kmac_err_chk.2312832657
Short name T141
Test name
Test status
Simulation time 5861594136 ps
CPU time 15.21 seconds
Started Mar 07 12:55:31 PM PST 24
Finished Mar 07 12:55:50 PM PST 24
Peak memory 211944 kb
Host smart-f6b8c475-a75c-4f1e-a7fe-de90e2e3352d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2312832657 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_kmac_err_chk.2312832657
Directory /workspace/37.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/37.rom_ctrl_max_throughput_chk.1352253995
Short name T316
Test name
Test status
Simulation time 10388988266 ps
CPU time 13.92 seconds
Started Mar 07 12:55:35 PM PST 24
Finished Mar 07 12:55:51 PM PST 24
Peak memory 210824 kb
Host smart-88a2162e-8b21-490c-b8c6-0a582ebf85e5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1352253995 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_max_throughput_chk.1352253995
Directory /workspace/37.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/37.rom_ctrl_smoke.3937199254
Short name T234
Test name
Test status
Simulation time 4697795594 ps
CPU time 36.33 seconds
Started Mar 07 12:55:34 PM PST 24
Finished Mar 07 12:56:13 PM PST 24
Peak memory 213412 kb
Host smart-1cbf77fb-e1c6-4dbb-8589-00388dce1328
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3937199254 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_smoke.3937199254
Directory /workspace/37.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/37.rom_ctrl_stress_all.3284638244
Short name T258
Test name
Test status
Simulation time 2423127901 ps
CPU time 10.89 seconds
Started Mar 07 12:56:19 PM PST 24
Finished Mar 07 12:56:30 PM PST 24
Peak memory 213876 kb
Host smart-7cf1dcfc-1635-484b-9448-57b07f08abb7
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3284638244 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 37.rom_ctrl_stress_all.3284638244
Directory /workspace/37.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/37.rom_ctrl_stress_all_with_rand_reset.254373756
Short name T54
Test name
Test status
Simulation time 87973355252 ps
CPU time 871.78 seconds
Started Mar 07 12:55:52 PM PST 24
Finished Mar 07 01:10:23 PM PST 24
Peak memory 235568 kb
Host smart-5b55a27b-af74-4452-a2c5-2e1dd464b2fa
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=254373756 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_stress_all_with_rand_reset.254373756
Directory /workspace/37.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.rom_ctrl_alert_test.944936983
Short name T302
Test name
Test status
Simulation time 7495683658 ps
CPU time 15.58 seconds
Started Mar 07 12:55:41 PM PST 24
Finished Mar 07 12:55:56 PM PST 24
Peak memory 210896 kb
Host smart-21190e35-9c18-4120-9614-71813fd9ab01
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=944936983 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_alert_test.944936983
Directory /workspace/38.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/38.rom_ctrl_corrupt_sig_fatal_chk.607139180
Short name T333
Test name
Test status
Simulation time 17454738883 ps
CPU time 244.17 seconds
Started Mar 07 12:55:45 PM PST 24
Finished Mar 07 12:59:50 PM PST 24
Peak memory 236444 kb
Host smart-011e824d-305e-4deb-94c4-e46b01af89dc
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=607139180 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_c
orrupt_sig_fatal_chk.607139180
Directory /workspace/38.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/38.rom_ctrl_kmac_err_chk.1849494550
Short name T342
Test name
Test status
Simulation time 1559168874 ps
CPU time 19.85 seconds
Started Mar 07 12:55:32 PM PST 24
Finished Mar 07 12:55:56 PM PST 24
Peak memory 211260 kb
Host smart-081cc99d-4ef9-43e4-957d-027a1f48e0e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1849494550 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_kmac_err_chk.1849494550
Directory /workspace/38.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/38.rom_ctrl_max_throughput_chk.2869867177
Short name T180
Test name
Test status
Simulation time 1743589969 ps
CPU time 8.53 seconds
Started Mar 07 12:55:43 PM PST 24
Finished Mar 07 12:55:52 PM PST 24
Peak memory 210768 kb
Host smart-18072a5c-44a0-4843-8a3d-c34e69ef132b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2869867177 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_max_throughput_chk.2869867177
Directory /workspace/38.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/38.rom_ctrl_smoke.2346398362
Short name T236
Test name
Test status
Simulation time 182041672 ps
CPU time 9.67 seconds
Started Mar 07 12:55:43 PM PST 24
Finished Mar 07 12:55:53 PM PST 24
Peak memory 213172 kb
Host smart-a3fb40f2-71dd-4c46-8371-8d0021321a27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2346398362 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_smoke.2346398362
Directory /workspace/38.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/38.rom_ctrl_stress_all.1449261560
Short name T208
Test name
Test status
Simulation time 4799832433 ps
CPU time 50.25 seconds
Started Mar 07 12:55:55 PM PST 24
Finished Mar 07 12:56:45 PM PST 24
Peak memory 212712 kb
Host smart-3326250b-98e2-4cb6-9dc5-31409e49c611
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1449261560 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 38.rom_ctrl_stress_all.1449261560
Directory /workspace/38.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/39.rom_ctrl_alert_test.312271879
Short name T297
Test name
Test status
Simulation time 4120403179 ps
CPU time 16.2 seconds
Started Mar 07 12:55:53 PM PST 24
Finished Mar 07 12:56:09 PM PST 24
Peak memory 210908 kb
Host smart-bf773881-514c-4cb4-9a8a-fe98bafefb51
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=312271879 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_alert_test.312271879
Directory /workspace/39.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/39.rom_ctrl_corrupt_sig_fatal_chk.2322093375
Short name T182
Test name
Test status
Simulation time 25563555784 ps
CPU time 272.81 seconds
Started Mar 07 12:55:41 PM PST 24
Finished Mar 07 01:00:14 PM PST 24
Peak memory 237400 kb
Host smart-47c9710e-96c7-4f64-9780-9c887ab42a6a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2322093375 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_
corrupt_sig_fatal_chk.2322093375
Directory /workspace/39.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/39.rom_ctrl_kmac_err_chk.2883863212
Short name T49
Test name
Test status
Simulation time 10862850033 ps
CPU time 22.04 seconds
Started Mar 07 12:55:46 PM PST 24
Finished Mar 07 12:56:08 PM PST 24
Peak memory 211608 kb
Host smart-d0d7103c-3e8e-4a17-8c8d-ea3135a1f841
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2883863212 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_kmac_err_chk.2883863212
Directory /workspace/39.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/39.rom_ctrl_max_throughput_chk.2894124438
Short name T149
Test name
Test status
Simulation time 1047677031 ps
CPU time 8.71 seconds
Started Mar 07 12:55:55 PM PST 24
Finished Mar 07 12:56:04 PM PST 24
Peak memory 210728 kb
Host smart-1f6e680a-5138-48c3-8cba-4a4bbb7a52e9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2894124438 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_max_throughput_chk.2894124438
Directory /workspace/39.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/39.rom_ctrl_smoke.1868142766
Short name T227
Test name
Test status
Simulation time 188567666 ps
CPU time 9.77 seconds
Started Mar 07 12:55:59 PM PST 24
Finished Mar 07 12:56:09 PM PST 24
Peak memory 212696 kb
Host smart-6fc0a31b-aac9-4c79-a6e1-54664ced1201
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1868142766 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_smoke.1868142766
Directory /workspace/39.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/39.rom_ctrl_stress_all.3088668752
Short name T291
Test name
Test status
Simulation time 12463070788 ps
CPU time 32.32 seconds
Started Mar 07 12:55:40 PM PST 24
Finished Mar 07 12:56:13 PM PST 24
Peak memory 213724 kb
Host smart-c8fc2205-3a3f-482c-9fd2-8ee60f83e6ee
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3088668752 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 39.rom_ctrl_stress_all.3088668752
Directory /workspace/39.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/4.rom_ctrl_alert_test.403272093
Short name T344
Test name
Test status
Simulation time 1700847436 ps
CPU time 14.88 seconds
Started Mar 07 12:55:10 PM PST 24
Finished Mar 07 12:55:25 PM PST 24
Peak memory 210832 kb
Host smart-eee6b561-cfb9-44a9-9fab-f22e0de30229
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=403272093 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_alert_test.403272093
Directory /workspace/4.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/4.rom_ctrl_corrupt_sig_fatal_chk.156448384
Short name T284
Test name
Test status
Simulation time 62231954068 ps
CPU time 333.1 seconds
Started Mar 07 12:55:31 PM PST 24
Finished Mar 07 01:01:08 PM PST 24
Peak memory 237368 kb
Host smart-4a047a4b-8954-4e6f-9164-097c8388a0aa
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=156448384 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_co
rrupt_sig_fatal_chk.156448384
Directory /workspace/4.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/4.rom_ctrl_kmac_err_chk.1865560449
Short name T10
Test name
Test status
Simulation time 4853263370 ps
CPU time 24.65 seconds
Started Mar 07 12:55:19 PM PST 24
Finished Mar 07 12:55:44 PM PST 24
Peak memory 211584 kb
Host smart-a5744277-df7a-4dcd-aeee-612ce0055775
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1865560449 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_kmac_err_chk.1865560449
Directory /workspace/4.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/4.rom_ctrl_max_throughput_chk.902909682
Short name T108
Test name
Test status
Simulation time 2659116758 ps
CPU time 17 seconds
Started Mar 07 12:55:18 PM PST 24
Finished Mar 07 12:55:36 PM PST 24
Peak memory 210640 kb
Host smart-7e831356-8bb2-4c6d-a941-8c232416bf4f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=902909682 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_max_throughput_chk.902909682
Directory /workspace/4.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/4.rom_ctrl_sec_cm.2208402889
Short name T35
Test name
Test status
Simulation time 1603518102 ps
CPU time 99.52 seconds
Started Mar 07 12:55:07 PM PST 24
Finished Mar 07 12:56:47 PM PST 24
Peak memory 230992 kb
Host smart-743c5802-4289-4275-9154-d70bdc07ccf8
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2208402889 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_sec_cm.2208402889
Directory /workspace/4.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/4.rom_ctrl_smoke.1428831057
Short name T363
Test name
Test status
Simulation time 404634825 ps
CPU time 9.75 seconds
Started Mar 07 12:55:15 PM PST 24
Finished Mar 07 12:55:27 PM PST 24
Peak memory 213488 kb
Host smart-2b25e4f3-0cbd-4481-b49b-67891b8c135f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1428831057 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_smoke.1428831057
Directory /workspace/4.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/4.rom_ctrl_stress_all.157099182
Short name T127
Test name
Test status
Simulation time 20154840051 ps
CPU time 84.85 seconds
Started Mar 07 12:55:07 PM PST 24
Finished Mar 07 12:56:32 PM PST 24
Peak memory 219108 kb
Host smart-003918f5-cc6f-417e-8352-0e6e197f0a24
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=157099182 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 4.rom_ctrl_stress_all.157099182
Directory /workspace/4.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/40.rom_ctrl_alert_test.283770598
Short name T299
Test name
Test status
Simulation time 2901760231 ps
CPU time 8.64 seconds
Started Mar 07 12:55:48 PM PST 24
Finished Mar 07 12:55:57 PM PST 24
Peak memory 210920 kb
Host smart-0c29c725-eb05-4fb9-8ba0-f421c4aa113a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=283770598 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_alert_test.283770598
Directory /workspace/40.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/40.rom_ctrl_corrupt_sig_fatal_chk.3282008792
Short name T23
Test name
Test status
Simulation time 3518724742 ps
CPU time 113.46 seconds
Started Mar 07 12:55:49 PM PST 24
Finished Mar 07 12:57:43 PM PST 24
Peak memory 220256 kb
Host smart-dc8fcad6-701e-4c9f-9231-d3037dd9e858
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3282008792 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_
corrupt_sig_fatal_chk.3282008792
Directory /workspace/40.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/40.rom_ctrl_kmac_err_chk.1961420742
Short name T305
Test name
Test status
Simulation time 2753550152 ps
CPU time 11.57 seconds
Started Mar 07 12:55:47 PM PST 24
Finished Mar 07 12:55:59 PM PST 24
Peak memory 211528 kb
Host smart-4eef89be-e748-4c9f-9387-04550e976179
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1961420742 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_kmac_err_chk.1961420742
Directory /workspace/40.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/40.rom_ctrl_max_throughput_chk.3749332144
Short name T153
Test name
Test status
Simulation time 4517328022 ps
CPU time 11.55 seconds
Started Mar 07 12:55:47 PM PST 24
Finished Mar 07 12:55:59 PM PST 24
Peak memory 210680 kb
Host smart-e06d1f63-5679-4689-b8a2-3a99e2655893
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3749332144 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_max_throughput_chk.3749332144
Directory /workspace/40.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/40.rom_ctrl_smoke.1954832103
Short name T110
Test name
Test status
Simulation time 870738348 ps
CPU time 15.31 seconds
Started Mar 07 12:55:49 PM PST 24
Finished Mar 07 12:56:05 PM PST 24
Peak memory 213064 kb
Host smart-1c9967b4-272f-40bb-8f39-281df5d02233
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1954832103 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_smoke.1954832103
Directory /workspace/40.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/40.rom_ctrl_stress_all.3949317907
Short name T61
Test name
Test status
Simulation time 13945904566 ps
CPU time 46.03 seconds
Started Mar 07 12:55:33 PM PST 24
Finished Mar 07 12:56:22 PM PST 24
Peak memory 219060 kb
Host smart-ebf233e2-b6c8-4833-bd93-f94e10dd9c46
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3949317907 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 40.rom_ctrl_stress_all.3949317907
Directory /workspace/40.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/41.rom_ctrl_alert_test.227006862
Short name T324
Test name
Test status
Simulation time 462889963 ps
CPU time 7.47 seconds
Started Mar 07 12:55:43 PM PST 24
Finished Mar 07 12:55:50 PM PST 24
Peak memory 210860 kb
Host smart-4c4a6505-3882-4ebf-957e-76cf34bcf23e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=227006862 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_alert_test.227006862
Directory /workspace/41.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/41.rom_ctrl_corrupt_sig_fatal_chk.3080125010
Short name T313
Test name
Test status
Simulation time 147701275204 ps
CPU time 387.29 seconds
Started Mar 07 12:55:45 PM PST 24
Finished Mar 07 01:02:17 PM PST 24
Peak memory 227904 kb
Host smart-6f2a4f09-c07c-4e6b-814b-bc7b39152675
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3080125010 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_
corrupt_sig_fatal_chk.3080125010
Directory /workspace/41.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/41.rom_ctrl_kmac_err_chk.2709364688
Short name T253
Test name
Test status
Simulation time 2509275796 ps
CPU time 13.69 seconds
Started Mar 07 12:55:45 PM PST 24
Finished Mar 07 12:55:59 PM PST 24
Peak memory 211424 kb
Host smart-1dd95599-2394-42f1-9349-e2948ca096ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2709364688 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_kmac_err_chk.2709364688
Directory /workspace/41.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/41.rom_ctrl_max_throughput_chk.25770245
Short name T63
Test name
Test status
Simulation time 100063666 ps
CPU time 5.61 seconds
Started Mar 07 12:55:36 PM PST 24
Finished Mar 07 12:55:42 PM PST 24
Peak memory 210752 kb
Host smart-d196d63b-0263-474f-bc1b-d5927fd874aa
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=25770245 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_max_throughput_chk.25770245
Directory /workspace/41.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/41.rom_ctrl_smoke.3740523277
Short name T296
Test name
Test status
Simulation time 14059726666 ps
CPU time 36.28 seconds
Started Mar 07 12:55:55 PM PST 24
Finished Mar 07 12:56:31 PM PST 24
Peak memory 213436 kb
Host smart-28d35fe5-e1b9-4067-95d9-7a43b14a9853
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3740523277 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_smoke.3740523277
Directory /workspace/41.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/41.rom_ctrl_stress_all.3060292973
Short name T189
Test name
Test status
Simulation time 1186726800 ps
CPU time 14.01 seconds
Started Mar 07 12:55:32 PM PST 24
Finished Mar 07 12:55:49 PM PST 24
Peak memory 213736 kb
Host smart-d09969d0-7b6a-4762-a301-4f279906423f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3060292973 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 41.rom_ctrl_stress_all.3060292973
Directory /workspace/41.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/42.rom_ctrl_alert_test.1666500926
Short name T228
Test name
Test status
Simulation time 347513667 ps
CPU time 5.41 seconds
Started Mar 07 12:55:51 PM PST 24
Finished Mar 07 12:55:56 PM PST 24
Peak memory 210776 kb
Host smart-22cd037a-3a67-4fd0-9d74-55155581537a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1666500926 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_alert_test.1666500926
Directory /workspace/42.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/42.rom_ctrl_corrupt_sig_fatal_chk.3775831874
Short name T137
Test name
Test status
Simulation time 11085105219 ps
CPU time 239.43 seconds
Started Mar 07 12:55:58 PM PST 24
Finished Mar 07 12:59:58 PM PST 24
Peak memory 220188 kb
Host smart-1160169e-f564-4914-9188-17508507f8ad
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3775831874 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_
corrupt_sig_fatal_chk.3775831874
Directory /workspace/42.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/42.rom_ctrl_kmac_err_chk.2724304130
Short name T28
Test name
Test status
Simulation time 2883085445 ps
CPU time 27.12 seconds
Started Mar 07 12:56:30 PM PST 24
Finished Mar 07 12:56:57 PM PST 24
Peak memory 211356 kb
Host smart-b5b2a869-fe50-41cc-a41d-e625f268affd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2724304130 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_kmac_err_chk.2724304130
Directory /workspace/42.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/42.rom_ctrl_max_throughput_chk.435837758
Short name T154
Test name
Test status
Simulation time 13949684362 ps
CPU time 14.17 seconds
Started Mar 07 12:55:37 PM PST 24
Finished Mar 07 12:55:52 PM PST 24
Peak memory 210816 kb
Host smart-05188012-5316-4df9-ad7d-75fe4127ee41
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=435837758 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_max_throughput_chk.435837758
Directory /workspace/42.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/42.rom_ctrl_smoke.127362330
Short name T140
Test name
Test status
Simulation time 1536023362 ps
CPU time 12.87 seconds
Started Mar 07 12:55:33 PM PST 24
Finished Mar 07 12:55:49 PM PST 24
Peak memory 212924 kb
Host smart-126e1d27-4b77-44e1-a85a-a0fcf8912655
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=127362330 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_smoke.127362330
Directory /workspace/42.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/42.rom_ctrl_stress_all.2853823716
Short name T213
Test name
Test status
Simulation time 2391615080 ps
CPU time 23.79 seconds
Started Mar 07 12:55:31 PM PST 24
Finished Mar 07 12:55:59 PM PST 24
Peak memory 212984 kb
Host smart-d4f426e2-b16d-4e11-9d52-06c4ac612895
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2853823716 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 42.rom_ctrl_stress_all.2853823716
Directory /workspace/42.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/42.rom_ctrl_stress_all_with_rand_reset.102690929
Short name T353
Test name
Test status
Simulation time 109297483840 ps
CPU time 1093.28 seconds
Started Mar 07 12:56:03 PM PST 24
Finished Mar 07 01:14:16 PM PST 24
Peak memory 235928 kb
Host smart-45113bd1-c725-4242-afc6-c01da0e44813
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=102690929 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_stress_all_with_rand_reset.102690929
Directory /workspace/42.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.rom_ctrl_alert_test.242935899
Short name T8
Test name
Test status
Simulation time 3610731711 ps
CPU time 9.82 seconds
Started Mar 07 12:55:52 PM PST 24
Finished Mar 07 12:56:02 PM PST 24
Peak memory 210884 kb
Host smart-f3bb622f-640f-4204-a02b-dd24a8022d92
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=242935899 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_alert_test.242935899
Directory /workspace/43.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/43.rom_ctrl_kmac_err_chk.108436079
Short name T139
Test name
Test status
Simulation time 3111693425 ps
CPU time 27.07 seconds
Started Mar 07 12:55:46 PM PST 24
Finished Mar 07 12:56:13 PM PST 24
Peak memory 211340 kb
Host smart-dd4a4808-b305-4d1f-a290-d638a6894bff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=108436079 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_kmac_err_chk.108436079
Directory /workspace/43.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/43.rom_ctrl_max_throughput_chk.2880679488
Short name T169
Test name
Test status
Simulation time 5184482294 ps
CPU time 12.73 seconds
Started Mar 07 12:55:40 PM PST 24
Finished Mar 07 12:55:53 PM PST 24
Peak memory 210788 kb
Host smart-2d653564-1e50-49e5-b8c0-7bfcd2903959
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2880679488 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_max_throughput_chk.2880679488
Directory /workspace/43.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/43.rom_ctrl_smoke.1955864721
Short name T44
Test name
Test status
Simulation time 5293521653 ps
CPU time 16.04 seconds
Started Mar 07 12:55:52 PM PST 24
Finished Mar 07 12:56:09 PM PST 24
Peak memory 213164 kb
Host smart-f252a96e-5c89-45cb-8196-170e76c42488
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1955864721 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_smoke.1955864721
Directory /workspace/43.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/43.rom_ctrl_stress_all.2004950526
Short name T311
Test name
Test status
Simulation time 56842216322 ps
CPU time 50.73 seconds
Started Mar 07 12:55:53 PM PST 24
Finished Mar 07 12:56:44 PM PST 24
Peak memory 216356 kb
Host smart-7e9a387c-3806-44f2-b395-bed3ca0e7a17
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2004950526 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 43.rom_ctrl_stress_all.2004950526
Directory /workspace/43.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/44.rom_ctrl_alert_test.1040771922
Short name T46
Test name
Test status
Simulation time 2803405635 ps
CPU time 7.3 seconds
Started Mar 07 12:55:48 PM PST 24
Finished Mar 07 12:55:56 PM PST 24
Peak memory 211044 kb
Host smart-c138b664-99cc-434f-a3bb-8983261ce2f3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1040771922 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_alert_test.1040771922
Directory /workspace/44.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/44.rom_ctrl_corrupt_sig_fatal_chk.1821171200
Short name T264
Test name
Test status
Simulation time 3013318144 ps
CPU time 141.47 seconds
Started Mar 07 12:55:43 PM PST 24
Finished Mar 07 12:58:05 PM PST 24
Peak memory 237396 kb
Host smart-8891401f-4d25-4ac3-906c-ff0169e0b6a3
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1821171200 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_
corrupt_sig_fatal_chk.1821171200
Directory /workspace/44.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/44.rom_ctrl_kmac_err_chk.2790692703
Short name T160
Test name
Test status
Simulation time 169898306 ps
CPU time 9.57 seconds
Started Mar 07 12:55:45 PM PST 24
Finished Mar 07 12:55:55 PM PST 24
Peak memory 211416 kb
Host smart-a151bd9f-b986-4ee0-900c-2d0053d6b138
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2790692703 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_kmac_err_chk.2790692703
Directory /workspace/44.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/44.rom_ctrl_smoke.2904266058
Short name T194
Test name
Test status
Simulation time 743262897 ps
CPU time 9.7 seconds
Started Mar 07 12:55:53 PM PST 24
Finished Mar 07 12:56:03 PM PST 24
Peak memory 213344 kb
Host smart-6600df01-acdf-4fa3-affe-0a2498d1f781
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2904266058 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_smoke.2904266058
Directory /workspace/44.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/44.rom_ctrl_stress_all.4008935236
Short name T211
Test name
Test status
Simulation time 3461130352 ps
CPU time 35.62 seconds
Started Mar 07 12:55:54 PM PST 24
Finished Mar 07 12:56:29 PM PST 24
Peak memory 212452 kb
Host smart-cf86b92b-8b47-4079-bfb3-acf9b06d0eb8
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4008935236 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 44.rom_ctrl_stress_all.4008935236
Directory /workspace/44.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/45.rom_ctrl_alert_test.3734268638
Short name T308
Test name
Test status
Simulation time 1575844018 ps
CPU time 13.61 seconds
Started Mar 07 12:55:48 PM PST 24
Finished Mar 07 12:56:02 PM PST 24
Peak memory 210948 kb
Host smart-f929d869-f143-48b0-8dda-5f602fb9499f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3734268638 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_alert_test.3734268638
Directory /workspace/45.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/45.rom_ctrl_corrupt_sig_fatal_chk.3212676229
Short name T307
Test name
Test status
Simulation time 6783520665 ps
CPU time 114.4 seconds
Started Mar 07 12:56:07 PM PST 24
Finished Mar 07 12:58:01 PM PST 24
Peak memory 236760 kb
Host smart-8ffc1113-871e-45ce-a36f-e03b6d274069
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3212676229 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_
corrupt_sig_fatal_chk.3212676229
Directory /workspace/45.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/45.rom_ctrl_kmac_err_chk.561466436
Short name T325
Test name
Test status
Simulation time 7624242948 ps
CPU time 32.34 seconds
Started Mar 07 12:55:47 PM PST 24
Finished Mar 07 12:56:20 PM PST 24
Peak memory 210892 kb
Host smart-8e588d5b-5cdd-46f5-9ea2-646d13c3b850
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=561466436 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_kmac_err_chk.561466436
Directory /workspace/45.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/45.rom_ctrl_max_throughput_chk.1661828627
Short name T323
Test name
Test status
Simulation time 3799409041 ps
CPU time 10.83 seconds
Started Mar 07 12:55:42 PM PST 24
Finished Mar 07 12:55:53 PM PST 24
Peak memory 210972 kb
Host smart-980e3dec-8efd-42a6-b17a-59c0252c2406
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1661828627 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_max_throughput_chk.1661828627
Directory /workspace/45.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/45.rom_ctrl_smoke.2026624927
Short name T300
Test name
Test status
Simulation time 1999992384 ps
CPU time 12.15 seconds
Started Mar 07 12:55:52 PM PST 24
Finished Mar 07 12:56:05 PM PST 24
Peak memory 212616 kb
Host smart-0f8e7db8-8769-4f82-9c8e-4f3b88ccc117
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2026624927 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_smoke.2026624927
Directory /workspace/45.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/45.rom_ctrl_stress_all.2852589544
Short name T349
Test name
Test status
Simulation time 4476006251 ps
CPU time 31.35 seconds
Started Mar 07 12:55:49 PM PST 24
Finished Mar 07 12:56:21 PM PST 24
Peak memory 212856 kb
Host smart-e18177ce-0e74-451b-8e9a-aee993093fbc
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2852589544 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 45.rom_ctrl_stress_all.2852589544
Directory /workspace/45.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/46.rom_ctrl_alert_test.3460135886
Short name T217
Test name
Test status
Simulation time 348282824 ps
CPU time 4.26 seconds
Started Mar 07 12:55:59 PM PST 24
Finished Mar 07 12:56:03 PM PST 24
Peak memory 210892 kb
Host smart-e529c985-1217-4aa1-bd6a-81d49ef99e75
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3460135886 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_alert_test.3460135886
Directory /workspace/46.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/46.rom_ctrl_corrupt_sig_fatal_chk.3923573458
Short name T167
Test name
Test status
Simulation time 18205667653 ps
CPU time 235.61 seconds
Started Mar 07 12:55:50 PM PST 24
Finished Mar 07 12:59:46 PM PST 24
Peak memory 239664 kb
Host smart-71d3d736-98dc-450b-b55d-099f3cef0384
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3923573458 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_
corrupt_sig_fatal_chk.3923573458
Directory /workspace/46.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/46.rom_ctrl_kmac_err_chk.2453836985
Short name T280
Test name
Test status
Simulation time 2407739356 ps
CPU time 13.6 seconds
Started Mar 07 12:55:49 PM PST 24
Finished Mar 07 12:56:02 PM PST 24
Peak memory 210916 kb
Host smart-e9192e87-0a58-4a07-9a64-cd58030d522c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2453836985 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_kmac_err_chk.2453836985
Directory /workspace/46.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/46.rom_ctrl_max_throughput_chk.1474968554
Short name T355
Test name
Test status
Simulation time 2188766918 ps
CPU time 11.83 seconds
Started Mar 07 12:56:02 PM PST 24
Finished Mar 07 12:56:14 PM PST 24
Peak memory 210764 kb
Host smart-649c22e5-8ab9-4608-acdf-24131b1fd28b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1474968554 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_max_throughput_chk.1474968554
Directory /workspace/46.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/46.rom_ctrl_stress_all.315270737
Short name T138
Test name
Test status
Simulation time 3260262924 ps
CPU time 18.37 seconds
Started Mar 07 12:56:11 PM PST 24
Finished Mar 07 12:56:29 PM PST 24
Peak memory 219056 kb
Host smart-990c8dc3-8301-4b14-9c0a-bf1c13388d73
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=315270737 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 46.rom_ctrl_stress_all.315270737
Directory /workspace/46.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/47.rom_ctrl_alert_test.2265609867
Short name T279
Test name
Test status
Simulation time 920046407 ps
CPU time 4.18 seconds
Started Mar 07 12:56:04 PM PST 24
Finished Mar 07 12:56:08 PM PST 24
Peak memory 210852 kb
Host smart-93cd4fdd-3059-4003-a6a8-a577920632da
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2265609867 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_alert_test.2265609867
Directory /workspace/47.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/47.rom_ctrl_corrupt_sig_fatal_chk.2058845202
Short name T65
Test name
Test status
Simulation time 12168766711 ps
CPU time 153.95 seconds
Started Mar 07 12:56:18 PM PST 24
Finished Mar 07 12:58:52 PM PST 24
Peak memory 228048 kb
Host smart-c63a0da3-a077-48ba-9dc1-42df2a7f9167
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2058845202 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_
corrupt_sig_fatal_chk.2058845202
Directory /workspace/47.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/47.rom_ctrl_kmac_err_chk.860272986
Short name T341
Test name
Test status
Simulation time 19486913023 ps
CPU time 30.57 seconds
Started Mar 07 12:55:44 PM PST 24
Finished Mar 07 12:56:15 PM PST 24
Peak memory 211664 kb
Host smart-d9c5c5d9-52c7-4741-8955-79ecc015ab62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=860272986 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_kmac_err_chk.860272986
Directory /workspace/47.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/47.rom_ctrl_max_throughput_chk.3087802652
Short name T109
Test name
Test status
Simulation time 6894981612 ps
CPU time 13.01 seconds
Started Mar 07 12:55:39 PM PST 24
Finished Mar 07 12:55:52 PM PST 24
Peak memory 210708 kb
Host smart-2b23a44e-0028-4fd2-bb1d-20226818b361
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3087802652 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_max_throughput_chk.3087802652
Directory /workspace/47.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/47.rom_ctrl_smoke.3439384331
Short name T177
Test name
Test status
Simulation time 2792248506 ps
CPU time 21.75 seconds
Started Mar 07 12:55:59 PM PST 24
Finished Mar 07 12:56:20 PM PST 24
Peak memory 212872 kb
Host smart-ff4c803b-7443-4416-a269-869d7e8452ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3439384331 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_smoke.3439384331
Directory /workspace/47.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/47.rom_ctrl_stress_all.1182858716
Short name T267
Test name
Test status
Simulation time 267290189 ps
CPU time 15.59 seconds
Started Mar 07 12:55:46 PM PST 24
Finished Mar 07 12:56:02 PM PST 24
Peak memory 211956 kb
Host smart-6068ed71-0845-4df8-8ddf-0c530c9c552d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1182858716 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 47.rom_ctrl_stress_all.1182858716
Directory /workspace/47.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/48.rom_ctrl_alert_test.1480370968
Short name T201
Test name
Test status
Simulation time 3549086478 ps
CPU time 14.92 seconds
Started Mar 07 12:55:45 PM PST 24
Finished Mar 07 12:56:01 PM PST 24
Peak memory 210912 kb
Host smart-8a6d6081-1826-4351-8457-bc49c0a8132a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1480370968 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_alert_test.1480370968
Directory /workspace/48.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/48.rom_ctrl_corrupt_sig_fatal_chk.1654459086
Short name T247
Test name
Test status
Simulation time 66795652906 ps
CPU time 207.94 seconds
Started Mar 07 12:55:59 PM PST 24
Finished Mar 07 12:59:28 PM PST 24
Peak memory 229400 kb
Host smart-188870a9-6bb1-4710-a31d-0dc3bcdfa773
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1654459086 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_
corrupt_sig_fatal_chk.1654459086
Directory /workspace/48.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/48.rom_ctrl_kmac_err_chk.1283582479
Short name T26
Test name
Test status
Simulation time 25550995289 ps
CPU time 22.3 seconds
Started Mar 07 12:55:48 PM PST 24
Finished Mar 07 12:56:11 PM PST 24
Peak memory 211628 kb
Host smart-96f246fe-dc28-4bd0-8bd8-3996e98becf3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1283582479 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_kmac_err_chk.1283582479
Directory /workspace/48.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/48.rom_ctrl_max_throughput_chk.2582831419
Short name T152
Test name
Test status
Simulation time 7225837119 ps
CPU time 15.38 seconds
Started Mar 07 12:55:53 PM PST 24
Finished Mar 07 12:56:09 PM PST 24
Peak memory 210892 kb
Host smart-d2109394-ea03-4f18-b696-7eda2d2e3bf9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2582831419 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_max_throughput_chk.2582831419
Directory /workspace/48.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/48.rom_ctrl_smoke.3643554970
Short name T350
Test name
Test status
Simulation time 907373340 ps
CPU time 11.33 seconds
Started Mar 07 12:55:48 PM PST 24
Finished Mar 07 12:56:01 PM PST 24
Peak memory 213372 kb
Host smart-df09bc55-08ac-4118-98c2-4d34544a2947
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3643554970 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_smoke.3643554970
Directory /workspace/48.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/48.rom_ctrl_stress_all.2413987634
Short name T165
Test name
Test status
Simulation time 1627162461 ps
CPU time 18.95 seconds
Started Mar 07 12:55:43 PM PST 24
Finished Mar 07 12:56:02 PM PST 24
Peak memory 213040 kb
Host smart-9e995720-108b-480f-a416-3d1312a2ad53
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2413987634 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 48.rom_ctrl_stress_all.2413987634
Directory /workspace/48.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/49.rom_ctrl_alert_test.1478954703
Short name T361
Test name
Test status
Simulation time 1751565649 ps
CPU time 9.91 seconds
Started Mar 07 12:55:46 PM PST 24
Finished Mar 07 12:55:56 PM PST 24
Peak memory 210916 kb
Host smart-8515a806-0cbc-45fb-9f52-d3bf4b117dbe
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1478954703 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_alert_test.1478954703
Directory /workspace/49.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/49.rom_ctrl_corrupt_sig_fatal_chk.2269372097
Short name T51
Test name
Test status
Simulation time 125459313968 ps
CPU time 298.23 seconds
Started Mar 07 12:55:45 PM PST 24
Finished Mar 07 01:00:44 PM PST 24
Peak memory 212248 kb
Host smart-b8c8df9f-ae9e-408d-9a3e-c4244b3db16b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2269372097 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_
corrupt_sig_fatal_chk.2269372097
Directory /workspace/49.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/49.rom_ctrl_kmac_err_chk.113737106
Short name T156
Test name
Test status
Simulation time 8826856061 ps
CPU time 34.21 seconds
Started Mar 07 12:56:02 PM PST 24
Finished Mar 07 12:56:36 PM PST 24
Peak memory 211824 kb
Host smart-1f9c4b23-190d-4597-8f92-436c6e04c770
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=113737106 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_kmac_err_chk.113737106
Directory /workspace/49.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/49.rom_ctrl_max_throughput_chk.3043080574
Short name T320
Test name
Test status
Simulation time 1148415223 ps
CPU time 12.07 seconds
Started Mar 07 12:55:48 PM PST 24
Finished Mar 07 12:56:00 PM PST 24
Peak memory 210752 kb
Host smart-02b905dc-78dd-4e78-9085-15bd7be3ba4c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3043080574 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_max_throughput_chk.3043080574
Directory /workspace/49.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/49.rom_ctrl_smoke.3247015685
Short name T131
Test name
Test status
Simulation time 186847075 ps
CPU time 9.75 seconds
Started Mar 07 12:55:52 PM PST 24
Finished Mar 07 12:56:02 PM PST 24
Peak memory 212404 kb
Host smart-3d84d28c-9d72-472f-9eb9-c731aea35435
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3247015685 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_smoke.3247015685
Directory /workspace/49.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/49.rom_ctrl_stress_all.2894271421
Short name T135
Test name
Test status
Simulation time 3266057027 ps
CPU time 25.53 seconds
Started Mar 07 12:55:45 PM PST 24
Finished Mar 07 12:56:11 PM PST 24
Peak memory 212892 kb
Host smart-a987c79c-6f90-492f-9fec-0867dbc76057
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2894271421 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 49.rom_ctrl_stress_all.2894271421
Directory /workspace/49.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/5.rom_ctrl_alert_test.525065099
Short name T186
Test name
Test status
Simulation time 12753896103 ps
CPU time 10.64 seconds
Started Mar 07 12:55:21 PM PST 24
Finished Mar 07 12:55:31 PM PST 24
Peak memory 210944 kb
Host smart-5ede9cd6-fb4c-4b7d-b881-f0185b2c83eb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=525065099 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_alert_test.525065099
Directory /workspace/5.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/5.rom_ctrl_corrupt_sig_fatal_chk.4094070309
Short name T223
Test name
Test status
Simulation time 10265103571 ps
CPU time 84.35 seconds
Started Mar 07 12:55:18 PM PST 24
Finished Mar 07 12:56:44 PM PST 24
Peak memory 237336 kb
Host smart-0b710ad2-c4c0-40c6-b810-a77293fd3144
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4094070309 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_c
orrupt_sig_fatal_chk.4094070309
Directory /workspace/5.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/5.rom_ctrl_kmac_err_chk.789979687
Short name T69
Test name
Test status
Simulation time 3281589524 ps
CPU time 29.74 seconds
Started Mar 07 12:55:04 PM PST 24
Finished Mar 07 12:55:34 PM PST 24
Peak memory 211492 kb
Host smart-836c3c3a-021c-405b-bfc8-d85166740feb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=789979687 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_kmac_err_chk.789979687
Directory /workspace/5.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/5.rom_ctrl_max_throughput_chk.823705107
Short name T272
Test name
Test status
Simulation time 7219723303 ps
CPU time 15.71 seconds
Started Mar 07 12:55:17 PM PST 24
Finished Mar 07 12:55:34 PM PST 24
Peak memory 210812 kb
Host smart-7c64b218-8b9d-44df-b624-7365ec2cc371
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=823705107 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_max_throughput_chk.823705107
Directory /workspace/5.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/5.rom_ctrl_smoke.224756346
Short name T164
Test name
Test status
Simulation time 550360356 ps
CPU time 11.64 seconds
Started Mar 07 12:55:16 PM PST 24
Finished Mar 07 12:55:29 PM PST 24
Peak memory 212836 kb
Host smart-a7f57502-2b6b-4003-9d97-6457e54a0d85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=224756346 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_smoke.224756346
Directory /workspace/5.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/5.rom_ctrl_stress_all.3875411033
Short name T362
Test name
Test status
Simulation time 3833650255 ps
CPU time 43 seconds
Started Mar 07 12:55:26 PM PST 24
Finished Mar 07 12:56:09 PM PST 24
Peak memory 215088 kb
Host smart-7e706b5d-c50e-47be-931f-50fdec83b5af
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3875411033 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 5.rom_ctrl_stress_all.3875411033
Directory /workspace/5.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/5.rom_ctrl_stress_all_with_rand_reset.1019395424
Short name T55
Test name
Test status
Simulation time 30657834750 ps
CPU time 1129.33 seconds
Started Mar 07 12:55:24 PM PST 24
Finished Mar 07 01:14:14 PM PST 24
Peak memory 229936 kb
Host smart-73701e5a-e703-4298-87ce-ccc45a2035f1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1019395424 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_stress_all_with_rand_reset.1019395424
Directory /workspace/5.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.rom_ctrl_alert_test.2511296960
Short name T318
Test name
Test status
Simulation time 553547592 ps
CPU time 4.25 seconds
Started Mar 07 12:55:24 PM PST 24
Finished Mar 07 12:55:29 PM PST 24
Peak memory 210856 kb
Host smart-a36e13a5-3228-45e4-a13c-bed4b3b81a94
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2511296960 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_alert_test.2511296960
Directory /workspace/6.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/6.rom_ctrl_corrupt_sig_fatal_chk.2233752383
Short name T244
Test name
Test status
Simulation time 21058220764 ps
CPU time 205.79 seconds
Started Mar 07 12:55:05 PM PST 24
Finished Mar 07 12:58:31 PM PST 24
Peak memory 211724 kb
Host smart-9d261e93-b448-459b-bff3-e2faf1729218
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2233752383 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_c
orrupt_sig_fatal_chk.2233752383
Directory /workspace/6.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/6.rom_ctrl_kmac_err_chk.2221445896
Short name T38
Test name
Test status
Simulation time 15508459893 ps
CPU time 33.8 seconds
Started Mar 07 12:55:15 PM PST 24
Finished Mar 07 12:55:50 PM PST 24
Peak memory 211692 kb
Host smart-179cf3dd-e4d9-481e-85fd-cf23e64989b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2221445896 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_kmac_err_chk.2221445896
Directory /workspace/6.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/6.rom_ctrl_max_throughput_chk.2545897806
Short name T57
Test name
Test status
Simulation time 96977472 ps
CPU time 5.59 seconds
Started Mar 07 12:55:20 PM PST 24
Finished Mar 07 12:55:25 PM PST 24
Peak memory 210760 kb
Host smart-17a6dc55-f856-4c0a-ae82-62b6f4bc888b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2545897806 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_max_throughput_chk.2545897806
Directory /workspace/6.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/6.rom_ctrl_smoke.3952586297
Short name T87
Test name
Test status
Simulation time 4350624361 ps
CPU time 36.76 seconds
Started Mar 07 12:55:16 PM PST 24
Finished Mar 07 12:55:54 PM PST 24
Peak memory 213300 kb
Host smart-0c134bb8-b285-4ec7-9d52-30f06feb1d2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3952586297 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_smoke.3952586297
Directory /workspace/6.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/6.rom_ctrl_stress_all.3043677196
Short name T45
Test name
Test status
Simulation time 12019602630 ps
CPU time 108.06 seconds
Started Mar 07 12:55:12 PM PST 24
Finished Mar 07 12:57:00 PM PST 24
Peak memory 219016 kb
Host smart-cf9b3bed-e520-4617-9afa-d36edf63a75b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3043677196 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 6.rom_ctrl_stress_all.3043677196
Directory /workspace/6.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/7.rom_ctrl_alert_test.3098167344
Short name T338
Test name
Test status
Simulation time 3253119874 ps
CPU time 9.06 seconds
Started Mar 07 12:55:00 PM PST 24
Finished Mar 07 12:55:10 PM PST 24
Peak memory 210948 kb
Host smart-2626f383-8a37-4512-a115-f5376f394eae
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3098167344 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_alert_test.3098167344
Directory /workspace/7.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/7.rom_ctrl_kmac_err_chk.1569233944
Short name T174
Test name
Test status
Simulation time 13690483620 ps
CPU time 30.24 seconds
Started Mar 07 12:55:16 PM PST 24
Finished Mar 07 12:55:47 PM PST 24
Peak memory 211872 kb
Host smart-ba6a051e-b1b7-4657-921a-b18988e26f98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1569233944 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_kmac_err_chk.1569233944
Directory /workspace/7.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/7.rom_ctrl_max_throughput_chk.3650284533
Short name T336
Test name
Test status
Simulation time 354502221 ps
CPU time 7.76 seconds
Started Mar 07 12:55:23 PM PST 24
Finished Mar 07 12:55:31 PM PST 24
Peak memory 210752 kb
Host smart-ce10ab61-81c0-4c55-a750-e5b55af4e227
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3650284533 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_max_throughput_chk.3650284533
Directory /workspace/7.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/7.rom_ctrl_smoke.2748102303
Short name T276
Test name
Test status
Simulation time 3423441269 ps
CPU time 37.46 seconds
Started Mar 07 12:55:15 PM PST 24
Finished Mar 07 12:55:54 PM PST 24
Peak memory 212676 kb
Host smart-042eb2cd-7b14-4942-8850-88d18166e301
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2748102303 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_smoke.2748102303
Directory /workspace/7.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/7.rom_ctrl_stress_all.2772375765
Short name T290
Test name
Test status
Simulation time 1832311778 ps
CPU time 16.5 seconds
Started Mar 07 12:55:17 PM PST 24
Finished Mar 07 12:55:35 PM PST 24
Peak memory 214696 kb
Host smart-b4592ffc-a239-4f65-b2ac-f1fb3d4d8141
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2772375765 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 7.rom_ctrl_stress_all.2772375765
Directory /workspace/7.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/8.rom_ctrl_alert_test.2100772672
Short name T212
Test name
Test status
Simulation time 5590412099 ps
CPU time 12.32 seconds
Started Mar 07 12:55:18 PM PST 24
Finished Mar 07 12:55:32 PM PST 24
Peak memory 210944 kb
Host smart-f891582f-4fec-42f7-908c-d47d4196152e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2100772672 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_alert_test.2100772672
Directory /workspace/8.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/8.rom_ctrl_corrupt_sig_fatal_chk.1329110182
Short name T230
Test name
Test status
Simulation time 21377697811 ps
CPU time 162.29 seconds
Started Mar 07 12:55:15 PM PST 24
Finished Mar 07 12:57:59 PM PST 24
Peak memory 233588 kb
Host smart-04bb6b86-9424-4833-91ac-c55acc4d88b9
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1329110182 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_c
orrupt_sig_fatal_chk.1329110182
Directory /workspace/8.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/8.rom_ctrl_kmac_err_chk.2285220683
Short name T33
Test name
Test status
Simulation time 1241583470 ps
CPU time 17.32 seconds
Started Mar 07 12:54:53 PM PST 24
Finished Mar 07 12:55:10 PM PST 24
Peak memory 211244 kb
Host smart-9ebfecb6-05af-4b92-b2fe-047c2b134513
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2285220683 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_kmac_err_chk.2285220683
Directory /workspace/8.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/8.rom_ctrl_max_throughput_chk.99617941
Short name T256
Test name
Test status
Simulation time 7452982631 ps
CPU time 12.36 seconds
Started Mar 07 12:55:06 PM PST 24
Finished Mar 07 12:55:19 PM PST 24
Peak memory 210772 kb
Host smart-cdb96ff6-3b72-46de-8815-039e6b140c93
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=99617941 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_max_throughput_chk.99617941
Directory /workspace/8.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/8.rom_ctrl_smoke.3708782908
Short name T206
Test name
Test status
Simulation time 3524737995 ps
CPU time 29.42 seconds
Started Mar 07 12:54:56 PM PST 24
Finished Mar 07 12:55:25 PM PST 24
Peak memory 213424 kb
Host smart-7cef4fe4-058a-4be4-a4d6-a45ac11a8d2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3708782908 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_smoke.3708782908
Directory /workspace/8.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/8.rom_ctrl_stress_all.3972293530
Short name T352
Test name
Test status
Simulation time 3750211366 ps
CPU time 31.72 seconds
Started Mar 07 12:55:12 PM PST 24
Finished Mar 07 12:55:44 PM PST 24
Peak memory 215136 kb
Host smart-0179a431-492e-4290-bfac-498635b22911
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3972293530 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 8.rom_ctrl_stress_all.3972293530
Directory /workspace/8.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/9.rom_ctrl_alert_test.3277735395
Short name T278
Test name
Test status
Simulation time 437375000 ps
CPU time 4.22 seconds
Started Mar 07 12:55:10 PM PST 24
Finished Mar 07 12:55:14 PM PST 24
Peak memory 210824 kb
Host smart-d3573701-efb2-4cd7-98e8-8fea967f5420
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3277735395 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_alert_test.3277735395
Directory /workspace/9.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/9.rom_ctrl_corrupt_sig_fatal_chk.1917374515
Short name T196
Test name
Test status
Simulation time 57573995333 ps
CPU time 308.34 seconds
Started Mar 07 12:55:22 PM PST 24
Finished Mar 07 01:00:31 PM PST 24
Peak memory 213232 kb
Host smart-decb58bd-da6b-4ffc-93f1-5a52436d1720
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1917374515 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_c
orrupt_sig_fatal_chk.1917374515
Directory /workspace/9.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/9.rom_ctrl_kmac_err_chk.258771633
Short name T312
Test name
Test status
Simulation time 21649329332 ps
CPU time 21 seconds
Started Mar 07 12:55:14 PM PST 24
Finished Mar 07 12:55:35 PM PST 24
Peak memory 210888 kb
Host smart-4c5d2acf-765b-4454-9116-96addf2e9b62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=258771633 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_kmac_err_chk.258771633
Directory /workspace/9.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/9.rom_ctrl_max_throughput_chk.2716599625
Short name T62
Test name
Test status
Simulation time 8235005641 ps
CPU time 12.71 seconds
Started Mar 07 12:55:22 PM PST 24
Finished Mar 07 12:55:35 PM PST 24
Peak memory 210768 kb
Host smart-8891a5d3-9dbf-40ba-9264-f53a30e26f78
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2716599625 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_max_throughput_chk.2716599625
Directory /workspace/9.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/9.rom_ctrl_smoke.834181647
Short name T232
Test name
Test status
Simulation time 30823077896 ps
CPU time 24.95 seconds
Started Mar 07 12:55:12 PM PST 24
Finished Mar 07 12:55:37 PM PST 24
Peak memory 213556 kb
Host smart-db28e9a8-3b2d-4f2e-a938-3a309b32986a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=834181647 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_smoke.834181647
Directory /workspace/9.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/9.rom_ctrl_stress_all.1668414411
Short name T301
Test name
Test status
Simulation time 1115348900 ps
CPU time 19.54 seconds
Started Mar 07 12:55:28 PM PST 24
Finished Mar 07 12:55:49 PM PST 24
Peak memory 213276 kb
Host smart-b9fc444e-95fa-4dcd-bd60-6d8713dddc4c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1668414411 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 9.rom_ctrl_stress_all.1668414411
Directory /workspace/9.rom_ctrl_stress_all/latest
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