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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
97.45 97.04 92.65 97.88 100.00 98.37 98.04 98.14


Total test records in report: 464
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html
T299 /workspace/coverage/default/43.rom_ctrl_smoke.4256858208 Mar 12 12:34:27 PM PDT 24 Mar 12 12:34:48 PM PDT 24 11190783985 ps
T300 /workspace/coverage/default/21.rom_ctrl_smoke.3226256008 Mar 12 12:33:29 PM PDT 24 Mar 12 12:33:39 PM PDT 24 371219706 ps
T301 /workspace/coverage/default/42.rom_ctrl_stress_all.38445361 Mar 12 12:34:23 PM PDT 24 Mar 12 12:34:45 PM PDT 24 398761620 ps
T302 /workspace/coverage/default/6.rom_ctrl_max_throughput_chk.1571560212 Mar 12 12:33:10 PM PDT 24 Mar 12 12:33:20 PM PDT 24 899184174 ps
T303 /workspace/coverage/default/24.rom_ctrl_alert_test.1347610474 Mar 12 12:33:46 PM PDT 24 Mar 12 12:34:02 PM PDT 24 1728392355 ps
T304 /workspace/coverage/default/25.rom_ctrl_max_throughput_chk.1351884767 Mar 12 12:33:50 PM PDT 24 Mar 12 12:34:00 PM PDT 24 3206254349 ps
T305 /workspace/coverage/default/23.rom_ctrl_stress_all_with_rand_reset.1111126566 Mar 12 12:33:39 PM PDT 24 Mar 12 01:08:28 PM PDT 24 56091379547 ps
T306 /workspace/coverage/default/30.rom_ctrl_smoke.2622077900 Mar 12 12:33:55 PM PDT 24 Mar 12 12:34:29 PM PDT 24 6191160080 ps
T307 /workspace/coverage/default/17.rom_ctrl_alert_test.1313088256 Mar 12 12:33:24 PM PDT 24 Mar 12 12:33:29 PM PDT 24 346631007 ps
T308 /workspace/coverage/default/5.rom_ctrl_corrupt_sig_fatal_chk.2746897821 Mar 12 12:33:06 PM PDT 24 Mar 12 12:36:17 PM PDT 24 47160524061 ps
T309 /workspace/coverage/default/2.rom_ctrl_stress_all.1861960046 Mar 12 12:32:57 PM PDT 24 Mar 12 12:33:59 PM PDT 24 21872417599 ps
T310 /workspace/coverage/default/0.rom_ctrl_max_throughput_chk.335284254 Mar 12 12:33:07 PM PDT 24 Mar 12 12:33:17 PM PDT 24 957437548 ps
T311 /workspace/coverage/default/5.rom_ctrl_kmac_err_chk.1302976754 Mar 12 12:33:08 PM PDT 24 Mar 12 12:33:39 PM PDT 24 3504426435 ps
T312 /workspace/coverage/default/1.rom_ctrl_kmac_err_chk.2399620869 Mar 12 12:32:57 PM PDT 24 Mar 12 12:33:29 PM PDT 24 8191521004 ps
T313 /workspace/coverage/default/3.rom_ctrl_max_throughput_chk.260657484 Mar 12 12:32:57 PM PDT 24 Mar 12 12:33:13 PM PDT 24 7664136175 ps
T314 /workspace/coverage/default/33.rom_ctrl_max_throughput_chk.3585985619 Mar 12 12:34:19 PM PDT 24 Mar 12 12:34:31 PM PDT 24 7656804956 ps
T315 /workspace/coverage/default/33.rom_ctrl_smoke.2795143038 Mar 12 12:34:17 PM PDT 24 Mar 12 12:34:52 PM PDT 24 6105359365 ps
T316 /workspace/coverage/default/13.rom_ctrl_max_throughput_chk.3725838102 Mar 12 12:33:18 PM PDT 24 Mar 12 12:33:23 PM PDT 24 346759498 ps
T317 /workspace/coverage/default/44.rom_ctrl_smoke.1284761428 Mar 12 12:34:32 PM PDT 24 Mar 12 12:35:11 PM PDT 24 77724103101 ps
T318 /workspace/coverage/default/21.rom_ctrl_stress_all.3486843491 Mar 12 12:33:51 PM PDT 24 Mar 12 12:35:12 PM PDT 24 8360755885 ps
T319 /workspace/coverage/default/41.rom_ctrl_max_throughput_chk.3384205501 Mar 12 12:34:24 PM PDT 24 Mar 12 12:34:30 PM PDT 24 100693889 ps
T320 /workspace/coverage/default/8.rom_ctrl_max_throughput_chk.2308882939 Mar 12 12:33:18 PM PDT 24 Mar 12 12:33:29 PM PDT 24 1180090824 ps
T321 /workspace/coverage/default/4.rom_ctrl_corrupt_sig_fatal_chk.2255628710 Mar 12 12:32:56 PM PDT 24 Mar 12 12:35:15 PM PDT 24 156715536062 ps
T322 /workspace/coverage/default/19.rom_ctrl_kmac_err_chk.3601075745 Mar 12 12:33:26 PM PDT 24 Mar 12 12:33:57 PM PDT 24 14317671298 ps
T323 /workspace/coverage/default/26.rom_ctrl_corrupt_sig_fatal_chk.2813211988 Mar 12 12:33:54 PM PDT 24 Mar 12 12:41:04 PM PDT 24 660697993987 ps
T324 /workspace/coverage/default/39.rom_ctrl_alert_test.3110998487 Mar 12 12:34:18 PM PDT 24 Mar 12 12:34:31 PM PDT 24 9443421803 ps
T325 /workspace/coverage/default/34.rom_ctrl_corrupt_sig_fatal_chk.1568379744 Mar 12 12:34:20 PM PDT 24 Mar 12 12:35:46 PM PDT 24 4259398338 ps
T326 /workspace/coverage/default/8.rom_ctrl_kmac_err_chk.3273510930 Mar 12 12:33:26 PM PDT 24 Mar 12 12:33:55 PM PDT 24 12953997343 ps
T327 /workspace/coverage/default/13.rom_ctrl_alert_test.481916283 Mar 12 12:33:18 PM PDT 24 Mar 12 12:33:29 PM PDT 24 3024869312 ps
T328 /workspace/coverage/default/45.rom_ctrl_corrupt_sig_fatal_chk.766285075 Mar 12 12:34:27 PM PDT 24 Mar 12 12:38:06 PM PDT 24 18151129961 ps
T329 /workspace/coverage/default/46.rom_ctrl_alert_test.3232561474 Mar 12 12:34:33 PM PDT 24 Mar 12 12:34:45 PM PDT 24 7688004429 ps
T330 /workspace/coverage/default/36.rom_ctrl_kmac_err_chk.1130329591 Mar 12 12:34:16 PM PDT 24 Mar 12 12:34:42 PM PDT 24 2851976338 ps
T331 /workspace/coverage/default/39.rom_ctrl_corrupt_sig_fatal_chk.3555951115 Mar 12 12:34:20 PM PDT 24 Mar 12 12:36:50 PM PDT 24 54918078266 ps
T332 /workspace/coverage/default/2.rom_ctrl_max_throughput_chk.2186946365 Mar 12 12:32:57 PM PDT 24 Mar 12 12:33:03 PM PDT 24 196322813 ps
T333 /workspace/coverage/default/30.rom_ctrl_corrupt_sig_fatal_chk.432073263 Mar 12 12:34:06 PM PDT 24 Mar 12 12:38:12 PM PDT 24 25422502527 ps
T334 /workspace/coverage/default/21.rom_ctrl_max_throughput_chk.1634848160 Mar 12 12:33:52 PM PDT 24 Mar 12 12:33:59 PM PDT 24 214511223 ps
T335 /workspace/coverage/default/7.rom_ctrl_kmac_err_chk.834600375 Mar 12 12:33:07 PM PDT 24 Mar 12 12:33:25 PM PDT 24 1333993371 ps
T336 /workspace/coverage/default/30.rom_ctrl_stress_all.642772041 Mar 12 12:34:05 PM PDT 24 Mar 12 12:34:15 PM PDT 24 366485489 ps
T337 /workspace/coverage/default/44.rom_ctrl_max_throughput_chk.3510281754 Mar 12 12:34:26 PM PDT 24 Mar 12 12:34:38 PM PDT 24 1169835470 ps
T338 /workspace/coverage/default/28.rom_ctrl_smoke.601741109 Mar 12 12:34:02 PM PDT 24 Mar 12 12:34:24 PM PDT 24 6212657633 ps
T339 /workspace/coverage/default/6.rom_ctrl_stress_all.3398150655 Mar 12 12:33:06 PM PDT 24 Mar 12 12:34:07 PM PDT 24 5124364997 ps
T340 /workspace/coverage/default/27.rom_ctrl_kmac_err_chk.4167181470 Mar 12 12:33:55 PM PDT 24 Mar 12 12:34:19 PM PDT 24 3135191652 ps
T341 /workspace/coverage/default/44.rom_ctrl_kmac_err_chk.3058737741 Mar 12 12:34:26 PM PDT 24 Mar 12 12:34:55 PM PDT 24 3630139709 ps
T342 /workspace/coverage/default/9.rom_ctrl_stress_all_with_rand_reset.2600872563 Mar 12 12:33:22 PM PDT 24 Mar 12 01:25:08 PM PDT 24 83925534631 ps
T343 /workspace/coverage/default/28.rom_ctrl_kmac_err_chk.3106873371 Mar 12 12:33:59 PM PDT 24 Mar 12 12:34:14 PM PDT 24 3756145894 ps
T344 /workspace/coverage/default/17.rom_ctrl_stress_all.172437080 Mar 12 12:33:33 PM PDT 24 Mar 12 12:34:00 PM PDT 24 1814660427 ps
T345 /workspace/coverage/default/42.rom_ctrl_max_throughput_chk.1678648154 Mar 12 12:34:28 PM PDT 24 Mar 12 12:34:46 PM PDT 24 2108300234 ps
T346 /workspace/coverage/default/39.rom_ctrl_kmac_err_chk.136549071 Mar 12 12:34:22 PM PDT 24 Mar 12 12:34:47 PM PDT 24 2611571356 ps
T347 /workspace/coverage/default/26.rom_ctrl_stress_all.1663996092 Mar 12 12:33:46 PM PDT 24 Mar 12 12:34:11 PM PDT 24 389030164 ps
T348 /workspace/coverage/default/20.rom_ctrl_alert_test.2824356708 Mar 12 12:33:27 PM PDT 24 Mar 12 12:33:43 PM PDT 24 9283011822 ps
T349 /workspace/coverage/default/27.rom_ctrl_max_throughput_chk.3918552664 Mar 12 12:33:55 PM PDT 24 Mar 12 12:34:14 PM PDT 24 8064403240 ps
T350 /workspace/coverage/default/11.rom_ctrl_kmac_err_chk.374585813 Mar 12 12:33:19 PM PDT 24 Mar 12 12:33:28 PM PDT 24 175590463 ps
T351 /workspace/coverage/default/2.rom_ctrl_smoke.3667125931 Mar 12 12:32:57 PM PDT 24 Mar 12 12:33:22 PM PDT 24 2647358798 ps
T352 /workspace/coverage/default/25.rom_ctrl_stress_all.1734888717 Mar 12 12:33:48 PM PDT 24 Mar 12 12:34:24 PM PDT 24 18545713400 ps
T122 /workspace/coverage/default/12.rom_ctrl_stress_all_with_rand_reset.785491897 Mar 12 12:33:17 PM PDT 24 Mar 12 12:51:39 PM PDT 24 25962500158 ps
T353 /workspace/coverage/default/4.rom_ctrl_kmac_err_chk.3589789907 Mar 12 12:33:02 PM PDT 24 Mar 12 12:33:31 PM PDT 24 43297186115 ps
T354 /workspace/coverage/default/30.rom_ctrl_alert_test.2225844217 Mar 12 12:34:06 PM PDT 24 Mar 12 12:34:13 PM PDT 24 426638875 ps
T355 /workspace/coverage/default/7.rom_ctrl_corrupt_sig_fatal_chk.2975983573 Mar 12 12:33:06 PM PDT 24 Mar 12 12:36:11 PM PDT 24 78663287556 ps
T356 /workspace/coverage/default/16.rom_ctrl_max_throughput_chk.1382199048 Mar 12 12:33:47 PM PDT 24 Mar 12 12:33:58 PM PDT 24 987813467 ps
T357 /workspace/coverage/default/42.rom_ctrl_alert_test.2386425849 Mar 12 12:34:27 PM PDT 24 Mar 12 12:34:33 PM PDT 24 175352408 ps
T358 /workspace/coverage/default/45.rom_ctrl_kmac_err_chk.4045809557 Mar 12 12:34:25 PM PDT 24 Mar 12 12:34:49 PM PDT 24 2450494573 ps
T359 /workspace/coverage/default/18.rom_ctrl_alert_test.578089570 Mar 12 12:33:25 PM PDT 24 Mar 12 12:33:42 PM PDT 24 2096860964 ps
T360 /workspace/coverage/default/16.rom_ctrl_kmac_err_chk.3414650585 Mar 12 12:33:27 PM PDT 24 Mar 12 12:33:53 PM PDT 24 2616026484 ps
T361 /workspace/coverage/default/19.rom_ctrl_smoke.747066907 Mar 12 12:33:30 PM PDT 24 Mar 12 12:33:41 PM PDT 24 1388802883 ps
T362 /workspace/coverage/default/26.rom_ctrl_kmac_err_chk.753270753 Mar 12 12:33:54 PM PDT 24 Mar 12 12:34:19 PM PDT 24 3128149054 ps
T363 /workspace/coverage/default/49.rom_ctrl_stress_all.2026441818 Mar 12 12:34:36 PM PDT 24 Mar 12 12:35:15 PM PDT 24 8610312382 ps
T364 /workspace/coverage/default/10.rom_ctrl_corrupt_sig_fatal_chk.3022947873 Mar 12 12:33:19 PM PDT 24 Mar 12 12:36:17 PM PDT 24 22012578300 ps
T365 /workspace/coverage/default/22.rom_ctrl_stress_all.2445027090 Mar 12 12:33:38 PM PDT 24 Mar 12 12:33:59 PM PDT 24 1584834113 ps
T366 /workspace/coverage/default/15.rom_ctrl_kmac_err_chk.929351899 Mar 12 12:33:26 PM PDT 24 Mar 12 12:33:36 PM PDT 24 176021268 ps
T367 /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_errors.1115531257 Mar 12 12:48:58 PM PDT 24 Mar 12 12:49:07 PM PDT 24 669914549 ps
T368 /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_errors.2247493630 Mar 12 12:48:39 PM PDT 24 Mar 12 12:48:54 PM PDT 24 6104530485 ps
T369 /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_errors.1417884137 Mar 12 12:48:32 PM PDT 24 Mar 12 12:48:51 PM PDT 24 1759779165 ps
T370 /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_walk.1490579910 Mar 12 12:48:33 PM PDT 24 Mar 12 12:48:40 PM PDT 24 2727635403 ps
T371 /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_errors.560028424 Mar 12 12:48:56 PM PDT 24 Mar 12 12:49:10 PM PDT 24 10210136196 ps
T64 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_bit_bash.2050231546 Mar 12 12:48:28 PM PDT 24 Mar 12 12:48:39 PM PDT 24 1065961398 ps
T65 /workspace/coverage/cover_reg_top/15.rom_ctrl_same_csr_outstanding.1918422470 Mar 12 12:48:53 PM PDT 24 Mar 12 12:49:02 PM PDT 24 816208125 ps
T66 /workspace/coverage/cover_reg_top/2.rom_ctrl_same_csr_outstanding.1976379634 Mar 12 12:48:34 PM PDT 24 Mar 12 12:48:49 PM PDT 24 12046960695 ps
T73 /workspace/coverage/cover_reg_top/1.rom_ctrl_passthru_mem_tl_intg_err.3420915251 Mar 12 12:48:34 PM PDT 24 Mar 12 12:49:01 PM PDT 24 2445623579 ps
T74 /workspace/coverage/cover_reg_top/19.rom_ctrl_same_csr_outstanding.3598627200 Mar 12 12:49:07 PM PDT 24 Mar 12 12:49:18 PM PDT 24 8890768196 ps
T116 /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_rw.1551406212 Mar 12 12:49:01 PM PDT 24 Mar 12 12:49:09 PM PDT 24 1203621512 ps
T372 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_hw_reset.2027649149 Mar 12 12:48:30 PM PDT 24 Mar 12 12:48:45 PM PDT 24 3401205997 ps
T110 /workspace/coverage/cover_reg_top/0.rom_ctrl_same_csr_outstanding.1267099734 Mar 12 12:48:35 PM PDT 24 Mar 12 12:48:43 PM PDT 24 926703314 ps
T117 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_aliasing.2414425476 Mar 12 12:48:55 PM PDT 24 Mar 12 12:49:06 PM PDT 24 1107188909 ps
T75 /workspace/coverage/cover_reg_top/18.rom_ctrl_same_csr_outstanding.16817705 Mar 12 12:49:11 PM PDT 24 Mar 12 12:49:26 PM PDT 24 11035164962 ps
T373 /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_errors.992798768 Mar 12 12:48:50 PM PDT 24 Mar 12 12:48:57 PM PDT 24 87177558 ps
T76 /workspace/coverage/cover_reg_top/14.rom_ctrl_passthru_mem_tl_intg_err.995193915 Mar 12 12:48:55 PM PDT 24 Mar 12 12:49:21 PM PDT 24 1173724257 ps
T374 /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_rw.1563203215 Mar 12 12:49:02 PM PDT 24 Mar 12 12:49:15 PM PDT 24 1415869228 ps
T111 /workspace/coverage/cover_reg_top/3.rom_ctrl_same_csr_outstanding.1825596096 Mar 12 12:48:44 PM PDT 24 Mar 12 12:48:52 PM PDT 24 1093342367 ps
T375 /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_mem_rw_with_rand_reset.1971621638 Mar 12 12:48:56 PM PDT 24 Mar 12 12:49:09 PM PDT 24 2941535706 ps
T376 /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_errors.1075650401 Mar 12 12:48:45 PM PDT 24 Mar 12 12:48:53 PM PDT 24 107840348 ps
T377 /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_partial_access.4170577423 Mar 12 12:48:46 PM PDT 24 Mar 12 12:48:58 PM PDT 24 5302068526 ps
T120 /workspace/coverage/cover_reg_top/4.rom_ctrl_passthru_mem_tl_intg_err.350470052 Mar 12 12:48:40 PM PDT 24 Mar 12 12:49:25 PM PDT 24 18443931354 ps
T112 /workspace/coverage/cover_reg_top/10.rom_ctrl_same_csr_outstanding.2561273818 Mar 12 12:48:39 PM PDT 24 Mar 12 12:48:53 PM PDT 24 9684973294 ps
T113 /workspace/coverage/cover_reg_top/1.rom_ctrl_same_csr_outstanding.1909183590 Mar 12 12:48:32 PM PDT 24 Mar 12 12:48:48 PM PDT 24 6717097054 ps
T378 /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_mem_rw_with_rand_reset.2053726937 Mar 12 12:49:08 PM PDT 24 Mar 12 12:49:16 PM PDT 24 475036109 ps
T114 /workspace/coverage/cover_reg_top/7.rom_ctrl_same_csr_outstanding.1618531807 Mar 12 12:48:38 PM PDT 24 Mar 12 12:48:52 PM PDT 24 2780331119 ps
T379 /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_walk.4259742207 Mar 12 12:48:34 PM PDT 24 Mar 12 12:48:49 PM PDT 24 4109754261 ps
T61 /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_intg_err.2620318136 Mar 12 12:48:48 PM PDT 24 Mar 12 12:49:25 PM PDT 24 699232670 ps
T380 /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_errors.2322656342 Mar 12 12:48:58 PM PDT 24 Mar 12 12:49:18 PM PDT 24 8467565235 ps
T381 /workspace/coverage/cover_reg_top/8.rom_ctrl_same_csr_outstanding.93114675 Mar 12 12:48:46 PM PDT 24 Mar 12 12:48:58 PM PDT 24 10956764936 ps
T77 /workspace/coverage/cover_reg_top/17.rom_ctrl_same_csr_outstanding.1416188658 Mar 12 12:49:05 PM PDT 24 Mar 12 12:49:20 PM PDT 24 1840060419 ps
T78 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_bit_bash.2175487390 Mar 12 12:48:29 PM PDT 24 Mar 12 12:48:45 PM PDT 24 14155900440 ps
T382 /workspace/coverage/cover_reg_top/15.rom_ctrl_passthru_mem_tl_intg_err.318715369 Mar 12 12:48:55 PM PDT 24 Mar 12 12:49:23 PM PDT 24 1106453306 ps
T383 /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_errors.2457267845 Mar 12 12:48:41 PM PDT 24 Mar 12 12:48:52 PM PDT 24 981617148 ps
T384 /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_mem_rw_with_rand_reset.2290397055 Mar 12 12:49:10 PM PDT 24 Mar 12 12:49:20 PM PDT 24 693070190 ps
T62 /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_intg_err.2907485754 Mar 12 12:48:42 PM PDT 24 Mar 12 12:50:03 PM PDT 24 2386454006 ps
T385 /workspace/coverage/cover_reg_top/9.rom_ctrl_same_csr_outstanding.3315126966 Mar 12 12:48:46 PM PDT 24 Mar 12 12:49:01 PM PDT 24 1622669415 ps
T63 /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_intg_err.3172840373 Mar 12 12:48:56 PM PDT 24 Mar 12 12:49:39 PM PDT 24 2671872006 ps
T386 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_bit_bash.2146700632 Mar 12 12:48:30 PM PDT 24 Mar 12 12:48:37 PM PDT 24 684082523 ps
T387 /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_walk.1170050708 Mar 12 12:48:29 PM PDT 24 Mar 12 12:48:43 PM PDT 24 2500066477 ps
T123 /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_intg_err.717347653 Mar 12 12:48:31 PM PDT 24 Mar 12 12:49:18 PM PDT 24 1803473453 ps
T388 /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_errors.1168235456 Mar 12 12:48:40 PM PDT 24 Mar 12 12:48:59 PM PDT 24 8650691997 ps
T79 /workspace/coverage/cover_reg_top/2.rom_ctrl_passthru_mem_tl_intg_err.3363952593 Mar 12 12:48:34 PM PDT 24 Mar 12 12:49:37 PM PDT 24 8026939167 ps
T389 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_hw_reset.3286765504 Mar 12 12:48:39 PM PDT 24 Mar 12 12:48:48 PM PDT 24 254102570 ps
T390 /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_errors.2533032824 Mar 12 12:49:00 PM PDT 24 Mar 12 12:49:16 PM PDT 24 5856508390 ps
T391 /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_rw.3607347670 Mar 12 12:48:51 PM PDT 24 Mar 12 12:49:05 PM PDT 24 10483627774 ps
T392 /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_rw.2848373929 Mar 12 12:48:52 PM PDT 24 Mar 12 12:49:06 PM PDT 24 4521919199 ps
T80 /workspace/coverage/cover_reg_top/13.rom_ctrl_passthru_mem_tl_intg_err.1825894067 Mar 12 12:48:54 PM PDT 24 Mar 12 12:50:02 PM PDT 24 7277244260 ps
T131 /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_intg_err.4285075308 Mar 12 12:48:58 PM PDT 24 Mar 12 12:50:10 PM PDT 24 5406018875 ps
T393 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_rw.2402071400 Mar 12 12:48:30 PM PDT 24 Mar 12 12:48:34 PM PDT 24 87239166 ps
T394 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_hw_reset.1363472643 Mar 12 12:48:36 PM PDT 24 Mar 12 12:48:46 PM PDT 24 677375667 ps
T395 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_mem_rw_with_rand_reset.3544764384 Mar 12 12:48:48 PM PDT 24 Mar 12 12:48:56 PM PDT 24 1310546340 ps
T396 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_mem_rw_with_rand_reset.1889904744 Mar 12 12:48:37 PM PDT 24 Mar 12 12:48:51 PM PDT 24 6680631410 ps
T397 /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_rw.2118112863 Mar 12 12:48:54 PM PDT 24 Mar 12 12:48:58 PM PDT 24 334000563 ps
T127 /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_intg_err.4061659027 Mar 12 12:48:39 PM PDT 24 Mar 12 12:49:19 PM PDT 24 1397995712 ps
T398 /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_mem_rw_with_rand_reset.4153219999 Mar 12 12:48:53 PM PDT 24 Mar 12 12:49:06 PM PDT 24 3291154860 ps
T399 /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_mem_rw_with_rand_reset.1267772596 Mar 12 12:48:40 PM PDT 24 Mar 12 12:48:48 PM PDT 24 364164215 ps
T81 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_rw.920032478 Mar 12 12:48:47 PM PDT 24 Mar 12 12:48:54 PM PDT 24 344775165 ps
T90 /workspace/coverage/cover_reg_top/5.rom_ctrl_passthru_mem_tl_intg_err.181393476 Mar 12 12:48:45 PM PDT 24 Mar 12 12:49:13 PM PDT 24 2269855948 ps
T95 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_bit_bash.2933006417 Mar 12 12:48:33 PM PDT 24 Mar 12 12:48:48 PM PDT 24 1848931482 ps
T400 /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_partial_access.1634563258 Mar 12 12:48:35 PM PDT 24 Mar 12 12:48:45 PM PDT 24 4136788652 ps
T124 /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_intg_err.555002465 Mar 12 12:48:31 PM PDT 24 Mar 12 12:49:44 PM PDT 24 556140523 ps
T401 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_rw.3104670114 Mar 12 12:48:39 PM PDT 24 Mar 12 12:48:43 PM PDT 24 347688555 ps
T125 /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_intg_err.2917716937 Mar 12 12:49:14 PM PDT 24 Mar 12 12:49:52 PM PDT 24 996350388 ps
T402 /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_rw.3135027060 Mar 12 12:48:59 PM PDT 24 Mar 12 12:49:13 PM PDT 24 1621708996 ps
T403 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_aliasing.2419732593 Mar 12 12:48:32 PM PDT 24 Mar 12 12:48:46 PM PDT 24 3508953830 ps
T404 /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_rw.176127959 Mar 12 12:48:48 PM PDT 24 Mar 12 12:49:04 PM PDT 24 31506886506 ps
T405 /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_partial_access.2037320253 Mar 12 12:48:32 PM PDT 24 Mar 12 12:48:36 PM PDT 24 396878475 ps
T406 /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_errors.738280086 Mar 12 12:49:11 PM PDT 24 Mar 12 12:49:20 PM PDT 24 250502214 ps
T91 /workspace/coverage/cover_reg_top/9.rom_ctrl_passthru_mem_tl_intg_err.1961472304 Mar 12 12:48:37 PM PDT 24 Mar 12 12:49:41 PM PDT 24 14786006767 ps
T92 /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_rw.3571321116 Mar 12 12:48:40 PM PDT 24 Mar 12 12:48:56 PM PDT 24 2162941690 ps
T407 /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_rw.1127760560 Mar 12 12:48:51 PM PDT 24 Mar 12 12:49:02 PM PDT 24 2391002735 ps
T408 /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_intg_err.95648169 Mar 12 12:48:57 PM PDT 24 Mar 12 12:49:40 PM PDT 24 4847412859 ps
T93 /workspace/coverage/cover_reg_top/16.rom_ctrl_passthru_mem_tl_intg_err.2965552809 Mar 12 12:49:05 PM PDT 24 Mar 12 12:50:12 PM PDT 24 39169595865 ps
T409 /workspace/coverage/cover_reg_top/4.rom_ctrl_same_csr_outstanding.2208522085 Mar 12 12:48:31 PM PDT 24 Mar 12 12:48:43 PM PDT 24 2396822626 ps
T94 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_hw_reset.2986386564 Mar 12 12:48:33 PM PDT 24 Mar 12 12:48:45 PM PDT 24 4074420958 ps
T128 /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_intg_err.1477210211 Mar 12 12:49:08 PM PDT 24 Mar 12 12:50:22 PM PDT 24 1497769813 ps
T410 /workspace/coverage/cover_reg_top/16.rom_ctrl_same_csr_outstanding.3017998151 Mar 12 12:49:06 PM PDT 24 Mar 12 12:49:16 PM PDT 24 1811060610 ps
T411 /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_rw.2984945199 Mar 12 12:48:58 PM PDT 24 Mar 12 12:49:09 PM PDT 24 4425398743 ps
T132 /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_intg_err.594986919 Mar 12 12:48:36 PM PDT 24 Mar 12 12:49:46 PM PDT 24 2016802452 ps
T412 /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_walk.661095237 Mar 12 12:48:58 PM PDT 24 Mar 12 12:49:05 PM PDT 24 7636460124 ps
T98 /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_rw.2003661052 Mar 12 12:48:59 PM PDT 24 Mar 12 12:49:03 PM PDT 24 87540736 ps
T413 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_mem_rw_with_rand_reset.1465784338 Mar 12 12:48:39 PM PDT 24 Mar 12 12:48:55 PM PDT 24 4223292522 ps
T414 /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_intg_err.2034467624 Mar 12 12:48:37 PM PDT 24 Mar 12 12:49:22 PM PDT 24 1585073321 ps
T101 /workspace/coverage/cover_reg_top/19.rom_ctrl_passthru_mem_tl_intg_err.3995253537 Mar 12 12:49:10 PM PDT 24 Mar 12 12:50:05 PM PDT 24 18342540546 ps
T415 /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_mem_rw_with_rand_reset.2813037380 Mar 12 12:48:51 PM PDT 24 Mar 12 12:48:55 PM PDT 24 378411428 ps
T416 /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_mem_rw_with_rand_reset.2123502678 Mar 12 12:48:37 PM PDT 24 Mar 12 12:48:42 PM PDT 24 202556030 ps
T417 /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_partial_access.3933098591 Mar 12 12:48:30 PM PDT 24 Mar 12 12:48:39 PM PDT 24 2799128892 ps
T418 /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_walk.639209434 Mar 12 12:48:28 PM PDT 24 Mar 12 12:48:38 PM PDT 24 1044436984 ps
T419 /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_errors.605935264 Mar 12 12:48:33 PM PDT 24 Mar 12 12:48:41 PM PDT 24 171919987 ps
T420 /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_errors.3727144890 Mar 12 12:49:08 PM PDT 24 Mar 12 12:49:24 PM PDT 24 2436722930 ps
T99 /workspace/coverage/cover_reg_top/8.rom_ctrl_passthru_mem_tl_intg_err.3093636639 Mar 12 12:48:49 PM PDT 24 Mar 12 12:49:53 PM PDT 24 31366662730 ps
T421 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_aliasing.2436972657 Mar 12 12:48:47 PM PDT 24 Mar 12 12:48:58 PM PDT 24 5852516264 ps
T422 /workspace/coverage/cover_reg_top/12.rom_ctrl_passthru_mem_tl_intg_err.303782904 Mar 12 12:48:39 PM PDT 24 Mar 12 12:49:11 PM PDT 24 3607159900 ps
T423 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_hw_reset.1619785962 Mar 12 12:48:35 PM PDT 24 Mar 12 12:48:41 PM PDT 24 91344732 ps
T133 /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_intg_err.1394100127 Mar 12 12:49:12 PM PDT 24 Mar 12 12:50:26 PM PDT 24 6019905848 ps
T424 /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_mem_rw_with_rand_reset.762793053 Mar 12 12:49:06 PM PDT 24 Mar 12 12:49:14 PM PDT 24 1345806198 ps
T129 /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_intg_err.2369435365 Mar 12 12:48:41 PM PDT 24 Mar 12 12:49:52 PM PDT 24 5765706989 ps
T425 /workspace/coverage/cover_reg_top/11.rom_ctrl_same_csr_outstanding.4259913244 Mar 12 12:48:39 PM PDT 24 Mar 12 12:48:53 PM PDT 24 1654374316 ps
T121 /workspace/coverage/cover_reg_top/11.rom_ctrl_passthru_mem_tl_intg_err.1914638796 Mar 12 12:48:38 PM PDT 24 Mar 12 12:49:39 PM PDT 24 9373222377 ps
T100 /workspace/coverage/cover_reg_top/3.rom_ctrl_passthru_mem_tl_intg_err.3459692677 Mar 12 12:48:31 PM PDT 24 Mar 12 12:49:53 PM PDT 24 38039802466 ps
T426 /workspace/coverage/cover_reg_top/5.rom_ctrl_same_csr_outstanding.351556023 Mar 12 12:48:37 PM PDT 24 Mar 12 12:48:53 PM PDT 24 1962917762 ps
T427 /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_errors.3678250716 Mar 12 12:48:46 PM PDT 24 Mar 12 12:48:55 PM PDT 24 695352783 ps
T428 /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_mem_rw_with_rand_reset.4069546027 Mar 12 12:49:09 PM PDT 24 Mar 12 12:49:24 PM PDT 24 1692985028 ps
T429 /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_mem_rw_with_rand_reset.3710825673 Mar 12 12:48:56 PM PDT 24 Mar 12 12:49:12 PM PDT 24 1810916720 ps
T430 /workspace/coverage/cover_reg_top/6.rom_ctrl_same_csr_outstanding.1073223504 Mar 12 12:48:39 PM PDT 24 Mar 12 12:48:46 PM PDT 24 100532398 ps
T431 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_bit_bash.318258392 Mar 12 12:48:34 PM PDT 24 Mar 12 12:48:40 PM PDT 24 168480062 ps
T432 /workspace/coverage/cover_reg_top/7.rom_ctrl_passthru_mem_tl_intg_err.3387673362 Mar 12 12:48:48 PM PDT 24 Mar 12 12:49:33 PM PDT 24 4276124576 ps
T433 /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_rw.2871337685 Mar 12 12:48:38 PM PDT 24 Mar 12 12:48:46 PM PDT 24 2462998092 ps
T434 /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_errors.801685675 Mar 12 12:49:07 PM PDT 24 Mar 12 12:49:28 PM PDT 24 10990062549 ps
T435 /workspace/coverage/cover_reg_top/10.rom_ctrl_passthru_mem_tl_intg_err.2536261756 Mar 12 12:48:49 PM PDT 24 Mar 12 12:49:26 PM PDT 24 3043925801 ps
T436 /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_mem_rw_with_rand_reset.3470319000 Mar 12 12:49:08 PM PDT 24 Mar 12 12:49:24 PM PDT 24 7879246657 ps
T437 /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_errors.1510072215 Mar 12 12:48:41 PM PDT 24 Mar 12 12:48:59 PM PDT 24 1655874076 ps
T438 /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_errors.2068866904 Mar 12 12:48:33 PM PDT 24 Mar 12 12:48:40 PM PDT 24 89119852 ps
T439 /workspace/coverage/cover_reg_top/0.rom_ctrl_passthru_mem_tl_intg_err.3900171383 Mar 12 12:48:29 PM PDT 24 Mar 12 12:49:44 PM PDT 24 8243821414 ps
T440 /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_errors.1463315816 Mar 12 12:49:09 PM PDT 24 Mar 12 12:49:28 PM PDT 24 7935311846 ps
T441 /workspace/coverage/cover_reg_top/14.rom_ctrl_same_csr_outstanding.2956222295 Mar 12 12:48:52 PM PDT 24 Mar 12 12:49:06 PM PDT 24 6809273966 ps
T126 /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_intg_err.3888525324 Mar 12 12:48:38 PM PDT 24 Mar 12 12:49:54 PM PDT 24 510826562 ps
T442 /workspace/coverage/cover_reg_top/6.rom_ctrl_passthru_mem_tl_intg_err.1091176087 Mar 12 12:48:37 PM PDT 24 Mar 12 12:48:56 PM PDT 24 5935183717 ps
T443 /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_errors.848208639 Mar 12 12:48:56 PM PDT 24 Mar 12 12:49:05 PM PDT 24 112089588 ps
T444 /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_errors.636162667 Mar 12 12:48:42 PM PDT 24 Mar 12 12:48:48 PM PDT 24 334164670 ps
T130 /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_intg_err.105606840 Mar 12 12:49:00 PM PDT 24 Mar 12 12:49:47 PM PDT 24 12061480139 ps
T445 /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_intg_err.3982152593 Mar 12 12:48:51 PM PDT 24 Mar 12 12:49:28 PM PDT 24 298584850 ps
T446 /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_mem_rw_with_rand_reset.3094879873 Mar 12 12:49:06 PM PDT 24 Mar 12 12:49:23 PM PDT 24 9621351651 ps
T447 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_rw.3926792152 Mar 12 12:48:41 PM PDT 24 Mar 12 12:48:56 PM PDT 24 3577532525 ps
T448 /workspace/coverage/cover_reg_top/17.rom_ctrl_passthru_mem_tl_intg_err.770513635 Mar 12 12:49:09 PM PDT 24 Mar 12 12:50:44 PM PDT 24 12157572818 ps
T449 /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_intg_err.4290703009 Mar 12 12:48:56 PM PDT 24 Mar 12 12:49:33 PM PDT 24 163860475 ps
T450 /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_mem_rw_with_rand_reset.3843462593 Mar 12 12:48:39 PM PDT 24 Mar 12 12:48:51 PM PDT 24 4885794701 ps
T96 /workspace/coverage/cover_reg_top/18.rom_ctrl_passthru_mem_tl_intg_err.1407096768 Mar 12 12:49:03 PM PDT 24 Mar 12 12:49:32 PM PDT 24 1866454406 ps
T451 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_mem_rw_with_rand_reset.946590211 Mar 12 12:48:35 PM PDT 24 Mar 12 12:48:42 PM PDT 24 1874880266 ps
T97 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_aliasing.2169325045 Mar 12 12:48:35 PM PDT 24 Mar 12 12:48:42 PM PDT 24 420926938 ps
T452 /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_partial_access.2307812757 Mar 12 12:48:34 PM PDT 24 Mar 12 12:48:50 PM PDT 24 8516360940 ps
T453 /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_intg_err.2125843018 Mar 12 12:49:07 PM PDT 24 Mar 12 12:50:23 PM PDT 24 1707859375 ps
T454 /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_mem_rw_with_rand_reset.1672820454 Mar 12 12:48:41 PM PDT 24 Mar 12 12:48:58 PM PDT 24 2124807678 ps
T455 /workspace/coverage/cover_reg_top/13.rom_ctrl_same_csr_outstanding.1257766577 Mar 12 12:48:55 PM PDT 24 Mar 12 12:49:05 PM PDT 24 12917723158 ps
T456 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_rw.2018712485 Mar 12 12:48:31 PM PDT 24 Mar 12 12:48:41 PM PDT 24 2244195964 ps
T457 /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_intg_err.4121168764 Mar 12 12:48:34 PM PDT 24 Mar 12 12:49:16 PM PDT 24 1024687245 ps
T458 /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_rw.738294235 Mar 12 12:48:54 PM PDT 24 Mar 12 12:49:08 PM PDT 24 1735492097 ps
T459 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_aliasing.1942611562 Mar 12 12:48:34 PM PDT 24 Mar 12 12:48:48 PM PDT 24 2085740773 ps
T460 /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_rw.2740851918 Mar 12 12:49:02 PM PDT 24 Mar 12 12:49:11 PM PDT 24 1315227146 ps
T461 /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_rw.3024732540 Mar 12 12:49:01 PM PDT 24 Mar 12 12:49:14 PM PDT 24 13789159934 ps
T462 /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_mem_rw_with_rand_reset.2417404263 Mar 12 12:48:37 PM PDT 24 Mar 12 12:48:55 PM PDT 24 1367945945 ps
T463 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_mem_rw_with_rand_reset.918001226 Mar 12 12:48:39 PM PDT 24 Mar 12 12:48:51 PM PDT 24 1387822205 ps
T464 /workspace/coverage/cover_reg_top/12.rom_ctrl_same_csr_outstanding.3987100636 Mar 12 12:48:51 PM PDT 24 Mar 12 12:48:56 PM PDT 24 346834195 ps

Test location /workspace/coverage/default/2.rom_ctrl_corrupt_sig_fatal_chk.3288418084
Short name T10
Test name
Test status
Simulation time 22922225501 ps
CPU time 127.61 seconds
Started Mar 12 12:33:00 PM PDT 24
Finished Mar 12 12:35:08 PM PDT 24
Peak memory 218708 kb
Host smart-80b4814f-95aa-41d8-8f45-9bd796ed4d3a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3288418084 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_c
orrupt_sig_fatal_chk.3288418084
Directory /workspace/2.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/24.rom_ctrl_stress_all_with_rand_reset.1019576543
Short name T13
Test name
Test status
Simulation time 176836257593 ps
CPU time 1896.58 seconds
Started Mar 12 12:33:47 PM PDT 24
Finished Mar 12 01:05:24 PM PDT 24
Peak memory 250988 kb
Host smart-0ec8e33b-d0e5-4ff5-84e1-ff9269f3048a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1019576543 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_stress_all_with_rand_reset.1019576543
Directory /workspace/24.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.rom_ctrl_corrupt_sig_fatal_chk.543992744
Short name T22
Test name
Test status
Simulation time 106885556516 ps
CPU time 278.22 seconds
Started Mar 12 12:33:17 PM PDT 24
Finished Mar 12 12:37:56 PM PDT 24
Peak memory 224292 kb
Host smart-3339024a-d39d-4e9e-9e6c-7db09d3a7663
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=543992744 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_co
rrupt_sig_fatal_chk.543992744
Directory /workspace/9.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/29.rom_ctrl_smoke.3070759196
Short name T1
Test name
Test status
Simulation time 3220754438 ps
CPU time 28.29 seconds
Started Mar 12 12:33:54 PM PDT 24
Finished Mar 12 12:34:23 PM PDT 24
Peak memory 211900 kb
Host smart-a367b4dd-01ca-429b-aa1d-d2b223010d08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3070759196 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_smoke.3070759196
Directory /workspace/29.rom_ctrl_smoke/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_intg_err.2907485754
Short name T62
Test name
Test status
Simulation time 2386454006 ps
CPU time 81.04 seconds
Started Mar 12 12:48:42 PM PDT 24
Finished Mar 12 12:50:03 PM PDT 24
Peak memory 211252 kb
Host smart-a55eb70f-16f5-4f8f-9084-1bca08e4e031
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2907485754 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_tl_i
ntg_err.2907485754
Directory /workspace/11.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/0.rom_ctrl_sec_cm.2425652208
Short name T31
Test name
Test status
Simulation time 7458285425 ps
CPU time 105.65 seconds
Started Mar 12 12:32:57 PM PDT 24
Finished Mar 12 12:34:43 PM PDT 24
Peak memory 236564 kb
Host smart-4995341d-1e38-4c3a-9f02-8d219353f5d8
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2425652208 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_sec_cm.2425652208
Directory /workspace/0.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/16.rom_ctrl_alert_test.2198304159
Short name T58
Test name
Test status
Simulation time 4646176064 ps
CPU time 10.63 seconds
Started Mar 12 12:33:28 PM PDT 24
Finished Mar 12 12:33:39 PM PDT 24
Peak memory 210420 kb
Host smart-cb64f9b1-c838-4efa-83e4-d306e689be98
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2198304159 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_alert_test.2198304159
Directory /workspace/16.rom_ctrl_alert_test/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_passthru_mem_tl_intg_err.3363952593
Short name T79
Test name
Test status
Simulation time 8026939167 ps
CPU time 62.1 seconds
Started Mar 12 12:48:34 PM PDT 24
Finished Mar 12 12:49:37 PM PDT 24
Peak memory 210972 kb
Host smart-43730580-7b37-4597-8ed4-b227b64dd45a
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3363952593 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_pa
ssthru_mem_tl_intg_err.3363952593
Directory /workspace/2.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_intg_err.1394100127
Short name T133
Test name
Test status
Simulation time 6019905848 ps
CPU time 74.45 seconds
Started Mar 12 12:49:12 PM PDT 24
Finished Mar 12 12:50:26 PM PDT 24
Peak memory 211908 kb
Host smart-909ec87b-6793-409a-be1c-7f92a5623cf4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1394100127 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_tl_i
ntg_err.1394100127
Directory /workspace/18.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/12.rom_ctrl_kmac_err_chk.2980841752
Short name T7
Test name
Test status
Simulation time 7876995070 ps
CPU time 22 seconds
Started Mar 12 12:33:20 PM PDT 24
Finished Mar 12 12:33:42 PM PDT 24
Peak memory 211328 kb
Host smart-3fdfa11c-e85d-4449-8c82-d7dc804836cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2980841752 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_kmac_err_chk.2980841752
Directory /workspace/12.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/14.rom_ctrl_kmac_err_chk.204527468
Short name T162
Test name
Test status
Simulation time 334437717 ps
CPU time 9.69 seconds
Started Mar 12 12:33:27 PM PDT 24
Finished Mar 12 12:33:38 PM PDT 24
Peak memory 211020 kb
Host smart-82238165-d569-439b-8d07-d19c3944e4e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=204527468 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_kmac_err_chk.204527468
Directory /workspace/14.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_same_csr_outstanding.1267099734
Short name T110
Test name
Test status
Simulation time 926703314 ps
CPU time 7.4 seconds
Started Mar 12 12:48:35 PM PDT 24
Finished Mar 12 12:48:43 PM PDT 24
Peak memory 210700 kb
Host smart-74f65f89-bc3c-4ea5-9324-a88d15a146e9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1267099734 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_c
trl_same_csr_outstanding.1267099734
Directory /workspace/0.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/default/16.rom_ctrl_stress_all.418587437
Short name T87
Test name
Test status
Simulation time 43859513316 ps
CPU time 54.56 seconds
Started Mar 12 12:33:26 PM PDT 24
Finished Mar 12 12:34:20 PM PDT 24
Peak memory 215052 kb
Host smart-e5a74dd0-91bf-4223-8d5c-7394b8548484
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=418587437 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 16.rom_ctrl_stress_all.418587437
Directory /workspace/16.rom_ctrl_stress_all/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_passthru_mem_tl_intg_err.1914638796
Short name T121
Test name
Test status
Simulation time 9373222377 ps
CPU time 60.82 seconds
Started Mar 12 12:48:38 PM PDT 24
Finished Mar 12 12:49:39 PM PDT 24
Peak memory 210976 kb
Host smart-db1a8bff-d697-468e-b284-524c4410f60e
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1914638796 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_p
assthru_mem_tl_intg_err.1914638796
Directory /workspace/11.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_intg_err.1477210211
Short name T128
Test name
Test status
Simulation time 1497769813 ps
CPU time 72.46 seconds
Started Mar 12 12:49:08 PM PDT 24
Finished Mar 12 12:50:22 PM PDT 24
Peak memory 210816 kb
Host smart-c2759ab3-3ac5-416a-8638-6e7f93deac42
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1477210211 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_tl_i
ntg_err.1477210211
Directory /workspace/16.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_intg_err.2369435365
Short name T129
Test name
Test status
Simulation time 5765706989 ps
CPU time 71.04 seconds
Started Mar 12 12:48:41 PM PDT 24
Finished Mar 12 12:49:52 PM PDT 24
Peak memory 210888 kb
Host smart-da4ed5f5-8d9d-4279-bda3-e61f223dd43a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2369435365 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_tl_in
tg_err.2369435365
Directory /workspace/3.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_intg_err.3888525324
Short name T126
Test name
Test status
Simulation time 510826562 ps
CPU time 76.21 seconds
Started Mar 12 12:48:38 PM PDT 24
Finished Mar 12 12:49:54 PM PDT 24
Peak memory 212724 kb
Host smart-2d48b56a-b071-4fa8-aacc-bc2ab4ecd0f3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3888525324 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_tl_in
tg_err.3888525324
Directory /workspace/9.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/12.rom_ctrl_max_throughput_chk.2732325741
Short name T140
Test name
Test status
Simulation time 2020597231 ps
CPU time 16.84 seconds
Started Mar 12 12:33:17 PM PDT 24
Finished Mar 12 12:33:34 PM PDT 24
Peak memory 210256 kb
Host smart-f4620e94-47f3-4d77-83de-437f7aef64ba
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2732325741 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_max_throughput_chk.2732325741
Directory /workspace/12.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/1.rom_ctrl_max_throughput_chk.711954232
Short name T115
Test name
Test status
Simulation time 1870462519 ps
CPU time 16.52 seconds
Started Mar 12 12:32:57 PM PDT 24
Finished Mar 12 12:33:14 PM PDT 24
Peak memory 210204 kb
Host smart-49f884dc-d357-4586-9cbc-5c9b2420d28d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=711954232 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_max_throughput_chk.711954232
Directory /workspace/1.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/4.rom_ctrl_stress_all_with_rand_reset.3455187115
Short name T17
Test name
Test status
Simulation time 273123713835 ps
CPU time 2695.23 seconds
Started Mar 12 12:32:59 PM PDT 24
Finished Mar 12 01:17:55 PM PDT 24
Peak memory 236996 kb
Host smart-339d8347-fd4b-47cd-92c6-1c6bb38a17c2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3455187115 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_stress_all_with_rand_reset.3455187115
Directory /workspace/4.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_aliasing.1942611562
Short name T459
Test name
Test status
Simulation time 2085740773 ps
CPU time 13.51 seconds
Started Mar 12 12:48:34 PM PDT 24
Finished Mar 12 12:48:48 PM PDT 24
Peak memory 210852 kb
Host smart-df350745-7c2b-48d1-9735-f1416f9b206c
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1942611562 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_alia
sing.1942611562
Directory /workspace/0.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_bit_bash.2933006417
Short name T95
Test name
Test status
Simulation time 1848931482 ps
CPU time 15.4 seconds
Started Mar 12 12:48:33 PM PDT 24
Finished Mar 12 12:48:48 PM PDT 24
Peak memory 210812 kb
Host smart-f79ca0bd-ed06-4803-bd6c-73bdeabe6a27
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2933006417 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_bit_
bash.2933006417
Directory /workspace/0.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_hw_reset.2986386564
Short name T94
Test name
Test status
Simulation time 4074420958 ps
CPU time 11.44 seconds
Started Mar 12 12:48:33 PM PDT 24
Finished Mar 12 12:48:45 PM PDT 24
Peak memory 210844 kb
Host smart-61b15a97-7d48-49d5-9db2-42d1ffa99535
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2986386564 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_hw_r
eset.2986386564
Directory /workspace/0.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_mem_rw_with_rand_reset.1465784338
Short name T413
Test name
Test status
Simulation time 4223292522 ps
CPU time 16.53 seconds
Started Mar 12 12:48:39 PM PDT 24
Finished Mar 12 12:48:55 PM PDT 24
Peak memory 214328 kb
Host smart-49296a73-6964-48fd-948c-fe9ff633f8bd
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1465784338 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 0.rom_ctrl_csr_mem_rw_with_rand_reset.1465784338
Directory /workspace/0.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_rw.2402071400
Short name T393
Test name
Test status
Simulation time 87239166 ps
CPU time 4.24 seconds
Started Mar 12 12:48:30 PM PDT 24
Finished Mar 12 12:48:34 PM PDT 24
Peak memory 210800 kb
Host smart-36e9e06c-0a7a-4211-96db-78492ea9b801
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2402071400 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_rw.2402071400
Directory /workspace/0.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_partial_access.3933098591
Short name T417
Test name
Test status
Simulation time 2799128892 ps
CPU time 8.56 seconds
Started Mar 12 12:48:30 PM PDT 24
Finished Mar 12 12:48:39 PM PDT 24
Peak memory 210776 kb
Host smart-f81d1343-ddf1-4296-9c03-020b64ce27ac
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3933098591 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctr
l_mem_partial_access.3933098591
Directory /workspace/0.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_walk.639209434
Short name T418
Test name
Test status
Simulation time 1044436984 ps
CPU time 10.17 seconds
Started Mar 12 12:48:28 PM PDT 24
Finished Mar 12 12:48:38 PM PDT 24
Peak memory 210804 kb
Host smart-fbcdaab1-0b67-4ece-ae0d-5eed1b4f6770
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=639209434 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_mem_walk.
639209434
Directory /workspace/0.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_passthru_mem_tl_intg_err.3900171383
Short name T439
Test name
Test status
Simulation time 8243821414 ps
CPU time 75.03 seconds
Started Mar 12 12:48:29 PM PDT 24
Finished Mar 12 12:49:44 PM PDT 24
Peak memory 210900 kb
Host smart-17f02ae2-0cf2-45d4-8824-8a8f62aa2b52
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3900171383 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_pa
ssthru_mem_tl_intg_err.3900171383
Directory /workspace/0.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_errors.1417884137
Short name T369
Test name
Test status
Simulation time 1759779165 ps
CPU time 18.32 seconds
Started Mar 12 12:48:32 PM PDT 24
Finished Mar 12 12:48:51 PM PDT 24
Peak memory 215116 kb
Host smart-3f04d8b6-0000-402a-b6a9-c352ea5d969e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1417884137 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_tl_errors.1417884137
Directory /workspace/0.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_intg_err.717347653
Short name T123
Test name
Test status
Simulation time 1803473453 ps
CPU time 45.14 seconds
Started Mar 12 12:48:31 PM PDT 24
Finished Mar 12 12:49:18 PM PDT 24
Peak memory 211408 kb
Host smart-f259e484-410f-4b7c-9fe2-a592b91a48c4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=717347653 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_tl_int
g_err.717347653
Directory /workspace/0.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_aliasing.2436972657
Short name T421
Test name
Test status
Simulation time 5852516264 ps
CPU time 11.45 seconds
Started Mar 12 12:48:47 PM PDT 24
Finished Mar 12 12:48:58 PM PDT 24
Peak memory 210960 kb
Host smart-c6588722-086c-436a-a86d-f2989dbf3bfc
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2436972657 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_alia
sing.2436972657
Directory /workspace/1.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_bit_bash.2050231546
Short name T64
Test name
Test status
Simulation time 1065961398 ps
CPU time 10.74 seconds
Started Mar 12 12:48:28 PM PDT 24
Finished Mar 12 12:48:39 PM PDT 24
Peak memory 210672 kb
Host smart-39202b35-9218-44fb-9714-7c2bb4357795
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2050231546 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_bit_
bash.2050231546
Directory /workspace/1.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_hw_reset.1363472643
Short name T394
Test name
Test status
Simulation time 677375667 ps
CPU time 9.83 seconds
Started Mar 12 12:48:36 PM PDT 24
Finished Mar 12 12:48:46 PM PDT 24
Peak memory 210856 kb
Host smart-b26ae176-a40f-4222-bbeb-c7bcb6f4500a
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1363472643 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_hw_r
eset.1363472643
Directory /workspace/1.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_mem_rw_with_rand_reset.3544764384
Short name T395
Test name
Test status
Simulation time 1310546340 ps
CPU time 8.44 seconds
Started Mar 12 12:48:48 PM PDT 24
Finished Mar 12 12:48:56 PM PDT 24
Peak memory 214440 kb
Host smart-0f8566f9-75fc-4f60-a53f-ec38c8ddbc0b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3544764384 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 1.rom_ctrl_csr_mem_rw_with_rand_reset.3544764384
Directory /workspace/1.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_rw.920032478
Short name T81
Test name
Test status
Simulation time 344775165 ps
CPU time 6.28 seconds
Started Mar 12 12:48:47 PM PDT 24
Finished Mar 12 12:48:54 PM PDT 24
Peak memory 210816 kb
Host smart-96457ae0-aaba-473c-9f49-51fee56d291f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=920032478 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_rw.920032478
Directory /workspace/1.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_partial_access.4170577423
Short name T377
Test name
Test status
Simulation time 5302068526 ps
CPU time 12.46 seconds
Started Mar 12 12:48:46 PM PDT 24
Finished Mar 12 12:48:58 PM PDT 24
Peak memory 210904 kb
Host smart-2de863a5-5680-4d6b-aed3-7e54e2ce0448
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4170577423 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctr
l_mem_partial_access.4170577423
Directory /workspace/1.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_walk.661095237
Short name T412
Test name
Test status
Simulation time 7636460124 ps
CPU time 7.62 seconds
Started Mar 12 12:48:58 PM PDT 24
Finished Mar 12 12:49:05 PM PDT 24
Peak memory 210956 kb
Host smart-92d2c118-b80a-4e6c-b96a-4a436ded88f9
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=661095237 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_mem_walk.
661095237
Directory /workspace/1.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_passthru_mem_tl_intg_err.3420915251
Short name T73
Test name
Test status
Simulation time 2445623579 ps
CPU time 27.66 seconds
Started Mar 12 12:48:34 PM PDT 24
Finished Mar 12 12:49:01 PM PDT 24
Peak memory 210796 kb
Host smart-4ba321b1-f89b-48c5-a235-335e0a8764ee
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3420915251 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_pa
ssthru_mem_tl_intg_err.3420915251
Directory /workspace/1.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_same_csr_outstanding.1909183590
Short name T113
Test name
Test status
Simulation time 6717097054 ps
CPU time 15.58 seconds
Started Mar 12 12:48:32 PM PDT 24
Finished Mar 12 12:48:48 PM PDT 24
Peak memory 210980 kb
Host smart-248e0feb-f36f-4154-ac72-04acbabf281f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1909183590 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_c
trl_same_csr_outstanding.1909183590
Directory /workspace/1.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_errors.2457267845
Short name T383
Test name
Test status
Simulation time 981617148 ps
CPU time 10.63 seconds
Started Mar 12 12:48:41 PM PDT 24
Finished Mar 12 12:48:52 PM PDT 24
Peak memory 215064 kb
Host smart-04b41aac-bf80-4944-bec1-758e63a3b969
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2457267845 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_tl_errors.2457267845
Directory /workspace/1.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_intg_err.3172840373
Short name T63
Test name
Test status
Simulation time 2671872006 ps
CPU time 43.21 seconds
Started Mar 12 12:48:56 PM PDT 24
Finished Mar 12 12:49:39 PM PDT 24
Peak memory 210900 kb
Host smart-8017f6b6-9778-4b5e-a8d9-1552262d83b7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3172840373 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_tl_in
tg_err.3172840373
Directory /workspace/1.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_mem_rw_with_rand_reset.1672820454
Short name T454
Test name
Test status
Simulation time 2124807678 ps
CPU time 17.56 seconds
Started Mar 12 12:48:41 PM PDT 24
Finished Mar 12 12:48:58 PM PDT 24
Peak memory 215132 kb
Host smart-897f4542-fa5e-4a4d-ac27-4d801f3a12c2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1672820454 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 10.rom_ctrl_csr_mem_rw_with_rand_reset.1672820454
Directory /workspace/10.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_rw.3571321116
Short name T92
Test name
Test status
Simulation time 2162941690 ps
CPU time 15.85 seconds
Started Mar 12 12:48:40 PM PDT 24
Finished Mar 12 12:48:56 PM PDT 24
Peak memory 210788 kb
Host smart-88764be5-3167-434c-adf0-529e3dab5987
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3571321116 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_csr_rw.3571321116
Directory /workspace/10.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_passthru_mem_tl_intg_err.2536261756
Short name T435
Test name
Test status
Simulation time 3043925801 ps
CPU time 36.83 seconds
Started Mar 12 12:48:49 PM PDT 24
Finished Mar 12 12:49:26 PM PDT 24
Peak memory 210876 kb
Host smart-e8a5a346-bf72-4e57-a11e-144badf0df19
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2536261756 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_p
assthru_mem_tl_intg_err.2536261756
Directory /workspace/10.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_same_csr_outstanding.2561273818
Short name T112
Test name
Test status
Simulation time 9684973294 ps
CPU time 14.24 seconds
Started Mar 12 12:48:39 PM PDT 24
Finished Mar 12 12:48:53 PM PDT 24
Peak memory 210908 kb
Host smart-fa1a1cd7-ffd2-4929-8dd5-5c5aa9a3c632
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2561273818 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_
ctrl_same_csr_outstanding.2561273818
Directory /workspace/10.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_errors.848208639
Short name T443
Test name
Test status
Simulation time 112089588 ps
CPU time 8.49 seconds
Started Mar 12 12:48:56 PM PDT 24
Finished Mar 12 12:49:05 PM PDT 24
Peak memory 219016 kb
Host smart-b62c03cd-bb99-402b-930f-0ba5848c1c13
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=848208639 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_tl_errors.848208639
Directory /workspace/10.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_intg_err.2620318136
Short name T61
Test name
Test status
Simulation time 699232670 ps
CPU time 36.78 seconds
Started Mar 12 12:48:48 PM PDT 24
Finished Mar 12 12:49:25 PM PDT 24
Peak memory 211148 kb
Host smart-9f5c941e-67c5-4a64-9077-a42997e01a30
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2620318136 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_tl_i
ntg_err.2620318136
Directory /workspace/10.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_mem_rw_with_rand_reset.3843462593
Short name T450
Test name
Test status
Simulation time 4885794701 ps
CPU time 11.3 seconds
Started Mar 12 12:48:39 PM PDT 24
Finished Mar 12 12:48:51 PM PDT 24
Peak memory 214760 kb
Host smart-86308562-f92d-416a-a720-94639d9bca0a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3843462593 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 11.rom_ctrl_csr_mem_rw_with_rand_reset.3843462593
Directory /workspace/11.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_rw.3607347670
Short name T391
Test name
Test status
Simulation time 10483627774 ps
CPU time 14.26 seconds
Started Mar 12 12:48:51 PM PDT 24
Finished Mar 12 12:49:05 PM PDT 24
Peak memory 210940 kb
Host smart-0fa987b2-d650-4f49-b9d3-66fa1e235a0e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3607347670 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_csr_rw.3607347670
Directory /workspace/11.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_same_csr_outstanding.4259913244
Short name T425
Test name
Test status
Simulation time 1654374316 ps
CPU time 13.24 seconds
Started Mar 12 12:48:39 PM PDT 24
Finished Mar 12 12:48:53 PM PDT 24
Peak memory 210736 kb
Host smart-3ba6a6c3-9320-4312-afec-310b16212500
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4259913244 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_
ctrl_same_csr_outstanding.4259913244
Directory /workspace/11.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_errors.560028424
Short name T371
Test name
Test status
Simulation time 10210136196 ps
CPU time 14.04 seconds
Started Mar 12 12:48:56 PM PDT 24
Finished Mar 12 12:49:10 PM PDT 24
Peak memory 215328 kb
Host smart-557c5461-32e7-4c8a-9710-0059a6108c5a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=560028424 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_tl_errors.560028424
Directory /workspace/11.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_mem_rw_with_rand_reset.1971621638
Short name T375
Test name
Test status
Simulation time 2941535706 ps
CPU time 13.21 seconds
Started Mar 12 12:48:56 PM PDT 24
Finished Mar 12 12:49:09 PM PDT 24
Peak memory 213896 kb
Host smart-7c5c5d02-1845-4930-84bc-689d04d455d1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1971621638 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 12.rom_ctrl_csr_mem_rw_with_rand_reset.1971621638
Directory /workspace/12.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_rw.738294235
Short name T458
Test name
Test status
Simulation time 1735492097 ps
CPU time 13.3 seconds
Started Mar 12 12:48:54 PM PDT 24
Finished Mar 12 12:49:08 PM PDT 24
Peak memory 210752 kb
Host smart-c0cc39da-d04a-4d9e-8528-752b989b8c9d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=738294235 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_csr_rw.738294235
Directory /workspace/12.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_passthru_mem_tl_intg_err.303782904
Short name T422
Test name
Test status
Simulation time 3607159900 ps
CPU time 32.31 seconds
Started Mar 12 12:48:39 PM PDT 24
Finished Mar 12 12:49:11 PM PDT 24
Peak memory 210864 kb
Host smart-bc127ddd-248e-42b3-8292-ad248905d566
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=303782904 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_pa
ssthru_mem_tl_intg_err.303782904
Directory /workspace/12.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_same_csr_outstanding.3987100636
Short name T464
Test name
Test status
Simulation time 346834195 ps
CPU time 4.48 seconds
Started Mar 12 12:48:51 PM PDT 24
Finished Mar 12 12:48:56 PM PDT 24
Peak memory 210808 kb
Host smart-5afab4b1-d27f-4206-929c-bf5b64ab3b2f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3987100636 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_
ctrl_same_csr_outstanding.3987100636
Directory /workspace/12.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_errors.2247493630
Short name T368
Test name
Test status
Simulation time 6104530485 ps
CPU time 14.92 seconds
Started Mar 12 12:48:39 PM PDT 24
Finished Mar 12 12:48:54 PM PDT 24
Peak memory 219108 kb
Host smart-19b81243-e0ed-4f43-895b-a0a2a87e52e0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2247493630 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_tl_errors.2247493630
Directory /workspace/12.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_intg_err.105606840
Short name T130
Test name
Test status
Simulation time 12061480139 ps
CPU time 47.61 seconds
Started Mar 12 12:49:00 PM PDT 24
Finished Mar 12 12:49:47 PM PDT 24
Peak memory 210860 kb
Host smart-7d20e37e-62c5-4381-bfa3-5c67ee32eaa6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=105606840 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_tl_in
tg_err.105606840
Directory /workspace/12.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_mem_rw_with_rand_reset.2053726937
Short name T378
Test name
Test status
Simulation time 475036109 ps
CPU time 7.38 seconds
Started Mar 12 12:49:08 PM PDT 24
Finished Mar 12 12:49:16 PM PDT 24
Peak memory 213936 kb
Host smart-36886524-c8fc-463d-a68b-59eb3c9da855
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2053726937 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 13.rom_ctrl_csr_mem_rw_with_rand_reset.2053726937
Directory /workspace/13.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_rw.2003661052
Short name T98
Test name
Test status
Simulation time 87540736 ps
CPU time 4.26 seconds
Started Mar 12 12:48:59 PM PDT 24
Finished Mar 12 12:49:03 PM PDT 24
Peak memory 210812 kb
Host smart-1dc641d9-5d2b-474a-a74d-1e6bef387a91
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2003661052 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_csr_rw.2003661052
Directory /workspace/13.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_passthru_mem_tl_intg_err.1825894067
Short name T80
Test name
Test status
Simulation time 7277244260 ps
CPU time 68 seconds
Started Mar 12 12:48:54 PM PDT 24
Finished Mar 12 12:50:02 PM PDT 24
Peak memory 210904 kb
Host smart-be1a0998-8d45-4db5-9ef3-4596ddf85398
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1825894067 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_p
assthru_mem_tl_intg_err.1825894067
Directory /workspace/13.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_same_csr_outstanding.1257766577
Short name T455
Test name
Test status
Simulation time 12917723158 ps
CPU time 9.52 seconds
Started Mar 12 12:48:55 PM PDT 24
Finished Mar 12 12:49:05 PM PDT 24
Peak memory 210908 kb
Host smart-1085bb97-93d6-4873-89b9-bb3381dc1271
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1257766577 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_
ctrl_same_csr_outstanding.1257766577
Directory /workspace/13.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_errors.2322656342
Short name T380
Test name
Test status
Simulation time 8467565235 ps
CPU time 20.02 seconds
Started Mar 12 12:48:58 PM PDT 24
Finished Mar 12 12:49:18 PM PDT 24
Peak memory 215424 kb
Host smart-71ae73ce-8747-4b00-aa4a-f67b3daf96bd
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2322656342 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_tl_errors.2322656342
Directory /workspace/13.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_intg_err.95648169
Short name T408
Test name
Test status
Simulation time 4847412859 ps
CPU time 43.11 seconds
Started Mar 12 12:48:57 PM PDT 24
Finished Mar 12 12:49:40 PM PDT 24
Peak memory 210976 kb
Host smart-768611d8-7864-4630-b937-098f35cd79b9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=95648169 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_tl_int
g_err.95648169
Directory /workspace/13.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_mem_rw_with_rand_reset.762793053
Short name T424
Test name
Test status
Simulation time 1345806198 ps
CPU time 7.91 seconds
Started Mar 12 12:49:06 PM PDT 24
Finished Mar 12 12:49:14 PM PDT 24
Peak memory 213060 kb
Host smart-f79e2c41-6ff0-4ab0-95fb-ebc9a562740d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=762793053 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 14.rom_ctrl_csr_mem_rw_with_rand_reset.762793053
Directory /workspace/14.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_rw.3024732540
Short name T461
Test name
Test status
Simulation time 13789159934 ps
CPU time 13.16 seconds
Started Mar 12 12:49:01 PM PDT 24
Finished Mar 12 12:49:14 PM PDT 24
Peak memory 210944 kb
Host smart-e5c6a1fb-3217-4b34-9976-e08be3cecb42
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3024732540 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_csr_rw.3024732540
Directory /workspace/14.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_passthru_mem_tl_intg_err.995193915
Short name T76
Test name
Test status
Simulation time 1173724257 ps
CPU time 25.73 seconds
Started Mar 12 12:48:55 PM PDT 24
Finished Mar 12 12:49:21 PM PDT 24
Peak memory 210864 kb
Host smart-e3c8c6d1-a749-4130-96ef-47681ae04332
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=995193915 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_pa
ssthru_mem_tl_intg_err.995193915
Directory /workspace/14.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_same_csr_outstanding.2956222295
Short name T441
Test name
Test status
Simulation time 6809273966 ps
CPU time 13.83 seconds
Started Mar 12 12:48:52 PM PDT 24
Finished Mar 12 12:49:06 PM PDT 24
Peak memory 210920 kb
Host smart-a4cbfada-b8fd-4b86-ad97-0e5a72d58938
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2956222295 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_
ctrl_same_csr_outstanding.2956222295
Directory /workspace/14.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_errors.1115531257
Short name T367
Test name
Test status
Simulation time 669914549 ps
CPU time 9.68 seconds
Started Mar 12 12:48:58 PM PDT 24
Finished Mar 12 12:49:07 PM PDT 24
Peak memory 215052 kb
Host smart-901b5b01-0355-4b81-ae2d-bc34d96644c4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1115531257 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_tl_errors.1115531257
Directory /workspace/14.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_intg_err.4285075308
Short name T131
Test name
Test status
Simulation time 5406018875 ps
CPU time 72.48 seconds
Started Mar 12 12:48:58 PM PDT 24
Finished Mar 12 12:50:10 PM PDT 24
Peak memory 210948 kb
Host smart-bff5c7a6-630a-4bab-b291-a3f3d1b4ad8d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4285075308 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_tl_i
ntg_err.4285075308
Directory /workspace/14.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_mem_rw_with_rand_reset.3710825673
Short name T429
Test name
Test status
Simulation time 1810916720 ps
CPU time 16.01 seconds
Started Mar 12 12:48:56 PM PDT 24
Finished Mar 12 12:49:12 PM PDT 24
Peak memory 213232 kb
Host smart-04ffc2b6-35b0-4f46-b591-2fed944c94c6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3710825673 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 15.rom_ctrl_csr_mem_rw_with_rand_reset.3710825673
Directory /workspace/15.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_rw.2984945199
Short name T411
Test name
Test status
Simulation time 4425398743 ps
CPU time 11.36 seconds
Started Mar 12 12:48:58 PM PDT 24
Finished Mar 12 12:49:09 PM PDT 24
Peak memory 210932 kb
Host smart-82134806-0524-4475-8063-286e5a70c7f3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2984945199 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_csr_rw.2984945199
Directory /workspace/15.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_passthru_mem_tl_intg_err.318715369
Short name T382
Test name
Test status
Simulation time 1106453306 ps
CPU time 27.42 seconds
Started Mar 12 12:48:55 PM PDT 24
Finished Mar 12 12:49:23 PM PDT 24
Peak memory 210740 kb
Host smart-87979515-1648-4d64-ad3f-d2f63ac49993
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=318715369 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_pa
ssthru_mem_tl_intg_err.318715369
Directory /workspace/15.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_same_csr_outstanding.1918422470
Short name T65
Test name
Test status
Simulation time 816208125 ps
CPU time 9.17 seconds
Started Mar 12 12:48:53 PM PDT 24
Finished Mar 12 12:49:02 PM PDT 24
Peak memory 210816 kb
Host smart-6f71dc9e-2ee3-4fbd-96bb-f1f3c31e95a4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1918422470 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_
ctrl_same_csr_outstanding.1918422470
Directory /workspace/15.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_errors.2533032824
Short name T390
Test name
Test status
Simulation time 5856508390 ps
CPU time 16.63 seconds
Started Mar 12 12:49:00 PM PDT 24
Finished Mar 12 12:49:16 PM PDT 24
Peak memory 215440 kb
Host smart-54500a84-ff18-4dba-ab51-1bab3c5499e4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2533032824 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_tl_errors.2533032824
Directory /workspace/15.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_intg_err.4290703009
Short name T449
Test name
Test status
Simulation time 163860475 ps
CPU time 36.67 seconds
Started Mar 12 12:48:56 PM PDT 24
Finished Mar 12 12:49:33 PM PDT 24
Peak memory 210800 kb
Host smart-b42d3a4e-8a8a-4f98-b172-311f9fe45712
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4290703009 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_tl_i
ntg_err.4290703009
Directory /workspace/15.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_mem_rw_with_rand_reset.2290397055
Short name T384
Test name
Test status
Simulation time 693070190 ps
CPU time 8.64 seconds
Started Mar 12 12:49:10 PM PDT 24
Finished Mar 12 12:49:20 PM PDT 24
Peak memory 212564 kb
Host smart-62742b24-48aa-4aae-8a04-fc1ebf571cff
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2290397055 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 16.rom_ctrl_csr_mem_rw_with_rand_reset.2290397055
Directory /workspace/16.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_rw.3135027060
Short name T402
Test name
Test status
Simulation time 1621708996 ps
CPU time 13.82 seconds
Started Mar 12 12:48:59 PM PDT 24
Finished Mar 12 12:49:13 PM PDT 24
Peak memory 210820 kb
Host smart-b652b64e-8c1d-4049-90d1-a16e4b45974f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3135027060 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_csr_rw.3135027060
Directory /workspace/16.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_passthru_mem_tl_intg_err.2965552809
Short name T93
Test name
Test status
Simulation time 39169595865 ps
CPU time 67.03 seconds
Started Mar 12 12:49:05 PM PDT 24
Finished Mar 12 12:50:12 PM PDT 24
Peak memory 210948 kb
Host smart-c138fe0f-6a05-47f6-a630-9f7628bed9b9
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2965552809 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_p
assthru_mem_tl_intg_err.2965552809
Directory /workspace/16.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_same_csr_outstanding.3017998151
Short name T410
Test name
Test status
Simulation time 1811060610 ps
CPU time 9.2 seconds
Started Mar 12 12:49:06 PM PDT 24
Finished Mar 12 12:49:16 PM PDT 24
Peak memory 210832 kb
Host smart-88448458-ae0b-467a-817f-4ea2ad473739
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3017998151 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_
ctrl_same_csr_outstanding.3017998151
Directory /workspace/16.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_errors.1463315816
Short name T440
Test name
Test status
Simulation time 7935311846 ps
CPU time 18.7 seconds
Started Mar 12 12:49:09 PM PDT 24
Finished Mar 12 12:49:28 PM PDT 24
Peak memory 216416 kb
Host smart-85f62852-9605-4bd4-80fa-5e129f202f96
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1463315816 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_tl_errors.1463315816
Directory /workspace/16.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_mem_rw_with_rand_reset.3470319000
Short name T436
Test name
Test status
Simulation time 7879246657 ps
CPU time 15.76 seconds
Started Mar 12 12:49:08 PM PDT 24
Finished Mar 12 12:49:24 PM PDT 24
Peak memory 214992 kb
Host smart-f078e04d-1e5a-44b0-bea0-b9ad2dccee13
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3470319000 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 17.rom_ctrl_csr_mem_rw_with_rand_reset.3470319000
Directory /workspace/17.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_rw.1551406212
Short name T116
Test name
Test status
Simulation time 1203621512 ps
CPU time 7.89 seconds
Started Mar 12 12:49:01 PM PDT 24
Finished Mar 12 12:49:09 PM PDT 24
Peak memory 210844 kb
Host smart-fc7cde1d-1258-4a13-91e4-3c29ff364d45
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1551406212 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_csr_rw.1551406212
Directory /workspace/17.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_passthru_mem_tl_intg_err.770513635
Short name T448
Test name
Test status
Simulation time 12157572818 ps
CPU time 94.83 seconds
Started Mar 12 12:49:09 PM PDT 24
Finished Mar 12 12:50:44 PM PDT 24
Peak memory 210940 kb
Host smart-0242854c-0c85-4e1b-a07e-c41b06ce64bd
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=770513635 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_pa
ssthru_mem_tl_intg_err.770513635
Directory /workspace/17.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_same_csr_outstanding.1416188658
Short name T77
Test name
Test status
Simulation time 1840060419 ps
CPU time 14.69 seconds
Started Mar 12 12:49:05 PM PDT 24
Finished Mar 12 12:49:20 PM PDT 24
Peak memory 210812 kb
Host smart-e385329a-175f-44bb-8c3f-d43a22d9bcf5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1416188658 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_
ctrl_same_csr_outstanding.1416188658
Directory /workspace/17.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_errors.801685675
Short name T434
Test name
Test status
Simulation time 10990062549 ps
CPU time 20.27 seconds
Started Mar 12 12:49:07 PM PDT 24
Finished Mar 12 12:49:28 PM PDT 24
Peak memory 214680 kb
Host smart-8bf9efe3-0746-427b-8fb4-033e9683eef7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=801685675 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_tl_errors.801685675
Directory /workspace/17.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_intg_err.2125843018
Short name T453
Test name
Test status
Simulation time 1707859375 ps
CPU time 75.93 seconds
Started Mar 12 12:49:07 PM PDT 24
Finished Mar 12 12:50:23 PM PDT 24
Peak memory 211456 kb
Host smart-09175222-420c-404f-8ea0-6eb9820c0197
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2125843018 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_tl_i
ntg_err.2125843018
Directory /workspace/17.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_mem_rw_with_rand_reset.4069546027
Short name T428
Test name
Test status
Simulation time 1692985028 ps
CPU time 14.59 seconds
Started Mar 12 12:49:09 PM PDT 24
Finished Mar 12 12:49:24 PM PDT 24
Peak memory 213660 kb
Host smart-6ba18f21-9bf2-4840-aa2b-ef6d88b021e5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4069546027 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 18.rom_ctrl_csr_mem_rw_with_rand_reset.4069546027
Directory /workspace/18.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_rw.1563203215
Short name T374
Test name
Test status
Simulation time 1415869228 ps
CPU time 12.62 seconds
Started Mar 12 12:49:02 PM PDT 24
Finished Mar 12 12:49:15 PM PDT 24
Peak memory 210840 kb
Host smart-9b12ee56-d805-4fd0-a5f3-12a9991260f7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1563203215 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_csr_rw.1563203215
Directory /workspace/18.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_passthru_mem_tl_intg_err.1407096768
Short name T96
Test name
Test status
Simulation time 1866454406 ps
CPU time 29.11 seconds
Started Mar 12 12:49:03 PM PDT 24
Finished Mar 12 12:49:32 PM PDT 24
Peak memory 210824 kb
Host smart-7b273680-35e9-42e7-97ee-abdf39ede632
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1407096768 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_p
assthru_mem_tl_intg_err.1407096768
Directory /workspace/18.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_same_csr_outstanding.16817705
Short name T75
Test name
Test status
Simulation time 11035164962 ps
CPU time 14.62 seconds
Started Mar 12 12:49:11 PM PDT 24
Finished Mar 12 12:49:26 PM PDT 24
Peak memory 210924 kb
Host smart-425dd24f-ad89-45bb-bd6f-9ab30e0b05f0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16817705 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ct
rl_same_csr_outstanding.16817705
Directory /workspace/18.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_errors.738280086
Short name T406
Test name
Test status
Simulation time 250502214 ps
CPU time 8.56 seconds
Started Mar 12 12:49:11 PM PDT 24
Finished Mar 12 12:49:20 PM PDT 24
Peak memory 215028 kb
Host smart-9e7162f2-ad66-47cf-b19f-43109debbceb
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=738280086 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_tl_errors.738280086
Directory /workspace/18.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_mem_rw_with_rand_reset.3094879873
Short name T446
Test name
Test status
Simulation time 9621351651 ps
CPU time 16.29 seconds
Started Mar 12 12:49:06 PM PDT 24
Finished Mar 12 12:49:23 PM PDT 24
Peak memory 216984 kb
Host smart-a4c4edfa-1c3b-45d4-a6fb-5a1a9af59437
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3094879873 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 19.rom_ctrl_csr_mem_rw_with_rand_reset.3094879873
Directory /workspace/19.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_rw.2740851918
Short name T460
Test name
Test status
Simulation time 1315227146 ps
CPU time 8.46 seconds
Started Mar 12 12:49:02 PM PDT 24
Finished Mar 12 12:49:11 PM PDT 24
Peak memory 210820 kb
Host smart-4063742f-dd70-4582-ac20-2421f4798286
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2740851918 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_csr_rw.2740851918
Directory /workspace/19.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_passthru_mem_tl_intg_err.3995253537
Short name T101
Test name
Test status
Simulation time 18342540546 ps
CPU time 54.14 seconds
Started Mar 12 12:49:10 PM PDT 24
Finished Mar 12 12:50:05 PM PDT 24
Peak memory 210964 kb
Host smart-3419cd40-0108-40cc-aa88-3c5b64769557
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3995253537 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_p
assthru_mem_tl_intg_err.3995253537
Directory /workspace/19.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_same_csr_outstanding.3598627200
Short name T74
Test name
Test status
Simulation time 8890768196 ps
CPU time 10.82 seconds
Started Mar 12 12:49:07 PM PDT 24
Finished Mar 12 12:49:18 PM PDT 24
Peak memory 210984 kb
Host smart-0b299d94-742e-4ed5-880e-4d7457408a62
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3598627200 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_
ctrl_same_csr_outstanding.3598627200
Directory /workspace/19.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_errors.3727144890
Short name T420
Test name
Test status
Simulation time 2436722930 ps
CPU time 14.82 seconds
Started Mar 12 12:49:08 PM PDT 24
Finished Mar 12 12:49:24 PM PDT 24
Peak memory 215148 kb
Host smart-ff68fd66-03f3-4c2a-8c3e-046aa891c4a4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3727144890 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_tl_errors.3727144890
Directory /workspace/19.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_intg_err.2917716937
Short name T125
Test name
Test status
Simulation time 996350388 ps
CPU time 37.45 seconds
Started Mar 12 12:49:14 PM PDT 24
Finished Mar 12 12:49:52 PM PDT 24
Peak memory 211060 kb
Host smart-ee204a23-89a5-45bc-943a-c92b5d4da061
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2917716937 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_tl_i
ntg_err.2917716937
Directory /workspace/19.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_aliasing.2414425476
Short name T117
Test name
Test status
Simulation time 1107188909 ps
CPU time 10.74 seconds
Started Mar 12 12:48:55 PM PDT 24
Finished Mar 12 12:49:06 PM PDT 24
Peak memory 210844 kb
Host smart-4ef7a3aa-128a-4b80-90a1-0a2e333347e3
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2414425476 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_alia
sing.2414425476
Directory /workspace/2.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_bit_bash.2146700632
Short name T386
Test name
Test status
Simulation time 684082523 ps
CPU time 6.66 seconds
Started Mar 12 12:48:30 PM PDT 24
Finished Mar 12 12:48:37 PM PDT 24
Peak memory 210836 kb
Host smart-020ceff6-2c8d-4ebe-9f68-2a2e49290323
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2146700632 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_bit_
bash.2146700632
Directory /workspace/2.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_hw_reset.1619785962
Short name T423
Test name
Test status
Simulation time 91344732 ps
CPU time 5.75 seconds
Started Mar 12 12:48:35 PM PDT 24
Finished Mar 12 12:48:41 PM PDT 24
Peak memory 210728 kb
Host smart-7853be73-dbdb-40c1-a88d-a1b5de2a35ab
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1619785962 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_hw_r
eset.1619785962
Directory /workspace/2.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_mem_rw_with_rand_reset.918001226
Short name T463
Test name
Test status
Simulation time 1387822205 ps
CPU time 12.57 seconds
Started Mar 12 12:48:39 PM PDT 24
Finished Mar 12 12:48:51 PM PDT 24
Peak memory 219028 kb
Host smart-ec04f6fb-ba2f-4302-9ff1-17f9de8b5ad7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=918001226 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 2.rom_ctrl_csr_mem_rw_with_rand_reset.918001226
Directory /workspace/2.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_rw.2018712485
Short name T456
Test name
Test status
Simulation time 2244195964 ps
CPU time 8.66 seconds
Started Mar 12 12:48:31 PM PDT 24
Finished Mar 12 12:48:41 PM PDT 24
Peak memory 210900 kb
Host smart-3d916117-c28c-4003-ae59-1062b020c4f1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2018712485 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_rw.2018712485
Directory /workspace/2.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_partial_access.2307812757
Short name T452
Test name
Test status
Simulation time 8516360940 ps
CPU time 15.86 seconds
Started Mar 12 12:48:34 PM PDT 24
Finished Mar 12 12:48:50 PM PDT 24
Peak memory 210780 kb
Host smart-53b5cb26-6fd1-4aed-a913-692c7ebe08bf
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2307812757 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctr
l_mem_partial_access.2307812757
Directory /workspace/2.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_walk.1170050708
Short name T387
Test name
Test status
Simulation time 2500066477 ps
CPU time 13.78 seconds
Started Mar 12 12:48:29 PM PDT 24
Finished Mar 12 12:48:43 PM PDT 24
Peak memory 210888 kb
Host smart-751e39ff-a421-4f10-ac58-1180996bf764
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1170050708 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_mem_walk
.1170050708
Directory /workspace/2.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_same_csr_outstanding.1976379634
Short name T66
Test name
Test status
Simulation time 12046960695 ps
CPU time 15.03 seconds
Started Mar 12 12:48:34 PM PDT 24
Finished Mar 12 12:48:49 PM PDT 24
Peak memory 210848 kb
Host smart-dedd4f8c-53a8-4249-9f06-9c6109b97af6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1976379634 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_c
trl_same_csr_outstanding.1976379634
Directory /workspace/2.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_errors.2068866904
Short name T438
Test name
Test status
Simulation time 89119852 ps
CPU time 5.97 seconds
Started Mar 12 12:48:33 PM PDT 24
Finished Mar 12 12:48:40 PM PDT 24
Peak memory 214572 kb
Host smart-06e8d44b-3c34-4dac-b25b-bcb62d24037e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2068866904 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_tl_errors.2068866904
Directory /workspace/2.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_intg_err.4121168764
Short name T457
Test name
Test status
Simulation time 1024687245 ps
CPU time 41.91 seconds
Started Mar 12 12:48:34 PM PDT 24
Finished Mar 12 12:49:16 PM PDT 24
Peak memory 211128 kb
Host smart-f61c3bd1-7290-4f8e-9ce3-ceec0b211174
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4121168764 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_tl_in
tg_err.4121168764
Directory /workspace/2.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_aliasing.2169325045
Short name T97
Test name
Test status
Simulation time 420926938 ps
CPU time 6.95 seconds
Started Mar 12 12:48:35 PM PDT 24
Finished Mar 12 12:48:42 PM PDT 24
Peak memory 210812 kb
Host smart-d44b6c57-a60b-4f15-8d1f-c3cb7bded8f8
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2169325045 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_alia
sing.2169325045
Directory /workspace/3.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_bit_bash.2175487390
Short name T78
Test name
Test status
Simulation time 14155900440 ps
CPU time 14.99 seconds
Started Mar 12 12:48:29 PM PDT 24
Finished Mar 12 12:48:45 PM PDT 24
Peak memory 210864 kb
Host smart-1f4ecb65-109d-4da7-9559-692c3d89dd69
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2175487390 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_bit_
bash.2175487390
Directory /workspace/3.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_hw_reset.3286765504
Short name T389
Test name
Test status
Simulation time 254102570 ps
CPU time 9.18 seconds
Started Mar 12 12:48:39 PM PDT 24
Finished Mar 12 12:48:48 PM PDT 24
Peak memory 210844 kb
Host smart-211caee5-1627-49fd-93f4-66557e3b5317
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3286765504 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_hw_r
eset.3286765504
Directory /workspace/3.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_mem_rw_with_rand_reset.946590211
Short name T451
Test name
Test status
Simulation time 1874880266 ps
CPU time 6.67 seconds
Started Mar 12 12:48:35 PM PDT 24
Finished Mar 12 12:48:42 PM PDT 24
Peak memory 214336 kb
Host smart-12e2c337-2865-4490-a0ff-6d0d81409739
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=946590211 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 3.rom_ctrl_csr_mem_rw_with_rand_reset.946590211
Directory /workspace/3.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_rw.3104670114
Short name T401
Test name
Test status
Simulation time 347688555 ps
CPU time 4.09 seconds
Started Mar 12 12:48:39 PM PDT 24
Finished Mar 12 12:48:43 PM PDT 24
Peak memory 210848 kb
Host smart-f6feaf84-5324-49bf-b31d-89b416dff2cf
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3104670114 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_rw.3104670114
Directory /workspace/3.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_partial_access.2037320253
Short name T405
Test name
Test status
Simulation time 396878475 ps
CPU time 4.03 seconds
Started Mar 12 12:48:32 PM PDT 24
Finished Mar 12 12:48:36 PM PDT 24
Peak memory 210720 kb
Host smart-55e50bea-4f36-48f5-95ac-739c751a9330
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2037320253 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctr
l_mem_partial_access.2037320253
Directory /workspace/3.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_walk.4259742207
Short name T379
Test name
Test status
Simulation time 4109754261 ps
CPU time 14.57 seconds
Started Mar 12 12:48:34 PM PDT 24
Finished Mar 12 12:48:49 PM PDT 24
Peak memory 210792 kb
Host smart-83b4f409-53d7-49b7-8066-e82e328d7d2c
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4259742207 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_mem_walk
.4259742207
Directory /workspace/3.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_passthru_mem_tl_intg_err.3459692677
Short name T100
Test name
Test status
Simulation time 38039802466 ps
CPU time 81.28 seconds
Started Mar 12 12:48:31 PM PDT 24
Finished Mar 12 12:49:53 PM PDT 24
Peak memory 210908 kb
Host smart-ddec75e6-fe41-4882-a77a-83d13c342a2f
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3459692677 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_pa
ssthru_mem_tl_intg_err.3459692677
Directory /workspace/3.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_same_csr_outstanding.1825596096
Short name T111
Test name
Test status
Simulation time 1093342367 ps
CPU time 7.75 seconds
Started Mar 12 12:48:44 PM PDT 24
Finished Mar 12 12:48:52 PM PDT 24
Peak memory 210804 kb
Host smart-41a87091-7016-44c2-8a65-0e8416e3a271
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1825596096 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_c
trl_same_csr_outstanding.1825596096
Directory /workspace/3.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_errors.3678250716
Short name T427
Test name
Test status
Simulation time 695352783 ps
CPU time 8.27 seconds
Started Mar 12 12:48:46 PM PDT 24
Finished Mar 12 12:48:55 PM PDT 24
Peak memory 213940 kb
Host smart-33b0968d-0d99-4e4f-9443-4f8824557921
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3678250716 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_tl_errors.3678250716
Directory /workspace/3.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_aliasing.2419732593
Short name T403
Test name
Test status
Simulation time 3508953830 ps
CPU time 14.2 seconds
Started Mar 12 12:48:32 PM PDT 24
Finished Mar 12 12:48:46 PM PDT 24
Peak memory 210880 kb
Host smart-95c7e74f-43bf-4316-acbf-36093dec903c
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2419732593 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_alia
sing.2419732593
Directory /workspace/4.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_bit_bash.318258392
Short name T431
Test name
Test status
Simulation time 168480062 ps
CPU time 5.79 seconds
Started Mar 12 12:48:34 PM PDT 24
Finished Mar 12 12:48:40 PM PDT 24
Peak memory 210812 kb
Host smart-14f636b6-045a-44bb-9109-9e1d16fd79c8
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=318258392 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_bit_b
ash.318258392
Directory /workspace/4.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_hw_reset.2027649149
Short name T372
Test name
Test status
Simulation time 3401205997 ps
CPU time 15.36 seconds
Started Mar 12 12:48:30 PM PDT 24
Finished Mar 12 12:48:45 PM PDT 24
Peak memory 210788 kb
Host smart-34acf58c-10b9-4789-a447-a15c79c125c5
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2027649149 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_hw_r
eset.2027649149
Directory /workspace/4.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_mem_rw_with_rand_reset.1889904744
Short name T396
Test name
Test status
Simulation time 6680631410 ps
CPU time 14.01 seconds
Started Mar 12 12:48:37 PM PDT 24
Finished Mar 12 12:48:51 PM PDT 24
Peak memory 214916 kb
Host smart-037ea51b-5cca-4603-9ff4-4a0ab646d2ea
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1889904744 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 4.rom_ctrl_csr_mem_rw_with_rand_reset.1889904744
Directory /workspace/4.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_rw.3926792152
Short name T447
Test name
Test status
Simulation time 3577532525 ps
CPU time 14.64 seconds
Started Mar 12 12:48:41 PM PDT 24
Finished Mar 12 12:48:56 PM PDT 24
Peak memory 210588 kb
Host smart-5c2bd453-e908-490a-8d29-a5fa615aee09
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3926792152 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_rw.3926792152
Directory /workspace/4.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_partial_access.1634563258
Short name T400
Test name
Test status
Simulation time 4136788652 ps
CPU time 10.11 seconds
Started Mar 12 12:48:35 PM PDT 24
Finished Mar 12 12:48:45 PM PDT 24
Peak memory 210848 kb
Host smart-c1b1d24f-a699-4685-9178-dcc9536e5e4d
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1634563258 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctr
l_mem_partial_access.1634563258
Directory /workspace/4.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_walk.1490579910
Short name T370
Test name
Test status
Simulation time 2727635403 ps
CPU time 6.97 seconds
Started Mar 12 12:48:33 PM PDT 24
Finished Mar 12 12:48:40 PM PDT 24
Peak memory 210808 kb
Host smart-5b56673f-4b61-460b-a2dd-77f9235516a3
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1490579910 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_mem_walk
.1490579910
Directory /workspace/4.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_passthru_mem_tl_intg_err.350470052
Short name T120
Test name
Test status
Simulation time 18443931354 ps
CPU time 44.77 seconds
Started Mar 12 12:48:40 PM PDT 24
Finished Mar 12 12:49:25 PM PDT 24
Peak memory 210964 kb
Host smart-a57b2997-3a88-41fd-8b20-4fbae43a8028
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=350470052 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_pas
sthru_mem_tl_intg_err.350470052
Directory /workspace/4.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_same_csr_outstanding.2208522085
Short name T409
Test name
Test status
Simulation time 2396822626 ps
CPU time 11.59 seconds
Started Mar 12 12:48:31 PM PDT 24
Finished Mar 12 12:48:43 PM PDT 24
Peak memory 210872 kb
Host smart-da04ca76-31e5-4bbe-9edd-e878179eeb63
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2208522085 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_c
trl_same_csr_outstanding.2208522085
Directory /workspace/4.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_errors.605935264
Short name T419
Test name
Test status
Simulation time 171919987 ps
CPU time 7.93 seconds
Started Mar 12 12:48:33 PM PDT 24
Finished Mar 12 12:48:41 PM PDT 24
Peak memory 216264 kb
Host smart-fbd255a2-890e-42fb-a145-22097f1b3b3d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=605935264 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_tl_errors.605935264
Directory /workspace/4.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_intg_err.555002465
Short name T124
Test name
Test status
Simulation time 556140523 ps
CPU time 71.38 seconds
Started Mar 12 12:48:31 PM PDT 24
Finished Mar 12 12:49:44 PM PDT 24
Peak memory 211548 kb
Host smart-0b16b924-e68d-447a-8656-34ef8f58e7a0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=555002465 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_tl_int
g_err.555002465
Directory /workspace/4.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_mem_rw_with_rand_reset.1267772596
Short name T399
Test name
Test status
Simulation time 364164215 ps
CPU time 7.79 seconds
Started Mar 12 12:48:40 PM PDT 24
Finished Mar 12 12:48:48 PM PDT 24
Peak memory 215244 kb
Host smart-e996fb6f-882f-4cc1-a38b-1572a0055547
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1267772596 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 5.rom_ctrl_csr_mem_rw_with_rand_reset.1267772596
Directory /workspace/5.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_rw.1127760560
Short name T407
Test name
Test status
Simulation time 2391002735 ps
CPU time 10.93 seconds
Started Mar 12 12:48:51 PM PDT 24
Finished Mar 12 12:49:02 PM PDT 24
Peak memory 210868 kb
Host smart-40df97c4-9232-4ab9-a016-3953550b41bc
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1127760560 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_csr_rw.1127760560
Directory /workspace/5.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_passthru_mem_tl_intg_err.181393476
Short name T90
Test name
Test status
Simulation time 2269855948 ps
CPU time 28.4 seconds
Started Mar 12 12:48:45 PM PDT 24
Finished Mar 12 12:49:13 PM PDT 24
Peak memory 210872 kb
Host smart-1681ca8a-3ddf-430f-b775-0b2f9d450926
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=181393476 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_pas
sthru_mem_tl_intg_err.181393476
Directory /workspace/5.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_same_csr_outstanding.351556023
Short name T426
Test name
Test status
Simulation time 1962917762 ps
CPU time 15.62 seconds
Started Mar 12 12:48:37 PM PDT 24
Finished Mar 12 12:48:53 PM PDT 24
Peak memory 210812 kb
Host smart-64da4b56-3954-4c9d-acf5-5fd653bd72e8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=351556023 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ct
rl_same_csr_outstanding.351556023
Directory /workspace/5.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_errors.636162667
Short name T444
Test name
Test status
Simulation time 334164670 ps
CPU time 6.3 seconds
Started Mar 12 12:48:42 PM PDT 24
Finished Mar 12 12:48:48 PM PDT 24
Peak memory 214788 kb
Host smart-2240c424-e0e3-44ba-9da8-350806e038a1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=636162667 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_tl_errors.636162667
Directory /workspace/5.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_intg_err.3982152593
Short name T445
Test name
Test status
Simulation time 298584850 ps
CPU time 36.98 seconds
Started Mar 12 12:48:51 PM PDT 24
Finished Mar 12 12:49:28 PM PDT 24
Peak memory 211344 kb
Host smart-55a63240-4c45-4a97-a445-609a5de244e0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3982152593 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_tl_in
tg_err.3982152593
Directory /workspace/5.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_mem_rw_with_rand_reset.2123502678
Short name T416
Test name
Test status
Simulation time 202556030 ps
CPU time 4.97 seconds
Started Mar 12 12:48:37 PM PDT 24
Finished Mar 12 12:48:42 PM PDT 24
Peak memory 214652 kb
Host smart-0dadbf83-e880-481c-a289-681c30fcb738
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2123502678 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 6.rom_ctrl_csr_mem_rw_with_rand_reset.2123502678
Directory /workspace/6.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_rw.2848373929
Short name T392
Test name
Test status
Simulation time 4521919199 ps
CPU time 14.13 seconds
Started Mar 12 12:48:52 PM PDT 24
Finished Mar 12 12:49:06 PM PDT 24
Peak memory 210928 kb
Host smart-f803c24c-729a-47e9-8f74-af2f27ffb770
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2848373929 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_csr_rw.2848373929
Directory /workspace/6.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_passthru_mem_tl_intg_err.1091176087
Short name T442
Test name
Test status
Simulation time 5935183717 ps
CPU time 19.11 seconds
Started Mar 12 12:48:37 PM PDT 24
Finished Mar 12 12:48:56 PM PDT 24
Peak memory 210964 kb
Host smart-d4e451a4-ea09-443c-91ea-b8cee3a85ac1
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1091176087 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_pa
ssthru_mem_tl_intg_err.1091176087
Directory /workspace/6.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_same_csr_outstanding.1073223504
Short name T430
Test name
Test status
Simulation time 100532398 ps
CPU time 6.11 seconds
Started Mar 12 12:48:39 PM PDT 24
Finished Mar 12 12:48:46 PM PDT 24
Peak memory 210804 kb
Host smart-fd322066-36e6-464b-a47d-4d50e4f21ad5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1073223504 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_c
trl_same_csr_outstanding.1073223504
Directory /workspace/6.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_errors.1510072215
Short name T437
Test name
Test status
Simulation time 1655874076 ps
CPU time 18.23 seconds
Started Mar 12 12:48:41 PM PDT 24
Finished Mar 12 12:48:59 PM PDT 24
Peak memory 215044 kb
Host smart-3dffbb7b-57a2-4664-b2eb-300f43787c93
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1510072215 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_tl_errors.1510072215
Directory /workspace/6.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_intg_err.594986919
Short name T132
Test name
Test status
Simulation time 2016802452 ps
CPU time 69.76 seconds
Started Mar 12 12:48:36 PM PDT 24
Finished Mar 12 12:49:46 PM PDT 24
Peak memory 210772 kb
Host smart-6f83d4db-630c-44c4-9291-ec2067f5df7c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=594986919 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_tl_int
g_err.594986919
Directory /workspace/6.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_mem_rw_with_rand_reset.4153219999
Short name T398
Test name
Test status
Simulation time 3291154860 ps
CPU time 12.86 seconds
Started Mar 12 12:48:53 PM PDT 24
Finished Mar 12 12:49:06 PM PDT 24
Peak memory 213040 kb
Host smart-124f7479-9412-448f-8067-bbd81f1a99a8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4153219999 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 7.rom_ctrl_csr_mem_rw_with_rand_reset.4153219999
Directory /workspace/7.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_rw.2871337685
Short name T433
Test name
Test status
Simulation time 2462998092 ps
CPU time 7.89 seconds
Started Mar 12 12:48:38 PM PDT 24
Finished Mar 12 12:48:46 PM PDT 24
Peak memory 210924 kb
Host smart-2bea12a9-4035-4147-a1cd-1091d185bd83
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2871337685 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_csr_rw.2871337685
Directory /workspace/7.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_passthru_mem_tl_intg_err.3387673362
Short name T432
Test name
Test status
Simulation time 4276124576 ps
CPU time 44.12 seconds
Started Mar 12 12:48:48 PM PDT 24
Finished Mar 12 12:49:33 PM PDT 24
Peak memory 210888 kb
Host smart-aaf8d126-60dc-49f1-96b6-7f118d45f74a
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3387673362 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_pa
ssthru_mem_tl_intg_err.3387673362
Directory /workspace/7.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_same_csr_outstanding.1618531807
Short name T114
Test name
Test status
Simulation time 2780331119 ps
CPU time 13.69 seconds
Started Mar 12 12:48:38 PM PDT 24
Finished Mar 12 12:48:52 PM PDT 24
Peak memory 210904 kb
Host smart-951d078b-890c-4df8-aaf5-45eb20695632
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1618531807 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_c
trl_same_csr_outstanding.1618531807
Directory /workspace/7.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_errors.1075650401
Short name T376
Test name
Test status
Simulation time 107840348 ps
CPU time 7.86 seconds
Started Mar 12 12:48:45 PM PDT 24
Finished Mar 12 12:48:53 PM PDT 24
Peak memory 213936 kb
Host smart-f9c415d0-8996-43f8-be98-dfb04d0305d3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1075650401 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_tl_errors.1075650401
Directory /workspace/7.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_intg_err.4061659027
Short name T127
Test name
Test status
Simulation time 1397995712 ps
CPU time 39.83 seconds
Started Mar 12 12:48:39 PM PDT 24
Finished Mar 12 12:49:19 PM PDT 24
Peak memory 211440 kb
Host smart-092c9410-7f0b-43e2-b422-e5630bcfbd20
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4061659027 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_tl_in
tg_err.4061659027
Directory /workspace/7.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_mem_rw_with_rand_reset.2813037380
Short name T415
Test name
Test status
Simulation time 378411428 ps
CPU time 4.29 seconds
Started Mar 12 12:48:51 PM PDT 24
Finished Mar 12 12:48:55 PM PDT 24
Peak memory 211248 kb
Host smart-69bfa7a9-2da5-4039-8697-847c50707c2d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2813037380 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 8.rom_ctrl_csr_mem_rw_with_rand_reset.2813037380
Directory /workspace/8.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_rw.2118112863
Short name T397
Test name
Test status
Simulation time 334000563 ps
CPU time 4.14 seconds
Started Mar 12 12:48:54 PM PDT 24
Finished Mar 12 12:48:58 PM PDT 24
Peak memory 210816 kb
Host smart-cf3c917f-7fa4-4fdb-961c-a92829d42bb8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2118112863 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_csr_rw.2118112863
Directory /workspace/8.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_passthru_mem_tl_intg_err.3093636639
Short name T99
Test name
Test status
Simulation time 31366662730 ps
CPU time 63.29 seconds
Started Mar 12 12:48:49 PM PDT 24
Finished Mar 12 12:49:53 PM PDT 24
Peak memory 210924 kb
Host smart-d8e1060a-ef72-4016-a560-2d6664109887
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3093636639 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_pa
ssthru_mem_tl_intg_err.3093636639
Directory /workspace/8.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_same_csr_outstanding.93114675
Short name T381
Test name
Test status
Simulation time 10956764936 ps
CPU time 11.23 seconds
Started Mar 12 12:48:46 PM PDT 24
Finished Mar 12 12:48:58 PM PDT 24
Peak memory 210952 kb
Host smart-a94514a9-002c-47c2-89a2-1582001b31b9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=93114675 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctr
l_same_csr_outstanding.93114675
Directory /workspace/8.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_errors.1168235456
Short name T388
Test name
Test status
Simulation time 8650691997 ps
CPU time 18.96 seconds
Started Mar 12 12:48:40 PM PDT 24
Finished Mar 12 12:48:59 PM PDT 24
Peak memory 215492 kb
Host smart-5cf504a3-18db-4c3b-9178-f7a70c394f45
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1168235456 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_tl_errors.1168235456
Directory /workspace/8.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_intg_err.2034467624
Short name T414
Test name
Test status
Simulation time 1585073321 ps
CPU time 44.53 seconds
Started Mar 12 12:48:37 PM PDT 24
Finished Mar 12 12:49:22 PM PDT 24
Peak memory 210732 kb
Host smart-23cfb0af-92ff-41c7-800f-eaf790f4a86a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2034467624 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_tl_in
tg_err.2034467624
Directory /workspace/8.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_mem_rw_with_rand_reset.2417404263
Short name T462
Test name
Test status
Simulation time 1367945945 ps
CPU time 12.91 seconds
Started Mar 12 12:48:37 PM PDT 24
Finished Mar 12 12:48:55 PM PDT 24
Peak memory 215812 kb
Host smart-b44a8f18-6303-4959-8bf9-7cd574efb4bc
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2417404263 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 9.rom_ctrl_csr_mem_rw_with_rand_reset.2417404263
Directory /workspace/9.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_rw.176127959
Short name T404
Test name
Test status
Simulation time 31506886506 ps
CPU time 14.99 seconds
Started Mar 12 12:48:48 PM PDT 24
Finished Mar 12 12:49:04 PM PDT 24
Peak memory 210936 kb
Host smart-391e443a-e091-49f2-8da5-bfa89020c411
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=176127959 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_csr_rw.176127959
Directory /workspace/9.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_passthru_mem_tl_intg_err.1961472304
Short name T91
Test name
Test status
Simulation time 14786006767 ps
CPU time 63.94 seconds
Started Mar 12 12:48:37 PM PDT 24
Finished Mar 12 12:49:41 PM PDT 24
Peak memory 210872 kb
Host smart-469545f3-c5be-400e-aa3d-561792bb573a
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1961472304 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_pa
ssthru_mem_tl_intg_err.1961472304
Directory /workspace/9.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_same_csr_outstanding.3315126966
Short name T385
Test name
Test status
Simulation time 1622669415 ps
CPU time 14.87 seconds
Started Mar 12 12:48:46 PM PDT 24
Finished Mar 12 12:49:01 PM PDT 24
Peak memory 210828 kb
Host smart-7589a07a-d1fd-4e5f-be94-121c98d906fd
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3315126966 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_c
trl_same_csr_outstanding.3315126966
Directory /workspace/9.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_errors.992798768
Short name T373
Test name
Test status
Simulation time 87177558 ps
CPU time 7.16 seconds
Started Mar 12 12:48:50 PM PDT 24
Finished Mar 12 12:48:57 PM PDT 24
Peak memory 214996 kb
Host smart-ae93d7a8-302a-4ed5-91b0-4d7ccb23710e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=992798768 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_tl_errors.992798768
Directory /workspace/9.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/default/0.rom_ctrl_alert_test.316967733
Short name T288
Test name
Test status
Simulation time 1479108609 ps
CPU time 8.99 seconds
Started Mar 12 12:33:07 PM PDT 24
Finished Mar 12 12:33:16 PM PDT 24
Peak memory 210124 kb
Host smart-d7353da1-e3a3-480e-9a8e-c695b29f8f4a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=316967733 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_alert_test.316967733
Directory /workspace/0.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/0.rom_ctrl_corrupt_sig_fatal_chk.2217332698
Short name T216
Test name
Test status
Simulation time 3307188528 ps
CPU time 85.6 seconds
Started Mar 12 12:33:04 PM PDT 24
Finished Mar 12 12:34:30 PM PDT 24
Peak memory 211796 kb
Host smart-bf225cfb-9e10-4f21-85b1-09a00ad7c62d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2217332698 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_c
orrupt_sig_fatal_chk.2217332698
Directory /workspace/0.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/0.rom_ctrl_kmac_err_chk.3164236989
Short name T198
Test name
Test status
Simulation time 13647844380 ps
CPU time 27.98 seconds
Started Mar 12 12:33:01 PM PDT 24
Finished Mar 12 12:33:29 PM PDT 24
Peak memory 211104 kb
Host smart-fc6ba08a-b438-4518-b6e5-5e723dda91fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3164236989 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_kmac_err_chk.3164236989
Directory /workspace/0.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/0.rom_ctrl_max_throughput_chk.335284254
Short name T310
Test name
Test status
Simulation time 957437548 ps
CPU time 10.39 seconds
Started Mar 12 12:33:07 PM PDT 24
Finished Mar 12 12:33:17 PM PDT 24
Peak memory 210140 kb
Host smart-734fc602-ef1a-4cf3-b088-3f9dc6e7d3f9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=335284254 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_max_throughput_chk.335284254
Directory /workspace/0.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/0.rom_ctrl_smoke.2145488070
Short name T295
Test name
Test status
Simulation time 788229306 ps
CPU time 14.87 seconds
Started Mar 12 12:32:58 PM PDT 24
Finished Mar 12 12:33:13 PM PDT 24
Peak memory 212036 kb
Host smart-ced794b3-8207-40ff-815c-7a19c428bf83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2145488070 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_smoke.2145488070
Directory /workspace/0.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/0.rom_ctrl_stress_all.2513263113
Short name T24
Test name
Test status
Simulation time 6658463645 ps
CPU time 63.94 seconds
Started Mar 12 12:32:57 PM PDT 24
Finished Mar 12 12:34:01 PM PDT 24
Peak memory 215740 kb
Host smart-f2290601-52dd-4c41-b1f7-3ef11a98c028
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2513263113 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 0.rom_ctrl_stress_all.2513263113
Directory /workspace/0.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/1.rom_ctrl_alert_test.3868254976
Short name T205
Test name
Test status
Simulation time 141131013 ps
CPU time 4.3 seconds
Started Mar 12 12:32:55 PM PDT 24
Finished Mar 12 12:33:00 PM PDT 24
Peak memory 210348 kb
Host smart-8af3c3a5-4866-4d5a-859e-372c4ba3b09a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3868254976 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_alert_test.3868254976
Directory /workspace/1.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/1.rom_ctrl_corrupt_sig_fatal_chk.591626754
Short name T222
Test name
Test status
Simulation time 18693774482 ps
CPU time 215.74 seconds
Started Mar 12 12:32:57 PM PDT 24
Finished Mar 12 12:36:33 PM PDT 24
Peak memory 236268 kb
Host smart-50c721b8-04fa-4319-9b39-a21d47555333
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=591626754 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_co
rrupt_sig_fatal_chk.591626754
Directory /workspace/1.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/1.rom_ctrl_kmac_err_chk.2399620869
Short name T312
Test name
Test status
Simulation time 8191521004 ps
CPU time 31.79 seconds
Started Mar 12 12:32:57 PM PDT 24
Finished Mar 12 12:33:29 PM PDT 24
Peak memory 211340 kb
Host smart-8d92654c-066f-43f3-99b7-42eaf3bded72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2399620869 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_kmac_err_chk.2399620869
Directory /workspace/1.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/1.rom_ctrl_sec_cm.1701626954
Short name T35
Test name
Test status
Simulation time 5357722495 ps
CPU time 58.4 seconds
Started Mar 12 12:33:00 PM PDT 24
Finished Mar 12 12:33:59 PM PDT 24
Peak memory 236204 kb
Host smart-620ea80f-4ba4-4dfd-896f-1bf7aa36f45a
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1701626954 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_sec_cm.1701626954
Directory /workspace/1.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/1.rom_ctrl_smoke.110247978
Short name T37
Test name
Test status
Simulation time 9980863013 ps
CPU time 24.54 seconds
Started Mar 12 12:33:10 PM PDT 24
Finished Mar 12 12:33:35 PM PDT 24
Peak memory 210676 kb
Host smart-01e53e8b-8714-4043-9b78-db3de1201997
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=110247978 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_smoke.110247978
Directory /workspace/1.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/1.rom_ctrl_stress_all.1360061224
Short name T253
Test name
Test status
Simulation time 3095871942 ps
CPU time 16.21 seconds
Started Mar 12 12:32:59 PM PDT 24
Finished Mar 12 12:33:16 PM PDT 24
Peak memory 218664 kb
Host smart-afcdaa8c-2b01-4b06-a441-94f9f6d3ac89
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1360061224 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 1.rom_ctrl_stress_all.1360061224
Directory /workspace/1.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/10.rom_ctrl_alert_test.3042304559
Short name T256
Test name
Test status
Simulation time 4484320321 ps
CPU time 15.74 seconds
Started Mar 12 12:33:19 PM PDT 24
Finished Mar 12 12:33:35 PM PDT 24
Peak memory 210508 kb
Host smart-3a1f3705-6f30-4e85-aeaa-ff0eb3efd246
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3042304559 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_alert_test.3042304559
Directory /workspace/10.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/10.rom_ctrl_corrupt_sig_fatal_chk.3022947873
Short name T364
Test name
Test status
Simulation time 22012578300 ps
CPU time 178.35 seconds
Started Mar 12 12:33:19 PM PDT 24
Finished Mar 12 12:36:17 PM PDT 24
Peak memory 223948 kb
Host smart-8d7cd9f4-36a5-4584-8ef7-1dfabb6692d7
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3022947873 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_
corrupt_sig_fatal_chk.3022947873
Directory /workspace/10.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/10.rom_ctrl_kmac_err_chk.2795933714
Short name T106
Test name
Test status
Simulation time 15989401589 ps
CPU time 33.77 seconds
Started Mar 12 12:33:24 PM PDT 24
Finished Mar 12 12:33:58 PM PDT 24
Peak memory 210504 kb
Host smart-ac27e9e8-53ab-435f-bbe0-2047aa3c7619
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2795933714 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_kmac_err_chk.2795933714
Directory /workspace/10.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/10.rom_ctrl_max_throughput_chk.3871463372
Short name T241
Test name
Test status
Simulation time 371010285 ps
CPU time 5.26 seconds
Started Mar 12 12:33:18 PM PDT 24
Finished Mar 12 12:33:24 PM PDT 24
Peak memory 210260 kb
Host smart-a3d749a6-0c4d-47a9-b7a0-6b090fbadb9e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3871463372 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_max_throughput_chk.3871463372
Directory /workspace/10.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/10.rom_ctrl_smoke.2382088100
Short name T174
Test name
Test status
Simulation time 1369066841 ps
CPU time 15.47 seconds
Started Mar 12 12:33:17 PM PDT 24
Finished Mar 12 12:33:32 PM PDT 24
Peak memory 212276 kb
Host smart-1b170bc3-3315-44e3-930c-e2fc7774c5b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2382088100 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_smoke.2382088100
Directory /workspace/10.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/10.rom_ctrl_stress_all.4119966693
Short name T272
Test name
Test status
Simulation time 12496528674 ps
CPU time 54.95 seconds
Started Mar 12 12:33:21 PM PDT 24
Finished Mar 12 12:34:17 PM PDT 24
Peak memory 218568 kb
Host smart-05715847-c382-40ef-8479-1ef7f95e0eeb
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4119966693 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 10.rom_ctrl_stress_all.4119966693
Directory /workspace/10.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/11.rom_ctrl_alert_test.3318947403
Short name T270
Test name
Test status
Simulation time 1383124285 ps
CPU time 10.63 seconds
Started Mar 12 12:33:17 PM PDT 24
Finished Mar 12 12:33:27 PM PDT 24
Peak memory 210364 kb
Host smart-1b749f95-6534-4472-b771-0e23cb74656d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3318947403 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_alert_test.3318947403
Directory /workspace/11.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/11.rom_ctrl_corrupt_sig_fatal_chk.1437168813
Short name T242
Test name
Test status
Simulation time 41324006992 ps
CPU time 406.15 seconds
Started Mar 12 12:33:18 PM PDT 24
Finished Mar 12 12:40:05 PM PDT 24
Peak memory 232928 kb
Host smart-f4ff71c4-2f91-4661-877c-b95371e6601f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1437168813 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_
corrupt_sig_fatal_chk.1437168813
Directory /workspace/11.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/11.rom_ctrl_kmac_err_chk.374585813
Short name T350
Test name
Test status
Simulation time 175590463 ps
CPU time 9 seconds
Started Mar 12 12:33:19 PM PDT 24
Finished Mar 12 12:33:28 PM PDT 24
Peak memory 210856 kb
Host smart-24c36fe1-fda0-417c-bab2-6673b5c17480
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=374585813 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_kmac_err_chk.374585813
Directory /workspace/11.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/11.rom_ctrl_max_throughput_chk.3989286800
Short name T223
Test name
Test status
Simulation time 1287814016 ps
CPU time 12.68 seconds
Started Mar 12 12:33:19 PM PDT 24
Finished Mar 12 12:33:32 PM PDT 24
Peak memory 210272 kb
Host smart-97ed1775-2ed6-419a-8f45-e15ebe92952d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3989286800 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_max_throughput_chk.3989286800
Directory /workspace/11.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/11.rom_ctrl_smoke.3479655195
Short name T150
Test name
Test status
Simulation time 23235303843 ps
CPU time 35.6 seconds
Started Mar 12 12:33:19 PM PDT 24
Finished Mar 12 12:33:55 PM PDT 24
Peak memory 212956 kb
Host smart-dba03624-dfc4-47df-9a3e-135021ae698e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3479655195 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_smoke.3479655195
Directory /workspace/11.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/11.rom_ctrl_stress_all.455516846
Short name T139
Test name
Test status
Simulation time 1025423124 ps
CPU time 15.6 seconds
Started Mar 12 12:33:19 PM PDT 24
Finished Mar 12 12:33:35 PM PDT 24
Peak memory 210212 kb
Host smart-7dfae28e-9cfa-400e-a207-8ea07b1f9929
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=455516846 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 11.rom_ctrl_stress_all.455516846
Directory /workspace/11.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/11.rom_ctrl_stress_all_with_rand_reset.3658491628
Short name T54
Test name
Test status
Simulation time 165129629916 ps
CPU time 1431.15 seconds
Started Mar 12 12:33:19 PM PDT 24
Finished Mar 12 12:57:10 PM PDT 24
Peak memory 235048 kb
Host smart-1c405e62-c962-4bab-84ea-973e4447550b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3658491628 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_stress_all_with_rand_reset.3658491628
Directory /workspace/11.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/12.rom_ctrl_alert_test.2942231662
Short name T32
Test name
Test status
Simulation time 1720971265 ps
CPU time 9.15 seconds
Started Mar 12 12:33:23 PM PDT 24
Finished Mar 12 12:33:32 PM PDT 24
Peak memory 210352 kb
Host smart-8f9c65a9-7fb2-411c-bff5-ea06ad73b8aa
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2942231662 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_alert_test.2942231662
Directory /workspace/12.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/12.rom_ctrl_corrupt_sig_fatal_chk.3747382631
Short name T213
Test name
Test status
Simulation time 124975344123 ps
CPU time 343.2 seconds
Started Mar 12 12:33:18 PM PDT 24
Finished Mar 12 12:39:02 PM PDT 24
Peak memory 236084 kb
Host smart-b25ea368-ceeb-40d3-b403-994d5b818b5b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3747382631 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_
corrupt_sig_fatal_chk.3747382631
Directory /workspace/12.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/12.rom_ctrl_smoke.962394848
Short name T215
Test name
Test status
Simulation time 10466029894 ps
CPU time 28.03 seconds
Started Mar 12 12:33:18 PM PDT 24
Finished Mar 12 12:33:47 PM PDT 24
Peak memory 214268 kb
Host smart-3592636d-66af-4bb1-9a0a-dbb6dd9ce7e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=962394848 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_smoke.962394848
Directory /workspace/12.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/12.rom_ctrl_stress_all.2735120489
Short name T68
Test name
Test status
Simulation time 76793965962 ps
CPU time 42.43 seconds
Started Mar 12 12:33:22 PM PDT 24
Finished Mar 12 12:34:05 PM PDT 24
Peak memory 218580 kb
Host smart-b8ae74aa-3d67-4795-8c32-cc1ed352ff78
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2735120489 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 12.rom_ctrl_stress_all.2735120489
Directory /workspace/12.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/12.rom_ctrl_stress_all_with_rand_reset.785491897
Short name T122
Test name
Test status
Simulation time 25962500158 ps
CPU time 1101.87 seconds
Started Mar 12 12:33:17 PM PDT 24
Finished Mar 12 12:51:39 PM PDT 24
Peak memory 234980 kb
Host smart-fd3d68e1-6a87-410c-a6dc-45ddcf1be699
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=785491897 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_stress_all_with_rand_reset.785491897
Directory /workspace/12.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/13.rom_ctrl_alert_test.481916283
Short name T327
Test name
Test status
Simulation time 3024869312 ps
CPU time 10.48 seconds
Started Mar 12 12:33:18 PM PDT 24
Finished Mar 12 12:33:29 PM PDT 24
Peak memory 210436 kb
Host smart-4c4e1f2f-35f1-42fe-8529-9e63f760d02c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=481916283 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_alert_test.481916283
Directory /workspace/13.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/13.rom_ctrl_corrupt_sig_fatal_chk.843167771
Short name T232
Test name
Test status
Simulation time 1527230105 ps
CPU time 81.8 seconds
Started Mar 12 12:33:24 PM PDT 24
Finished Mar 12 12:34:46 PM PDT 24
Peak memory 219392 kb
Host smart-b4b46f70-a519-49d0-b229-167f9dc6ea61
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=843167771 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_c
orrupt_sig_fatal_chk.843167771
Directory /workspace/13.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/13.rom_ctrl_kmac_err_chk.2866399633
Short name T154
Test name
Test status
Simulation time 3101954396 ps
CPU time 26.11 seconds
Started Mar 12 12:33:20 PM PDT 24
Finished Mar 12 12:33:46 PM PDT 24
Peak memory 210940 kb
Host smart-c76d795f-fefb-41dc-b1aa-e30dd13fa7cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2866399633 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_kmac_err_chk.2866399633
Directory /workspace/13.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/13.rom_ctrl_max_throughput_chk.3725838102
Short name T316
Test name
Test status
Simulation time 346759498 ps
CPU time 5.25 seconds
Started Mar 12 12:33:18 PM PDT 24
Finished Mar 12 12:33:23 PM PDT 24
Peak memory 210184 kb
Host smart-52a83de3-c828-420a-a7cf-0cd06c8c00c9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3725838102 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_max_throughput_chk.3725838102
Directory /workspace/13.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/13.rom_ctrl_smoke.1117440384
Short name T168
Test name
Test status
Simulation time 182922530 ps
CPU time 10.31 seconds
Started Mar 12 12:33:19 PM PDT 24
Finished Mar 12 12:33:30 PM PDT 24
Peak memory 211648 kb
Host smart-bf0f0ab4-42fb-4d4c-8e32-73d9e6d808b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1117440384 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_smoke.1117440384
Directory /workspace/13.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/13.rom_ctrl_stress_all.1174676245
Short name T194
Test name
Test status
Simulation time 4526246532 ps
CPU time 25.37 seconds
Started Mar 12 12:33:22 PM PDT 24
Finished Mar 12 12:33:48 PM PDT 24
Peak memory 211944 kb
Host smart-8cd22060-2647-4f7d-ba33-051803a49718
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1174676245 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 13.rom_ctrl_stress_all.1174676245
Directory /workspace/13.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/14.rom_ctrl_alert_test.1429498335
Short name T259
Test name
Test status
Simulation time 431899441 ps
CPU time 6.7 seconds
Started Mar 12 12:33:25 PM PDT 24
Finished Mar 12 12:33:32 PM PDT 24
Peak memory 210384 kb
Host smart-1b989656-1948-4758-b6cd-13fafe7d04f4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1429498335 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_alert_test.1429498335
Directory /workspace/14.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/14.rom_ctrl_corrupt_sig_fatal_chk.2573947501
Short name T237
Test name
Test status
Simulation time 93448432797 ps
CPU time 221.59 seconds
Started Mar 12 12:33:26 PM PDT 24
Finished Mar 12 12:37:08 PM PDT 24
Peak memory 236132 kb
Host smart-af265530-7f69-4ae9-94bc-bea7c118dd56
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2573947501 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_
corrupt_sig_fatal_chk.2573947501
Directory /workspace/14.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/14.rom_ctrl_max_throughput_chk.1685300951
Short name T245
Test name
Test status
Simulation time 1420756058 ps
CPU time 13.74 seconds
Started Mar 12 12:33:30 PM PDT 24
Finished Mar 12 12:33:44 PM PDT 24
Peak memory 210232 kb
Host smart-62174ff0-fbf2-4832-9873-5a71fcb0b662
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1685300951 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_max_throughput_chk.1685300951
Directory /workspace/14.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/14.rom_ctrl_smoke.1176643127
Short name T255
Test name
Test status
Simulation time 9701537777 ps
CPU time 22.57 seconds
Started Mar 12 12:33:21 PM PDT 24
Finished Mar 12 12:33:44 PM PDT 24
Peak memory 212472 kb
Host smart-a60a315c-14f6-4cd6-bebc-060d845052f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1176643127 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_smoke.1176643127
Directory /workspace/14.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/14.rom_ctrl_stress_all.3985743090
Short name T238
Test name
Test status
Simulation time 28336276244 ps
CPU time 72.02 seconds
Started Mar 12 12:33:18 PM PDT 24
Finished Mar 12 12:34:31 PM PDT 24
Peak memory 218568 kb
Host smart-d85c2aa8-6d41-4658-96b7-c5aa1b29209f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3985743090 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 14.rom_ctrl_stress_all.3985743090
Directory /workspace/14.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/15.rom_ctrl_alert_test.2882945397
Short name T294
Test name
Test status
Simulation time 3638956766 ps
CPU time 14.24 seconds
Started Mar 12 12:33:26 PM PDT 24
Finished Mar 12 12:33:41 PM PDT 24
Peak memory 210480 kb
Host smart-746ee8f0-7bcb-48fe-8a75-c5cc5bc1e1a5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2882945397 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_alert_test.2882945397
Directory /workspace/15.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/15.rom_ctrl_corrupt_sig_fatal_chk.2516112827
Short name T46
Test name
Test status
Simulation time 82649583044 ps
CPU time 154.12 seconds
Started Mar 12 12:33:32 PM PDT 24
Finished Mar 12 12:36:06 PM PDT 24
Peak memory 211640 kb
Host smart-48542543-ba05-44b6-a56c-666b409ca36e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2516112827 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_
corrupt_sig_fatal_chk.2516112827
Directory /workspace/15.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/15.rom_ctrl_kmac_err_chk.929351899
Short name T366
Test name
Test status
Simulation time 176021268 ps
CPU time 9.18 seconds
Started Mar 12 12:33:26 PM PDT 24
Finished Mar 12 12:33:36 PM PDT 24
Peak memory 211100 kb
Host smart-ab0c6574-9fbc-40c3-9a1c-4aa423e850cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=929351899 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_kmac_err_chk.929351899
Directory /workspace/15.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/15.rom_ctrl_max_throughput_chk.3654244623
Short name T234
Test name
Test status
Simulation time 380103913 ps
CPU time 5.4 seconds
Started Mar 12 12:33:27 PM PDT 24
Finished Mar 12 12:33:32 PM PDT 24
Peak memory 210276 kb
Host smart-56c74c09-6ef4-478c-8e15-09f82848c1f8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3654244623 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_max_throughput_chk.3654244623
Directory /workspace/15.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/15.rom_ctrl_smoke.2967264091
Short name T166
Test name
Test status
Simulation time 820528883 ps
CPU time 9.85 seconds
Started Mar 12 12:33:25 PM PDT 24
Finished Mar 12 12:33:35 PM PDT 24
Peak memory 212272 kb
Host smart-9dc7550d-381e-47ff-a52d-9aee5a961a27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2967264091 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_smoke.2967264091
Directory /workspace/15.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/15.rom_ctrl_stress_all.3263910435
Short name T155
Test name
Test status
Simulation time 36213315653 ps
CPU time 19.64 seconds
Started Mar 12 12:33:28 PM PDT 24
Finished Mar 12 12:33:48 PM PDT 24
Peak memory 210516 kb
Host smart-8190a81f-9875-4529-aa14-00e9a2a8fc33
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3263910435 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 15.rom_ctrl_stress_all.3263910435
Directory /workspace/15.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/16.rom_ctrl_corrupt_sig_fatal_chk.3317852030
Short name T226
Test name
Test status
Simulation time 77729720654 ps
CPU time 203.48 seconds
Started Mar 12 12:33:37 PM PDT 24
Finished Mar 12 12:37:01 PM PDT 24
Peak memory 239308 kb
Host smart-4b2d57d2-b95b-4fd7-9a5c-7f3b4c525c95
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3317852030 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_
corrupt_sig_fatal_chk.3317852030
Directory /workspace/16.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/16.rom_ctrl_kmac_err_chk.3414650585
Short name T360
Test name
Test status
Simulation time 2616026484 ps
CPU time 24.87 seconds
Started Mar 12 12:33:27 PM PDT 24
Finished Mar 12 12:33:53 PM PDT 24
Peak memory 210472 kb
Host smart-b1325d28-a0b5-4ef6-b737-f6473e005009
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3414650585 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_kmac_err_chk.3414650585
Directory /workspace/16.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/16.rom_ctrl_max_throughput_chk.1382199048
Short name T356
Test name
Test status
Simulation time 987813467 ps
CPU time 11.11 seconds
Started Mar 12 12:33:47 PM PDT 24
Finished Mar 12 12:33:58 PM PDT 24
Peak memory 210276 kb
Host smart-f0cecb46-b26f-4d11-bc3b-cce53748779f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1382199048 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_max_throughput_chk.1382199048
Directory /workspace/16.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/16.rom_ctrl_smoke.485019765
Short name T200
Test name
Test status
Simulation time 6385833488 ps
CPU time 31.18 seconds
Started Mar 12 12:33:30 PM PDT 24
Finished Mar 12 12:34:01 PM PDT 24
Peak memory 213392 kb
Host smart-819c6c40-fd6c-406e-8c09-bcfc388764f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=485019765 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_smoke.485019765
Directory /workspace/16.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/17.rom_ctrl_alert_test.1313088256
Short name T307
Test name
Test status
Simulation time 346631007 ps
CPU time 4.17 seconds
Started Mar 12 12:33:24 PM PDT 24
Finished Mar 12 12:33:29 PM PDT 24
Peak memory 210356 kb
Host smart-0aedc88f-b01b-4470-9a0b-cac04c4f5761
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1313088256 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_alert_test.1313088256
Directory /workspace/17.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/17.rom_ctrl_corrupt_sig_fatal_chk.804449535
Short name T152
Test name
Test status
Simulation time 24237890109 ps
CPU time 130 seconds
Started Mar 12 12:33:27 PM PDT 24
Finished Mar 12 12:35:38 PM PDT 24
Peak memory 223956 kb
Host smart-44380956-d768-4754-a573-0fefc0255747
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=804449535 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_c
orrupt_sig_fatal_chk.804449535
Directory /workspace/17.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/17.rom_ctrl_kmac_err_chk.1153501092
Short name T239
Test name
Test status
Simulation time 2822244268 ps
CPU time 25.97 seconds
Started Mar 12 12:33:28 PM PDT 24
Finished Mar 12 12:33:54 PM PDT 24
Peak memory 210456 kb
Host smart-cfbc33b9-57e0-48d5-b3ce-406d2c0e09fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1153501092 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_kmac_err_chk.1153501092
Directory /workspace/17.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/17.rom_ctrl_max_throughput_chk.1264096748
Short name T274
Test name
Test status
Simulation time 2275885165 ps
CPU time 8.64 seconds
Started Mar 12 12:33:33 PM PDT 24
Finished Mar 12 12:33:42 PM PDT 24
Peak memory 210300 kb
Host smart-023792d4-d912-444b-9be6-da27ece4c9d0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1264096748 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_max_throughput_chk.1264096748
Directory /workspace/17.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/17.rom_ctrl_smoke.1570343649
Short name T148
Test name
Test status
Simulation time 854799970 ps
CPU time 10.12 seconds
Started Mar 12 12:33:31 PM PDT 24
Finished Mar 12 12:33:42 PM PDT 24
Peak memory 212948 kb
Host smart-686f18f7-ad91-421c-9ebe-66cd16df409a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1570343649 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_smoke.1570343649
Directory /workspace/17.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/17.rom_ctrl_stress_all.172437080
Short name T344
Test name
Test status
Simulation time 1814660427 ps
CPU time 27.33 seconds
Started Mar 12 12:33:33 PM PDT 24
Finished Mar 12 12:34:00 PM PDT 24
Peak memory 214852 kb
Host smart-9c46bea1-3599-45be-abdd-a02339206509
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=172437080 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 17.rom_ctrl_stress_all.172437080
Directory /workspace/17.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/18.rom_ctrl_alert_test.578089570
Short name T359
Test name
Test status
Simulation time 2096860964 ps
CPU time 16.85 seconds
Started Mar 12 12:33:25 PM PDT 24
Finished Mar 12 12:33:42 PM PDT 24
Peak memory 210344 kb
Host smart-d244e580-f0ec-4e2a-a27e-ffc7132da94a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=578089570 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_alert_test.578089570
Directory /workspace/18.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/18.rom_ctrl_corrupt_sig_fatal_chk.3789003269
Short name T202
Test name
Test status
Simulation time 181026414325 ps
CPU time 433.55 seconds
Started Mar 12 12:33:27 PM PDT 24
Finished Mar 12 12:40:41 PM PDT 24
Peak memory 235824 kb
Host smart-d1b46644-3966-494e-8b86-756d97cd44ed
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3789003269 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_
corrupt_sig_fatal_chk.3789003269
Directory /workspace/18.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/18.rom_ctrl_kmac_err_chk.3819741256
Short name T208
Test name
Test status
Simulation time 3340279327 ps
CPU time 28.18 seconds
Started Mar 12 12:33:30 PM PDT 24
Finished Mar 12 12:33:58 PM PDT 24
Peak memory 211080 kb
Host smart-8e7391b5-5ebf-47ba-8e3d-6024ddd8dc43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3819741256 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_kmac_err_chk.3819741256
Directory /workspace/18.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/18.rom_ctrl_max_throughput_chk.3800593205
Short name T40
Test name
Test status
Simulation time 7464746961 ps
CPU time 13.51 seconds
Started Mar 12 12:33:25 PM PDT 24
Finished Mar 12 12:33:39 PM PDT 24
Peak memory 210328 kb
Host smart-a41b86f5-08bb-461d-a367-b107c525cc5f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3800593205 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_max_throughput_chk.3800593205
Directory /workspace/18.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/18.rom_ctrl_smoke.2265536937
Short name T118
Test name
Test status
Simulation time 9726530820 ps
CPU time 26.97 seconds
Started Mar 12 12:33:27 PM PDT 24
Finished Mar 12 12:33:55 PM PDT 24
Peak memory 213436 kb
Host smart-9ea3d268-f4e1-4407-a6a9-fea66d564626
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2265536937 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_smoke.2265536937
Directory /workspace/18.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/18.rom_ctrl_stress_all.856022535
Short name T42
Test name
Test status
Simulation time 1571535600 ps
CPU time 21.16 seconds
Started Mar 12 12:33:25 PM PDT 24
Finished Mar 12 12:33:47 PM PDT 24
Peak memory 215160 kb
Host smart-fda416a0-1825-41ae-95bc-9037f2251ef0
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=856022535 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 18.rom_ctrl_stress_all.856022535
Directory /workspace/18.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/18.rom_ctrl_stress_all_with_rand_reset.130467003
Short name T52
Test name
Test status
Simulation time 16351084814 ps
CPU time 288.65 seconds
Started Mar 12 12:33:46 PM PDT 24
Finished Mar 12 12:38:35 PM PDT 24
Peak memory 220424 kb
Host smart-3a9ab015-0366-494d-b406-e7ce0e8d0d50
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=130467003 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_stress_all_with_rand_reset.130467003
Directory /workspace/18.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/19.rom_ctrl_alert_test.383891335
Short name T279
Test name
Test status
Simulation time 85735632 ps
CPU time 4.29 seconds
Started Mar 12 12:33:25 PM PDT 24
Finished Mar 12 12:33:30 PM PDT 24
Peak memory 210396 kb
Host smart-694fa633-742f-4f39-915f-7911e253ded3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=383891335 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_alert_test.383891335
Directory /workspace/19.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/19.rom_ctrl_corrupt_sig_fatal_chk.2103060566
Short name T28
Test name
Test status
Simulation time 13610763706 ps
CPU time 140.65 seconds
Started Mar 12 12:33:29 PM PDT 24
Finished Mar 12 12:35:50 PM PDT 24
Peak memory 227756 kb
Host smart-d7f8966f-b294-4419-8aa2-bdbddc09991e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2103060566 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_
corrupt_sig_fatal_chk.2103060566
Directory /workspace/19.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/19.rom_ctrl_kmac_err_chk.3601075745
Short name T322
Test name
Test status
Simulation time 14317671298 ps
CPU time 30.23 seconds
Started Mar 12 12:33:26 PM PDT 24
Finished Mar 12 12:33:57 PM PDT 24
Peak memory 211144 kb
Host smart-e9e45a97-0a89-4018-a513-6a29fbb1d784
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3601075745 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_kmac_err_chk.3601075745
Directory /workspace/19.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/19.rom_ctrl_max_throughput_chk.3593094861
Short name T102
Test name
Test status
Simulation time 1351691165 ps
CPU time 12.94 seconds
Started Mar 12 12:33:28 PM PDT 24
Finished Mar 12 12:33:41 PM PDT 24
Peak memory 210252 kb
Host smart-d1c6947f-9ee0-4e0e-a184-88831c858089
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3593094861 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_max_throughput_chk.3593094861
Directory /workspace/19.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/19.rom_ctrl_smoke.747066907
Short name T361
Test name
Test status
Simulation time 1388802883 ps
CPU time 10.17 seconds
Started Mar 12 12:33:30 PM PDT 24
Finished Mar 12 12:33:41 PM PDT 24
Peak memory 212100 kb
Host smart-69b91915-792e-456e-9972-13ad8ec08507
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=747066907 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_smoke.747066907
Directory /workspace/19.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/19.rom_ctrl_stress_all.1275067890
Short name T5
Test name
Test status
Simulation time 7824131566 ps
CPU time 39.12 seconds
Started Mar 12 12:33:29 PM PDT 24
Finished Mar 12 12:34:09 PM PDT 24
Peak memory 213452 kb
Host smart-9968fbb9-52a8-4b92-9a7c-c1200d17e001
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1275067890 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 19.rom_ctrl_stress_all.1275067890
Directory /workspace/19.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/19.rom_ctrl_stress_all_with_rand_reset.2460595849
Short name T16
Test name
Test status
Simulation time 157561469699 ps
CPU time 6133.1 seconds
Started Mar 12 12:33:30 PM PDT 24
Finished Mar 12 02:15:44 PM PDT 24
Peak memory 234992 kb
Host smart-d17b23dc-d22e-4968-ad92-1902eeef2350
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2460595849 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_stress_all_with_rand_reset.2460595849
Directory /workspace/19.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.rom_ctrl_alert_test.2170608985
Short name T291
Test name
Test status
Simulation time 1302404723 ps
CPU time 11.86 seconds
Started Mar 12 12:32:58 PM PDT 24
Finished Mar 12 12:33:10 PM PDT 24
Peak memory 210304 kb
Host smart-ee06ceb1-96ba-430f-848a-0df6385f8f02
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2170608985 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_alert_test.2170608985
Directory /workspace/2.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/2.rom_ctrl_kmac_err_chk.3803862347
Short name T201
Test name
Test status
Simulation time 3934922128 ps
CPU time 16.07 seconds
Started Mar 12 12:32:59 PM PDT 24
Finished Mar 12 12:33:15 PM PDT 24
Peak memory 212144 kb
Host smart-79c0ef66-1628-4cfc-a610-3cfd124ec20e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3803862347 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_kmac_err_chk.3803862347
Directory /workspace/2.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/2.rom_ctrl_max_throughput_chk.2186946365
Short name T332
Test name
Test status
Simulation time 196322813 ps
CPU time 5.85 seconds
Started Mar 12 12:32:57 PM PDT 24
Finished Mar 12 12:33:03 PM PDT 24
Peak memory 210200 kb
Host smart-d7ef70ce-d16b-4106-95dc-3d3561834862
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2186946365 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_max_throughput_chk.2186946365
Directory /workspace/2.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/2.rom_ctrl_sec_cm.3772387897
Short name T30
Test name
Test status
Simulation time 1387910063 ps
CPU time 59.55 seconds
Started Mar 12 12:32:56 PM PDT 24
Finished Mar 12 12:33:56 PM PDT 24
Peak memory 236264 kb
Host smart-26a00e37-06a3-4ac4-8c6b-ed7cb568d621
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3772387897 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_sec_cm.3772387897
Directory /workspace/2.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/2.rom_ctrl_smoke.3667125931
Short name T351
Test name
Test status
Simulation time 2647358798 ps
CPU time 25.14 seconds
Started Mar 12 12:32:57 PM PDT 24
Finished Mar 12 12:33:22 PM PDT 24
Peak memory 212380 kb
Host smart-de28d7a4-c0bf-4e0d-a9c2-caedcf0e0657
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3667125931 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_smoke.3667125931
Directory /workspace/2.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/2.rom_ctrl_stress_all.1861960046
Short name T309
Test name
Test status
Simulation time 21872417599 ps
CPU time 61.26 seconds
Started Mar 12 12:32:57 PM PDT 24
Finished Mar 12 12:33:59 PM PDT 24
Peak memory 218564 kb
Host smart-80092072-2a12-4d67-ba25-c2540ea01abd
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1861960046 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 2.rom_ctrl_stress_all.1861960046
Directory /workspace/2.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/20.rom_ctrl_alert_test.2824356708
Short name T348
Test name
Test status
Simulation time 9283011822 ps
CPU time 16.16 seconds
Started Mar 12 12:33:27 PM PDT 24
Finished Mar 12 12:33:43 PM PDT 24
Peak memory 210388 kb
Host smart-f0503c48-803d-40a3-9d61-465fb9d5dba7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2824356708 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_alert_test.2824356708
Directory /workspace/20.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/20.rom_ctrl_corrupt_sig_fatal_chk.1649473153
Short name T230
Test name
Test status
Simulation time 82896182943 ps
CPU time 250.78 seconds
Started Mar 12 12:33:29 PM PDT 24
Finished Mar 12 12:37:40 PM PDT 24
Peak memory 233300 kb
Host smart-b90ced20-dda2-49bb-83bb-fbc59c378243
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1649473153 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_
corrupt_sig_fatal_chk.1649473153
Directory /workspace/20.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/20.rom_ctrl_kmac_err_chk.2262539278
Short name T136
Test name
Test status
Simulation time 27198661165 ps
CPU time 26.19 seconds
Started Mar 12 12:33:45 PM PDT 24
Finished Mar 12 12:34:12 PM PDT 24
Peak memory 211148 kb
Host smart-9664d4f9-47cd-4439-a3a8-d80330111fa2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2262539278 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_kmac_err_chk.2262539278
Directory /workspace/20.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/20.rom_ctrl_max_throughput_chk.2733130108
Short name T289
Test name
Test status
Simulation time 985406971 ps
CPU time 6.66 seconds
Started Mar 12 12:33:26 PM PDT 24
Finished Mar 12 12:33:33 PM PDT 24
Peak memory 210216 kb
Host smart-2b8a4302-16b2-4067-aaea-9fd70b55a1fe
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2733130108 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_max_throughput_chk.2733130108
Directory /workspace/20.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/20.rom_ctrl_smoke.2534690892
Short name T254
Test name
Test status
Simulation time 714739331 ps
CPU time 9.68 seconds
Started Mar 12 12:33:27 PM PDT 24
Finished Mar 12 12:33:38 PM PDT 24
Peak memory 212352 kb
Host smart-c9b4bc85-e7c3-4e82-86f1-357b879f6e22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2534690892 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_smoke.2534690892
Directory /workspace/20.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/20.rom_ctrl_stress_all.41246266
Short name T8
Test name
Test status
Simulation time 19438618444 ps
CPU time 43.53 seconds
Started Mar 12 12:33:35 PM PDT 24
Finished Mar 12 12:34:18 PM PDT 24
Peak memory 218636 kb
Host smart-9ba260dd-9003-4829-97fd-cdb88629bbde
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41246266 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +U
VM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n
ame 20.rom_ctrl_stress_all.41246266
Directory /workspace/20.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/21.rom_ctrl_alert_test.3029032985
Short name T153
Test name
Test status
Simulation time 3490786323 ps
CPU time 14.09 seconds
Started Mar 12 12:33:39 PM PDT 24
Finished Mar 12 12:33:54 PM PDT 24
Peak memory 210432 kb
Host smart-4be1f56a-19c0-409e-a8c2-9264fa9b493b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3029032985 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_alert_test.3029032985
Directory /workspace/21.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/21.rom_ctrl_corrupt_sig_fatal_chk.3290896776
Short name T177
Test name
Test status
Simulation time 97023707967 ps
CPU time 233.12 seconds
Started Mar 12 12:33:37 PM PDT 24
Finished Mar 12 12:37:30 PM PDT 24
Peak memory 239412 kb
Host smart-af6d7890-3b91-4143-928a-94aa5db8ab26
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3290896776 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_
corrupt_sig_fatal_chk.3290896776
Directory /workspace/21.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/21.rom_ctrl_kmac_err_chk.340955124
Short name T25
Test name
Test status
Simulation time 3335213199 ps
CPU time 29.98 seconds
Started Mar 12 12:33:36 PM PDT 24
Finished Mar 12 12:34:06 PM PDT 24
Peak memory 210964 kb
Host smart-8427cca7-2285-4089-beff-a62a5c669df8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=340955124 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_kmac_err_chk.340955124
Directory /workspace/21.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/21.rom_ctrl_max_throughput_chk.1634848160
Short name T334
Test name
Test status
Simulation time 214511223 ps
CPU time 6.63 seconds
Started Mar 12 12:33:52 PM PDT 24
Finished Mar 12 12:33:59 PM PDT 24
Peak memory 210324 kb
Host smart-1d485a0e-216d-468b-a71d-28c8009295dc
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1634848160 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_max_throughput_chk.1634848160
Directory /workspace/21.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/21.rom_ctrl_smoke.3226256008
Short name T300
Test name
Test status
Simulation time 371219706 ps
CPU time 9.56 seconds
Started Mar 12 12:33:29 PM PDT 24
Finished Mar 12 12:33:39 PM PDT 24
Peak memory 212564 kb
Host smart-89877a8a-0a81-442e-901f-234e1802dcec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3226256008 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_smoke.3226256008
Directory /workspace/21.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/21.rom_ctrl_stress_all.3486843491
Short name T318
Test name
Test status
Simulation time 8360755885 ps
CPU time 80.08 seconds
Started Mar 12 12:33:51 PM PDT 24
Finished Mar 12 12:35:12 PM PDT 24
Peak memory 218664 kb
Host smart-552a9959-3774-4b7b-a011-18b9f0212ec8
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3486843491 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 21.rom_ctrl_stress_all.3486843491
Directory /workspace/21.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/22.rom_ctrl_alert_test.1590148559
Short name T263
Test name
Test status
Simulation time 126325180 ps
CPU time 4.27 seconds
Started Mar 12 12:33:39 PM PDT 24
Finished Mar 12 12:33:44 PM PDT 24
Peak memory 210396 kb
Host smart-301056c3-0b50-4dc6-b739-409f0b6422eb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1590148559 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_alert_test.1590148559
Directory /workspace/22.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/22.rom_ctrl_corrupt_sig_fatal_chk.1932790415
Short name T217
Test name
Test status
Simulation time 2599555336 ps
CPU time 149.16 seconds
Started Mar 12 12:33:39 PM PDT 24
Finished Mar 12 12:36:09 PM PDT 24
Peak memory 236068 kb
Host smart-3a5bc199-8d61-405d-b68d-6de3546e72c2
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1932790415 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_
corrupt_sig_fatal_chk.1932790415
Directory /workspace/22.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/22.rom_ctrl_kmac_err_chk.3186148938
Short name T9
Test name
Test status
Simulation time 756054968 ps
CPU time 9.31 seconds
Started Mar 12 12:33:38 PM PDT 24
Finished Mar 12 12:33:48 PM PDT 24
Peak memory 210796 kb
Host smart-6269f554-0ad0-457c-a148-3a50c3480161
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3186148938 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_kmac_err_chk.3186148938
Directory /workspace/22.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/22.rom_ctrl_max_throughput_chk.235205899
Short name T220
Test name
Test status
Simulation time 1157445369 ps
CPU time 9.06 seconds
Started Mar 12 12:33:33 PM PDT 24
Finished Mar 12 12:33:43 PM PDT 24
Peak memory 210328 kb
Host smart-a4834736-e37f-456f-9256-e519ea3156c2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=235205899 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_max_throughput_chk.235205899
Directory /workspace/22.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/22.rom_ctrl_smoke.727981129
Short name T18
Test name
Test status
Simulation time 22828017884 ps
CPU time 28.68 seconds
Started Mar 12 12:33:38 PM PDT 24
Finished Mar 12 12:34:07 PM PDT 24
Peak memory 213504 kb
Host smart-ddc1d1e5-334c-48db-b39e-7079faa31e7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=727981129 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_smoke.727981129
Directory /workspace/22.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/22.rom_ctrl_stress_all.2445027090
Short name T365
Test name
Test status
Simulation time 1584834113 ps
CPU time 20.31 seconds
Started Mar 12 12:33:38 PM PDT 24
Finished Mar 12 12:33:59 PM PDT 24
Peak memory 210208 kb
Host smart-2822e6ff-7f81-490f-a640-a50730d7baf7
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2445027090 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 22.rom_ctrl_stress_all.2445027090
Directory /workspace/22.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/22.rom_ctrl_stress_all_with_rand_reset.2500622179
Short name T236
Test name
Test status
Simulation time 110642618372 ps
CPU time 1018.22 seconds
Started Mar 12 12:33:35 PM PDT 24
Finished Mar 12 12:50:33 PM PDT 24
Peak memory 233664 kb
Host smart-104e4648-2475-432c-a6d1-ac178b93f427
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2500622179 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_stress_all_with_rand_reset.2500622179
Directory /workspace/22.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/23.rom_ctrl_alert_test.2258669474
Short name T187
Test name
Test status
Simulation time 1989032219 ps
CPU time 10.28 seconds
Started Mar 12 12:33:36 PM PDT 24
Finished Mar 12 12:33:46 PM PDT 24
Peak memory 210392 kb
Host smart-1639ea41-5111-4238-b0de-e9709c91b637
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2258669474 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_alert_test.2258669474
Directory /workspace/23.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/23.rom_ctrl_corrupt_sig_fatal_chk.2625969431
Short name T107
Test name
Test status
Simulation time 88007095617 ps
CPU time 325.28 seconds
Started Mar 12 12:33:33 PM PDT 24
Finished Mar 12 12:38:59 PM PDT 24
Peak memory 236968 kb
Host smart-947a26d3-b09b-4aed-9342-9de1c0dc8ae1
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2625969431 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_
corrupt_sig_fatal_chk.2625969431
Directory /workspace/23.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/23.rom_ctrl_kmac_err_chk.3845451952
Short name T147
Test name
Test status
Simulation time 416862274 ps
CPU time 12.38 seconds
Started Mar 12 12:33:51 PM PDT 24
Finished Mar 12 12:34:03 PM PDT 24
Peak memory 210940 kb
Host smart-36bc49e5-0aea-4bb7-8f63-ab1d04089f9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3845451952 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_kmac_err_chk.3845451952
Directory /workspace/23.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/23.rom_ctrl_max_throughput_chk.2944676261
Short name T141
Test name
Test status
Simulation time 1145051091 ps
CPU time 10.85 seconds
Started Mar 12 12:33:59 PM PDT 24
Finished Mar 12 12:34:10 PM PDT 24
Peak memory 210300 kb
Host smart-95f53ec4-cb23-4708-b5b4-5245765f0ba2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2944676261 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_max_throughput_chk.2944676261
Directory /workspace/23.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/23.rom_ctrl_smoke.1756517542
Short name T169
Test name
Test status
Simulation time 14365525825 ps
CPU time 37.38 seconds
Started Mar 12 12:33:59 PM PDT 24
Finished Mar 12 12:34:36 PM PDT 24
Peak memory 212380 kb
Host smart-11b541c3-08e8-4da6-88b3-e11279989202
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1756517542 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_smoke.1756517542
Directory /workspace/23.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/23.rom_ctrl_stress_all_with_rand_reset.1111126566
Short name T305
Test name
Test status
Simulation time 56091379547 ps
CPU time 2088.61 seconds
Started Mar 12 12:33:39 PM PDT 24
Finished Mar 12 01:08:28 PM PDT 24
Peak memory 243224 kb
Host smart-8b9b10ba-2f26-45c3-a828-3011ba7bd750
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1111126566 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_stress_all_with_rand_reset.1111126566
Directory /workspace/23.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/24.rom_ctrl_alert_test.1347610474
Short name T303
Test name
Test status
Simulation time 1728392355 ps
CPU time 15.05 seconds
Started Mar 12 12:33:46 PM PDT 24
Finished Mar 12 12:34:02 PM PDT 24
Peak memory 210356 kb
Host smart-963f82e0-97ca-4b46-b8bc-d2fe1d05d49b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1347610474 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_alert_test.1347610474
Directory /workspace/24.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/24.rom_ctrl_corrupt_sig_fatal_chk.2549463698
Short name T260
Test name
Test status
Simulation time 61171796443 ps
CPU time 219.96 seconds
Started Mar 12 12:33:47 PM PDT 24
Finished Mar 12 12:37:27 PM PDT 24
Peak memory 236420 kb
Host smart-cbdfe4af-0233-43a5-aaa8-43bbc421e547
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2549463698 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_
corrupt_sig_fatal_chk.2549463698
Directory /workspace/24.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/24.rom_ctrl_kmac_err_chk.3221251651
Short name T21
Test name
Test status
Simulation time 203026387 ps
CPU time 9.42 seconds
Started Mar 12 12:33:50 PM PDT 24
Finished Mar 12 12:34:00 PM PDT 24
Peak memory 210356 kb
Host smart-c89cfb4f-f4b7-4f9d-926f-eb8ed4c73449
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3221251651 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_kmac_err_chk.3221251651
Directory /workspace/24.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/24.rom_ctrl_max_throughput_chk.3835077390
Short name T190
Test name
Test status
Simulation time 1276108752 ps
CPU time 9.13 seconds
Started Mar 12 12:33:35 PM PDT 24
Finished Mar 12 12:33:44 PM PDT 24
Peak memory 210212 kb
Host smart-77587c4f-36a9-4a73-b19c-ce505fe1170a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3835077390 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_max_throughput_chk.3835077390
Directory /workspace/24.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/24.rom_ctrl_smoke.3714240181
Short name T258
Test name
Test status
Simulation time 13118331446 ps
CPU time 22.48 seconds
Started Mar 12 12:33:39 PM PDT 24
Finished Mar 12 12:34:01 PM PDT 24
Peak memory 212876 kb
Host smart-c6220866-614e-4fe7-a0f6-b8df0a76619e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3714240181 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_smoke.3714240181
Directory /workspace/24.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/24.rom_ctrl_stress_all.1230130052
Short name T151
Test name
Test status
Simulation time 17451065563 ps
CPU time 40.76 seconds
Started Mar 12 12:33:45 PM PDT 24
Finished Mar 12 12:34:26 PM PDT 24
Peak memory 218632 kb
Host smart-5155f13d-ee62-4734-8f82-55752c05acf4
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1230130052 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 24.rom_ctrl_stress_all.1230130052
Directory /workspace/24.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/25.rom_ctrl_alert_test.3729795524
Short name T105
Test name
Test status
Simulation time 363285119 ps
CPU time 4.22 seconds
Started Mar 12 12:33:51 PM PDT 24
Finished Mar 12 12:33:56 PM PDT 24
Peak memory 210456 kb
Host smart-86e70f5c-33c2-4ca6-aa94-add6437654a9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3729795524 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_alert_test.3729795524
Directory /workspace/25.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/25.rom_ctrl_corrupt_sig_fatal_chk.1547906367
Short name T197
Test name
Test status
Simulation time 22673077599 ps
CPU time 201.76 seconds
Started Mar 12 12:33:46 PM PDT 24
Finished Mar 12 12:37:08 PM PDT 24
Peak memory 219756 kb
Host smart-ec0ee435-8610-4402-8b80-d9f14e51a519
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1547906367 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_
corrupt_sig_fatal_chk.1547906367
Directory /workspace/25.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/25.rom_ctrl_kmac_err_chk.49794121
Short name T257
Test name
Test status
Simulation time 2072389590 ps
CPU time 9.55 seconds
Started Mar 12 12:33:45 PM PDT 24
Finished Mar 12 12:33:55 PM PDT 24
Peak memory 210992 kb
Host smart-d5a1cd5b-dfa8-4616-8333-a5c6f1635f2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=49794121 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_kmac_err_chk.49794121
Directory /workspace/25.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/25.rom_ctrl_max_throughput_chk.1351884767
Short name T304
Test name
Test status
Simulation time 3206254349 ps
CPU time 9.71 seconds
Started Mar 12 12:33:50 PM PDT 24
Finished Mar 12 12:34:00 PM PDT 24
Peak memory 210300 kb
Host smart-a3de964f-3217-4fa1-b0bd-c5879c80adaf
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1351884767 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_max_throughput_chk.1351884767
Directory /workspace/25.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/25.rom_ctrl_smoke.2673695776
Short name T296
Test name
Test status
Simulation time 3062522272 ps
CPU time 29.61 seconds
Started Mar 12 12:33:44 PM PDT 24
Finished Mar 12 12:34:14 PM PDT 24
Peak memory 211716 kb
Host smart-f82eb256-796e-4e1f-b86b-413b1ceedb40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2673695776 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_smoke.2673695776
Directory /workspace/25.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/25.rom_ctrl_stress_all.1734888717
Short name T352
Test name
Test status
Simulation time 18545713400 ps
CPU time 35.81 seconds
Started Mar 12 12:33:48 PM PDT 24
Finished Mar 12 12:34:24 PM PDT 24
Peak memory 213980 kb
Host smart-b68caa22-a548-4a20-999c-8d976cbd564d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1734888717 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 25.rom_ctrl_stress_all.1734888717
Directory /workspace/25.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/26.rom_ctrl_alert_test.3714428580
Short name T218
Test name
Test status
Simulation time 1831107845 ps
CPU time 14.88 seconds
Started Mar 12 12:33:57 PM PDT 24
Finished Mar 12 12:34:12 PM PDT 24
Peak memory 210428 kb
Host smart-add1650d-06b5-40a9-8e18-6f22cf9097f4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3714428580 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_alert_test.3714428580
Directory /workspace/26.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/26.rom_ctrl_corrupt_sig_fatal_chk.2813211988
Short name T323
Test name
Test status
Simulation time 660697993987 ps
CPU time 429.22 seconds
Started Mar 12 12:33:54 PM PDT 24
Finished Mar 12 12:41:04 PM PDT 24
Peak memory 211736 kb
Host smart-d107be7e-d4de-421d-a3fe-bbcae010a179
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2813211988 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_
corrupt_sig_fatal_chk.2813211988
Directory /workspace/26.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/26.rom_ctrl_kmac_err_chk.753270753
Short name T362
Test name
Test status
Simulation time 3128149054 ps
CPU time 24.36 seconds
Started Mar 12 12:33:54 PM PDT 24
Finished Mar 12 12:34:19 PM PDT 24
Peak memory 210800 kb
Host smart-d1b1e7e6-064b-443d-85e9-5c94694c8553
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=753270753 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_kmac_err_chk.753270753
Directory /workspace/26.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/26.rom_ctrl_max_throughput_chk.2225585328
Short name T44
Test name
Test status
Simulation time 6911556481 ps
CPU time 15.57 seconds
Started Mar 12 12:33:55 PM PDT 24
Finished Mar 12 12:34:11 PM PDT 24
Peak memory 210356 kb
Host smart-2b73445b-16ad-47cd-8ae4-91efb96971e5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2225585328 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_max_throughput_chk.2225585328
Directory /workspace/26.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/26.rom_ctrl_smoke.1837158907
Short name T67
Test name
Test status
Simulation time 13173204173 ps
CPU time 32.5 seconds
Started Mar 12 12:33:46 PM PDT 24
Finished Mar 12 12:34:18 PM PDT 24
Peak memory 212896 kb
Host smart-7d2059b3-8c6b-464b-87a8-445880c63fa1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1837158907 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_smoke.1837158907
Directory /workspace/26.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/26.rom_ctrl_stress_all.1663996092
Short name T347
Test name
Test status
Simulation time 389030164 ps
CPU time 24.62 seconds
Started Mar 12 12:33:46 PM PDT 24
Finished Mar 12 12:34:11 PM PDT 24
Peak memory 213488 kb
Host smart-d137ed82-364d-4ae6-b162-4dc3e6903292
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1663996092 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 26.rom_ctrl_stress_all.1663996092
Directory /workspace/26.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/27.rom_ctrl_alert_test.1434724033
Short name T231
Test name
Test status
Simulation time 752061283 ps
CPU time 4.25 seconds
Started Mar 12 12:33:55 PM PDT 24
Finished Mar 12 12:34:00 PM PDT 24
Peak memory 210372 kb
Host smart-e20cac2c-09a8-4fb0-a098-d7f5d3453e8a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1434724033 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_alert_test.1434724033
Directory /workspace/27.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/27.rom_ctrl_corrupt_sig_fatal_chk.1408047009
Short name T27
Test name
Test status
Simulation time 22663646188 ps
CPU time 133.33 seconds
Started Mar 12 12:33:55 PM PDT 24
Finished Mar 12 12:36:09 PM PDT 24
Peak memory 210972 kb
Host smart-c1db91b1-f2fa-4fbc-88cc-119e4e63a189
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1408047009 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_
corrupt_sig_fatal_chk.1408047009
Directory /workspace/27.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/27.rom_ctrl_kmac_err_chk.4167181470
Short name T340
Test name
Test status
Simulation time 3135191652 ps
CPU time 23.05 seconds
Started Mar 12 12:33:55 PM PDT 24
Finished Mar 12 12:34:19 PM PDT 24
Peak memory 211088 kb
Host smart-6ee6fcb2-532b-4287-a46d-c70029013de3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4167181470 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_kmac_err_chk.4167181470
Directory /workspace/27.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/27.rom_ctrl_max_throughput_chk.3918552664
Short name T349
Test name
Test status
Simulation time 8064403240 ps
CPU time 17.53 seconds
Started Mar 12 12:33:55 PM PDT 24
Finished Mar 12 12:34:14 PM PDT 24
Peak memory 210324 kb
Host smart-e495a10f-362d-43b5-9fde-3f668cc88b2b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3918552664 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_max_throughput_chk.3918552664
Directory /workspace/27.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/27.rom_ctrl_smoke.4082864272
Short name T186
Test name
Test status
Simulation time 4847332448 ps
CPU time 19.9 seconds
Started Mar 12 12:38:11 PM PDT 24
Finished Mar 12 12:38:32 PM PDT 24
Peak memory 212808 kb
Host smart-c324e436-d18e-4b2f-9e70-eb221a5ba2c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4082864272 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_smoke.4082864272
Directory /workspace/27.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/27.rom_ctrl_stress_all.866029627
Short name T86
Test name
Test status
Simulation time 807296548 ps
CPU time 22.28 seconds
Started Mar 12 12:33:53 PM PDT 24
Finished Mar 12 12:34:16 PM PDT 24
Peak memory 212304 kb
Host smart-db042bcf-b993-41ac-9e1d-bdebc5ca3abb
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=866029627 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 27.rom_ctrl_stress_all.866029627
Directory /workspace/27.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/28.rom_ctrl_alert_test.1078561364
Short name T108
Test name
Test status
Simulation time 4496273570 ps
CPU time 11.03 seconds
Started Mar 12 12:33:52 PM PDT 24
Finished Mar 12 12:34:04 PM PDT 24
Peak memory 210464 kb
Host smart-2682bba0-b2a7-43b3-b6a6-c47c9f3a3d45
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1078561364 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_alert_test.1078561364
Directory /workspace/28.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/28.rom_ctrl_corrupt_sig_fatal_chk.3973065241
Short name T48
Test name
Test status
Simulation time 45164123829 ps
CPU time 174 seconds
Started Mar 12 12:33:56 PM PDT 24
Finished Mar 12 12:36:51 PM PDT 24
Peak memory 236384 kb
Host smart-e620b70a-8f03-48dc-9ad0-9c09f8c838ba
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3973065241 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_
corrupt_sig_fatal_chk.3973065241
Directory /workspace/28.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/28.rom_ctrl_kmac_err_chk.3106873371
Short name T343
Test name
Test status
Simulation time 3756145894 ps
CPU time 15.3 seconds
Started Mar 12 12:33:59 PM PDT 24
Finished Mar 12 12:34:14 PM PDT 24
Peak memory 210508 kb
Host smart-1c548d8e-dbeb-47ce-928b-142f9aa99a4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3106873371 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_kmac_err_chk.3106873371
Directory /workspace/28.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/28.rom_ctrl_max_throughput_chk.1589276374
Short name T225
Test name
Test status
Simulation time 800708271 ps
CPU time 10.41 seconds
Started Mar 12 12:34:02 PM PDT 24
Finished Mar 12 12:34:14 PM PDT 24
Peak memory 210084 kb
Host smart-4a7e9184-6141-4510-8cd6-0c4db0eca82a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1589276374 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_max_throughput_chk.1589276374
Directory /workspace/28.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/28.rom_ctrl_smoke.601741109
Short name T338
Test name
Test status
Simulation time 6212657633 ps
CPU time 20.96 seconds
Started Mar 12 12:34:02 PM PDT 24
Finished Mar 12 12:34:24 PM PDT 24
Peak memory 218636 kb
Host smart-32f83f58-4db0-4d93-acb3-48c4cdfa9df2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=601741109 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_smoke.601741109
Directory /workspace/28.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/28.rom_ctrl_stress_all.2066590398
Short name T159
Test name
Test status
Simulation time 14135946731 ps
CPU time 14.72 seconds
Started Mar 12 12:33:55 PM PDT 24
Finished Mar 12 12:34:11 PM PDT 24
Peak memory 210276 kb
Host smart-e61af9e8-835b-4488-9a87-e03a04aae921
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2066590398 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 28.rom_ctrl_stress_all.2066590398
Directory /workspace/28.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/29.rom_ctrl_alert_test.2191365035
Short name T195
Test name
Test status
Simulation time 2127623182 ps
CPU time 15.15 seconds
Started Mar 12 12:33:54 PM PDT 24
Finished Mar 12 12:34:11 PM PDT 24
Peak memory 210444 kb
Host smart-9d683870-60d1-4fb3-8d70-bdb5ba30e710
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2191365035 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_alert_test.2191365035
Directory /workspace/29.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/29.rom_ctrl_corrupt_sig_fatal_chk.4005816156
Short name T20
Test name
Test status
Simulation time 150699323082 ps
CPU time 338.76 seconds
Started Mar 12 12:33:58 PM PDT 24
Finished Mar 12 12:39:37 PM PDT 24
Peak memory 239716 kb
Host smart-cc14ca93-6ea7-49af-ade4-f463f8c09691
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4005816156 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_
corrupt_sig_fatal_chk.4005816156
Directory /workspace/29.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/29.rom_ctrl_kmac_err_chk.2801514682
Short name T164
Test name
Test status
Simulation time 11343942591 ps
CPU time 20.38 seconds
Started Mar 12 12:33:59 PM PDT 24
Finished Mar 12 12:34:20 PM PDT 24
Peak memory 211392 kb
Host smart-ff571fa3-f336-4f98-9d1a-fca5ca63e8dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2801514682 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_kmac_err_chk.2801514682
Directory /workspace/29.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/29.rom_ctrl_max_throughput_chk.1653208646
Short name T6
Test name
Test status
Simulation time 2012893301 ps
CPU time 15.96 seconds
Started Mar 12 12:37:56 PM PDT 24
Finished Mar 12 12:38:12 PM PDT 24
Peak memory 209284 kb
Host smart-d2a8693b-2b99-409d-9e00-72a387e937bd
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1653208646 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_max_throughput_chk.1653208646
Directory /workspace/29.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/29.rom_ctrl_stress_all.675373302
Short name T229
Test name
Test status
Simulation time 52130691976 ps
CPU time 34.03 seconds
Started Mar 12 12:37:55 PM PDT 24
Finished Mar 12 12:38:30 PM PDT 24
Peak memory 217440 kb
Host smart-a1f1c711-53fd-4e74-9d38-bc4dc0884ab1
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=675373302 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 29.rom_ctrl_stress_all.675373302
Directory /workspace/29.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/29.rom_ctrl_stress_all_with_rand_reset.3622761975
Short name T53
Test name
Test status
Simulation time 15866829541 ps
CPU time 4124.82 seconds
Started Mar 12 12:34:02 PM PDT 24
Finished Mar 12 01:42:48 PM PDT 24
Peak memory 224268 kb
Host smart-03e493e3-2616-4a1a-ad18-41058f15cdec
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3622761975 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_stress_all_with_rand_reset.3622761975
Directory /workspace/29.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.rom_ctrl_alert_test.3442680816
Short name T143
Test name
Test status
Simulation time 7678254919 ps
CPU time 13.01 seconds
Started Mar 12 12:33:01 PM PDT 24
Finished Mar 12 12:33:14 PM PDT 24
Peak memory 210432 kb
Host smart-d82bad22-a17d-42a0-a4f9-9326027af33f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3442680816 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_alert_test.3442680816
Directory /workspace/3.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/3.rom_ctrl_corrupt_sig_fatal_chk.2742409441
Short name T47
Test name
Test status
Simulation time 1469687274 ps
CPU time 107.05 seconds
Started Mar 12 12:33:00 PM PDT 24
Finished Mar 12 12:34:47 PM PDT 24
Peak memory 235816 kb
Host smart-58b0ab6b-bbd2-4ee8-9295-f56bb723995d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2742409441 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_c
orrupt_sig_fatal_chk.2742409441
Directory /workspace/3.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/3.rom_ctrl_kmac_err_chk.2326259310
Short name T71
Test name
Test status
Simulation time 7810132023 ps
CPU time 32.99 seconds
Started Mar 12 12:32:55 PM PDT 24
Finished Mar 12 12:33:29 PM PDT 24
Peak memory 211536 kb
Host smart-2ad87ae8-e661-4b70-9ade-d42faed5e10a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2326259310 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_kmac_err_chk.2326259310
Directory /workspace/3.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/3.rom_ctrl_max_throughput_chk.260657484
Short name T313
Test name
Test status
Simulation time 7664136175 ps
CPU time 16.34 seconds
Started Mar 12 12:32:57 PM PDT 24
Finished Mar 12 12:33:13 PM PDT 24
Peak memory 210316 kb
Host smart-7b04e2ba-3677-45a4-9414-de4981ec4f48
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=260657484 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_max_throughput_chk.260657484
Directory /workspace/3.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/3.rom_ctrl_sec_cm.3148388255
Short name T36
Test name
Test status
Simulation time 905249405 ps
CPU time 58.56 seconds
Started Mar 12 12:33:07 PM PDT 24
Finished Mar 12 12:34:05 PM PDT 24
Peak memory 236548 kb
Host smart-40b951d4-2e37-43cc-bef6-92879730ca99
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3148388255 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_sec_cm.3148388255
Directory /workspace/3.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/3.rom_ctrl_smoke.4195052384
Short name T88
Test name
Test status
Simulation time 400377975 ps
CPU time 12.48 seconds
Started Mar 12 12:32:57 PM PDT 24
Finished Mar 12 12:33:10 PM PDT 24
Peak memory 211968 kb
Host smart-ee63597c-acb0-433a-8640-96308cd727c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4195052384 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_smoke.4195052384
Directory /workspace/3.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/3.rom_ctrl_stress_all.3760185862
Short name T176
Test name
Test status
Simulation time 9859540037 ps
CPU time 24.52 seconds
Started Mar 12 12:32:58 PM PDT 24
Finished Mar 12 12:33:23 PM PDT 24
Peak memory 218536 kb
Host smart-dfde58c9-0a4d-4301-89e8-e3f826a1f80d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3760185862 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 3.rom_ctrl_stress_all.3760185862
Directory /workspace/3.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/30.rom_ctrl_alert_test.2225844217
Short name T354
Test name
Test status
Simulation time 426638875 ps
CPU time 6.91 seconds
Started Mar 12 12:34:06 PM PDT 24
Finished Mar 12 12:34:13 PM PDT 24
Peak memory 210384 kb
Host smart-0cbcced0-e56b-41d3-897c-186305efc60e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2225844217 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_alert_test.2225844217
Directory /workspace/30.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/30.rom_ctrl_corrupt_sig_fatal_chk.432073263
Short name T333
Test name
Test status
Simulation time 25422502527 ps
CPU time 245.84 seconds
Started Mar 12 12:34:06 PM PDT 24
Finished Mar 12 12:38:12 PM PDT 24
Peak memory 236152 kb
Host smart-71f933f3-73fe-453e-8eec-a5251b0a9a86
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=432073263 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_c
orrupt_sig_fatal_chk.432073263
Directory /workspace/30.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/30.rom_ctrl_kmac_err_chk.2349395752
Short name T209
Test name
Test status
Simulation time 1522662801 ps
CPU time 11.9 seconds
Started Mar 12 12:34:05 PM PDT 24
Finished Mar 12 12:34:17 PM PDT 24
Peak memory 213052 kb
Host smart-cc987476-5f8c-42c0-af80-fce45c9fa2ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2349395752 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_kmac_err_chk.2349395752
Directory /workspace/30.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/30.rom_ctrl_max_throughput_chk.851840670
Short name T172
Test name
Test status
Simulation time 4016251266 ps
CPU time 16.83 seconds
Started Mar 12 12:34:06 PM PDT 24
Finished Mar 12 12:34:23 PM PDT 24
Peak memory 210328 kb
Host smart-95e9ae9e-1f1f-4794-a365-d263d1c6b0b2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=851840670 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_max_throughput_chk.851840670
Directory /workspace/30.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/30.rom_ctrl_smoke.2622077900
Short name T306
Test name
Test status
Simulation time 6191160080 ps
CPU time 33.26 seconds
Started Mar 12 12:33:55 PM PDT 24
Finished Mar 12 12:34:29 PM PDT 24
Peak memory 218540 kb
Host smart-3515b456-d3e1-408c-b64f-06bdf5bc4bf0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2622077900 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_smoke.2622077900
Directory /workspace/30.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/30.rom_ctrl_stress_all.642772041
Short name T336
Test name
Test status
Simulation time 366485489 ps
CPU time 9.05 seconds
Started Mar 12 12:34:05 PM PDT 24
Finished Mar 12 12:34:15 PM PDT 24
Peak memory 210376 kb
Host smart-d6e5441f-5227-4677-b4a4-b42961848057
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=642772041 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 30.rom_ctrl_stress_all.642772041
Directory /workspace/30.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/31.rom_ctrl_alert_test.2619737702
Short name T103
Test name
Test status
Simulation time 5348171278 ps
CPU time 12.23 seconds
Started Mar 12 12:34:06 PM PDT 24
Finished Mar 12 12:34:19 PM PDT 24
Peak memory 210480 kb
Host smart-3da14c5a-e3c8-40b2-885d-1abcd56bdae7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2619737702 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_alert_test.2619737702
Directory /workspace/31.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/31.rom_ctrl_corrupt_sig_fatal_chk.1098999048
Short name T265
Test name
Test status
Simulation time 31333283198 ps
CPU time 131.29 seconds
Started Mar 12 12:34:04 PM PDT 24
Finished Mar 12 12:36:16 PM PDT 24
Peak memory 227772 kb
Host smart-dcc710f9-47a8-4ea2-9723-a4083147f735
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1098999048 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_
corrupt_sig_fatal_chk.1098999048
Directory /workspace/31.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/31.rom_ctrl_kmac_err_chk.4228693180
Short name T12
Test name
Test status
Simulation time 4446738723 ps
CPU time 15.95 seconds
Started Mar 12 12:34:04 PM PDT 24
Finished Mar 12 12:34:20 PM PDT 24
Peak memory 211220 kb
Host smart-bdaabfd0-957e-4389-b27b-a7e428d815a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4228693180 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_kmac_err_chk.4228693180
Directory /workspace/31.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/31.rom_ctrl_max_throughput_chk.2449416977
Short name T11
Test name
Test status
Simulation time 23759096827 ps
CPU time 15.12 seconds
Started Mar 12 12:34:06 PM PDT 24
Finished Mar 12 12:34:22 PM PDT 24
Peak memory 210300 kb
Host smart-91d29bf2-ec06-42f3-8f45-c08aa87acf84
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2449416977 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_max_throughput_chk.2449416977
Directory /workspace/31.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/31.rom_ctrl_smoke.1811674961
Short name T250
Test name
Test status
Simulation time 507211306 ps
CPU time 10 seconds
Started Mar 12 12:34:04 PM PDT 24
Finished Mar 12 12:34:15 PM PDT 24
Peak memory 212804 kb
Host smart-d66c4584-f371-439e-b7c8-d0fc4b70927d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1811674961 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_smoke.1811674961
Directory /workspace/31.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/31.rom_ctrl_stress_all.1823057741
Short name T171
Test name
Test status
Simulation time 31109972169 ps
CPU time 26.69 seconds
Started Mar 12 12:34:05 PM PDT 24
Finished Mar 12 12:34:32 PM PDT 24
Peak memory 218548 kb
Host smart-3f1bf642-719b-4d99-b104-44f7da5b4cf6
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1823057741 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 31.rom_ctrl_stress_all.1823057741
Directory /workspace/31.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/32.rom_ctrl_alert_test.3284351710
Short name T33
Test name
Test status
Simulation time 2138000985 ps
CPU time 15.86 seconds
Started Mar 12 12:34:19 PM PDT 24
Finished Mar 12 12:34:35 PM PDT 24
Peak memory 210404 kb
Host smart-bef818d6-f5f1-4823-b96d-97edc2f59424
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3284351710 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_alert_test.3284351710
Directory /workspace/32.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/32.rom_ctrl_corrupt_sig_fatal_chk.3999188979
Short name T45
Test name
Test status
Simulation time 87091900668 ps
CPU time 240.38 seconds
Started Mar 12 12:34:06 PM PDT 24
Finished Mar 12 12:38:07 PM PDT 24
Peak memory 212124 kb
Host smart-de5330c6-7447-4cb0-82b1-c6e72a4e6fa3
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3999188979 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_
corrupt_sig_fatal_chk.3999188979
Directory /workspace/32.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/32.rom_ctrl_kmac_err_chk.3773057585
Short name T156
Test name
Test status
Simulation time 4928413375 ps
CPU time 18.21 seconds
Started Mar 12 12:34:05 PM PDT 24
Finished Mar 12 12:34:24 PM PDT 24
Peak memory 211100 kb
Host smart-3d7e0b8e-2371-43ef-9329-2b9dcca635a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3773057585 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_kmac_err_chk.3773057585
Directory /workspace/32.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/32.rom_ctrl_max_throughput_chk.2388180899
Short name T119
Test name
Test status
Simulation time 184572319 ps
CPU time 5.38 seconds
Started Mar 12 12:34:05 PM PDT 24
Finished Mar 12 12:34:11 PM PDT 24
Peak memory 210272 kb
Host smart-5dc8ca51-4b59-4c0d-993f-9f299e55aa62
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2388180899 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_max_throughput_chk.2388180899
Directory /workspace/32.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/32.rom_ctrl_smoke.3224181409
Short name T276
Test name
Test status
Simulation time 1700084255 ps
CPU time 12.88 seconds
Started Mar 12 12:34:07 PM PDT 24
Finished Mar 12 12:34:21 PM PDT 24
Peak memory 211504 kb
Host smart-b3bda716-c893-4490-ac80-3200fdf7ca4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3224181409 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_smoke.3224181409
Directory /workspace/32.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/32.rom_ctrl_stress_all.2557258911
Short name T157
Test name
Test status
Simulation time 6136572735 ps
CPU time 55.33 seconds
Started Mar 12 12:34:06 PM PDT 24
Finished Mar 12 12:35:02 PM PDT 24
Peak memory 218508 kb
Host smart-d483fab9-6d7c-459f-87d8-c0bd000df5ab
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2557258911 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 32.rom_ctrl_stress_all.2557258911
Directory /workspace/32.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/33.rom_ctrl_alert_test.1517134148
Short name T227
Test name
Test status
Simulation time 5489495526 ps
CPU time 7.41 seconds
Started Mar 12 12:34:17 PM PDT 24
Finished Mar 12 12:34:24 PM PDT 24
Peak memory 210520 kb
Host smart-c9176a5a-3d0f-4585-ae06-2091bd789fce
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1517134148 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_alert_test.1517134148
Directory /workspace/33.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/33.rom_ctrl_corrupt_sig_fatal_chk.3724557580
Short name T19
Test name
Test status
Simulation time 20039564225 ps
CPU time 193.35 seconds
Started Mar 12 12:34:18 PM PDT 24
Finished Mar 12 12:37:32 PM PDT 24
Peak memory 233068 kb
Host smart-0fda9afe-3467-43c3-9f0c-7b0a9d1555e2
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3724557580 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_
corrupt_sig_fatal_chk.3724557580
Directory /workspace/33.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/33.rom_ctrl_kmac_err_chk.880909428
Short name T137
Test name
Test status
Simulation time 13672459880 ps
CPU time 30.18 seconds
Started Mar 12 12:34:19 PM PDT 24
Finished Mar 12 12:34:49 PM PDT 24
Peak memory 211196 kb
Host smart-2ca8a7c1-b7f3-4204-9146-e041720d39ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=880909428 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_kmac_err_chk.880909428
Directory /workspace/33.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/33.rom_ctrl_max_throughput_chk.3585985619
Short name T314
Test name
Test status
Simulation time 7656804956 ps
CPU time 11.61 seconds
Started Mar 12 12:34:19 PM PDT 24
Finished Mar 12 12:34:31 PM PDT 24
Peak memory 210336 kb
Host smart-d490747d-aa02-4448-9373-c6f71e032a25
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3585985619 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_max_throughput_chk.3585985619
Directory /workspace/33.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/33.rom_ctrl_smoke.2795143038
Short name T315
Test name
Test status
Simulation time 6105359365 ps
CPU time 35.18 seconds
Started Mar 12 12:34:17 PM PDT 24
Finished Mar 12 12:34:52 PM PDT 24
Peak memory 212476 kb
Host smart-3a4cb72e-330c-4e9a-8a46-12b53e69245c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2795143038 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_smoke.2795143038
Directory /workspace/33.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/33.rom_ctrl_stress_all.3264340164
Short name T280
Test name
Test status
Simulation time 8555973163 ps
CPU time 78.58 seconds
Started Mar 12 12:34:21 PM PDT 24
Finished Mar 12 12:35:40 PM PDT 24
Peak memory 215256 kb
Host smart-0c053ec9-41a5-4ff3-827c-ba547bc183ff
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3264340164 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 33.rom_ctrl_stress_all.3264340164
Directory /workspace/33.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/34.rom_ctrl_alert_test.4286148080
Short name T60
Test name
Test status
Simulation time 6466852324 ps
CPU time 13.62 seconds
Started Mar 12 12:34:19 PM PDT 24
Finished Mar 12 12:34:33 PM PDT 24
Peak memory 210468 kb
Host smart-c367eaa1-f70c-4117-91f1-e959f4409b66
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4286148080 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_alert_test.4286148080
Directory /workspace/34.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/34.rom_ctrl_corrupt_sig_fatal_chk.1568379744
Short name T325
Test name
Test status
Simulation time 4259398338 ps
CPU time 85.63 seconds
Started Mar 12 12:34:20 PM PDT 24
Finished Mar 12 12:35:46 PM PDT 24
Peak memory 239032 kb
Host smart-e63ae596-c334-48ae-ad32-5e5a0d79670d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1568379744 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_
corrupt_sig_fatal_chk.1568379744
Directory /workspace/34.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/34.rom_ctrl_kmac_err_chk.1405238241
Short name T244
Test name
Test status
Simulation time 172318482 ps
CPU time 9.27 seconds
Started Mar 12 12:34:17 PM PDT 24
Finished Mar 12 12:34:26 PM PDT 24
Peak memory 210460 kb
Host smart-7268c185-f0cd-41fa-9ac6-1b4e462bd4d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1405238241 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_kmac_err_chk.1405238241
Directory /workspace/34.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/34.rom_ctrl_max_throughput_chk.3589658118
Short name T277
Test name
Test status
Simulation time 186813796 ps
CPU time 5.26 seconds
Started Mar 12 12:34:17 PM PDT 24
Finished Mar 12 12:34:22 PM PDT 24
Peak memory 210200 kb
Host smart-a1d0afca-8444-43b5-a083-ba8da07e1def
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3589658118 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_max_throughput_chk.3589658118
Directory /workspace/34.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/34.rom_ctrl_smoke.2345521768
Short name T180
Test name
Test status
Simulation time 4616173919 ps
CPU time 13.54 seconds
Started Mar 12 12:34:19 PM PDT 24
Finished Mar 12 12:34:33 PM PDT 24
Peak memory 218600 kb
Host smart-9e626884-b384-4b2a-ae91-d27791c5fc9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2345521768 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_smoke.2345521768
Directory /workspace/34.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/34.rom_ctrl_stress_all.305009895
Short name T39
Test name
Test status
Simulation time 11620708537 ps
CPU time 61.46 seconds
Started Mar 12 12:34:20 PM PDT 24
Finished Mar 12 12:35:22 PM PDT 24
Peak memory 218544 kb
Host smart-d4ce2f10-c15e-4e8e-a5e1-631463e4d92d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=305009895 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 34.rom_ctrl_stress_all.305009895
Directory /workspace/34.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/35.rom_ctrl_alert_test.1662418028
Short name T248
Test name
Test status
Simulation time 1862949598 ps
CPU time 10.06 seconds
Started Mar 12 12:34:17 PM PDT 24
Finished Mar 12 12:34:28 PM PDT 24
Peak memory 210360 kb
Host smart-23803549-56ac-4ff7-a1ad-0700d98c4244
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1662418028 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_alert_test.1662418028
Directory /workspace/35.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/35.rom_ctrl_corrupt_sig_fatal_chk.3173905469
Short name T281
Test name
Test status
Simulation time 98622260541 ps
CPU time 121.58 seconds
Started Mar 12 12:34:18 PM PDT 24
Finished Mar 12 12:36:20 PM PDT 24
Peak memory 236096 kb
Host smart-686e3498-2d77-4476-9a94-1b6225eb1564
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3173905469 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_
corrupt_sig_fatal_chk.3173905469
Directory /workspace/35.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/35.rom_ctrl_kmac_err_chk.2609192964
Short name T262
Test name
Test status
Simulation time 6643566520 ps
CPU time 28.42 seconds
Started Mar 12 12:34:22 PM PDT 24
Finished Mar 12 12:34:50 PM PDT 24
Peak memory 211564 kb
Host smart-9eb5d8c4-e937-4492-adbe-6c0cac68d9cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2609192964 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_kmac_err_chk.2609192964
Directory /workspace/35.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/35.rom_ctrl_max_throughput_chk.2826682314
Short name T181
Test name
Test status
Simulation time 468788187 ps
CPU time 8.25 seconds
Started Mar 12 12:34:19 PM PDT 24
Finished Mar 12 12:34:28 PM PDT 24
Peak memory 210192 kb
Host smart-b536a171-655f-4c36-a0d3-0d9aca0fa38a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2826682314 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_max_throughput_chk.2826682314
Directory /workspace/35.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/35.rom_ctrl_smoke.2866349306
Short name T290
Test name
Test status
Simulation time 1213479390 ps
CPU time 17.82 seconds
Started Mar 12 12:34:17 PM PDT 24
Finished Mar 12 12:34:35 PM PDT 24
Peak memory 211904 kb
Host smart-54838ffb-17f9-429f-a281-3cf0cb168e15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2866349306 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_smoke.2866349306
Directory /workspace/35.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/35.rom_ctrl_stress_all.3360140053
Short name T70
Test name
Test status
Simulation time 4463974714 ps
CPU time 15.48 seconds
Started Mar 12 12:34:15 PM PDT 24
Finished Mar 12 12:34:31 PM PDT 24
Peak memory 210328 kb
Host smart-058116f2-8cb6-4af1-9c1e-772ad02bd05a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3360140053 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 35.rom_ctrl_stress_all.3360140053
Directory /workspace/35.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/35.rom_ctrl_stress_all_with_rand_reset.3828333320
Short name T56
Test name
Test status
Simulation time 29598567707 ps
CPU time 1208.56 seconds
Started Mar 12 12:34:20 PM PDT 24
Finished Mar 12 12:54:29 PM PDT 24
Peak memory 226984 kb
Host smart-8d1ca316-58e5-4ec1-9326-ffc7df00188a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3828333320 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_stress_all_with_rand_reset.3828333320
Directory /workspace/35.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.rom_ctrl_alert_test.4173233929
Short name T191
Test name
Test status
Simulation time 2715064571 ps
CPU time 15.73 seconds
Started Mar 12 12:34:17 PM PDT 24
Finished Mar 12 12:34:33 PM PDT 24
Peak memory 210452 kb
Host smart-1a463888-189d-4318-9fcd-c7a00ff42e12
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4173233929 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_alert_test.4173233929
Directory /workspace/36.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/36.rom_ctrl_corrupt_sig_fatal_chk.4286240227
Short name T29
Test name
Test status
Simulation time 3013320905 ps
CPU time 93.75 seconds
Started Mar 12 12:34:18 PM PDT 24
Finished Mar 12 12:35:52 PM PDT 24
Peak memory 235892 kb
Host smart-4001e6ff-235c-40f0-a71c-9d89d2dffeb4
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4286240227 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_
corrupt_sig_fatal_chk.4286240227
Directory /workspace/36.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/36.rom_ctrl_kmac_err_chk.1130329591
Short name T330
Test name
Test status
Simulation time 2851976338 ps
CPU time 25.9 seconds
Started Mar 12 12:34:16 PM PDT 24
Finished Mar 12 12:34:42 PM PDT 24
Peak memory 210956 kb
Host smart-c37aa3c2-3be7-47b3-998c-0f53182e473e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1130329591 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_kmac_err_chk.1130329591
Directory /workspace/36.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/36.rom_ctrl_max_throughput_chk.1226213998
Short name T145
Test name
Test status
Simulation time 603776264 ps
CPU time 5.25 seconds
Started Mar 12 12:34:16 PM PDT 24
Finished Mar 12 12:34:21 PM PDT 24
Peak memory 210324 kb
Host smart-11b4bc1c-8485-4713-ba1b-b799cf55bccd
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1226213998 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_max_throughput_chk.1226213998
Directory /workspace/36.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/36.rom_ctrl_smoke.3807733885
Short name T158
Test name
Test status
Simulation time 189519580 ps
CPU time 10.12 seconds
Started Mar 12 12:34:17 PM PDT 24
Finished Mar 12 12:34:27 PM PDT 24
Peak memory 212032 kb
Host smart-0472c4b0-f016-4c12-a84d-aefeb59e4463
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3807733885 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_smoke.3807733885
Directory /workspace/36.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/36.rom_ctrl_stress_all.3845298995
Short name T83
Test name
Test status
Simulation time 24602525898 ps
CPU time 51.64 seconds
Started Mar 12 12:34:18 PM PDT 24
Finished Mar 12 12:35:10 PM PDT 24
Peak memory 213312 kb
Host smart-4da845dc-1f82-44a8-a6c8-07d0ca114559
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3845298995 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 36.rom_ctrl_stress_all.3845298995
Directory /workspace/36.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/37.rom_ctrl_alert_test.4007614146
Short name T284
Test name
Test status
Simulation time 3439410647 ps
CPU time 9.84 seconds
Started Mar 12 12:34:18 PM PDT 24
Finished Mar 12 12:34:28 PM PDT 24
Peak memory 210396 kb
Host smart-ad8b7133-9668-456d-bde2-48129700b531
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4007614146 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_alert_test.4007614146
Directory /workspace/37.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/37.rom_ctrl_corrupt_sig_fatal_chk.4076847658
Short name T286
Test name
Test status
Simulation time 4148013045 ps
CPU time 134.86 seconds
Started Mar 12 12:34:18 PM PDT 24
Finished Mar 12 12:36:33 PM PDT 24
Peak memory 227368 kb
Host smart-7b22dea9-0177-4d74-9d8d-13600f7785c6
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4076847658 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_
corrupt_sig_fatal_chk.4076847658
Directory /workspace/37.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/37.rom_ctrl_kmac_err_chk.2649182710
Short name T175
Test name
Test status
Simulation time 6420185004 ps
CPU time 28.85 seconds
Started Mar 12 12:34:20 PM PDT 24
Finished Mar 12 12:34:49 PM PDT 24
Peak memory 211376 kb
Host smart-c2d24391-4a92-4877-8f8a-05078461e66d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2649182710 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_kmac_err_chk.2649182710
Directory /workspace/37.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/37.rom_ctrl_max_throughput_chk.2437405186
Short name T165
Test name
Test status
Simulation time 7939906299 ps
CPU time 16.44 seconds
Started Mar 12 12:34:16 PM PDT 24
Finished Mar 12 12:34:32 PM PDT 24
Peak memory 210388 kb
Host smart-8e4306d0-c5ca-4322-8f8d-26f19c0cda27
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2437405186 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_max_throughput_chk.2437405186
Directory /workspace/37.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/37.rom_ctrl_smoke.3382766288
Short name T283
Test name
Test status
Simulation time 29771162335 ps
CPU time 33.33 seconds
Started Mar 12 12:34:18 PM PDT 24
Finished Mar 12 12:34:51 PM PDT 24
Peak memory 212480 kb
Host smart-e4f5e3cb-9d06-4848-9eab-fd320afa1f65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3382766288 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_smoke.3382766288
Directory /workspace/37.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/37.rom_ctrl_stress_all.3110972708
Short name T104
Test name
Test status
Simulation time 8673645003 ps
CPU time 20.81 seconds
Started Mar 12 12:34:17 PM PDT 24
Finished Mar 12 12:34:38 PM PDT 24
Peak memory 210476 kb
Host smart-c9608fe5-e8ea-4c83-9e92-a5959edbbaad
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3110972708 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 37.rom_ctrl_stress_all.3110972708
Directory /workspace/37.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/38.rom_ctrl_alert_test.1572676157
Short name T3
Test name
Test status
Simulation time 744727563 ps
CPU time 8.64 seconds
Started Mar 12 12:34:17 PM PDT 24
Finished Mar 12 12:34:26 PM PDT 24
Peak memory 210440 kb
Host smart-36275365-e0cb-472e-8fb0-0ed6abe7c27b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1572676157 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_alert_test.1572676157
Directory /workspace/38.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/38.rom_ctrl_corrupt_sig_fatal_chk.4209608809
Short name T233
Test name
Test status
Simulation time 6914853924 ps
CPU time 126.39 seconds
Started Mar 12 12:34:20 PM PDT 24
Finished Mar 12 12:36:27 PM PDT 24
Peak memory 237112 kb
Host smart-9a082c4d-c265-4bf3-a5ee-85e94794a550
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4209608809 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_
corrupt_sig_fatal_chk.4209608809
Directory /workspace/38.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/38.rom_ctrl_kmac_err_chk.1307729136
Short name T243
Test name
Test status
Simulation time 13479023129 ps
CPU time 30.06 seconds
Started Mar 12 12:34:21 PM PDT 24
Finished Mar 12 12:34:51 PM PDT 24
Peak memory 211124 kb
Host smart-15148fec-07b6-4412-a447-b5d0afdf7984
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1307729136 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_kmac_err_chk.1307729136
Directory /workspace/38.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/38.rom_ctrl_max_throughput_chk.3763849688
Short name T138
Test name
Test status
Simulation time 1897271945 ps
CPU time 15.93 seconds
Started Mar 12 12:34:20 PM PDT 24
Finished Mar 12 12:34:36 PM PDT 24
Peak memory 210300 kb
Host smart-c654c6bb-45b7-4438-a57b-c798517c2f37
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3763849688 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_max_throughput_chk.3763849688
Directory /workspace/38.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/38.rom_ctrl_smoke.613282948
Short name T224
Test name
Test status
Simulation time 7211250559 ps
CPU time 20.73 seconds
Started Mar 12 12:34:18 PM PDT 24
Finished Mar 12 12:34:39 PM PDT 24
Peak memory 218568 kb
Host smart-c49af808-3662-411e-a948-a63eb8b06178
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=613282948 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_smoke.613282948
Directory /workspace/38.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/38.rom_ctrl_stress_all.2765922636
Short name T278
Test name
Test status
Simulation time 912517526 ps
CPU time 12.64 seconds
Started Mar 12 12:34:18 PM PDT 24
Finished Mar 12 12:34:30 PM PDT 24
Peak memory 212580 kb
Host smart-c706b094-ec30-474f-82a2-a7df2ab27616
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2765922636 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 38.rom_ctrl_stress_all.2765922636
Directory /workspace/38.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/39.rom_ctrl_alert_test.3110998487
Short name T324
Test name
Test status
Simulation time 9443421803 ps
CPU time 12.19 seconds
Started Mar 12 12:34:18 PM PDT 24
Finished Mar 12 12:34:31 PM PDT 24
Peak memory 210388 kb
Host smart-01f5bbe0-f135-41f9-8651-a0be902997a6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3110998487 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_alert_test.3110998487
Directory /workspace/39.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/39.rom_ctrl_corrupt_sig_fatal_chk.3555951115
Short name T331
Test name
Test status
Simulation time 54918078266 ps
CPU time 149.61 seconds
Started Mar 12 12:34:20 PM PDT 24
Finished Mar 12 12:36:50 PM PDT 24
Peak memory 233480 kb
Host smart-8e7b6126-3213-45a9-8e61-e90d61ff6269
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3555951115 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_
corrupt_sig_fatal_chk.3555951115
Directory /workspace/39.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/39.rom_ctrl_kmac_err_chk.136549071
Short name T346
Test name
Test status
Simulation time 2611571356 ps
CPU time 25.38 seconds
Started Mar 12 12:34:22 PM PDT 24
Finished Mar 12 12:34:47 PM PDT 24
Peak memory 210824 kb
Host smart-dfad1345-a972-4056-92a1-3d7c8891b840
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=136549071 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_kmac_err_chk.136549071
Directory /workspace/39.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/39.rom_ctrl_max_throughput_chk.4076118904
Short name T49
Test name
Test status
Simulation time 410149023 ps
CPU time 5.62 seconds
Started Mar 12 12:34:19 PM PDT 24
Finished Mar 12 12:34:25 PM PDT 24
Peak memory 210308 kb
Host smart-9f261970-a198-4a12-a6b5-98f02cac9c35
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4076118904 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_max_throughput_chk.4076118904
Directory /workspace/39.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/39.rom_ctrl_smoke.949384810
Short name T72
Test name
Test status
Simulation time 3538501559 ps
CPU time 29.2 seconds
Started Mar 12 12:34:19 PM PDT 24
Finished Mar 12 12:34:48 PM PDT 24
Peak memory 211816 kb
Host smart-ab7f1738-36a3-4e76-aa2e-eb4db167c2c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=949384810 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_smoke.949384810
Directory /workspace/39.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/39.rom_ctrl_stress_all.322453089
Short name T188
Test name
Test status
Simulation time 12065361049 ps
CPU time 56.76 seconds
Started Mar 12 12:34:20 PM PDT 24
Finished Mar 12 12:35:17 PM PDT 24
Peak memory 213352 kb
Host smart-b11b0267-bdba-46b4-ae0a-5ff5c556a568
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=322453089 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 39.rom_ctrl_stress_all.322453089
Directory /workspace/39.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/4.rom_ctrl_alert_test.2769906207
Short name T57
Test name
Test status
Simulation time 3290728988 ps
CPU time 14.52 seconds
Started Mar 12 12:33:06 PM PDT 24
Finished Mar 12 12:33:20 PM PDT 24
Peak memory 210476 kb
Host smart-3c7479c7-7f0d-4fe1-a415-63396f0df63d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2769906207 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_alert_test.2769906207
Directory /workspace/4.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/4.rom_ctrl_corrupt_sig_fatal_chk.2255628710
Short name T321
Test name
Test status
Simulation time 156715536062 ps
CPU time 137.79 seconds
Started Mar 12 12:32:56 PM PDT 24
Finished Mar 12 12:35:15 PM PDT 24
Peak memory 236956 kb
Host smart-4cd8a3fe-c7e3-403a-82ac-90d226df0e32
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2255628710 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_c
orrupt_sig_fatal_chk.2255628710
Directory /workspace/4.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/4.rom_ctrl_kmac_err_chk.3589789907
Short name T353
Test name
Test status
Simulation time 43297186115 ps
CPU time 28.46 seconds
Started Mar 12 12:33:02 PM PDT 24
Finished Mar 12 12:33:31 PM PDT 24
Peak memory 211116 kb
Host smart-287af3e9-3dc8-4c1e-808e-3505d1ea8058
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3589789907 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_kmac_err_chk.3589789907
Directory /workspace/4.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/4.rom_ctrl_max_throughput_chk.2968377508
Short name T221
Test name
Test status
Simulation time 4294495637 ps
CPU time 12.15 seconds
Started Mar 12 12:33:00 PM PDT 24
Finished Mar 12 12:33:12 PM PDT 24
Peak memory 210300 kb
Host smart-2b737f23-a1ff-4869-800f-2f2d9a3d4627
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2968377508 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_max_throughput_chk.2968377508
Directory /workspace/4.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/4.rom_ctrl_sec_cm.4229576724
Short name T23
Test name
Test status
Simulation time 2787943412 ps
CPU time 58.95 seconds
Started Mar 12 12:32:56 PM PDT 24
Finished Mar 12 12:33:55 PM PDT 24
Peak memory 237064 kb
Host smart-f074c145-680e-4783-a39c-43b00b481d13
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4229576724 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_sec_cm.4229576724
Directory /workspace/4.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/4.rom_ctrl_smoke.1843229432
Short name T182
Test name
Test status
Simulation time 9285107688 ps
CPU time 31.31 seconds
Started Mar 12 12:32:57 PM PDT 24
Finished Mar 12 12:33:28 PM PDT 24
Peak memory 213284 kb
Host smart-5ee9878f-7eee-49d5-8270-10d4eb0c264d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1843229432 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_smoke.1843229432
Directory /workspace/4.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/4.rom_ctrl_stress_all.1415273599
Short name T85
Test name
Test status
Simulation time 394850263 ps
CPU time 22.53 seconds
Started Mar 12 12:33:00 PM PDT 24
Finished Mar 12 12:33:23 PM PDT 24
Peak memory 215612 kb
Host smart-f79ca9e2-a6d2-4b56-b5b9-ca456a53ec19
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1415273599 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 4.rom_ctrl_stress_all.1415273599
Directory /workspace/4.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/40.rom_ctrl_alert_test.2764119142
Short name T206
Test name
Test status
Simulation time 1279784107 ps
CPU time 8.3 seconds
Started Mar 12 12:34:32 PM PDT 24
Finished Mar 12 12:34:41 PM PDT 24
Peak memory 210392 kb
Host smart-2690fb5c-cc48-480b-b74f-9333dc9ace64
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2764119142 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_alert_test.2764119142
Directory /workspace/40.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/40.rom_ctrl_corrupt_sig_fatal_chk.1742188982
Short name T184
Test name
Test status
Simulation time 78409581387 ps
CPU time 237.76 seconds
Started Mar 12 12:38:11 PM PDT 24
Finished Mar 12 12:42:08 PM PDT 24
Peak memory 235900 kb
Host smart-61ad7e10-c155-4b1f-b36d-c73e76fa0be0
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1742188982 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_
corrupt_sig_fatal_chk.1742188982
Directory /workspace/40.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/40.rom_ctrl_kmac_err_chk.2172407233
Short name T161
Test name
Test status
Simulation time 834714331 ps
CPU time 9.25 seconds
Started Mar 12 12:34:27 PM PDT 24
Finished Mar 12 12:34:37 PM PDT 24
Peak memory 211648 kb
Host smart-b948d6eb-0b95-4582-914e-1ba5375319b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2172407233 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_kmac_err_chk.2172407233
Directory /workspace/40.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/40.rom_ctrl_max_throughput_chk.3233581157
Short name T41
Test name
Test status
Simulation time 3004608046 ps
CPU time 13.72 seconds
Started Mar 12 12:34:32 PM PDT 24
Finished Mar 12 12:34:45 PM PDT 24
Peak memory 210388 kb
Host smart-af065f64-0619-4901-9a8e-0bb3226a4d00
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3233581157 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_max_throughput_chk.3233581157
Directory /workspace/40.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/40.rom_ctrl_smoke.3351265372
Short name T210
Test name
Test status
Simulation time 7000708282 ps
CPU time 21.63 seconds
Started Mar 12 12:34:16 PM PDT 24
Finished Mar 12 12:34:38 PM PDT 24
Peak memory 212116 kb
Host smart-49a3118e-2545-4793-b021-0fbb4ee9ced5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3351265372 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_smoke.3351265372
Directory /workspace/40.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/40.rom_ctrl_stress_all.4099553340
Short name T266
Test name
Test status
Simulation time 38577305842 ps
CPU time 38.81 seconds
Started Mar 12 12:34:24 PM PDT 24
Finished Mar 12 12:35:03 PM PDT 24
Peak memory 214204 kb
Host smart-14b23be9-2949-4634-a098-674450c6e5a9
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4099553340 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 40.rom_ctrl_stress_all.4099553340
Directory /workspace/40.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/41.rom_ctrl_alert_test.3941021789
Short name T211
Test name
Test status
Simulation time 14543231178 ps
CPU time 14.35 seconds
Started Mar 12 12:34:28 PM PDT 24
Finished Mar 12 12:34:42 PM PDT 24
Peak memory 210464 kb
Host smart-4e348a3f-8ef4-4b97-9f8e-a5637f0e0ae9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3941021789 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_alert_test.3941021789
Directory /workspace/41.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/41.rom_ctrl_corrupt_sig_fatal_chk.2319586187
Short name T179
Test name
Test status
Simulation time 96594262371 ps
CPU time 122.35 seconds
Started Mar 12 12:34:26 PM PDT 24
Finished Mar 12 12:36:28 PM PDT 24
Peak memory 234756 kb
Host smart-4a035b09-2cb8-426e-a3bd-6ec96a46e609
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2319586187 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_
corrupt_sig_fatal_chk.2319586187
Directory /workspace/41.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/41.rom_ctrl_kmac_err_chk.2464299377
Short name T43
Test name
Test status
Simulation time 2071166404 ps
CPU time 9.53 seconds
Started Mar 12 12:34:27 PM PDT 24
Finished Mar 12 12:34:37 PM PDT 24
Peak memory 210732 kb
Host smart-6e9a015c-2e58-4d79-afe5-540cf7170cae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2464299377 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_kmac_err_chk.2464299377
Directory /workspace/41.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/41.rom_ctrl_max_throughput_chk.3384205501
Short name T319
Test name
Test status
Simulation time 100693889 ps
CPU time 5.78 seconds
Started Mar 12 12:34:24 PM PDT 24
Finished Mar 12 12:34:30 PM PDT 24
Peak memory 210340 kb
Host smart-14e0e5e8-c94d-4f0b-9404-a6c9c8bf1689
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3384205501 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_max_throughput_chk.3384205501
Directory /workspace/41.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/41.rom_ctrl_smoke.79973687
Short name T271
Test name
Test status
Simulation time 9184625863 ps
CPU time 23.59 seconds
Started Mar 12 12:34:23 PM PDT 24
Finished Mar 12 12:34:47 PM PDT 24
Peak memory 213084 kb
Host smart-94fb23b9-8aab-4365-b218-815dfb3cfcb0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=79973687 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_smoke.79973687
Directory /workspace/41.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/41.rom_ctrl_stress_all.3004529534
Short name T269
Test name
Test status
Simulation time 28293834503 ps
CPU time 58.13 seconds
Started Mar 12 12:34:24 PM PDT 24
Finished Mar 12 12:35:23 PM PDT 24
Peak memory 218640 kb
Host smart-7d5b9254-217b-4a3a-86c4-9dbaea55684c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3004529534 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 41.rom_ctrl_stress_all.3004529534
Directory /workspace/41.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/42.rom_ctrl_alert_test.2386425849
Short name T357
Test name
Test status
Simulation time 175352408 ps
CPU time 5.44 seconds
Started Mar 12 12:34:27 PM PDT 24
Finished Mar 12 12:34:33 PM PDT 24
Peak memory 210424 kb
Host smart-34e40c64-84a2-4f6f-aecc-9421ee179e8b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2386425849 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_alert_test.2386425849
Directory /workspace/42.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/42.rom_ctrl_corrupt_sig_fatal_chk.504470514
Short name T207
Test name
Test status
Simulation time 12131683201 ps
CPU time 106.88 seconds
Started Mar 12 12:34:27 PM PDT 24
Finished Mar 12 12:36:14 PM PDT 24
Peak memory 231228 kb
Host smart-e3a25866-29ff-4fe3-a441-f7024439c5c7
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=504470514 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_c
orrupt_sig_fatal_chk.504470514
Directory /workspace/42.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/42.rom_ctrl_kmac_err_chk.730761595
Short name T240
Test name
Test status
Simulation time 7455187902 ps
CPU time 21.24 seconds
Started Mar 12 12:34:28 PM PDT 24
Finished Mar 12 12:34:49 PM PDT 24
Peak memory 211192 kb
Host smart-90ab3baa-4b9b-456e-ba94-2a79fc27bfc5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=730761595 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_kmac_err_chk.730761595
Directory /workspace/42.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/42.rom_ctrl_max_throughput_chk.1678648154
Short name T345
Test name
Test status
Simulation time 2108300234 ps
CPU time 17.72 seconds
Started Mar 12 12:34:28 PM PDT 24
Finished Mar 12 12:34:46 PM PDT 24
Peak memory 210268 kb
Host smart-db3fab45-d352-4211-8ba4-92c49580253e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1678648154 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_max_throughput_chk.1678648154
Directory /workspace/42.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/42.rom_ctrl_smoke.1943825895
Short name T189
Test name
Test status
Simulation time 3441435922 ps
CPU time 20.25 seconds
Started Mar 12 12:34:24 PM PDT 24
Finished Mar 12 12:34:45 PM PDT 24
Peak memory 211060 kb
Host smart-eb870233-aa77-4f7c-8eb4-3302b48d10a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1943825895 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_smoke.1943825895
Directory /workspace/42.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/42.rom_ctrl_stress_all.38445361
Short name T301
Test name
Test status
Simulation time 398761620 ps
CPU time 21.59 seconds
Started Mar 12 12:34:23 PM PDT 24
Finished Mar 12 12:34:45 PM PDT 24
Peak memory 215312 kb
Host smart-69690291-2b01-47f8-8508-80fe0f1fcf17
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38445361 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +U
VM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n
ame 42.rom_ctrl_stress_all.38445361
Directory /workspace/42.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/43.rom_ctrl_alert_test.1232136320
Short name T144
Test name
Test status
Simulation time 31924659054 ps
CPU time 14.32 seconds
Started Mar 12 12:34:26 PM PDT 24
Finished Mar 12 12:34:41 PM PDT 24
Peak memory 210380 kb
Host smart-38b74543-f7ef-4b47-9de1-4cffce81f7f1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1232136320 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_alert_test.1232136320
Directory /workspace/43.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/43.rom_ctrl_corrupt_sig_fatal_chk.3341856139
Short name T163
Test name
Test status
Simulation time 2158533937 ps
CPU time 109.38 seconds
Started Mar 12 12:34:32 PM PDT 24
Finished Mar 12 12:36:22 PM PDT 24
Peak memory 228588 kb
Host smart-ecda8762-8a4a-4881-9293-0fee761302e8
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3341856139 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_
corrupt_sig_fatal_chk.3341856139
Directory /workspace/43.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/43.rom_ctrl_kmac_err_chk.648306207
Short name T170
Test name
Test status
Simulation time 2390274889 ps
CPU time 13.26 seconds
Started Mar 12 12:34:26 PM PDT 24
Finished Mar 12 12:34:40 PM PDT 24
Peak memory 210952 kb
Host smart-03fd2afb-a2ba-4d80-bb23-825028127eb2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=648306207 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_kmac_err_chk.648306207
Directory /workspace/43.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/43.rom_ctrl_max_throughput_chk.2946356071
Short name T275
Test name
Test status
Simulation time 1179770731 ps
CPU time 11.93 seconds
Started Mar 12 12:34:28 PM PDT 24
Finished Mar 12 12:34:40 PM PDT 24
Peak memory 210256 kb
Host smart-7b6b5210-37e0-4e00-ab20-afe21ccc1735
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2946356071 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_max_throughput_chk.2946356071
Directory /workspace/43.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/43.rom_ctrl_smoke.4256858208
Short name T299
Test name
Test status
Simulation time 11190783985 ps
CPU time 21.52 seconds
Started Mar 12 12:34:27 PM PDT 24
Finished Mar 12 12:34:48 PM PDT 24
Peak memory 212948 kb
Host smart-c9d6afe6-9b79-42da-9c2d-e557372c270a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4256858208 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_smoke.4256858208
Directory /workspace/43.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/43.rom_ctrl_stress_all.2915935719
Short name T298
Test name
Test status
Simulation time 1130992286 ps
CPU time 14.13 seconds
Started Mar 12 12:34:25 PM PDT 24
Finished Mar 12 12:34:39 PM PDT 24
Peak memory 212372 kb
Host smart-d2cd9d20-fa76-4a7d-9d2d-38999e45e462
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2915935719 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 43.rom_ctrl_stress_all.2915935719
Directory /workspace/43.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/43.rom_ctrl_stress_all_with_rand_reset.17324260
Short name T15
Test name
Test status
Simulation time 50172559042 ps
CPU time 1840.07 seconds
Started Mar 12 12:34:26 PM PDT 24
Finished Mar 12 01:05:06 PM PDT 24
Peak memory 234828 kb
Host smart-d8f25131-4b65-43f2-88d7-317c449fc883
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17324260 -assert nopos
tproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_stress_all_with_rand_reset.17324260
Directory /workspace/43.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.rom_ctrl_alert_test.2067160480
Short name T261
Test name
Test status
Simulation time 1044399464 ps
CPU time 10.85 seconds
Started Mar 12 12:34:26 PM PDT 24
Finished Mar 12 12:34:37 PM PDT 24
Peak memory 210388 kb
Host smart-c3d13315-5024-4b0f-a5e3-ca29f47dd4dc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2067160480 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_alert_test.2067160480
Directory /workspace/44.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/44.rom_ctrl_corrupt_sig_fatal_chk.3693979287
Short name T285
Test name
Test status
Simulation time 6825913611 ps
CPU time 95.73 seconds
Started Mar 12 12:34:26 PM PDT 24
Finished Mar 12 12:36:02 PM PDT 24
Peak memory 227792 kb
Host smart-d8481936-e30a-44ec-bf87-3ab5bba679cf
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3693979287 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_
corrupt_sig_fatal_chk.3693979287
Directory /workspace/44.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/44.rom_ctrl_kmac_err_chk.3058737741
Short name T341
Test name
Test status
Simulation time 3630139709 ps
CPU time 29.29 seconds
Started Mar 12 12:34:26 PM PDT 24
Finished Mar 12 12:34:55 PM PDT 24
Peak memory 210876 kb
Host smart-d2bc3047-43d0-4557-b61f-138a93194456
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3058737741 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_kmac_err_chk.3058737741
Directory /workspace/44.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/44.rom_ctrl_max_throughput_chk.3510281754
Short name T337
Test name
Test status
Simulation time 1169835470 ps
CPU time 12.15 seconds
Started Mar 12 12:34:26 PM PDT 24
Finished Mar 12 12:34:38 PM PDT 24
Peak memory 210276 kb
Host smart-377dda44-bb90-418a-8c32-333eecae9086
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3510281754 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_max_throughput_chk.3510281754
Directory /workspace/44.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/44.rom_ctrl_smoke.1284761428
Short name T317
Test name
Test status
Simulation time 77724103101 ps
CPU time 38.69 seconds
Started Mar 12 12:34:32 PM PDT 24
Finished Mar 12 12:35:11 PM PDT 24
Peak memory 211532 kb
Host smart-09a3d72f-bb52-4f52-91f7-7323a6327e49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1284761428 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_smoke.1284761428
Directory /workspace/44.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/44.rom_ctrl_stress_all.697666903
Short name T235
Test name
Test status
Simulation time 9278806219 ps
CPU time 65.63 seconds
Started Mar 12 12:34:24 PM PDT 24
Finished Mar 12 12:35:30 PM PDT 24
Peak memory 212976 kb
Host smart-ad7d15df-d29f-4299-9c51-f3553c37f554
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=697666903 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 44.rom_ctrl_stress_all.697666903
Directory /workspace/44.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/45.rom_ctrl_alert_test.3957736822
Short name T38
Test name
Test status
Simulation time 10460000319 ps
CPU time 14.07 seconds
Started Mar 12 12:34:25 PM PDT 24
Finished Mar 12 12:34:40 PM PDT 24
Peak memory 210488 kb
Host smart-187d2746-3242-4d86-beed-01688b01b5dd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3957736822 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_alert_test.3957736822
Directory /workspace/45.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/45.rom_ctrl_corrupt_sig_fatal_chk.766285075
Short name T328
Test name
Test status
Simulation time 18151129961 ps
CPU time 218.8 seconds
Started Mar 12 12:34:27 PM PDT 24
Finished Mar 12 12:38:06 PM PDT 24
Peak memory 239584 kb
Host smart-7a67ed9e-37d7-4dd3-9211-8a208d5819c8
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=766285075 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_c
orrupt_sig_fatal_chk.766285075
Directory /workspace/45.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/45.rom_ctrl_kmac_err_chk.4045809557
Short name T358
Test name
Test status
Simulation time 2450494573 ps
CPU time 23.83 seconds
Started Mar 12 12:34:25 PM PDT 24
Finished Mar 12 12:34:49 PM PDT 24
Peak memory 212768 kb
Host smart-76bc712c-48bd-4e08-8ab9-5db42c354e0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4045809557 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_kmac_err_chk.4045809557
Directory /workspace/45.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/45.rom_ctrl_max_throughput_chk.1581601826
Short name T264
Test name
Test status
Simulation time 1288625527 ps
CPU time 12.84 seconds
Started Mar 12 12:34:28 PM PDT 24
Finished Mar 12 12:34:41 PM PDT 24
Peak memory 210240 kb
Host smart-74bc6e48-f915-4742-a0b5-45b2e69b9edb
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1581601826 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_max_throughput_chk.1581601826
Directory /workspace/45.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/45.rom_ctrl_smoke.3375951293
Short name T246
Test name
Test status
Simulation time 11294898054 ps
CPU time 30.68 seconds
Started Mar 12 12:34:24 PM PDT 24
Finished Mar 12 12:34:55 PM PDT 24
Peak memory 218556 kb
Host smart-afe99013-df8b-4853-b122-b9d0f9875715
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3375951293 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_smoke.3375951293
Directory /workspace/45.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/45.rom_ctrl_stress_all.2285055190
Short name T267
Test name
Test status
Simulation time 937133689 ps
CPU time 49.36 seconds
Started Mar 12 12:34:28 PM PDT 24
Finished Mar 12 12:35:17 PM PDT 24
Peak memory 214896 kb
Host smart-a3e3e6f1-2fb1-471b-ad9a-e167c1c6141d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2285055190 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 45.rom_ctrl_stress_all.2285055190
Directory /workspace/45.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/46.rom_ctrl_alert_test.3232561474
Short name T329
Test name
Test status
Simulation time 7688004429 ps
CPU time 11.58 seconds
Started Mar 12 12:34:33 PM PDT 24
Finished Mar 12 12:34:45 PM PDT 24
Peak memory 210500 kb
Host smart-869311ca-f8b0-4ad1-97c4-9d5a77ee7935
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3232561474 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_alert_test.3232561474
Directory /workspace/46.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/46.rom_ctrl_corrupt_sig_fatal_chk.2064171993
Short name T134
Test name
Test status
Simulation time 240776889124 ps
CPU time 274.36 seconds
Started Mar 12 12:34:34 PM PDT 24
Finished Mar 12 12:39:09 PM PDT 24
Peak memory 224008 kb
Host smart-a2d0c01d-e18b-4b09-95e3-731987b6abb5
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2064171993 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_
corrupt_sig_fatal_chk.2064171993
Directory /workspace/46.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/46.rom_ctrl_kmac_err_chk.163174968
Short name T196
Test name
Test status
Simulation time 3817143802 ps
CPU time 30.34 seconds
Started Mar 12 12:34:34 PM PDT 24
Finished Mar 12 12:35:05 PM PDT 24
Peak memory 210984 kb
Host smart-bdfe344d-4a8d-4ef3-98e0-9cd50540d098
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=163174968 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_kmac_err_chk.163174968
Directory /workspace/46.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/46.rom_ctrl_max_throughput_chk.1946632507
Short name T219
Test name
Test status
Simulation time 3616042294 ps
CPU time 15.81 seconds
Started Mar 12 12:34:27 PM PDT 24
Finished Mar 12 12:34:43 PM PDT 24
Peak memory 210328 kb
Host smart-bc352a5d-be97-4202-811d-30c79f55869e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1946632507 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_max_throughput_chk.1946632507
Directory /workspace/46.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/46.rom_ctrl_smoke.4146448849
Short name T249
Test name
Test status
Simulation time 2088512773 ps
CPU time 23.06 seconds
Started Mar 12 12:34:25 PM PDT 24
Finished Mar 12 12:34:48 PM PDT 24
Peak memory 212068 kb
Host smart-07d00e68-4c2b-4a73-9109-6fd1dd030366
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4146448849 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_smoke.4146448849
Directory /workspace/46.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/46.rom_ctrl_stress_all.1033318337
Short name T173
Test name
Test status
Simulation time 5092163939 ps
CPU time 43.34 seconds
Started Mar 12 12:34:31 PM PDT 24
Finished Mar 12 12:35:14 PM PDT 24
Peak memory 216124 kb
Host smart-a6d618ec-fd70-4c5a-80c0-cbbcfeccf854
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1033318337 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 46.rom_ctrl_stress_all.1033318337
Directory /workspace/46.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/46.rom_ctrl_stress_all_with_rand_reset.1274629975
Short name T55
Test name
Test status
Simulation time 52980297057 ps
CPU time 2617.89 seconds
Started Mar 12 12:34:34 PM PDT 24
Finished Mar 12 01:18:12 PM PDT 24
Peak memory 235120 kb
Host smart-5f45d389-55cf-44e5-9f33-9f0679f9e484
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1274629975 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_stress_all_with_rand_reset.1274629975
Directory /workspace/46.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.rom_ctrl_alert_test.1040646154
Short name T59
Test name
Test status
Simulation time 346773640 ps
CPU time 4.23 seconds
Started Mar 12 12:34:34 PM PDT 24
Finished Mar 12 12:34:39 PM PDT 24
Peak memory 210372 kb
Host smart-9548a426-e30d-43ce-94a6-ae7605a69dbd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1040646154 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_alert_test.1040646154
Directory /workspace/47.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/47.rom_ctrl_corrupt_sig_fatal_chk.4251480815
Short name T26
Test name
Test status
Simulation time 19852553624 ps
CPU time 133.26 seconds
Started Mar 12 12:34:34 PM PDT 24
Finished Mar 12 12:36:48 PM PDT 24
Peak memory 233528 kb
Host smart-3e184ddc-c154-4cf4-bc71-8edc8f572e51
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4251480815 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_
corrupt_sig_fatal_chk.4251480815
Directory /workspace/47.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/47.rom_ctrl_kmac_err_chk.322480972
Short name T167
Test name
Test status
Simulation time 4898634783 ps
CPU time 23.97 seconds
Started Mar 12 12:34:34 PM PDT 24
Finished Mar 12 12:34:58 PM PDT 24
Peak memory 211204 kb
Host smart-b001e6af-2554-48cf-8b55-0fb8d38e6104
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=322480972 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_kmac_err_chk.322480972
Directory /workspace/47.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/47.rom_ctrl_max_throughput_chk.1344256495
Short name T146
Test name
Test status
Simulation time 129954883 ps
CPU time 5.42 seconds
Started Mar 12 12:34:36 PM PDT 24
Finished Mar 12 12:34:41 PM PDT 24
Peak memory 210276 kb
Host smart-d1f26a0a-fb34-4065-abcb-c61e3d4c69ca
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1344256495 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_max_throughput_chk.1344256495
Directory /workspace/47.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/47.rom_ctrl_smoke.2346945008
Short name T82
Test name
Test status
Simulation time 858167941 ps
CPU time 16.44 seconds
Started Mar 12 12:34:33 PM PDT 24
Finished Mar 12 12:34:50 PM PDT 24
Peak memory 212228 kb
Host smart-b369edb1-d347-4637-a9b9-d4988fe99a34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2346945008 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_smoke.2346945008
Directory /workspace/47.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/47.rom_ctrl_stress_all.3133965546
Short name T252
Test name
Test status
Simulation time 15779946476 ps
CPU time 35.8 seconds
Started Mar 12 12:34:34 PM PDT 24
Finished Mar 12 12:35:10 PM PDT 24
Peak memory 218548 kb
Host smart-492e2d49-a6c9-4e08-8aeb-171fd3c7bf13
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3133965546 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 47.rom_ctrl_stress_all.3133965546
Directory /workspace/47.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/48.rom_ctrl_alert_test.3860965473
Short name T251
Test name
Test status
Simulation time 16505237820 ps
CPU time 9.68 seconds
Started Mar 12 12:34:38 PM PDT 24
Finished Mar 12 12:34:47 PM PDT 24
Peak memory 210480 kb
Host smart-9ee5a4ac-0ad5-4a44-bbbb-752ad723748b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3860965473 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_alert_test.3860965473
Directory /workspace/48.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/48.rom_ctrl_corrupt_sig_fatal_chk.2890212738
Short name T293
Test name
Test status
Simulation time 28275235372 ps
CPU time 140.11 seconds
Started Mar 12 12:34:33 PM PDT 24
Finished Mar 12 12:36:54 PM PDT 24
Peak memory 213696 kb
Host smart-5ca608e5-1f50-469d-8e00-931398e3cec6
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2890212738 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_
corrupt_sig_fatal_chk.2890212738
Directory /workspace/48.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/48.rom_ctrl_kmac_err_chk.2866061880
Short name T142
Test name
Test status
Simulation time 168948147 ps
CPU time 9.54 seconds
Started Mar 12 12:34:36 PM PDT 24
Finished Mar 12 12:34:46 PM PDT 24
Peak memory 210776 kb
Host smart-33ca6d88-2c83-49d9-908c-dabbd5f6e099
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2866061880 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_kmac_err_chk.2866061880
Directory /workspace/48.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/48.rom_ctrl_max_throughput_chk.2043742469
Short name T292
Test name
Test status
Simulation time 98678273 ps
CPU time 5.29 seconds
Started Mar 12 12:34:34 PM PDT 24
Finished Mar 12 12:34:39 PM PDT 24
Peak memory 210300 kb
Host smart-5b0130c1-2e34-4f8e-bb29-475eedee093d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2043742469 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_max_throughput_chk.2043742469
Directory /workspace/48.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/48.rom_ctrl_smoke.4286817763
Short name T268
Test name
Test status
Simulation time 6900081474 ps
CPU time 20.19 seconds
Started Mar 12 12:34:33 PM PDT 24
Finished Mar 12 12:34:54 PM PDT 24
Peak memory 213060 kb
Host smart-871c3524-db07-47c7-b66c-31feeff983c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4286817763 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_smoke.4286817763
Directory /workspace/48.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/48.rom_ctrl_stress_all.530189335
Short name T89
Test name
Test status
Simulation time 7872570179 ps
CPU time 28.01 seconds
Started Mar 12 12:34:35 PM PDT 24
Finished Mar 12 12:35:03 PM PDT 24
Peak memory 215900 kb
Host smart-4b6bdc34-c83c-4e1c-9cad-3edb39d68435
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=530189335 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 48.rom_ctrl_stress_all.530189335
Directory /workspace/48.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/49.rom_ctrl_alert_test.734170820
Short name T149
Test name
Test status
Simulation time 1973529221 ps
CPU time 16.31 seconds
Started Mar 12 12:34:51 PM PDT 24
Finished Mar 12 12:35:08 PM PDT 24
Peak memory 210476 kb
Host smart-eaf90a12-5533-4ce9-85e1-d2d0b7109aab
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=734170820 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_alert_test.734170820
Directory /workspace/49.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/49.rom_ctrl_corrupt_sig_fatal_chk.3540546278
Short name T203
Test name
Test status
Simulation time 8732207110 ps
CPU time 88.45 seconds
Started Mar 12 12:34:50 PM PDT 24
Finished Mar 12 12:36:19 PM PDT 24
Peak memory 211796 kb
Host smart-f3a40b67-4586-483d-b5bc-bc88f778d77e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3540546278 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_
corrupt_sig_fatal_chk.3540546278
Directory /workspace/49.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/49.rom_ctrl_kmac_err_chk.376481885
Short name T183
Test name
Test status
Simulation time 1082540350 ps
CPU time 16.28 seconds
Started Mar 12 12:34:44 PM PDT 24
Finished Mar 12 12:35:01 PM PDT 24
Peak memory 210748 kb
Host smart-20ab45a1-c54a-475e-a6a2-8c8be6df5664
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=376481885 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_kmac_err_chk.376481885
Directory /workspace/49.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/49.rom_ctrl_max_throughput_chk.3239478721
Short name T287
Test name
Test status
Simulation time 1510661581 ps
CPU time 14.28 seconds
Started Mar 12 12:34:39 PM PDT 24
Finished Mar 12 12:34:54 PM PDT 24
Peak memory 210276 kb
Host smart-3421cdfe-5f7a-4a08-94a4-d071c275d6db
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3239478721 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_max_throughput_chk.3239478721
Directory /workspace/49.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/49.rom_ctrl_smoke.3765021764
Short name T4
Test name
Test status
Simulation time 8133452417 ps
CPU time 31.83 seconds
Started Mar 12 12:34:32 PM PDT 24
Finished Mar 12 12:35:04 PM PDT 24
Peak memory 218504 kb
Host smart-8c4bdb42-1f1f-4c21-b4f0-77b2a3989478
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3765021764 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_smoke.3765021764
Directory /workspace/49.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/49.rom_ctrl_stress_all.2026441818
Short name T363
Test name
Test status
Simulation time 8610312382 ps
CPU time 38.86 seconds
Started Mar 12 12:34:36 PM PDT 24
Finished Mar 12 12:35:15 PM PDT 24
Peak memory 213204 kb
Host smart-8b9e64be-ed51-44b7-85c6-81c4542f56f4
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2026441818 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 49.rom_ctrl_stress_all.2026441818
Directory /workspace/49.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/49.rom_ctrl_stress_all_with_rand_reset.2918029086
Short name T51
Test name
Test status
Simulation time 202912718382 ps
CPU time 1238.55 seconds
Started Mar 12 12:34:44 PM PDT 24
Finished Mar 12 12:55:24 PM PDT 24
Peak memory 235088 kb
Host smart-b46d27d4-7d8c-4ebd-986e-bdf182875d9e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2918029086 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_stress_all_with_rand_reset.2918029086
Directory /workspace/49.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.rom_ctrl_alert_test.2433289120
Short name T193
Test name
Test status
Simulation time 195332374 ps
CPU time 4.5 seconds
Started Mar 12 12:33:07 PM PDT 24
Finished Mar 12 12:33:11 PM PDT 24
Peak memory 210440 kb
Host smart-5682c236-467e-41ff-8e1e-e0410b894028
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2433289120 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_alert_test.2433289120
Directory /workspace/5.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/5.rom_ctrl_corrupt_sig_fatal_chk.2746897821
Short name T308
Test name
Test status
Simulation time 47160524061 ps
CPU time 190.47 seconds
Started Mar 12 12:33:06 PM PDT 24
Finished Mar 12 12:36:17 PM PDT 24
Peak memory 237200 kb
Host smart-fba040e5-7597-4b43-b226-b26c0d6fd27f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2746897821 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_c
orrupt_sig_fatal_chk.2746897821
Directory /workspace/5.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/5.rom_ctrl_kmac_err_chk.1302976754
Short name T311
Test name
Test status
Simulation time 3504426435 ps
CPU time 30.59 seconds
Started Mar 12 12:33:08 PM PDT 24
Finished Mar 12 12:33:39 PM PDT 24
Peak memory 210940 kb
Host smart-959ab71d-3f33-4df3-a894-8add64ecb458
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1302976754 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_kmac_err_chk.1302976754
Directory /workspace/5.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/5.rom_ctrl_max_throughput_chk.2802867110
Short name T34
Test name
Test status
Simulation time 1763994052 ps
CPU time 15.34 seconds
Started Mar 12 12:33:06 PM PDT 24
Finished Mar 12 12:33:21 PM PDT 24
Peak memory 210336 kb
Host smart-6741692b-fca7-44c0-b3f3-7f6dda658e36
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2802867110 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_max_throughput_chk.2802867110
Directory /workspace/5.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/5.rom_ctrl_smoke.465322097
Short name T228
Test name
Test status
Simulation time 899382958 ps
CPU time 10.07 seconds
Started Mar 12 12:33:07 PM PDT 24
Finished Mar 12 12:33:17 PM PDT 24
Peak memory 212432 kb
Host smart-461a4994-4151-4fb7-8c35-9bb369d08ef3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=465322097 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_smoke.465322097
Directory /workspace/5.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/5.rom_ctrl_stress_all.1712259399
Short name T160
Test name
Test status
Simulation time 2899168440 ps
CPU time 9.79 seconds
Started Mar 12 12:33:01 PM PDT 24
Finished Mar 12 12:33:10 PM PDT 24
Peak memory 210432 kb
Host smart-62842f3d-b4e4-49b5-8b77-8b060974db2a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1712259399 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 5.rom_ctrl_stress_all.1712259399
Directory /workspace/5.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/6.rom_ctrl_alert_test.2666213117
Short name T282
Test name
Test status
Simulation time 346713714 ps
CPU time 4.32 seconds
Started Mar 12 12:33:07 PM PDT 24
Finished Mar 12 12:33:11 PM PDT 24
Peak memory 210300 kb
Host smart-4d47ff79-7d0f-4adc-aac2-5ff2d4a60562
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2666213117 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_alert_test.2666213117
Directory /workspace/6.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/6.rom_ctrl_corrupt_sig_fatal_chk.74436394
Short name T135
Test name
Test status
Simulation time 39064933176 ps
CPU time 187.07 seconds
Started Mar 12 12:33:08 PM PDT 24
Finished Mar 12 12:36:15 PM PDT 24
Peak memory 221008 kb
Host smart-d5f17c3f-0b82-40d4-8e78-3b4ad31012cc
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74436394 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_
sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_cor
rupt_sig_fatal_chk.74436394
Directory /workspace/6.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/6.rom_ctrl_kmac_err_chk.771203410
Short name T297
Test name
Test status
Simulation time 2208517492 ps
CPU time 23.18 seconds
Started Mar 12 12:33:10 PM PDT 24
Finished Mar 12 12:33:34 PM PDT 24
Peak memory 210952 kb
Host smart-a969a26c-4380-4b00-a3fc-2c5775759b02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=771203410 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_kmac_err_chk.771203410
Directory /workspace/6.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/6.rom_ctrl_max_throughput_chk.1571560212
Short name T302
Test name
Test status
Simulation time 899184174 ps
CPU time 9.87 seconds
Started Mar 12 12:33:10 PM PDT 24
Finished Mar 12 12:33:20 PM PDT 24
Peak memory 210320 kb
Host smart-fb38f771-63e0-40c8-ac02-d542b00ed5ca
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1571560212 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_max_throughput_chk.1571560212
Directory /workspace/6.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/6.rom_ctrl_smoke.204534500
Short name T84
Test name
Test status
Simulation time 3525593091 ps
CPU time 34.25 seconds
Started Mar 12 12:33:05 PM PDT 24
Finished Mar 12 12:33:39 PM PDT 24
Peak memory 212444 kb
Host smart-37b8ab56-92e3-4b83-a3f3-ae6e84737c1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=204534500 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_smoke.204534500
Directory /workspace/6.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/6.rom_ctrl_stress_all.3398150655
Short name T339
Test name
Test status
Simulation time 5124364997 ps
CPU time 60.7 seconds
Started Mar 12 12:33:06 PM PDT 24
Finished Mar 12 12:34:07 PM PDT 24
Peak memory 215652 kb
Host smart-246ae6dc-ceaa-446f-b0d7-ed7f9982a173
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3398150655 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 6.rom_ctrl_stress_all.3398150655
Directory /workspace/6.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/6.rom_ctrl_stress_all_with_rand_reset.1078142488
Short name T50
Test name
Test status
Simulation time 163147491019 ps
CPU time 1014.34 seconds
Started Mar 12 12:33:09 PM PDT 24
Finished Mar 12 12:50:04 PM PDT 24
Peak memory 233960 kb
Host smart-9e1fbef0-82e2-45ba-af4b-59fe6c4b1ede
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1078142488 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_stress_all_with_rand_reset.1078142488
Directory /workspace/6.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.rom_ctrl_alert_test.3393248750
Short name T204
Test name
Test status
Simulation time 498092499 ps
CPU time 7.43 seconds
Started Mar 12 12:33:08 PM PDT 24
Finished Mar 12 12:33:16 PM PDT 24
Peak memory 210364 kb
Host smart-b4e39aa8-14c5-4b0b-a60c-64e9a17f615c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3393248750 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_alert_test.3393248750
Directory /workspace/7.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/7.rom_ctrl_corrupt_sig_fatal_chk.2975983573
Short name T355
Test name
Test status
Simulation time 78663287556 ps
CPU time 184.39 seconds
Started Mar 12 12:33:06 PM PDT 24
Finished Mar 12 12:36:11 PM PDT 24
Peak memory 213116 kb
Host smart-9bc2d61b-a24d-4f5d-8ece-13e481270632
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2975983573 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_c
orrupt_sig_fatal_chk.2975983573
Directory /workspace/7.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/7.rom_ctrl_kmac_err_chk.834600375
Short name T335
Test name
Test status
Simulation time 1333993371 ps
CPU time 17.79 seconds
Started Mar 12 12:33:07 PM PDT 24
Finished Mar 12 12:33:25 PM PDT 24
Peak memory 210840 kb
Host smart-b90f907d-e541-4592-9850-8fdd0ef73aaf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=834600375 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_kmac_err_chk.834600375
Directory /workspace/7.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/7.rom_ctrl_max_throughput_chk.2037131445
Short name T2
Test name
Test status
Simulation time 428759360 ps
CPU time 8.16 seconds
Started Mar 12 12:33:07 PM PDT 24
Finished Mar 12 12:33:15 PM PDT 24
Peak memory 210228 kb
Host smart-c27d35a3-b83c-4379-aebf-beb824598ea0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2037131445 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_max_throughput_chk.2037131445
Directory /workspace/7.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/7.rom_ctrl_smoke.2805226632
Short name T69
Test name
Test status
Simulation time 7147532940 ps
CPU time 33.75 seconds
Started Mar 12 12:33:06 PM PDT 24
Finished Mar 12 12:33:40 PM PDT 24
Peak memory 213168 kb
Host smart-fc44716d-4dba-421d-9307-8d04adab0c36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2805226632 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_smoke.2805226632
Directory /workspace/7.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/7.rom_ctrl_stress_all.3111926096
Short name T273
Test name
Test status
Simulation time 380513291 ps
CPU time 21.45 seconds
Started Mar 12 12:33:09 PM PDT 24
Finished Mar 12 12:33:30 PM PDT 24
Peak memory 214640 kb
Host smart-b6dc24f1-ef2a-4fd9-a34d-658d4b211928
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3111926096 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 7.rom_ctrl_stress_all.3111926096
Directory /workspace/7.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/8.rom_ctrl_alert_test.92824099
Short name T192
Test name
Test status
Simulation time 1514854694 ps
CPU time 7.22 seconds
Started Mar 12 12:33:21 PM PDT 24
Finished Mar 12 12:33:28 PM PDT 24
Peak memory 210368 kb
Host smart-279ca672-d565-4a3a-aa38-8bf6ed593b06
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=92824099 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_alert_test.92824099
Directory /workspace/8.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/8.rom_ctrl_corrupt_sig_fatal_chk.910475075
Short name T109
Test name
Test status
Simulation time 176194073136 ps
CPU time 416.8 seconds
Started Mar 12 12:33:18 PM PDT 24
Finished Mar 12 12:40:15 PM PDT 24
Peak memory 232964 kb
Host smart-d2b96b62-409a-43fa-b2a1-bd53f752c21d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=910475075 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_co
rrupt_sig_fatal_chk.910475075
Directory /workspace/8.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/8.rom_ctrl_kmac_err_chk.3273510930
Short name T326
Test name
Test status
Simulation time 12953997343 ps
CPU time 29.19 seconds
Started Mar 12 12:33:26 PM PDT 24
Finished Mar 12 12:33:55 PM PDT 24
Peak memory 210508 kb
Host smart-20e82dc0-4585-41c6-8c64-e8de125638df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3273510930 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_kmac_err_chk.3273510930
Directory /workspace/8.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/8.rom_ctrl_max_throughput_chk.2308882939
Short name T320
Test name
Test status
Simulation time 1180090824 ps
CPU time 10.54 seconds
Started Mar 12 12:33:18 PM PDT 24
Finished Mar 12 12:33:29 PM PDT 24
Peak memory 210196 kb
Host smart-d6142616-fffb-4460-8772-55693a493cc7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2308882939 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_max_throughput_chk.2308882939
Directory /workspace/8.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/8.rom_ctrl_smoke.2717853130
Short name T199
Test name
Test status
Simulation time 4277809116 ps
CPU time 33.7 seconds
Started Mar 12 12:33:07 PM PDT 24
Finished Mar 12 12:33:41 PM PDT 24
Peak memory 212152 kb
Host smart-b660024b-2733-4e88-8a6c-210da7e0ca4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2717853130 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_smoke.2717853130
Directory /workspace/8.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/8.rom_ctrl_stress_all.1658717097
Short name T214
Test name
Test status
Simulation time 3105649073 ps
CPU time 36.41 seconds
Started Mar 12 12:33:07 PM PDT 24
Finished Mar 12 12:33:44 PM PDT 24
Peak memory 218580 kb
Host smart-19ca532b-1417-487c-9d1b-2ac0e15d6ec5
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1658717097 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 8.rom_ctrl_stress_all.1658717097
Directory /workspace/8.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/9.rom_ctrl_alert_test.3156126748
Short name T178
Test name
Test status
Simulation time 1394975372 ps
CPU time 12.61 seconds
Started Mar 12 12:33:20 PM PDT 24
Finished Mar 12 12:33:32 PM PDT 24
Peak memory 210500 kb
Host smart-cb4c1d1f-ce34-4164-b54b-787716fd2674
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3156126748 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_alert_test.3156126748
Directory /workspace/9.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/9.rom_ctrl_kmac_err_chk.3978378674
Short name T14
Test name
Test status
Simulation time 30937636405 ps
CPU time 26.33 seconds
Started Mar 12 12:33:18 PM PDT 24
Finished Mar 12 12:33:45 PM PDT 24
Peak memory 215588 kb
Host smart-01dfa484-612f-4531-b36d-43c76e9826ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3978378674 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_kmac_err_chk.3978378674
Directory /workspace/9.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/9.rom_ctrl_max_throughput_chk.2233920504
Short name T185
Test name
Test status
Simulation time 3101864570 ps
CPU time 13.49 seconds
Started Mar 12 12:33:18 PM PDT 24
Finished Mar 12 12:33:31 PM PDT 24
Peak memory 210300 kb
Host smart-b337f361-d7ac-4f8e-a8fd-d3d72331a801
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2233920504 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_max_throughput_chk.2233920504
Directory /workspace/9.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/9.rom_ctrl_smoke.3415632793
Short name T212
Test name
Test status
Simulation time 184637233 ps
CPU time 10.09 seconds
Started Mar 12 12:33:20 PM PDT 24
Finished Mar 12 12:33:30 PM PDT 24
Peak memory 211356 kb
Host smart-7581ced0-c614-4e60-b57e-57395da15436
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3415632793 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_smoke.3415632793
Directory /workspace/9.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/9.rom_ctrl_stress_all.162683204
Short name T247
Test name
Test status
Simulation time 25575983053 ps
CPU time 56.68 seconds
Started Mar 12 12:33:22 PM PDT 24
Finished Mar 12 12:34:18 PM PDT 24
Peak memory 218564 kb
Host smart-014ca38a-ff04-4be9-8ad6-1afdea5100e3
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=162683204 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 9.rom_ctrl_stress_all.162683204
Directory /workspace/9.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/9.rom_ctrl_stress_all_with_rand_reset.2600872563
Short name T342
Test name
Test status
Simulation time 83925534631 ps
CPU time 3105.96 seconds
Started Mar 12 12:33:22 PM PDT 24
Finished Mar 12 01:25:08 PM PDT 24
Peak memory 245628 kb
Host smart-22b229a3-fd54-4207-8bb6-5a58f9ac2379
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2600872563 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_stress_all_with_rand_reset.2600872563
Directory /workspace/9.rom_ctrl_stress_all_with_rand_reset/latest
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