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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
97.63 96.97 92.80 97.88 100.00 98.68 98.04 99.07


Total test records in report: 466
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html
T300 /workspace/coverage/default/49.rom_ctrl_smoke.3486682248 Mar 14 01:18:06 PM PDT 24 Mar 14 01:18:28 PM PDT 24 7884376307 ps
T301 /workspace/coverage/default/3.rom_ctrl_max_throughput_chk.2548451821 Mar 14 01:17:19 PM PDT 24 Mar 14 01:17:31 PM PDT 24 2428239865 ps
T302 /workspace/coverage/default/26.rom_ctrl_stress_all.2375473399 Mar 14 01:17:48 PM PDT 24 Mar 14 01:18:49 PM PDT 24 24629485904 ps
T303 /workspace/coverage/default/15.rom_ctrl_corrupt_sig_fatal_chk.1889309826 Mar 14 01:17:35 PM PDT 24 Mar 14 01:24:40 PM PDT 24 439523145026 ps
T304 /workspace/coverage/default/45.rom_ctrl_stress_all_with_rand_reset.2718576783 Mar 14 01:18:00 PM PDT 24 Mar 14 03:15:23 PM PDT 24 148476410136 ps
T305 /workspace/coverage/default/45.rom_ctrl_corrupt_sig_fatal_chk.1685765837 Mar 14 01:18:03 PM PDT 24 Mar 14 01:20:57 PM PDT 24 29703091714 ps
T306 /workspace/coverage/default/42.rom_ctrl_smoke.1750079506 Mar 14 01:18:02 PM PDT 24 Mar 14 01:18:22 PM PDT 24 3296800662 ps
T307 /workspace/coverage/default/21.rom_ctrl_kmac_err_chk.4088486353 Mar 14 01:17:37 PM PDT 24 Mar 14 01:18:10 PM PDT 24 4064239507 ps
T106 /workspace/coverage/default/41.rom_ctrl_max_throughput_chk.2426430812 Mar 14 01:18:01 PM PDT 24 Mar 14 01:18:16 PM PDT 24 1774591128 ps
T308 /workspace/coverage/default/13.rom_ctrl_corrupt_sig_fatal_chk.4214307019 Mar 14 01:17:28 PM PDT 24 Mar 14 01:20:15 PM PDT 24 54183740694 ps
T309 /workspace/coverage/default/32.rom_ctrl_kmac_err_chk.1065076795 Mar 14 01:17:44 PM PDT 24 Mar 14 01:17:54 PM PDT 24 333985083 ps
T310 /workspace/coverage/default/22.rom_ctrl_stress_all.371334210 Mar 14 01:17:36 PM PDT 24 Mar 14 01:17:47 PM PDT 24 979909134 ps
T311 /workspace/coverage/default/38.rom_ctrl_alert_test.2292134380 Mar 14 01:18:02 PM PDT 24 Mar 14 01:18:06 PM PDT 24 347048401 ps
T312 /workspace/coverage/default/44.rom_ctrl_stress_all_with_rand_reset.2507738239 Mar 14 01:18:02 PM PDT 24 Mar 14 01:34:59 PM PDT 24 24335127547 ps
T313 /workspace/coverage/default/42.rom_ctrl_alert_test.2415415578 Mar 14 01:17:58 PM PDT 24 Mar 14 01:18:11 PM PDT 24 4371721877 ps
T314 /workspace/coverage/default/26.rom_ctrl_max_throughput_chk.146332037 Mar 14 01:17:55 PM PDT 24 Mar 14 01:18:09 PM PDT 24 6133131653 ps
T315 /workspace/coverage/default/35.rom_ctrl_max_throughput_chk.3920768318 Mar 14 01:17:48 PM PDT 24 Mar 14 01:18:01 PM PDT 24 5706418238 ps
T316 /workspace/coverage/default/5.rom_ctrl_alert_test.2617943503 Mar 14 01:17:09 PM PDT 24 Mar 14 01:17:22 PM PDT 24 4992973361 ps
T317 /workspace/coverage/default/20.rom_ctrl_alert_test.2538462303 Mar 14 01:17:36 PM PDT 24 Mar 14 01:17:43 PM PDT 24 632307671 ps
T318 /workspace/coverage/default/48.rom_ctrl_stress_all.4103449289 Mar 14 01:18:06 PM PDT 24 Mar 14 01:18:31 PM PDT 24 409065386 ps
T319 /workspace/coverage/default/44.rom_ctrl_corrupt_sig_fatal_chk.1071441818 Mar 14 01:18:06 PM PDT 24 Mar 14 01:21:52 PM PDT 24 36095446935 ps
T320 /workspace/coverage/default/24.rom_ctrl_smoke.3727657567 Mar 14 01:17:37 PM PDT 24 Mar 14 01:17:47 PM PDT 24 235697335 ps
T321 /workspace/coverage/default/25.rom_ctrl_alert_test.1917948077 Mar 14 01:17:58 PM PDT 24 Mar 14 01:18:15 PM PDT 24 11845382115 ps
T322 /workspace/coverage/default/33.rom_ctrl_kmac_err_chk.1674489351 Mar 14 01:17:48 PM PDT 24 Mar 14 01:18:00 PM PDT 24 1588401671 ps
T323 /workspace/coverage/default/10.rom_ctrl_kmac_err_chk.3942611405 Mar 14 01:17:10 PM PDT 24 Mar 14 01:17:20 PM PDT 24 1381666637 ps
T38 /workspace/coverage/default/1.rom_ctrl_sec_cm.3606755111 Mar 14 01:17:03 PM PDT 24 Mar 14 01:18:51 PM PDT 24 3493439306 ps
T324 /workspace/coverage/default/36.rom_ctrl_alert_test.3285531240 Mar 14 01:17:51 PM PDT 24 Mar 14 01:18:03 PM PDT 24 1267637290 ps
T325 /workspace/coverage/default/11.rom_ctrl_kmac_err_chk.401368072 Mar 14 01:17:25 PM PDT 24 Mar 14 01:17:46 PM PDT 24 23645144401 ps
T326 /workspace/coverage/default/17.rom_ctrl_alert_test.2060677484 Mar 14 01:17:36 PM PDT 24 Mar 14 01:17:47 PM PDT 24 4446328965 ps
T327 /workspace/coverage/default/42.rom_ctrl_stress_all.1343306720 Mar 14 01:18:03 PM PDT 24 Mar 14 01:18:25 PM PDT 24 1981383340 ps
T328 /workspace/coverage/default/0.rom_ctrl_alert_test.720020083 Mar 14 01:17:07 PM PDT 24 Mar 14 01:17:11 PM PDT 24 86508675 ps
T329 /workspace/coverage/default/20.rom_ctrl_corrupt_sig_fatal_chk.2321245056 Mar 14 01:17:38 PM PDT 24 Mar 14 01:21:53 PM PDT 24 44270281566 ps
T330 /workspace/coverage/default/43.rom_ctrl_stress_all_with_rand_reset.3062916112 Mar 14 01:18:03 PM PDT 24 Mar 14 01:45:28 PM PDT 24 44320325822 ps
T331 /workspace/coverage/default/40.rom_ctrl_smoke.1334448886 Mar 14 01:18:06 PM PDT 24 Mar 14 01:18:36 PM PDT 24 6159165772 ps
T332 /workspace/coverage/default/18.rom_ctrl_stress_all.4021875872 Mar 14 01:17:34 PM PDT 24 Mar 14 01:17:52 PM PDT 24 778613576 ps
T333 /workspace/coverage/default/25.rom_ctrl_smoke.4279867871 Mar 14 01:17:38 PM PDT 24 Mar 14 01:18:04 PM PDT 24 17269299594 ps
T334 /workspace/coverage/default/29.rom_ctrl_corrupt_sig_fatal_chk.4178076188 Mar 14 01:17:47 PM PDT 24 Mar 14 01:19:59 PM PDT 24 4413202836 ps
T335 /workspace/coverage/default/13.rom_ctrl_smoke.2587572310 Mar 14 01:17:20 PM PDT 24 Mar 14 01:17:55 PM PDT 24 24791201032 ps
T336 /workspace/coverage/default/9.rom_ctrl_alert_test.3529770203 Mar 14 01:17:19 PM PDT 24 Mar 14 01:17:36 PM PDT 24 2183981287 ps
T337 /workspace/coverage/default/11.rom_ctrl_alert_test.284281328 Mar 14 01:17:25 PM PDT 24 Mar 14 01:17:29 PM PDT 24 85476437 ps
T338 /workspace/coverage/default/5.rom_ctrl_smoke.868629500 Mar 14 01:17:20 PM PDT 24 Mar 14 01:17:43 PM PDT 24 1737777916 ps
T339 /workspace/coverage/default/14.rom_ctrl_smoke.1951700899 Mar 14 01:17:26 PM PDT 24 Mar 14 01:18:03 PM PDT 24 7366339273 ps
T340 /workspace/coverage/default/2.rom_ctrl_corrupt_sig_fatal_chk.364674333 Mar 14 01:17:20 PM PDT 24 Mar 14 01:21:56 PM PDT 24 27963399520 ps
T341 /workspace/coverage/default/41.rom_ctrl_kmac_err_chk.471809134 Mar 14 01:18:03 PM PDT 24 Mar 14 01:18:13 PM PDT 24 333930629 ps
T342 /workspace/coverage/default/7.rom_ctrl_smoke.1671730516 Mar 14 01:17:20 PM PDT 24 Mar 14 01:17:57 PM PDT 24 15731943156 ps
T343 /workspace/coverage/default/28.rom_ctrl_max_throughput_chk.2622229814 Mar 14 01:17:51 PM PDT 24 Mar 14 01:17:57 PM PDT 24 97386236 ps
T344 /workspace/coverage/default/16.rom_ctrl_stress_all.2309893407 Mar 14 01:17:35 PM PDT 24 Mar 14 01:17:49 PM PDT 24 1429278054 ps
T345 /workspace/coverage/default/48.rom_ctrl_kmac_err_chk.1456030870 Mar 14 01:18:07 PM PDT 24 Mar 14 01:18:39 PM PDT 24 7915658164 ps
T346 /workspace/coverage/default/17.rom_ctrl_kmac_err_chk.2079729604 Mar 14 01:17:36 PM PDT 24 Mar 14 01:18:07 PM PDT 24 3655248123 ps
T347 /workspace/coverage/default/3.rom_ctrl_kmac_err_chk.381334944 Mar 14 01:17:23 PM PDT 24 Mar 14 01:17:54 PM PDT 24 17490356858 ps
T348 /workspace/coverage/default/32.rom_ctrl_max_throughput_chk.2860635191 Mar 14 01:17:46 PM PDT 24 Mar 14 01:18:02 PM PDT 24 1942011242 ps
T349 /workspace/coverage/default/37.rom_ctrl_smoke.3907921357 Mar 14 01:18:00 PM PDT 24 Mar 14 01:18:10 PM PDT 24 334749455 ps
T350 /workspace/coverage/default/30.rom_ctrl_smoke.1569619930 Mar 14 01:17:46 PM PDT 24 Mar 14 01:18:16 PM PDT 24 4498750083 ps
T351 /workspace/coverage/default/14.rom_ctrl_stress_all.2184684276 Mar 14 01:17:21 PM PDT 24 Mar 14 01:18:13 PM PDT 24 4190089318 ps
T126 /workspace/coverage/default/1.rom_ctrl_stress_all.3253661678 Mar 14 01:17:11 PM PDT 24 Mar 14 01:17:26 PM PDT 24 1374675287 ps
T352 /workspace/coverage/default/25.rom_ctrl_corrupt_sig_fatal_chk.1840242101 Mar 14 01:17:38 PM PDT 24 Mar 14 01:19:47 PM PDT 24 8720352538 ps
T25 /workspace/coverage/default/34.rom_ctrl_kmac_err_chk.3249250393 Mar 14 01:17:51 PM PDT 24 Mar 14 01:18:18 PM PDT 24 40944773220 ps
T353 /workspace/coverage/default/23.rom_ctrl_stress_all.1083018177 Mar 14 01:17:38 PM PDT 24 Mar 14 01:17:59 PM PDT 24 1502199947 ps
T354 /workspace/coverage/default/20.rom_ctrl_max_throughput_chk.3145401072 Mar 14 01:17:36 PM PDT 24 Mar 14 01:17:41 PM PDT 24 352086723 ps
T355 /workspace/coverage/default/34.rom_ctrl_corrupt_sig_fatal_chk.1631311119 Mar 14 01:17:50 PM PDT 24 Mar 14 01:24:22 PM PDT 24 266159580060 ps
T356 /workspace/coverage/default/16.rom_ctrl_alert_test.4041163150 Mar 14 01:17:34 PM PDT 24 Mar 14 01:17:48 PM PDT 24 1619410855 ps
T357 /workspace/coverage/default/39.rom_ctrl_kmac_err_chk.1450792391 Mar 14 01:17:59 PM PDT 24 Mar 14 01:18:22 PM PDT 24 7927877026 ps
T358 /workspace/coverage/default/25.rom_ctrl_max_throughput_chk.3720414796 Mar 14 01:17:38 PM PDT 24 Mar 14 01:17:43 PM PDT 24 694213761 ps
T359 /workspace/coverage/default/37.rom_ctrl_kmac_err_chk.1922608332 Mar 14 01:18:09 PM PDT 24 Mar 14 01:18:35 PM PDT 24 2925367128 ps
T360 /workspace/coverage/default/41.rom_ctrl_smoke.3823452976 Mar 14 01:18:07 PM PDT 24 Mar 14 01:18:48 PM PDT 24 3444105770 ps
T361 /workspace/coverage/default/36.rom_ctrl_kmac_err_chk.425186559 Mar 14 01:17:49 PM PDT 24 Mar 14 01:18:09 PM PDT 24 3118712527 ps
T362 /workspace/coverage/default/8.rom_ctrl_corrupt_sig_fatal_chk.3506029630 Mar 14 01:17:23 PM PDT 24 Mar 14 01:19:12 PM PDT 24 1867783801 ps
T15 /workspace/coverage/default/48.rom_ctrl_stress_all_with_rand_reset.1829770058 Mar 14 01:18:11 PM PDT 24 Mar 14 02:17:59 PM PDT 24 47778131121 ps
T363 /workspace/coverage/default/38.rom_ctrl_smoke.82280542 Mar 14 01:18:04 PM PDT 24 Mar 14 01:18:32 PM PDT 24 5574247613 ps
T364 /workspace/coverage/default/36.rom_ctrl_corrupt_sig_fatal_chk.3957264362 Mar 14 01:17:49 PM PDT 24 Mar 14 01:24:57 PM PDT 24 296610161899 ps
T365 /workspace/coverage/default/20.rom_ctrl_kmac_err_chk.3142315502 Mar 14 01:17:35 PM PDT 24 Mar 14 01:17:44 PM PDT 24 1106043104 ps
T57 /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_intg_err.1617818761 Mar 14 01:15:17 PM PDT 24 Mar 14 01:16:02 PM PDT 24 6562989621 ps
T60 /workspace/coverage/cover_reg_top/6.rom_ctrl_same_csr_outstanding.3578120627 Mar 14 01:14:59 PM PDT 24 Mar 14 01:15:13 PM PDT 24 1314202799 ps
T61 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_bit_bash.3301604563 Mar 14 01:15:04 PM PDT 24 Mar 14 01:15:08 PM PDT 24 204866207 ps
T366 /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_mem_rw_with_rand_reset.3267135477 Mar 14 01:15:32 PM PDT 24 Mar 14 01:15:45 PM PDT 24 2582724384 ps
T367 /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_mem_rw_with_rand_reset.830189929 Mar 14 01:15:38 PM PDT 24 Mar 14 01:15:54 PM PDT 24 2070050556 ps
T368 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_mem_rw_with_rand_reset.3988347656 Mar 14 01:15:04 PM PDT 24 Mar 14 01:15:09 PM PDT 24 103299115 ps
T107 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_aliasing.2936219218 Mar 14 01:14:55 PM PDT 24 Mar 14 01:14:59 PM PDT 24 347102399 ps
T65 /workspace/coverage/cover_reg_top/2.rom_ctrl_passthru_mem_tl_intg_err.2130307902 Mar 14 01:14:55 PM PDT 24 Mar 14 01:16:19 PM PDT 24 10083889495 ps
T369 /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_errors.828963433 Mar 14 01:15:18 PM PDT 24 Mar 14 01:15:29 PM PDT 24 464213541 ps
T370 /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_errors.3752568281 Mar 14 01:15:06 PM PDT 24 Mar 14 01:15:25 PM PDT 24 2057964601 ps
T371 /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_walk.3943585491 Mar 14 01:15:01 PM PDT 24 Mar 14 01:15:13 PM PDT 24 2716144475 ps
T66 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_aliasing.2645322395 Mar 14 01:15:03 PM PDT 24 Mar 14 01:15:17 PM PDT 24 6619626811 ps
T372 /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_mem_rw_with_rand_reset.1663312360 Mar 14 01:15:16 PM PDT 24 Mar 14 01:15:30 PM PDT 24 3039716446 ps
T373 /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_errors.371992029 Mar 14 01:15:35 PM PDT 24 Mar 14 01:15:52 PM PDT 24 1673419516 ps
T98 /workspace/coverage/cover_reg_top/2.rom_ctrl_same_csr_outstanding.4089416758 Mar 14 01:15:06 PM PDT 24 Mar 14 01:15:23 PM PDT 24 9220757200 ps
T99 /workspace/coverage/cover_reg_top/0.rom_ctrl_same_csr_outstanding.2685617472 Mar 14 01:14:58 PM PDT 24 Mar 14 01:15:12 PM PDT 24 4198636763 ps
T374 /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_mem_rw_with_rand_reset.1374837488 Mar 14 01:15:32 PM PDT 24 Mar 14 01:15:44 PM PDT 24 2517724781 ps
T108 /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_rw.2343589680 Mar 14 01:15:32 PM PDT 24 Mar 14 01:15:42 PM PDT 24 3679421168 ps
T58 /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_intg_err.165429751 Mar 14 01:15:03 PM PDT 24 Mar 14 01:15:43 PM PDT 24 481711029 ps
T109 /workspace/coverage/cover_reg_top/1.rom_ctrl_passthru_mem_tl_intg_err.1232045901 Mar 14 01:14:52 PM PDT 24 Mar 14 01:15:49 PM PDT 24 7171381886 ps
T67 /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_rw.550616756 Mar 14 01:15:34 PM PDT 24 Mar 14 01:15:50 PM PDT 24 1992469943 ps
T375 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_bit_bash.1007970888 Mar 14 01:15:03 PM PDT 24 Mar 14 01:15:19 PM PDT 24 8380518584 ps
T59 /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_intg_err.777056836 Mar 14 01:15:15 PM PDT 24 Mar 14 01:16:32 PM PDT 24 39058802308 ps
T68 /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_rw.5707714 Mar 14 01:15:31 PM PDT 24 Mar 14 01:15:46 PM PDT 24 1949544688 ps
T69 /workspace/coverage/cover_reg_top/18.rom_ctrl_passthru_mem_tl_intg_err.1790892973 Mar 14 01:15:30 PM PDT 24 Mar 14 01:16:38 PM PDT 24 13160528553 ps
T376 /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_mem_rw_with_rand_reset.2081614350 Mar 14 01:15:31 PM PDT 24 Mar 14 01:15:46 PM PDT 24 5764641831 ps
T115 /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_intg_err.920273803 Mar 14 01:15:35 PM PDT 24 Mar 14 01:16:52 PM PDT 24 9895773940 ps
T70 /workspace/coverage/cover_reg_top/8.rom_ctrl_same_csr_outstanding.3938133369 Mar 14 01:15:18 PM PDT 24 Mar 14 01:15:31 PM PDT 24 4259662878 ps
T100 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_rw.3715747676 Mar 14 01:15:00 PM PDT 24 Mar 14 01:15:04 PM PDT 24 1037495873 ps
T71 /workspace/coverage/cover_reg_top/9.rom_ctrl_same_csr_outstanding.1129449618 Mar 14 01:15:17 PM PDT 24 Mar 14 01:15:35 PM PDT 24 11303924028 ps
T377 /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_mem_rw_with_rand_reset.2860346492 Mar 14 01:15:02 PM PDT 24 Mar 14 01:15:14 PM PDT 24 4114709593 ps
T101 /workspace/coverage/cover_reg_top/1.rom_ctrl_same_csr_outstanding.198070201 Mar 14 01:14:54 PM PDT 24 Mar 14 01:14:58 PM PDT 24 89780329 ps
T378 /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_errors.884749473 Mar 14 01:15:20 PM PDT 24 Mar 14 01:15:35 PM PDT 24 1770665293 ps
T119 /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_intg_err.2840026370 Mar 14 01:14:59 PM PDT 24 Mar 14 01:15:46 PM PDT 24 7976025280 ps
T114 /workspace/coverage/cover_reg_top/7.rom_ctrl_passthru_mem_tl_intg_err.1147878994 Mar 14 01:15:04 PM PDT 24 Mar 14 01:16:41 PM PDT 24 49094610638 ps
T379 /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_mem_rw_with_rand_reset.2796635100 Mar 14 01:15:17 PM PDT 24 Mar 14 01:15:22 PM PDT 24 392506561 ps
T102 /workspace/coverage/cover_reg_top/0.rom_ctrl_passthru_mem_tl_intg_err.3294228269 Mar 14 01:14:55 PM PDT 24 Mar 14 01:16:07 PM PDT 24 19464647937 ps
T380 /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_errors.62134410 Mar 14 01:15:32 PM PDT 24 Mar 14 01:15:50 PM PDT 24 3652610117 ps
T381 /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_rw.2946039642 Mar 14 01:15:17 PM PDT 24 Mar 14 01:15:27 PM PDT 24 2057292505 ps
T382 /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_errors.2710837599 Mar 14 01:14:49 PM PDT 24 Mar 14 01:15:01 PM PDT 24 1564330650 ps
T116 /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_intg_err.1461954390 Mar 14 01:14:58 PM PDT 24 Mar 14 01:16:12 PM PDT 24 2350543091 ps
T72 /workspace/coverage/cover_reg_top/6.rom_ctrl_passthru_mem_tl_intg_err.823281628 Mar 14 01:15:02 PM PDT 24 Mar 14 01:15:21 PM PDT 24 1483268664 ps
T73 /workspace/coverage/cover_reg_top/12.rom_ctrl_passthru_mem_tl_intg_err.1977376583 Mar 14 01:15:14 PM PDT 24 Mar 14 01:16:11 PM PDT 24 6723811828 ps
T103 /workspace/coverage/cover_reg_top/11.rom_ctrl_same_csr_outstanding.3016746262 Mar 14 01:15:16 PM PDT 24 Mar 14 01:15:24 PM PDT 24 674186024 ps
T74 /workspace/coverage/cover_reg_top/15.rom_ctrl_same_csr_outstanding.1944423135 Mar 14 01:15:31 PM PDT 24 Mar 14 01:15:42 PM PDT 24 1125953666 ps
T383 /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_errors.53877308 Mar 14 01:15:04 PM PDT 24 Mar 14 01:15:23 PM PDT 24 1751531113 ps
T384 /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_errors.3724029201 Mar 14 01:15:31 PM PDT 24 Mar 14 01:15:43 PM PDT 24 3416511672 ps
T117 /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_intg_err.1248901327 Mar 14 01:15:18 PM PDT 24 Mar 14 01:16:38 PM PDT 24 2366242408 ps
T385 /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_rw.111655649 Mar 14 01:15:03 PM PDT 24 Mar 14 01:15:11 PM PDT 24 2591617314 ps
T81 /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_rw.3933491623 Mar 14 01:15:04 PM PDT 24 Mar 14 01:15:21 PM PDT 24 10862084732 ps
T386 /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_intg_err.3853243009 Mar 14 01:15:31 PM PDT 24 Mar 14 01:16:14 PM PDT 24 1474213027 ps
T82 /workspace/coverage/cover_reg_top/10.rom_ctrl_passthru_mem_tl_intg_err.3113648825 Mar 14 01:15:18 PM PDT 24 Mar 14 01:15:52 PM PDT 24 20635270656 ps
T387 /workspace/coverage/cover_reg_top/13.rom_ctrl_passthru_mem_tl_intg_err.4003737699 Mar 14 01:15:20 PM PDT 24 Mar 14 01:15:39 PM PDT 24 1440048064 ps
T388 /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_errors.1802792717 Mar 14 01:15:14 PM PDT 24 Mar 14 01:15:24 PM PDT 24 1981950520 ps
T389 /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_rw.3919858096 Mar 14 01:15:34 PM PDT 24 Mar 14 01:15:38 PM PDT 24 88937223 ps
T390 /workspace/coverage/cover_reg_top/7.rom_ctrl_same_csr_outstanding.207141502 Mar 14 01:15:17 PM PDT 24 Mar 14 01:15:30 PM PDT 24 1126097064 ps
T83 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_hw_reset.795796934 Mar 14 01:15:01 PM PDT 24 Mar 14 01:15:19 PM PDT 24 6889767896 ps
T391 /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_intg_err.3225594475 Mar 14 01:15:37 PM PDT 24 Mar 14 01:16:12 PM PDT 24 3016957308 ps
T392 /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_errors.2819234614 Mar 14 01:15:00 PM PDT 24 Mar 14 01:15:07 PM PDT 24 591861443 ps
T393 /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_errors.1236564439 Mar 14 01:15:36 PM PDT 24 Mar 14 01:15:55 PM PDT 24 1919416870 ps
T394 /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_mem_rw_with_rand_reset.2206879989 Mar 14 01:15:18 PM PDT 24 Mar 14 01:15:24 PM PDT 24 195630344 ps
T395 /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_rw.2336723114 Mar 14 01:15:14 PM PDT 24 Mar 14 01:15:26 PM PDT 24 2475343518 ps
T396 /workspace/coverage/cover_reg_top/16.rom_ctrl_same_csr_outstanding.1263866091 Mar 14 01:15:36 PM PDT 24 Mar 14 01:15:42 PM PDT 24 385681544 ps
T397 /workspace/coverage/cover_reg_top/12.rom_ctrl_same_csr_outstanding.3021457376 Mar 14 01:15:19 PM PDT 24 Mar 14 01:15:36 PM PDT 24 12273050256 ps
T121 /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_intg_err.2751498260 Mar 14 01:15:16 PM PDT 24 Mar 14 01:15:55 PM PDT 24 1460594444 ps
T398 /workspace/coverage/cover_reg_top/10.rom_ctrl_same_csr_outstanding.111113869 Mar 14 01:15:14 PM PDT 24 Mar 14 01:15:26 PM PDT 24 8795831885 ps
T399 /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_errors.2336944926 Mar 14 01:14:55 PM PDT 24 Mar 14 01:15:07 PM PDT 24 956943702 ps
T400 /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_intg_err.552099239 Mar 14 01:15:18 PM PDT 24 Mar 14 01:16:27 PM PDT 24 326824027 ps
T84 /workspace/coverage/cover_reg_top/16.rom_ctrl_passthru_mem_tl_intg_err.4031610115 Mar 14 01:15:32 PM PDT 24 Mar 14 01:16:16 PM PDT 24 17891140870 ps
T88 /workspace/coverage/cover_reg_top/17.rom_ctrl_passthru_mem_tl_intg_err.3363248691 Mar 14 01:15:32 PM PDT 24 Mar 14 01:16:12 PM PDT 24 8641363547 ps
T401 /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_rw.547459964 Mar 14 01:15:14 PM PDT 24 Mar 14 01:15:25 PM PDT 24 4797905544 ps
T402 /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_errors.1909495695 Mar 14 01:15:18 PM PDT 24 Mar 14 01:15:25 PM PDT 24 378052759 ps
T85 /workspace/coverage/cover_reg_top/15.rom_ctrl_passthru_mem_tl_intg_err.3728792744 Mar 14 01:15:34 PM PDT 24 Mar 14 01:17:05 PM PDT 24 55975290276 ps
T403 /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_partial_access.887519949 Mar 14 01:15:03 PM PDT 24 Mar 14 01:15:12 PM PDT 24 814752930 ps
T118 /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_intg_err.1085759311 Mar 14 01:15:36 PM PDT 24 Mar 14 01:16:20 PM PDT 24 1568831265 ps
T404 /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_partial_access.3105686210 Mar 14 01:14:59 PM PDT 24 Mar 14 01:15:04 PM PDT 24 488211456 ps
T405 /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_errors.3996470485 Mar 14 01:15:03 PM PDT 24 Mar 14 01:15:16 PM PDT 24 4780972159 ps
T406 /workspace/coverage/cover_reg_top/5.rom_ctrl_same_csr_outstanding.2995258861 Mar 14 01:15:04 PM PDT 24 Mar 14 01:15:20 PM PDT 24 2079360356 ps
T407 /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_intg_err.429423326 Mar 14 01:15:04 PM PDT 24 Mar 14 01:15:50 PM PDT 24 4023402836 ps
T408 /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_rw.1371576695 Mar 14 01:15:17 PM PDT 24 Mar 14 01:15:26 PM PDT 24 2629446266 ps
T409 /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_errors.1838964353 Mar 14 01:15:18 PM PDT 24 Mar 14 01:15:34 PM PDT 24 6470860268 ps
T410 /workspace/coverage/cover_reg_top/3.rom_ctrl_same_csr_outstanding.3106252969 Mar 14 01:14:57 PM PDT 24 Mar 14 01:15:13 PM PDT 24 9979122868 ps
T411 /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_errors.1789644021 Mar 14 01:14:55 PM PDT 24 Mar 14 01:15:10 PM PDT 24 1053427417 ps
T412 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_mem_rw_with_rand_reset.2414882399 Mar 14 01:15:04 PM PDT 24 Mar 14 01:15:09 PM PDT 24 330483952 ps
T413 /workspace/coverage/cover_reg_top/11.rom_ctrl_passthru_mem_tl_intg_err.4225672462 Mar 14 01:15:18 PM PDT 24 Mar 14 01:16:06 PM PDT 24 19070046907 ps
T124 /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_intg_err.89680543 Mar 14 01:14:54 PM PDT 24 Mar 14 01:16:12 PM PDT 24 8314117427 ps
T414 /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_errors.1977097294 Mar 14 01:15:31 PM PDT 24 Mar 14 01:15:45 PM PDT 24 4148066593 ps
T415 /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_mem_rw_with_rand_reset.915532242 Mar 14 01:15:17 PM PDT 24 Mar 14 01:15:28 PM PDT 24 1040291770 ps
T416 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_hw_reset.1110542880 Mar 14 01:15:02 PM PDT 24 Mar 14 01:15:14 PM PDT 24 1070534274 ps
T417 /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_intg_err.3620055260 Mar 14 01:15:31 PM PDT 24 Mar 14 01:16:10 PM PDT 24 671374220 ps
T418 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_rw.1205380674 Mar 14 01:15:03 PM PDT 24 Mar 14 01:15:14 PM PDT 24 4474044087 ps
T419 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_mem_rw_with_rand_reset.2533160014 Mar 14 01:15:00 PM PDT 24 Mar 14 01:15:15 PM PDT 24 1653609362 ps
T420 /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_rw.850953601 Mar 14 01:15:20 PM PDT 24 Mar 14 01:15:30 PM PDT 24 5782016030 ps
T421 /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_partial_access.1504963680 Mar 14 01:14:51 PM PDT 24 Mar 14 01:14:59 PM PDT 24 1415984221 ps
T422 /workspace/coverage/cover_reg_top/4.rom_ctrl_same_csr_outstanding.1147868118 Mar 14 01:15:07 PM PDT 24 Mar 14 01:15:18 PM PDT 24 3263033981 ps
T423 /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_mem_rw_with_rand_reset.1817801209 Mar 14 01:15:17 PM PDT 24 Mar 14 01:15:23 PM PDT 24 103185404 ps
T122 /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_intg_err.2608821630 Mar 14 01:15:03 PM PDT 24 Mar 14 01:15:47 PM PDT 24 5339665374 ps
T89 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_hw_reset.1571609181 Mar 14 01:14:52 PM PDT 24 Mar 14 01:15:08 PM PDT 24 1704021728 ps
T424 /workspace/coverage/cover_reg_top/5.rom_ctrl_passthru_mem_tl_intg_err.3209182899 Mar 14 01:15:02 PM PDT 24 Mar 14 01:16:35 PM PDT 24 39174629120 ps
T425 /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_errors.1533432224 Mar 14 01:15:19 PM PDT 24 Mar 14 01:15:38 PM PDT 24 1918995334 ps
T426 /workspace/coverage/cover_reg_top/8.rom_ctrl_passthru_mem_tl_intg_err.3078807196 Mar 14 01:15:14 PM PDT 24 Mar 14 01:15:43 PM PDT 24 2086771223 ps
T427 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_mem_rw_with_rand_reset.258049491 Mar 14 01:14:49 PM PDT 24 Mar 14 01:14:54 PM PDT 24 244451178 ps
T428 /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_mem_rw_with_rand_reset.216656795 Mar 14 01:15:36 PM PDT 24 Mar 14 01:15:44 PM PDT 24 546677052 ps
T429 /workspace/coverage/cover_reg_top/19.rom_ctrl_same_csr_outstanding.4108576239 Mar 14 01:15:33 PM PDT 24 Mar 14 01:15:43 PM PDT 24 13400059340 ps
T86 /workspace/coverage/cover_reg_top/4.rom_ctrl_passthru_mem_tl_intg_err.3802037367 Mar 14 01:15:04 PM PDT 24 Mar 14 01:16:05 PM PDT 24 7653883607 ps
T430 /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_mem_rw_with_rand_reset.3600329492 Mar 14 01:15:32 PM PDT 24 Mar 14 01:15:47 PM PDT 24 6659410328 ps
T431 /workspace/coverage/cover_reg_top/3.rom_ctrl_passthru_mem_tl_intg_err.630787112 Mar 14 01:15:01 PM PDT 24 Mar 14 01:15:52 PM PDT 24 7193330730 ps
T432 /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_intg_err.2945820114 Mar 14 01:15:03 PM PDT 24 Mar 14 01:15:48 PM PDT 24 477096335 ps
T433 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_mem_rw_with_rand_reset.2579606309 Mar 14 01:14:52 PM PDT 24 Mar 14 01:15:05 PM PDT 24 5651193963 ps
T434 /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_walk.2229936312 Mar 14 01:14:52 PM PDT 24 Mar 14 01:15:03 PM PDT 24 2315685814 ps
T435 /workspace/coverage/cover_reg_top/14.rom_ctrl_passthru_mem_tl_intg_err.1544757951 Mar 14 01:15:16 PM PDT 24 Mar 14 01:15:54 PM PDT 24 3018515151 ps
T436 /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_rw.2059274124 Mar 14 01:15:18 PM PDT 24 Mar 14 01:15:29 PM PDT 24 1261437735 ps
T437 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_aliasing.587813799 Mar 14 01:15:02 PM PDT 24 Mar 14 01:15:17 PM PDT 24 6491475797 ps
T438 /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_walk.1711766569 Mar 14 01:14:52 PM PDT 24 Mar 14 01:14:58 PM PDT 24 456022844 ps
T439 /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_walk.2597953472 Mar 14 01:14:53 PM PDT 24 Mar 14 01:15:00 PM PDT 24 1480309022 ps
T440 /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_mem_rw_with_rand_reset.779171850 Mar 14 01:15:02 PM PDT 24 Mar 14 01:15:08 PM PDT 24 317429548 ps
T441 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_bit_bash.3051120695 Mar 14 01:15:01 PM PDT 24 Mar 14 01:15:14 PM PDT 24 1483975445 ps
T120 /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_intg_err.3932414242 Mar 14 01:15:18 PM PDT 24 Mar 14 01:16:35 PM PDT 24 1163976277 ps
T442 /workspace/coverage/cover_reg_top/18.rom_ctrl_same_csr_outstanding.1234925459 Mar 14 01:15:32 PM PDT 24 Mar 14 01:15:40 PM PDT 24 683900923 ps
T443 /workspace/coverage/cover_reg_top/14.rom_ctrl_same_csr_outstanding.2772153040 Mar 14 01:15:17 PM PDT 24 Mar 14 01:15:28 PM PDT 24 3867116250 ps
T444 /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_intg_err.2225225822 Mar 14 01:15:01 PM PDT 24 Mar 14 01:15:38 PM PDT 24 166285091 ps
T445 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_bit_bash.2104100717 Mar 14 01:14:52 PM PDT 24 Mar 14 01:15:05 PM PDT 24 1361836410 ps
T446 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_rw.865004165 Mar 14 01:14:56 PM PDT 24 Mar 14 01:15:02 PM PDT 24 593344678 ps
T447 /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_mem_rw_with_rand_reset.2282034200 Mar 14 01:15:18 PM PDT 24 Mar 14 01:15:31 PM PDT 24 5772752654 ps
T448 /workspace/coverage/cover_reg_top/13.rom_ctrl_same_csr_outstanding.3137623535 Mar 14 01:15:17 PM PDT 24 Mar 14 01:15:34 PM PDT 24 2044729339 ps
T449 /workspace/coverage/cover_reg_top/9.rom_ctrl_passthru_mem_tl_intg_err.4038166378 Mar 14 01:15:15 PM PDT 24 Mar 14 01:15:48 PM PDT 24 9327891732 ps
T450 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_hw_reset.2001778395 Mar 14 01:14:50 PM PDT 24 Mar 14 01:15:05 PM PDT 24 1255394202 ps
T451 /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_rw.356798705 Mar 14 01:15:19 PM PDT 24 Mar 14 01:15:26 PM PDT 24 1039386986 ps
T452 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_aliasing.334570255 Mar 14 01:15:03 PM PDT 24 Mar 14 01:15:14 PM PDT 24 4767602225 ps
T453 /workspace/coverage/cover_reg_top/17.rom_ctrl_same_csr_outstanding.1886710993 Mar 14 01:15:37 PM PDT 24 Mar 14 01:15:51 PM PDT 24 1508444581 ps
T454 /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_partial_access.76802475 Mar 14 01:14:55 PM PDT 24 Mar 14 01:15:06 PM PDT 24 1059207816 ps
T455 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_rw.450974091 Mar 14 01:14:54 PM PDT 24 Mar 14 01:14:59 PM PDT 24 168162883 ps
T456 /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_errors.2618321573 Mar 14 01:14:59 PM PDT 24 Mar 14 01:15:07 PM PDT 24 347391246 ps
T457 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_aliasing.2807289496 Mar 14 01:14:58 PM PDT 24 Mar 14 01:15:16 PM PDT 24 2242251539 ps
T458 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_hw_reset.3236797439 Mar 14 01:14:55 PM PDT 24 Mar 14 01:15:00 PM PDT 24 354726586 ps
T459 /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_partial_access.3595358417 Mar 14 01:15:05 PM PDT 24 Mar 14 01:15:19 PM PDT 24 3562442474 ps
T460 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_rw.1251612339 Mar 14 01:15:07 PM PDT 24 Mar 14 01:15:19 PM PDT 24 1446572160 ps
T461 /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_walk.2078954763 Mar 14 01:15:04 PM PDT 24 Mar 14 01:15:15 PM PDT 24 1189270256 ps
T462 /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_rw.3042255892 Mar 14 01:15:18 PM PDT 24 Mar 14 01:15:26 PM PDT 24 695180853 ps
T463 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_bit_bash.3497461674 Mar 14 01:14:58 PM PDT 24 Mar 14 01:15:13 PM PDT 24 1939680871 ps
T464 /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_mem_rw_with_rand_reset.311474362 Mar 14 01:15:19 PM PDT 24 Mar 14 01:15:27 PM PDT 24 2273570590 ps
T123 /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_intg_err.2563979262 Mar 14 01:15:13 PM PDT 24 Mar 14 01:15:57 PM PDT 24 1394879731 ps
T87 /workspace/coverage/cover_reg_top/19.rom_ctrl_passthru_mem_tl_intg_err.941573651 Mar 14 01:15:38 PM PDT 24 Mar 14 01:16:29 PM PDT 24 22560739866 ps
T465 /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_rw.1139550177 Mar 14 01:15:32 PM PDT 24 Mar 14 01:15:44 PM PDT 24 8701403869 ps
T466 /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_errors.1479618660 Mar 14 01:15:17 PM PDT 24 Mar 14 01:15:36 PM PDT 24 7606055716 ps

Test location /workspace/coverage/default/25.rom_ctrl_stress_all_with_rand_reset.1996701834
Short name T1
Test name
Test status
Simulation time 131488084041 ps
CPU time 1406.48 seconds
Started Mar 14 01:17:48 PM PDT 24
Finished Mar 14 01:41:15 PM PDT 24
Peak memory 235828 kb
Host smart-eeee750c-e66a-4016-a2a4-f79d81e92764
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1996701834 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_stress_all_with_rand_reset.1996701834
Directory /workspace/25.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/16.rom_ctrl_corrupt_sig_fatal_chk.1694673465
Short name T9
Test name
Test status
Simulation time 141835625692 ps
CPU time 394.61 seconds
Started Mar 14 01:17:34 PM PDT 24
Finished Mar 14 01:24:08 PM PDT 24
Peak memory 225080 kb
Host smart-aaba067b-2c0a-4bea-a035-46c115b912b4
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1694673465 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_
corrupt_sig_fatal_chk.1694673465
Directory /workspace/16.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/10.rom_ctrl_corrupt_sig_fatal_chk.619900417
Short name T22
Test name
Test status
Simulation time 16081780552 ps
CPU time 208.06 seconds
Started Mar 14 01:17:24 PM PDT 24
Finished Mar 14 01:20:52 PM PDT 24
Peak memory 228536 kb
Host smart-a60adf03-eb9b-4014-9051-1675f704ed47
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=619900417 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_c
orrupt_sig_fatal_chk.619900417
Directory /workspace/10.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_intg_err.920273803
Short name T115
Test name
Test status
Simulation time 9895773940 ps
CPU time 76.28 seconds
Started Mar 14 01:15:35 PM PDT 24
Finished Mar 14 01:16:52 PM PDT 24
Peak memory 212316 kb
Host smart-f5e21628-03f5-43e2-85b8-ee7c25fa6818
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=920273803 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_tl_in
tg_err.920273803
Directory /workspace/19.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/0.rom_ctrl_smoke.233353498
Short name T40
Test name
Test status
Simulation time 28827729148 ps
CPU time 23.48 seconds
Started Mar 14 01:17:06 PM PDT 24
Finished Mar 14 01:17:30 PM PDT 24
Peak memory 214228 kb
Host smart-0e0126cf-ed47-49c3-b1fa-7027597f3c4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=233353498 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_smoke.233353498
Directory /workspace/0.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/0.rom_ctrl_sec_cm.4211938548
Short name T37
Test name
Test status
Simulation time 4164195607 ps
CPU time 108.65 seconds
Started Mar 14 01:17:08 PM PDT 24
Finished Mar 14 01:18:56 PM PDT 24
Peak memory 237804 kb
Host smart-76cab939-4815-47d4-960a-657edd0852a5
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4211938548 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_sec_cm.4211938548
Directory /workspace/0.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/49.rom_ctrl_stress_all.3208597286
Short name T8
Test name
Test status
Simulation time 9159690765 ps
CPU time 32.76 seconds
Started Mar 14 01:18:11 PM PDT 24
Finished Mar 14 01:18:44 PM PDT 24
Peak memory 215548 kb
Host smart-cdecb8bd-4b53-48e7-8489-cf2df48b90a0
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3208597286 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 49.rom_ctrl_stress_all.3208597286
Directory /workspace/49.rom_ctrl_stress_all/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_aliasing.2645322395
Short name T66
Test name
Test status
Simulation time 6619626811 ps
CPU time 13.93 seconds
Started Mar 14 01:15:03 PM PDT 24
Finished Mar 14 01:15:17 PM PDT 24
Peak memory 211336 kb
Host smart-1165ff71-5308-4a6f-bb08-0fb744c09bc1
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2645322395 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_alia
sing.2645322395
Directory /workspace/4.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_intg_err.3932414242
Short name T120
Test name
Test status
Simulation time 1163976277 ps
CPU time 75.91 seconds
Started Mar 14 01:15:18 PM PDT 24
Finished Mar 14 01:16:35 PM PDT 24
Peak memory 212288 kb
Host smart-958c76b1-499c-49f1-b519-98bad7b13171
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3932414242 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_tl_i
ntg_err.3932414242
Directory /workspace/11.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/14.rom_ctrl_alert_test.1413817386
Short name T7
Test name
Test status
Simulation time 4747340163 ps
CPU time 11.98 seconds
Started Mar 14 01:17:25 PM PDT 24
Finished Mar 14 01:17:37 PM PDT 24
Peak memory 211216 kb
Host smart-90bc1498-a93f-41ab-9bb8-e8c2cac3b453
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1413817386 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_alert_test.1413817386
Directory /workspace/14.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/1.rom_ctrl_stress_all.3253661678
Short name T126
Test name
Test status
Simulation time 1374675287 ps
CPU time 14.76 seconds
Started Mar 14 01:17:11 PM PDT 24
Finished Mar 14 01:17:26 PM PDT 24
Peak memory 211612 kb
Host smart-2bf4cc1b-60a3-4178-88d8-42d572b65f3e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3253661678 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 1.rom_ctrl_stress_all.3253661678
Directory /workspace/1.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/35.rom_ctrl_kmac_err_chk.1625390028
Short name T21
Test name
Test status
Simulation time 340333864 ps
CPU time 9.45 seconds
Started Mar 14 01:17:50 PM PDT 24
Finished Mar 14 01:18:00 PM PDT 24
Peak memory 211732 kb
Host smart-785ff3bc-c7f5-4f9b-8585-8717ea1a63d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1625390028 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_kmac_err_chk.1625390028
Directory /workspace/35.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/24.rom_ctrl_kmac_err_chk.1743834131
Short name T140
Test name
Test status
Simulation time 3269071883 ps
CPU time 28.48 seconds
Started Mar 14 01:17:37 PM PDT 24
Finished Mar 14 01:18:06 PM PDT 24
Peak memory 211580 kb
Host smart-b7e530b2-eeab-4dee-a58c-d70929f3c5cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1743834131 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_kmac_err_chk.1743834131
Directory /workspace/24.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/34.rom_ctrl_kmac_err_chk.3249250393
Short name T25
Test name
Test status
Simulation time 40944773220 ps
CPU time 26.26 seconds
Started Mar 14 01:17:51 PM PDT 24
Finished Mar 14 01:18:18 PM PDT 24
Peak memory 212288 kb
Host smart-efc19be0-bc39-4433-8c6e-a960bf2afe2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3249250393 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_kmac_err_chk.3249250393
Directory /workspace/34.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/26.rom_ctrl_corrupt_sig_fatal_chk.1399686286
Short name T29
Test name
Test status
Simulation time 160320195740 ps
CPU time 382.17 seconds
Started Mar 14 01:17:52 PM PDT 24
Finished Mar 14 01:24:14 PM PDT 24
Peak memory 236700 kb
Host smart-ba49e349-1d05-406e-afd0-6aa85114eb3f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1399686286 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_
corrupt_sig_fatal_chk.1399686286
Directory /workspace/26.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_passthru_mem_tl_intg_err.3294228269
Short name T102
Test name
Test status
Simulation time 19464647937 ps
CPU time 70.88 seconds
Started Mar 14 01:14:55 PM PDT 24
Finished Mar 14 01:16:07 PM PDT 24
Peak memory 211344 kb
Host smart-969b047b-3ec3-4e7d-a71c-714d79f0d016
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3294228269 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_pa
ssthru_mem_tl_intg_err.3294228269
Directory /workspace/0.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_intg_err.1461954390
Short name T116
Test name
Test status
Simulation time 2350543091 ps
CPU time 74 seconds
Started Mar 14 01:14:58 PM PDT 24
Finished Mar 14 01:16:12 PM PDT 24
Peak memory 212352 kb
Host smart-a0a48963-c961-43bb-a448-58758d2582e0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1461954390 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_tl_in
tg_err.1461954390
Directory /workspace/0.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_intg_err.2840026370
Short name T119
Test name
Test status
Simulation time 7976025280 ps
CPU time 46.95 seconds
Started Mar 14 01:14:59 PM PDT 24
Finished Mar 14 01:15:46 PM PDT 24
Peak memory 212452 kb
Host smart-ce50ef66-0592-4c26-a2ea-fe1c2954fa2f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2840026370 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_tl_in
tg_err.2840026370
Directory /workspace/1.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/10.rom_ctrl_smoke.565929975
Short name T41
Test name
Test status
Simulation time 20799771933 ps
CPU time 46.62 seconds
Started Mar 14 01:17:19 PM PDT 24
Finished Mar 14 01:18:06 PM PDT 24
Peak memory 213700 kb
Host smart-06089e8c-eeaf-4ebb-a302-4156eff5cf50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=565929975 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_smoke.565929975
Directory /workspace/10.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/41.rom_ctrl_max_throughput_chk.2426430812
Short name T106
Test name
Test status
Simulation time 1774591128 ps
CPU time 14.15 seconds
Started Mar 14 01:18:01 PM PDT 24
Finished Mar 14 01:18:16 PM PDT 24
Peak memory 211080 kb
Host smart-0a6f58a4-53a9-4b2c-9744-f1ee3d2accf5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2426430812 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_max_throughput_chk.2426430812
Directory /workspace/41.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/11.rom_ctrl_stress_all_with_rand_reset.2403252766
Short name T14
Test name
Test status
Simulation time 259063676678 ps
CPU time 2243.09 seconds
Started Mar 14 01:17:19 PM PDT 24
Finished Mar 14 01:54:43 PM PDT 24
Peak memory 239008 kb
Host smart-a380040a-b398-4575-9b9a-b71d09a3dbac
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2403252766 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_stress_all_with_rand_reset.2403252766
Directory /workspace/11.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_aliasing.2807289496
Short name T457
Test name
Test status
Simulation time 2242251539 ps
CPU time 17.03 seconds
Started Mar 14 01:14:58 PM PDT 24
Finished Mar 14 01:15:16 PM PDT 24
Peak memory 211324 kb
Host smart-5c0c6af2-64ff-445d-8f1d-3aae0a9266fe
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2807289496 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_alia
sing.2807289496
Directory /workspace/0.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_bit_bash.3497461674
Short name T463
Test name
Test status
Simulation time 1939680871 ps
CPU time 15.13 seconds
Started Mar 14 01:14:58 PM PDT 24
Finished Mar 14 01:15:13 PM PDT 24
Peak memory 211264 kb
Host smart-ea3198b0-e584-49c2-a56e-a53902b272a9
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3497461674 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_bit_
bash.3497461674
Directory /workspace/0.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_hw_reset.2001778395
Short name T450
Test name
Test status
Simulation time 1255394202 ps
CPU time 15 seconds
Started Mar 14 01:14:50 PM PDT 24
Finished Mar 14 01:15:05 PM PDT 24
Peak memory 211248 kb
Host smart-7e04fa13-8310-477f-9ce1-0700ae7519df
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2001778395 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_hw_r
eset.2001778395
Directory /workspace/0.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_mem_rw_with_rand_reset.2579606309
Short name T433
Test name
Test status
Simulation time 5651193963 ps
CPU time 12.45 seconds
Started Mar 14 01:14:52 PM PDT 24
Finished Mar 14 01:15:05 PM PDT 24
Peak memory 219592 kb
Host smart-3998bf8f-7a75-4ddb-a43c-002adb044b71
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2579606309 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 0.rom_ctrl_csr_mem_rw_with_rand_reset.2579606309
Directory /workspace/0.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_rw.450974091
Short name T455
Test name
Test status
Simulation time 168162883 ps
CPU time 4.19 seconds
Started Mar 14 01:14:54 PM PDT 24
Finished Mar 14 01:14:59 PM PDT 24
Peak memory 211224 kb
Host smart-855bdfec-a6c7-4db0-b4ec-bbbd6021cf51
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=450974091 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_rw.450974091
Directory /workspace/0.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_partial_access.3105686210
Short name T404
Test name
Test status
Simulation time 488211456 ps
CPU time 4.2 seconds
Started Mar 14 01:14:59 PM PDT 24
Finished Mar 14 01:15:04 PM PDT 24
Peak memory 211132 kb
Host smart-6af023cd-dce2-4551-8569-3d874c68e8c7
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3105686210 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctr
l_mem_partial_access.3105686210
Directory /workspace/0.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_walk.1711766569
Short name T438
Test name
Test status
Simulation time 456022844 ps
CPU time 6.34 seconds
Started Mar 14 01:14:52 PM PDT 24
Finished Mar 14 01:14:58 PM PDT 24
Peak memory 211208 kb
Host smart-8d970d1d-87aa-4dfb-a6e4-76497f539a8b
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1711766569 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_mem_walk
.1711766569
Directory /workspace/0.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_same_csr_outstanding.2685617472
Short name T99
Test name
Test status
Simulation time 4198636763 ps
CPU time 14.33 seconds
Started Mar 14 01:14:58 PM PDT 24
Finished Mar 14 01:15:12 PM PDT 24
Peak memory 211348 kb
Host smart-16175fc0-e32c-4aa1-af43-daca4f1b6e50
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2685617472 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_c
trl_same_csr_outstanding.2685617472
Directory /workspace/0.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_errors.1789644021
Short name T411
Test name
Test status
Simulation time 1053427417 ps
CPU time 14.95 seconds
Started Mar 14 01:14:55 PM PDT 24
Finished Mar 14 01:15:10 PM PDT 24
Peak memory 219516 kb
Host smart-efaba7ce-0c24-438e-9a42-79a97aa742f9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1789644021 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_tl_errors.1789644021
Directory /workspace/0.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_aliasing.2936219218
Short name T107
Test name
Test status
Simulation time 347102399 ps
CPU time 4.18 seconds
Started Mar 14 01:14:55 PM PDT 24
Finished Mar 14 01:14:59 PM PDT 24
Peak memory 211220 kb
Host smart-6ce963c8-397d-44e6-9c71-afabdc136925
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2936219218 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_alia
sing.2936219218
Directory /workspace/1.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_bit_bash.2104100717
Short name T445
Test name
Test status
Simulation time 1361836410 ps
CPU time 12.15 seconds
Started Mar 14 01:14:52 PM PDT 24
Finished Mar 14 01:15:05 PM PDT 24
Peak memory 211248 kb
Host smart-e90d0c03-f824-46af-8e7d-71a45697d7da
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2104100717 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_bit_
bash.2104100717
Directory /workspace/1.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_hw_reset.1571609181
Short name T89
Test name
Test status
Simulation time 1704021728 ps
CPU time 15.12 seconds
Started Mar 14 01:14:52 PM PDT 24
Finished Mar 14 01:15:08 PM PDT 24
Peak memory 211292 kb
Host smart-1fe504bc-5b74-484d-a8e4-430de9e110b8
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1571609181 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_hw_r
eset.1571609181
Directory /workspace/1.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_mem_rw_with_rand_reset.258049491
Short name T427
Test name
Test status
Simulation time 244451178 ps
CPU time 5.38 seconds
Started Mar 14 01:14:49 PM PDT 24
Finished Mar 14 01:14:54 PM PDT 24
Peak memory 219472 kb
Host smart-eab217eb-ce34-4871-9526-7b32ef5c4a4f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=258049491 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 1.rom_ctrl_csr_mem_rw_with_rand_reset.258049491
Directory /workspace/1.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_rw.865004165
Short name T446
Test name
Test status
Simulation time 593344678 ps
CPU time 5.77 seconds
Started Mar 14 01:14:56 PM PDT 24
Finished Mar 14 01:15:02 PM PDT 24
Peak memory 211252 kb
Host smart-575055ef-242e-4c53-bdee-0009c19fc320
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=865004165 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_rw.865004165
Directory /workspace/1.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_partial_access.76802475
Short name T454
Test name
Test status
Simulation time 1059207816 ps
CPU time 10.26 seconds
Started Mar 14 01:14:55 PM PDT 24
Finished Mar 14 01:15:06 PM PDT 24
Peak memory 211092 kb
Host smart-c91665ae-c171-4e93-8a43-5426f226d020
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76802475 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_c
trl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_
mem_partial_access.76802475
Directory /workspace/1.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_walk.2229936312
Short name T434
Test name
Test status
Simulation time 2315685814 ps
CPU time 10.87 seconds
Started Mar 14 01:14:52 PM PDT 24
Finished Mar 14 01:15:03 PM PDT 24
Peak memory 211240 kb
Host smart-172ee2ec-2ebd-4788-9da7-01deb4606574
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2229936312 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_mem_walk
.2229936312
Directory /workspace/1.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_passthru_mem_tl_intg_err.1232045901
Short name T109
Test name
Test status
Simulation time 7171381886 ps
CPU time 56.45 seconds
Started Mar 14 01:14:52 PM PDT 24
Finished Mar 14 01:15:49 PM PDT 24
Peak memory 211368 kb
Host smart-aabb647a-5d6a-4133-b32d-dedc779b0bb8
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1232045901 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_pa
ssthru_mem_tl_intg_err.1232045901
Directory /workspace/1.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_same_csr_outstanding.198070201
Short name T101
Test name
Test status
Simulation time 89780329 ps
CPU time 4.21 seconds
Started Mar 14 01:14:54 PM PDT 24
Finished Mar 14 01:14:58 PM PDT 24
Peak memory 211264 kb
Host smart-893d1ab1-118f-461b-8eb0-d481ab5f68b8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=198070201 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ct
rl_same_csr_outstanding.198070201
Directory /workspace/1.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_errors.2336944926
Short name T399
Test name
Test status
Simulation time 956943702 ps
CPU time 12.03 seconds
Started Mar 14 01:14:55 PM PDT 24
Finished Mar 14 01:15:07 PM PDT 24
Peak memory 219516 kb
Host smart-dbfec3d0-cfb4-40a9-a9d7-a8c34a8881ab
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2336944926 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_tl_errors.2336944926
Directory /workspace/1.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_mem_rw_with_rand_reset.1817801209
Short name T423
Test name
Test status
Simulation time 103185404 ps
CPU time 5.77 seconds
Started Mar 14 01:15:17 PM PDT 24
Finished Mar 14 01:15:23 PM PDT 24
Peak memory 216040 kb
Host smart-2eab27d1-0a4f-49e7-b865-99233a15da09
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1817801209 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 10.rom_ctrl_csr_mem_rw_with_rand_reset.1817801209
Directory /workspace/10.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_rw.2059274124
Short name T436
Test name
Test status
Simulation time 1261437735 ps
CPU time 11.24 seconds
Started Mar 14 01:15:18 PM PDT 24
Finished Mar 14 01:15:29 PM PDT 24
Peak memory 211252 kb
Host smart-d0bdf0ad-0d29-4f8e-b4fc-aa9cfca8f9cb
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2059274124 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_csr_rw.2059274124
Directory /workspace/10.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_passthru_mem_tl_intg_err.3113648825
Short name T82
Test name
Test status
Simulation time 20635270656 ps
CPU time 33.85 seconds
Started Mar 14 01:15:18 PM PDT 24
Finished Mar 14 01:15:52 PM PDT 24
Peak memory 211272 kb
Host smart-175ef30e-f985-4cb9-a8ec-c4681ca456b6
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3113648825 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_p
assthru_mem_tl_intg_err.3113648825
Directory /workspace/10.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_same_csr_outstanding.111113869
Short name T398
Test name
Test status
Simulation time 8795831885 ps
CPU time 11.67 seconds
Started Mar 14 01:15:14 PM PDT 24
Finished Mar 14 01:15:26 PM PDT 24
Peak memory 211344 kb
Host smart-7dd40a89-4267-44a7-88eb-1ab35d2bc668
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=111113869 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_c
trl_same_csr_outstanding.111113869
Directory /workspace/10.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_errors.884749473
Short name T378
Test name
Test status
Simulation time 1770665293 ps
CPU time 15.19 seconds
Started Mar 14 01:15:20 PM PDT 24
Finished Mar 14 01:15:35 PM PDT 24
Peak memory 214816 kb
Host smart-33c741bc-8e31-4461-a878-f2fb26f67a13
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=884749473 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_tl_errors.884749473
Directory /workspace/10.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_intg_err.552099239
Short name T400
Test name
Test status
Simulation time 326824027 ps
CPU time 68.91 seconds
Started Mar 14 01:15:18 PM PDT 24
Finished Mar 14 01:16:27 PM PDT 24
Peak memory 211188 kb
Host smart-3df589ec-12b4-490d-bf18-f274180e31a1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=552099239 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_tl_in
tg_err.552099239
Directory /workspace/10.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_mem_rw_with_rand_reset.1663312360
Short name T372
Test name
Test status
Simulation time 3039716446 ps
CPU time 13.84 seconds
Started Mar 14 01:15:16 PM PDT 24
Finished Mar 14 01:15:30 PM PDT 24
Peak memory 219552 kb
Host smart-f7416c3b-eeec-4632-a41e-0eaabd0ca031
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1663312360 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 11.rom_ctrl_csr_mem_rw_with_rand_reset.1663312360
Directory /workspace/11.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_rw.1371576695
Short name T408
Test name
Test status
Simulation time 2629446266 ps
CPU time 8.57 seconds
Started Mar 14 01:15:17 PM PDT 24
Finished Mar 14 01:15:26 PM PDT 24
Peak memory 218952 kb
Host smart-f18f7f24-b92f-4955-99f6-d615062857e7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1371576695 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_csr_rw.1371576695
Directory /workspace/11.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_passthru_mem_tl_intg_err.4225672462
Short name T413
Test name
Test status
Simulation time 19070046907 ps
CPU time 47.8 seconds
Started Mar 14 01:15:18 PM PDT 24
Finished Mar 14 01:16:06 PM PDT 24
Peak memory 211280 kb
Host smart-6cd3bcb6-78c0-4a3a-ac2a-6df2ae7050db
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4225672462 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_p
assthru_mem_tl_intg_err.4225672462
Directory /workspace/11.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_same_csr_outstanding.3016746262
Short name T103
Test name
Test status
Simulation time 674186024 ps
CPU time 7.45 seconds
Started Mar 14 01:15:16 PM PDT 24
Finished Mar 14 01:15:24 PM PDT 24
Peak memory 211264 kb
Host smart-595a62d3-7a92-4359-b83f-89de3eba2f6d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3016746262 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_
ctrl_same_csr_outstanding.3016746262
Directory /workspace/11.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_errors.1479618660
Short name T466
Test name
Test status
Simulation time 7606055716 ps
CPU time 18.03 seconds
Started Mar 14 01:15:17 PM PDT 24
Finished Mar 14 01:15:36 PM PDT 24
Peak memory 219572 kb
Host smart-9fd25a5f-8cd3-47b9-8df5-eef99d93eeb3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1479618660 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_tl_errors.1479618660
Directory /workspace/11.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_mem_rw_with_rand_reset.2796635100
Short name T379
Test name
Test status
Simulation time 392506561 ps
CPU time 4.84 seconds
Started Mar 14 01:15:17 PM PDT 24
Finished Mar 14 01:15:22 PM PDT 24
Peak memory 219496 kb
Host smart-1efd78e5-2b4e-49d5-a955-08c5f2e14b5d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2796635100 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 12.rom_ctrl_csr_mem_rw_with_rand_reset.2796635100
Directory /workspace/12.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_rw.850953601
Short name T420
Test name
Test status
Simulation time 5782016030 ps
CPU time 10.29 seconds
Started Mar 14 01:15:20 PM PDT 24
Finished Mar 14 01:15:30 PM PDT 24
Peak memory 211204 kb
Host smart-a16868e1-a014-4dab-910c-e3965bd5731e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=850953601 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_csr_rw.850953601
Directory /workspace/12.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_passthru_mem_tl_intg_err.1977376583
Short name T73
Test name
Test status
Simulation time 6723811828 ps
CPU time 57.03 seconds
Started Mar 14 01:15:14 PM PDT 24
Finished Mar 14 01:16:11 PM PDT 24
Peak memory 211296 kb
Host smart-d1e835af-67aa-4892-9686-2fd7dbea5d9e
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1977376583 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_p
assthru_mem_tl_intg_err.1977376583
Directory /workspace/12.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_same_csr_outstanding.3021457376
Short name T397
Test name
Test status
Simulation time 12273050256 ps
CPU time 16.32 seconds
Started Mar 14 01:15:19 PM PDT 24
Finished Mar 14 01:15:36 PM PDT 24
Peak memory 211396 kb
Host smart-c41f9340-0268-4678-b150-f5d73e774804
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3021457376 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_
ctrl_same_csr_outstanding.3021457376
Directory /workspace/12.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_errors.828963433
Short name T369
Test name
Test status
Simulation time 464213541 ps
CPU time 11.16 seconds
Started Mar 14 01:15:18 PM PDT 24
Finished Mar 14 01:15:29 PM PDT 24
Peak memory 215716 kb
Host smart-88f95ec0-aa74-4bb8-9cde-29e798cad156
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=828963433 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_tl_errors.828963433
Directory /workspace/12.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_intg_err.1248901327
Short name T117
Test name
Test status
Simulation time 2366242408 ps
CPU time 79.58 seconds
Started Mar 14 01:15:18 PM PDT 24
Finished Mar 14 01:16:38 PM PDT 24
Peak memory 212256 kb
Host smart-9ba40025-5da9-44d2-933d-d73fe2f1077b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1248901327 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_tl_i
ntg_err.1248901327
Directory /workspace/12.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_mem_rw_with_rand_reset.2282034200
Short name T447
Test name
Test status
Simulation time 5772752654 ps
CPU time 12.87 seconds
Started Mar 14 01:15:18 PM PDT 24
Finished Mar 14 01:15:31 PM PDT 24
Peak memory 219520 kb
Host smart-6d85cda9-0903-4542-8bfa-ae377263b55b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2282034200 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 13.rom_ctrl_csr_mem_rw_with_rand_reset.2282034200
Directory /workspace/13.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_rw.3042255892
Short name T462
Test name
Test status
Simulation time 695180853 ps
CPU time 8.32 seconds
Started Mar 14 01:15:18 PM PDT 24
Finished Mar 14 01:15:26 PM PDT 24
Peak memory 211264 kb
Host smart-77412f96-2497-4d0d-9009-bb75ef94e869
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3042255892 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_csr_rw.3042255892
Directory /workspace/13.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_passthru_mem_tl_intg_err.4003737699
Short name T387
Test name
Test status
Simulation time 1440048064 ps
CPU time 18.75 seconds
Started Mar 14 01:15:20 PM PDT 24
Finished Mar 14 01:15:39 PM PDT 24
Peak memory 210512 kb
Host smart-46f202cc-7eb4-4c04-8a06-aed15701a701
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4003737699 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_p
assthru_mem_tl_intg_err.4003737699
Directory /workspace/13.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_same_csr_outstanding.3137623535
Short name T448
Test name
Test status
Simulation time 2044729339 ps
CPU time 15.92 seconds
Started Mar 14 01:15:17 PM PDT 24
Finished Mar 14 01:15:34 PM PDT 24
Peak memory 211224 kb
Host smart-13c73d83-d2e6-4fa1-8e6f-27ece9b577d8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3137623535 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_
ctrl_same_csr_outstanding.3137623535
Directory /workspace/13.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_errors.1533432224
Short name T425
Test name
Test status
Simulation time 1918995334 ps
CPU time 18.47 seconds
Started Mar 14 01:15:19 PM PDT 24
Finished Mar 14 01:15:38 PM PDT 24
Peak memory 215692 kb
Host smart-077019a5-849d-4cfa-a6bf-6c765381221a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1533432224 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_tl_errors.1533432224
Directory /workspace/13.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_intg_err.1617818761
Short name T57
Test name
Test status
Simulation time 6562989621 ps
CPU time 43.94 seconds
Started Mar 14 01:15:17 PM PDT 24
Finished Mar 14 01:16:02 PM PDT 24
Peak memory 212008 kb
Host smart-e43d0ba1-1c12-44fd-b9d5-b7f642bf9837
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1617818761 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_tl_i
ntg_err.1617818761
Directory /workspace/13.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_mem_rw_with_rand_reset.1374837488
Short name T374
Test name
Test status
Simulation time 2517724781 ps
CPU time 11.74 seconds
Started Mar 14 01:15:32 PM PDT 24
Finished Mar 14 01:15:44 PM PDT 24
Peak memory 219564 kb
Host smart-d9e5bce8-2b0e-42f9-9a32-01757be028ae
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1374837488 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 14.rom_ctrl_csr_mem_rw_with_rand_reset.1374837488
Directory /workspace/14.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_rw.2946039642
Short name T381
Test name
Test status
Simulation time 2057292505 ps
CPU time 9.99 seconds
Started Mar 14 01:15:17 PM PDT 24
Finished Mar 14 01:15:27 PM PDT 24
Peak memory 211252 kb
Host smart-dc2105ac-cad9-4c5b-9769-d0832300d392
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2946039642 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_csr_rw.2946039642
Directory /workspace/14.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_passthru_mem_tl_intg_err.1544757951
Short name T435
Test name
Test status
Simulation time 3018515151 ps
CPU time 37.74 seconds
Started Mar 14 01:15:16 PM PDT 24
Finished Mar 14 01:15:54 PM PDT 24
Peak memory 217632 kb
Host smart-b6605ea3-b732-41d3-8adc-e93cf45ca27e
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1544757951 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_p
assthru_mem_tl_intg_err.1544757951
Directory /workspace/14.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_same_csr_outstanding.2772153040
Short name T443
Test name
Test status
Simulation time 3867116250 ps
CPU time 9.67 seconds
Started Mar 14 01:15:17 PM PDT 24
Finished Mar 14 01:15:28 PM PDT 24
Peak memory 211356 kb
Host smart-edc45a8c-3f0f-4998-9721-84baa2c1f759
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2772153040 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_
ctrl_same_csr_outstanding.2772153040
Directory /workspace/14.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_errors.1838964353
Short name T409
Test name
Test status
Simulation time 6470860268 ps
CPU time 15.9 seconds
Started Mar 14 01:15:18 PM PDT 24
Finished Mar 14 01:15:34 PM PDT 24
Peak memory 219596 kb
Host smart-37365605-a5c5-4b19-a46c-919612344e13
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1838964353 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_tl_errors.1838964353
Directory /workspace/14.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_intg_err.2563979262
Short name T123
Test name
Test status
Simulation time 1394879731 ps
CPU time 43.94 seconds
Started Mar 14 01:15:13 PM PDT 24
Finished Mar 14 01:15:57 PM PDT 24
Peak memory 211720 kb
Host smart-520eaf1c-9875-4be6-b301-5a8ef0b41450
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2563979262 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_tl_i
ntg_err.2563979262
Directory /workspace/14.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_mem_rw_with_rand_reset.3600329492
Short name T430
Test name
Test status
Simulation time 6659410328 ps
CPU time 14.7 seconds
Started Mar 14 01:15:32 PM PDT 24
Finished Mar 14 01:15:47 PM PDT 24
Peak memory 219552 kb
Host smart-bf6b422e-0d18-4979-bf1f-570d4ba82f47
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3600329492 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 15.rom_ctrl_csr_mem_rw_with_rand_reset.3600329492
Directory /workspace/15.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_rw.550616756
Short name T67
Test name
Test status
Simulation time 1992469943 ps
CPU time 15.79 seconds
Started Mar 14 01:15:34 PM PDT 24
Finished Mar 14 01:15:50 PM PDT 24
Peak memory 211276 kb
Host smart-a66aab5e-ceb2-4eb7-af24-3f275c6ff2a8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=550616756 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_csr_rw.550616756
Directory /workspace/15.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_passthru_mem_tl_intg_err.3728792744
Short name T85
Test name
Test status
Simulation time 55975290276 ps
CPU time 90.55 seconds
Started Mar 14 01:15:34 PM PDT 24
Finished Mar 14 01:17:05 PM PDT 24
Peak memory 211336 kb
Host smart-c8ec06a2-da64-43da-af8a-52a47d77f83c
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3728792744 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_p
assthru_mem_tl_intg_err.3728792744
Directory /workspace/15.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_same_csr_outstanding.1944423135
Short name T74
Test name
Test status
Simulation time 1125953666 ps
CPU time 10.81 seconds
Started Mar 14 01:15:31 PM PDT 24
Finished Mar 14 01:15:42 PM PDT 24
Peak memory 211248 kb
Host smart-68174d4b-2731-452e-b696-5b05396ce120
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1944423135 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_
ctrl_same_csr_outstanding.1944423135
Directory /workspace/15.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_errors.62134410
Short name T380
Test name
Test status
Simulation time 3652610117 ps
CPU time 18.18 seconds
Started Mar 14 01:15:32 PM PDT 24
Finished Mar 14 01:15:50 PM PDT 24
Peak memory 219452 kb
Host smart-1e1a463c-5f8c-4301-81c9-d009adda5860
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=62134410 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_tl_errors.62134410
Directory /workspace/15.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_intg_err.3620055260
Short name T417
Test name
Test status
Simulation time 671374220 ps
CPU time 38.92 seconds
Started Mar 14 01:15:31 PM PDT 24
Finished Mar 14 01:16:10 PM PDT 24
Peak memory 211264 kb
Host smart-8ed7dd79-365b-45c3-9294-ea8a3a151d6c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3620055260 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_tl_i
ntg_err.3620055260
Directory /workspace/15.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_mem_rw_with_rand_reset.830189929
Short name T367
Test name
Test status
Simulation time 2070050556 ps
CPU time 15.74 seconds
Started Mar 14 01:15:38 PM PDT 24
Finished Mar 14 01:15:54 PM PDT 24
Peak memory 219476 kb
Host smart-abee09c9-eca0-4dca-9e57-bafc37f0725e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=830189929 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 16.rom_ctrl_csr_mem_rw_with_rand_reset.830189929
Directory /workspace/16.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_rw.3919858096
Short name T389
Test name
Test status
Simulation time 88937223 ps
CPU time 4.25 seconds
Started Mar 14 01:15:34 PM PDT 24
Finished Mar 14 01:15:38 PM PDT 24
Peak memory 211180 kb
Host smart-ec8fc587-ec8b-4363-b57b-d9fc336afe68
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3919858096 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_csr_rw.3919858096
Directory /workspace/16.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_passthru_mem_tl_intg_err.4031610115
Short name T84
Test name
Test status
Simulation time 17891140870 ps
CPU time 44.37 seconds
Started Mar 14 01:15:32 PM PDT 24
Finished Mar 14 01:16:16 PM PDT 24
Peak memory 211328 kb
Host smart-de322344-98d4-4304-ad33-7bcd77e6c6da
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4031610115 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_p
assthru_mem_tl_intg_err.4031610115
Directory /workspace/16.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_same_csr_outstanding.1263866091
Short name T396
Test name
Test status
Simulation time 385681544 ps
CPU time 6.2 seconds
Started Mar 14 01:15:36 PM PDT 24
Finished Mar 14 01:15:42 PM PDT 24
Peak memory 211248 kb
Host smart-80fbe7c6-00e0-41d3-8f8d-ec3216849909
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1263866091 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_
ctrl_same_csr_outstanding.1263866091
Directory /workspace/16.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_errors.1236564439
Short name T393
Test name
Test status
Simulation time 1919416870 ps
CPU time 18.25 seconds
Started Mar 14 01:15:36 PM PDT 24
Finished Mar 14 01:15:55 PM PDT 24
Peak memory 219540 kb
Host smart-f825ffff-bf6c-45ec-9055-56711a7fba36
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1236564439 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_tl_errors.1236564439
Directory /workspace/16.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_intg_err.3853243009
Short name T386
Test name
Test status
Simulation time 1474213027 ps
CPU time 43.47 seconds
Started Mar 14 01:15:31 PM PDT 24
Finished Mar 14 01:16:14 PM PDT 24
Peak memory 212040 kb
Host smart-ca70f592-f738-4932-9b2b-9f59b33bf623
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3853243009 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_tl_i
ntg_err.3853243009
Directory /workspace/16.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_mem_rw_with_rand_reset.216656795
Short name T428
Test name
Test status
Simulation time 546677052 ps
CPU time 8.27 seconds
Started Mar 14 01:15:36 PM PDT 24
Finished Mar 14 01:15:44 PM PDT 24
Peak memory 219484 kb
Host smart-916b02b3-0359-49c7-91b4-a1ba5285e917
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=216656795 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 17.rom_ctrl_csr_mem_rw_with_rand_reset.216656795
Directory /workspace/17.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_rw.5707714
Short name T68
Test name
Test status
Simulation time 1949544688 ps
CPU time 14.97 seconds
Started Mar 14 01:15:31 PM PDT 24
Finished Mar 14 01:15:46 PM PDT 24
Peak memory 211248 kb
Host smart-c0b6025c-2ff2-413b-8e85-a0832e86b2a8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=5707714 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_csr_rw.5707714
Directory /workspace/17.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_passthru_mem_tl_intg_err.3363248691
Short name T88
Test name
Test status
Simulation time 8641363547 ps
CPU time 40.17 seconds
Started Mar 14 01:15:32 PM PDT 24
Finished Mar 14 01:16:12 PM PDT 24
Peak memory 211304 kb
Host smart-237b138c-dbfa-49ba-81c7-81faf643e559
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3363248691 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_p
assthru_mem_tl_intg_err.3363248691
Directory /workspace/17.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_same_csr_outstanding.1886710993
Short name T453
Test name
Test status
Simulation time 1508444581 ps
CPU time 14.1 seconds
Started Mar 14 01:15:37 PM PDT 24
Finished Mar 14 01:15:51 PM PDT 24
Peak memory 210956 kb
Host smart-73e16e49-39ba-41a6-8928-80035fc71a55
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1886710993 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_
ctrl_same_csr_outstanding.1886710993
Directory /workspace/17.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_errors.3724029201
Short name T384
Test name
Test status
Simulation time 3416511672 ps
CPU time 11.51 seconds
Started Mar 14 01:15:31 PM PDT 24
Finished Mar 14 01:15:43 PM PDT 24
Peak memory 219608 kb
Host smart-79433d82-bdf1-48a8-9a07-1d0b6941eb72
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3724029201 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_tl_errors.3724029201
Directory /workspace/17.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_intg_err.3225594475
Short name T391
Test name
Test status
Simulation time 3016957308 ps
CPU time 35.75 seconds
Started Mar 14 01:15:37 PM PDT 24
Finished Mar 14 01:16:12 PM PDT 24
Peak memory 211060 kb
Host smart-19899857-ff4c-40f5-881e-def3cf19d457
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3225594475 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_tl_i
ntg_err.3225594475
Directory /workspace/17.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_mem_rw_with_rand_reset.3267135477
Short name T366
Test name
Test status
Simulation time 2582724384 ps
CPU time 12.28 seconds
Started Mar 14 01:15:32 PM PDT 24
Finished Mar 14 01:15:45 PM PDT 24
Peak memory 212788 kb
Host smart-063bceae-d246-4b83-bedd-055a2b5f6b63
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3267135477 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 18.rom_ctrl_csr_mem_rw_with_rand_reset.3267135477
Directory /workspace/18.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_rw.2343589680
Short name T108
Test name
Test status
Simulation time 3679421168 ps
CPU time 9.09 seconds
Started Mar 14 01:15:32 PM PDT 24
Finished Mar 14 01:15:42 PM PDT 24
Peak memory 211316 kb
Host smart-e67d6d43-cfa8-4866-9184-5e4e25dcc2c9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2343589680 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_csr_rw.2343589680
Directory /workspace/18.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_passthru_mem_tl_intg_err.1790892973
Short name T69
Test name
Test status
Simulation time 13160528553 ps
CPU time 66.99 seconds
Started Mar 14 01:15:30 PM PDT 24
Finished Mar 14 01:16:38 PM PDT 24
Peak memory 211316 kb
Host smart-dfd996ed-baa4-4ce1-a568-7ca21508755a
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1790892973 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_p
assthru_mem_tl_intg_err.1790892973
Directory /workspace/18.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_same_csr_outstanding.1234925459
Short name T442
Test name
Test status
Simulation time 683900923 ps
CPU time 8.38 seconds
Started Mar 14 01:15:32 PM PDT 24
Finished Mar 14 01:15:40 PM PDT 24
Peak memory 211216 kb
Host smart-6b0bf89f-575a-43c1-9d73-6b45729b7b48
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1234925459 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_
ctrl_same_csr_outstanding.1234925459
Directory /workspace/18.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_errors.1977097294
Short name T414
Test name
Test status
Simulation time 4148066593 ps
CPU time 13.69 seconds
Started Mar 14 01:15:31 PM PDT 24
Finished Mar 14 01:15:45 PM PDT 24
Peak memory 219632 kb
Host smart-a0d83e47-1849-49ae-9502-a9b803382b7f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1977097294 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_tl_errors.1977097294
Directory /workspace/18.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_intg_err.1085759311
Short name T118
Test name
Test status
Simulation time 1568831265 ps
CPU time 43.96 seconds
Started Mar 14 01:15:36 PM PDT 24
Finished Mar 14 01:16:20 PM PDT 24
Peak memory 211976 kb
Host smart-07cd9e24-b046-45e1-8fbb-21c976bd9886
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1085759311 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_tl_i
ntg_err.1085759311
Directory /workspace/18.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_mem_rw_with_rand_reset.2081614350
Short name T376
Test name
Test status
Simulation time 5764641831 ps
CPU time 14.26 seconds
Started Mar 14 01:15:31 PM PDT 24
Finished Mar 14 01:15:46 PM PDT 24
Peak memory 219560 kb
Host smart-b8abdb61-a3a9-4a64-b01a-ecb94fced57b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2081614350 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 19.rom_ctrl_csr_mem_rw_with_rand_reset.2081614350
Directory /workspace/19.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_rw.1139550177
Short name T465
Test name
Test status
Simulation time 8701403869 ps
CPU time 12.07 seconds
Started Mar 14 01:15:32 PM PDT 24
Finished Mar 14 01:15:44 PM PDT 24
Peak memory 211320 kb
Host smart-6a4a5805-85ba-4791-a64a-e17d501dc59f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1139550177 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_csr_rw.1139550177
Directory /workspace/19.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_passthru_mem_tl_intg_err.941573651
Short name T87
Test name
Test status
Simulation time 22560739866 ps
CPU time 50.57 seconds
Started Mar 14 01:15:38 PM PDT 24
Finished Mar 14 01:16:29 PM PDT 24
Peak memory 211340 kb
Host smart-606e4946-430a-4269-9d63-44e5fa521461
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=941573651 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_pa
ssthru_mem_tl_intg_err.941573651
Directory /workspace/19.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_same_csr_outstanding.4108576239
Short name T429
Test name
Test status
Simulation time 13400059340 ps
CPU time 10.33 seconds
Started Mar 14 01:15:33 PM PDT 24
Finished Mar 14 01:15:43 PM PDT 24
Peak memory 211328 kb
Host smart-a6baca47-acc8-492b-9bd5-b687c3aedb52
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4108576239 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_
ctrl_same_csr_outstanding.4108576239
Directory /workspace/19.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_errors.371992029
Short name T373
Test name
Test status
Simulation time 1673419516 ps
CPU time 16.06 seconds
Started Mar 14 01:15:35 PM PDT 24
Finished Mar 14 01:15:52 PM PDT 24
Peak memory 215488 kb
Host smart-a8a77446-9723-49a6-b0aa-f4b891ce0e67
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=371992029 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_tl_errors.371992029
Directory /workspace/19.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_aliasing.334570255
Short name T452
Test name
Test status
Simulation time 4767602225 ps
CPU time 11.06 seconds
Started Mar 14 01:15:03 PM PDT 24
Finished Mar 14 01:15:14 PM PDT 24
Peak memory 211320 kb
Host smart-b32e1238-a338-4a6d-988f-2d810eb226c0
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=334570255 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_alias
ing.334570255
Directory /workspace/2.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_bit_bash.3051120695
Short name T441
Test name
Test status
Simulation time 1483975445 ps
CPU time 12.63 seconds
Started Mar 14 01:15:01 PM PDT 24
Finished Mar 14 01:15:14 PM PDT 24
Peak memory 211248 kb
Host smart-18f754f7-924b-47e2-a7be-2e730c72b2c9
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3051120695 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_bit_
bash.3051120695
Directory /workspace/2.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_hw_reset.3236797439
Short name T458
Test name
Test status
Simulation time 354726586 ps
CPU time 5.82 seconds
Started Mar 14 01:14:55 PM PDT 24
Finished Mar 14 01:15:00 PM PDT 24
Peak memory 211228 kb
Host smart-1b20b862-8c64-4775-a3d5-04b6fa9966fd
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3236797439 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_hw_r
eset.3236797439
Directory /workspace/2.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_mem_rw_with_rand_reset.2533160014
Short name T419
Test name
Test status
Simulation time 1653609362 ps
CPU time 14.26 seconds
Started Mar 14 01:15:00 PM PDT 24
Finished Mar 14 01:15:15 PM PDT 24
Peak memory 219504 kb
Host smart-1ae23a02-84c6-4e0c-86da-70a2ae4ef446
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2533160014 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 2.rom_ctrl_csr_mem_rw_with_rand_reset.2533160014
Directory /workspace/2.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_rw.3715747676
Short name T100
Test name
Test status
Simulation time 1037495873 ps
CPU time 4.21 seconds
Started Mar 14 01:15:00 PM PDT 24
Finished Mar 14 01:15:04 PM PDT 24
Peak memory 211264 kb
Host smart-13fb186a-948a-4fea-9b81-9d86f592dfc3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3715747676 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_rw.3715747676
Directory /workspace/2.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_partial_access.1504963680
Short name T421
Test name
Test status
Simulation time 1415984221 ps
CPU time 6.94 seconds
Started Mar 14 01:14:51 PM PDT 24
Finished Mar 14 01:14:59 PM PDT 24
Peak memory 211104 kb
Host smart-d7d958e1-ff77-4927-a6f0-71ea18465c3c
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1504963680 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctr
l_mem_partial_access.1504963680
Directory /workspace/2.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_walk.2597953472
Short name T439
Test name
Test status
Simulation time 1480309022 ps
CPU time 6.6 seconds
Started Mar 14 01:14:53 PM PDT 24
Finished Mar 14 01:15:00 PM PDT 24
Peak memory 211192 kb
Host smart-c3c674ba-c401-4cc5-8e3d-ba4c9a5039e2
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2597953472 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_mem_walk
.2597953472
Directory /workspace/2.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_passthru_mem_tl_intg_err.2130307902
Short name T65
Test name
Test status
Simulation time 10083889495 ps
CPU time 84.08 seconds
Started Mar 14 01:14:55 PM PDT 24
Finished Mar 14 01:16:19 PM PDT 24
Peak memory 211340 kb
Host smart-81c56c39-c21a-4692-a1b8-886815a3609d
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2130307902 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_pa
ssthru_mem_tl_intg_err.2130307902
Directory /workspace/2.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_same_csr_outstanding.4089416758
Short name T98
Test name
Test status
Simulation time 9220757200 ps
CPU time 16.55 seconds
Started Mar 14 01:15:06 PM PDT 24
Finished Mar 14 01:15:23 PM PDT 24
Peak memory 211324 kb
Host smart-2907ec36-3b0e-4a6f-abd4-03913bf0a397
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4089416758 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_c
trl_same_csr_outstanding.4089416758
Directory /workspace/2.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_errors.2710837599
Short name T382
Test name
Test status
Simulation time 1564330650 ps
CPU time 11.32 seconds
Started Mar 14 01:14:49 PM PDT 24
Finished Mar 14 01:15:01 PM PDT 24
Peak memory 219532 kb
Host smart-2ee1dddc-5cf1-4755-a0b3-54ed13918fd0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2710837599 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_tl_errors.2710837599
Directory /workspace/2.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_intg_err.89680543
Short name T124
Test name
Test status
Simulation time 8314117427 ps
CPU time 78.68 seconds
Started Mar 14 01:14:54 PM PDT 24
Finished Mar 14 01:16:12 PM PDT 24
Peak memory 219496 kb
Host smart-049fdd6c-7865-495f-b99f-4c9bed3be7b6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89680543 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_tl_intg
_err.89680543
Directory /workspace/2.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_aliasing.587813799
Short name T437
Test name
Test status
Simulation time 6491475797 ps
CPU time 13.7 seconds
Started Mar 14 01:15:02 PM PDT 24
Finished Mar 14 01:15:17 PM PDT 24
Peak memory 211316 kb
Host smart-d36129d8-6544-470d-a768-6ce05625d1d5
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=587813799 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_alias
ing.587813799
Directory /workspace/3.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_bit_bash.3301604563
Short name T61
Test name
Test status
Simulation time 204866207 ps
CPU time 4.53 seconds
Started Mar 14 01:15:04 PM PDT 24
Finished Mar 14 01:15:08 PM PDT 24
Peak memory 211224 kb
Host smart-02108e70-e4a6-4a41-8d3e-469f1a40ca68
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3301604563 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_bit_
bash.3301604563
Directory /workspace/3.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_hw_reset.795796934
Short name T83
Test name
Test status
Simulation time 6889767896 ps
CPU time 17.15 seconds
Started Mar 14 01:15:01 PM PDT 24
Finished Mar 14 01:15:19 PM PDT 24
Peak memory 211276 kb
Host smart-4de37d52-7f62-4957-8bdb-8c7a8f4c7428
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=795796934 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_hw_re
set.795796934
Directory /workspace/3.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_mem_rw_with_rand_reset.3988347656
Short name T368
Test name
Test status
Simulation time 103299115 ps
CPU time 5.09 seconds
Started Mar 14 01:15:04 PM PDT 24
Finished Mar 14 01:15:09 PM PDT 24
Peak memory 219532 kb
Host smart-f160f671-86a9-4b65-b8e0-79fe148a6f34
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3988347656 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 3.rom_ctrl_csr_mem_rw_with_rand_reset.3988347656
Directory /workspace/3.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_rw.1205380674
Short name T418
Test name
Test status
Simulation time 4474044087 ps
CPU time 10.97 seconds
Started Mar 14 01:15:03 PM PDT 24
Finished Mar 14 01:15:14 PM PDT 24
Peak memory 211344 kb
Host smart-adcebbc5-ffcf-4921-af92-a35b7365f1ce
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1205380674 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_rw.1205380674
Directory /workspace/3.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_partial_access.3595358417
Short name T459
Test name
Test status
Simulation time 3562442474 ps
CPU time 14.15 seconds
Started Mar 14 01:15:05 PM PDT 24
Finished Mar 14 01:15:19 PM PDT 24
Peak memory 211160 kb
Host smart-7d0f053c-42f0-4413-89ed-5f96876938db
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3595358417 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctr
l_mem_partial_access.3595358417
Directory /workspace/3.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_walk.3943585491
Short name T371
Test name
Test status
Simulation time 2716144475 ps
CPU time 12.33 seconds
Started Mar 14 01:15:01 PM PDT 24
Finished Mar 14 01:15:13 PM PDT 24
Peak memory 211220 kb
Host smart-fa85aa0f-55a3-4663-bdf9-8155b03961cf
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3943585491 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_mem_walk
.3943585491
Directory /workspace/3.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_passthru_mem_tl_intg_err.630787112
Short name T431
Test name
Test status
Simulation time 7193330730 ps
CPU time 49.88 seconds
Started Mar 14 01:15:01 PM PDT 24
Finished Mar 14 01:15:52 PM PDT 24
Peak memory 211364 kb
Host smart-18b18670-1a26-4929-9466-afc78875ca17
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=630787112 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_pas
sthru_mem_tl_intg_err.630787112
Directory /workspace/3.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_same_csr_outstanding.3106252969
Short name T410
Test name
Test status
Simulation time 9979122868 ps
CPU time 15.28 seconds
Started Mar 14 01:14:57 PM PDT 24
Finished Mar 14 01:15:13 PM PDT 24
Peak memory 211324 kb
Host smart-f4e458c5-69ef-4427-abc3-87e7b15a447c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3106252969 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_c
trl_same_csr_outstanding.3106252969
Directory /workspace/3.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_errors.3752568281
Short name T370
Test name
Test status
Simulation time 2057964601 ps
CPU time 18.71 seconds
Started Mar 14 01:15:06 PM PDT 24
Finished Mar 14 01:15:25 PM PDT 24
Peak memory 219524 kb
Host smart-63820d1e-80c9-4c79-a02b-6af2d209a0ec
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3752568281 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_tl_errors.3752568281
Directory /workspace/3.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_intg_err.2945820114
Short name T432
Test name
Test status
Simulation time 477096335 ps
CPU time 44.19 seconds
Started Mar 14 01:15:03 PM PDT 24
Finished Mar 14 01:15:48 PM PDT 24
Peak memory 213268 kb
Host smart-362dca5b-fbf3-47c8-be5f-fcfa02c2a397
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2945820114 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_tl_in
tg_err.2945820114
Directory /workspace/3.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_bit_bash.1007970888
Short name T375
Test name
Test status
Simulation time 8380518584 ps
CPU time 16.36 seconds
Started Mar 14 01:15:03 PM PDT 24
Finished Mar 14 01:15:19 PM PDT 24
Peak memory 211316 kb
Host smart-2a5ab8c0-405f-4f09-9c0d-a730893b947e
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1007970888 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_bit_
bash.1007970888
Directory /workspace/4.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_hw_reset.1110542880
Short name T416
Test name
Test status
Simulation time 1070534274 ps
CPU time 11.79 seconds
Started Mar 14 01:15:02 PM PDT 24
Finished Mar 14 01:15:14 PM PDT 24
Peak memory 211156 kb
Host smart-174abf15-ceb3-41e9-a3cd-173eb92f05e9
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1110542880 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_hw_r
eset.1110542880
Directory /workspace/4.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_mem_rw_with_rand_reset.2414882399
Short name T412
Test name
Test status
Simulation time 330483952 ps
CPU time 5.05 seconds
Started Mar 14 01:15:04 PM PDT 24
Finished Mar 14 01:15:09 PM PDT 24
Peak memory 219432 kb
Host smart-1bff89dd-6b94-4d77-bcbf-619b0f3fb7e4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2414882399 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 4.rom_ctrl_csr_mem_rw_with_rand_reset.2414882399
Directory /workspace/4.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_rw.1251612339
Short name T460
Test name
Test status
Simulation time 1446572160 ps
CPU time 12.36 seconds
Started Mar 14 01:15:07 PM PDT 24
Finished Mar 14 01:15:19 PM PDT 24
Peak memory 211272 kb
Host smart-46f75ea5-99b1-42af-b595-660e69bdf967
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1251612339 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_rw.1251612339
Directory /workspace/4.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_partial_access.887519949
Short name T403
Test name
Test status
Simulation time 814752930 ps
CPU time 8.84 seconds
Started Mar 14 01:15:03 PM PDT 24
Finished Mar 14 01:15:12 PM PDT 24
Peak memory 211044 kb
Host smart-8bb5fff0-5363-4c0c-990a-82dfd0b066ae
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=887519949 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl
_mem_partial_access.887519949
Directory /workspace/4.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_walk.2078954763
Short name T461
Test name
Test status
Simulation time 1189270256 ps
CPU time 11.16 seconds
Started Mar 14 01:15:04 PM PDT 24
Finished Mar 14 01:15:15 PM PDT 24
Peak memory 211168 kb
Host smart-a51031e0-f448-459e-b5ba-b4d6bf935d1a
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2078954763 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_mem_walk
.2078954763
Directory /workspace/4.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_passthru_mem_tl_intg_err.3802037367
Short name T86
Test name
Test status
Simulation time 7653883607 ps
CPU time 60.41 seconds
Started Mar 14 01:15:04 PM PDT 24
Finished Mar 14 01:16:05 PM PDT 24
Peak memory 211268 kb
Host smart-05096160-3271-4c90-9e61-41f2f8053d18
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3802037367 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_pa
ssthru_mem_tl_intg_err.3802037367
Directory /workspace/4.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_same_csr_outstanding.1147868118
Short name T422
Test name
Test status
Simulation time 3263033981 ps
CPU time 11.01 seconds
Started Mar 14 01:15:07 PM PDT 24
Finished Mar 14 01:15:18 PM PDT 24
Peak memory 211348 kb
Host smart-874541dd-72eb-4c57-89a8-0df08d00ce66
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1147868118 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_c
trl_same_csr_outstanding.1147868118
Directory /workspace/4.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_errors.53877308
Short name T383
Test name
Test status
Simulation time 1751531113 ps
CPU time 18.5 seconds
Started Mar 14 01:15:04 PM PDT 24
Finished Mar 14 01:15:23 PM PDT 24
Peak memory 216828 kb
Host smart-591def17-bdb5-4845-8a04-0582aa5f3ec0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=53877308 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_tl_errors.53877308
Directory /workspace/4.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_intg_err.2608821630
Short name T122
Test name
Test status
Simulation time 5339665374 ps
CPU time 43.4 seconds
Started Mar 14 01:15:03 PM PDT 24
Finished Mar 14 01:15:47 PM PDT 24
Peak memory 212364 kb
Host smart-9727cfa0-dab1-4584-b97c-8979ddcec868
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2608821630 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_tl_in
tg_err.2608821630
Directory /workspace/4.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_mem_rw_with_rand_reset.2860346492
Short name T377
Test name
Test status
Simulation time 4114709593 ps
CPU time 11.12 seconds
Started Mar 14 01:15:02 PM PDT 24
Finished Mar 14 01:15:14 PM PDT 24
Peak memory 219524 kb
Host smart-b3150ad6-4055-4d91-b304-206133c8742c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2860346492 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 5.rom_ctrl_csr_mem_rw_with_rand_reset.2860346492
Directory /workspace/5.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_rw.3933491623
Short name T81
Test name
Test status
Simulation time 10862084732 ps
CPU time 16.79 seconds
Started Mar 14 01:15:04 PM PDT 24
Finished Mar 14 01:15:21 PM PDT 24
Peak memory 211344 kb
Host smart-aec66396-59e6-49b9-ba4c-b02b8778cecc
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3933491623 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_csr_rw.3933491623
Directory /workspace/5.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_passthru_mem_tl_intg_err.3209182899
Short name T424
Test name
Test status
Simulation time 39174629120 ps
CPU time 92.38 seconds
Started Mar 14 01:15:02 PM PDT 24
Finished Mar 14 01:16:35 PM PDT 24
Peak memory 211344 kb
Host smart-fd1f8c95-53ee-4f06-89f8-a1e6d1ecea74
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3209182899 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_pa
ssthru_mem_tl_intg_err.3209182899
Directory /workspace/5.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_same_csr_outstanding.2995258861
Short name T406
Test name
Test status
Simulation time 2079360356 ps
CPU time 16.09 seconds
Started Mar 14 01:15:04 PM PDT 24
Finished Mar 14 01:15:20 PM PDT 24
Peak memory 211240 kb
Host smart-be895efa-1555-4a0a-b6fa-896a287265a3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2995258861 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_c
trl_same_csr_outstanding.2995258861
Directory /workspace/5.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_errors.2618321573
Short name T456
Test name
Test status
Simulation time 347391246 ps
CPU time 6.66 seconds
Started Mar 14 01:14:59 PM PDT 24
Finished Mar 14 01:15:07 PM PDT 24
Peak memory 219484 kb
Host smart-3beb200f-43a8-4de3-8398-bf6ba5b0de17
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2618321573 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_tl_errors.2618321573
Directory /workspace/5.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_intg_err.429423326
Short name T407
Test name
Test status
Simulation time 4023402836 ps
CPU time 46.18 seconds
Started Mar 14 01:15:04 PM PDT 24
Finished Mar 14 01:15:50 PM PDT 24
Peak memory 212788 kb
Host smart-f044575e-be54-4eb6-a933-a51029a2c9b0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=429423326 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_tl_int
g_err.429423326
Directory /workspace/5.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_mem_rw_with_rand_reset.779171850
Short name T440
Test name
Test status
Simulation time 317429548 ps
CPU time 6.24 seconds
Started Mar 14 01:15:02 PM PDT 24
Finished Mar 14 01:15:08 PM PDT 24
Peak memory 219492 kb
Host smart-26aefc5f-4719-45c1-ab97-42f5664286d2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=779171850 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 6.rom_ctrl_csr_mem_rw_with_rand_reset.779171850
Directory /workspace/6.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_rw.111655649
Short name T385
Test name
Test status
Simulation time 2591617314 ps
CPU time 8.34 seconds
Started Mar 14 01:15:03 PM PDT 24
Finished Mar 14 01:15:11 PM PDT 24
Peak memory 211252 kb
Host smart-660eb50b-5010-4769-bfd5-26508fc97868
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=111655649 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_csr_rw.111655649
Directory /workspace/6.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_passthru_mem_tl_intg_err.823281628
Short name T72
Test name
Test status
Simulation time 1483268664 ps
CPU time 18.58 seconds
Started Mar 14 01:15:02 PM PDT 24
Finished Mar 14 01:15:21 PM PDT 24
Peak memory 211372 kb
Host smart-8c161576-3787-4e15-95ab-117710469721
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=823281628 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_pas
sthru_mem_tl_intg_err.823281628
Directory /workspace/6.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_same_csr_outstanding.3578120627
Short name T60
Test name
Test status
Simulation time 1314202799 ps
CPU time 12.12 seconds
Started Mar 14 01:14:59 PM PDT 24
Finished Mar 14 01:15:13 PM PDT 24
Peak memory 211216 kb
Host smart-7ce0422c-d758-4ea7-8245-dd13fbdae178
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3578120627 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_c
trl_same_csr_outstanding.3578120627
Directory /workspace/6.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_errors.2819234614
Short name T392
Test name
Test status
Simulation time 591861443 ps
CPU time 6.87 seconds
Started Mar 14 01:15:00 PM PDT 24
Finished Mar 14 01:15:07 PM PDT 24
Peak memory 219512 kb
Host smart-1c025970-b7f5-423d-a395-cf3afc5306dc
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2819234614 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_tl_errors.2819234614
Directory /workspace/6.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_intg_err.165429751
Short name T58
Test name
Test status
Simulation time 481711029 ps
CPU time 39.46 seconds
Started Mar 14 01:15:03 PM PDT 24
Finished Mar 14 01:15:43 PM PDT 24
Peak memory 211272 kb
Host smart-94c65dfd-c954-4041-807f-5f4adccc36d6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=165429751 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_tl_int
g_err.165429751
Directory /workspace/6.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_mem_rw_with_rand_reset.915532242
Short name T415
Test name
Test status
Simulation time 1040291770 ps
CPU time 10.95 seconds
Started Mar 14 01:15:17 PM PDT 24
Finished Mar 14 01:15:28 PM PDT 24
Peak memory 219476 kb
Host smart-0d603bb8-edea-4331-a5b4-35e00ef1f811
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=915532242 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 7.rom_ctrl_csr_mem_rw_with_rand_reset.915532242
Directory /workspace/7.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_rw.547459964
Short name T401
Test name
Test status
Simulation time 4797905544 ps
CPU time 10.97 seconds
Started Mar 14 01:15:14 PM PDT 24
Finished Mar 14 01:15:25 PM PDT 24
Peak memory 211300 kb
Host smart-09cef348-d365-4057-9eb5-f218778c611b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=547459964 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_csr_rw.547459964
Directory /workspace/7.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_passthru_mem_tl_intg_err.1147878994
Short name T114
Test name
Test status
Simulation time 49094610638 ps
CPU time 96.27 seconds
Started Mar 14 01:15:04 PM PDT 24
Finished Mar 14 01:16:41 PM PDT 24
Peak memory 211360 kb
Host smart-608ef9c6-41ee-4b47-8086-cf956d34446a
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1147878994 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_pa
ssthru_mem_tl_intg_err.1147878994
Directory /workspace/7.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_same_csr_outstanding.207141502
Short name T390
Test name
Test status
Simulation time 1126097064 ps
CPU time 12.79 seconds
Started Mar 14 01:15:17 PM PDT 24
Finished Mar 14 01:15:30 PM PDT 24
Peak memory 211300 kb
Host smart-b785a24e-70e3-4dcb-8b05-033a93517a99
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=207141502 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ct
rl_same_csr_outstanding.207141502
Directory /workspace/7.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_errors.3996470485
Short name T405
Test name
Test status
Simulation time 4780972159 ps
CPU time 13.18 seconds
Started Mar 14 01:15:03 PM PDT 24
Finished Mar 14 01:15:16 PM PDT 24
Peak memory 214704 kb
Host smart-bb7460a5-9ebd-466e-9614-064eac4f51ef
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3996470485 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_tl_errors.3996470485
Directory /workspace/7.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_intg_err.2225225822
Short name T444
Test name
Test status
Simulation time 166285091 ps
CPU time 36.73 seconds
Started Mar 14 01:15:01 PM PDT 24
Finished Mar 14 01:15:38 PM PDT 24
Peak memory 212180 kb
Host smart-04edc86b-3d61-4a79-abdb-eb339f159b3c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2225225822 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_tl_in
tg_err.2225225822
Directory /workspace/7.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_mem_rw_with_rand_reset.2206879989
Short name T394
Test name
Test status
Simulation time 195630344 ps
CPU time 5.8 seconds
Started Mar 14 01:15:18 PM PDT 24
Finished Mar 14 01:15:24 PM PDT 24
Peak memory 219456 kb
Host smart-3ffaec71-3233-43aa-94f9-a99751bf6bee
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2206879989 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 8.rom_ctrl_csr_mem_rw_with_rand_reset.2206879989
Directory /workspace/8.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_rw.356798705
Short name T451
Test name
Test status
Simulation time 1039386986 ps
CPU time 7.34 seconds
Started Mar 14 01:15:19 PM PDT 24
Finished Mar 14 01:15:26 PM PDT 24
Peak memory 211328 kb
Host smart-9a6e989e-ca52-483b-82f9-ec665f1c7712
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=356798705 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_csr_rw.356798705
Directory /workspace/8.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_passthru_mem_tl_intg_err.3078807196
Short name T426
Test name
Test status
Simulation time 2086771223 ps
CPU time 28.32 seconds
Started Mar 14 01:15:14 PM PDT 24
Finished Mar 14 01:15:43 PM PDT 24
Peak memory 211312 kb
Host smart-b0a450a2-b253-480d-8d24-6b33187145f6
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3078807196 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_pa
ssthru_mem_tl_intg_err.3078807196
Directory /workspace/8.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_same_csr_outstanding.3938133369
Short name T70
Test name
Test status
Simulation time 4259662878 ps
CPU time 12.58 seconds
Started Mar 14 01:15:18 PM PDT 24
Finished Mar 14 01:15:31 PM PDT 24
Peak memory 211288 kb
Host smart-0039a18c-2e02-46b0-be91-d8009c562cc8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3938133369 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_c
trl_same_csr_outstanding.3938133369
Directory /workspace/8.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_errors.1802792717
Short name T388
Test name
Test status
Simulation time 1981950520 ps
CPU time 10.09 seconds
Started Mar 14 01:15:14 PM PDT 24
Finished Mar 14 01:15:24 PM PDT 24
Peak memory 215768 kb
Host smart-42bdf5f4-cae7-40e4-8c46-3004b4afd20a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1802792717 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_tl_errors.1802792717
Directory /workspace/8.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_intg_err.777056836
Short name T59
Test name
Test status
Simulation time 39058802308 ps
CPU time 77.33 seconds
Started Mar 14 01:15:15 PM PDT 24
Finished Mar 14 01:16:32 PM PDT 24
Peak memory 212800 kb
Host smart-df66b27b-9ed5-455b-bffb-76401845aa6c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=777056836 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_tl_int
g_err.777056836
Directory /workspace/8.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_mem_rw_with_rand_reset.311474362
Short name T464
Test name
Test status
Simulation time 2273570590 ps
CPU time 8.11 seconds
Started Mar 14 01:15:19 PM PDT 24
Finished Mar 14 01:15:27 PM PDT 24
Peak memory 219568 kb
Host smart-0c3ecd69-b4b2-4b38-867a-6dcec634ce42
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=311474362 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 9.rom_ctrl_csr_mem_rw_with_rand_reset.311474362
Directory /workspace/9.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_rw.2336723114
Short name T395
Test name
Test status
Simulation time 2475343518 ps
CPU time 11.71 seconds
Started Mar 14 01:15:14 PM PDT 24
Finished Mar 14 01:15:26 PM PDT 24
Peak memory 211304 kb
Host smart-5a9984ef-ea46-4138-ad1c-342de0f0ee2a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2336723114 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_csr_rw.2336723114
Directory /workspace/9.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_passthru_mem_tl_intg_err.4038166378
Short name T449
Test name
Test status
Simulation time 9327891732 ps
CPU time 32.64 seconds
Started Mar 14 01:15:15 PM PDT 24
Finished Mar 14 01:15:48 PM PDT 24
Peak memory 211316 kb
Host smart-5829c11b-7f16-48e5-bd13-79162403b48e
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4038166378 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_pa
ssthru_mem_tl_intg_err.4038166378
Directory /workspace/9.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_same_csr_outstanding.1129449618
Short name T71
Test name
Test status
Simulation time 11303924028 ps
CPU time 17.59 seconds
Started Mar 14 01:15:17 PM PDT 24
Finished Mar 14 01:15:35 PM PDT 24
Peak memory 211312 kb
Host smart-b16d74a2-641a-4497-9280-c287a1fd1ef5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1129449618 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_c
trl_same_csr_outstanding.1129449618
Directory /workspace/9.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_errors.1909495695
Short name T402
Test name
Test status
Simulation time 378052759 ps
CPU time 6.63 seconds
Started Mar 14 01:15:18 PM PDT 24
Finished Mar 14 01:15:25 PM PDT 24
Peak memory 219508 kb
Host smart-31f82151-8e89-4b67-891c-67fe94aa0498
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1909495695 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_tl_errors.1909495695
Directory /workspace/9.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_intg_err.2751498260
Short name T121
Test name
Test status
Simulation time 1460594444 ps
CPU time 38.3 seconds
Started Mar 14 01:15:16 PM PDT 24
Finished Mar 14 01:15:55 PM PDT 24
Peak memory 211148 kb
Host smart-f9d585d8-aa0a-49a8-b8d0-0c02505f5d4a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2751498260 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_tl_in
tg_err.2751498260
Directory /workspace/9.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/0.rom_ctrl_alert_test.720020083
Short name T328
Test name
Test status
Simulation time 86508675 ps
CPU time 4.33 seconds
Started Mar 14 01:17:07 PM PDT 24
Finished Mar 14 01:17:11 PM PDT 24
Peak memory 211128 kb
Host smart-a3170c9c-a028-46d8-b5dd-23d34881ac88
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=720020083 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_alert_test.720020083
Directory /workspace/0.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/0.rom_ctrl_corrupt_sig_fatal_chk.4221765512
Short name T298
Test name
Test status
Simulation time 5929541455 ps
CPU time 110.73 seconds
Started Mar 14 01:17:13 PM PDT 24
Finished Mar 14 01:19:04 PM PDT 24
Peak memory 229644 kb
Host smart-ba2ca6e0-08ba-4a57-b22b-bd25496a6ed8
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4221765512 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_c
orrupt_sig_fatal_chk.4221765512
Directory /workspace/0.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/0.rom_ctrl_kmac_err_chk.1104073756
Short name T263
Test name
Test status
Simulation time 8471389824 ps
CPU time 23.64 seconds
Started Mar 14 01:17:07 PM PDT 24
Finished Mar 14 01:17:31 PM PDT 24
Peak memory 212452 kb
Host smart-f4c6bad6-0454-453c-9cb2-82d65d475228
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1104073756 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_kmac_err_chk.1104073756
Directory /workspace/0.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/0.rom_ctrl_max_throughput_chk.1395806818
Short name T165
Test name
Test status
Simulation time 192372350 ps
CPU time 5.45 seconds
Started Mar 14 01:17:13 PM PDT 24
Finished Mar 14 01:17:19 PM PDT 24
Peak memory 211076 kb
Host smart-a2bb9398-f78f-44be-bf7f-25c15793b45c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1395806818 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_max_throughput_chk.1395806818
Directory /workspace/0.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/0.rom_ctrl_stress_all.2186832651
Short name T199
Test name
Test status
Simulation time 9483442238 ps
CPU time 62.48 seconds
Started Mar 14 01:17:09 PM PDT 24
Finished Mar 14 01:18:11 PM PDT 24
Peak memory 219372 kb
Host smart-87334eed-4cae-4ac3-97c3-a0eb342e9f23
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2186832651 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 0.rom_ctrl_stress_all.2186832651
Directory /workspace/0.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/1.rom_ctrl_alert_test.378478080
Short name T179
Test name
Test status
Simulation time 1506194301 ps
CPU time 8.95 seconds
Started Mar 14 01:17:13 PM PDT 24
Finished Mar 14 01:17:22 PM PDT 24
Peak memory 211044 kb
Host smart-ed8ba633-9410-4ff8-8e0e-1bac825b8e40
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=378478080 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_alert_test.378478080
Directory /workspace/1.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/1.rom_ctrl_corrupt_sig_fatal_chk.427871393
Short name T214
Test name
Test status
Simulation time 5666295941 ps
CPU time 130.36 seconds
Started Mar 14 01:17:09 PM PDT 24
Finished Mar 14 01:19:19 PM PDT 24
Peak memory 230812 kb
Host smart-25ea0e04-0d0c-4ccc-a59c-5651d980aade
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=427871393 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_co
rrupt_sig_fatal_chk.427871393
Directory /workspace/1.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/1.rom_ctrl_kmac_err_chk.2392073307
Short name T226
Test name
Test status
Simulation time 3113080618 ps
CPU time 28.63 seconds
Started Mar 14 01:17:11 PM PDT 24
Finished Mar 14 01:17:39 PM PDT 24
Peak memory 211660 kb
Host smart-a323e0fd-c2c2-43c4-8e47-5940705f72fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2392073307 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_kmac_err_chk.2392073307
Directory /workspace/1.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/1.rom_ctrl_max_throughput_chk.3870635953
Short name T223
Test name
Test status
Simulation time 99295262 ps
CPU time 5.68 seconds
Started Mar 14 01:17:11 PM PDT 24
Finished Mar 14 01:17:17 PM PDT 24
Peak memory 211072 kb
Host smart-d17a87a0-39db-4dfe-abec-026b270073fd
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3870635953 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_max_throughput_chk.3870635953
Directory /workspace/1.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/1.rom_ctrl_sec_cm.3606755111
Short name T38
Test name
Test status
Simulation time 3493439306 ps
CPU time 108.28 seconds
Started Mar 14 01:17:03 PM PDT 24
Finished Mar 14 01:18:51 PM PDT 24
Peak memory 238020 kb
Host smart-f727923a-54ae-4408-8d56-52b2de674609
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3606755111 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_sec_cm.3606755111
Directory /workspace/1.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/1.rom_ctrl_smoke.1000871007
Short name T75
Test name
Test status
Simulation time 2222464787 ps
CPU time 26.06 seconds
Started Mar 14 01:17:06 PM PDT 24
Finished Mar 14 01:17:32 PM PDT 24
Peak memory 212720 kb
Host smart-5abefe25-bf08-4cb4-9542-1e2eeab75dab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1000871007 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_smoke.1000871007
Directory /workspace/1.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/10.rom_ctrl_alert_test.4032083551
Short name T215
Test name
Test status
Simulation time 923817382 ps
CPU time 7.07 seconds
Started Mar 14 01:17:20 PM PDT 24
Finished Mar 14 01:17:27 PM PDT 24
Peak memory 211112 kb
Host smart-b9483409-1631-46ae-95fe-a5db73dbde0c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4032083551 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_alert_test.4032083551
Directory /workspace/10.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/10.rom_ctrl_kmac_err_chk.3942611405
Short name T323
Test name
Test status
Simulation time 1381666637 ps
CPU time 9.31 seconds
Started Mar 14 01:17:10 PM PDT 24
Finished Mar 14 01:17:20 PM PDT 24
Peak memory 211800 kb
Host smart-56fd61ff-4558-41f3-9257-2c4e8a9bbbcc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3942611405 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_kmac_err_chk.3942611405
Directory /workspace/10.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/10.rom_ctrl_max_throughput_chk.1788036901
Short name T127
Test name
Test status
Simulation time 2144697955 ps
CPU time 17.4 seconds
Started Mar 14 01:17:20 PM PDT 24
Finished Mar 14 01:17:38 PM PDT 24
Peak memory 211060 kb
Host smart-6ac44fdb-f718-495b-b252-876bc462db3d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1788036901 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_max_throughput_chk.1788036901
Directory /workspace/10.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/10.rom_ctrl_stress_all.1234174024
Short name T95
Test name
Test status
Simulation time 3100339478 ps
CPU time 20.87 seconds
Started Mar 14 01:17:20 PM PDT 24
Finished Mar 14 01:17:41 PM PDT 24
Peak memory 213008 kb
Host smart-6aa74dc7-c2dc-48ed-ae7f-db859372f7b9
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1234174024 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 10.rom_ctrl_stress_all.1234174024
Directory /workspace/10.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/11.rom_ctrl_alert_test.284281328
Short name T337
Test name
Test status
Simulation time 85476437 ps
CPU time 4.14 seconds
Started Mar 14 01:17:25 PM PDT 24
Finished Mar 14 01:17:29 PM PDT 24
Peak memory 211028 kb
Host smart-3ecb5218-a0b4-4533-a127-46992c4ba5b5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=284281328 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_alert_test.284281328
Directory /workspace/11.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/11.rom_ctrl_corrupt_sig_fatal_chk.1032728443
Short name T193
Test name
Test status
Simulation time 100508538967 ps
CPU time 282.22 seconds
Started Mar 14 01:17:25 PM PDT 24
Finished Mar 14 01:22:07 PM PDT 24
Peak memory 212412 kb
Host smart-f3582638-b98e-4c7d-ada0-05906abb3919
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1032728443 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_
corrupt_sig_fatal_chk.1032728443
Directory /workspace/11.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/11.rom_ctrl_kmac_err_chk.401368072
Short name T325
Test name
Test status
Simulation time 23645144401 ps
CPU time 20.78 seconds
Started Mar 14 01:17:25 PM PDT 24
Finished Mar 14 01:17:46 PM PDT 24
Peak memory 212044 kb
Host smart-090cd53f-0909-4c53-bdb2-61be4c630f40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=401368072 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_kmac_err_chk.401368072
Directory /workspace/11.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/11.rom_ctrl_max_throughput_chk.3808711502
Short name T206
Test name
Test status
Simulation time 15274643775 ps
CPU time 11.99 seconds
Started Mar 14 01:17:19 PM PDT 24
Finished Mar 14 01:17:31 PM PDT 24
Peak memory 211180 kb
Host smart-4a53f7f7-a169-452f-adc7-625eb8e0a276
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3808711502 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_max_throughput_chk.3808711502
Directory /workspace/11.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/11.rom_ctrl_smoke.138254603
Short name T221
Test name
Test status
Simulation time 4538548105 ps
CPU time 26.03 seconds
Started Mar 14 01:17:19 PM PDT 24
Finished Mar 14 01:17:45 PM PDT 24
Peak memory 213568 kb
Host smart-2b9fd1b9-a3a8-4939-9a45-43e569c0f8a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=138254603 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_smoke.138254603
Directory /workspace/11.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/11.rom_ctrl_stress_all.3324441397
Short name T266
Test name
Test status
Simulation time 14212113063 ps
CPU time 34.94 seconds
Started Mar 14 01:17:20 PM PDT 24
Finished Mar 14 01:17:55 PM PDT 24
Peak memory 213872 kb
Host smart-5c1e066b-7518-46bd-9e7a-87c5f50baa56
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3324441397 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 11.rom_ctrl_stress_all.3324441397
Directory /workspace/11.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/12.rom_ctrl_alert_test.4174693252
Short name T97
Test name
Test status
Simulation time 11701592792 ps
CPU time 13.06 seconds
Started Mar 14 01:17:10 PM PDT 24
Finished Mar 14 01:17:23 PM PDT 24
Peak memory 211196 kb
Host smart-153c4c75-2d46-4d3f-82f0-3928a13739f6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4174693252 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_alert_test.4174693252
Directory /workspace/12.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/12.rom_ctrl_corrupt_sig_fatal_chk.845657774
Short name T274
Test name
Test status
Simulation time 46522276235 ps
CPU time 222.74 seconds
Started Mar 14 01:17:19 PM PDT 24
Finished Mar 14 01:21:02 PM PDT 24
Peak memory 235980 kb
Host smart-5358e130-1253-480e-aa61-899c3e9489e1
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=845657774 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_c
orrupt_sig_fatal_chk.845657774
Directory /workspace/12.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/12.rom_ctrl_kmac_err_chk.1704307395
Short name T252
Test name
Test status
Simulation time 6670911144 ps
CPU time 29.02 seconds
Started Mar 14 01:17:24 PM PDT 24
Finished Mar 14 01:17:54 PM PDT 24
Peak memory 211064 kb
Host smart-2cde7f79-86e8-4ff3-94ec-7e642306d94d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1704307395 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_kmac_err_chk.1704307395
Directory /workspace/12.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/12.rom_ctrl_max_throughput_chk.2213865143
Short name T134
Test name
Test status
Simulation time 6502285031 ps
CPU time 15.51 seconds
Started Mar 14 01:17:11 PM PDT 24
Finished Mar 14 01:17:26 PM PDT 24
Peak memory 211160 kb
Host smart-4e4e81f5-d84b-4a73-a95d-87d2f06cf62e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2213865143 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_max_throughput_chk.2213865143
Directory /workspace/12.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/12.rom_ctrl_smoke.3121785815
Short name T178
Test name
Test status
Simulation time 6836342019 ps
CPU time 21.77 seconds
Started Mar 14 01:17:24 PM PDT 24
Finished Mar 14 01:17:46 PM PDT 24
Peak memory 219204 kb
Host smart-fefc1404-213e-4b6b-aaf0-9d52096ee0c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3121785815 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_smoke.3121785815
Directory /workspace/12.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/12.rom_ctrl_stress_all.3863642043
Short name T259
Test name
Test status
Simulation time 16539259963 ps
CPU time 33.78 seconds
Started Mar 14 01:17:25 PM PDT 24
Finished Mar 14 01:17:58 PM PDT 24
Peak memory 219344 kb
Host smart-649e32a3-f5d1-4128-82a9-183de507c822
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3863642043 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 12.rom_ctrl_stress_all.3863642043
Directory /workspace/12.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/12.rom_ctrl_stress_all_with_rand_reset.3844741392
Short name T53
Test name
Test status
Simulation time 146089274029 ps
CPU time 1711.15 seconds
Started Mar 14 01:17:10 PM PDT 24
Finished Mar 14 01:45:42 PM PDT 24
Peak memory 229648 kb
Host smart-084a0fb6-a137-47b2-a1e6-c5b32a5f096c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3844741392 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_stress_all_with_rand_reset.3844741392
Directory /workspace/12.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/13.rom_ctrl_alert_test.2788757643
Short name T92
Test name
Test status
Simulation time 250571302 ps
CPU time 6.14 seconds
Started Mar 14 01:17:21 PM PDT 24
Finished Mar 14 01:17:27 PM PDT 24
Peak memory 211072 kb
Host smart-88f94a57-880b-4950-ad98-8e05ce2aad5d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2788757643 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_alert_test.2788757643
Directory /workspace/13.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/13.rom_ctrl_corrupt_sig_fatal_chk.4214307019
Short name T308
Test name
Test status
Simulation time 54183740694 ps
CPU time 167.17 seconds
Started Mar 14 01:17:28 PM PDT 24
Finished Mar 14 01:20:15 PM PDT 24
Peak memory 212388 kb
Host smart-23a0b3ad-0b85-42a9-a4b2-c30d05d8046c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4214307019 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_
corrupt_sig_fatal_chk.4214307019
Directory /workspace/13.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/13.rom_ctrl_kmac_err_chk.3436565407
Short name T217
Test name
Test status
Simulation time 3803754913 ps
CPU time 28.5 seconds
Started Mar 14 01:17:23 PM PDT 24
Finished Mar 14 01:17:51 PM PDT 24
Peak memory 212344 kb
Host smart-780d7670-1a96-4464-b8bf-66feddfffe49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3436565407 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_kmac_err_chk.3436565407
Directory /workspace/13.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/13.rom_ctrl_max_throughput_chk.2108446074
Short name T166
Test name
Test status
Simulation time 4793033292 ps
CPU time 18.42 seconds
Started Mar 14 01:17:21 PM PDT 24
Finished Mar 14 01:17:40 PM PDT 24
Peak memory 211128 kb
Host smart-b15def36-7039-4783-af9a-b4df7cec3148
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2108446074 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_max_throughput_chk.2108446074
Directory /workspace/13.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/13.rom_ctrl_smoke.2587572310
Short name T335
Test name
Test status
Simulation time 24791201032 ps
CPU time 35.1 seconds
Started Mar 14 01:17:20 PM PDT 24
Finished Mar 14 01:17:55 PM PDT 24
Peak memory 213988 kb
Host smart-056df59e-9807-49c5-82de-4ed99b151a07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2587572310 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_smoke.2587572310
Directory /workspace/13.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/13.rom_ctrl_stress_all.2982389655
Short name T185
Test name
Test status
Simulation time 25248651884 ps
CPU time 52.27 seconds
Started Mar 14 01:17:28 PM PDT 24
Finished Mar 14 01:18:20 PM PDT 24
Peak memory 215888 kb
Host smart-4b32d952-fd6a-43d7-b2dc-ce3bcb9b66b1
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2982389655 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 13.rom_ctrl_stress_all.2982389655
Directory /workspace/13.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/14.rom_ctrl_corrupt_sig_fatal_chk.1888156905
Short name T291
Test name
Test status
Simulation time 8287464946 ps
CPU time 162.16 seconds
Started Mar 14 01:17:20 PM PDT 24
Finished Mar 14 01:20:02 PM PDT 24
Peak memory 228496 kb
Host smart-141c8ece-94f2-4574-8e80-b0389d0092e0
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1888156905 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_
corrupt_sig_fatal_chk.1888156905
Directory /workspace/14.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/14.rom_ctrl_kmac_err_chk.3747373652
Short name T245
Test name
Test status
Simulation time 9087174065 ps
CPU time 20.69 seconds
Started Mar 14 01:17:20 PM PDT 24
Finished Mar 14 01:17:41 PM PDT 24
Peak memory 211920 kb
Host smart-f602aca3-adf6-4dba-9260-e4ecc4223dd2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3747373652 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_kmac_err_chk.3747373652
Directory /workspace/14.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/14.rom_ctrl_max_throughput_chk.3906624100
Short name T218
Test name
Test status
Simulation time 7888852065 ps
CPU time 16.34 seconds
Started Mar 14 01:17:20 PM PDT 24
Finished Mar 14 01:17:36 PM PDT 24
Peak memory 211224 kb
Host smart-73a1780f-fd1c-4526-85b6-d0aec0f56392
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3906624100 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_max_throughput_chk.3906624100
Directory /workspace/14.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/14.rom_ctrl_smoke.1951700899
Short name T339
Test name
Test status
Simulation time 7366339273 ps
CPU time 36.95 seconds
Started Mar 14 01:17:26 PM PDT 24
Finished Mar 14 01:18:03 PM PDT 24
Peak memory 213708 kb
Host smart-6febb238-fba2-4ed3-88e0-1a666b59cec9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1951700899 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_smoke.1951700899
Directory /workspace/14.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/14.rom_ctrl_stress_all.2184684276
Short name T351
Test name
Test status
Simulation time 4190089318 ps
CPU time 51.44 seconds
Started Mar 14 01:17:21 PM PDT 24
Finished Mar 14 01:18:13 PM PDT 24
Peak memory 217000 kb
Host smart-5b787bad-6fc1-4bc1-87f5-7331a3b43564
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2184684276 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 14.rom_ctrl_stress_all.2184684276
Directory /workspace/14.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/15.rom_ctrl_alert_test.3193795520
Short name T282
Test name
Test status
Simulation time 85819682 ps
CPU time 4.41 seconds
Started Mar 14 01:17:37 PM PDT 24
Finished Mar 14 01:17:41 PM PDT 24
Peak memory 211044 kb
Host smart-03fe29d2-dd1e-46bb-aa70-a778140db5f0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3193795520 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_alert_test.3193795520
Directory /workspace/15.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/15.rom_ctrl_corrupt_sig_fatal_chk.1889309826
Short name T303
Test name
Test status
Simulation time 439523145026 ps
CPU time 424.79 seconds
Started Mar 14 01:17:35 PM PDT 24
Finished Mar 14 01:24:40 PM PDT 24
Peak memory 228452 kb
Host smart-7aafbdc0-1e77-4f23-a795-4ae869356ae0
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1889309826 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_
corrupt_sig_fatal_chk.1889309826
Directory /workspace/15.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/15.rom_ctrl_kmac_err_chk.1810852381
Short name T174
Test name
Test status
Simulation time 1267938228 ps
CPU time 17.37 seconds
Started Mar 14 01:17:35 PM PDT 24
Finished Mar 14 01:17:52 PM PDT 24
Peak memory 211592 kb
Host smart-d528d146-72b9-4a44-92de-f716212df066
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1810852381 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_kmac_err_chk.1810852381
Directory /workspace/15.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/15.rom_ctrl_max_throughput_chk.3292850285
Short name T247
Test name
Test status
Simulation time 4946471267 ps
CPU time 12.57 seconds
Started Mar 14 01:17:38 PM PDT 24
Finished Mar 14 01:17:50 PM PDT 24
Peak memory 211164 kb
Host smart-c0e2c633-5b3f-4874-93bd-f84184518983
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3292850285 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_max_throughput_chk.3292850285
Directory /workspace/15.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/15.rom_ctrl_smoke.1046735984
Short name T201
Test name
Test status
Simulation time 3687580300 ps
CPU time 17.86 seconds
Started Mar 14 01:17:21 PM PDT 24
Finished Mar 14 01:17:39 PM PDT 24
Peak memory 219280 kb
Host smart-f77fc35f-afa3-4511-895f-df08150c7aea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1046735984 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_smoke.1046735984
Directory /workspace/15.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/15.rom_ctrl_stress_all.3834486509
Short name T163
Test name
Test status
Simulation time 11542857609 ps
CPU time 66.87 seconds
Started Mar 14 01:17:24 PM PDT 24
Finished Mar 14 01:18:31 PM PDT 24
Peak memory 219332 kb
Host smart-ae1e575d-86e7-46a8-aa4a-abd71ed9bcc1
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3834486509 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 15.rom_ctrl_stress_all.3834486509
Directory /workspace/15.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/16.rom_ctrl_alert_test.4041163150
Short name T356
Test name
Test status
Simulation time 1619410855 ps
CPU time 13.61 seconds
Started Mar 14 01:17:34 PM PDT 24
Finished Mar 14 01:17:48 PM PDT 24
Peak memory 211104 kb
Host smart-3b4cb0ee-37cd-49e4-ae36-3f2c8fbf9af8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4041163150 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_alert_test.4041163150
Directory /workspace/16.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/16.rom_ctrl_kmac_err_chk.1262308008
Short name T44
Test name
Test status
Simulation time 693633911 ps
CPU time 9.33 seconds
Started Mar 14 01:17:39 PM PDT 24
Finished Mar 14 01:17:49 PM PDT 24
Peak memory 211876 kb
Host smart-3a288f0e-5b85-4c49-9fa1-1400c6ad4c28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1262308008 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_kmac_err_chk.1262308008
Directory /workspace/16.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/16.rom_ctrl_max_throughput_chk.4220264769
Short name T248
Test name
Test status
Simulation time 142358215 ps
CPU time 6.47 seconds
Started Mar 14 01:17:40 PM PDT 24
Finished Mar 14 01:17:46 PM PDT 24
Peak memory 210972 kb
Host smart-f8148315-b176-4b26-9618-afbb630547b6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4220264769 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_max_throughput_chk.4220264769
Directory /workspace/16.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/16.rom_ctrl_smoke.1748383259
Short name T202
Test name
Test status
Simulation time 1581416942 ps
CPU time 9.69 seconds
Started Mar 14 01:17:36 PM PDT 24
Finished Mar 14 01:17:46 PM PDT 24
Peak memory 213084 kb
Host smart-eb924097-a03b-4c62-8a47-beb96f792979
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1748383259 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_smoke.1748383259
Directory /workspace/16.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/16.rom_ctrl_stress_all.2309893407
Short name T344
Test name
Test status
Simulation time 1429278054 ps
CPU time 13.77 seconds
Started Mar 14 01:17:35 PM PDT 24
Finished Mar 14 01:17:49 PM PDT 24
Peak memory 213592 kb
Host smart-d39792f0-8037-4462-967e-898ff969e9ed
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2309893407 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 16.rom_ctrl_stress_all.2309893407
Directory /workspace/16.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/17.rom_ctrl_alert_test.2060677484
Short name T326
Test name
Test status
Simulation time 4446328965 ps
CPU time 11.32 seconds
Started Mar 14 01:17:36 PM PDT 24
Finished Mar 14 01:17:47 PM PDT 24
Peak memory 211064 kb
Host smart-aee33185-9e22-4d15-b49f-031fce9ad360
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2060677484 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_alert_test.2060677484
Directory /workspace/17.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/17.rom_ctrl_corrupt_sig_fatal_chk.1547080255
Short name T50
Test name
Test status
Simulation time 22087281239 ps
CPU time 104.55 seconds
Started Mar 14 01:17:32 PM PDT 24
Finished Mar 14 01:19:17 PM PDT 24
Peak memory 232748 kb
Host smart-cf4b4696-2020-411a-a003-699b010afb67
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1547080255 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_
corrupt_sig_fatal_chk.1547080255
Directory /workspace/17.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/17.rom_ctrl_kmac_err_chk.2079729604
Short name T346
Test name
Test status
Simulation time 3655248123 ps
CPU time 30.75 seconds
Started Mar 14 01:17:36 PM PDT 24
Finished Mar 14 01:18:07 PM PDT 24
Peak memory 211636 kb
Host smart-9286de47-9975-4867-bbfd-4e0b610879a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2079729604 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_kmac_err_chk.2079729604
Directory /workspace/17.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/17.rom_ctrl_max_throughput_chk.356636816
Short name T156
Test name
Test status
Simulation time 3786081566 ps
CPU time 10.66 seconds
Started Mar 14 01:17:36 PM PDT 24
Finished Mar 14 01:17:47 PM PDT 24
Peak memory 211128 kb
Host smart-2a4be34a-2f36-4ca6-b509-a51ddbaf66a4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=356636816 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_max_throughput_chk.356636816
Directory /workspace/17.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/17.rom_ctrl_smoke.203057090
Short name T183
Test name
Test status
Simulation time 191137552 ps
CPU time 10.64 seconds
Started Mar 14 01:17:36 PM PDT 24
Finished Mar 14 01:17:47 PM PDT 24
Peak memory 212956 kb
Host smart-c679feed-38f2-4def-ae31-172a79d7a680
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=203057090 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_smoke.203057090
Directory /workspace/17.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/17.rom_ctrl_stress_all.1433541641
Short name T240
Test name
Test status
Simulation time 12306955212 ps
CPU time 103.76 seconds
Started Mar 14 01:17:35 PM PDT 24
Finished Mar 14 01:19:19 PM PDT 24
Peak memory 217108 kb
Host smart-7b4421ea-9f7b-459f-9612-02af74906594
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1433541641 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 17.rom_ctrl_stress_all.1433541641
Directory /workspace/17.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/17.rom_ctrl_stress_all_with_rand_reset.1685870157
Short name T12
Test name
Test status
Simulation time 475207749614 ps
CPU time 2142.25 seconds
Started Mar 14 01:17:38 PM PDT 24
Finished Mar 14 01:53:20 PM PDT 24
Peak memory 237276 kb
Host smart-30232560-866c-4961-b5df-5df8a8b77e4b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1685870157 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_stress_all_with_rand_reset.1685870157
Directory /workspace/17.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/18.rom_ctrl_alert_test.696405506
Short name T46
Test name
Test status
Simulation time 204308865 ps
CPU time 4.27 seconds
Started Mar 14 01:17:36 PM PDT 24
Finished Mar 14 01:17:40 PM PDT 24
Peak memory 211068 kb
Host smart-efb529e5-7611-415a-8ffc-5a8dda89a421
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=696405506 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_alert_test.696405506
Directory /workspace/18.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/18.rom_ctrl_corrupt_sig_fatal_chk.41990020
Short name T283
Test name
Test status
Simulation time 67441050464 ps
CPU time 249.48 seconds
Started Mar 14 01:17:36 PM PDT 24
Finished Mar 14 01:21:45 PM PDT 24
Peak memory 221268 kb
Host smart-d3f38117-f5be-4d0f-9ba3-9c0b6e401695
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41990020 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_
sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_co
rrupt_sig_fatal_chk.41990020
Directory /workspace/18.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/18.rom_ctrl_kmac_err_chk.922683379
Short name T262
Test name
Test status
Simulation time 3399592856 ps
CPU time 28.74 seconds
Started Mar 14 01:17:40 PM PDT 24
Finished Mar 14 01:18:08 PM PDT 24
Peak memory 211892 kb
Host smart-538f2cb2-2acc-4652-bfcd-34c635cae1d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=922683379 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_kmac_err_chk.922683379
Directory /workspace/18.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/18.rom_ctrl_max_throughput_chk.549041913
Short name T294
Test name
Test status
Simulation time 97043791 ps
CPU time 5.46 seconds
Started Mar 14 01:17:35 PM PDT 24
Finished Mar 14 01:17:40 PM PDT 24
Peak memory 211028 kb
Host smart-ac91559c-5165-4b34-972e-e485b6761536
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=549041913 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_max_throughput_chk.549041913
Directory /workspace/18.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/18.rom_ctrl_smoke.641651618
Short name T224
Test name
Test status
Simulation time 183689714 ps
CPU time 10.11 seconds
Started Mar 14 01:17:38 PM PDT 24
Finished Mar 14 01:17:49 PM PDT 24
Peak memory 219144 kb
Host smart-deeffaf6-52a3-43e1-9fe7-89ddf37a18ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=641651618 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_smoke.641651618
Directory /workspace/18.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/18.rom_ctrl_stress_all.4021875872
Short name T332
Test name
Test status
Simulation time 778613576 ps
CPU time 17.23 seconds
Started Mar 14 01:17:34 PM PDT 24
Finished Mar 14 01:17:52 PM PDT 24
Peak memory 213384 kb
Host smart-7690e724-01a3-4062-b913-85a14c185fa9
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4021875872 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 18.rom_ctrl_stress_all.4021875872
Directory /workspace/18.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/19.rom_ctrl_alert_test.3649054838
Short name T64
Test name
Test status
Simulation time 7228003059 ps
CPU time 16.27 seconds
Started Mar 14 01:17:35 PM PDT 24
Finished Mar 14 01:17:51 PM PDT 24
Peak memory 211272 kb
Host smart-c30c6a7d-df0e-4212-88d7-a2699f71625f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3649054838 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_alert_test.3649054838
Directory /workspace/19.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/19.rom_ctrl_corrupt_sig_fatal_chk.2185683076
Short name T3
Test name
Test status
Simulation time 6069471655 ps
CPU time 99.43 seconds
Started Mar 14 01:17:35 PM PDT 24
Finished Mar 14 01:19:15 PM PDT 24
Peak memory 228488 kb
Host smart-419f0321-e175-4429-b8fe-5b34a1c05571
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2185683076 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_
corrupt_sig_fatal_chk.2185683076
Directory /workspace/19.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/19.rom_ctrl_kmac_err_chk.3346825832
Short name T187
Test name
Test status
Simulation time 333851236 ps
CPU time 9.51 seconds
Started Mar 14 01:17:35 PM PDT 24
Finished Mar 14 01:17:45 PM PDT 24
Peak memory 211684 kb
Host smart-71dcb6ae-0a1d-4953-b949-4434b5875560
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3346825832 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_kmac_err_chk.3346825832
Directory /workspace/19.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/19.rom_ctrl_max_throughput_chk.677457890
Short name T135
Test name
Test status
Simulation time 5259929037 ps
CPU time 14.26 seconds
Started Mar 14 01:17:36 PM PDT 24
Finished Mar 14 01:17:50 PM PDT 24
Peak memory 211144 kb
Host smart-a1511cf8-d330-4574-ab2e-d28a4d2d08f8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=677457890 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_max_throughput_chk.677457890
Directory /workspace/19.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/19.rom_ctrl_smoke.1220037433
Short name T42
Test name
Test status
Simulation time 1150135730 ps
CPU time 17.29 seconds
Started Mar 14 01:17:37 PM PDT 24
Finished Mar 14 01:17:54 PM PDT 24
Peak memory 219240 kb
Host smart-e3d793f8-eb07-412f-bdc1-ec64dc2f5eaf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1220037433 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_smoke.1220037433
Directory /workspace/19.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/19.rom_ctrl_stress_all.4047738862
Short name T146
Test name
Test status
Simulation time 22298292207 ps
CPU time 59.01 seconds
Started Mar 14 01:17:36 PM PDT 24
Finished Mar 14 01:18:35 PM PDT 24
Peak memory 216868 kb
Host smart-7c79fb88-5295-4ce0-9421-3e9d7ba5ead5
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4047738862 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 19.rom_ctrl_stress_all.4047738862
Directory /workspace/19.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/2.rom_ctrl_alert_test.1987987511
Short name T62
Test name
Test status
Simulation time 1023201250 ps
CPU time 10.31 seconds
Started Mar 14 01:17:07 PM PDT 24
Finished Mar 14 01:17:17 PM PDT 24
Peak memory 211088 kb
Host smart-3c3efb77-7bcc-47c1-9380-4aacbb86ea77
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1987987511 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_alert_test.1987987511
Directory /workspace/2.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/2.rom_ctrl_corrupt_sig_fatal_chk.364674333
Short name T340
Test name
Test status
Simulation time 27963399520 ps
CPU time 275.91 seconds
Started Mar 14 01:17:20 PM PDT 24
Finished Mar 14 01:21:56 PM PDT 24
Peak memory 220360 kb
Host smart-68e5aa85-6c40-449b-be47-56dd4c97eefe
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=364674333 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_co
rrupt_sig_fatal_chk.364674333
Directory /workspace/2.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/2.rom_ctrl_kmac_err_chk.2716942006
Short name T20
Test name
Test status
Simulation time 175641544 ps
CPU time 9.6 seconds
Started Mar 14 01:17:08 PM PDT 24
Finished Mar 14 01:17:18 PM PDT 24
Peak memory 211672 kb
Host smart-a8367674-0672-417e-bd24-5087fd54c451
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2716942006 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_kmac_err_chk.2716942006
Directory /workspace/2.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/2.rom_ctrl_max_throughput_chk.4101026778
Short name T188
Test name
Test status
Simulation time 1222906523 ps
CPU time 7.47 seconds
Started Mar 14 01:17:08 PM PDT 24
Finished Mar 14 01:17:15 PM PDT 24
Peak memory 211004 kb
Host smart-60a7a378-cf47-4f87-a3a6-d61da403fd76
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4101026778 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_max_throughput_chk.4101026778
Directory /workspace/2.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/2.rom_ctrl_sec_cm.1470902693
Short name T30
Test name
Test status
Simulation time 2670048355 ps
CPU time 58.57 seconds
Started Mar 14 01:17:23 PM PDT 24
Finished Mar 14 01:18:22 PM PDT 24
Peak memory 236708 kb
Host smart-fafa6286-cbcb-45ee-8b58-8010b602cf56
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1470902693 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_sec_cm.1470902693
Directory /workspace/2.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/2.rom_ctrl_smoke.1652312785
Short name T184
Test name
Test status
Simulation time 192846965 ps
CPU time 10.18 seconds
Started Mar 14 01:17:12 PM PDT 24
Finished Mar 14 01:17:22 PM PDT 24
Peak memory 219256 kb
Host smart-33c71ad3-116e-4ea5-85d7-655ce35a77fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1652312785 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_smoke.1652312785
Directory /workspace/2.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/2.rom_ctrl_stress_all.910948164
Short name T130
Test name
Test status
Simulation time 605655273 ps
CPU time 34.2 seconds
Started Mar 14 01:17:04 PM PDT 24
Finished Mar 14 01:17:38 PM PDT 24
Peak memory 215048 kb
Host smart-2a64ce24-a44f-4e26-b676-71e76849ed60
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=910948164 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 2.rom_ctrl_stress_all.910948164
Directory /workspace/2.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/20.rom_ctrl_alert_test.2538462303
Short name T317
Test name
Test status
Simulation time 632307671 ps
CPU time 6.56 seconds
Started Mar 14 01:17:36 PM PDT 24
Finished Mar 14 01:17:43 PM PDT 24
Peak memory 211104 kb
Host smart-8705bec9-7895-440e-b436-8bee81638e92
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2538462303 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_alert_test.2538462303
Directory /workspace/20.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/20.rom_ctrl_corrupt_sig_fatal_chk.2321245056
Short name T329
Test name
Test status
Simulation time 44270281566 ps
CPU time 253.58 seconds
Started Mar 14 01:17:38 PM PDT 24
Finished Mar 14 01:21:53 PM PDT 24
Peak memory 234856 kb
Host smart-5c596f9d-ff55-4cc7-b4b4-adc6cb34c822
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2321245056 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_
corrupt_sig_fatal_chk.2321245056
Directory /workspace/20.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/20.rom_ctrl_kmac_err_chk.3142315502
Short name T365
Test name
Test status
Simulation time 1106043104 ps
CPU time 9.36 seconds
Started Mar 14 01:17:35 PM PDT 24
Finished Mar 14 01:17:44 PM PDT 24
Peak memory 211476 kb
Host smart-e8830282-5582-4ed6-9a8f-608f2d1c3720
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3142315502 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_kmac_err_chk.3142315502
Directory /workspace/20.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/20.rom_ctrl_max_throughput_chk.3145401072
Short name T354
Test name
Test status
Simulation time 352086723 ps
CPU time 5.54 seconds
Started Mar 14 01:17:36 PM PDT 24
Finished Mar 14 01:17:41 PM PDT 24
Peak memory 210956 kb
Host smart-dd93eedf-d74f-4b0f-a61e-24a9b6c4c83f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3145401072 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_max_throughput_chk.3145401072
Directory /workspace/20.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/20.rom_ctrl_smoke.1255634189
Short name T227
Test name
Test status
Simulation time 7321110010 ps
CPU time 31.42 seconds
Started Mar 14 01:17:35 PM PDT 24
Finished Mar 14 01:18:06 PM PDT 24
Peak memory 213824 kb
Host smart-0502c3a3-6569-4bcb-8ac8-85730866a330
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1255634189 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_smoke.1255634189
Directory /workspace/20.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/20.rom_ctrl_stress_all.810637238
Short name T297
Test name
Test status
Simulation time 207731296 ps
CPU time 10.21 seconds
Started Mar 14 01:17:37 PM PDT 24
Finished Mar 14 01:17:48 PM PDT 24
Peak memory 213988 kb
Host smart-66dcebe5-6f09-4df3-bf6f-208861330bca
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=810637238 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 20.rom_ctrl_stress_all.810637238
Directory /workspace/20.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/21.rom_ctrl_alert_test.2050324604
Short name T168
Test name
Test status
Simulation time 1402793466 ps
CPU time 12.69 seconds
Started Mar 14 01:17:36 PM PDT 24
Finished Mar 14 01:17:49 PM PDT 24
Peak memory 210944 kb
Host smart-3823b6bf-f563-4537-bc29-c144bb854069
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2050324604 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_alert_test.2050324604
Directory /workspace/21.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/21.rom_ctrl_corrupt_sig_fatal_chk.2528799043
Short name T261
Test name
Test status
Simulation time 573040574346 ps
CPU time 346.83 seconds
Started Mar 14 01:17:35 PM PDT 24
Finished Mar 14 01:23:22 PM PDT 24
Peak memory 237676 kb
Host smart-37c6a4bf-66fe-4e79-bac1-55fc24e4bd86
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2528799043 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_
corrupt_sig_fatal_chk.2528799043
Directory /workspace/21.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/21.rom_ctrl_kmac_err_chk.4088486353
Short name T307
Test name
Test status
Simulation time 4064239507 ps
CPU time 33.25 seconds
Started Mar 14 01:17:37 PM PDT 24
Finished Mar 14 01:18:10 PM PDT 24
Peak memory 211612 kb
Host smart-2d75646d-9084-49d8-b62f-20323287a73f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4088486353 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_kmac_err_chk.4088486353
Directory /workspace/21.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/21.rom_ctrl_max_throughput_chk.464712460
Short name T196
Test name
Test status
Simulation time 1770551039 ps
CPU time 15.83 seconds
Started Mar 14 01:17:37 PM PDT 24
Finished Mar 14 01:17:53 PM PDT 24
Peak memory 211068 kb
Host smart-0a996f41-5400-428c-a0e6-c68af64c4cf8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=464712460 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_max_throughput_chk.464712460
Directory /workspace/21.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/21.rom_ctrl_smoke.369360961
Short name T17
Test name
Test status
Simulation time 1039730203 ps
CPU time 16.32 seconds
Started Mar 14 01:17:32 PM PDT 24
Finished Mar 14 01:17:49 PM PDT 24
Peak memory 213212 kb
Host smart-6a50a7a0-4b9d-4100-bd8e-05863fe817b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=369360961 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_smoke.369360961
Directory /workspace/21.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/21.rom_ctrl_stress_all.839635473
Short name T270
Test name
Test status
Simulation time 1017690716 ps
CPU time 26.29 seconds
Started Mar 14 01:17:38 PM PDT 24
Finished Mar 14 01:18:04 PM PDT 24
Peak memory 213596 kb
Host smart-4260c20c-ebcc-497a-beec-c525d15ec244
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=839635473 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 21.rom_ctrl_stress_all.839635473
Directory /workspace/21.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/22.rom_ctrl_alert_test.1158629815
Short name T268
Test name
Test status
Simulation time 2131635621 ps
CPU time 16.86 seconds
Started Mar 14 01:17:34 PM PDT 24
Finished Mar 14 01:17:51 PM PDT 24
Peak memory 211100 kb
Host smart-f1698013-048e-4d91-bd93-b0e13496c543
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1158629815 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_alert_test.1158629815
Directory /workspace/22.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/22.rom_ctrl_corrupt_sig_fatal_chk.2654030537
Short name T232
Test name
Test status
Simulation time 6677076375 ps
CPU time 113.98 seconds
Started Mar 14 01:17:36 PM PDT 24
Finished Mar 14 01:19:30 PM PDT 24
Peak memory 232688 kb
Host smart-f1a09264-55bd-41f7-b5d7-e4d06cc977f8
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2654030537 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_
corrupt_sig_fatal_chk.2654030537
Directory /workspace/22.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/22.rom_ctrl_kmac_err_chk.15095044
Short name T94
Test name
Test status
Simulation time 171866707 ps
CPU time 9.36 seconds
Started Mar 14 01:17:35 PM PDT 24
Finished Mar 14 01:17:45 PM PDT 24
Peak memory 211792 kb
Host smart-be098a73-f755-4f23-a82f-dc21a08c613c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=15095044 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_kmac_err_chk.15095044
Directory /workspace/22.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/22.rom_ctrl_max_throughput_chk.1734798673
Short name T23
Test name
Test status
Simulation time 2668660157 ps
CPU time 13.32 seconds
Started Mar 14 01:17:35 PM PDT 24
Finished Mar 14 01:17:49 PM PDT 24
Peak memory 211052 kb
Host smart-1e311c67-b771-48c7-8e7c-d68d79490db4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1734798673 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_max_throughput_chk.1734798673
Directory /workspace/22.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/22.rom_ctrl_smoke.4011158184
Short name T299
Test name
Test status
Simulation time 365363386 ps
CPU time 10.17 seconds
Started Mar 14 01:17:36 PM PDT 24
Finished Mar 14 01:17:46 PM PDT 24
Peak memory 212724 kb
Host smart-821dc294-3d53-48d6-a449-009621bbbf74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4011158184 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_smoke.4011158184
Directory /workspace/22.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/22.rom_ctrl_stress_all.371334210
Short name T310
Test name
Test status
Simulation time 979909134 ps
CPU time 10.69 seconds
Started Mar 14 01:17:36 PM PDT 24
Finished Mar 14 01:17:47 PM PDT 24
Peak memory 213004 kb
Host smart-00021ac4-5244-4e3d-ab5b-62518fd78918
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=371334210 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 22.rom_ctrl_stress_all.371334210
Directory /workspace/22.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/23.rom_ctrl_alert_test.3280650420
Short name T33
Test name
Test status
Simulation time 1819605183 ps
CPU time 7.51 seconds
Started Mar 14 01:17:38 PM PDT 24
Finished Mar 14 01:17:45 PM PDT 24
Peak memory 211048 kb
Host smart-6e712762-6f12-4858-9b1e-bafb08779dc4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3280650420 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_alert_test.3280650420
Directory /workspace/23.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/23.rom_ctrl_corrupt_sig_fatal_chk.2802678571
Short name T150
Test name
Test status
Simulation time 279184075183 ps
CPU time 195.92 seconds
Started Mar 14 01:17:39 PM PDT 24
Finished Mar 14 01:20:55 PM PDT 24
Peak memory 236632 kb
Host smart-8ee6e87b-9bcc-4570-a577-4b4c62e66837
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2802678571 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_
corrupt_sig_fatal_chk.2802678571
Directory /workspace/23.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/23.rom_ctrl_kmac_err_chk.2055608528
Short name T238
Test name
Test status
Simulation time 7301142740 ps
CPU time 30.94 seconds
Started Mar 14 01:17:33 PM PDT 24
Finished Mar 14 01:18:04 PM PDT 24
Peak memory 212036 kb
Host smart-6926a594-cb29-4008-ae76-081adc88e651
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2055608528 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_kmac_err_chk.2055608528
Directory /workspace/23.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/23.rom_ctrl_max_throughput_chk.4065088404
Short name T181
Test name
Test status
Simulation time 94804500 ps
CPU time 5.29 seconds
Started Mar 14 01:17:36 PM PDT 24
Finished Mar 14 01:17:42 PM PDT 24
Peak memory 211040 kb
Host smart-f74a658c-b8d2-4c87-a1cb-273988acfb03
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4065088404 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_max_throughput_chk.4065088404
Directory /workspace/23.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/23.rom_ctrl_smoke.2322485762
Short name T4
Test name
Test status
Simulation time 8903227539 ps
CPU time 23.85 seconds
Started Mar 14 01:17:35 PM PDT 24
Finished Mar 14 01:17:59 PM PDT 24
Peak memory 219328 kb
Host smart-bc0f7c96-a641-4ed0-ac6d-549772fd38eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2322485762 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_smoke.2322485762
Directory /workspace/23.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/23.rom_ctrl_stress_all.1083018177
Short name T353
Test name
Test status
Simulation time 1502199947 ps
CPU time 21.26 seconds
Started Mar 14 01:17:38 PM PDT 24
Finished Mar 14 01:17:59 PM PDT 24
Peak memory 219236 kb
Host smart-eb182f9f-914f-4060-8305-d81af703803e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1083018177 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 23.rom_ctrl_stress_all.1083018177
Directory /workspace/23.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/24.rom_ctrl_alert_test.2515177160
Short name T194
Test name
Test status
Simulation time 8178410543 ps
CPU time 16.73 seconds
Started Mar 14 01:17:36 PM PDT 24
Finished Mar 14 01:17:53 PM PDT 24
Peak memory 211268 kb
Host smart-683fef74-50ff-4cbf-8257-8392645e249b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2515177160 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_alert_test.2515177160
Directory /workspace/24.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/24.rom_ctrl_corrupt_sig_fatal_chk.3534124462
Short name T175
Test name
Test status
Simulation time 124198206847 ps
CPU time 318.27 seconds
Started Mar 14 01:17:37 PM PDT 24
Finished Mar 14 01:22:56 PM PDT 24
Peak memory 224508 kb
Host smart-cc33791c-49bd-4fba-aa7f-864a3064502e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3534124462 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_
corrupt_sig_fatal_chk.3534124462
Directory /workspace/24.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/24.rom_ctrl_max_throughput_chk.1155192788
Short name T287
Test name
Test status
Simulation time 99194399 ps
CPU time 5.62 seconds
Started Mar 14 01:17:37 PM PDT 24
Finished Mar 14 01:17:43 PM PDT 24
Peak memory 211060 kb
Host smart-43ffc72b-791e-4d40-b241-bc82a27ac165
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1155192788 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_max_throughput_chk.1155192788
Directory /workspace/24.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/24.rom_ctrl_smoke.3727657567
Short name T320
Test name
Test status
Simulation time 235697335 ps
CPU time 9.76 seconds
Started Mar 14 01:17:37 PM PDT 24
Finished Mar 14 01:17:47 PM PDT 24
Peak memory 219140 kb
Host smart-c0d5da1a-571b-4851-9a07-330b53716325
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3727657567 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_smoke.3727657567
Directory /workspace/24.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/24.rom_ctrl_stress_all.3233998761
Short name T234
Test name
Test status
Simulation time 7379494562 ps
CPU time 11.97 seconds
Started Mar 14 01:17:37 PM PDT 24
Finished Mar 14 01:17:49 PM PDT 24
Peak memory 218280 kb
Host smart-2e05da28-35d5-473d-a4de-656840d4d711
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3233998761 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 24.rom_ctrl_stress_all.3233998761
Directory /workspace/24.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/25.rom_ctrl_alert_test.1917948077
Short name T321
Test name
Test status
Simulation time 11845382115 ps
CPU time 16.1 seconds
Started Mar 14 01:17:58 PM PDT 24
Finished Mar 14 01:18:15 PM PDT 24
Peak memory 211164 kb
Host smart-36471ad9-df40-4247-a61b-53e014e976a1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1917948077 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_alert_test.1917948077
Directory /workspace/25.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/25.rom_ctrl_corrupt_sig_fatal_chk.1840242101
Short name T352
Test name
Test status
Simulation time 8720352538 ps
CPU time 129.27 seconds
Started Mar 14 01:17:38 PM PDT 24
Finished Mar 14 01:19:47 PM PDT 24
Peak memory 229808 kb
Host smart-6d10403b-dcee-43f4-ae45-6b1b0242c608
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1840242101 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_
corrupt_sig_fatal_chk.1840242101
Directory /workspace/25.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/25.rom_ctrl_kmac_err_chk.1164247231
Short name T230
Test name
Test status
Simulation time 7329311108 ps
CPU time 18.19 seconds
Started Mar 14 01:17:47 PM PDT 24
Finished Mar 14 01:18:05 PM PDT 24
Peak memory 212384 kb
Host smart-6d733150-ec49-4672-a21c-518f18c33cf5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1164247231 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_kmac_err_chk.1164247231
Directory /workspace/25.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/25.rom_ctrl_max_throughput_chk.3720414796
Short name T358
Test name
Test status
Simulation time 694213761 ps
CPU time 5.53 seconds
Started Mar 14 01:17:38 PM PDT 24
Finished Mar 14 01:17:43 PM PDT 24
Peak memory 211004 kb
Host smart-fcc28206-c72d-49ea-b611-c0f5b036956f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3720414796 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_max_throughput_chk.3720414796
Directory /workspace/25.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/25.rom_ctrl_smoke.4279867871
Short name T333
Test name
Test status
Simulation time 17269299594 ps
CPU time 26.2 seconds
Started Mar 14 01:17:38 PM PDT 24
Finished Mar 14 01:18:04 PM PDT 24
Peak memory 214064 kb
Host smart-0a96006a-b158-4a33-a241-d0fbabaf17c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4279867871 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_smoke.4279867871
Directory /workspace/25.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/25.rom_ctrl_stress_all.1655748009
Short name T16
Test name
Test status
Simulation time 1194076802 ps
CPU time 16.49 seconds
Started Mar 14 01:17:37 PM PDT 24
Finished Mar 14 01:17:54 PM PDT 24
Peak memory 219228 kb
Host smart-4a3d194a-194f-4d03-8520-aa0887c48f60
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1655748009 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 25.rom_ctrl_stress_all.1655748009
Directory /workspace/25.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/26.rom_ctrl_alert_test.4108645279
Short name T148
Test name
Test status
Simulation time 7887097016 ps
CPU time 15.83 seconds
Started Mar 14 01:17:50 PM PDT 24
Finished Mar 14 01:18:06 PM PDT 24
Peak memory 211180 kb
Host smart-2739afbf-ac2b-4187-843b-fc42487a5624
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4108645279 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_alert_test.4108645279
Directory /workspace/26.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/26.rom_ctrl_kmac_err_chk.3941200105
Short name T131
Test name
Test status
Simulation time 7186356353 ps
CPU time 29.72 seconds
Started Mar 14 01:17:48 PM PDT 24
Finished Mar 14 01:18:18 PM PDT 24
Peak memory 212368 kb
Host smart-e07391c6-7d89-4a09-ad29-78d730494911
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3941200105 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_kmac_err_chk.3941200105
Directory /workspace/26.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/26.rom_ctrl_max_throughput_chk.146332037
Short name T314
Test name
Test status
Simulation time 6133131653 ps
CPU time 13.74 seconds
Started Mar 14 01:17:55 PM PDT 24
Finished Mar 14 01:18:09 PM PDT 24
Peak memory 211188 kb
Host smart-60804d3b-5804-4eea-af70-355a73a6f3d0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=146332037 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_max_throughput_chk.146332037
Directory /workspace/26.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/26.rom_ctrl_smoke.701329232
Short name T205
Test name
Test status
Simulation time 360168554 ps
CPU time 11.94 seconds
Started Mar 14 01:17:47 PM PDT 24
Finished Mar 14 01:17:59 PM PDT 24
Peak memory 212824 kb
Host smart-e1edbfd7-81d4-4cc7-a942-4e7b3672447b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=701329232 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_smoke.701329232
Directory /workspace/26.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/26.rom_ctrl_stress_all.2375473399
Short name T302
Test name
Test status
Simulation time 24629485904 ps
CPU time 60.71 seconds
Started Mar 14 01:17:48 PM PDT 24
Finished Mar 14 01:18:49 PM PDT 24
Peak memory 217472 kb
Host smart-f65bde5a-534c-4e8e-a574-1fdb07d5018a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2375473399 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 26.rom_ctrl_stress_all.2375473399
Directory /workspace/26.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/27.rom_ctrl_alert_test.2897144022
Short name T198
Test name
Test status
Simulation time 28524090526 ps
CPU time 12.86 seconds
Started Mar 14 01:17:54 PM PDT 24
Finished Mar 14 01:18:07 PM PDT 24
Peak memory 211156 kb
Host smart-e088eb10-2fe6-4516-88f3-95f8d23417b2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2897144022 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_alert_test.2897144022
Directory /workspace/27.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/27.rom_ctrl_corrupt_sig_fatal_chk.2053974178
Short name T250
Test name
Test status
Simulation time 1745254549 ps
CPU time 123.97 seconds
Started Mar 14 01:17:50 PM PDT 24
Finished Mar 14 01:19:54 PM PDT 24
Peak memory 236220 kb
Host smart-d94ac185-a6a2-42c7-822e-a71e8aed766a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2053974178 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_
corrupt_sig_fatal_chk.2053974178
Directory /workspace/27.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/27.rom_ctrl_kmac_err_chk.1356933473
Short name T2
Test name
Test status
Simulation time 451391602 ps
CPU time 9.61 seconds
Started Mar 14 01:17:44 PM PDT 24
Finished Mar 14 01:17:54 PM PDT 24
Peak memory 211720 kb
Host smart-dbec65c8-e93a-4d09-997f-f3aa25accf22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1356933473 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_kmac_err_chk.1356933473
Directory /workspace/27.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/27.rom_ctrl_max_throughput_chk.467099641
Short name T39
Test name
Test status
Simulation time 25801852085 ps
CPU time 13.57 seconds
Started Mar 14 01:17:48 PM PDT 24
Finished Mar 14 01:18:02 PM PDT 24
Peak memory 211144 kb
Host smart-16385295-fc5a-49a5-9c8c-f45df4f283f2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=467099641 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_max_throughput_chk.467099641
Directory /workspace/27.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/27.rom_ctrl_smoke.2632298914
Short name T6
Test name
Test status
Simulation time 1772390586 ps
CPU time 10.3 seconds
Started Mar 14 01:17:46 PM PDT 24
Finished Mar 14 01:17:57 PM PDT 24
Peak memory 213288 kb
Host smart-44176e71-9873-49d2-be9e-6c7fa20d18ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2632298914 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_smoke.2632298914
Directory /workspace/27.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/27.rom_ctrl_stress_all.1790081819
Short name T236
Test name
Test status
Simulation time 4757301979 ps
CPU time 13.99 seconds
Started Mar 14 01:17:48 PM PDT 24
Finished Mar 14 01:18:02 PM PDT 24
Peak memory 212104 kb
Host smart-c886d03f-6017-4360-b1e0-a57940d4a76d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1790081819 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 27.rom_ctrl_stress_all.1790081819
Directory /workspace/27.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/28.rom_ctrl_alert_test.2453672520
Short name T173
Test name
Test status
Simulation time 1851613130 ps
CPU time 15.25 seconds
Started Mar 14 01:17:51 PM PDT 24
Finished Mar 14 01:18:07 PM PDT 24
Peak memory 211112 kb
Host smart-050ba151-1f39-4b2b-8050-7336aeefa663
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2453672520 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_alert_test.2453672520
Directory /workspace/28.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/28.rom_ctrl_corrupt_sig_fatal_chk.2281254370
Short name T27
Test name
Test status
Simulation time 68840032956 ps
CPU time 413.49 seconds
Started Mar 14 01:17:48 PM PDT 24
Finished Mar 14 01:24:41 PM PDT 24
Peak memory 237796 kb
Host smart-3f618a85-57c1-4f60-95b5-d857f3275024
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2281254370 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_
corrupt_sig_fatal_chk.2281254370
Directory /workspace/28.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/28.rom_ctrl_kmac_err_chk.2648326613
Short name T269
Test name
Test status
Simulation time 177396702 ps
CPU time 9.19 seconds
Started Mar 14 01:17:49 PM PDT 24
Finished Mar 14 01:17:58 PM PDT 24
Peak memory 210948 kb
Host smart-c8e7f778-a80d-4afc-b5e0-067db216e6eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2648326613 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_kmac_err_chk.2648326613
Directory /workspace/28.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/28.rom_ctrl_max_throughput_chk.2622229814
Short name T343
Test name
Test status
Simulation time 97386236 ps
CPU time 5.72 seconds
Started Mar 14 01:17:51 PM PDT 24
Finished Mar 14 01:17:57 PM PDT 24
Peak memory 210992 kb
Host smart-ca20ec6c-f979-457f-b8dd-c62bf085b822
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2622229814 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_max_throughput_chk.2622229814
Directory /workspace/28.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/28.rom_ctrl_smoke.2603155066
Short name T18
Test name
Test status
Simulation time 1338200831 ps
CPU time 18.28 seconds
Started Mar 14 01:17:48 PM PDT 24
Finished Mar 14 01:18:06 PM PDT 24
Peak memory 211692 kb
Host smart-ba3e1abe-83da-47a4-a10a-2cd787b33b3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2603155066 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_smoke.2603155066
Directory /workspace/28.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/28.rom_ctrl_stress_all.1157940033
Short name T170
Test name
Test status
Simulation time 1603262668 ps
CPU time 13.3 seconds
Started Mar 14 01:17:49 PM PDT 24
Finished Mar 14 01:18:02 PM PDT 24
Peak memory 210956 kb
Host smart-8b231028-1aa5-4240-bc27-0720039fccf0
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1157940033 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 28.rom_ctrl_stress_all.1157940033
Directory /workspace/28.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/28.rom_ctrl_stress_all_with_rand_reset.1495296395
Short name T11
Test name
Test status
Simulation time 14144797094 ps
CPU time 497.92 seconds
Started Mar 14 01:17:50 PM PDT 24
Finished Mar 14 01:26:08 PM PDT 24
Peak memory 230660 kb
Host smart-e7ffe8f0-6c82-461d-be1e-9a2a13d45f2f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1495296395 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_stress_all_with_rand_reset.1495296395
Directory /workspace/28.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/29.rom_ctrl_alert_test.1616059987
Short name T34
Test name
Test status
Simulation time 1905191077 ps
CPU time 7.51 seconds
Started Mar 14 01:17:50 PM PDT 24
Finished Mar 14 01:17:58 PM PDT 24
Peak memory 211036 kb
Host smart-537407c4-66fb-400b-88cb-20e05d7016bd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1616059987 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_alert_test.1616059987
Directory /workspace/29.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/29.rom_ctrl_corrupt_sig_fatal_chk.4178076188
Short name T334
Test name
Test status
Simulation time 4413202836 ps
CPU time 131.55 seconds
Started Mar 14 01:17:47 PM PDT 24
Finished Mar 14 01:19:59 PM PDT 24
Peak memory 237100 kb
Host smart-dea26480-60ad-4495-a983-3da65bde154a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4178076188 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_
corrupt_sig_fatal_chk.4178076188
Directory /workspace/29.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/29.rom_ctrl_kmac_err_chk.3218149529
Short name T26
Test name
Test status
Simulation time 1994356882 ps
CPU time 20.8 seconds
Started Mar 14 01:17:53 PM PDT 24
Finished Mar 14 01:18:14 PM PDT 24
Peak memory 211752 kb
Host smart-442e52db-b973-43d5-a00a-a60356fe1685
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3218149529 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_kmac_err_chk.3218149529
Directory /workspace/29.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/29.rom_ctrl_max_throughput_chk.4078485975
Short name T143
Test name
Test status
Simulation time 308803161 ps
CPU time 7.43 seconds
Started Mar 14 01:17:51 PM PDT 24
Finished Mar 14 01:17:59 PM PDT 24
Peak memory 210992 kb
Host smart-98cb13b8-d9c0-4fd0-8b3d-9612b5403054
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4078485975 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_max_throughput_chk.4078485975
Directory /workspace/29.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/29.rom_ctrl_smoke.216827209
Short name T254
Test name
Test status
Simulation time 600054338 ps
CPU time 10.27 seconds
Started Mar 14 01:17:46 PM PDT 24
Finished Mar 14 01:17:57 PM PDT 24
Peak memory 219224 kb
Host smart-42cfd77c-098f-4033-a2d6-df0b2f347117
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=216827209 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_smoke.216827209
Directory /workspace/29.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/29.rom_ctrl_stress_all.924831774
Short name T278
Test name
Test status
Simulation time 7767752627 ps
CPU time 40.16 seconds
Started Mar 14 01:17:53 PM PDT 24
Finished Mar 14 01:18:33 PM PDT 24
Peak memory 214856 kb
Host smart-fbaadff9-8cd7-42e9-aa44-3a7176e20929
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=924831774 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 29.rom_ctrl_stress_all.924831774
Directory /workspace/29.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/3.rom_ctrl_alert_test.4015802480
Short name T279
Test name
Test status
Simulation time 1651749678 ps
CPU time 14.24 seconds
Started Mar 14 01:17:10 PM PDT 24
Finished Mar 14 01:17:25 PM PDT 24
Peak memory 211096 kb
Host smart-b3b0a6b4-2d02-41eb-9f6e-1c9770187155
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4015802480 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_alert_test.4015802480
Directory /workspace/3.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/3.rom_ctrl_corrupt_sig_fatal_chk.3609057889
Short name T272
Test name
Test status
Simulation time 21732576082 ps
CPU time 119.18 seconds
Started Mar 14 01:17:10 PM PDT 24
Finished Mar 14 01:19:10 PM PDT 24
Peak memory 230264 kb
Host smart-6e7f445d-83be-4e16-96ab-a1f1585fbb5d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3609057889 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_c
orrupt_sig_fatal_chk.3609057889
Directory /workspace/3.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/3.rom_ctrl_kmac_err_chk.381334944
Short name T347
Test name
Test status
Simulation time 17490356858 ps
CPU time 30.7 seconds
Started Mar 14 01:17:23 PM PDT 24
Finished Mar 14 01:17:54 PM PDT 24
Peak memory 212104 kb
Host smart-9ad5e1c6-8eb5-414c-ad23-189279f95c16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=381334944 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_kmac_err_chk.381334944
Directory /workspace/3.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/3.rom_ctrl_max_throughput_chk.2548451821
Short name T301
Test name
Test status
Simulation time 2428239865 ps
CPU time 11.91 seconds
Started Mar 14 01:17:19 PM PDT 24
Finished Mar 14 01:17:31 PM PDT 24
Peak memory 211092 kb
Host smart-b965a835-fd34-460f-b73d-e33de782e50d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2548451821 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_max_throughput_chk.2548451821
Directory /workspace/3.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/3.rom_ctrl_sec_cm.74361930
Short name T32
Test name
Test status
Simulation time 272996250 ps
CPU time 55.05 seconds
Started Mar 14 01:17:08 PM PDT 24
Finished Mar 14 01:18:03 PM PDT 24
Peak memory 236960 kb
Host smart-8ccad66e-2c88-42c5-9ef3-13212849d131
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74361930 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_sec_cm.74361930
Directory /workspace/3.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/3.rom_ctrl_smoke.421676639
Short name T80
Test name
Test status
Simulation time 6039082663 ps
CPU time 19.81 seconds
Started Mar 14 01:17:12 PM PDT 24
Finished Mar 14 01:17:31 PM PDT 24
Peak memory 212724 kb
Host smart-d6996f3d-67c2-46b3-9ecd-ad3de0c10a89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=421676639 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_smoke.421676639
Directory /workspace/3.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/3.rom_ctrl_stress_all.3923157940
Short name T142
Test name
Test status
Simulation time 460787073 ps
CPU time 12.77 seconds
Started Mar 14 01:17:11 PM PDT 24
Finished Mar 14 01:17:24 PM PDT 24
Peak memory 210964 kb
Host smart-f8ae85a2-9958-4819-87db-a66ff0489306
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3923157940 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 3.rom_ctrl_stress_all.3923157940
Directory /workspace/3.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/3.rom_ctrl_stress_all_with_rand_reset.913132670
Short name T52
Test name
Test status
Simulation time 40328224989 ps
CPU time 1498.47 seconds
Started Mar 14 01:17:20 PM PDT 24
Finished Mar 14 01:42:18 PM PDT 24
Peak memory 235848 kb
Host smart-43c2b435-3644-4d08-992a-147be66255f1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=913132670 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_stress_all_with_rand_reset.913132670
Directory /workspace/3.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.rom_ctrl_alert_test.3818586696
Short name T172
Test name
Test status
Simulation time 7488696723 ps
CPU time 15.51 seconds
Started Mar 14 01:17:47 PM PDT 24
Finished Mar 14 01:18:03 PM PDT 24
Peak memory 211128 kb
Host smart-5c588433-cd40-48c1-9f67-22a087fe1b46
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3818586696 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_alert_test.3818586696
Directory /workspace/30.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/30.rom_ctrl_corrupt_sig_fatal_chk.3574765862
Short name T180
Test name
Test status
Simulation time 159078676917 ps
CPU time 305.2 seconds
Started Mar 14 01:17:47 PM PDT 24
Finished Mar 14 01:22:52 PM PDT 24
Peak memory 236580 kb
Host smart-bb0811ec-bf11-4e2e-80e8-0d40d837011b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3574765862 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_
corrupt_sig_fatal_chk.3574765862
Directory /workspace/30.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/30.rom_ctrl_kmac_err_chk.3618401695
Short name T212
Test name
Test status
Simulation time 10939714676 ps
CPU time 23.66 seconds
Started Mar 14 01:17:51 PM PDT 24
Finished Mar 14 01:18:15 PM PDT 24
Peak memory 212304 kb
Host smart-b73e8692-7c7f-47f0-9a66-90cf75cd41eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3618401695 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_kmac_err_chk.3618401695
Directory /workspace/30.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/30.rom_ctrl_max_throughput_chk.2024810962
Short name T190
Test name
Test status
Simulation time 990311923 ps
CPU time 10.95 seconds
Started Mar 14 01:17:48 PM PDT 24
Finished Mar 14 01:17:59 PM PDT 24
Peak memory 211068 kb
Host smart-58fd7c81-9744-4ab2-b52c-fd057dac8f3d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2024810962 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_max_throughput_chk.2024810962
Directory /workspace/30.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/30.rom_ctrl_smoke.1569619930
Short name T350
Test name
Test status
Simulation time 4498750083 ps
CPU time 29.16 seconds
Started Mar 14 01:17:46 PM PDT 24
Finished Mar 14 01:18:16 PM PDT 24
Peak memory 211808 kb
Host smart-1ce9c4b7-c4f7-4f2d-a9d5-a439a168f4b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1569619930 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_smoke.1569619930
Directory /workspace/30.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/30.rom_ctrl_stress_all.2521775765
Short name T242
Test name
Test status
Simulation time 6776111130 ps
CPU time 16.76 seconds
Started Mar 14 01:17:51 PM PDT 24
Finished Mar 14 01:18:08 PM PDT 24
Peak memory 212156 kb
Host smart-68d1720b-4140-48fc-a144-0acaaa21631f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2521775765 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 30.rom_ctrl_stress_all.2521775765
Directory /workspace/30.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/31.rom_ctrl_alert_test.1759002051
Short name T145
Test name
Test status
Simulation time 252598943 ps
CPU time 6.1 seconds
Started Mar 14 01:17:46 PM PDT 24
Finished Mar 14 01:17:53 PM PDT 24
Peak memory 211132 kb
Host smart-1ddb22bf-03c0-4c67-b94b-b9f82233de2c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1759002051 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_alert_test.1759002051
Directory /workspace/31.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/31.rom_ctrl_corrupt_sig_fatal_chk.60684645
Short name T277
Test name
Test status
Simulation time 95075751875 ps
CPU time 297.78 seconds
Started Mar 14 01:17:51 PM PDT 24
Finished Mar 14 01:22:49 PM PDT 24
Peak memory 236800 kb
Host smart-be05e329-061b-4978-8b07-08a1dbca3bac
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=60684645 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_
sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_co
rrupt_sig_fatal_chk.60684645
Directory /workspace/31.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/31.rom_ctrl_kmac_err_chk.1942576533
Short name T231
Test name
Test status
Simulation time 5750478134 ps
CPU time 26.45 seconds
Started Mar 14 01:17:47 PM PDT 24
Finished Mar 14 01:18:13 PM PDT 24
Peak memory 211932 kb
Host smart-a163e4f2-637e-485a-ab84-bf26746bd82d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1942576533 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_kmac_err_chk.1942576533
Directory /workspace/31.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/31.rom_ctrl_max_throughput_chk.2853803079
Short name T239
Test name
Test status
Simulation time 389980312 ps
CPU time 5.42 seconds
Started Mar 14 01:17:49 PM PDT 24
Finished Mar 14 01:17:54 PM PDT 24
Peak memory 210992 kb
Host smart-4dae3758-3857-4a1b-a84b-0e659c54a630
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2853803079 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_max_throughput_chk.2853803079
Directory /workspace/31.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/31.rom_ctrl_smoke.3435502764
Short name T154
Test name
Test status
Simulation time 17591502052 ps
CPU time 36.03 seconds
Started Mar 14 01:17:48 PM PDT 24
Finished Mar 14 01:18:24 PM PDT 24
Peak memory 213476 kb
Host smart-7454d77f-b58c-4300-8e3d-9ce42826478a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3435502764 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_smoke.3435502764
Directory /workspace/31.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/31.rom_ctrl_stress_all.961553492
Short name T176
Test name
Test status
Simulation time 13010842269 ps
CPU time 30.49 seconds
Started Mar 14 01:17:46 PM PDT 24
Finished Mar 14 01:18:17 PM PDT 24
Peak memory 219248 kb
Host smart-67fb808b-5fe2-445d-8145-fc00a4e96d99
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=961553492 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 31.rom_ctrl_stress_all.961553492
Directory /workspace/31.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/31.rom_ctrl_stress_all_with_rand_reset.520922249
Short name T13
Test name
Test status
Simulation time 64576936340 ps
CPU time 2419.66 seconds
Started Mar 14 01:17:46 PM PDT 24
Finished Mar 14 01:58:07 PM PDT 24
Peak memory 238752 kb
Host smart-3a766f5a-f091-4b0c-a99c-6b96e939aecb
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=520922249 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_stress_all_with_rand_reset.520922249
Directory /workspace/31.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.rom_ctrl_alert_test.918401119
Short name T159
Test name
Test status
Simulation time 171653712 ps
CPU time 4.22 seconds
Started Mar 14 01:17:48 PM PDT 24
Finished Mar 14 01:17:53 PM PDT 24
Peak memory 211056 kb
Host smart-7253ddc4-cc52-4030-b7c2-f881a9cb661c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=918401119 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_alert_test.918401119
Directory /workspace/32.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/32.rom_ctrl_corrupt_sig_fatal_chk.1352907754
Short name T162
Test name
Test status
Simulation time 6187486087 ps
CPU time 75.66 seconds
Started Mar 14 01:17:47 PM PDT 24
Finished Mar 14 01:19:03 PM PDT 24
Peak memory 237184 kb
Host smart-0a589041-c7ae-4c75-a73f-e60205d7f63d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1352907754 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_
corrupt_sig_fatal_chk.1352907754
Directory /workspace/32.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/32.rom_ctrl_kmac_err_chk.1065076795
Short name T309
Test name
Test status
Simulation time 333985083 ps
CPU time 9.39 seconds
Started Mar 14 01:17:44 PM PDT 24
Finished Mar 14 01:17:54 PM PDT 24
Peak memory 211748 kb
Host smart-f40db0e1-31e1-47b1-88c0-6a07310ac217
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1065076795 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_kmac_err_chk.1065076795
Directory /workspace/32.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/32.rom_ctrl_max_throughput_chk.2860635191
Short name T348
Test name
Test status
Simulation time 1942011242 ps
CPU time 15.79 seconds
Started Mar 14 01:17:46 PM PDT 24
Finished Mar 14 01:18:02 PM PDT 24
Peak memory 211044 kb
Host smart-e5fe2597-9a90-44d6-8eab-211baeb5d3ab
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2860635191 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_max_throughput_chk.2860635191
Directory /workspace/32.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/32.rom_ctrl_smoke.3258015364
Short name T76
Test name
Test status
Simulation time 3303810245 ps
CPU time 32.87 seconds
Started Mar 14 01:17:50 PM PDT 24
Finished Mar 14 01:18:23 PM PDT 24
Peak memory 218900 kb
Host smart-27e7ab74-1b93-4837-8b29-93f7c3dd662e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3258015364 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_smoke.3258015364
Directory /workspace/32.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/32.rom_ctrl_stress_all.857321642
Short name T192
Test name
Test status
Simulation time 9049342277 ps
CPU time 27.67 seconds
Started Mar 14 01:17:48 PM PDT 24
Finished Mar 14 01:18:16 PM PDT 24
Peak memory 215256 kb
Host smart-9f00ca51-8507-4c61-9820-2b921620b602
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=857321642 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 32.rom_ctrl_stress_all.857321642
Directory /workspace/32.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/33.rom_ctrl_alert_test.3550796350
Short name T137
Test name
Test status
Simulation time 4342721319 ps
CPU time 9.05 seconds
Started Mar 14 01:17:50 PM PDT 24
Finished Mar 14 01:18:00 PM PDT 24
Peak memory 211156 kb
Host smart-1d2d6447-1c9e-413e-a5a2-76215c8ef905
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3550796350 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_alert_test.3550796350
Directory /workspace/33.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/33.rom_ctrl_corrupt_sig_fatal_chk.3252178459
Short name T213
Test name
Test status
Simulation time 5414960897 ps
CPU time 102.04 seconds
Started Mar 14 01:17:48 PM PDT 24
Finished Mar 14 01:19:31 PM PDT 24
Peak memory 233936 kb
Host smart-7ffebfce-eaeb-40d5-80bb-3d1ff6cc524d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3252178459 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_
corrupt_sig_fatal_chk.3252178459
Directory /workspace/33.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/33.rom_ctrl_kmac_err_chk.1674489351
Short name T322
Test name
Test status
Simulation time 1588401671 ps
CPU time 12.23 seconds
Started Mar 14 01:17:48 PM PDT 24
Finished Mar 14 01:18:00 PM PDT 24
Peak memory 212748 kb
Host smart-c916ea64-5466-42ab-9571-e8fbc09b0c64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1674489351 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_kmac_err_chk.1674489351
Directory /workspace/33.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/33.rom_ctrl_max_throughput_chk.823542323
Short name T284
Test name
Test status
Simulation time 1455534650 ps
CPU time 13.2 seconds
Started Mar 14 01:17:55 PM PDT 24
Finished Mar 14 01:18:09 PM PDT 24
Peak memory 211068 kb
Host smart-2d21a940-c322-474f-a9fc-518906f4224c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=823542323 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_max_throughput_chk.823542323
Directory /workspace/33.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/33.rom_ctrl_smoke.2203558476
Short name T243
Test name
Test status
Simulation time 623865725 ps
CPU time 14.23 seconds
Started Mar 14 01:17:51 PM PDT 24
Finished Mar 14 01:18:06 PM PDT 24
Peak memory 219220 kb
Host smart-2e31da60-783c-47a9-aacb-bf9f15f0a333
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2203558476 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_smoke.2203558476
Directory /workspace/33.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/33.rom_ctrl_stress_all.2436654232
Short name T235
Test name
Test status
Simulation time 8713222173 ps
CPU time 53.2 seconds
Started Mar 14 01:17:49 PM PDT 24
Finished Mar 14 01:18:43 PM PDT 24
Peak memory 219312 kb
Host smart-07b27998-11b0-48b3-b40c-ec9879c7cbac
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2436654232 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 33.rom_ctrl_stress_all.2436654232
Directory /workspace/33.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/34.rom_ctrl_alert_test.264616934
Short name T286
Test name
Test status
Simulation time 833998384 ps
CPU time 6.13 seconds
Started Mar 14 01:17:48 PM PDT 24
Finished Mar 14 01:17:54 PM PDT 24
Peak memory 211044 kb
Host smart-b2ebeca7-d773-41d7-b40c-28e5f302217a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=264616934 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_alert_test.264616934
Directory /workspace/34.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/34.rom_ctrl_corrupt_sig_fatal_chk.1631311119
Short name T355
Test name
Test status
Simulation time 266159580060 ps
CPU time 391.72 seconds
Started Mar 14 01:17:50 PM PDT 24
Finished Mar 14 01:24:22 PM PDT 24
Peak memory 239064 kb
Host smart-6fde12ac-3f14-4d3c-a1d4-2c85b3f4e8bd
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1631311119 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_
corrupt_sig_fatal_chk.1631311119
Directory /workspace/34.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/34.rom_ctrl_max_throughput_chk.22639018
Short name T271
Test name
Test status
Simulation time 2441981175 ps
CPU time 12.59 seconds
Started Mar 14 01:17:49 PM PDT 24
Finished Mar 14 01:18:01 PM PDT 24
Peak memory 211048 kb
Host smart-e99522ef-d6f4-4969-9a78-179cfa0553bf
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=22639018 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_max_throughput_chk.22639018
Directory /workspace/34.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/34.rom_ctrl_smoke.2202930431
Short name T211
Test name
Test status
Simulation time 16408314787 ps
CPU time 40.94 seconds
Started Mar 14 01:17:49 PM PDT 24
Finished Mar 14 01:18:30 PM PDT 24
Peak memory 213916 kb
Host smart-3a863870-5baa-4844-aecd-64e0d09a97e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2202930431 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_smoke.2202930431
Directory /workspace/34.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/34.rom_ctrl_stress_all.885517576
Short name T204
Test name
Test status
Simulation time 4242049118 ps
CPU time 12.16 seconds
Started Mar 14 01:17:50 PM PDT 24
Finished Mar 14 01:18:02 PM PDT 24
Peak memory 211072 kb
Host smart-1b8442a1-09d1-4c35-bd23-ffd0de09c448
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=885517576 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 34.rom_ctrl_stress_all.885517576
Directory /workspace/34.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/35.rom_ctrl_alert_test.2935200008
Short name T144
Test name
Test status
Simulation time 4965287826 ps
CPU time 11.46 seconds
Started Mar 14 01:17:55 PM PDT 24
Finished Mar 14 01:18:06 PM PDT 24
Peak memory 211232 kb
Host smart-8de87346-41d3-47dc-a3b8-a793fca88209
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2935200008 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_alert_test.2935200008
Directory /workspace/35.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/35.rom_ctrl_corrupt_sig_fatal_chk.663469909
Short name T28
Test name
Test status
Simulation time 12042644889 ps
CPU time 165.25 seconds
Started Mar 14 01:17:51 PM PDT 24
Finished Mar 14 01:20:37 PM PDT 24
Peak memory 212640 kb
Host smart-aefcf005-a5c7-4386-8df7-7a812834ca4b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=663469909 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_c
orrupt_sig_fatal_chk.663469909
Directory /workspace/35.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/35.rom_ctrl_max_throughput_chk.3920768318
Short name T315
Test name
Test status
Simulation time 5706418238 ps
CPU time 13.35 seconds
Started Mar 14 01:17:48 PM PDT 24
Finished Mar 14 01:18:01 PM PDT 24
Peak memory 211028 kb
Host smart-2ef2e045-4a5a-47cb-9776-733872a2cf53
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3920768318 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_max_throughput_chk.3920768318
Directory /workspace/35.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/35.rom_ctrl_smoke.663133351
Short name T113
Test name
Test status
Simulation time 13064521554 ps
CPU time 28.56 seconds
Started Mar 14 01:17:51 PM PDT 24
Finished Mar 14 01:18:20 PM PDT 24
Peak memory 219412 kb
Host smart-30f49ba0-d6d0-4374-8d6b-df4b855aa0f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=663133351 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_smoke.663133351
Directory /workspace/35.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/35.rom_ctrl_stress_all.1768058374
Short name T129
Test name
Test status
Simulation time 4274402206 ps
CPU time 37.97 seconds
Started Mar 14 01:17:51 PM PDT 24
Finished Mar 14 01:18:29 PM PDT 24
Peak memory 219348 kb
Host smart-b9b267d2-5724-445c-a85b-f76a6a5bbffc
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1768058374 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 35.rom_ctrl_stress_all.1768058374
Directory /workspace/35.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/36.rom_ctrl_alert_test.3285531240
Short name T324
Test name
Test status
Simulation time 1267637290 ps
CPU time 11.54 seconds
Started Mar 14 01:17:51 PM PDT 24
Finished Mar 14 01:18:03 PM PDT 24
Peak memory 211108 kb
Host smart-9661629f-6583-4e53-ac57-6845ce52c841
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3285531240 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_alert_test.3285531240
Directory /workspace/36.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/36.rom_ctrl_corrupt_sig_fatal_chk.3957264362
Short name T364
Test name
Test status
Simulation time 296610161899 ps
CPU time 427.9 seconds
Started Mar 14 01:17:49 PM PDT 24
Finished Mar 14 01:24:57 PM PDT 24
Peak memory 236568 kb
Host smart-52ccee4a-a1a5-4389-a69c-2ebbf6d48bb2
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3957264362 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_
corrupt_sig_fatal_chk.3957264362
Directory /workspace/36.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/36.rom_ctrl_kmac_err_chk.425186559
Short name T361
Test name
Test status
Simulation time 3118712527 ps
CPU time 18.9 seconds
Started Mar 14 01:17:49 PM PDT 24
Finished Mar 14 01:18:09 PM PDT 24
Peak memory 211700 kb
Host smart-50ea9a13-8528-4e6d-83a1-e889b99ccabe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=425186559 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_kmac_err_chk.425186559
Directory /workspace/36.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/36.rom_ctrl_max_throughput_chk.2392658468
Short name T255
Test name
Test status
Simulation time 1935677338 ps
CPU time 16.21 seconds
Started Mar 14 01:17:48 PM PDT 24
Finished Mar 14 01:18:04 PM PDT 24
Peak memory 211028 kb
Host smart-3cf7d283-6609-420a-a525-f173c19bc898
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2392658468 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_max_throughput_chk.2392658468
Directory /workspace/36.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/36.rom_ctrl_smoke.2757517266
Short name T251
Test name
Test status
Simulation time 15627724331 ps
CPU time 29.76 seconds
Started Mar 14 01:17:49 PM PDT 24
Finished Mar 14 01:18:20 PM PDT 24
Peak memory 213808 kb
Host smart-ae936dbe-c530-4a6c-ace8-cb44b2052163
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2757517266 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_smoke.2757517266
Directory /workspace/36.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/36.rom_ctrl_stress_all.3150991125
Short name T293
Test name
Test status
Simulation time 21430663282 ps
CPU time 67.07 seconds
Started Mar 14 01:17:49 PM PDT 24
Finished Mar 14 01:18:56 PM PDT 24
Peak memory 216936 kb
Host smart-045d68a0-ff75-4440-93cb-2aa36f69a6eb
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3150991125 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 36.rom_ctrl_stress_all.3150991125
Directory /workspace/36.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/37.rom_ctrl_alert_test.1287590722
Short name T139
Test name
Test status
Simulation time 2780230388 ps
CPU time 12.55 seconds
Started Mar 14 01:17:59 PM PDT 24
Finished Mar 14 01:18:12 PM PDT 24
Peak memory 211168 kb
Host smart-40e60b4d-abaa-4385-9784-659e612f0e30
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1287590722 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_alert_test.1287590722
Directory /workspace/37.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/37.rom_ctrl_corrupt_sig_fatal_chk.947024682
Short name T216
Test name
Test status
Simulation time 70385248788 ps
CPU time 395.49 seconds
Started Mar 14 01:18:01 PM PDT 24
Finished Mar 14 01:24:36 PM PDT 24
Peak memory 233556 kb
Host smart-a49e4597-6800-41cd-b2a0-c62be8905467
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=947024682 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_c
orrupt_sig_fatal_chk.947024682
Directory /workspace/37.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/37.rom_ctrl_kmac_err_chk.1922608332
Short name T359
Test name
Test status
Simulation time 2925367128 ps
CPU time 25.66 seconds
Started Mar 14 01:18:09 PM PDT 24
Finished Mar 14 01:18:35 PM PDT 24
Peak memory 212052 kb
Host smart-921abf27-1987-4aac-b622-a2be2c868d72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1922608332 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_kmac_err_chk.1922608332
Directory /workspace/37.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/37.rom_ctrl_max_throughput_chk.710880829
Short name T141
Test name
Test status
Simulation time 605625312 ps
CPU time 9.13 seconds
Started Mar 14 01:17:57 PM PDT 24
Finished Mar 14 01:18:06 PM PDT 24
Peak memory 211064 kb
Host smart-4ebcfc81-3b69-4c15-8ec6-3642db9093a8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=710880829 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_max_throughput_chk.710880829
Directory /workspace/37.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/37.rom_ctrl_smoke.3907921357
Short name T349
Test name
Test status
Simulation time 334749455 ps
CPU time 10.12 seconds
Started Mar 14 01:18:00 PM PDT 24
Finished Mar 14 01:18:10 PM PDT 24
Peak memory 219160 kb
Host smart-f6d487a8-ecc5-4a7d-b06c-9e752edf609e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3907921357 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_smoke.3907921357
Directory /workspace/37.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/37.rom_ctrl_stress_all.1133767359
Short name T91
Test name
Test status
Simulation time 1429581442 ps
CPU time 7.39 seconds
Started Mar 14 01:18:01 PM PDT 24
Finished Mar 14 01:18:09 PM PDT 24
Peak memory 210992 kb
Host smart-d4312a74-f11a-4605-a80c-5f11c21b614e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1133767359 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 37.rom_ctrl_stress_all.1133767359
Directory /workspace/37.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/38.rom_ctrl_alert_test.2292134380
Short name T311
Test name
Test status
Simulation time 347048401 ps
CPU time 4.2 seconds
Started Mar 14 01:18:02 PM PDT 24
Finished Mar 14 01:18:06 PM PDT 24
Peak memory 211124 kb
Host smart-e8d0654a-969e-4e29-b88e-3102b849801a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2292134380 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_alert_test.2292134380
Directory /workspace/38.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/38.rom_ctrl_corrupt_sig_fatal_chk.2410385744
Short name T49
Test name
Test status
Simulation time 104354855653 ps
CPU time 266.19 seconds
Started Mar 14 01:18:03 PM PDT 24
Finished Mar 14 01:22:30 PM PDT 24
Peak memory 211284 kb
Host smart-a3bf7fb9-bfae-4f12-9ba0-3bbecc4ed79a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2410385744 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_
corrupt_sig_fatal_chk.2410385744
Directory /workspace/38.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/38.rom_ctrl_kmac_err_chk.1907020738
Short name T93
Test name
Test status
Simulation time 665700654 ps
CPU time 9.36 seconds
Started Mar 14 01:18:02 PM PDT 24
Finished Mar 14 01:18:11 PM PDT 24
Peak memory 211672 kb
Host smart-f16ad8da-80e8-4179-aac9-61735d40352b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1907020738 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_kmac_err_chk.1907020738
Directory /workspace/38.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/38.rom_ctrl_max_throughput_chk.3153947918
Short name T110
Test name
Test status
Simulation time 1357560119 ps
CPU time 10.1 seconds
Started Mar 14 01:18:04 PM PDT 24
Finished Mar 14 01:18:14 PM PDT 24
Peak memory 211004 kb
Host smart-76aa1373-b8db-41e4-8040-a3f906f2d31b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3153947918 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_max_throughput_chk.3153947918
Directory /workspace/38.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/38.rom_ctrl_smoke.82280542
Short name T363
Test name
Test status
Simulation time 5574247613 ps
CPU time 27.43 seconds
Started Mar 14 01:18:04 PM PDT 24
Finished Mar 14 01:18:32 PM PDT 24
Peak memory 219308 kb
Host smart-9afed1b0-82fa-41f0-a0de-9c25f666d51f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=82280542 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_smoke.82280542
Directory /workspace/38.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/38.rom_ctrl_stress_all.2337135650
Short name T19
Test name
Test status
Simulation time 24674714732 ps
CPU time 45.28 seconds
Started Mar 14 01:18:01 PM PDT 24
Finished Mar 14 01:18:47 PM PDT 24
Peak memory 219200 kb
Host smart-fde2fcfb-1a44-4e28-bfc5-37539151065d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2337135650 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 38.rom_ctrl_stress_all.2337135650
Directory /workspace/38.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/38.rom_ctrl_stress_all_with_rand_reset.75725336
Short name T56
Test name
Test status
Simulation time 242729772547 ps
CPU time 1553.53 seconds
Started Mar 14 01:17:59 PM PDT 24
Finished Mar 14 01:43:53 PM PDT 24
Peak memory 235860 kb
Host smart-eeb20b3c-6769-43df-b026-c77dea8c0bea
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75725336 -assert nopos
tproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_stress_all_with_rand_reset.75725336
Directory /workspace/38.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.rom_ctrl_alert_test.3016465831
Short name T292
Test name
Test status
Simulation time 10039016628 ps
CPU time 9.1 seconds
Started Mar 14 01:18:04 PM PDT 24
Finished Mar 14 01:18:13 PM PDT 24
Peak memory 211160 kb
Host smart-b1fba0c4-c972-4798-aed4-23289f45c165
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3016465831 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_alert_test.3016465831
Directory /workspace/39.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/39.rom_ctrl_corrupt_sig_fatal_chk.422901174
Short name T125
Test name
Test status
Simulation time 42132329506 ps
CPU time 240.73 seconds
Started Mar 14 01:18:02 PM PDT 24
Finished Mar 14 01:22:04 PM PDT 24
Peak memory 212316 kb
Host smart-2752e9b0-ef70-42f3-b409-72bae800607c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=422901174 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_c
orrupt_sig_fatal_chk.422901174
Directory /workspace/39.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/39.rom_ctrl_kmac_err_chk.1450792391
Short name T357
Test name
Test status
Simulation time 7927877026 ps
CPU time 22.33 seconds
Started Mar 14 01:17:59 PM PDT 24
Finished Mar 14 01:18:22 PM PDT 24
Peak memory 211252 kb
Host smart-1e257da2-2187-47eb-88df-b903cf20a486
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1450792391 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_kmac_err_chk.1450792391
Directory /workspace/39.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/39.rom_ctrl_max_throughput_chk.3997584875
Short name T267
Test name
Test status
Simulation time 99350604 ps
CPU time 5.5 seconds
Started Mar 14 01:18:02 PM PDT 24
Finished Mar 14 01:18:08 PM PDT 24
Peak memory 211000 kb
Host smart-de1b0a5a-9910-4a1e-9065-6c02f7b56bae
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3997584875 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_max_throughput_chk.3997584875
Directory /workspace/39.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/39.rom_ctrl_smoke.3827070608
Short name T151
Test name
Test status
Simulation time 10083781274 ps
CPU time 21.58 seconds
Started Mar 14 01:18:02 PM PDT 24
Finished Mar 14 01:18:24 PM PDT 24
Peak memory 219372 kb
Host smart-81fe87b9-208f-4e45-b799-a9cb3a072faa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3827070608 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_smoke.3827070608
Directory /workspace/39.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/39.rom_ctrl_stress_all.4048489640
Short name T182
Test name
Test status
Simulation time 5203803217 ps
CPU time 58.97 seconds
Started Mar 14 01:17:57 PM PDT 24
Finished Mar 14 01:18:56 PM PDT 24
Peak memory 215952 kb
Host smart-beac81de-be0a-43b0-a354-222c4081f871
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4048489640 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 39.rom_ctrl_stress_all.4048489640
Directory /workspace/39.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/4.rom_ctrl_alert_test.488252993
Short name T189
Test name
Test status
Simulation time 1546904527 ps
CPU time 13 seconds
Started Mar 14 01:17:19 PM PDT 24
Finished Mar 14 01:17:32 PM PDT 24
Peak memory 211104 kb
Host smart-8fd7573f-3aec-417f-809a-03186eeb8e20
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=488252993 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_alert_test.488252993
Directory /workspace/4.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/4.rom_ctrl_corrupt_sig_fatal_chk.3705068026
Short name T186
Test name
Test status
Simulation time 15526540555 ps
CPU time 278.69 seconds
Started Mar 14 01:17:22 PM PDT 24
Finished Mar 14 01:22:01 PM PDT 24
Peak memory 230736 kb
Host smart-93192047-b59c-461d-bf71-78e720323f45
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3705068026 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_c
orrupt_sig_fatal_chk.3705068026
Directory /workspace/4.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/4.rom_ctrl_kmac_err_chk.741089113
Short name T5
Test name
Test status
Simulation time 3574636233 ps
CPU time 24.7 seconds
Started Mar 14 01:17:19 PM PDT 24
Finished Mar 14 01:17:44 PM PDT 24
Peak memory 211840 kb
Host smart-4ca3afe8-d0a8-4c27-a9ec-70d6b1ea2a87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=741089113 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_kmac_err_chk.741089113
Directory /workspace/4.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/4.rom_ctrl_max_throughput_chk.1043734035
Short name T96
Test name
Test status
Simulation time 99990723 ps
CPU time 5.78 seconds
Started Mar 14 01:17:22 PM PDT 24
Finished Mar 14 01:17:28 PM PDT 24
Peak memory 211068 kb
Host smart-143e90a8-b36f-4369-81e9-02e09294bed1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1043734035 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_max_throughput_chk.1043734035
Directory /workspace/4.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/4.rom_ctrl_sec_cm.3519876170
Short name T31
Test name
Test status
Simulation time 3185478675 ps
CPU time 107.69 seconds
Started Mar 14 01:17:18 PM PDT 24
Finished Mar 14 01:19:06 PM PDT 24
Peak memory 233580 kb
Host smart-d03c376b-4005-4c45-8b1f-1edeb6beb195
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3519876170 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_sec_cm.3519876170
Directory /workspace/4.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/4.rom_ctrl_smoke.2839954900
Short name T158
Test name
Test status
Simulation time 180806271 ps
CPU time 9.54 seconds
Started Mar 14 01:17:21 PM PDT 24
Finished Mar 14 01:17:31 PM PDT 24
Peak memory 213004 kb
Host smart-dccea607-ef56-4e5e-ad31-8571eec06657
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2839954900 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_smoke.2839954900
Directory /workspace/4.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/4.rom_ctrl_stress_all.1180725528
Short name T128
Test name
Test status
Simulation time 11279215326 ps
CPU time 26.66 seconds
Started Mar 14 01:17:20 PM PDT 24
Finished Mar 14 01:17:47 PM PDT 24
Peak memory 214440 kb
Host smart-2935205c-1351-47f2-b4eb-eeb65c91eac7
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1180725528 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 4.rom_ctrl_stress_all.1180725528
Directory /workspace/4.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/40.rom_ctrl_alert_test.2484926446
Short name T35
Test name
Test status
Simulation time 660662082 ps
CPU time 8.65 seconds
Started Mar 14 01:18:01 PM PDT 24
Finished Mar 14 01:18:10 PM PDT 24
Peak memory 211084 kb
Host smart-dc087d65-4918-4984-ba07-1dc0c03b6829
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2484926446 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_alert_test.2484926446
Directory /workspace/40.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/40.rom_ctrl_corrupt_sig_fatal_chk.3352307187
Short name T288
Test name
Test status
Simulation time 27247012370 ps
CPU time 123.35 seconds
Started Mar 14 01:18:02 PM PDT 24
Finished Mar 14 01:20:06 PM PDT 24
Peak memory 236704 kb
Host smart-c03b4fca-4982-4b5e-9027-8dde26e195e5
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3352307187 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_
corrupt_sig_fatal_chk.3352307187
Directory /workspace/40.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/40.rom_ctrl_kmac_err_chk.758917904
Short name T132
Test name
Test status
Simulation time 1082093878 ps
CPU time 10.73 seconds
Started Mar 14 01:18:06 PM PDT 24
Finished Mar 14 01:18:17 PM PDT 24
Peak memory 211656 kb
Host smart-236e680b-e8c7-4622-ae0d-e3083a47d075
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=758917904 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_kmac_err_chk.758917904
Directory /workspace/40.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/40.rom_ctrl_max_throughput_chk.658014000
Short name T258
Test name
Test status
Simulation time 204042305 ps
CPU time 5.63 seconds
Started Mar 14 01:18:00 PM PDT 24
Finished Mar 14 01:18:06 PM PDT 24
Peak memory 211024 kb
Host smart-af1ab118-d63f-4557-b912-faddf9120af7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=658014000 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_max_throughput_chk.658014000
Directory /workspace/40.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/40.rom_ctrl_smoke.1334448886
Short name T331
Test name
Test status
Simulation time 6159165772 ps
CPU time 29.41 seconds
Started Mar 14 01:18:06 PM PDT 24
Finished Mar 14 01:18:36 PM PDT 24
Peak memory 214220 kb
Host smart-14cabcbe-85f7-4054-9e4b-12718ef7a134
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1334448886 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_smoke.1334448886
Directory /workspace/40.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/40.rom_ctrl_stress_all.2890061646
Short name T155
Test name
Test status
Simulation time 4519090470 ps
CPU time 54.76 seconds
Started Mar 14 01:18:00 PM PDT 24
Finished Mar 14 01:18:55 PM PDT 24
Peak memory 216228 kb
Host smart-3e70c870-67dc-4637-9fb5-2f54cfc5804b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2890061646 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 40.rom_ctrl_stress_all.2890061646
Directory /workspace/40.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/40.rom_ctrl_stress_all_with_rand_reset.2499926079
Short name T55
Test name
Test status
Simulation time 27216805005 ps
CPU time 1678.78 seconds
Started Mar 14 01:18:00 PM PDT 24
Finished Mar 14 01:45:59 PM PDT 24
Peak memory 235368 kb
Host smart-2e3779b8-26d3-46a5-b094-021afedf216d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2499926079 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_stress_all_with_rand_reset.2499926079
Directory /workspace/40.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.rom_ctrl_alert_test.907960418
Short name T160
Test name
Test status
Simulation time 1372596940 ps
CPU time 12.99 seconds
Started Mar 14 01:18:03 PM PDT 24
Finished Mar 14 01:18:16 PM PDT 24
Peak memory 211032 kb
Host smart-92ed441d-a4c3-4fcb-99cc-d8e7bf45a155
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=907960418 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_alert_test.907960418
Directory /workspace/41.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/41.rom_ctrl_corrupt_sig_fatal_chk.3135925419
Short name T265
Test name
Test status
Simulation time 20461641965 ps
CPU time 114.92 seconds
Started Mar 14 01:18:10 PM PDT 24
Finished Mar 14 01:20:05 PM PDT 24
Peak memory 237976 kb
Host smart-1989fd8b-2fa8-4b59-bee0-ab13915a343b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3135925419 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_
corrupt_sig_fatal_chk.3135925419
Directory /workspace/41.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/41.rom_ctrl_kmac_err_chk.471809134
Short name T341
Test name
Test status
Simulation time 333930629 ps
CPU time 9.22 seconds
Started Mar 14 01:18:03 PM PDT 24
Finished Mar 14 01:18:13 PM PDT 24
Peak memory 211724 kb
Host smart-26ae39de-4b3e-4c91-ba32-01b137dfe9b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=471809134 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_kmac_err_chk.471809134
Directory /workspace/41.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/41.rom_ctrl_smoke.3823452976
Short name T360
Test name
Test status
Simulation time 3444105770 ps
CPU time 40.6 seconds
Started Mar 14 01:18:07 PM PDT 24
Finished Mar 14 01:18:48 PM PDT 24
Peak memory 213344 kb
Host smart-e04cfb3c-c8a6-4b73-a3d8-174a2200891b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3823452976 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_smoke.3823452976
Directory /workspace/41.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/41.rom_ctrl_stress_all.3451834644
Short name T36
Test name
Test status
Simulation time 6712376368 ps
CPU time 31.51 seconds
Started Mar 14 01:17:59 PM PDT 24
Finished Mar 14 01:18:31 PM PDT 24
Peak memory 215936 kb
Host smart-6f25cf44-4d96-4a25-92b0-5405cb3d4359
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3451834644 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 41.rom_ctrl_stress_all.3451834644
Directory /workspace/41.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/42.rom_ctrl_alert_test.2415415578
Short name T313
Test name
Test status
Simulation time 4371721877 ps
CPU time 12.45 seconds
Started Mar 14 01:17:58 PM PDT 24
Finished Mar 14 01:18:11 PM PDT 24
Peak memory 211184 kb
Host smart-8de027d7-0172-4aff-9d12-37bb371d9d5d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2415415578 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_alert_test.2415415578
Directory /workspace/42.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/42.rom_ctrl_corrupt_sig_fatal_chk.3227403600
Short name T200
Test name
Test status
Simulation time 1066583439 ps
CPU time 58.82 seconds
Started Mar 14 01:18:00 PM PDT 24
Finished Mar 14 01:19:00 PM PDT 24
Peak memory 227520 kb
Host smart-3005dad5-1edc-4bc2-8ea4-7daf50d82b9b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3227403600 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_
corrupt_sig_fatal_chk.3227403600
Directory /workspace/42.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/42.rom_ctrl_kmac_err_chk.610381558
Short name T10
Test name
Test status
Simulation time 4267182051 ps
CPU time 21.85 seconds
Started Mar 14 01:18:04 PM PDT 24
Finished Mar 14 01:18:26 PM PDT 24
Peak memory 211872 kb
Host smart-dee8d5cc-b38f-458d-850f-6ad4e013ad23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=610381558 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_kmac_err_chk.610381558
Directory /workspace/42.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/42.rom_ctrl_max_throughput_chk.1191939376
Short name T241
Test name
Test status
Simulation time 8229349197 ps
CPU time 16.82 seconds
Started Mar 14 01:18:02 PM PDT 24
Finished Mar 14 01:18:19 PM PDT 24
Peak memory 211176 kb
Host smart-4a890447-edb7-4de4-92ff-fa4aa0939fdb
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1191939376 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_max_throughput_chk.1191939376
Directory /workspace/42.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/42.rom_ctrl_smoke.1750079506
Short name T306
Test name
Test status
Simulation time 3296800662 ps
CPU time 19.89 seconds
Started Mar 14 01:18:02 PM PDT 24
Finished Mar 14 01:18:22 PM PDT 24
Peak memory 213188 kb
Host smart-46b8f46f-3b93-40d6-9fab-67e843e88c31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1750079506 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_smoke.1750079506
Directory /workspace/42.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/42.rom_ctrl_stress_all.1343306720
Short name T327
Test name
Test status
Simulation time 1981383340 ps
CPU time 21.16 seconds
Started Mar 14 01:18:03 PM PDT 24
Finished Mar 14 01:18:25 PM PDT 24
Peak memory 211784 kb
Host smart-8cd38bd3-ac4f-43f4-80bf-35bc5daaeb3b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1343306720 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 42.rom_ctrl_stress_all.1343306720
Directory /workspace/42.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/42.rom_ctrl_stress_all_with_rand_reset.3521576941
Short name T276
Test name
Test status
Simulation time 11663396149 ps
CPU time 428.28 seconds
Started Mar 14 01:18:05 PM PDT 24
Finished Mar 14 01:25:13 PM PDT 24
Peak memory 227692 kb
Host smart-0279286e-44b1-4a67-b0d9-f297a3cf3ec0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3521576941 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_stress_all_with_rand_reset.3521576941
Directory /workspace/42.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.rom_ctrl_alert_test.1032913379
Short name T203
Test name
Test status
Simulation time 692845640 ps
CPU time 8.77 seconds
Started Mar 14 01:17:56 PM PDT 24
Finished Mar 14 01:18:05 PM PDT 24
Peak memory 211100 kb
Host smart-0fcb5d91-ed8b-469f-8de9-9d32f41f67be
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1032913379 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_alert_test.1032913379
Directory /workspace/43.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/43.rom_ctrl_corrupt_sig_fatal_chk.2863666913
Short name T48
Test name
Test status
Simulation time 33273285713 ps
CPU time 189.4 seconds
Started Mar 14 01:18:08 PM PDT 24
Finished Mar 14 01:21:17 PM PDT 24
Peak memory 237720 kb
Host smart-6d0757c3-d20c-40b1-8df1-5702d5cbb2b7
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2863666913 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_
corrupt_sig_fatal_chk.2863666913
Directory /workspace/43.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/43.rom_ctrl_kmac_err_chk.3416654031
Short name T169
Test name
Test status
Simulation time 7989873650 ps
CPU time 32.23 seconds
Started Mar 14 01:18:04 PM PDT 24
Finished Mar 14 01:18:37 PM PDT 24
Peak memory 213628 kb
Host smart-4e14d895-1994-443d-b2cc-a8a10a5a73df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3416654031 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_kmac_err_chk.3416654031
Directory /workspace/43.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/43.rom_ctrl_max_throughput_chk.2414989656
Short name T157
Test name
Test status
Simulation time 122747766 ps
CPU time 5.5 seconds
Started Mar 14 01:18:06 PM PDT 24
Finished Mar 14 01:18:12 PM PDT 24
Peak memory 211084 kb
Host smart-73a3e84c-bae8-473e-b41e-b7c66f43d2f7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2414989656 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_max_throughput_chk.2414989656
Directory /workspace/43.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/43.rom_ctrl_smoke.3930053090
Short name T273
Test name
Test status
Simulation time 2234232374 ps
CPU time 25.46 seconds
Started Mar 14 01:18:09 PM PDT 24
Finished Mar 14 01:18:35 PM PDT 24
Peak memory 219300 kb
Host smart-b2e0e249-f6bd-4a4b-be4d-348b7d1e84be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3930053090 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_smoke.3930053090
Directory /workspace/43.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/43.rom_ctrl_stress_all.2628690909
Short name T77
Test name
Test status
Simulation time 13497913690 ps
CPU time 125.5 seconds
Started Mar 14 01:18:01 PM PDT 24
Finished Mar 14 01:20:06 PM PDT 24
Peak memory 216884 kb
Host smart-46030239-5c5f-4e16-a10f-64e29cd9b003
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2628690909 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 43.rom_ctrl_stress_all.2628690909
Directory /workspace/43.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/43.rom_ctrl_stress_all_with_rand_reset.3062916112
Short name T330
Test name
Test status
Simulation time 44320325822 ps
CPU time 1644.33 seconds
Started Mar 14 01:18:03 PM PDT 24
Finished Mar 14 01:45:28 PM PDT 24
Peak memory 235860 kb
Host smart-73ed6c7a-aadf-4c9e-b006-9c252948ddbd
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3062916112 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_stress_all_with_rand_reset.3062916112
Directory /workspace/43.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.rom_ctrl_alert_test.3366060895
Short name T164
Test name
Test status
Simulation time 1416406348 ps
CPU time 12.42 seconds
Started Mar 14 01:18:04 PM PDT 24
Finished Mar 14 01:18:17 PM PDT 24
Peak memory 211064 kb
Host smart-ff4156e8-730b-450d-8362-fd40dda1fd75
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3366060895 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_alert_test.3366060895
Directory /workspace/44.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/44.rom_ctrl_corrupt_sig_fatal_chk.1071441818
Short name T319
Test name
Test status
Simulation time 36095446935 ps
CPU time 225.5 seconds
Started Mar 14 01:18:06 PM PDT 24
Finished Mar 14 01:21:52 PM PDT 24
Peak memory 230696 kb
Host smart-3d1422ee-03e7-41da-9a08-2219b1a0da48
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1071441818 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_
corrupt_sig_fatal_chk.1071441818
Directory /workspace/44.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/44.rom_ctrl_kmac_err_chk.813114466
Short name T220
Test name
Test status
Simulation time 4483771575 ps
CPU time 22.5 seconds
Started Mar 14 01:18:06 PM PDT 24
Finished Mar 14 01:18:29 PM PDT 24
Peak memory 212348 kb
Host smart-9edf362c-6d26-4a51-9ad6-e26af86132d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=813114466 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_kmac_err_chk.813114466
Directory /workspace/44.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/44.rom_ctrl_max_throughput_chk.2353411205
Short name T104
Test name
Test status
Simulation time 8086471245 ps
CPU time 17.23 seconds
Started Mar 14 01:18:10 PM PDT 24
Finished Mar 14 01:18:27 PM PDT 24
Peak memory 211188 kb
Host smart-1e77a218-2d99-4e8b-9e60-70cb3f90af0a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2353411205 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_max_throughput_chk.2353411205
Directory /workspace/44.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/44.rom_ctrl_smoke.786334527
Short name T285
Test name
Test status
Simulation time 10019009151 ps
CPU time 23.41 seconds
Started Mar 14 01:18:04 PM PDT 24
Finished Mar 14 01:18:28 PM PDT 24
Peak memory 213692 kb
Host smart-314d35d8-9fcc-4141-9fef-cd54d026c252
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=786334527 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_smoke.786334527
Directory /workspace/44.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/44.rom_ctrl_stress_all.33687329
Short name T78
Test name
Test status
Simulation time 1540366848 ps
CPU time 19.84 seconds
Started Mar 14 01:18:01 PM PDT 24
Finished Mar 14 01:18:21 PM PDT 24
Peak memory 215100 kb
Host smart-5a6b3ad9-6f26-4a89-89ee-d84837cc6922
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33687329 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +U
VM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n
ame 44.rom_ctrl_stress_all.33687329
Directory /workspace/44.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/44.rom_ctrl_stress_all_with_rand_reset.2507738239
Short name T312
Test name
Test status
Simulation time 24335127547 ps
CPU time 1016.43 seconds
Started Mar 14 01:18:02 PM PDT 24
Finished Mar 14 01:34:59 PM PDT 24
Peak memory 235828 kb
Host smart-2601f913-b6ad-409b-956a-2d18d12e6114
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2507738239 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_stress_all_with_rand_reset.2507738239
Directory /workspace/44.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.rom_ctrl_alert_test.3297801120
Short name T237
Test name
Test status
Simulation time 2232508272 ps
CPU time 11.01 seconds
Started Mar 14 01:18:06 PM PDT 24
Finished Mar 14 01:18:17 PM PDT 24
Peak memory 211188 kb
Host smart-456449f3-eb5c-4304-964b-c1a5b32b4c24
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3297801120 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_alert_test.3297801120
Directory /workspace/45.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/45.rom_ctrl_corrupt_sig_fatal_chk.1685765837
Short name T305
Test name
Test status
Simulation time 29703091714 ps
CPU time 172.98 seconds
Started Mar 14 01:18:03 PM PDT 24
Finished Mar 14 01:20:57 PM PDT 24
Peak memory 236720 kb
Host smart-dfa6aa6b-590a-4e5c-a057-f3d3c1029383
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1685765837 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_
corrupt_sig_fatal_chk.1685765837
Directory /workspace/45.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/45.rom_ctrl_kmac_err_chk.3826060082
Short name T256
Test name
Test status
Simulation time 6817417148 ps
CPU time 28.95 seconds
Started Mar 14 01:18:02 PM PDT 24
Finished Mar 14 01:18:32 PM PDT 24
Peak memory 211844 kb
Host smart-c4e3d5d6-7e0c-4041-925a-bd7fba3a6ad8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3826060082 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_kmac_err_chk.3826060082
Directory /workspace/45.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/45.rom_ctrl_max_throughput_chk.1731946535
Short name T281
Test name
Test status
Simulation time 1712942589 ps
CPU time 15.03 seconds
Started Mar 14 01:18:07 PM PDT 24
Finished Mar 14 01:18:22 PM PDT 24
Peak memory 211016 kb
Host smart-22e10b13-6afc-4af5-83f2-ebfca3d912d3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1731946535 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_max_throughput_chk.1731946535
Directory /workspace/45.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/45.rom_ctrl_smoke.503068613
Short name T253
Test name
Test status
Simulation time 2496968937 ps
CPU time 28.47 seconds
Started Mar 14 01:18:07 PM PDT 24
Finished Mar 14 01:18:35 PM PDT 24
Peak memory 212536 kb
Host smart-463e6aa3-7601-4de9-a9ab-bf03f084b5db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=503068613 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_smoke.503068613
Directory /workspace/45.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/45.rom_ctrl_stress_all.1964968567
Short name T105
Test name
Test status
Simulation time 3323170157 ps
CPU time 20.36 seconds
Started Mar 14 01:18:08 PM PDT 24
Finished Mar 14 01:18:28 PM PDT 24
Peak memory 219268 kb
Host smart-2c383e3b-a4e9-4525-9235-4c62fd9dc670
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1964968567 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 45.rom_ctrl_stress_all.1964968567
Directory /workspace/45.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/45.rom_ctrl_stress_all_with_rand_reset.2718576783
Short name T304
Test name
Test status
Simulation time 148476410136 ps
CPU time 7042.49 seconds
Started Mar 14 01:18:00 PM PDT 24
Finished Mar 14 03:15:23 PM PDT 24
Peak memory 235712 kb
Host smart-18302bef-acc6-49eb-8cb1-7dc997e11570
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2718576783 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_stress_all_with_rand_reset.2718576783
Directory /workspace/45.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.rom_ctrl_alert_test.1103393339
Short name T209
Test name
Test status
Simulation time 3845174993 ps
CPU time 13.19 seconds
Started Mar 14 01:18:09 PM PDT 24
Finished Mar 14 01:18:22 PM PDT 24
Peak memory 211136 kb
Host smart-8a53ed70-08c0-4dd3-b4b0-8c5e1aa8b816
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1103393339 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_alert_test.1103393339
Directory /workspace/46.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/46.rom_ctrl_corrupt_sig_fatal_chk.2355084876
Short name T244
Test name
Test status
Simulation time 2763337527 ps
CPU time 98.78 seconds
Started Mar 14 01:18:04 PM PDT 24
Finished Mar 14 01:19:43 PM PDT 24
Peak memory 221432 kb
Host smart-4db8463d-5665-4f86-95a7-b606d80bf23a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2355084876 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_
corrupt_sig_fatal_chk.2355084876
Directory /workspace/46.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/46.rom_ctrl_kmac_err_chk.1195328550
Short name T229
Test name
Test status
Simulation time 3456167080 ps
CPU time 28.39 seconds
Started Mar 14 01:18:07 PM PDT 24
Finished Mar 14 01:18:36 PM PDT 24
Peak memory 212008 kb
Host smart-6e3b61c3-9bab-40b4-a7ee-88e9dbbe71ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1195328550 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_kmac_err_chk.1195328550
Directory /workspace/46.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/46.rom_ctrl_max_throughput_chk.1416798123
Short name T257
Test name
Test status
Simulation time 5940829423 ps
CPU time 14.14 seconds
Started Mar 14 01:18:02 PM PDT 24
Finished Mar 14 01:18:16 PM PDT 24
Peak memory 211120 kb
Host smart-bf4aea3a-0213-4ead-b88b-3cb17b264ff4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1416798123 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_max_throughput_chk.1416798123
Directory /workspace/46.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/46.rom_ctrl_smoke.1075279964
Short name T280
Test name
Test status
Simulation time 861348874 ps
CPU time 16.38 seconds
Started Mar 14 01:18:03 PM PDT 24
Finished Mar 14 01:18:20 PM PDT 24
Peak memory 219164 kb
Host smart-bef86162-5f2d-43d1-9475-c8c87efb1780
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1075279964 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_smoke.1075279964
Directory /workspace/46.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/46.rom_ctrl_stress_all.2967770228
Short name T153
Test name
Test status
Simulation time 11983796129 ps
CPU time 32.7 seconds
Started Mar 14 01:18:03 PM PDT 24
Finished Mar 14 01:18:36 PM PDT 24
Peak memory 217072 kb
Host smart-c9c10e2c-c4a8-45b6-a514-1fd17dcc481a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2967770228 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 46.rom_ctrl_stress_all.2967770228
Directory /workspace/46.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/47.rom_ctrl_alert_test.723913979
Short name T296
Test name
Test status
Simulation time 4098860230 ps
CPU time 6.18 seconds
Started Mar 14 01:18:11 PM PDT 24
Finished Mar 14 01:18:17 PM PDT 24
Peak memory 211048 kb
Host smart-c37f04f3-5db8-4d8b-a6fd-af23dbf39ae7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=723913979 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_alert_test.723913979
Directory /workspace/47.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/47.rom_ctrl_corrupt_sig_fatal_chk.2995116466
Short name T219
Test name
Test status
Simulation time 23817077418 ps
CPU time 232.3 seconds
Started Mar 14 01:18:08 PM PDT 24
Finished Mar 14 01:22:00 PM PDT 24
Peak memory 228248 kb
Host smart-9f69688b-6278-4349-8ec7-73101b092835
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2995116466 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_
corrupt_sig_fatal_chk.2995116466
Directory /workspace/47.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/47.rom_ctrl_kmac_err_chk.447928666
Short name T207
Test name
Test status
Simulation time 5099993371 ps
CPU time 17.88 seconds
Started Mar 14 01:18:11 PM PDT 24
Finished Mar 14 01:18:29 PM PDT 24
Peak memory 212040 kb
Host smart-95c0c909-cd1b-444b-9769-c64037f1df99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=447928666 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_kmac_err_chk.447928666
Directory /workspace/47.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/47.rom_ctrl_max_throughput_chk.3470662136
Short name T45
Test name
Test status
Simulation time 4111830181 ps
CPU time 16.71 seconds
Started Mar 14 01:18:08 PM PDT 24
Finished Mar 14 01:18:25 PM PDT 24
Peak memory 211100 kb
Host smart-05156c81-314a-498c-9280-932231643ab2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3470662136 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_max_throughput_chk.3470662136
Directory /workspace/47.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/47.rom_ctrl_smoke.1952495522
Short name T79
Test name
Test status
Simulation time 1811548250 ps
CPU time 10.07 seconds
Started Mar 14 01:18:07 PM PDT 24
Finished Mar 14 01:18:18 PM PDT 24
Peak memory 213592 kb
Host smart-cd9f28af-a7dc-4204-9462-f031989a019c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1952495522 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_smoke.1952495522
Directory /workspace/47.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/47.rom_ctrl_stress_all.21133047
Short name T171
Test name
Test status
Simulation time 1470958897 ps
CPU time 17.52 seconds
Started Mar 14 01:18:07 PM PDT 24
Finished Mar 14 01:18:25 PM PDT 24
Peak memory 211892 kb
Host smart-803e6a04-831a-4735-bb16-7e32798e6684
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21133047 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +U
VM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n
ame 47.rom_ctrl_stress_all.21133047
Directory /workspace/47.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/48.rom_ctrl_alert_test.2947625918
Short name T275
Test name
Test status
Simulation time 4319800373 ps
CPU time 10.65 seconds
Started Mar 14 01:18:11 PM PDT 24
Finished Mar 14 01:18:21 PM PDT 24
Peak memory 211132 kb
Host smart-9f0d2733-a425-478b-8fa7-62f91fe554fb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2947625918 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_alert_test.2947625918
Directory /workspace/48.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/48.rom_ctrl_corrupt_sig_fatal_chk.3670184605
Short name T47
Test name
Test status
Simulation time 92685535967 ps
CPU time 239.08 seconds
Started Mar 14 01:17:59 PM PDT 24
Finished Mar 14 01:21:59 PM PDT 24
Peak memory 213388 kb
Host smart-4704962f-85c0-4fdf-9f45-393ebbc461f0
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3670184605 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_
corrupt_sig_fatal_chk.3670184605
Directory /workspace/48.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/48.rom_ctrl_kmac_err_chk.1456030870
Short name T345
Test name
Test status
Simulation time 7915658164 ps
CPU time 31.85 seconds
Started Mar 14 01:18:07 PM PDT 24
Finished Mar 14 01:18:39 PM PDT 24
Peak memory 211796 kb
Host smart-ccdb057b-2ec7-4ee2-a9a3-9a26218a98d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1456030870 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_kmac_err_chk.1456030870
Directory /workspace/48.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/48.rom_ctrl_max_throughput_chk.2839865959
Short name T112
Test name
Test status
Simulation time 5754108175 ps
CPU time 14.24 seconds
Started Mar 14 01:18:07 PM PDT 24
Finished Mar 14 01:18:22 PM PDT 24
Peak memory 211040 kb
Host smart-8b5c027d-0cf8-499c-acba-f417d6aeafa6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2839865959 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_max_throughput_chk.2839865959
Directory /workspace/48.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/48.rom_ctrl_smoke.4200767228
Short name T264
Test name
Test status
Simulation time 2590888823 ps
CPU time 24.74 seconds
Started Mar 14 01:18:03 PM PDT 24
Finished Mar 14 01:18:28 PM PDT 24
Peak memory 219308 kb
Host smart-0904c65e-ddc7-42d0-a7fb-61b38b8da2cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4200767228 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_smoke.4200767228
Directory /workspace/48.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/48.rom_ctrl_stress_all.4103449289
Short name T318
Test name
Test status
Simulation time 409065386 ps
CPU time 24.06 seconds
Started Mar 14 01:18:06 PM PDT 24
Finished Mar 14 01:18:31 PM PDT 24
Peak memory 216256 kb
Host smart-9268c7a7-5937-43a9-9681-2486750da568
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4103449289 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 48.rom_ctrl_stress_all.4103449289
Directory /workspace/48.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/48.rom_ctrl_stress_all_with_rand_reset.1829770058
Short name T15
Test name
Test status
Simulation time 47778131121 ps
CPU time 3587.25 seconds
Started Mar 14 01:18:11 PM PDT 24
Finished Mar 14 02:17:59 PM PDT 24
Peak memory 227588 kb
Host smart-028a23c5-20e5-4282-8648-5f2abf81fbca
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1829770058 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_stress_all_with_rand_reset.1829770058
Directory /workspace/48.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/49.rom_ctrl_alert_test.1305570823
Short name T208
Test name
Test status
Simulation time 2179080927 ps
CPU time 11.36 seconds
Started Mar 14 01:18:00 PM PDT 24
Finished Mar 14 01:18:12 PM PDT 24
Peak memory 211404 kb
Host smart-9544cbf3-e1e0-4371-a546-f1bc118742ce
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1305570823 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_alert_test.1305570823
Directory /workspace/49.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/49.rom_ctrl_corrupt_sig_fatal_chk.3184803038
Short name T225
Test name
Test status
Simulation time 43862938121 ps
CPU time 272.83 seconds
Started Mar 14 01:18:03 PM PDT 24
Finished Mar 14 01:22:36 PM PDT 24
Peak memory 228216 kb
Host smart-c18afdbd-f02b-4798-bd25-343fa3924f16
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3184803038 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_
corrupt_sig_fatal_chk.3184803038
Directory /workspace/49.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/49.rom_ctrl_kmac_err_chk.2976110700
Short name T152
Test name
Test status
Simulation time 3260059816 ps
CPU time 28 seconds
Started Mar 14 01:18:04 PM PDT 24
Finished Mar 14 01:18:33 PM PDT 24
Peak memory 211856 kb
Host smart-fc43012b-2931-4bba-b3f8-215b9f341c27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2976110700 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_kmac_err_chk.2976110700
Directory /workspace/49.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/49.rom_ctrl_max_throughput_chk.1969203670
Short name T136
Test name
Test status
Simulation time 4455663100 ps
CPU time 12.41 seconds
Started Mar 14 01:18:11 PM PDT 24
Finished Mar 14 01:18:23 PM PDT 24
Peak memory 211088 kb
Host smart-0a61650e-895a-48b9-b36c-e377c5517440
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1969203670 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_max_throughput_chk.1969203670
Directory /workspace/49.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/49.rom_ctrl_smoke.3486682248
Short name T300
Test name
Test status
Simulation time 7884376307 ps
CPU time 20.88 seconds
Started Mar 14 01:18:06 PM PDT 24
Finished Mar 14 01:18:28 PM PDT 24
Peak memory 214648 kb
Host smart-f7da2f5d-1277-4e18-83e9-452ebf4212ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3486682248 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_smoke.3486682248
Directory /workspace/49.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/5.rom_ctrl_alert_test.2617943503
Short name T316
Test name
Test status
Simulation time 4992973361 ps
CPU time 12.55 seconds
Started Mar 14 01:17:09 PM PDT 24
Finished Mar 14 01:17:22 PM PDT 24
Peak memory 211244 kb
Host smart-77fba99a-611d-40e1-a6c5-c972457e5688
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2617943503 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_alert_test.2617943503
Directory /workspace/5.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/5.rom_ctrl_corrupt_sig_fatal_chk.2343548528
Short name T290
Test name
Test status
Simulation time 16839447574 ps
CPU time 165.5 seconds
Started Mar 14 01:17:23 PM PDT 24
Finished Mar 14 01:20:09 PM PDT 24
Peak memory 227508 kb
Host smart-772357ad-f22b-49a4-aad1-4234ccd4cb19
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2343548528 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_c
orrupt_sig_fatal_chk.2343548528
Directory /workspace/5.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/5.rom_ctrl_kmac_err_chk.3729209796
Short name T133
Test name
Test status
Simulation time 765921099 ps
CPU time 14.56 seconds
Started Mar 14 01:17:19 PM PDT 24
Finished Mar 14 01:17:33 PM PDT 24
Peak memory 211108 kb
Host smart-1e1b4c21-d445-4cb0-a4e5-82215f4b846d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3729209796 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_kmac_err_chk.3729209796
Directory /workspace/5.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/5.rom_ctrl_max_throughput_chk.475405725
Short name T138
Test name
Test status
Simulation time 2782343245 ps
CPU time 12.05 seconds
Started Mar 14 01:17:17 PM PDT 24
Finished Mar 14 01:17:29 PM PDT 24
Peak memory 211064 kb
Host smart-7fe1ce8d-3032-41c0-b024-88b398d51464
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=475405725 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_max_throughput_chk.475405725
Directory /workspace/5.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/5.rom_ctrl_smoke.868629500
Short name T338
Test name
Test status
Simulation time 1737777916 ps
CPU time 22.87 seconds
Started Mar 14 01:17:20 PM PDT 24
Finished Mar 14 01:17:43 PM PDT 24
Peak memory 212160 kb
Host smart-8fdb82e0-99a6-4dfe-aedb-c6ec645f4539
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=868629500 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_smoke.868629500
Directory /workspace/5.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/5.rom_ctrl_stress_all.1447580645
Short name T197
Test name
Test status
Simulation time 3134703207 ps
CPU time 23.07 seconds
Started Mar 14 01:17:20 PM PDT 24
Finished Mar 14 01:17:43 PM PDT 24
Peak memory 219304 kb
Host smart-2bba91e5-80ca-464a-8fef-2cc0f3319b95
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1447580645 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 5.rom_ctrl_stress_all.1447580645
Directory /workspace/5.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/6.rom_ctrl_alert_test.1075145949
Short name T149
Test name
Test status
Simulation time 6847708780 ps
CPU time 9.46 seconds
Started Mar 14 01:17:19 PM PDT 24
Finished Mar 14 01:17:28 PM PDT 24
Peak memory 211220 kb
Host smart-0ff57098-f89d-494c-9d51-3c6204f7dd24
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1075145949 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_alert_test.1075145949
Directory /workspace/6.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/6.rom_ctrl_corrupt_sig_fatal_chk.3574224411
Short name T24
Test name
Test status
Simulation time 87820006966 ps
CPU time 189.6 seconds
Started Mar 14 01:17:23 PM PDT 24
Finished Mar 14 01:20:33 PM PDT 24
Peak memory 234848 kb
Host smart-3966aee9-d9e7-442d-a7ab-d428be536132
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3574224411 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_c
orrupt_sig_fatal_chk.3574224411
Directory /workspace/6.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/6.rom_ctrl_kmac_err_chk.3819829159
Short name T147
Test name
Test status
Simulation time 349756327 ps
CPU time 11.68 seconds
Started Mar 14 01:17:11 PM PDT 24
Finished Mar 14 01:17:23 PM PDT 24
Peak memory 211100 kb
Host smart-682b1d8c-96a0-4828-b926-e9a80277daa1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3819829159 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_kmac_err_chk.3819829159
Directory /workspace/6.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/6.rom_ctrl_max_throughput_chk.1598485594
Short name T167
Test name
Test status
Simulation time 103896779 ps
CPU time 5.54 seconds
Started Mar 14 01:17:20 PM PDT 24
Finished Mar 14 01:17:26 PM PDT 24
Peak memory 211076 kb
Host smart-f29ef6d8-4ee4-42cc-88b3-ab6d54013641
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1598485594 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_max_throughput_chk.1598485594
Directory /workspace/6.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/6.rom_ctrl_smoke.3450610126
Short name T222
Test name
Test status
Simulation time 26082609532 ps
CPU time 32.71 seconds
Started Mar 14 01:17:22 PM PDT 24
Finished Mar 14 01:17:55 PM PDT 24
Peak memory 219344 kb
Host smart-2c856852-ad0d-4397-a332-d1d594ffd134
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3450610126 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_smoke.3450610126
Directory /workspace/6.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/6.rom_ctrl_stress_all.2198680804
Short name T111
Test name
Test status
Simulation time 1361301923 ps
CPU time 29.55 seconds
Started Mar 14 01:17:20 PM PDT 24
Finished Mar 14 01:17:50 PM PDT 24
Peak memory 216244 kb
Host smart-4befcf89-fc72-48ab-8bef-c6c857213e28
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2198680804 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 6.rom_ctrl_stress_all.2198680804
Directory /workspace/6.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/7.rom_ctrl_alert_test.462742845
Short name T191
Test name
Test status
Simulation time 2089950481 ps
CPU time 16.55 seconds
Started Mar 14 01:17:18 PM PDT 24
Finished Mar 14 01:17:35 PM PDT 24
Peak memory 211112 kb
Host smart-77787a08-807a-49de-ba26-5b27c9c02d5b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=462742845 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_alert_test.462742845
Directory /workspace/7.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/7.rom_ctrl_corrupt_sig_fatal_chk.3720001379
Short name T161
Test name
Test status
Simulation time 2379573987 ps
CPU time 143.52 seconds
Started Mar 14 01:17:23 PM PDT 24
Finished Mar 14 01:19:47 PM PDT 24
Peak memory 230640 kb
Host smart-7bfb9681-da5a-4efa-a510-09eb9361d51f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3720001379 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_c
orrupt_sig_fatal_chk.3720001379
Directory /workspace/7.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/7.rom_ctrl_kmac_err_chk.1832710375
Short name T228
Test name
Test status
Simulation time 510857640 ps
CPU time 12.52 seconds
Started Mar 14 01:17:20 PM PDT 24
Finished Mar 14 01:17:32 PM PDT 24
Peak memory 211144 kb
Host smart-a0a85e4c-2055-4f34-b8ed-70fad4adbba9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1832710375 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_kmac_err_chk.1832710375
Directory /workspace/7.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/7.rom_ctrl_max_throughput_chk.2916659898
Short name T90
Test name
Test status
Simulation time 19067459957 ps
CPU time 11.32 seconds
Started Mar 14 01:17:18 PM PDT 24
Finished Mar 14 01:17:29 PM PDT 24
Peak memory 211152 kb
Host smart-5b59ea94-2e3b-48ae-92f5-4dd15e099a77
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2916659898 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_max_throughput_chk.2916659898
Directory /workspace/7.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/7.rom_ctrl_smoke.1671730516
Short name T342
Test name
Test status
Simulation time 15731943156 ps
CPU time 36.59 seconds
Started Mar 14 01:17:20 PM PDT 24
Finished Mar 14 01:17:57 PM PDT 24
Peak memory 219352 kb
Host smart-78aad2ce-0fb5-43d7-88b2-3d60ad5201df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1671730516 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_smoke.1671730516
Directory /workspace/7.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/7.rom_ctrl_stress_all.1067446516
Short name T260
Test name
Test status
Simulation time 5497342638 ps
CPU time 28.63 seconds
Started Mar 14 01:17:23 PM PDT 24
Finished Mar 14 01:17:52 PM PDT 24
Peak memory 217172 kb
Host smart-c91d8225-efc2-4801-b7d5-9edca917c1b1
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1067446516 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 7.rom_ctrl_stress_all.1067446516
Directory /workspace/7.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/8.rom_ctrl_alert_test.667259325
Short name T63
Test name
Test status
Simulation time 88393485 ps
CPU time 4.21 seconds
Started Mar 14 01:17:23 PM PDT 24
Finished Mar 14 01:17:27 PM PDT 24
Peak memory 211080 kb
Host smart-c2131329-008d-4a9e-a185-2e3522b932f1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=667259325 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_alert_test.667259325
Directory /workspace/8.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/8.rom_ctrl_corrupt_sig_fatal_chk.3506029630
Short name T362
Test name
Test status
Simulation time 1867783801 ps
CPU time 109.09 seconds
Started Mar 14 01:17:23 PM PDT 24
Finished Mar 14 01:19:12 PM PDT 24
Peak memory 228444 kb
Host smart-0a37e55d-e4ff-4b41-b472-1b1c2e1f9642
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3506029630 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_c
orrupt_sig_fatal_chk.3506029630
Directory /workspace/8.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/8.rom_ctrl_kmac_err_chk.1145186348
Short name T289
Test name
Test status
Simulation time 19345968471 ps
CPU time 20.13 seconds
Started Mar 14 01:17:19 PM PDT 24
Finished Mar 14 01:17:39 PM PDT 24
Peak memory 211980 kb
Host smart-181ced1f-cddd-4c74-8062-d44b30bb27d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1145186348 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_kmac_err_chk.1145186348
Directory /workspace/8.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/8.rom_ctrl_max_throughput_chk.1945122785
Short name T210
Test name
Test status
Simulation time 2473886442 ps
CPU time 17.46 seconds
Started Mar 14 01:17:20 PM PDT 24
Finished Mar 14 01:17:38 PM PDT 24
Peak memory 211128 kb
Host smart-f4a9583a-9712-46dd-86e1-2d9f4f6e60cf
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1945122785 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_max_throughput_chk.1945122785
Directory /workspace/8.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/8.rom_ctrl_smoke.340994785
Short name T295
Test name
Test status
Simulation time 8257004134 ps
CPU time 21.59 seconds
Started Mar 14 01:17:19 PM PDT 24
Finished Mar 14 01:17:40 PM PDT 24
Peak memory 214036 kb
Host smart-47d4e2d8-4380-4ec0-a246-6a50137f34fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=340994785 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_smoke.340994785
Directory /workspace/8.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/8.rom_ctrl_stress_all.3741904990
Short name T233
Test name
Test status
Simulation time 8063480551 ps
CPU time 21.52 seconds
Started Mar 14 01:17:20 PM PDT 24
Finished Mar 14 01:17:42 PM PDT 24
Peak memory 212384 kb
Host smart-b4f13887-2645-4cd1-8f8f-d9f14544ba72
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3741904990 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 8.rom_ctrl_stress_all.3741904990
Directory /workspace/8.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/8.rom_ctrl_stress_all_with_rand_reset.4255366763
Short name T54
Test name
Test status
Simulation time 66826586453 ps
CPU time 678.54 seconds
Started Mar 14 01:17:20 PM PDT 24
Finished Mar 14 01:28:39 PM PDT 24
Peak memory 229428 kb
Host smart-a46f4883-727d-4911-b04e-ad64e13b4ef5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4255366763 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_stress_all_with_rand_reset.4255366763
Directory /workspace/8.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.rom_ctrl_alert_test.3529770203
Short name T336
Test name
Test status
Simulation time 2183981287 ps
CPU time 17.11 seconds
Started Mar 14 01:17:19 PM PDT 24
Finished Mar 14 01:17:36 PM PDT 24
Peak memory 211160 kb
Host smart-9d61be59-b0cd-46fc-ae3c-b0b19fb5314e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3529770203 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_alert_test.3529770203
Directory /workspace/9.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/9.rom_ctrl_corrupt_sig_fatal_chk.1625749067
Short name T249
Test name
Test status
Simulation time 6792844227 ps
CPU time 88.54 seconds
Started Mar 14 01:17:18 PM PDT 24
Finished Mar 14 01:18:46 PM PDT 24
Peak memory 213340 kb
Host smart-65cbc064-7e32-4b3c-987e-05a08072b0df
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1625749067 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_c
orrupt_sig_fatal_chk.1625749067
Directory /workspace/9.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/9.rom_ctrl_kmac_err_chk.365781542
Short name T177
Test name
Test status
Simulation time 1506467022 ps
CPU time 9.03 seconds
Started Mar 14 01:17:19 PM PDT 24
Finished Mar 14 01:17:28 PM PDT 24
Peak memory 211804 kb
Host smart-a64a0dcc-bcaf-4a2e-885d-268b89eebbb4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=365781542 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_kmac_err_chk.365781542
Directory /workspace/9.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/9.rom_ctrl_max_throughput_chk.1552294077
Short name T246
Test name
Test status
Simulation time 8223103796 ps
CPU time 16.21 seconds
Started Mar 14 01:17:20 PM PDT 24
Finished Mar 14 01:17:36 PM PDT 24
Peak memory 211184 kb
Host smart-4638e3ec-4cea-47e5-ab22-957d77948a0f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1552294077 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_max_throughput_chk.1552294077
Directory /workspace/9.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/9.rom_ctrl_smoke.959313963
Short name T195
Test name
Test status
Simulation time 2153921186 ps
CPU time 23.39 seconds
Started Mar 14 01:17:20 PM PDT 24
Finished Mar 14 01:17:43 PM PDT 24
Peak memory 212856 kb
Host smart-eabdaeee-fbe2-4630-99c3-ca150294edb5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=959313963 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_smoke.959313963
Directory /workspace/9.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/9.rom_ctrl_stress_all.1497816367
Short name T43
Test name
Test status
Simulation time 5953149939 ps
CPU time 18.22 seconds
Started Mar 14 01:17:18 PM PDT 24
Finished Mar 14 01:17:36 PM PDT 24
Peak memory 218248 kb
Host smart-5b261f9f-fa51-424e-b0bb-d9c022a4814c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1497816367 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 9.rom_ctrl_stress_all.1497816367
Directory /workspace/9.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/9.rom_ctrl_stress_all_with_rand_reset.3401195638
Short name T51
Test name
Test status
Simulation time 201630503135 ps
CPU time 1940.79 seconds
Started Mar 14 01:17:19 PM PDT 24
Finished Mar 14 01:49:40 PM PDT 24
Peak memory 235824 kb
Host smart-d25d81dd-112e-47e4-8501-3de4f5fbf606
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3401195638 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_stress_all_with_rand_reset.3401195638
Directory /workspace/9.rom_ctrl_stress_all_with_rand_reset/latest
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