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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
97.62 96.97 93.25 97.88 100.00 99.01 97.89 98.37


Total test records in report: 918
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T765 /workspace/coverage/cover_reg_top/12.rom_ctrl_passthru_mem_tl_intg_err.2902151561 Mar 17 03:03:44 PM PDT 24 Mar 17 03:05:09 PM PDT 24 32824746626 ps
T766 /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_intg_err.3654813291 Mar 17 01:46:47 PM PDT 24 Mar 17 01:47:32 PM PDT 24 1706320209 ps
T767 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_hw_reset.578141283 Mar 17 03:03:37 PM PDT 24 Mar 17 03:03:59 PM PDT 24 3028451403 ps
T91 /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_rw.3121422655 Mar 17 01:46:46 PM PDT 24 Mar 17 01:46:59 PM PDT 24 1362611942 ps
T768 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_hw_reset.545082918 Mar 17 03:03:29 PM PDT 24 Mar 17 03:04:00 PM PDT 24 2855265355 ps
T95 /workspace/coverage/cover_reg_top/6.rom_ctrl_passthru_mem_tl_intg_err.2345597660 Mar 17 01:46:32 PM PDT 24 Mar 17 01:47:00 PM PDT 24 576337815 ps
T101 /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_rw.1206934947 Mar 17 01:46:37 PM PDT 24 Mar 17 01:46:48 PM PDT 24 1952587921 ps
T769 /workspace/coverage/cover_reg_top/16.rom_ctrl_same_csr_outstanding.1559122405 Mar 17 01:46:41 PM PDT 24 Mar 17 01:46:48 PM PDT 24 168377317 ps
T770 /workspace/coverage/cover_reg_top/5.rom_ctrl_same_csr_outstanding.1287813981 Mar 17 03:03:39 PM PDT 24 Mar 17 03:03:47 PM PDT 24 201004914 ps
T125 /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_intg_err.2172910030 Mar 17 03:03:33 PM PDT 24 Mar 17 03:06:08 PM PDT 24 730196479 ps
T771 /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_errors.550115819 Mar 17 03:03:44 PM PDT 24 Mar 17 03:04:03 PM PDT 24 1789530810 ps
T126 /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_intg_err.645059273 Mar 17 01:46:35 PM PDT 24 Mar 17 01:47:49 PM PDT 24 4561807869 ps
T772 /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_errors.3528433805 Mar 17 01:46:19 PM PDT 24 Mar 17 01:46:32 PM PDT 24 6838243246 ps
T92 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_aliasing.2896721605 Mar 17 01:46:17 PM PDT 24 Mar 17 01:46:33 PM PDT 24 30101084036 ps
T773 /workspace/coverage/cover_reg_top/9.rom_ctrl_same_csr_outstanding.2685376988 Mar 17 03:03:38 PM PDT 24 Mar 17 03:03:57 PM PDT 24 2384556133 ps
T774 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_aliasing.3831537009 Mar 17 03:03:29 PM PDT 24 Mar 17 03:03:56 PM PDT 24 13899433626 ps
T775 /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_walk.865019294 Mar 17 01:46:29 PM PDT 24 Mar 17 01:46:39 PM PDT 24 991691328 ps
T776 /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_errors.3311149162 Mar 17 01:46:20 PM PDT 24 Mar 17 01:46:29 PM PDT 24 208843021 ps
T777 /workspace/coverage/cover_reg_top/14.rom_ctrl_same_csr_outstanding.2680687915 Mar 17 03:03:47 PM PDT 24 Mar 17 03:03:57 PM PDT 24 346347484 ps
T124 /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_intg_err.2344670470 Mar 17 03:03:32 PM PDT 24 Mar 17 03:05:01 PM PDT 24 1551914537 ps
T123 /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_intg_err.1498486714 Mar 17 03:03:49 PM PDT 24 Mar 17 03:06:26 PM PDT 24 1018254247 ps
T778 /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_intg_err.3832809027 Mar 17 03:03:43 PM PDT 24 Mar 17 03:06:31 PM PDT 24 2841964454 ps
T779 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_bit_bash.2090414585 Mar 17 03:03:35 PM PDT 24 Mar 17 03:04:00 PM PDT 24 2895010120 ps
T780 /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_rw.4024222459 Mar 17 03:03:49 PM PDT 24 Mar 17 03:04:06 PM PDT 24 5119928194 ps
T781 /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_intg_err.1496372546 Mar 17 01:46:36 PM PDT 24 Mar 17 01:47:45 PM PDT 24 247577285 ps
T782 /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_mem_rw_with_rand_reset.212742078 Mar 17 01:46:38 PM PDT 24 Mar 17 01:46:45 PM PDT 24 1544584220 ps
T783 /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_intg_err.2793405513 Mar 17 03:03:36 PM PDT 24 Mar 17 03:05:22 PM PDT 24 35394990712 ps
T784 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_mem_rw_with_rand_reset.4163980674 Mar 17 01:46:17 PM PDT 24 Mar 17 01:46:22 PM PDT 24 376679803 ps
T785 /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_errors.1403137524 Mar 17 01:46:34 PM PDT 24 Mar 17 01:46:42 PM PDT 24 249508597 ps
T786 /workspace/coverage/cover_reg_top/9.rom_ctrl_same_csr_outstanding.2686007922 Mar 17 01:46:51 PM PDT 24 Mar 17 01:47:09 PM PDT 24 2060898266 ps
T96 /workspace/coverage/cover_reg_top/18.rom_ctrl_passthru_mem_tl_intg_err.2539767700 Mar 17 03:03:51 PM PDT 24 Mar 17 03:05:07 PM PDT 24 12512882661 ps
T787 /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_errors.1288208012 Mar 17 03:03:39 PM PDT 24 Mar 17 03:04:00 PM PDT 24 4941254075 ps
T788 /workspace/coverage/cover_reg_top/19.rom_ctrl_same_csr_outstanding.1772179938 Mar 17 03:03:50 PM PDT 24 Mar 17 03:04:05 PM PDT 24 4117239993 ps
T789 /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_errors.3224678173 Mar 17 01:46:38 PM PDT 24 Mar 17 01:46:58 PM PDT 24 7347078670 ps
T790 /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_errors.1048432229 Mar 17 01:46:48 PM PDT 24 Mar 17 01:47:06 PM PDT 24 1894675144 ps
T791 /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_mem_rw_with_rand_reset.3759365943 Mar 17 01:46:46 PM PDT 24 Mar 17 01:47:03 PM PDT 24 1984679000 ps
T792 /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_intg_err.1875171987 Mar 17 01:46:21 PM PDT 24 Mar 17 01:47:05 PM PDT 24 1490838345 ps
T793 /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_errors.3958934648 Mar 17 01:46:19 PM PDT 24 Mar 17 01:46:27 PM PDT 24 462133234 ps
T794 /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_mem_rw_with_rand_reset.4103126399 Mar 17 01:46:36 PM PDT 24 Mar 17 01:46:42 PM PDT 24 1023058714 ps
T795 /workspace/coverage/cover_reg_top/12.rom_ctrl_same_csr_outstanding.2129637500 Mar 17 01:46:40 PM PDT 24 Mar 17 01:46:52 PM PDT 24 1738953565 ps
T796 /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_partial_access.2935224628 Mar 17 01:46:39 PM PDT 24 Mar 17 01:46:46 PM PDT 24 85603285 ps
T797 /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_rw.3505466336 Mar 17 01:46:38 PM PDT 24 Mar 17 01:46:57 PM PDT 24 2765534209 ps
T798 /workspace/coverage/cover_reg_top/8.rom_ctrl_passthru_mem_tl_intg_err.4139229356 Mar 17 01:46:37 PM PDT 24 Mar 17 01:47:52 PM PDT 24 31957258629 ps
T799 /workspace/coverage/cover_reg_top/4.rom_ctrl_same_csr_outstanding.159228480 Mar 17 03:03:36 PM PDT 24 Mar 17 03:03:49 PM PDT 24 196293025 ps
T800 /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_rw.439176315 Mar 17 01:46:39 PM PDT 24 Mar 17 01:46:52 PM PDT 24 4221649013 ps
T801 /workspace/coverage/cover_reg_top/14.rom_ctrl_same_csr_outstanding.388667606 Mar 17 01:46:47 PM PDT 24 Mar 17 01:46:52 PM PDT 24 183085444 ps
T802 /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_mem_rw_with_rand_reset.1741092366 Mar 17 03:03:39 PM PDT 24 Mar 17 03:03:49 PM PDT 24 182412737 ps
T803 /workspace/coverage/cover_reg_top/9.rom_ctrl_passthru_mem_tl_intg_err.107376349 Mar 17 03:03:39 PM PDT 24 Mar 17 03:04:36 PM PDT 24 2200272002 ps
T804 /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_errors.4176034932 Mar 17 01:46:29 PM PDT 24 Mar 17 01:46:48 PM PDT 24 4043499143 ps
T805 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_rw.2793713128 Mar 17 03:03:30 PM PDT 24 Mar 17 03:03:59 PM PDT 24 3836291315 ps
T806 /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_errors.2371698408 Mar 17 03:03:40 PM PDT 24 Mar 17 03:04:08 PM PDT 24 4544509895 ps
T807 /workspace/coverage/cover_reg_top/3.rom_ctrl_same_csr_outstanding.4186002120 Mar 17 01:46:26 PM PDT 24 Mar 17 01:46:43 PM PDT 24 2076252430 ps
T808 /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_rw.1356556173 Mar 17 03:03:44 PM PDT 24 Mar 17 03:04:06 PM PDT 24 2320218895 ps
T809 /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_errors.2284006067 Mar 17 01:46:35 PM PDT 24 Mar 17 01:46:51 PM PDT 24 1324126127 ps
T810 /workspace/coverage/cover_reg_top/18.rom_ctrl_passthru_mem_tl_intg_err.2824180787 Mar 17 01:46:37 PM PDT 24 Mar 17 01:47:45 PM PDT 24 16406728269 ps
T811 /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_mem_rw_with_rand_reset.903369673 Mar 17 03:03:52 PM PDT 24 Mar 17 03:04:19 PM PDT 24 4656989327 ps
T93 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_aliasing.3221700984 Mar 17 01:46:20 PM PDT 24 Mar 17 01:46:36 PM PDT 24 2311937266 ps
T128 /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_intg_err.3283114625 Mar 17 01:46:19 PM PDT 24 Mar 17 01:47:28 PM PDT 24 2037982748 ps
T812 /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_mem_rw_with_rand_reset.3434566561 Mar 17 03:03:40 PM PDT 24 Mar 17 03:04:01 PM PDT 24 3885293470 ps
T813 /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_mem_rw_with_rand_reset.3851908791 Mar 17 01:46:41 PM PDT 24 Mar 17 01:46:59 PM PDT 24 7430820454 ps
T814 /workspace/coverage/cover_reg_top/16.rom_ctrl_passthru_mem_tl_intg_err.3344279216 Mar 17 01:46:41 PM PDT 24 Mar 17 01:47:10 PM PDT 24 4876292049 ps
T815 /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_errors.2240187352 Mar 17 03:03:40 PM PDT 24 Mar 17 03:03:55 PM PDT 24 6599456714 ps
T816 /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_partial_access.566793679 Mar 17 01:46:29 PM PDT 24 Mar 17 01:46:44 PM PDT 24 5179175345 ps
T817 /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_intg_err.3338459938 Mar 17 03:03:47 PM PDT 24 Mar 17 03:06:35 PM PDT 24 3104529321 ps
T818 /workspace/coverage/cover_reg_top/15.rom_ctrl_same_csr_outstanding.2382858330 Mar 17 01:46:47 PM PDT 24 Mar 17 01:46:57 PM PDT 24 678870325 ps
T819 /workspace/coverage/cover_reg_top/19.rom_ctrl_same_csr_outstanding.1153569827 Mar 17 01:46:39 PM PDT 24 Mar 17 01:46:52 PM PDT 24 985161838 ps
T820 /workspace/coverage/cover_reg_top/17.rom_ctrl_passthru_mem_tl_intg_err.1473044298 Mar 17 03:03:51 PM PDT 24 Mar 17 03:06:10 PM PDT 24 27626006917 ps
T129 /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_intg_err.2332380111 Mar 17 03:03:47 PM PDT 24 Mar 17 03:05:14 PM PDT 24 604574215 ps
T821 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_bit_bash.2529435185 Mar 17 01:46:35 PM PDT 24 Mar 17 01:46:44 PM PDT 24 585299710 ps
T822 /workspace/coverage/cover_reg_top/18.rom_ctrl_same_csr_outstanding.2355409888 Mar 17 03:03:51 PM PDT 24 Mar 17 03:04:17 PM PDT 24 3039843026 ps
T823 /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_intg_err.2397098153 Mar 17 01:46:40 PM PDT 24 Mar 17 01:47:55 PM PDT 24 2709168888 ps
T824 /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_errors.3798293278 Mar 17 03:03:42 PM PDT 24 Mar 17 03:04:09 PM PDT 24 19224342804 ps
T825 /workspace/coverage/cover_reg_top/2.rom_ctrl_same_csr_outstanding.2743693738 Mar 17 01:46:27 PM PDT 24 Mar 17 01:46:39 PM PDT 24 2649303233 ps
T826 /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_mem_rw_with_rand_reset.853194963 Mar 17 01:46:45 PM PDT 24 Mar 17 01:46:54 PM PDT 24 1288745792 ps
T827 /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_mem_rw_with_rand_reset.980785730 Mar 17 03:03:57 PM PDT 24 Mar 17 03:04:07 PM PDT 24 719076873 ps
T828 /workspace/coverage/cover_reg_top/10.rom_ctrl_same_csr_outstanding.132327016 Mar 17 03:03:43 PM PDT 24 Mar 17 03:04:04 PM PDT 24 7491297301 ps
T829 /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_mem_rw_with_rand_reset.3864577099 Mar 17 03:03:51 PM PDT 24 Mar 17 03:04:09 PM PDT 24 1624323422 ps
T830 /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_intg_err.4120875476 Mar 17 01:46:37 PM PDT 24 Mar 17 01:47:51 PM PDT 24 1701605440 ps
T831 /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_rw.1022523324 Mar 17 01:46:33 PM PDT 24 Mar 17 01:46:47 PM PDT 24 3020131963 ps
T832 /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_mem_rw_with_rand_reset.3226601687 Mar 17 03:03:48 PM PDT 24 Mar 17 03:04:07 PM PDT 24 6861586867 ps
T833 /workspace/coverage/cover_reg_top/1.rom_ctrl_passthru_mem_tl_intg_err.4088068354 Mar 17 03:03:29 PM PDT 24 Mar 17 03:04:42 PM PDT 24 22361335296 ps
T834 /workspace/coverage/cover_reg_top/17.rom_ctrl_same_csr_outstanding.3495932245 Mar 17 01:46:38 PM PDT 24 Mar 17 01:46:52 PM PDT 24 1693896572 ps
T835 /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_partial_access.3976869629 Mar 17 03:03:30 PM PDT 24 Mar 17 03:03:51 PM PDT 24 8823974009 ps
T836 /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_mem_rw_with_rand_reset.842854893 Mar 17 01:46:37 PM PDT 24 Mar 17 01:46:51 PM PDT 24 1384008605 ps
T837 /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_rw.2428353412 Mar 17 03:03:51 PM PDT 24 Mar 17 03:04:00 PM PDT 24 662036787 ps
T838 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_bit_bash.741914318 Mar 17 03:03:39 PM PDT 24 Mar 17 03:03:47 PM PDT 24 167601798 ps
T839 /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_intg_err.2670205429 Mar 17 03:03:40 PM PDT 24 Mar 17 03:06:23 PM PDT 24 8571290541 ps
T840 /workspace/coverage/cover_reg_top/13.rom_ctrl_passthru_mem_tl_intg_err.1520998352 Mar 17 03:03:43 PM PDT 24 Mar 17 03:04:20 PM PDT 24 2731916781 ps
T841 /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_errors.3584547661 Mar 17 03:03:47 PM PDT 24 Mar 17 03:04:19 PM PDT 24 6904418342 ps
T842 /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_mem_rw_with_rand_reset.1626075762 Mar 17 03:03:40 PM PDT 24 Mar 17 03:03:49 PM PDT 24 196704546 ps
T843 /workspace/coverage/cover_reg_top/4.rom_ctrl_passthru_mem_tl_intg_err.550059597 Mar 17 01:46:37 PM PDT 24 Mar 17 01:47:31 PM PDT 24 5908370573 ps
T844 /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_rw.1643870051 Mar 17 03:03:43 PM PDT 24 Mar 17 03:04:07 PM PDT 24 3025379335 ps
T845 /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_errors.1366244962 Mar 17 01:46:36 PM PDT 24 Mar 17 01:46:47 PM PDT 24 1044916483 ps
T846 /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_rw.1580008818 Mar 17 01:46:47 PM PDT 24 Mar 17 01:47:03 PM PDT 24 1966940287 ps
T847 /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_rw.3554516882 Mar 17 01:46:38 PM PDT 24 Mar 17 01:46:42 PM PDT 24 490249392 ps
T848 /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_intg_err.418044336 Mar 17 01:46:18 PM PDT 24 Mar 17 01:47:34 PM PDT 24 2623835040 ps
T849 /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_intg_err.2978449986 Mar 17 01:46:45 PM PDT 24 Mar 17 01:47:30 PM PDT 24 1580290334 ps
T850 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_rw.3768779427 Mar 17 03:03:29 PM PDT 24 Mar 17 03:03:44 PM PDT 24 4788419297 ps
T851 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_aliasing.1659733979 Mar 17 01:46:26 PM PDT 24 Mar 17 01:46:32 PM PDT 24 343921973 ps
T852 /workspace/coverage/cover_reg_top/11.rom_ctrl_same_csr_outstanding.678615813 Mar 17 03:03:43 PM PDT 24 Mar 17 03:04:16 PM PDT 24 17715567344 ps
T853 /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_rw.327132231 Mar 17 01:46:43 PM PDT 24 Mar 17 01:46:49 PM PDT 24 362916959 ps
T854 /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_rw.2557344350 Mar 17 03:03:48 PM PDT 24 Mar 17 03:04:12 PM PDT 24 2787669594 ps
T855 /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_rw.3975477352 Mar 17 03:03:37 PM PDT 24 Mar 17 03:03:45 PM PDT 24 338955996 ps
T856 /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_errors.63013736 Mar 17 01:46:37 PM PDT 24 Mar 17 01:46:52 PM PDT 24 1072602505 ps
T857 /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_intg_err.2628565628 Mar 17 03:03:52 PM PDT 24 Mar 17 03:06:33 PM PDT 24 1783639438 ps
T858 /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_intg_err.831093996 Mar 17 03:03:45 PM PDT 24 Mar 17 03:06:37 PM PDT 24 3268764839 ps
T859 /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_errors.2508490786 Mar 17 03:03:54 PM PDT 24 Mar 17 03:04:27 PM PDT 24 7164472702 ps
T860 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_bit_bash.559628861 Mar 17 03:03:29 PM PDT 24 Mar 17 03:03:59 PM PDT 24 13631235295 ps
T861 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_aliasing.1767239726 Mar 17 01:46:36 PM PDT 24 Mar 17 01:46:51 PM PDT 24 10411309392 ps
T862 /workspace/coverage/cover_reg_top/0.rom_ctrl_same_csr_outstanding.3449430927 Mar 17 01:46:29 PM PDT 24 Mar 17 01:46:43 PM PDT 24 3229657676 ps
T863 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_mem_rw_with_rand_reset.2416006096 Mar 17 03:03:38 PM PDT 24 Mar 17 03:03:55 PM PDT 24 1084146412 ps
T864 /workspace/coverage/cover_reg_top/8.rom_ctrl_same_csr_outstanding.4110888516 Mar 17 01:46:22 PM PDT 24 Mar 17 01:46:30 PM PDT 24 3033173261 ps
T865 /workspace/coverage/cover_reg_top/7.rom_ctrl_same_csr_outstanding.353940142 Mar 17 01:46:38 PM PDT 24 Mar 17 01:46:44 PM PDT 24 744892301 ps
T94 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_rw.3417057284 Mar 17 03:03:37 PM PDT 24 Mar 17 03:03:50 PM PDT 24 1674557202 ps
T866 /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_intg_err.1808694213 Mar 17 03:03:26 PM PDT 24 Mar 17 03:04:50 PM PDT 24 609135777 ps
T867 /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_rw.517811420 Mar 17 03:03:39 PM PDT 24 Mar 17 03:03:57 PM PDT 24 7825177765 ps
T868 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_hw_reset.2145786495 Mar 17 01:46:36 PM PDT 24 Mar 17 01:46:45 PM PDT 24 3308328473 ps
T869 /workspace/coverage/cover_reg_top/3.rom_ctrl_same_csr_outstanding.1641767694 Mar 17 03:03:34 PM PDT 24 Mar 17 03:03:43 PM PDT 24 167515969 ps
T870 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_bit_bash.1330050488 Mar 17 01:46:39 PM PDT 24 Mar 17 01:46:47 PM PDT 24 589181394 ps
T871 /workspace/coverage/cover_reg_top/19.rom_ctrl_passthru_mem_tl_intg_err.1401564344 Mar 17 01:46:46 PM PDT 24 Mar 17 01:48:18 PM PDT 24 11552196087 ps
T872 /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_intg_err.3507845179 Mar 17 03:03:51 PM PDT 24 Mar 17 03:05:11 PM PDT 24 4456865364 ps
T873 /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_mem_rw_with_rand_reset.400417528 Mar 17 01:46:48 PM PDT 24 Mar 17 01:47:05 PM PDT 24 9396890891 ps
T874 /workspace/coverage/cover_reg_top/15.rom_ctrl_passthru_mem_tl_intg_err.591726984 Mar 17 03:03:47 PM PDT 24 Mar 17 03:05:12 PM PDT 24 8193824746 ps
T875 /workspace/coverage/cover_reg_top/15.rom_ctrl_same_csr_outstanding.1349885958 Mar 17 03:03:48 PM PDT 24 Mar 17 03:04:05 PM PDT 24 4326469107 ps
T876 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_mem_rw_with_rand_reset.1125704318 Mar 17 01:46:32 PM PDT 24 Mar 17 01:46:45 PM PDT 24 1358734388 ps
T877 /workspace/coverage/cover_reg_top/6.rom_ctrl_same_csr_outstanding.2448028377 Mar 17 03:03:43 PM PDT 24 Mar 17 03:04:15 PM PDT 24 20695633060 ps
T878 /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_errors.1732660954 Mar 17 03:03:31 PM PDT 24 Mar 17 03:03:58 PM PDT 24 24504589935 ps
T879 /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_errors.212342058 Mar 17 01:46:36 PM PDT 24 Mar 17 01:46:49 PM PDT 24 4686946673 ps
T880 /workspace/coverage/cover_reg_top/11.rom_ctrl_passthru_mem_tl_intg_err.799456846 Mar 17 03:03:44 PM PDT 24 Mar 17 03:06:09 PM PDT 24 16121855427 ps
T881 /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_errors.2170540184 Mar 17 03:03:47 PM PDT 24 Mar 17 03:04:00 PM PDT 24 750882503 ps
T882 /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_intg_err.3283606122 Mar 17 01:46:41 PM PDT 24 Mar 17 01:47:54 PM PDT 24 405553314 ps
T883 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_mem_rw_with_rand_reset.258482631 Mar 17 01:46:30 PM PDT 24 Mar 17 01:46:36 PM PDT 24 853065092 ps
T884 /workspace/coverage/cover_reg_top/12.rom_ctrl_passthru_mem_tl_intg_err.82438918 Mar 17 01:46:37 PM PDT 24 Mar 17 01:47:26 PM PDT 24 5725755101 ps
T127 /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_intg_err.2284332475 Mar 17 03:03:42 PM PDT 24 Mar 17 03:05:25 PM PDT 24 3956845477 ps
T885 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_aliasing.343438463 Mar 17 03:03:30 PM PDT 24 Mar 17 03:03:58 PM PDT 24 3225581309 ps
T886 /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_rw.1022749269 Mar 17 03:03:45 PM PDT 24 Mar 17 03:04:12 PM PDT 24 12559715853 ps
T887 /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_errors.1754609830 Mar 17 01:46:46 PM PDT 24 Mar 17 01:47:04 PM PDT 24 4015240045 ps
T888 /workspace/coverage/cover_reg_top/9.rom_ctrl_passthru_mem_tl_intg_err.359025467 Mar 17 01:46:34 PM PDT 24 Mar 17 01:47:02 PM PDT 24 2542747849 ps
T889 /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_rw.1974190397 Mar 17 03:03:41 PM PDT 24 Mar 17 03:04:11 PM PDT 24 13788950725 ps
T890 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_hw_reset.3049942000 Mar 17 01:46:19 PM PDT 24 Mar 17 01:46:30 PM PDT 24 1014234650 ps
T891 /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_rw.1623396972 Mar 17 01:46:45 PM PDT 24 Mar 17 01:46:56 PM PDT 24 3800484944 ps
T892 /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_intg_err.3562502021 Mar 17 03:03:45 PM PDT 24 Mar 17 03:05:12 PM PDT 24 5849610339 ps
T893 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_mem_rw_with_rand_reset.570192668 Mar 17 03:03:30 PM PDT 24 Mar 17 03:03:39 PM PDT 24 464087230 ps
T894 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_bit_bash.1547676259 Mar 17 03:03:30 PM PDT 24 Mar 17 03:03:44 PM PDT 24 14734382297 ps
T895 /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_errors.3651538445 Mar 17 03:03:31 PM PDT 24 Mar 17 03:04:01 PM PDT 24 46563390684 ps
T896 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_bit_bash.2137190958 Mar 17 01:46:17 PM PDT 24 Mar 17 01:46:28 PM PDT 24 3949294483 ps
T897 /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_mem_rw_with_rand_reset.2203020293 Mar 17 01:46:38 PM PDT 24 Mar 17 01:46:46 PM PDT 24 2293415055 ps
T898 /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_mem_rw_with_rand_reset.993929276 Mar 17 03:03:44 PM PDT 24 Mar 17 03:03:53 PM PDT 24 350213064 ps
T899 /workspace/coverage/cover_reg_top/8.rom_ctrl_same_csr_outstanding.4064995413 Mar 17 03:03:39 PM PDT 24 Mar 17 03:03:55 PM PDT 24 1194388456 ps
T900 /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_walk.2555958024 Mar 17 01:46:29 PM PDT 24 Mar 17 01:46:36 PM PDT 24 836062536 ps
T901 /workspace/coverage/cover_reg_top/11.rom_ctrl_passthru_mem_tl_intg_err.3672777150 Mar 17 01:46:38 PM PDT 24 Mar 17 01:48:26 PM PDT 24 178720454836 ps
T902 /workspace/coverage/cover_reg_top/10.rom_ctrl_passthru_mem_tl_intg_err.2214174984 Mar 17 03:03:39 PM PDT 24 Mar 17 03:06:45 PM PDT 24 80842852054 ps
T903 /workspace/coverage/cover_reg_top/4.rom_ctrl_passthru_mem_tl_intg_err.3122997504 Mar 17 03:03:35 PM PDT 24 Mar 17 03:04:21 PM PDT 24 1349988154 ps
T904 /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_walk.2665989611 Mar 17 01:46:33 PM PDT 24 Mar 17 01:46:37 PM PDT 24 831441537 ps
T905 /workspace/coverage/cover_reg_top/0.rom_ctrl_same_csr_outstanding.3690518951 Mar 17 03:03:31 PM PDT 24 Mar 17 03:03:47 PM PDT 24 15207879422 ps
T906 /workspace/coverage/cover_reg_top/7.rom_ctrl_passthru_mem_tl_intg_err.3040676562 Mar 17 03:03:39 PM PDT 24 Mar 17 03:06:55 PM PDT 24 51271129695 ps
T907 /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_errors.1702554542 Mar 17 03:03:54 PM PDT 24 Mar 17 03:04:07 PM PDT 24 2060208426 ps
T908 /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_mem_rw_with_rand_reset.4249553696 Mar 17 01:46:35 PM PDT 24 Mar 17 01:46:44 PM PDT 24 771794666 ps
T909 /workspace/coverage/cover_reg_top/10.rom_ctrl_same_csr_outstanding.2543132196 Mar 17 01:46:43 PM PDT 24 Mar 17 01:46:52 PM PDT 24 1203190701 ps
T910 /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_intg_err.449291752 Mar 17 01:46:33 PM PDT 24 Mar 17 01:47:11 PM PDT 24 180203511 ps
T911 /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_walk.2682797787 Mar 17 03:03:35 PM PDT 24 Mar 17 03:03:58 PM PDT 24 4967576161 ps
T912 /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_errors.4150068350 Mar 17 03:03:39 PM PDT 24 Mar 17 03:04:11 PM PDT 24 4818616698 ps
T913 /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_walk.996695879 Mar 17 03:03:29 PM PDT 24 Mar 17 03:03:51 PM PDT 24 11795056173 ps
T914 /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_partial_access.1222522036 Mar 17 01:46:30 PM PDT 24 Mar 17 01:46:42 PM PDT 24 4783408427 ps
T915 /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_mem_rw_with_rand_reset.1036821444 Mar 17 01:46:48 PM PDT 24 Mar 17 01:47:02 PM PDT 24 1622609827 ps
T916 /workspace/coverage/cover_reg_top/4.rom_ctrl_same_csr_outstanding.1625034167 Mar 17 01:46:47 PM PDT 24 Mar 17 01:46:52 PM PDT 24 592336567 ps
T917 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_aliasing.790444085 Mar 17 03:03:31 PM PDT 24 Mar 17 03:04:01 PM PDT 24 14085843712 ps
T918 /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_intg_err.167461228 Mar 17 01:46:44 PM PDT 24 Mar 17 01:47:58 PM PDT 24 1128098946 ps

Test location /workspace/coverage/default/7.rom_ctrl_stress_all_with_rand_reset.3309250793
Short name T2
Test name
Test status
Simulation time 95499029881 ps
CPU time 893.65 seconds
Started Mar 17 01:46:59 PM PDT 24
Finished Mar 17 02:01:53 PM PDT 24
Peak memory 235816 kb
Host smart-ba16fff6-e40b-4547-bd1b-3c5e9dc50a61
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3309250793 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_stress_all_with_rand_reset.3309250793
Directory /workspace/7.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.rom_ctrl_corrupt_sig_fatal_chk.3365604854
Short name T31
Test name
Test status
Simulation time 359954201517 ps
CPU time 910.68 seconds
Started Mar 17 01:47:25 PM PDT 24
Finished Mar 17 02:02:36 PM PDT 24
Peak memory 237412 kb
Host smart-4af5162e-a5e4-43c6-816a-eef62dd3b043
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3365604854 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_
corrupt_sig_fatal_chk.3365604854
Directory /workspace/30.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/33.rom_ctrl_smoke.3823416388
Short name T11
Test name
Test status
Simulation time 30920718131 ps
CPU time 83.13 seconds
Started Mar 17 01:47:21 PM PDT 24
Finished Mar 17 01:48:44 PM PDT 24
Peak memory 217808 kb
Host smart-c26bf377-6976-4d19-ae63-880648c36c93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3823416388 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_smoke.3823416388
Directory /workspace/33.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/3.rom_ctrl_corrupt_sig_fatal_chk.3813037218
Short name T225
Test name
Test status
Simulation time 472054324320 ps
CPU time 1241.47 seconds
Started Mar 17 01:46:44 PM PDT 24
Finished Mar 17 02:07:28 PM PDT 24
Peak memory 216528 kb
Host smart-23dbacb6-9633-4f07-acc3-7f918fd60ea8
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3813037218 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_c
orrupt_sig_fatal_chk.3813037218
Directory /workspace/3.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_intg_err.1014787117
Short name T119
Test name
Test status
Simulation time 2051911767 ps
CPU time 78.11 seconds
Started Mar 17 01:46:35 PM PDT 24
Finished Mar 17 01:47:53 PM PDT 24
Peak memory 211740 kb
Host smart-f2eca56c-5367-4836-a479-03977e707f6b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1014787117 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_tl_in
tg_err.1014787117
Directory /workspace/2.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/3.rom_ctrl_sec_cm.505821869
Short name T5
Test name
Test status
Simulation time 5336756701 ps
CPU time 255.73 seconds
Started Mar 17 02:39:58 PM PDT 24
Finished Mar 17 02:44:15 PM PDT 24
Peak memory 239844 kb
Host smart-395a39d3-08a1-423c-9b67-499b81f0bdf1
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=505821869 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_sec_cm.505821869
Directory /workspace/3.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_hw_reset.2446679506
Short name T68
Test name
Test status
Simulation time 1805851537 ps
CPU time 25.64 seconds
Started Mar 17 03:03:30 PM PDT 24
Finished Mar 17 03:03:56 PM PDT 24
Peak memory 211212 kb
Host smart-03ea2aad-3c4b-40be-9354-d11a321ff552
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2446679506 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_hw_r
eset.2446679506
Directory /workspace/1.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/default/18.rom_ctrl_stress_all.3240056323
Short name T18
Test name
Test status
Simulation time 11576117060 ps
CPU time 119.62 seconds
Started Mar 17 02:40:10 PM PDT 24
Finished Mar 17 02:42:10 PM PDT 24
Peak memory 219240 kb
Host smart-5a9d476f-9d5c-479e-bd12-d5b4d517e404
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3240056323 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 18.rom_ctrl_stress_all.3240056323
Directory /workspace/18.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/44.rom_ctrl_stress_all_with_rand_reset.914977500
Short name T17
Test name
Test status
Simulation time 293284531341 ps
CPU time 5133.18 seconds
Started Mar 17 01:47:35 PM PDT 24
Finished Mar 17 03:13:09 PM PDT 24
Peak memory 252196 kb
Host smart-9e5ed9f9-a205-4c7f-944e-0d02d60c20e7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=914977500 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_stress_all_with_rand_reset.914977500
Directory /workspace/44.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_intg_err.831093996
Short name T858
Test name
Test status
Simulation time 3268764839 ps
CPU time 170.67 seconds
Started Mar 17 03:03:45 PM PDT 24
Finished Mar 17 03:06:37 PM PDT 24
Peak memory 213744 kb
Host smart-12a974d1-3520-4448-884d-0886757793f5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=831093996 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_tl_in
tg_err.831093996
Directory /workspace/12.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_intg_err.1510247427
Short name T122
Test name
Test status
Simulation time 2180359667 ps
CPU time 78.68 seconds
Started Mar 17 01:46:44 PM PDT 24
Finished Mar 17 01:48:05 PM PDT 24
Peak memory 211008 kb
Host smart-a2aea5c5-fc5b-4bd9-9653-3f158e0d5cc9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1510247427 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_tl_i
ntg_err.1510247427
Directory /workspace/17.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/44.rom_ctrl_alert_test.3129590686
Short name T10
Test name
Test status
Simulation time 3968155914 ps
CPU time 31 seconds
Started Mar 17 02:40:54 PM PDT 24
Finished Mar 17 02:41:25 PM PDT 24
Peak memory 211832 kb
Host smart-2d2cb11a-f241-452b-b0b8-2b05af081d42
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3129590686 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_alert_test.3129590686
Directory /workspace/44.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/2.rom_ctrl_stress_all_with_rand_reset.3038034171
Short name T13
Test name
Test status
Simulation time 59451768038 ps
CPU time 1803.19 seconds
Started Mar 17 02:40:06 PM PDT 24
Finished Mar 17 03:10:10 PM PDT 24
Peak memory 231164 kb
Host smart-e4248c25-76b6-4d2b-82c4-8a21c6e6990c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3038034171 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_stress_all_with_rand_reset.3038034171
Directory /workspace/2.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/11.rom_ctrl_kmac_err_chk.301570678
Short name T21
Test name
Test status
Simulation time 503671247 ps
CPU time 22.48 seconds
Started Mar 17 01:46:55 PM PDT 24
Finished Mar 17 01:47:18 PM PDT 24
Peak memory 213904 kb
Host smart-9f3e4ddf-c6e7-44ff-8f01-0e1cc6191a8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=301570678 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_kmac_err_chk.301570678
Directory /workspace/11.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/13.rom_ctrl_kmac_err_chk.1939229920
Short name T150
Test name
Test status
Simulation time 19617450562 ps
CPU time 49.77 seconds
Started Mar 17 02:40:09 PM PDT 24
Finished Mar 17 02:40:59 PM PDT 24
Peak memory 215020 kb
Host smart-6bd3cc81-af03-4dcd-808c-ed50588d589d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1939229920 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_kmac_err_chk.1939229920
Directory /workspace/13.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/33.rom_ctrl_kmac_err_chk.2198798246
Short name T25
Test name
Test status
Simulation time 60326771694 ps
CPU time 67.49 seconds
Started Mar 17 01:47:29 PM PDT 24
Finished Mar 17 01:48:37 PM PDT 24
Peak memory 214908 kb
Host smart-bad936d3-9e1b-4ff6-9526-fda52cc8ea31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2198798246 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_kmac_err_chk.2198798246
Directory /workspace/33.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_passthru_mem_tl_intg_err.3365695975
Short name T73
Test name
Test status
Simulation time 22155906339 ps
CPU time 88.75 seconds
Started Mar 17 01:46:18 PM PDT 24
Finished Mar 17 01:47:52 PM PDT 24
Peak memory 210960 kb
Host smart-49b9f7ab-f5ec-4f20-9604-aa06919800ec
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3365695975 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_pa
ssthru_mem_tl_intg_err.3365695975
Directory /workspace/2.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/default/0.rom_ctrl_stress_all_with_rand_reset.3974346046
Short name T14
Test name
Test status
Simulation time 126842560708 ps
CPU time 2235.05 seconds
Started Mar 17 01:46:55 PM PDT 24
Finished Mar 17 02:24:11 PM PDT 24
Peak memory 240204 kb
Host smart-2a8d89df-9598-4238-8882-b494a52a9846
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3974346046 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_stress_all_with_rand_reset.3974346046
Directory /workspace/0.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/11.rom_ctrl_corrupt_sig_fatal_chk.2197161058
Short name T179
Test name
Test status
Simulation time 296080932284 ps
CPU time 717.53 seconds
Started Mar 17 02:40:06 PM PDT 24
Finished Mar 17 02:52:04 PM PDT 24
Peak memory 239852 kb
Host smart-38b11027-0d79-4ed2-a138-328f2808fa8c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2197161058 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_
corrupt_sig_fatal_chk.2197161058
Directory /workspace/11.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_intg_err.645059273
Short name T126
Test name
Test status
Simulation time 4561807869 ps
CPU time 73.45 seconds
Started Mar 17 01:46:35 PM PDT 24
Finished Mar 17 01:47:49 PM PDT 24
Peak memory 219240 kb
Host smart-6144c4b1-fc6c-4be1-bb85-792fca433634
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=645059273 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_tl_in
tg_err.645059273
Directory /workspace/16.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_aliasing.1659733979
Short name T851
Test name
Test status
Simulation time 343921973 ps
CPU time 5.62 seconds
Started Mar 17 01:46:26 PM PDT 24
Finished Mar 17 01:46:32 PM PDT 24
Peak memory 210896 kb
Host smart-56bbec89-7413-4721-bccb-0cdea1547541
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1659733979 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_alia
sing.1659733979
Directory /workspace/0.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_aliasing.3831537009
Short name T774
Test name
Test status
Simulation time 13899433626 ps
CPU time 26.27 seconds
Started Mar 17 03:03:29 PM PDT 24
Finished Mar 17 03:03:56 PM PDT 24
Peak memory 211332 kb
Host smart-8e36d195-7833-42c5-9576-7ca11dc01d68
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3831537009 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_alia
sing.3831537009
Directory /workspace/0.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_bit_bash.1227717046
Short name T690
Test name
Test status
Simulation time 1312643216 ps
CPU time 12.4 seconds
Started Mar 17 01:46:18 PM PDT 24
Finished Mar 17 01:46:30 PM PDT 24
Peak memory 210872 kb
Host smart-6e239330-7ceb-4adc-a5a9-71536de56848
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1227717046 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_bit_
bash.1227717046
Directory /workspace/0.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_bit_bash.559628861
Short name T860
Test name
Test status
Simulation time 13631235295 ps
CPU time 29.36 seconds
Started Mar 17 03:03:29 PM PDT 24
Finished Mar 17 03:03:59 PM PDT 24
Peak memory 211656 kb
Host smart-23bee780-4029-4f5b-a512-eda70d9bdee6
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=559628861 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_bit_b
ash.559628861
Directory /workspace/0.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_hw_reset.4160690343
Short name T71
Test name
Test status
Simulation time 2171618131 ps
CPU time 20.41 seconds
Started Mar 17 01:46:35 PM PDT 24
Finished Mar 17 01:46:55 PM PDT 24
Peak memory 210984 kb
Host smart-8990e9e8-4000-42c4-98f4-a9c5c2e099fa
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4160690343 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_hw_r
eset.4160690343
Directory /workspace/0.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_hw_reset.545082918
Short name T768
Test name
Test status
Simulation time 2855265355 ps
CPU time 30.08 seconds
Started Mar 17 03:03:29 PM PDT 24
Finished Mar 17 03:04:00 PM PDT 24
Peak memory 211284 kb
Host smart-fb8ca4ff-25dd-4876-81bc-b2360dd6dce4
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=545082918 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_hw_re
set.545082918
Directory /workspace/0.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_mem_rw_with_rand_reset.1125704318
Short name T876
Test name
Test status
Simulation time 1358734388 ps
CPU time 12.7 seconds
Started Mar 17 01:46:32 PM PDT 24
Finished Mar 17 01:46:45 PM PDT 24
Peak memory 219116 kb
Host smart-75081d9a-a2c7-4a9b-bec8-f8e6dca51d93
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1125704318 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 0.rom_ctrl_csr_mem_rw_with_rand_reset.1125704318
Directory /workspace/0.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_mem_rw_with_rand_reset.570192668
Short name T893
Test name
Test status
Simulation time 464087230 ps
CPU time 8.62 seconds
Started Mar 17 03:03:30 PM PDT 24
Finished Mar 17 03:03:39 PM PDT 24
Peak memory 215732 kb
Host smart-c5bef404-4b20-4a1c-bc62-7b00451bb8dc
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=570192668 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 0.rom_ctrl_csr_mem_rw_with_rand_reset.570192668
Directory /workspace/0.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_rw.2238015129
Short name T700
Test name
Test status
Simulation time 2849892775 ps
CPU time 12.41 seconds
Started Mar 17 01:46:31 PM PDT 24
Finished Mar 17 01:46:44 PM PDT 24
Peak memory 210932 kb
Host smart-952ce91a-ce78-4e5d-ae58-7fd6797e9215
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2238015129 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_rw.2238015129
Directory /workspace/0.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_rw.84816771
Short name T714
Test name
Test status
Simulation time 6817079954 ps
CPU time 27.01 seconds
Started Mar 17 03:03:27 PM PDT 24
Finished Mar 17 03:03:54 PM PDT 24
Peak memory 211852 kb
Host smart-2da5f199-c219-4c14-8e0a-69790a8a1b35
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=84816771 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_rw.84816771
Directory /workspace/0.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_partial_access.1222522036
Short name T914
Test name
Test status
Simulation time 4783408427 ps
CPU time 11.41 seconds
Started Mar 17 01:46:30 PM PDT 24
Finished Mar 17 01:46:42 PM PDT 24
Peak memory 210888 kb
Host smart-8581efb7-13b9-4bd7-9fda-df0af94bcb1d
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1222522036 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctr
l_mem_partial_access.1222522036
Directory /workspace/0.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_partial_access.3976869629
Short name T835
Test name
Test status
Simulation time 8823974009 ps
CPU time 20.36 seconds
Started Mar 17 03:03:30 PM PDT 24
Finished Mar 17 03:03:51 PM PDT 24
Peak memory 210780 kb
Host smart-538d1a34-bfe8-43e6-b236-dbde6d1cc687
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3976869629 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctr
l_mem_partial_access.3976869629
Directory /workspace/0.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_walk.2665989611
Short name T904
Test name
Test status
Simulation time 831441537 ps
CPU time 4.06 seconds
Started Mar 17 01:46:33 PM PDT 24
Finished Mar 17 01:46:37 PM PDT 24
Peak memory 210808 kb
Host smart-3f545039-38d3-48a1-b00d-3170091b210c
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2665989611 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_mem_walk
.2665989611
Directory /workspace/0.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_walk.3102946291
Short name T698
Test name
Test status
Simulation time 689399433 ps
CPU time 7.93 seconds
Started Mar 17 03:03:27 PM PDT 24
Finished Mar 17 03:03:35 PM PDT 24
Peak memory 210840 kb
Host smart-818a6c25-10fb-40a1-911c-b81ffaf18232
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3102946291 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_mem_walk
.3102946291
Directory /workspace/0.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_passthru_mem_tl_intg_err.3237202044
Short name T69
Test name
Test status
Simulation time 41020685080 ps
CPU time 62.99 seconds
Started Mar 17 01:46:19 PM PDT 24
Finished Mar 17 01:47:22 PM PDT 24
Peak memory 211000 kb
Host smart-ec1040a0-50ea-456f-b5af-c4184bd8a5e1
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3237202044 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_pa
ssthru_mem_tl_intg_err.3237202044
Directory /workspace/0.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_passthru_mem_tl_intg_err.9605631
Short name T748
Test name
Test status
Simulation time 53308190828 ps
CPU time 138.53 seconds
Started Mar 17 03:03:30 PM PDT 24
Finished Mar 17 03:05:49 PM PDT 24
Peak memory 214968 kb
Host smart-c4e1c6f1-0353-4aea-bbd3-353f12d4d5dd
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=9605631 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_passt
hru_mem_tl_intg_err.9605631
Directory /workspace/0.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_same_csr_outstanding.3449430927
Short name T862
Test name
Test status
Simulation time 3229657676 ps
CPU time 13.98 seconds
Started Mar 17 01:46:29 PM PDT 24
Finished Mar 17 01:46:43 PM PDT 24
Peak memory 210960 kb
Host smart-2f4d0d4b-5992-43a7-b9db-71c3b4a80d0c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3449430927 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_c
trl_same_csr_outstanding.3449430927
Directory /workspace/0.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_same_csr_outstanding.3690518951
Short name T905
Test name
Test status
Simulation time 15207879422 ps
CPU time 15.56 seconds
Started Mar 17 03:03:31 PM PDT 24
Finished Mar 17 03:03:47 PM PDT 24
Peak memory 210944 kb
Host smart-f16490c6-cd83-4234-af8b-f84dc4a3aecf
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3690518951 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_c
trl_same_csr_outstanding.3690518951
Directory /workspace/0.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_errors.2681308974
Short name T691
Test name
Test status
Simulation time 8017980038 ps
CPU time 16.13 seconds
Started Mar 17 01:46:33 PM PDT 24
Finished Mar 17 01:46:50 PM PDT 24
Peak memory 219184 kb
Host smart-94e162af-df8a-47da-bba2-e2af316bdaee
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2681308974 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_tl_errors.2681308974
Directory /workspace/0.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_errors.2852518682
Short name T755
Test name
Test status
Simulation time 34427708171 ps
CPU time 36.86 seconds
Started Mar 17 03:03:29 PM PDT 24
Finished Mar 17 03:04:07 PM PDT 24
Peak memory 217552 kb
Host smart-ba0c88f1-4331-49d3-b378-8da96f4a6e3d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2852518682 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_tl_errors.2852518682
Directory /workspace/0.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_intg_err.1808694213
Short name T866
Test name
Test status
Simulation time 609135777 ps
CPU time 83.04 seconds
Started Mar 17 03:03:26 PM PDT 24
Finished Mar 17 03:04:50 PM PDT 24
Peak memory 213132 kb
Host smart-047f8d8f-0807-4c45-a6a7-4ba6896495f1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1808694213 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_tl_in
tg_err.1808694213
Directory /workspace/0.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_intg_err.3392309052
Short name T118
Test name
Test status
Simulation time 170922661 ps
CPU time 37.23 seconds
Started Mar 17 01:46:37 PM PDT 24
Finished Mar 17 01:47:14 PM PDT 24
Peak memory 210912 kb
Host smart-d6aac4c5-7311-4e7b-bbd9-ef6bbb58ccef
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3392309052 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_tl_in
tg_err.3392309052
Directory /workspace/0.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_aliasing.3990139412
Short name T86
Test name
Test status
Simulation time 7035543694 ps
CPU time 14.51 seconds
Started Mar 17 01:46:21 PM PDT 24
Finished Mar 17 01:46:41 PM PDT 24
Peak memory 210976 kb
Host smart-3a49eb99-a29f-45ef-8d35-581e96f97e0e
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3990139412 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_alia
sing.3990139412
Directory /workspace/1.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_aliasing.790444085
Short name T917
Test name
Test status
Simulation time 14085843712 ps
CPU time 28.82 seconds
Started Mar 17 03:03:31 PM PDT 24
Finished Mar 17 03:04:01 PM PDT 24
Peak memory 211968 kb
Host smart-cb0b6b1c-db31-4820-bb02-e8c2cd71ada4
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=790444085 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_alias
ing.790444085
Directory /workspace/1.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_bit_bash.1547676259
Short name T894
Test name
Test status
Simulation time 14734382297 ps
CPU time 13.61 seconds
Started Mar 17 03:03:30 PM PDT 24
Finished Mar 17 03:03:44 PM PDT 24
Peak memory 211040 kb
Host smart-ef179ca7-2a79-4b30-9539-8f8c13f5e8cb
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1547676259 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_bit_
bash.1547676259
Directory /workspace/1.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_bit_bash.2137190958
Short name T896
Test name
Test status
Simulation time 3949294483 ps
CPU time 10.25 seconds
Started Mar 17 01:46:17 PM PDT 24
Finished Mar 17 01:46:28 PM PDT 24
Peak memory 210964 kb
Host smart-a9774360-0cfb-41b8-abbf-f1ece08c2988
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2137190958 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_bit_
bash.2137190958
Directory /workspace/1.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_hw_reset.2145786495
Short name T868
Test name
Test status
Simulation time 3308328473 ps
CPU time 8.84 seconds
Started Mar 17 01:46:36 PM PDT 24
Finished Mar 17 01:46:45 PM PDT 24
Peak memory 210884 kb
Host smart-da4842c7-8b23-48b9-bf62-1ba240709460
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2145786495 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_hw_r
eset.2145786495
Directory /workspace/1.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_mem_rw_with_rand_reset.4163980674
Short name T784
Test name
Test status
Simulation time 376679803 ps
CPU time 4.5 seconds
Started Mar 17 01:46:17 PM PDT 24
Finished Mar 17 01:46:22 PM PDT 24
Peak memory 212720 kb
Host smart-ba627176-c5a8-485b-9ce3-17ef714e4c5f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4163980674 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 1.rom_ctrl_csr_mem_rw_with_rand_reset.4163980674
Directory /workspace/1.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_mem_rw_with_rand_reset.848105283
Short name T692
Test name
Test status
Simulation time 1669618225 ps
CPU time 20.73 seconds
Started Mar 17 03:03:27 PM PDT 24
Finished Mar 17 03:03:48 PM PDT 24
Peak memory 217136 kb
Host smart-e04e4414-e022-4939-9999-a3ebfcb1d6be
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=848105283 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 1.rom_ctrl_csr_mem_rw_with_rand_reset.848105283
Directory /workspace/1.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_rw.2793713128
Short name T805
Test name
Test status
Simulation time 3836291315 ps
CPU time 29.15 seconds
Started Mar 17 03:03:30 PM PDT 24
Finished Mar 17 03:03:59 PM PDT 24
Peak memory 210960 kb
Host smart-28bef62c-248a-44ce-bf48-5a9ed6daa1f0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2793713128 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_rw.2793713128
Directory /workspace/1.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_rw.4204484479
Short name T72
Test name
Test status
Simulation time 1836303386 ps
CPU time 14.85 seconds
Started Mar 17 01:46:36 PM PDT 24
Finished Mar 17 01:46:52 PM PDT 24
Peak memory 210880 kb
Host smart-4bbe7e74-1ae7-4305-8f2e-83ceefb09a4a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4204484479 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_rw.4204484479
Directory /workspace/1.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_partial_access.1924001721
Short name T696
Test name
Test status
Simulation time 5854361768 ps
CPU time 25.63 seconds
Started Mar 17 03:03:29 PM PDT 24
Finished Mar 17 03:03:55 PM PDT 24
Peak memory 210928 kb
Host smart-d2a5e311-4849-48bc-af5a-c5f141d076b0
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1924001721 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctr
l_mem_partial_access.1924001721
Directory /workspace/1.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_partial_access.2433034621
Short name T712
Test name
Test status
Simulation time 369978697 ps
CPU time 6.47 seconds
Started Mar 17 01:46:39 PM PDT 24
Finished Mar 17 01:46:47 PM PDT 24
Peak memory 210468 kb
Host smart-1a1fa16e-759a-4ca5-9a71-5d7c1c5b6a25
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2433034621 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctr
l_mem_partial_access.2433034621
Directory /workspace/1.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_walk.3356067977
Short name T689
Test name
Test status
Simulation time 85573550 ps
CPU time 4.11 seconds
Started Mar 17 01:46:32 PM PDT 24
Finished Mar 17 01:46:36 PM PDT 24
Peak memory 210812 kb
Host smart-f47c2a2a-b7b2-43b3-8d23-cedc6b8c9837
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3356067977 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_mem_walk
.3356067977
Directory /workspace/1.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_walk.996695879
Short name T913
Test name
Test status
Simulation time 11795056173 ps
CPU time 21.18 seconds
Started Mar 17 03:03:29 PM PDT 24
Finished Mar 17 03:03:51 PM PDT 24
Peak memory 210832 kb
Host smart-8befeb75-e04b-48e4-a331-edf493eccc97
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=996695879 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_mem_walk.
996695879
Directory /workspace/1.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_passthru_mem_tl_intg_err.1622733056
Short name T57
Test name
Test status
Simulation time 1799312988 ps
CPU time 18.39 seconds
Started Mar 17 01:46:33 PM PDT 24
Finished Mar 17 01:46:52 PM PDT 24
Peak memory 210908 kb
Host smart-840a1af4-2cb0-4c49-86df-1d100f85469f
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1622733056 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_pa
ssthru_mem_tl_intg_err.1622733056
Directory /workspace/1.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_passthru_mem_tl_intg_err.4088068354
Short name T833
Test name
Test status
Simulation time 22361335296 ps
CPU time 72.53 seconds
Started Mar 17 03:03:29 PM PDT 24
Finished Mar 17 03:04:42 PM PDT 24
Peak memory 214036 kb
Host smart-f2963957-4135-4cbb-9e0e-fe458928db97
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4088068354 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_pa
ssthru_mem_tl_intg_err.4088068354
Directory /workspace/1.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_same_csr_outstanding.1411356242
Short name T77
Test name
Test status
Simulation time 331789479 ps
CPU time 8.23 seconds
Started Mar 17 03:03:30 PM PDT 24
Finished Mar 17 03:03:39 PM PDT 24
Peak memory 210904 kb
Host smart-9ccd0328-cad6-4c29-afd4-7e2bd76d0f64
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1411356242 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_c
trl_same_csr_outstanding.1411356242
Directory /workspace/1.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_same_csr_outstanding.2998312366
Short name T728
Test name
Test status
Simulation time 2305408745 ps
CPU time 12.94 seconds
Started Mar 17 01:46:39 PM PDT 24
Finished Mar 17 01:46:53 PM PDT 24
Peak memory 210984 kb
Host smart-b63ff167-2291-4c2a-97d5-dd9db21e9af2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2998312366 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_c
trl_same_csr_outstanding.2998312366
Directory /workspace/1.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_errors.1732660954
Short name T878
Test name
Test status
Simulation time 24504589935 ps
CPU time 27.06 seconds
Started Mar 17 03:03:31 PM PDT 24
Finished Mar 17 03:03:58 PM PDT 24
Peak memory 218536 kb
Host smart-b2e0b0d8-ca23-4c34-922f-a574a9901065
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1732660954 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_tl_errors.1732660954
Directory /workspace/1.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_errors.3958934648
Short name T793
Test name
Test status
Simulation time 462133234 ps
CPU time 8.04 seconds
Started Mar 17 01:46:19 PM PDT 24
Finished Mar 17 01:46:27 PM PDT 24
Peak memory 219116 kb
Host smart-5f9488a1-dc99-4a45-ba29-4214c9abe4f0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3958934648 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_tl_errors.3958934648
Directory /workspace/1.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_intg_err.3005206521
Short name T55
Test name
Test status
Simulation time 17566049856 ps
CPU time 170.82 seconds
Started Mar 17 03:03:29 PM PDT 24
Finished Mar 17 03:06:20 PM PDT 24
Peak memory 213816 kb
Host smart-9d84127b-b47b-4e91-bc3e-14fa39f66a2c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3005206521 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_tl_in
tg_err.3005206521
Directory /workspace/1.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_intg_err.418044336
Short name T848
Test name
Test status
Simulation time 2623835040 ps
CPU time 75.77 seconds
Started Mar 17 01:46:18 PM PDT 24
Finished Mar 17 01:47:34 PM PDT 24
Peak memory 219100 kb
Host smart-5a536113-27ef-426a-8a08-7f6ede368f20
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=418044336 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_tl_int
g_err.418044336
Directory /workspace/1.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_mem_rw_with_rand_reset.1628681182
Short name T688
Test name
Test status
Simulation time 10244941848 ps
CPU time 23.81 seconds
Started Mar 17 03:03:38 PM PDT 24
Finished Mar 17 03:04:02 PM PDT 24
Peak memory 217424 kb
Host smart-4bb47d36-7558-4d4b-a846-04cf6f7ca545
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1628681182 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 10.rom_ctrl_csr_mem_rw_with_rand_reset.1628681182
Directory /workspace/10.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_mem_rw_with_rand_reset.3759365943
Short name T791
Test name
Test status
Simulation time 1984679000 ps
CPU time 15.93 seconds
Started Mar 17 01:46:46 PM PDT 24
Finished Mar 17 01:47:03 PM PDT 24
Peak memory 219112 kb
Host smart-4831f971-f649-4866-8aa7-0edd3f35474f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3759365943 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 10.rom_ctrl_csr_mem_rw_with_rand_reset.3759365943
Directory /workspace/10.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_rw.1643870051
Short name T844
Test name
Test status
Simulation time 3025379335 ps
CPU time 23.65 seconds
Started Mar 17 03:03:43 PM PDT 24
Finished Mar 17 03:04:07 PM PDT 24
Peak memory 211596 kb
Host smart-bbc8eb63-56bc-4c3c-82b2-6ea332915ccd
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1643870051 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_csr_rw.1643870051
Directory /workspace/10.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_rw.430842432
Short name T709
Test name
Test status
Simulation time 1930258233 ps
CPU time 15.65 seconds
Started Mar 17 01:46:39 PM PDT 24
Finished Mar 17 01:46:56 PM PDT 24
Peak memory 210908 kb
Host smart-ddc15d27-b77d-4a9e-9522-1e1bbb4850a3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=430842432 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_csr_rw.430842432
Directory /workspace/10.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_passthru_mem_tl_intg_err.1522455794
Short name T735
Test name
Test status
Simulation time 23791923531 ps
CPU time 62.73 seconds
Started Mar 17 01:46:38 PM PDT 24
Finished Mar 17 01:47:42 PM PDT 24
Peak memory 210884 kb
Host smart-4e67df59-83a5-47e6-a352-77855d9dd134
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1522455794 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_p
assthru_mem_tl_intg_err.1522455794
Directory /workspace/10.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_passthru_mem_tl_intg_err.2214174984
Short name T902
Test name
Test status
Simulation time 80842852054 ps
CPU time 185.41 seconds
Started Mar 17 03:03:39 PM PDT 24
Finished Mar 17 03:06:45 PM PDT 24
Peak memory 215160 kb
Host smart-4bcddcb1-8d6d-45cf-be65-dbbf7292d388
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2214174984 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_p
assthru_mem_tl_intg_err.2214174984
Directory /workspace/10.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_same_csr_outstanding.132327016
Short name T828
Test name
Test status
Simulation time 7491297301 ps
CPU time 20.48 seconds
Started Mar 17 03:03:43 PM PDT 24
Finished Mar 17 03:04:04 PM PDT 24
Peak memory 212428 kb
Host smart-5b5d375d-eea2-4584-a1c5-2d061168b78e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=132327016 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_c
trl_same_csr_outstanding.132327016
Directory /workspace/10.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_same_csr_outstanding.2543132196
Short name T909
Test name
Test status
Simulation time 1203190701 ps
CPU time 7.15 seconds
Started Mar 17 01:46:43 PM PDT 24
Finished Mar 17 01:46:52 PM PDT 24
Peak memory 211132 kb
Host smart-96c06453-6b73-4613-9bca-652279903c71
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2543132196 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_
ctrl_same_csr_outstanding.2543132196
Directory /workspace/10.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_errors.1366244962
Short name T845
Test name
Test status
Simulation time 1044916483 ps
CPU time 10.83 seconds
Started Mar 17 01:46:36 PM PDT 24
Finished Mar 17 01:46:47 PM PDT 24
Peak memory 219148 kb
Host smart-380721df-29af-49b8-9003-cf28a6828ef8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1366244962 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_tl_errors.1366244962
Directory /workspace/10.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_errors.3798293278
Short name T824
Test name
Test status
Simulation time 19224342804 ps
CPU time 26.43 seconds
Started Mar 17 03:03:42 PM PDT 24
Finished Mar 17 03:04:09 PM PDT 24
Peak memory 218448 kb
Host smart-3729357d-163c-4708-8b0b-4c4ec9e87c61
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3798293278 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_tl_errors.3798293278
Directory /workspace/10.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_intg_err.3283606122
Short name T882
Test name
Test status
Simulation time 405553314 ps
CPU time 71.99 seconds
Started Mar 17 01:46:41 PM PDT 24
Finished Mar 17 01:47:54 PM PDT 24
Peak memory 211872 kb
Host smart-60ca3cb4-b7d4-4a77-9556-1d82dbcd52f5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3283606122 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_tl_i
ntg_err.3283606122
Directory /workspace/10.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_intg_err.4017938206
Short name T751
Test name
Test status
Simulation time 5501283925 ps
CPU time 95.53 seconds
Started Mar 17 03:03:40 PM PDT 24
Finished Mar 17 03:05:16 PM PDT 24
Peak memory 213256 kb
Host smart-8c484190-1fb4-405f-a127-5a7d95fcffea
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4017938206 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_tl_i
ntg_err.4017938206
Directory /workspace/10.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_mem_rw_with_rand_reset.3226601687
Short name T832
Test name
Test status
Simulation time 6861586867 ps
CPU time 18.78 seconds
Started Mar 17 03:03:48 PM PDT 24
Finished Mar 17 03:04:07 PM PDT 24
Peak memory 215812 kb
Host smart-e38b9486-35dc-4982-bee6-afa277202ff0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3226601687 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 11.rom_ctrl_csr_mem_rw_with_rand_reset.3226601687
Directory /workspace/11.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_mem_rw_with_rand_reset.853194963
Short name T826
Test name
Test status
Simulation time 1288745792 ps
CPU time 7.09 seconds
Started Mar 17 01:46:45 PM PDT 24
Finished Mar 17 01:46:54 PM PDT 24
Peak memory 219112 kb
Host smart-dd7c655a-213b-4e8e-a7ec-18292e5fa59c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=853194963 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 11.rom_ctrl_csr_mem_rw_with_rand_reset.853194963
Directory /workspace/11.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_rw.2557344350
Short name T854
Test name
Test status
Simulation time 2787669594 ps
CPU time 24.26 seconds
Started Mar 17 03:03:48 PM PDT 24
Finished Mar 17 03:04:12 PM PDT 24
Peak memory 211004 kb
Host smart-b09d359c-357d-423d-9c44-9b2d65222588
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2557344350 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_csr_rw.2557344350
Directory /workspace/11.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_rw.3676003637
Short name T720
Test name
Test status
Simulation time 3001148684 ps
CPU time 7.98 seconds
Started Mar 17 01:46:40 PM PDT 24
Finished Mar 17 01:46:49 PM PDT 24
Peak memory 210940 kb
Host smart-c2f3bd6c-0fcb-47e7-8ed0-e3def0c6b9f8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3676003637 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_csr_rw.3676003637
Directory /workspace/11.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_passthru_mem_tl_intg_err.3672777150
Short name T901
Test name
Test status
Simulation time 178720454836 ps
CPU time 105.07 seconds
Started Mar 17 01:46:38 PM PDT 24
Finished Mar 17 01:48:26 PM PDT 24
Peak memory 210992 kb
Host smart-54d7d271-86f8-4880-b4e4-10e7c0b50b5a
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3672777150 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_p
assthru_mem_tl_intg_err.3672777150
Directory /workspace/11.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_passthru_mem_tl_intg_err.799456846
Short name T880
Test name
Test status
Simulation time 16121855427 ps
CPU time 145.12 seconds
Started Mar 17 03:03:44 PM PDT 24
Finished Mar 17 03:06:09 PM PDT 24
Peak memory 215456 kb
Host smart-3ebed04a-f5b3-4f6b-8c30-65fdf0ea6681
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=799456846 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_pa
ssthru_mem_tl_intg_err.799456846
Directory /workspace/11.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_same_csr_outstanding.1400939795
Short name T729
Test name
Test status
Simulation time 1880926693 ps
CPU time 13.83 seconds
Started Mar 17 01:46:40 PM PDT 24
Finished Mar 17 01:46:55 PM PDT 24
Peak memory 210876 kb
Host smart-742cd284-b9c7-425c-8bd1-f4c163def851
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1400939795 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_
ctrl_same_csr_outstanding.1400939795
Directory /workspace/11.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_same_csr_outstanding.678615813
Short name T852
Test name
Test status
Simulation time 17715567344 ps
CPU time 32.09 seconds
Started Mar 17 03:03:43 PM PDT 24
Finished Mar 17 03:04:16 PM PDT 24
Peak memory 212224 kb
Host smart-83ce166a-b60e-440b-be07-303a544efc56
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=678615813 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_c
trl_same_csr_outstanding.678615813
Directory /workspace/11.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_errors.36666148
Short name T685
Test name
Test status
Simulation time 309306100 ps
CPU time 6.45 seconds
Started Mar 17 01:46:34 PM PDT 24
Finished Mar 17 01:46:41 PM PDT 24
Peak memory 219112 kb
Host smart-4de27a40-dde6-426a-bcd6-d0700e8c9a50
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36666148 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_tl_errors.36666148
Directory /workspace/11.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_errors.3726857235
Short name T695
Test name
Test status
Simulation time 5832290993 ps
CPU time 16.35 seconds
Started Mar 17 03:03:46 PM PDT 24
Finished Mar 17 03:04:03 PM PDT 24
Peak memory 217952 kb
Host smart-093e3c1d-1434-49db-97b0-f999546e7f87
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3726857235 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_tl_errors.3726857235
Directory /workspace/11.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_intg_err.1673240878
Short name T121
Test name
Test status
Simulation time 1959889808 ps
CPU time 77.75 seconds
Started Mar 17 01:46:36 PM PDT 24
Finished Mar 17 01:47:54 PM PDT 24
Peak memory 210908 kb
Host smart-b8dd9f73-305e-4e87-a63c-acccb42b93a7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1673240878 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_tl_i
ntg_err.1673240878
Directory /workspace/11.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_intg_err.3562502021
Short name T892
Test name
Test status
Simulation time 5849610339 ps
CPU time 86.32 seconds
Started Mar 17 03:03:45 PM PDT 24
Finished Mar 17 03:05:12 PM PDT 24
Peak memory 212480 kb
Host smart-16c93895-3d18-4f73-9e0b-9d3f712063eb
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3562502021 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_tl_i
ntg_err.3562502021
Directory /workspace/11.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_mem_rw_with_rand_reset.1036821444
Short name T915
Test name
Test status
Simulation time 1622609827 ps
CPU time 13.57 seconds
Started Mar 17 01:46:48 PM PDT 24
Finished Mar 17 01:47:02 PM PDT 24
Peak memory 213168 kb
Host smart-3b5f97d0-b0e1-4061-9097-9ee7112c1d71
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1036821444 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 12.rom_ctrl_csr_mem_rw_with_rand_reset.1036821444
Directory /workspace/12.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_mem_rw_with_rand_reset.993929276
Short name T898
Test name
Test status
Simulation time 350213064 ps
CPU time 8.4 seconds
Started Mar 17 03:03:44 PM PDT 24
Finished Mar 17 03:03:53 PM PDT 24
Peak memory 214388 kb
Host smart-c26cfc2d-4064-4e3c-ac80-ecd90086d1e8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=993929276 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 12.rom_ctrl_csr_mem_rw_with_rand_reset.993929276
Directory /workspace/12.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_rw.1356556173
Short name T808
Test name
Test status
Simulation time 2320218895 ps
CPU time 21.58 seconds
Started Mar 17 03:03:44 PM PDT 24
Finished Mar 17 03:04:06 PM PDT 24
Peak memory 210988 kb
Host smart-5918a0f5-4e9c-481f-84ed-ede359e651bc
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1356556173 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_csr_rw.1356556173
Directory /workspace/12.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_rw.327132231
Short name T853
Test name
Test status
Simulation time 362916959 ps
CPU time 4.21 seconds
Started Mar 17 01:46:43 PM PDT 24
Finished Mar 17 01:46:49 PM PDT 24
Peak memory 210832 kb
Host smart-c3ab8a27-3c0a-4e91-97a1-281d984e1641
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=327132231 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_csr_rw.327132231
Directory /workspace/12.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_passthru_mem_tl_intg_err.2902151561
Short name T765
Test name
Test status
Simulation time 32824746626 ps
CPU time 84.6 seconds
Started Mar 17 03:03:44 PM PDT 24
Finished Mar 17 03:05:09 PM PDT 24
Peak memory 214004 kb
Host smart-4e86cb53-bce6-4cb8-b722-063140bb7ccd
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2902151561 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_p
assthru_mem_tl_intg_err.2902151561
Directory /workspace/12.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_passthru_mem_tl_intg_err.82438918
Short name T884
Test name
Test status
Simulation time 5725755101 ps
CPU time 48.99 seconds
Started Mar 17 01:46:37 PM PDT 24
Finished Mar 17 01:47:26 PM PDT 24
Peak memory 210928 kb
Host smart-8989646a-7a2f-4901-839a-cfcfeab956ee
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82438918 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_pas
sthru_mem_tl_intg_err.82438918
Directory /workspace/12.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_same_csr_outstanding.2129637500
Short name T795
Test name
Test status
Simulation time 1738953565 ps
CPU time 9.79 seconds
Started Mar 17 01:46:40 PM PDT 24
Finished Mar 17 01:46:52 PM PDT 24
Peak memory 210884 kb
Host smart-ca456099-3463-40fa-aac0-d9d9d89c53de
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2129637500 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_
ctrl_same_csr_outstanding.2129637500
Directory /workspace/12.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_same_csr_outstanding.3119699993
Short name T105
Test name
Test status
Simulation time 2518282830 ps
CPU time 26.4 seconds
Started Mar 17 03:03:46 PM PDT 24
Finished Mar 17 03:04:13 PM PDT 24
Peak memory 212196 kb
Host smart-98887e7f-e18a-443d-a871-495de4d608b4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3119699993 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_
ctrl_same_csr_outstanding.3119699993
Directory /workspace/12.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_errors.3584547661
Short name T841
Test name
Test status
Simulation time 6904418342 ps
CPU time 32.02 seconds
Started Mar 17 03:03:47 PM PDT 24
Finished Mar 17 03:04:19 PM PDT 24
Peak memory 218136 kb
Host smart-7a2e5715-b173-44ec-baa0-0234c11a28df
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3584547661 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_tl_errors.3584547661
Directory /workspace/12.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_errors.803506873
Short name T693
Test name
Test status
Simulation time 3881144355 ps
CPU time 18.39 seconds
Started Mar 17 01:46:34 PM PDT 24
Finished Mar 17 01:46:53 PM PDT 24
Peak memory 219192 kb
Host smart-6ed47716-3578-4064-a7f3-6326956f9389
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=803506873 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_tl_errors.803506873
Directory /workspace/12.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_intg_err.449291752
Short name T910
Test name
Test status
Simulation time 180203511 ps
CPU time 37.63 seconds
Started Mar 17 01:46:33 PM PDT 24
Finished Mar 17 01:47:11 PM PDT 24
Peak memory 211780 kb
Host smart-d7aaf6e6-cd03-4a4a-91eb-0cd89790137c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=449291752 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_tl_in
tg_err.449291752
Directory /workspace/12.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_mem_rw_with_rand_reset.3901225978
Short name T706
Test name
Test status
Simulation time 2959552788 ps
CPU time 12.91 seconds
Started Mar 17 01:46:37 PM PDT 24
Finished Mar 17 01:46:50 PM PDT 24
Peak memory 214216 kb
Host smart-8e6f7d66-3e54-4de3-81ba-25dad802e1bc
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3901225978 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 13.rom_ctrl_csr_mem_rw_with_rand_reset.3901225978
Directory /workspace/13.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_mem_rw_with_rand_reset.4232572056
Short name T711
Test name
Test status
Simulation time 11803409125 ps
CPU time 20.96 seconds
Started Mar 17 03:03:44 PM PDT 24
Finished Mar 17 03:04:05 PM PDT 24
Peak memory 218176 kb
Host smart-bf55074a-1830-41c3-aab9-eb930f5f560a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4232572056 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 13.rom_ctrl_csr_mem_rw_with_rand_reset.4232572056
Directory /workspace/13.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_rw.1580008818
Short name T846
Test name
Test status
Simulation time 1966940287 ps
CPU time 15.02 seconds
Started Mar 17 01:46:47 PM PDT 24
Finished Mar 17 01:47:03 PM PDT 24
Peak memory 210848 kb
Host smart-08bbc92a-47dc-4f27-83d3-c26da3ffcdd7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1580008818 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_csr_rw.1580008818
Directory /workspace/13.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_rw.3394145132
Short name T746
Test name
Test status
Simulation time 1964450619 ps
CPU time 10.64 seconds
Started Mar 17 03:03:47 PM PDT 24
Finished Mar 17 03:03:58 PM PDT 24
Peak memory 210900 kb
Host smart-6843564b-a8f2-4fdb-b4de-cde3fff871b5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3394145132 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_csr_rw.3394145132
Directory /workspace/13.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_passthru_mem_tl_intg_err.1520998352
Short name T840
Test name
Test status
Simulation time 2731916781 ps
CPU time 37 seconds
Started Mar 17 03:03:43 PM PDT 24
Finished Mar 17 03:04:20 PM PDT 24
Peak memory 212984 kb
Host smart-0903297c-b1fb-4e18-8b87-cb979c27eb32
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1520998352 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_p
assthru_mem_tl_intg_err.1520998352
Directory /workspace/13.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_passthru_mem_tl_intg_err.177590283
Short name T718
Test name
Test status
Simulation time 7548224744 ps
CPU time 61.81 seconds
Started Mar 17 01:46:51 PM PDT 24
Finished Mar 17 01:47:53 PM PDT 24
Peak memory 210912 kb
Host smart-4fcc3e1b-8118-4173-88ef-0445d36a5244
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=177590283 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_pa
ssthru_mem_tl_intg_err.177590283
Directory /workspace/13.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_same_csr_outstanding.169562638
Short name T107
Test name
Test status
Simulation time 4645904799 ps
CPU time 19.91 seconds
Started Mar 17 03:03:46 PM PDT 24
Finished Mar 17 03:04:06 PM PDT 24
Peak memory 212400 kb
Host smart-8f84dbd2-6397-4c63-a230-ad8cbd82e876
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=169562638 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_c
trl_same_csr_outstanding.169562638
Directory /workspace/13.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_same_csr_outstanding.987308985
Short name T734
Test name
Test status
Simulation time 346245688 ps
CPU time 4.19 seconds
Started Mar 17 01:46:39 PM PDT 24
Finished Mar 17 01:46:45 PM PDT 24
Peak memory 210888 kb
Host smart-c5043495-3cf4-4ce8-9e54-2b0683a29808
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=987308985 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_c
trl_same_csr_outstanding.987308985
Directory /workspace/13.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_errors.2170540184
Short name T881
Test name
Test status
Simulation time 750882503 ps
CPU time 12.46 seconds
Started Mar 17 03:03:47 PM PDT 24
Finished Mar 17 03:04:00 PM PDT 24
Peak memory 217124 kb
Host smart-8c24b599-4199-42f2-8b8b-1780fa34383d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2170540184 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_tl_errors.2170540184
Directory /workspace/13.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_errors.89601485
Short name T737
Test name
Test status
Simulation time 332660235 ps
CPU time 10.07 seconds
Started Mar 17 01:46:41 PM PDT 24
Finished Mar 17 01:46:53 PM PDT 24
Peak memory 219132 kb
Host smart-2215be27-83a0-4c31-a1b1-aed35f9a9f16
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89601485 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_tl_errors.89601485
Directory /workspace/13.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_intg_err.3338459938
Short name T817
Test name
Test status
Simulation time 3104529321 ps
CPU time 167.14 seconds
Started Mar 17 03:03:47 PM PDT 24
Finished Mar 17 03:06:35 PM PDT 24
Peak memory 213596 kb
Host smart-f7e8dec1-b9a4-442a-a18f-f852a7af0290
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3338459938 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_tl_i
ntg_err.3338459938
Directory /workspace/13.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_intg_err.3654813291
Short name T766
Test name
Test status
Simulation time 1706320209 ps
CPU time 44.02 seconds
Started Mar 17 01:46:47 PM PDT 24
Finished Mar 17 01:47:32 PM PDT 24
Peak memory 211392 kb
Host smart-ecaba4d9-a50c-4856-92e0-2b0e118fba9a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3654813291 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_tl_i
ntg_err.3654813291
Directory /workspace/13.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_mem_rw_with_rand_reset.3392095923
Short name T747
Test name
Test status
Simulation time 430642075 ps
CPU time 5.18 seconds
Started Mar 17 01:46:57 PM PDT 24
Finished Mar 17 01:47:02 PM PDT 24
Peak memory 219048 kb
Host smart-fa08140c-188f-4a30-9dfa-7454be59ca15
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3392095923 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 14.rom_ctrl_csr_mem_rw_with_rand_reset.3392095923
Directory /workspace/14.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_mem_rw_with_rand_reset.740541076
Short name T687
Test name
Test status
Simulation time 261608397 ps
CPU time 11.28 seconds
Started Mar 17 03:03:47 PM PDT 24
Finished Mar 17 03:03:58 PM PDT 24
Peak memory 216896 kb
Host smart-e89e9ef6-4889-4c50-a0f6-4e8b43eb711c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=740541076 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 14.rom_ctrl_csr_mem_rw_with_rand_reset.740541076
Directory /workspace/14.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_rw.1022749269
Short name T886
Test name
Test status
Simulation time 12559715853 ps
CPU time 27.03 seconds
Started Mar 17 03:03:45 PM PDT 24
Finished Mar 17 03:04:12 PM PDT 24
Peak memory 211748 kb
Host smart-b349e0aa-0043-4ef2-a9fa-9037b682c2d7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1022749269 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_csr_rw.1022749269
Directory /workspace/14.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_rw.1623396972
Short name T891
Test name
Test status
Simulation time 3800484944 ps
CPU time 9.66 seconds
Started Mar 17 01:46:45 PM PDT 24
Finished Mar 17 01:46:56 PM PDT 24
Peak memory 210908 kb
Host smart-04f36246-601e-4e53-973a-5017066f3b8c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1623396972 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_csr_rw.1623396972
Directory /workspace/14.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_passthru_mem_tl_intg_err.3634736167
Short name T90
Test name
Test status
Simulation time 27891444262 ps
CPU time 66.63 seconds
Started Mar 17 01:46:46 PM PDT 24
Finished Mar 17 01:47:53 PM PDT 24
Peak memory 210912 kb
Host smart-29f10d69-a76d-4920-b1c2-568e1e548101
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3634736167 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_p
assthru_mem_tl_intg_err.3634736167
Directory /workspace/14.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_passthru_mem_tl_intg_err.4106010723
Short name T85
Test name
Test status
Simulation time 3436258568 ps
CPU time 37.54 seconds
Started Mar 17 03:03:47 PM PDT 24
Finished Mar 17 03:04:24 PM PDT 24
Peak memory 213964 kb
Host smart-187539fd-0a81-47f2-8466-8fe92304aa69
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4106010723 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_p
assthru_mem_tl_intg_err.4106010723
Directory /workspace/14.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_same_csr_outstanding.2680687915
Short name T777
Test name
Test status
Simulation time 346347484 ps
CPU time 10.53 seconds
Started Mar 17 03:03:47 PM PDT 24
Finished Mar 17 03:03:57 PM PDT 24
Peak memory 210904 kb
Host smart-c4293305-6aba-4246-ab3e-37bf77d2c4e2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2680687915 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_
ctrl_same_csr_outstanding.2680687915
Directory /workspace/14.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_same_csr_outstanding.388667606
Short name T801
Test name
Test status
Simulation time 183085444 ps
CPU time 4.26 seconds
Started Mar 17 01:46:47 PM PDT 24
Finished Mar 17 01:46:52 PM PDT 24
Peak memory 210804 kb
Host smart-f37253a4-e147-4740-bd09-5f1db36b49f4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=388667606 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_c
trl_same_csr_outstanding.388667606
Directory /workspace/14.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_errors.1924118542
Short name T726
Test name
Test status
Simulation time 636848275 ps
CPU time 12.07 seconds
Started Mar 17 03:03:44 PM PDT 24
Finished Mar 17 03:03:57 PM PDT 24
Peak memory 217004 kb
Host smart-04d167df-8d0e-4b18-837c-107d380a9d81
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1924118542 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_tl_errors.1924118542
Directory /workspace/14.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_errors.31994833
Short name T733
Test name
Test status
Simulation time 1596833156 ps
CPU time 16.9 seconds
Started Mar 17 01:46:32 PM PDT 24
Finished Mar 17 01:46:49 PM PDT 24
Peak memory 219140 kb
Host smart-93be7aef-3380-4e9b-b93d-4490fa2640be
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31994833 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_tl_errors.31994833
Directory /workspace/14.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_intg_err.2332380111
Short name T129
Test name
Test status
Simulation time 604574215 ps
CPU time 87.42 seconds
Started Mar 17 03:03:47 PM PDT 24
Finished Mar 17 03:05:14 PM PDT 24
Peak memory 213232 kb
Host smart-ac155838-948f-4f11-a99c-111ef4f296d9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2332380111 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_tl_i
ntg_err.2332380111
Directory /workspace/14.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_intg_err.2978449986
Short name T849
Test name
Test status
Simulation time 1580290334 ps
CPU time 43.29 seconds
Started Mar 17 01:46:45 PM PDT 24
Finished Mar 17 01:47:30 PM PDT 24
Peak memory 211684 kb
Host smart-fd091ed5-51e3-4489-8b2e-9d9c056dc2ea
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2978449986 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_tl_i
ntg_err.2978449986
Directory /workspace/14.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_mem_rw_with_rand_reset.1504431880
Short name T752
Test name
Test status
Simulation time 11360670054 ps
CPU time 23.7 seconds
Started Mar 17 03:03:52 PM PDT 24
Finished Mar 17 03:04:17 PM PDT 24
Peak memory 217556 kb
Host smart-ca6f0071-aa04-46ef-8462-ee0f22ca74ca
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1504431880 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 15.rom_ctrl_csr_mem_rw_with_rand_reset.1504431880
Directory /workspace/15.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_mem_rw_with_rand_reset.212742078
Short name T782
Test name
Test status
Simulation time 1544584220 ps
CPU time 7 seconds
Started Mar 17 01:46:38 PM PDT 24
Finished Mar 17 01:46:45 PM PDT 24
Peak memory 219196 kb
Host smart-36805f1e-16f0-4b61-9b97-1231c832ba5a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=212742078 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 15.rom_ctrl_csr_mem_rw_with_rand_reset.212742078
Directory /workspace/15.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_rw.2428353412
Short name T837
Test name
Test status
Simulation time 662036787 ps
CPU time 8.19 seconds
Started Mar 17 03:03:51 PM PDT 24
Finished Mar 17 03:04:00 PM PDT 24
Peak memory 210916 kb
Host smart-5947b73e-725e-449d-9cf5-b91099560f91
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2428353412 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_csr_rw.2428353412
Directory /workspace/15.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_rw.3505466336
Short name T797
Test name
Test status
Simulation time 2765534209 ps
CPU time 12.63 seconds
Started Mar 17 01:46:38 PM PDT 24
Finished Mar 17 01:46:57 PM PDT 24
Peak memory 211076 kb
Host smart-7cba8fd5-9b5c-436d-a9c6-695e58f23520
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3505466336 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_csr_rw.3505466336
Directory /workspace/15.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_passthru_mem_tl_intg_err.1252474765
Short name T74
Test name
Test status
Simulation time 37155503080 ps
CPU time 80.38 seconds
Started Mar 17 01:46:36 PM PDT 24
Finished Mar 17 01:47:57 PM PDT 24
Peak memory 210900 kb
Host smart-c11e868d-e177-4dcf-b9de-11155b223e0c
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1252474765 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_p
assthru_mem_tl_intg_err.1252474765
Directory /workspace/15.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_passthru_mem_tl_intg_err.591726984
Short name T874
Test name
Test status
Simulation time 8193824746 ps
CPU time 84.5 seconds
Started Mar 17 03:03:47 PM PDT 24
Finished Mar 17 03:05:12 PM PDT 24
Peak memory 213340 kb
Host smart-bca259f5-5756-491f-ba42-48f66ec99d92
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=591726984 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_pa
ssthru_mem_tl_intg_err.591726984
Directory /workspace/15.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_same_csr_outstanding.1349885958
Short name T875
Test name
Test status
Simulation time 4326469107 ps
CPU time 17.13 seconds
Started Mar 17 03:03:48 PM PDT 24
Finished Mar 17 03:04:05 PM PDT 24
Peak memory 212520 kb
Host smart-6df85c57-5da2-412a-b525-4089bf6a5499
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1349885958 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_
ctrl_same_csr_outstanding.1349885958
Directory /workspace/15.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_same_csr_outstanding.2382858330
Short name T818
Test name
Test status
Simulation time 678870325 ps
CPU time 8.51 seconds
Started Mar 17 01:46:47 PM PDT 24
Finished Mar 17 01:46:57 PM PDT 24
Peak memory 210904 kb
Host smart-16902b22-3737-4d53-a597-a02a0a1fdaef
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2382858330 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_
ctrl_same_csr_outstanding.2382858330
Directory /workspace/15.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_errors.3716736546
Short name T749
Test name
Test status
Simulation time 19611413337 ps
CPU time 19.69 seconds
Started Mar 17 01:46:39 PM PDT 24
Finished Mar 17 01:47:00 PM PDT 24
Peak memory 219192 kb
Host smart-0aa36cc8-410d-475a-8807-7a9c95a0270c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3716736546 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_tl_errors.3716736546
Directory /workspace/15.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_errors.550115819
Short name T771
Test name
Test status
Simulation time 1789530810 ps
CPU time 18.56 seconds
Started Mar 17 03:03:44 PM PDT 24
Finished Mar 17 03:04:03 PM PDT 24
Peak memory 218352 kb
Host smart-312da257-5773-40ac-a64d-c5816271b9af
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=550115819 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_tl_errors.550115819
Directory /workspace/15.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_intg_err.1646681431
Short name T115
Test name
Test status
Simulation time 2065704616 ps
CPU time 161.05 seconds
Started Mar 17 03:03:44 PM PDT 24
Finished Mar 17 03:06:25 PM PDT 24
Peak memory 213708 kb
Host smart-2b39fac8-15ab-404c-8cdb-44c8256f643e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1646681431 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_tl_i
ntg_err.1646681431
Directory /workspace/15.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_intg_err.2782732819
Short name T53
Test name
Test status
Simulation time 6919680007 ps
CPU time 44.81 seconds
Started Mar 17 01:46:41 PM PDT 24
Finished Mar 17 01:47:28 PM PDT 24
Peak memory 212224 kb
Host smart-9dc7e6f9-68b5-4bc6-a76f-d2addad4195f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2782732819 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_tl_i
ntg_err.2782732819
Directory /workspace/15.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_mem_rw_with_rand_reset.3851908791
Short name T813
Test name
Test status
Simulation time 7430820454 ps
CPU time 15.62 seconds
Started Mar 17 01:46:41 PM PDT 24
Finished Mar 17 01:46:59 PM PDT 24
Peak memory 219164 kb
Host smart-95ec52de-03e7-4449-9077-3c45ecc88ed9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3851908791 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 16.rom_ctrl_csr_mem_rw_with_rand_reset.3851908791
Directory /workspace/16.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_mem_rw_with_rand_reset.3864577099
Short name T829
Test name
Test status
Simulation time 1624323422 ps
CPU time 18.48 seconds
Started Mar 17 03:03:51 PM PDT 24
Finished Mar 17 03:04:09 PM PDT 24
Peak memory 215632 kb
Host smart-ea1f6142-0262-4282-a684-09576d6d2194
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3864577099 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 16.rom_ctrl_csr_mem_rw_with_rand_reset.3864577099
Directory /workspace/16.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_rw.3121422655
Short name T91
Test name
Test status
Simulation time 1362611942 ps
CPU time 12.64 seconds
Started Mar 17 01:46:46 PM PDT 24
Finished Mar 17 01:46:59 PM PDT 24
Peak memory 210872 kb
Host smart-3a886e5c-432d-4302-8e43-583fd183869c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3121422655 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_csr_rw.3121422655
Directory /workspace/16.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_rw.8174707
Short name T736
Test name
Test status
Simulation time 688215243 ps
CPU time 8.1 seconds
Started Mar 17 03:03:57 PM PDT 24
Finished Mar 17 03:04:07 PM PDT 24
Peak memory 210876 kb
Host smart-a6d22380-0db8-46d1-a668-89f5fee763b9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=8174707 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_csr_rw.8174707
Directory /workspace/16.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_passthru_mem_tl_intg_err.2048813737
Short name T100
Test name
Test status
Simulation time 8515513865 ps
CPU time 87.83 seconds
Started Mar 17 03:03:50 PM PDT 24
Finished Mar 17 03:05:18 PM PDT 24
Peak memory 213976 kb
Host smart-230e84b7-1b28-43dc-ac17-8d063d80684e
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2048813737 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_p
assthru_mem_tl_intg_err.2048813737
Directory /workspace/16.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_passthru_mem_tl_intg_err.3344279216
Short name T814
Test name
Test status
Simulation time 4876292049 ps
CPU time 26.84 seconds
Started Mar 17 01:46:41 PM PDT 24
Finished Mar 17 01:47:10 PM PDT 24
Peak memory 210996 kb
Host smart-a5f92cb2-38b9-4954-929b-1a59ea56af33
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3344279216 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_p
assthru_mem_tl_intg_err.3344279216
Directory /workspace/16.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_same_csr_outstanding.1559122405
Short name T769
Test name
Test status
Simulation time 168377317 ps
CPU time 5.44 seconds
Started Mar 17 01:46:41 PM PDT 24
Finished Mar 17 01:46:48 PM PDT 24
Peak memory 210844 kb
Host smart-79a58fb8-fe89-440e-8562-87cb380d9813
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1559122405 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_
ctrl_same_csr_outstanding.1559122405
Directory /workspace/16.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_same_csr_outstanding.840915454
Short name T102
Test name
Test status
Simulation time 6386845087 ps
CPU time 16.51 seconds
Started Mar 17 03:03:52 PM PDT 24
Finished Mar 17 03:04:09 PM PDT 24
Peak memory 212248 kb
Host smart-6709bbff-d24d-4fdd-a930-e5cb356da6c5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=840915454 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_c
trl_same_csr_outstanding.840915454
Directory /workspace/16.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_errors.1702554542
Short name T907
Test name
Test status
Simulation time 2060208426 ps
CPU time 12.86 seconds
Started Mar 17 03:03:54 PM PDT 24
Finished Mar 17 03:04:07 PM PDT 24
Peak memory 217172 kb
Host smart-0f8e9f77-7096-4d0d-9da7-7b0b9b15ebec
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1702554542 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_tl_errors.1702554542
Directory /workspace/16.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_errors.212342058
Short name T879
Test name
Test status
Simulation time 4686946673 ps
CPU time 12.03 seconds
Started Mar 17 01:46:36 PM PDT 24
Finished Mar 17 01:46:49 PM PDT 24
Peak memory 219184 kb
Host smart-515f1e3a-bd8b-45f2-aa4a-1b4674b5ae8f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=212342058 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_tl_errors.212342058
Directory /workspace/16.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_intg_err.2628565628
Short name T857
Test name
Test status
Simulation time 1783639438 ps
CPU time 159.53 seconds
Started Mar 17 03:03:52 PM PDT 24
Finished Mar 17 03:06:33 PM PDT 24
Peak memory 213728 kb
Host smart-3b2fe5af-e6f8-447b-a365-45ce126d9a44
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2628565628 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_tl_i
ntg_err.2628565628
Directory /workspace/16.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_mem_rw_with_rand_reset.1022645797
Short name T721
Test name
Test status
Simulation time 1080129563 ps
CPU time 8.55 seconds
Started Mar 17 01:46:38 PM PDT 24
Finished Mar 17 01:46:47 PM PDT 24
Peak memory 219168 kb
Host smart-c370bdaf-3897-406a-b613-6ed4edfa3a55
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1022645797 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 17.rom_ctrl_csr_mem_rw_with_rand_reset.1022645797
Directory /workspace/17.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_mem_rw_with_rand_reset.903369673
Short name T811
Test name
Test status
Simulation time 4656989327 ps
CPU time 25.76 seconds
Started Mar 17 03:03:52 PM PDT 24
Finished Mar 17 03:04:19 PM PDT 24
Peak memory 215192 kb
Host smart-0ba73b16-4a7c-485d-b26b-4e0680d91d79
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=903369673 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 17.rom_ctrl_csr_mem_rw_with_rand_reset.903369673
Directory /workspace/17.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_rw.1103312910
Short name T763
Test name
Test status
Simulation time 1524959585 ps
CPU time 12.93 seconds
Started Mar 17 01:46:37 PM PDT 24
Finished Mar 17 01:46:50 PM PDT 24
Peak memory 210856 kb
Host smart-5b2b9901-8662-4a88-9aef-28d13bad4836
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1103312910 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_csr_rw.1103312910
Directory /workspace/17.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_rw.1104404679
Short name T707
Test name
Test status
Simulation time 8226434318 ps
CPU time 31.8 seconds
Started Mar 17 03:03:54 PM PDT 24
Finished Mar 17 03:04:26 PM PDT 24
Peak memory 212164 kb
Host smart-daeafa15-2ade-42cf-923d-eeb7c0a8a82b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1104404679 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_csr_rw.1104404679
Directory /workspace/17.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_passthru_mem_tl_intg_err.1473044298
Short name T820
Test name
Test status
Simulation time 27626006917 ps
CPU time 139.33 seconds
Started Mar 17 03:03:51 PM PDT 24
Finished Mar 17 03:06:10 PM PDT 24
Peak memory 215088 kb
Host smart-7b53d875-7b43-434c-afb3-158c207e1c1d
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1473044298 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_p
assthru_mem_tl_intg_err.1473044298
Directory /workspace/17.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_passthru_mem_tl_intg_err.2527803337
Short name T715
Test name
Test status
Simulation time 34420166225 ps
CPU time 62.02 seconds
Started Mar 17 01:46:45 PM PDT 24
Finished Mar 17 01:47:49 PM PDT 24
Peak memory 211240 kb
Host smart-c0104ed1-eac6-4963-b28e-5b089f75ed59
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2527803337 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_p
assthru_mem_tl_intg_err.2527803337
Directory /workspace/17.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_same_csr_outstanding.2425103095
Short name T108
Test name
Test status
Simulation time 614753403 ps
CPU time 13.77 seconds
Started Mar 17 03:03:51 PM PDT 24
Finished Mar 17 03:04:04 PM PDT 24
Peak memory 212036 kb
Host smart-30c74c0b-57ad-4f21-b1d0-bc9d6e8901e4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2425103095 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_
ctrl_same_csr_outstanding.2425103095
Directory /workspace/17.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_same_csr_outstanding.3495932245
Short name T834
Test name
Test status
Simulation time 1693896572 ps
CPU time 13.95 seconds
Started Mar 17 01:46:38 PM PDT 24
Finished Mar 17 01:46:52 PM PDT 24
Peak memory 210904 kb
Host smart-cc04cdf5-2137-42ff-8a06-a972b4caa707
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3495932245 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_
ctrl_same_csr_outstanding.3495932245
Directory /workspace/17.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_errors.352364076
Short name T717
Test name
Test status
Simulation time 87946076 ps
CPU time 6.51 seconds
Started Mar 17 01:46:39 PM PDT 24
Finished Mar 17 01:46:48 PM PDT 24
Peak memory 219128 kb
Host smart-69909162-6bda-4f90-8c59-f063e1e1457c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=352364076 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_tl_errors.352364076
Directory /workspace/17.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_errors.3923967088
Short name T754
Test name
Test status
Simulation time 8211396385 ps
CPU time 34.79 seconds
Started Mar 17 03:03:51 PM PDT 24
Finished Mar 17 03:04:26 PM PDT 24
Peak memory 217144 kb
Host smart-ea9c7ff0-3d20-445c-904b-adeceb73c4aa
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3923967088 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_tl_errors.3923967088
Directory /workspace/17.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_intg_err.60773468
Short name T117
Test name
Test status
Simulation time 1346456217 ps
CPU time 161.29 seconds
Started Mar 17 03:03:52 PM PDT 24
Finished Mar 17 03:06:34 PM PDT 24
Peak memory 213652 kb
Host smart-6d43ec4c-dbc2-4597-95b9-84e7fea5aa62
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=60773468 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_tl_int
g_err.60773468
Directory /workspace/17.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_mem_rw_with_rand_reset.4103126399
Short name T794
Test name
Test status
Simulation time 1023058714 ps
CPU time 4.77 seconds
Started Mar 17 01:46:36 PM PDT 24
Finished Mar 17 01:46:42 PM PDT 24
Peak memory 214108 kb
Host smart-7c96c4b2-a56b-49f5-b03c-ab31bf936b55
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4103126399 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 18.rom_ctrl_csr_mem_rw_with_rand_reset.4103126399
Directory /workspace/18.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_mem_rw_with_rand_reset.980785730
Short name T827
Test name
Test status
Simulation time 719076873 ps
CPU time 9.42 seconds
Started Mar 17 03:03:57 PM PDT 24
Finished Mar 17 03:04:07 PM PDT 24
Peak memory 216712 kb
Host smart-352f2eae-f77e-45a4-91ab-044cde23d964
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=980785730 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 18.rom_ctrl_csr_mem_rw_with_rand_reset.980785730
Directory /workspace/18.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_rw.2330894339
Short name T732
Test name
Test status
Simulation time 1571505189 ps
CPU time 8.71 seconds
Started Mar 17 01:46:36 PM PDT 24
Finished Mar 17 01:46:45 PM PDT 24
Peak memory 210780 kb
Host smart-7c673052-d243-4bec-9241-7184565f34ad
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2330894339 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_csr_rw.2330894339
Directory /workspace/18.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_rw.4024222459
Short name T780
Test name
Test status
Simulation time 5119928194 ps
CPU time 16.31 seconds
Started Mar 17 03:03:49 PM PDT 24
Finished Mar 17 03:04:06 PM PDT 24
Peak memory 211992 kb
Host smart-400fc565-f62a-4d74-9749-c8be07b8da5a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4024222459 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_csr_rw.4024222459
Directory /workspace/18.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_passthru_mem_tl_intg_err.2539767700
Short name T96
Test name
Test status
Simulation time 12512882661 ps
CPU time 76.5 seconds
Started Mar 17 03:03:51 PM PDT 24
Finished Mar 17 03:05:07 PM PDT 24
Peak memory 214492 kb
Host smart-0bbca141-c875-4d60-bde6-8901ff5463d4
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2539767700 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_p
assthru_mem_tl_intg_err.2539767700
Directory /workspace/18.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_passthru_mem_tl_intg_err.2824180787
Short name T810
Test name
Test status
Simulation time 16406728269 ps
CPU time 67.83 seconds
Started Mar 17 01:46:37 PM PDT 24
Finished Mar 17 01:47:45 PM PDT 24
Peak memory 211012 kb
Host smart-b3e593eb-0d58-44be-befd-d9bb5b7dba8d
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2824180787 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_p
assthru_mem_tl_intg_err.2824180787
Directory /workspace/18.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_same_csr_outstanding.2355409888
Short name T822
Test name
Test status
Simulation time 3039843026 ps
CPU time 25.94 seconds
Started Mar 17 03:03:51 PM PDT 24
Finished Mar 17 03:04:17 PM PDT 24
Peak memory 212232 kb
Host smart-cfa70b9d-6fcc-4a76-9bf8-14f3023dada9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2355409888 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_
ctrl_same_csr_outstanding.2355409888
Directory /workspace/18.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_same_csr_outstanding.3617827774
Short name T104
Test name
Test status
Simulation time 178466195 ps
CPU time 5.85 seconds
Started Mar 17 01:46:53 PM PDT 24
Finished Mar 17 01:46:59 PM PDT 24
Peak memory 210880 kb
Host smart-bc9151a6-a898-4f71-89e1-6e04104d6ffa
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3617827774 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_
ctrl_same_csr_outstanding.3617827774
Directory /workspace/18.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_errors.1048432229
Short name T790
Test name
Test status
Simulation time 1894675144 ps
CPU time 18 seconds
Started Mar 17 01:46:48 PM PDT 24
Finished Mar 17 01:47:06 PM PDT 24
Peak memory 219164 kb
Host smart-37d373b4-b692-4441-ace3-8d153acc9ea1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1048432229 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_tl_errors.1048432229
Directory /workspace/18.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_errors.1718473088
Short name T762
Test name
Test status
Simulation time 905397940 ps
CPU time 18.98 seconds
Started Mar 17 03:03:52 PM PDT 24
Finished Mar 17 03:04:12 PM PDT 24
Peak memory 218228 kb
Host smart-e63cd160-f446-42d0-a15d-4863bb887ff4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1718473088 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_tl_errors.1718473088
Directory /workspace/18.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_intg_err.1498486714
Short name T123
Test name
Test status
Simulation time 1018254247 ps
CPU time 156.1 seconds
Started Mar 17 03:03:49 PM PDT 24
Finished Mar 17 03:06:26 PM PDT 24
Peak memory 213800 kb
Host smart-67cd6e23-cc44-4283-8f46-d9eec83c7ccd
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1498486714 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_tl_i
ntg_err.1498486714
Directory /workspace/18.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_intg_err.167461228
Short name T918
Test name
Test status
Simulation time 1128098946 ps
CPU time 71.69 seconds
Started Mar 17 01:46:44 PM PDT 24
Finished Mar 17 01:47:58 PM PDT 24
Peak memory 211912 kb
Host smart-fd7bcfb2-0e09-4aa6-b24b-1ab3d5fe658b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=167461228 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_tl_in
tg_err.167461228
Directory /workspace/18.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_mem_rw_with_rand_reset.3029946167
Short name T705
Test name
Test status
Simulation time 2701299076 ps
CPU time 15.65 seconds
Started Mar 17 01:46:44 PM PDT 24
Finished Mar 17 01:47:01 PM PDT 24
Peak memory 214184 kb
Host smart-ecb83008-d23a-40b1-a481-bc855c43316e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3029946167 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 19.rom_ctrl_csr_mem_rw_with_rand_reset.3029946167
Directory /workspace/19.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_mem_rw_with_rand_reset.860348567
Short name T724
Test name
Test status
Simulation time 56266806478 ps
CPU time 28.3 seconds
Started Mar 17 03:03:51 PM PDT 24
Finished Mar 17 03:04:20 PM PDT 24
Peak memory 216408 kb
Host smart-404c9cfb-7370-4661-bd79-265af1c50ceb
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=860348567 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 19.rom_ctrl_csr_mem_rw_with_rand_reset.860348567
Directory /workspace/19.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_rw.91332107
Short name T88
Test name
Test status
Simulation time 1241936550 ps
CPU time 12.23 seconds
Started Mar 17 01:46:41 PM PDT 24
Finished Mar 17 01:46:55 PM PDT 24
Peak memory 210920 kb
Host smart-9af4c2ee-9fc4-43d9-a766-da5834b3df24
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=91332107 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_csr_rw.91332107
Directory /workspace/19.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_rw.963652610
Short name T744
Test name
Test status
Simulation time 16323978051 ps
CPU time 30.85 seconds
Started Mar 17 03:03:50 PM PDT 24
Finished Mar 17 03:04:21 PM PDT 24
Peak memory 211284 kb
Host smart-b3d92159-8290-4a83-a9cc-adb3f58f453f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=963652610 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_csr_rw.963652610
Directory /workspace/19.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_passthru_mem_tl_intg_err.1401564344
Short name T871
Test name
Test status
Simulation time 11552196087 ps
CPU time 91.17 seconds
Started Mar 17 01:46:46 PM PDT 24
Finished Mar 17 01:48:18 PM PDT 24
Peak memory 210912 kb
Host smart-53e375d9-b759-4027-996a-389fcb3115bf
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1401564344 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_p
assthru_mem_tl_intg_err.1401564344
Directory /workspace/19.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_passthru_mem_tl_intg_err.141594743
Short name T97
Test name
Test status
Simulation time 5973189610 ps
CPU time 59.28 seconds
Started Mar 17 03:03:51 PM PDT 24
Finished Mar 17 03:04:50 PM PDT 24
Peak memory 213076 kb
Host smart-1e698f87-9f4a-4af5-a741-af06afd0af72
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=141594743 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_pa
ssthru_mem_tl_intg_err.141594743
Directory /workspace/19.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_same_csr_outstanding.1153569827
Short name T819
Test name
Test status
Simulation time 985161838 ps
CPU time 10.54 seconds
Started Mar 17 01:46:39 PM PDT 24
Finished Mar 17 01:46:52 PM PDT 24
Peak memory 210844 kb
Host smart-c9fd7b69-6879-4447-960f-7d8007a9c08c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1153569827 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_
ctrl_same_csr_outstanding.1153569827
Directory /workspace/19.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_same_csr_outstanding.1772179938
Short name T788
Test name
Test status
Simulation time 4117239993 ps
CPU time 14.5 seconds
Started Mar 17 03:03:50 PM PDT 24
Finished Mar 17 03:04:05 PM PDT 24
Peak memory 211220 kb
Host smart-bdf849d6-e982-442d-a733-9034f20c0237
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1772179938 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_
ctrl_same_csr_outstanding.1772179938
Directory /workspace/19.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_errors.2508490786
Short name T859
Test name
Test status
Simulation time 7164472702 ps
CPU time 32.9 seconds
Started Mar 17 03:03:54 PM PDT 24
Finished Mar 17 03:04:27 PM PDT 24
Peak memory 218256 kb
Host smart-dbca6fec-8be7-4b97-923b-400b038fead8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2508490786 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_tl_errors.2508490786
Directory /workspace/19.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_errors.999308683
Short name T704
Test name
Test status
Simulation time 175141029 ps
CPU time 7.61 seconds
Started Mar 17 01:46:42 PM PDT 24
Finished Mar 17 01:46:52 PM PDT 24
Peak memory 219156 kb
Host smart-7977cf70-4c9e-47bc-9ffc-4f2efc180ff4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=999308683 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_tl_errors.999308683
Directory /workspace/19.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_intg_err.2397098153
Short name T823
Test name
Test status
Simulation time 2709168888 ps
CPU time 73.69 seconds
Started Mar 17 01:46:40 PM PDT 24
Finished Mar 17 01:47:55 PM PDT 24
Peak memory 211588 kb
Host smart-90c90f6a-87b2-4d7e-b472-310c9354cad8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2397098153 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_tl_i
ntg_err.2397098153
Directory /workspace/19.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_intg_err.3507845179
Short name T872
Test name
Test status
Simulation time 4456865364 ps
CPU time 79.51 seconds
Started Mar 17 03:03:51 PM PDT 24
Finished Mar 17 03:05:11 PM PDT 24
Peak memory 213836 kb
Host smart-7da9e25a-bc28-4ab9-b40d-fa0871ac916f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3507845179 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_tl_i
ntg_err.3507845179
Directory /workspace/19.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_aliasing.2896721605
Short name T92
Test name
Test status
Simulation time 30101084036 ps
CPU time 15.56 seconds
Started Mar 17 01:46:17 PM PDT 24
Finished Mar 17 01:46:33 PM PDT 24
Peak memory 210956 kb
Host smart-a7e62b99-17f1-4a48-8c92-a1268e095064
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2896721605 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_alia
sing.2896721605
Directory /workspace/2.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_aliasing.343438463
Short name T885
Test name
Test status
Simulation time 3225581309 ps
CPU time 26.77 seconds
Started Mar 17 03:03:30 PM PDT 24
Finished Mar 17 03:03:58 PM PDT 24
Peak memory 211548 kb
Host smart-53ab0d83-4325-47e3-b230-e79153b0d6f7
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=343438463 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_alias
ing.343438463
Directory /workspace/2.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_bit_bash.3891974375
Short name T703
Test name
Test status
Simulation time 554923210 ps
CPU time 4.6 seconds
Started Mar 17 01:46:33 PM PDT 24
Finished Mar 17 01:46:37 PM PDT 24
Peak memory 210924 kb
Host smart-f88f9dbb-e6cd-444d-98c5-7234d4dddf39
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3891974375 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_bit_
bash.3891974375
Directory /workspace/2.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_bit_bash.515300759
Short name T708
Test name
Test status
Simulation time 717470895 ps
CPU time 8.36 seconds
Started Mar 17 03:03:29 PM PDT 24
Finished Mar 17 03:03:38 PM PDT 24
Peak memory 210944 kb
Host smart-49809d10-4efb-4a20-9e75-fad19908cacd
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=515300759 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_bit_b
ash.515300759
Directory /workspace/2.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_hw_reset.1809070316
Short name T759
Test name
Test status
Simulation time 369708879 ps
CPU time 5.91 seconds
Started Mar 17 01:46:32 PM PDT 24
Finished Mar 17 01:46:38 PM PDT 24
Peak memory 210808 kb
Host smart-91acaf4b-4a6d-4b28-bedf-af9600f9142c
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1809070316 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_hw_r
eset.1809070316
Directory /workspace/2.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_hw_reset.3148273661
Short name T743
Test name
Test status
Simulation time 13517330388 ps
CPU time 31.58 seconds
Started Mar 17 03:03:29 PM PDT 24
Finished Mar 17 03:04:01 PM PDT 24
Peak memory 211688 kb
Host smart-e9cfebfa-b3fc-471f-b2c2-00d2db9ccf4d
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3148273661 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_hw_r
eset.3148273661
Directory /workspace/2.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_mem_rw_with_rand_reset.1792085894
Short name T701
Test name
Test status
Simulation time 1222679684 ps
CPU time 12 seconds
Started Mar 17 01:46:27 PM PDT 24
Finished Mar 17 01:46:39 PM PDT 24
Peak memory 219080 kb
Host smart-52868aaa-092f-48f4-a517-3a9cdd92eb2b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1792085894 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 2.rom_ctrl_csr_mem_rw_with_rand_reset.1792085894
Directory /workspace/2.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_mem_rw_with_rand_reset.4123902100
Short name T742
Test name
Test status
Simulation time 954479758 ps
CPU time 14.33 seconds
Started Mar 17 03:03:28 PM PDT 24
Finished Mar 17 03:03:43 PM PDT 24
Peak memory 215788 kb
Host smart-00b21e83-4d04-4cd4-92a7-e3d88f0a0b7f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4123902100 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 2.rom_ctrl_csr_mem_rw_with_rand_reset.4123902100
Directory /workspace/2.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_rw.1805097211
Short name T750
Test name
Test status
Simulation time 1610316093 ps
CPU time 13.38 seconds
Started Mar 17 01:46:30 PM PDT 24
Finished Mar 17 01:46:43 PM PDT 24
Peak memory 210928 kb
Host smart-2df0c86c-f912-4ff1-ad77-a9ee31fe5eee
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1805097211 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_rw.1805097211
Directory /workspace/2.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_rw.3768779427
Short name T850
Test name
Test status
Simulation time 4788419297 ps
CPU time 15.67 seconds
Started Mar 17 03:03:29 PM PDT 24
Finished Mar 17 03:03:44 PM PDT 24
Peak memory 210988 kb
Host smart-f15feb55-8664-43b6-8875-c7bf26601d0e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3768779427 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_rw.3768779427
Directory /workspace/2.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_partial_access.2183060286
Short name T730
Test name
Test status
Simulation time 338441755 ps
CPU time 7.7 seconds
Started Mar 17 03:03:30 PM PDT 24
Finished Mar 17 03:03:38 PM PDT 24
Peak memory 210820 kb
Host smart-4e9ea9ad-6ef6-4ec2-927d-85f9b9fe6d47
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2183060286 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctr
l_mem_partial_access.2183060286
Directory /workspace/2.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_partial_access.2935224628
Short name T796
Test name
Test status
Simulation time 85603285 ps
CPU time 4.14 seconds
Started Mar 17 01:46:39 PM PDT 24
Finished Mar 17 01:46:46 PM PDT 24
Peak memory 210780 kb
Host smart-6a838780-ff97-414d-a5ef-e16bb727552c
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2935224628 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctr
l_mem_partial_access.2935224628
Directory /workspace/2.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_walk.189393696
Short name T699
Test name
Test status
Simulation time 643523935 ps
CPU time 7.53 seconds
Started Mar 17 01:46:27 PM PDT 24
Finished Mar 17 01:46:35 PM PDT 24
Peak memory 210784 kb
Host smart-293e1e0a-b926-4c7a-bb28-573b420e7c66
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=189393696 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_mem_walk.
189393696
Directory /workspace/2.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_walk.884224578
Short name T702
Test name
Test status
Simulation time 170994248 ps
CPU time 8.23 seconds
Started Mar 17 03:03:29 PM PDT 24
Finished Mar 17 03:03:38 PM PDT 24
Peak memory 210864 kb
Host smart-ad0bc833-16f4-4c16-be79-1b88df532ddd
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=884224578 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_mem_walk.
884224578
Directory /workspace/2.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_passthru_mem_tl_intg_err.251339904
Short name T70
Test name
Test status
Simulation time 12506275856 ps
CPU time 74.81 seconds
Started Mar 17 03:03:29 PM PDT 24
Finished Mar 17 03:04:44 PM PDT 24
Peak memory 212976 kb
Host smart-50fd6fd1-c651-4957-a30e-daeef3a1e069
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=251339904 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_pas
sthru_mem_tl_intg_err.251339904
Directory /workspace/2.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_same_csr_outstanding.2743693738
Short name T825
Test name
Test status
Simulation time 2649303233 ps
CPU time 11.88 seconds
Started Mar 17 01:46:27 PM PDT 24
Finished Mar 17 01:46:39 PM PDT 24
Peak memory 210964 kb
Host smart-6c19df0e-e9a0-46ba-821d-713d0c96f3ae
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2743693738 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_c
trl_same_csr_outstanding.2743693738
Directory /workspace/2.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_same_csr_outstanding.2782523141
Short name T103
Test name
Test status
Simulation time 15583750517 ps
CPU time 30.11 seconds
Started Mar 17 03:03:28 PM PDT 24
Finished Mar 17 03:03:59 PM PDT 24
Peak memory 212096 kb
Host smart-831753d9-66f7-4e16-a6ec-b22df9e26466
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2782523141 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_c
trl_same_csr_outstanding.2782523141
Directory /workspace/2.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_errors.1433767236
Short name T739
Test name
Test status
Simulation time 10787186558 ps
CPU time 20.48 seconds
Started Mar 17 03:03:29 PM PDT 24
Finished Mar 17 03:03:50 PM PDT 24
Peak memory 218612 kb
Host smart-1ee980d7-5cc1-4d48-a100-4d101cfaa863
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1433767236 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_tl_errors.1433767236
Directory /workspace/2.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_errors.4176034932
Short name T804
Test name
Test status
Simulation time 4043499143 ps
CPU time 18.62 seconds
Started Mar 17 01:46:29 PM PDT 24
Finished Mar 17 01:46:48 PM PDT 24
Peak memory 219240 kb
Host smart-13922d5c-b277-483c-879a-143da51ed6b4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4176034932 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_tl_errors.4176034932
Directory /workspace/2.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_intg_err.2344670470
Short name T124
Test name
Test status
Simulation time 1551914537 ps
CPU time 88.3 seconds
Started Mar 17 03:03:32 PM PDT 24
Finished Mar 17 03:05:01 PM PDT 24
Peak memory 213032 kb
Host smart-2a60e4e1-af60-4475-bc5f-7efd7ac73afb
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2344670470 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_tl_in
tg_err.2344670470
Directory /workspace/2.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_aliasing.1336384152
Short name T697
Test name
Test status
Simulation time 3588036172 ps
CPU time 28.21 seconds
Started Mar 17 03:03:41 PM PDT 24
Finished Mar 17 03:04:09 PM PDT 24
Peak memory 211480 kb
Host smart-7a0d5e5a-b2da-446a-ac3c-fdc68ff4d5a4
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1336384152 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_alia
sing.1336384152
Directory /workspace/3.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_aliasing.3221700984
Short name T93
Test name
Test status
Simulation time 2311937266 ps
CPU time 15.16 seconds
Started Mar 17 01:46:20 PM PDT 24
Finished Mar 17 01:46:36 PM PDT 24
Peak memory 210980 kb
Host smart-4dc7885b-c840-4d5d-a047-d1478222facb
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3221700984 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_alia
sing.3221700984
Directory /workspace/3.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_bit_bash.2090414585
Short name T779
Test name
Test status
Simulation time 2895010120 ps
CPU time 24.85 seconds
Started Mar 17 03:03:35 PM PDT 24
Finished Mar 17 03:04:00 PM PDT 24
Peak memory 210980 kb
Host smart-ac5c71a0-0305-4f68-a5e8-66cbb4ac3d22
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2090414585 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_bit_
bash.2090414585
Directory /workspace/3.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_bit_bash.2529435185
Short name T821
Test name
Test status
Simulation time 585299710 ps
CPU time 8.12 seconds
Started Mar 17 01:46:35 PM PDT 24
Finished Mar 17 01:46:44 PM PDT 24
Peak memory 210908 kb
Host smart-e0469364-1960-4320-979e-e6af8f123275
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2529435185 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_bit_
bash.2529435185
Directory /workspace/3.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_hw_reset.3049942000
Short name T890
Test name
Test status
Simulation time 1014234650 ps
CPU time 10.43 seconds
Started Mar 17 01:46:19 PM PDT 24
Finished Mar 17 01:46:30 PM PDT 24
Peak memory 210916 kb
Host smart-84bc9a2c-b92a-4899-acbe-8b6423cddfd5
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3049942000 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_hw_r
eset.3049942000
Directory /workspace/3.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_hw_reset.578141283
Short name T767
Test name
Test status
Simulation time 3028451403 ps
CPU time 21.72 seconds
Started Mar 17 03:03:37 PM PDT 24
Finished Mar 17 03:03:59 PM PDT 24
Peak memory 211124 kb
Host smart-a4652f95-29d4-4985-a207-0dcb6184f6a7
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=578141283 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_hw_re
set.578141283
Directory /workspace/3.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_mem_rw_with_rand_reset.258482631
Short name T883
Test name
Test status
Simulation time 853065092 ps
CPU time 5.07 seconds
Started Mar 17 01:46:30 PM PDT 24
Finished Mar 17 01:46:36 PM PDT 24
Peak memory 211236 kb
Host smart-73506080-b92b-4674-baa0-23e1d89baa7c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=258482631 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 3.rom_ctrl_csr_mem_rw_with_rand_reset.258482631
Directory /workspace/3.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_mem_rw_with_rand_reset.3718370813
Short name T694
Test name
Test status
Simulation time 1540942993 ps
CPU time 18.3 seconds
Started Mar 17 03:03:39 PM PDT 24
Finished Mar 17 03:03:57 PM PDT 24
Peak memory 216368 kb
Host smart-705cd55c-0bc9-4cae-8441-2b86366f67fc
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3718370813 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 3.rom_ctrl_csr_mem_rw_with_rand_reset.3718370813
Directory /workspace/3.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_rw.2054813018
Short name T89
Test name
Test status
Simulation time 21912329501 ps
CPU time 20.92 seconds
Started Mar 17 03:03:34 PM PDT 24
Finished Mar 17 03:03:56 PM PDT 24
Peak memory 211992 kb
Host smart-326e1d39-aeca-4404-a4e7-6eff6846be1f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2054813018 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_rw.2054813018
Directory /workspace/3.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_rw.3692533954
Short name T713
Test name
Test status
Simulation time 1153128459 ps
CPU time 11.24 seconds
Started Mar 17 01:46:21 PM PDT 24
Finished Mar 17 01:46:33 PM PDT 24
Peak memory 210828 kb
Host smart-afebb953-3014-4bdf-ae13-584d482db6a0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3692533954 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_rw.3692533954
Directory /workspace/3.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_partial_access.3094005006
Short name T756
Test name
Test status
Simulation time 2747548374 ps
CPU time 24.37 seconds
Started Mar 17 03:03:37 PM PDT 24
Finished Mar 17 03:04:01 PM PDT 24
Peak memory 210936 kb
Host smart-ee1ba661-14be-4a29-993e-3efdab7aaa81
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3094005006 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctr
l_mem_partial_access.3094005006
Directory /workspace/3.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_partial_access.3523353911
Short name T740
Test name
Test status
Simulation time 136571460 ps
CPU time 4.14 seconds
Started Mar 17 01:46:28 PM PDT 24
Finished Mar 17 01:46:33 PM PDT 24
Peak memory 210760 kb
Host smart-8c777213-16ab-45a2-9d86-b1ff47aaca1a
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3523353911 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctr
l_mem_partial_access.3523353911
Directory /workspace/3.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_walk.2787362718
Short name T731
Test name
Test status
Simulation time 2140859762 ps
CPU time 21.37 seconds
Started Mar 17 03:03:36 PM PDT 24
Finished Mar 17 03:03:57 PM PDT 24
Peak memory 210868 kb
Host smart-d8abd4e7-2251-4add-ab36-7bc2b3c0eff8
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2787362718 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_mem_walk
.2787362718
Directory /workspace/3.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_walk.865019294
Short name T775
Test name
Test status
Simulation time 991691328 ps
CPU time 10.02 seconds
Started Mar 17 01:46:29 PM PDT 24
Finished Mar 17 01:46:39 PM PDT 24
Peak memory 210772 kb
Host smart-a76110a2-6628-4b54-8c25-186e1a794983
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=865019294 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_mem_walk.
865019294
Directory /workspace/3.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_passthru_mem_tl_intg_err.1227229255
Short name T87
Test name
Test status
Simulation time 1396711629 ps
CPU time 27.36 seconds
Started Mar 17 01:46:20 PM PDT 24
Finished Mar 17 01:46:48 PM PDT 24
Peak memory 210912 kb
Host smart-d40aafa9-5769-408f-ae65-dd0ba08fba2d
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1227229255 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_pa
ssthru_mem_tl_intg_err.1227229255
Directory /workspace/3.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_passthru_mem_tl_intg_err.3022656132
Short name T98
Test name
Test status
Simulation time 83242763151 ps
CPU time 187.37 seconds
Started Mar 17 03:03:31 PM PDT 24
Finished Mar 17 03:06:39 PM PDT 24
Peak memory 215068 kb
Host smart-481f1c23-da64-40b9-b4d7-4644d8175926
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3022656132 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_pa
ssthru_mem_tl_intg_err.3022656132
Directory /workspace/3.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_same_csr_outstanding.1641767694
Short name T869
Test name
Test status
Simulation time 167515969 ps
CPU time 8.38 seconds
Started Mar 17 03:03:34 PM PDT 24
Finished Mar 17 03:03:43 PM PDT 24
Peak memory 210928 kb
Host smart-9f47ee0b-8040-465d-8b16-a8c7b67ad930
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1641767694 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_c
trl_same_csr_outstanding.1641767694
Directory /workspace/3.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_same_csr_outstanding.4186002120
Short name T807
Test name
Test status
Simulation time 2076252430 ps
CPU time 16.99 seconds
Started Mar 17 01:46:26 PM PDT 24
Finished Mar 17 01:46:43 PM PDT 24
Peak memory 210904 kb
Host smart-7b3cc7d9-7ad1-4a04-a7a7-e77a7c99dca3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4186002120 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_c
trl_same_csr_outstanding.4186002120
Directory /workspace/3.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_errors.3528433805
Short name T772
Test name
Test status
Simulation time 6838243246 ps
CPU time 13.16 seconds
Started Mar 17 01:46:19 PM PDT 24
Finished Mar 17 01:46:32 PM PDT 24
Peak memory 219192 kb
Host smart-3fdd8f23-2002-40e8-8dc0-9e777ddd6ba0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3528433805 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_tl_errors.3528433805
Directory /workspace/3.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_errors.3651538445
Short name T895
Test name
Test status
Simulation time 46563390684 ps
CPU time 29.1 seconds
Started Mar 17 03:03:31 PM PDT 24
Finished Mar 17 03:04:01 PM PDT 24
Peak memory 217936 kb
Host smart-1e49c542-c5d7-43ed-9ab7-7ae3efb9e034
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3651538445 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_tl_errors.3651538445
Directory /workspace/3.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_intg_err.1875171987
Short name T792
Test name
Test status
Simulation time 1490838345 ps
CPU time 43.52 seconds
Started Mar 17 01:46:21 PM PDT 24
Finished Mar 17 01:47:05 PM PDT 24
Peak memory 211716 kb
Host smart-1621bb61-22fa-4649-a564-6c573870abe8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1875171987 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_tl_in
tg_err.1875171987
Directory /workspace/3.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_intg_err.2793405513
Short name T783
Test name
Test status
Simulation time 35394990712 ps
CPU time 105.97 seconds
Started Mar 17 03:03:36 PM PDT 24
Finished Mar 17 03:05:22 PM PDT 24
Peak memory 213104 kb
Host smart-c0290b98-362e-4605-a6e8-f36b42dcd907
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2793405513 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_tl_in
tg_err.2793405513
Directory /workspace/3.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_aliasing.1767239726
Short name T861
Test name
Test status
Simulation time 10411309392 ps
CPU time 14.56 seconds
Started Mar 17 01:46:36 PM PDT 24
Finished Mar 17 01:46:51 PM PDT 24
Peak memory 211000 kb
Host smart-50babbc8-6390-45e4-aedf-99ed19be71ec
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1767239726 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_alia
sing.1767239726
Directory /workspace/4.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_aliasing.3067863103
Short name T725
Test name
Test status
Simulation time 4221422092 ps
CPU time 32.27 seconds
Started Mar 17 03:03:36 PM PDT 24
Finished Mar 17 03:04:08 PM PDT 24
Peak memory 211340 kb
Host smart-08adfbb5-a86b-47d4-89b6-6b549dde54f6
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3067863103 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_alia
sing.3067863103
Directory /workspace/4.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_bit_bash.1330050488
Short name T870
Test name
Test status
Simulation time 589181394 ps
CPU time 6.49 seconds
Started Mar 17 01:46:39 PM PDT 24
Finished Mar 17 01:46:47 PM PDT 24
Peak memory 210584 kb
Host smart-aa98fd03-20c3-4761-9704-3083d36e016f
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1330050488 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_bit_
bash.1330050488
Directory /workspace/4.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_bit_bash.741914318
Short name T838
Test name
Test status
Simulation time 167601798 ps
CPU time 8.42 seconds
Started Mar 17 03:03:39 PM PDT 24
Finished Mar 17 03:03:47 PM PDT 24
Peak memory 210952 kb
Host smart-b387b872-6855-4ada-933d-01d6cafe9c6b
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=741914318 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_bit_b
ash.741914318
Directory /workspace/4.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_hw_reset.3843506222
Short name T761
Test name
Test status
Simulation time 1993027740 ps
CPU time 15.69 seconds
Started Mar 17 01:46:44 PM PDT 24
Finished Mar 17 01:47:02 PM PDT 24
Peak memory 210928 kb
Host smart-b061ff7b-3bc3-4cf4-b91b-775a48c20871
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3843506222 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_hw_r
eset.3843506222
Directory /workspace/4.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_hw_reset.3954970487
Short name T76
Test name
Test status
Simulation time 60692569687 ps
CPU time 40.82 seconds
Started Mar 17 03:03:37 PM PDT 24
Finished Mar 17 03:04:18 PM PDT 24
Peak memory 211940 kb
Host smart-daf764ff-7cf8-4fb3-875e-401294ca3ada
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3954970487 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_hw_r
eset.3954970487
Directory /workspace/4.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_mem_rw_with_rand_reset.2416006096
Short name T863
Test name
Test status
Simulation time 1084146412 ps
CPU time 16.71 seconds
Started Mar 17 03:03:38 PM PDT 24
Finished Mar 17 03:03:55 PM PDT 24
Peak memory 217404 kb
Host smart-69c4e0c6-7e0b-4bb4-adb0-461f6f578d4c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2416006096 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 4.rom_ctrl_csr_mem_rw_with_rand_reset.2416006096
Directory /workspace/4.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_mem_rw_with_rand_reset.4030918074
Short name T56
Test name
Test status
Simulation time 2989862014 ps
CPU time 9.04 seconds
Started Mar 17 01:46:47 PM PDT 24
Finished Mar 17 01:46:56 PM PDT 24
Peak memory 219116 kb
Host smart-3c9ca99b-cd4d-41de-9bb1-8041364d7892
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4030918074 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 4.rom_ctrl_csr_mem_rw_with_rand_reset.4030918074
Directory /workspace/4.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_rw.3417057284
Short name T94
Test name
Test status
Simulation time 1674557202 ps
CPU time 13.45 seconds
Started Mar 17 03:03:37 PM PDT 24
Finished Mar 17 03:03:50 PM PDT 24
Peak memory 211168 kb
Host smart-e127a3c6-b9e7-4832-a3e5-4c8cab16180f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3417057284 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_rw.3417057284
Directory /workspace/4.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_rw.3628052986
Short name T738
Test name
Test status
Simulation time 1706382395 ps
CPU time 14.6 seconds
Started Mar 17 01:46:39 PM PDT 24
Finished Mar 17 01:46:55 PM PDT 24
Peak memory 210880 kb
Host smart-7bbe5499-ccfc-48b9-9a40-2755a049d0c3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3628052986 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_rw.3628052986
Directory /workspace/4.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_partial_access.3608036920
Short name T753
Test name
Test status
Simulation time 660564228 ps
CPU time 7.97 seconds
Started Mar 17 03:03:40 PM PDT 24
Finished Mar 17 03:03:49 PM PDT 24
Peak memory 210796 kb
Host smart-91b6f20f-4750-42f2-8a4c-eb8463979919
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3608036920 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctr
l_mem_partial_access.3608036920
Directory /workspace/4.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_partial_access.566793679
Short name T816
Test name
Test status
Simulation time 5179175345 ps
CPU time 14.4 seconds
Started Mar 17 01:46:29 PM PDT 24
Finished Mar 17 01:46:44 PM PDT 24
Peak memory 210852 kb
Host smart-447695a7-c1c2-4974-ae4e-4d3528c6264b
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=566793679 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl
_mem_partial_access.566793679
Directory /workspace/4.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_walk.2555958024
Short name T900
Test name
Test status
Simulation time 836062536 ps
CPU time 6.85 seconds
Started Mar 17 01:46:29 PM PDT 24
Finished Mar 17 01:46:36 PM PDT 24
Peak memory 210776 kb
Host smart-ee26dd02-2089-4aed-8ae7-119ab58f63ec
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2555958024 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_mem_walk
.2555958024
Directory /workspace/4.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_walk.2682797787
Short name T911
Test name
Test status
Simulation time 4967576161 ps
CPU time 22.24 seconds
Started Mar 17 03:03:35 PM PDT 24
Finished Mar 17 03:03:58 PM PDT 24
Peak memory 210868 kb
Host smart-9dcbe70f-5740-450e-9b82-e0f90d501808
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2682797787 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_mem_walk
.2682797787
Directory /workspace/4.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_passthru_mem_tl_intg_err.3122997504
Short name T903
Test name
Test status
Simulation time 1349988154 ps
CPU time 45.67 seconds
Started Mar 17 03:03:35 PM PDT 24
Finished Mar 17 03:04:21 PM PDT 24
Peak memory 213032 kb
Host smart-b7fe9729-88cb-495e-bb3e-35d18fc1e8a5
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3122997504 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_pa
ssthru_mem_tl_intg_err.3122997504
Directory /workspace/4.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_passthru_mem_tl_intg_err.550059597
Short name T843
Test name
Test status
Simulation time 5908370573 ps
CPU time 54.06 seconds
Started Mar 17 01:46:37 PM PDT 24
Finished Mar 17 01:47:31 PM PDT 24
Peak memory 210952 kb
Host smart-702b0587-2274-4aa6-83e8-5dfbd37862c4
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=550059597 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_pas
sthru_mem_tl_intg_err.550059597
Directory /workspace/4.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_same_csr_outstanding.159228480
Short name T799
Test name
Test status
Simulation time 196293025 ps
CPU time 12.34 seconds
Started Mar 17 03:03:36 PM PDT 24
Finished Mar 17 03:03:49 PM PDT 24
Peak memory 212096 kb
Host smart-89c4008c-26cb-47f5-a684-ef1f0fcae537
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=159228480 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ct
rl_same_csr_outstanding.159228480
Directory /workspace/4.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_same_csr_outstanding.1625034167
Short name T916
Test name
Test status
Simulation time 592336567 ps
CPU time 4.12 seconds
Started Mar 17 01:46:47 PM PDT 24
Finished Mar 17 01:46:52 PM PDT 24
Peak memory 210844 kb
Host smart-024d50d4-f3bf-4754-9012-ae2fb9b4cf57
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1625034167 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_c
trl_same_csr_outstanding.1625034167
Directory /workspace/4.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_errors.2028533123
Short name T716
Test name
Test status
Simulation time 171036082 ps
CPU time 11.58 seconds
Started Mar 17 03:03:40 PM PDT 24
Finished Mar 17 03:03:52 PM PDT 24
Peak memory 216796 kb
Host smart-1d6fa1fa-3931-428b-8f88-84c2846fd3e7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2028533123 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_tl_errors.2028533123
Directory /workspace/4.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_errors.3311149162
Short name T776
Test name
Test status
Simulation time 208843021 ps
CPU time 8.03 seconds
Started Mar 17 01:46:20 PM PDT 24
Finished Mar 17 01:46:29 PM PDT 24
Peak memory 219068 kb
Host smart-f3cc9709-1d93-4d82-9116-aec50a9afbfb
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3311149162 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_tl_errors.3311149162
Directory /workspace/4.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_intg_err.2172910030
Short name T125
Test name
Test status
Simulation time 730196479 ps
CPU time 155.23 seconds
Started Mar 17 03:03:33 PM PDT 24
Finished Mar 17 03:06:08 PM PDT 24
Peak memory 213560 kb
Host smart-03fb7dab-5f67-42c7-a8a0-4f028327e101
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2172910030 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_tl_in
tg_err.2172910030
Directory /workspace/4.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_intg_err.3283114625
Short name T128
Test name
Test status
Simulation time 2037982748 ps
CPU time 68.87 seconds
Started Mar 17 01:46:19 PM PDT 24
Finished Mar 17 01:47:28 PM PDT 24
Peak memory 211840 kb
Host smart-82ceda96-5cdb-48f6-afaf-927d4cb15048
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3283114625 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_tl_in
tg_err.3283114625
Directory /workspace/4.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_mem_rw_with_rand_reset.1159129953
Short name T760
Test name
Test status
Simulation time 499795863 ps
CPU time 11.93 seconds
Started Mar 17 03:03:42 PM PDT 24
Finished Mar 17 03:03:54 PM PDT 24
Peak memory 214516 kb
Host smart-d01a678e-e786-4dba-aa6a-b08837e75c22
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1159129953 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 5.rom_ctrl_csr_mem_rw_with_rand_reset.1159129953
Directory /workspace/5.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_mem_rw_with_rand_reset.296957029
Short name T686
Test name
Test status
Simulation time 101758441 ps
CPU time 4.81 seconds
Started Mar 17 01:46:34 PM PDT 24
Finished Mar 17 01:46:39 PM PDT 24
Peak memory 219084 kb
Host smart-51555fb7-d372-473f-b0ef-d136c9115d90
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=296957029 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 5.rom_ctrl_csr_mem_rw_with_rand_reset.296957029
Directory /workspace/5.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_rw.439176315
Short name T800
Test name
Test status
Simulation time 4221649013 ps
CPU time 10.72 seconds
Started Mar 17 01:46:39 PM PDT 24
Finished Mar 17 01:46:52 PM PDT 24
Peak memory 210972 kb
Host smart-7bb4bb09-8f33-4f37-9080-fbdcbcbd1622
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=439176315 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_csr_rw.439176315
Directory /workspace/5.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_rw.517811420
Short name T867
Test name
Test status
Simulation time 7825177765 ps
CPU time 18.34 seconds
Started Mar 17 03:03:39 PM PDT 24
Finished Mar 17 03:03:57 PM PDT 24
Peak memory 211480 kb
Host smart-3f37c7af-8aaa-4887-9408-2ae4c20f3f51
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=517811420 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_csr_rw.517811420
Directory /workspace/5.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_passthru_mem_tl_intg_err.2058178771
Short name T722
Test name
Test status
Simulation time 27659347545 ps
CPU time 140.09 seconds
Started Mar 17 03:03:36 PM PDT 24
Finished Mar 17 03:05:56 PM PDT 24
Peak memory 215072 kb
Host smart-c14c1274-3953-49b8-b87b-8822badd9a1c
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2058178771 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_pa
ssthru_mem_tl_intg_err.2058178771
Directory /workspace/5.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_passthru_mem_tl_intg_err.4238042482
Short name T723
Test name
Test status
Simulation time 8555488005 ps
CPU time 44.05 seconds
Started Mar 17 01:46:22 PM PDT 24
Finished Mar 17 01:47:12 PM PDT 24
Peak memory 210980 kb
Host smart-b54bfd71-e84f-4380-b89a-f15a7f6f615c
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4238042482 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_pa
ssthru_mem_tl_intg_err.4238042482
Directory /workspace/5.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_same_csr_outstanding.1287813981
Short name T770
Test name
Test status
Simulation time 201004914 ps
CPU time 8.29 seconds
Started Mar 17 03:03:39 PM PDT 24
Finished Mar 17 03:03:47 PM PDT 24
Peak memory 210976 kb
Host smart-962c1d80-548c-4736-b3a2-71334582bc89
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1287813981 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_c
trl_same_csr_outstanding.1287813981
Directory /workspace/5.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_same_csr_outstanding.462132336
Short name T741
Test name
Test status
Simulation time 6572876419 ps
CPU time 13.2 seconds
Started Mar 17 01:46:39 PM PDT 24
Finished Mar 17 01:46:54 PM PDT 24
Peak memory 210988 kb
Host smart-d54ce085-06ab-4353-91fd-f967ae817fe4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=462132336 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ct
rl_same_csr_outstanding.462132336
Directory /workspace/5.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_errors.1403137524
Short name T785
Test name
Test status
Simulation time 249508597 ps
CPU time 7.83 seconds
Started Mar 17 01:46:34 PM PDT 24
Finished Mar 17 01:46:42 PM PDT 24
Peak memory 219180 kb
Host smart-0b53e166-9354-4cf0-989e-ba31edba285d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1403137524 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_tl_errors.1403137524
Directory /workspace/5.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_errors.2240187352
Short name T815
Test name
Test status
Simulation time 6599456714 ps
CPU time 13.92 seconds
Started Mar 17 03:03:40 PM PDT 24
Finished Mar 17 03:03:55 PM PDT 24
Peak memory 217432 kb
Host smart-522de614-9d16-49be-a392-d01f54f6ac1f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2240187352 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_tl_errors.2240187352
Directory /workspace/5.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_intg_err.2873706860
Short name T54
Test name
Test status
Simulation time 1797195103 ps
CPU time 45.62 seconds
Started Mar 17 01:46:34 PM PDT 24
Finished Mar 17 01:47:20 PM PDT 24
Peak memory 210908 kb
Host smart-51cbc7ba-a181-42ba-bd65-d2e558584cf7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2873706860 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_tl_in
tg_err.2873706860
Directory /workspace/5.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_intg_err.3367239095
Short name T758
Test name
Test status
Simulation time 2048349621 ps
CPU time 93.06 seconds
Started Mar 17 03:03:35 PM PDT 24
Finished Mar 17 03:05:08 PM PDT 24
Peak memory 213168 kb
Host smart-bc64dee5-4fde-4a4a-8b1d-c4c82f0776e7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3367239095 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_tl_in
tg_err.3367239095
Directory /workspace/5.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_mem_rw_with_rand_reset.2203020293
Short name T897
Test name
Test status
Simulation time 2293415055 ps
CPU time 7.4 seconds
Started Mar 17 01:46:38 PM PDT 24
Finished Mar 17 01:46:46 PM PDT 24
Peak memory 211848 kb
Host smart-5ef966cb-b82d-4f0b-be1e-00115d0da8b7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2203020293 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 6.rom_ctrl_csr_mem_rw_with_rand_reset.2203020293
Directory /workspace/6.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_mem_rw_with_rand_reset.504528445
Short name T727
Test name
Test status
Simulation time 8983528961 ps
CPU time 21.35 seconds
Started Mar 17 03:03:38 PM PDT 24
Finished Mar 17 03:04:00 PM PDT 24
Peak memory 216856 kb
Host smart-aa57ac60-dd28-4954-a205-a5671ccd10f1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=504528445 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 6.rom_ctrl_csr_mem_rw_with_rand_reset.504528445
Directory /workspace/6.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_rw.1206934947
Short name T101
Test name
Test status
Simulation time 1952587921 ps
CPU time 10.18 seconds
Started Mar 17 01:46:37 PM PDT 24
Finished Mar 17 01:46:48 PM PDT 24
Peak memory 210916 kb
Host smart-63ec15b4-33fe-40ce-8b3b-abc205bde49d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1206934947 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_csr_rw.1206934947
Directory /workspace/6.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_rw.3975477352
Short name T855
Test name
Test status
Simulation time 338955996 ps
CPU time 7.93 seconds
Started Mar 17 03:03:37 PM PDT 24
Finished Mar 17 03:03:45 PM PDT 24
Peak memory 210928 kb
Host smart-d17c3687-1254-4575-b59b-eb1cfb039966
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3975477352 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_csr_rw.3975477352
Directory /workspace/6.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_passthru_mem_tl_intg_err.1991820061
Short name T710
Test name
Test status
Simulation time 27842836129 ps
CPU time 49.6 seconds
Started Mar 17 03:03:46 PM PDT 24
Finished Mar 17 03:04:36 PM PDT 24
Peak memory 214036 kb
Host smart-a7d89a98-102b-444d-ab1d-c86a167f8968
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1991820061 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_pa
ssthru_mem_tl_intg_err.1991820061
Directory /workspace/6.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_passthru_mem_tl_intg_err.2345597660
Short name T95
Test name
Test status
Simulation time 576337815 ps
CPU time 28.1 seconds
Started Mar 17 01:46:32 PM PDT 24
Finished Mar 17 01:47:00 PM PDT 24
Peak memory 210936 kb
Host smart-cbc99d75-8f02-4407-88f5-552314058f50
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2345597660 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_pa
ssthru_mem_tl_intg_err.2345597660
Directory /workspace/6.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_same_csr_outstanding.2448028377
Short name T877
Test name
Test status
Simulation time 20695633060 ps
CPU time 31.93 seconds
Started Mar 17 03:03:43 PM PDT 24
Finished Mar 17 03:04:15 PM PDT 24
Peak memory 212344 kb
Host smart-bd0e729a-94f0-411f-8d71-45e1b90955a7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2448028377 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_c
trl_same_csr_outstanding.2448028377
Directory /workspace/6.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_same_csr_outstanding.913866995
Short name T106
Test name
Test status
Simulation time 1075906666 ps
CPU time 11.99 seconds
Started Mar 17 01:46:35 PM PDT 24
Finished Mar 17 01:46:48 PM PDT 24
Peak memory 210852 kb
Host smart-60a7cd07-ee0d-4144-b1fb-14ac33d3ec1b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=913866995 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ct
rl_same_csr_outstanding.913866995
Directory /workspace/6.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_errors.2284006067
Short name T809
Test name
Test status
Simulation time 1324126127 ps
CPU time 15.75 seconds
Started Mar 17 01:46:35 PM PDT 24
Finished Mar 17 01:46:51 PM PDT 24
Peak memory 219156 kb
Host smart-c1837d67-367c-4377-b00c-978cc81b8c5f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2284006067 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_tl_errors.2284006067
Directory /workspace/6.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_errors.4150068350
Short name T912
Test name
Test status
Simulation time 4818616698 ps
CPU time 31.53 seconds
Started Mar 17 03:03:39 PM PDT 24
Finished Mar 17 03:04:11 PM PDT 24
Peak memory 218416 kb
Host smart-796bf8c1-afef-4bb4-851c-1a529c8bf90a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4150068350 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_tl_errors.4150068350
Directory /workspace/6.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_intg_err.2670205429
Short name T839
Test name
Test status
Simulation time 8571290541 ps
CPU time 162.65 seconds
Started Mar 17 03:03:40 PM PDT 24
Finished Mar 17 03:06:23 PM PDT 24
Peak memory 213956 kb
Host smart-860bf9d5-3d43-4e53-aa4c-edc2de9c7802
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2670205429 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_tl_in
tg_err.2670205429
Directory /workspace/6.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_intg_err.635580028
Short name T116
Test name
Test status
Simulation time 4212879812 ps
CPU time 70.87 seconds
Started Mar 17 01:46:29 PM PDT 24
Finished Mar 17 01:47:40 PM PDT 24
Peak memory 211928 kb
Host smart-67e5ddee-f510-43cc-bb47-9e4f0dc6443f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=635580028 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_tl_int
g_err.635580028
Directory /workspace/6.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_mem_rw_with_rand_reset.1626075762
Short name T842
Test name
Test status
Simulation time 196704546 ps
CPU time 9.07 seconds
Started Mar 17 03:03:40 PM PDT 24
Finished Mar 17 03:03:49 PM PDT 24
Peak memory 216500 kb
Host smart-8668a19f-845d-4717-be62-4ab44f9a0339
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1626075762 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 7.rom_ctrl_csr_mem_rw_with_rand_reset.1626075762
Directory /workspace/7.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_mem_rw_with_rand_reset.4249553696
Short name T908
Test name
Test status
Simulation time 771794666 ps
CPU time 9.32 seconds
Started Mar 17 01:46:35 PM PDT 24
Finished Mar 17 01:46:44 PM PDT 24
Peak memory 214188 kb
Host smart-e0821619-21db-40ce-a813-07ce322b77c7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4249553696 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 7.rom_ctrl_csr_mem_rw_with_rand_reset.4249553696
Directory /workspace/7.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_rw.1022523324
Short name T831
Test name
Test status
Simulation time 3020131963 ps
CPU time 13.39 seconds
Started Mar 17 01:46:33 PM PDT 24
Finished Mar 17 01:46:47 PM PDT 24
Peak memory 210976 kb
Host smart-a06464de-5fdc-4cd6-8d3e-3bfd86f30dc5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1022523324 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_csr_rw.1022523324
Directory /workspace/7.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_rw.1974190397
Short name T889
Test name
Test status
Simulation time 13788950725 ps
CPU time 29.2 seconds
Started Mar 17 03:03:41 PM PDT 24
Finished Mar 17 03:04:11 PM PDT 24
Peak memory 212004 kb
Host smart-4efda410-e06f-4765-97a1-71400c9c347d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1974190397 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_csr_rw.1974190397
Directory /workspace/7.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_passthru_mem_tl_intg_err.3040676562
Short name T906
Test name
Test status
Simulation time 51271129695 ps
CPU time 195.87 seconds
Started Mar 17 03:03:39 PM PDT 24
Finished Mar 17 03:06:55 PM PDT 24
Peak memory 214784 kb
Host smart-9939bd5b-b7cb-4e62-9e1e-c38577c4a9ee
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3040676562 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_pa
ssthru_mem_tl_intg_err.3040676562
Directory /workspace/7.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_passthru_mem_tl_intg_err.3945501248
Short name T75
Test name
Test status
Simulation time 33891675839 ps
CPU time 67.59 seconds
Started Mar 17 01:46:40 PM PDT 24
Finished Mar 17 01:47:49 PM PDT 24
Peak memory 211036 kb
Host smart-fa6960cf-98e4-4779-92b0-5d0e3a74a600
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3945501248 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_pa
ssthru_mem_tl_intg_err.3945501248
Directory /workspace/7.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_same_csr_outstanding.1199609549
Short name T719
Test name
Test status
Simulation time 22427653060 ps
CPU time 35.73 seconds
Started Mar 17 03:03:43 PM PDT 24
Finished Mar 17 03:04:19 PM PDT 24
Peak memory 212288 kb
Host smart-2fb70303-d504-4fb0-b9b5-8471a1a899b3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1199609549 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_c
trl_same_csr_outstanding.1199609549
Directory /workspace/7.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_same_csr_outstanding.353940142
Short name T865
Test name
Test status
Simulation time 744892301 ps
CPU time 6.11 seconds
Started Mar 17 01:46:38 PM PDT 24
Finished Mar 17 01:46:44 PM PDT 24
Peak memory 210832 kb
Host smart-8af232d0-34a4-4656-80d6-7bc856de5809
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=353940142 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ct
rl_same_csr_outstanding.353940142
Directory /workspace/7.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_errors.1288208012
Short name T787
Test name
Test status
Simulation time 4941254075 ps
CPU time 21.22 seconds
Started Mar 17 03:03:39 PM PDT 24
Finished Mar 17 03:04:00 PM PDT 24
Peak memory 218452 kb
Host smart-a5f853cf-e4a2-46ad-824e-c00fbde02211
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1288208012 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_tl_errors.1288208012
Directory /workspace/7.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_errors.1754609830
Short name T887
Test name
Test status
Simulation time 4015240045 ps
CPU time 17.08 seconds
Started Mar 17 01:46:46 PM PDT 24
Finished Mar 17 01:47:04 PM PDT 24
Peak memory 219216 kb
Host smart-04f9517d-2c82-486d-a1b2-3274a7a046f5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1754609830 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_tl_errors.1754609830
Directory /workspace/7.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_intg_err.2284332475
Short name T127
Test name
Test status
Simulation time 3956845477 ps
CPU time 103.54 seconds
Started Mar 17 03:03:42 PM PDT 24
Finished Mar 17 03:05:25 PM PDT 24
Peak memory 214016 kb
Host smart-c7e420d4-448e-445f-a134-09c65fff1f7e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2284332475 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_tl_in
tg_err.2284332475
Directory /workspace/7.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_intg_err.3214194719
Short name T745
Test name
Test status
Simulation time 7473553057 ps
CPU time 79.22 seconds
Started Mar 17 01:46:41 PM PDT 24
Finished Mar 17 01:48:02 PM PDT 24
Peak memory 211876 kb
Host smart-6bd8ef7c-3778-40aa-8198-0c50a8184967
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3214194719 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_tl_in
tg_err.3214194719
Directory /workspace/7.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_mem_rw_with_rand_reset.3434566561
Short name T812
Test name
Test status
Simulation time 3885293470 ps
CPU time 20.69 seconds
Started Mar 17 03:03:40 PM PDT 24
Finished Mar 17 03:04:01 PM PDT 24
Peak memory 216180 kb
Host smart-4b3ada8d-67cd-4289-a377-9c01612b700e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3434566561 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 8.rom_ctrl_csr_mem_rw_with_rand_reset.3434566561
Directory /workspace/8.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_mem_rw_with_rand_reset.400417528
Short name T873
Test name
Test status
Simulation time 9396890891 ps
CPU time 16.53 seconds
Started Mar 17 01:46:48 PM PDT 24
Finished Mar 17 01:47:05 PM PDT 24
Peak memory 219112 kb
Host smart-2863ecf9-3959-4304-af64-c86c91842d6c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=400417528 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 8.rom_ctrl_csr_mem_rw_with_rand_reset.400417528
Directory /workspace/8.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_rw.1127079260
Short name T84
Test name
Test status
Simulation time 661746104 ps
CPU time 7.96 seconds
Started Mar 17 03:03:40 PM PDT 24
Finished Mar 17 03:03:48 PM PDT 24
Peak memory 210864 kb
Host smart-9cd51835-41a0-4e6b-9e47-12dc2cbc6d74
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1127079260 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_csr_rw.1127079260
Directory /workspace/8.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_rw.3554516882
Short name T847
Test name
Test status
Simulation time 490249392 ps
CPU time 4.09 seconds
Started Mar 17 01:46:38 PM PDT 24
Finished Mar 17 01:46:42 PM PDT 24
Peak memory 210888 kb
Host smart-bf241a99-558d-4de8-992c-f20260d2ab37
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3554516882 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_csr_rw.3554516882
Directory /workspace/8.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_passthru_mem_tl_intg_err.2786547416
Short name T99
Test name
Test status
Simulation time 12734287670 ps
CPU time 124.78 seconds
Started Mar 17 03:03:40 PM PDT 24
Finished Mar 17 03:05:46 PM PDT 24
Peak memory 215504 kb
Host smart-11c1c3a7-de90-49ea-b770-ae7e43c6358a
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2786547416 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_pa
ssthru_mem_tl_intg_err.2786547416
Directory /workspace/8.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_passthru_mem_tl_intg_err.4139229356
Short name T798
Test name
Test status
Simulation time 31957258629 ps
CPU time 74.11 seconds
Started Mar 17 01:46:37 PM PDT 24
Finished Mar 17 01:47:52 PM PDT 24
Peak memory 210980 kb
Host smart-24f0fdc3-445e-43b0-b124-6cfbb6b7ab8d
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4139229356 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_pa
ssthru_mem_tl_intg_err.4139229356
Directory /workspace/8.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_same_csr_outstanding.4064995413
Short name T899
Test name
Test status
Simulation time 1194388456 ps
CPU time 16.33 seconds
Started Mar 17 03:03:39 PM PDT 24
Finished Mar 17 03:03:55 PM PDT 24
Peak memory 211680 kb
Host smart-487a6e25-3067-4d2b-acb9-835370853de4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4064995413 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_c
trl_same_csr_outstanding.4064995413
Directory /workspace/8.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_same_csr_outstanding.4110888516
Short name T864
Test name
Test status
Simulation time 3033173261 ps
CPU time 7.45 seconds
Started Mar 17 01:46:22 PM PDT 24
Finished Mar 17 01:46:30 PM PDT 24
Peak memory 210968 kb
Host smart-b9d37a60-578c-41da-802c-6426715a002c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4110888516 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_c
trl_same_csr_outstanding.4110888516
Directory /workspace/8.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_errors.3224678173
Short name T789
Test name
Test status
Simulation time 7347078670 ps
CPU time 17.37 seconds
Started Mar 17 01:46:38 PM PDT 24
Finished Mar 17 01:46:58 PM PDT 24
Peak memory 219192 kb
Host smart-ee93348d-6f42-456c-be63-ac5d8b1fd9a9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3224678173 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_tl_errors.3224678173
Directory /workspace/8.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_errors.4130559946
Short name T764
Test name
Test status
Simulation time 16538628914 ps
CPU time 39.6 seconds
Started Mar 17 03:03:39 PM PDT 24
Finished Mar 17 03:04:19 PM PDT 24
Peak memory 217660 kb
Host smart-17162526-543c-49ea-9750-6af3bf373e61
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4130559946 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_tl_errors.4130559946
Directory /workspace/8.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_intg_err.304156524
Short name T120
Test name
Test status
Simulation time 2791247500 ps
CPU time 166.65 seconds
Started Mar 17 03:03:38 PM PDT 24
Finished Mar 17 03:06:25 PM PDT 24
Peak memory 213640 kb
Host smart-1b938cda-1c00-4297-867a-dcd0c7a1d02a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=304156524 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_tl_int
g_err.304156524
Directory /workspace/8.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_intg_err.4120875476
Short name T830
Test name
Test status
Simulation time 1701605440 ps
CPU time 73.16 seconds
Started Mar 17 01:46:37 PM PDT 24
Finished Mar 17 01:47:51 PM PDT 24
Peak memory 210920 kb
Host smart-18680743-f72e-428f-9c68-3862b1160e39
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4120875476 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_tl_in
tg_err.4120875476
Directory /workspace/8.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_mem_rw_with_rand_reset.1741092366
Short name T802
Test name
Test status
Simulation time 182412737 ps
CPU time 9.11 seconds
Started Mar 17 03:03:39 PM PDT 24
Finished Mar 17 03:03:49 PM PDT 24
Peak memory 216020 kb
Host smart-0585b3f9-91bd-4764-84ab-98b4733f44aa
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1741092366 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 9.rom_ctrl_csr_mem_rw_with_rand_reset.1741092366
Directory /workspace/9.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_mem_rw_with_rand_reset.842854893
Short name T836
Test name
Test status
Simulation time 1384008605 ps
CPU time 13.29 seconds
Started Mar 17 01:46:37 PM PDT 24
Finished Mar 17 01:46:51 PM PDT 24
Peak memory 219132 kb
Host smart-9dbb495f-b234-495b-87f7-f1bb6a74d7e9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=842854893 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 9.rom_ctrl_csr_mem_rw_with_rand_reset.842854893
Directory /workspace/9.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_rw.2534699816
Short name T757
Test name
Test status
Simulation time 2053712159 ps
CPU time 19.62 seconds
Started Mar 17 03:03:46 PM PDT 24
Finished Mar 17 03:04:06 PM PDT 24
Peak memory 211540 kb
Host smart-70bd8cf0-e328-4ec2-bae2-5d79c7b8f571
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2534699816 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_csr_rw.2534699816
Directory /workspace/9.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_rw.3523468814
Short name T109
Test name
Test status
Simulation time 2727073297 ps
CPU time 7.72 seconds
Started Mar 17 01:46:43 PM PDT 24
Finished Mar 17 01:46:52 PM PDT 24
Peak memory 210952 kb
Host smart-22437c41-1a18-49b5-afee-a787b94b60f0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3523468814 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_csr_rw.3523468814
Directory /workspace/9.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_passthru_mem_tl_intg_err.107376349
Short name T803
Test name
Test status
Simulation time 2200272002 ps
CPU time 56.68 seconds
Started Mar 17 03:03:39 PM PDT 24
Finished Mar 17 03:04:36 PM PDT 24
Peak memory 213492 kb
Host smart-e6bb0e38-60e0-4a29-ae93-561100ca5948
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=107376349 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_pas
sthru_mem_tl_intg_err.107376349
Directory /workspace/9.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_passthru_mem_tl_intg_err.359025467
Short name T888
Test name
Test status
Simulation time 2542747849 ps
CPU time 27.04 seconds
Started Mar 17 01:46:34 PM PDT 24
Finished Mar 17 01:47:02 PM PDT 24
Peak memory 210888 kb
Host smart-e123f06a-0e7f-4379-8fc5-2a59159ba88d
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=359025467 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_pas
sthru_mem_tl_intg_err.359025467
Directory /workspace/9.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_same_csr_outstanding.2685376988
Short name T773
Test name
Test status
Simulation time 2384556133 ps
CPU time 19.07 seconds
Started Mar 17 03:03:38 PM PDT 24
Finished Mar 17 03:03:57 PM PDT 24
Peak memory 212360 kb
Host smart-3b369e68-fff7-4620-af52-cc0422433615
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2685376988 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_c
trl_same_csr_outstanding.2685376988
Directory /workspace/9.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_same_csr_outstanding.2686007922
Short name T786
Test name
Test status
Simulation time 2060898266 ps
CPU time 17.09 seconds
Started Mar 17 01:46:51 PM PDT 24
Finished Mar 17 01:47:09 PM PDT 24
Peak memory 210872 kb
Host smart-bf340a8d-416f-44f1-8d71-7d14203c89c8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2686007922 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_c
trl_same_csr_outstanding.2686007922
Directory /workspace/9.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_errors.2371698408
Short name T806
Test name
Test status
Simulation time 4544509895 ps
CPU time 27.12 seconds
Started Mar 17 03:03:40 PM PDT 24
Finished Mar 17 03:04:08 PM PDT 24
Peak memory 217644 kb
Host smart-670711cc-2742-4554-8fcc-481407a693ad
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2371698408 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_tl_errors.2371698408
Directory /workspace/9.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_errors.63013736
Short name T856
Test name
Test status
Simulation time 1072602505 ps
CPU time 14.27 seconds
Started Mar 17 01:46:37 PM PDT 24
Finished Mar 17 01:46:52 PM PDT 24
Peak memory 219144 kb
Host smart-6cd1788a-a727-4848-89a9-c79403b8fed6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=63013736 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_tl_errors.63013736
Directory /workspace/9.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_intg_err.1496372546
Short name T781
Test name
Test status
Simulation time 247577285 ps
CPU time 68.57 seconds
Started Mar 17 01:46:36 PM PDT 24
Finished Mar 17 01:47:45 PM PDT 24
Peak memory 211936 kb
Host smart-b2fc627b-aa08-414a-ba93-7134b569fc3b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1496372546 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_tl_in
tg_err.1496372546
Directory /workspace/9.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_intg_err.3832809027
Short name T778
Test name
Test status
Simulation time 2841964454 ps
CPU time 168.74 seconds
Started Mar 17 03:03:43 PM PDT 24
Finished Mar 17 03:06:31 PM PDT 24
Peak memory 214548 kb
Host smart-de99f702-71e2-435a-ba73-7e03bbd29c32
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3832809027 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_tl_in
tg_err.3832809027
Directory /workspace/9.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/0.rom_ctrl_alert_test.1079938141
Short name T608
Test name
Test status
Simulation time 2743705767 ps
CPU time 12.97 seconds
Started Mar 17 01:46:40 PM PDT 24
Finished Mar 17 01:46:55 PM PDT 24
Peak memory 211228 kb
Host smart-bdafac5c-80b4-4813-9776-ae7c1a6f3ea3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1079938141 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_alert_test.1079938141
Directory /workspace/0.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/0.rom_ctrl_alert_test.1224475746
Short name T37
Test name
Test status
Simulation time 3383473131 ps
CPU time 28.05 seconds
Started Mar 17 02:40:02 PM PDT 24
Finished Mar 17 02:40:30 PM PDT 24
Peak memory 211936 kb
Host smart-9627cfbd-e871-4d0a-b4af-11869c59fe6c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1224475746 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_alert_test.1224475746
Directory /workspace/0.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/0.rom_ctrl_corrupt_sig_fatal_chk.152651657
Short name T522
Test name
Test status
Simulation time 133401594998 ps
CPU time 695.67 seconds
Started Mar 17 01:46:51 PM PDT 24
Finished Mar 17 01:58:28 PM PDT 24
Peak memory 216196 kb
Host smart-87f86acc-fa25-4373-be81-bf17dfd1a105
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=152651657 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_co
rrupt_sig_fatal_chk.152651657
Directory /workspace/0.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/0.rom_ctrl_corrupt_sig_fatal_chk.2346362498
Short name T625
Test name
Test status
Simulation time 4640807182 ps
CPU time 330.97 seconds
Started Mar 17 02:39:58 PM PDT 24
Finished Mar 17 02:45:29 PM PDT 24
Peak memory 237588 kb
Host smart-4ae7f095-15b8-4288-bea1-9bbedf22a01c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2346362498 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_c
orrupt_sig_fatal_chk.2346362498
Directory /workspace/0.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/0.rom_ctrl_kmac_err_chk.1090251405
Short name T440
Test name
Test status
Simulation time 12280033025 ps
CPU time 37.61 seconds
Started Mar 17 02:39:56 PM PDT 24
Finished Mar 17 02:40:33 PM PDT 24
Peak memory 214996 kb
Host smart-01b66897-1fee-467a-82ac-9dd4ccbbdcd2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1090251405 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_kmac_err_chk.1090251405
Directory /workspace/0.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/0.rom_ctrl_kmac_err_chk.718753374
Short name T316
Test name
Test status
Simulation time 1938857138 ps
CPU time 18.65 seconds
Started Mar 17 01:46:40 PM PDT 24
Finished Mar 17 01:47:01 PM PDT 24
Peak memory 214440 kb
Host smart-0bfa1df6-5a54-4025-b34f-43d5bc05919b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=718753374 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_kmac_err_chk.718753374
Directory /workspace/0.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/0.rom_ctrl_max_throughput_chk.248688014
Short name T191
Test name
Test status
Simulation time 5114716140 ps
CPU time 26.1 seconds
Started Mar 17 02:39:58 PM PDT 24
Finished Mar 17 02:40:24 PM PDT 24
Peak memory 212708 kb
Host smart-69c35097-7450-43b0-a876-b131d332416f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=248688014 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_max_throughput_chk.248688014
Directory /workspace/0.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/0.rom_ctrl_max_throughput_chk.3393054898
Short name T363
Test name
Test status
Simulation time 3400472732 ps
CPU time 20.17 seconds
Started Mar 17 01:46:41 PM PDT 24
Finished Mar 17 01:47:03 PM PDT 24
Peak memory 211964 kb
Host smart-cfaf0cac-3eb3-427f-aab0-f21991b9460f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3393054898 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_max_throughput_chk.3393054898
Directory /workspace/0.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/0.rom_ctrl_sec_cm.3503057243
Short name T41
Test name
Test status
Simulation time 25920052469 ps
CPU time 237.68 seconds
Started Mar 17 01:46:49 PM PDT 24
Finished Mar 17 01:50:46 PM PDT 24
Peak memory 238020 kb
Host smart-10ac4533-967f-4078-876b-e1ded7a5436d
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3503057243 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_sec_cm.3503057243
Directory /workspace/0.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/0.rom_ctrl_sec_cm.561420741
Short name T35
Test name
Test status
Simulation time 1979083042 ps
CPU time 130.43 seconds
Started Mar 17 02:39:59 PM PDT 24
Finished Mar 17 02:42:10 PM PDT 24
Peak memory 236976 kb
Host smart-37eb8de1-e9d3-4d55-a0f3-d1f754fbcf5e
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=561420741 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_sec_cm.561420741
Directory /workspace/0.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/0.rom_ctrl_smoke.1326638789
Short name T443
Test name
Test status
Simulation time 5950061901 ps
CPU time 63.79 seconds
Started Mar 17 02:39:52 PM PDT 24
Finished Mar 17 02:40:56 PM PDT 24
Peak memory 218428 kb
Host smart-091e40a8-22db-493c-877b-8088b90a373a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1326638789 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_smoke.1326638789
Directory /workspace/0.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/0.rom_ctrl_smoke.274477004
Short name T203
Test name
Test status
Simulation time 2028766202 ps
CPU time 19.84 seconds
Started Mar 17 01:46:54 PM PDT 24
Finished Mar 17 01:47:14 PM PDT 24
Peak memory 217624 kb
Host smart-e3838167-e172-4b15-b778-cc62ca30175a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=274477004 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_smoke.274477004
Directory /workspace/0.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/0.rom_ctrl_stress_all.1681129718
Short name T375
Test name
Test status
Simulation time 10121868599 ps
CPU time 67.79 seconds
Started Mar 17 01:46:52 PM PDT 24
Finished Mar 17 01:48:01 PM PDT 24
Peak memory 219280 kb
Host smart-13936d92-c92c-4aae-9e0c-7e3e75b9097e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1681129718 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 0.rom_ctrl_stress_all.1681129718
Directory /workspace/0.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/0.rom_ctrl_stress_all.2183748701
Short name T582
Test name
Test status
Simulation time 36675983281 ps
CPU time 120.94 seconds
Started Mar 17 02:39:53 PM PDT 24
Finished Mar 17 02:41:54 PM PDT 24
Peak memory 219272 kb
Host smart-0032af91-afd8-4e37-a8db-426bace4cb71
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2183748701 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 0.rom_ctrl_stress_all.2183748701
Directory /workspace/0.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/1.rom_ctrl_alert_test.167413444
Short name T643
Test name
Test status
Simulation time 332494120 ps
CPU time 8.46 seconds
Started Mar 17 02:39:57 PM PDT 24
Finished Mar 17 02:40:06 PM PDT 24
Peak memory 211240 kb
Host smart-817e1a76-6cbe-44e1-b6e1-98b5ad088703
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=167413444 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_alert_test.167413444
Directory /workspace/1.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/1.rom_ctrl_alert_test.2397308970
Short name T252
Test name
Test status
Simulation time 10306657762 ps
CPU time 23.47 seconds
Started Mar 17 01:46:39 PM PDT 24
Finished Mar 17 01:47:04 PM PDT 24
Peak memory 212072 kb
Host smart-8a3edd46-1f50-4c00-b811-b22c735b6816
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2397308970 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_alert_test.2397308970
Directory /workspace/1.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/1.rom_ctrl_corrupt_sig_fatal_chk.1292698581
Short name T294
Test name
Test status
Simulation time 106325231093 ps
CPU time 416.84 seconds
Started Mar 17 02:39:58 PM PDT 24
Finished Mar 17 02:46:55 PM PDT 24
Peak memory 233596 kb
Host smart-78239e72-8211-4231-a787-82ef7872a812
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1292698581 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_c
orrupt_sig_fatal_chk.1292698581
Directory /workspace/1.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/1.rom_ctrl_corrupt_sig_fatal_chk.3109400400
Short name T544
Test name
Test status
Simulation time 90658711437 ps
CPU time 828.59 seconds
Started Mar 17 01:46:43 PM PDT 24
Finished Mar 17 02:00:33 PM PDT 24
Peak memory 234384 kb
Host smart-1170de8c-f806-4fb9-9e27-ed9df307ebf0
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3109400400 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_c
orrupt_sig_fatal_chk.3109400400
Directory /workspace/1.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/1.rom_ctrl_kmac_err_chk.1601572617
Short name T296
Test name
Test status
Simulation time 19651650672 ps
CPU time 38.87 seconds
Started Mar 17 01:46:51 PM PDT 24
Finished Mar 17 01:47:31 PM PDT 24
Peak memory 214916 kb
Host smart-9e6b286f-0d8d-4b2c-ab44-6ab625068ae8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1601572617 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_kmac_err_chk.1601572617
Directory /workspace/1.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/1.rom_ctrl_kmac_err_chk.3184268685
Short name T521
Test name
Test status
Simulation time 8462103907 ps
CPU time 71.37 seconds
Started Mar 17 02:39:59 PM PDT 24
Finished Mar 17 02:41:10 PM PDT 24
Peak memory 214900 kb
Host smart-1e6df4a0-ac6b-4642-bd01-8b317f79b3ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3184268685 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_kmac_err_chk.3184268685
Directory /workspace/1.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/1.rom_ctrl_max_throughput_chk.3295912955
Short name T313
Test name
Test status
Simulation time 719113334 ps
CPU time 10.33 seconds
Started Mar 17 02:39:58 PM PDT 24
Finished Mar 17 02:40:09 PM PDT 24
Peak memory 212528 kb
Host smart-a951b30a-7e30-422b-964e-98b086d5f2e5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3295912955 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_max_throughput_chk.3295912955
Directory /workspace/1.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/1.rom_ctrl_max_throughput_chk.745699672
Short name T144
Test name
Test status
Simulation time 13243037962 ps
CPU time 27.08 seconds
Started Mar 17 01:46:43 PM PDT 24
Finished Mar 17 01:47:12 PM PDT 24
Peak memory 212416 kb
Host smart-36940f56-19b0-4831-8f18-adca8bbb0e38
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=745699672 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_max_throughput_chk.745699672
Directory /workspace/1.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/1.rom_ctrl_sec_cm.3266632601
Short name T42
Test name
Test status
Simulation time 3933453406 ps
CPU time 139.9 seconds
Started Mar 17 01:46:48 PM PDT 24
Finished Mar 17 01:49:08 PM PDT 24
Peak memory 236440 kb
Host smart-689bf03f-7f9e-4b07-ba26-23ade0c0fe28
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3266632601 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_sec_cm.3266632601
Directory /workspace/1.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/1.rom_ctrl_sec_cm.650652803
Short name T38
Test name
Test status
Simulation time 2992569778 ps
CPU time 132.42 seconds
Started Mar 17 02:40:01 PM PDT 24
Finished Mar 17 02:42:13 PM PDT 24
Peak memory 237112 kb
Host smart-7237ef09-0a0d-4dac-99fe-cf3a85aa2e53
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=650652803 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_sec_cm.650652803
Directory /workspace/1.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/1.rom_ctrl_smoke.1137122925
Short name T408
Test name
Test status
Simulation time 2234893803 ps
CPU time 37.82 seconds
Started Mar 17 02:39:57 PM PDT 24
Finished Mar 17 02:40:36 PM PDT 24
Peak memory 216220 kb
Host smart-2739857e-068d-4926-8895-d97f76760784
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1137122925 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_smoke.1137122925
Directory /workspace/1.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/1.rom_ctrl_smoke.2519170505
Short name T368
Test name
Test status
Simulation time 8591580344 ps
CPU time 49.78 seconds
Started Mar 17 01:46:41 PM PDT 24
Finished Mar 17 01:47:33 PM PDT 24
Peak memory 217944 kb
Host smart-e9eea384-5d93-408b-b253-12ef915bfcee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2519170505 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_smoke.2519170505
Directory /workspace/1.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/1.rom_ctrl_stress_all.2713703730
Short name T289
Test name
Test status
Simulation time 5173314444 ps
CPU time 38.25 seconds
Started Mar 17 01:46:46 PM PDT 24
Finished Mar 17 01:47:26 PM PDT 24
Peak memory 211236 kb
Host smart-425bbd3c-e2d8-4c0b-90e4-098aefc3662f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2713703730 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 1.rom_ctrl_stress_all.2713703730
Directory /workspace/1.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/1.rom_ctrl_stress_all.2887657673
Short name T64
Test name
Test status
Simulation time 36820911405 ps
CPU time 43.65 seconds
Started Mar 17 02:39:57 PM PDT 24
Finished Mar 17 02:40:41 PM PDT 24
Peak memory 217720 kb
Host smart-40264c78-012e-4cf8-8ff5-ba0651dc79b0
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2887657673 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 1.rom_ctrl_stress_all.2887657673
Directory /workspace/1.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/10.rom_ctrl_alert_test.3571989429
Short name T362
Test name
Test status
Simulation time 23177191688 ps
CPU time 33.61 seconds
Started Mar 17 01:46:57 PM PDT 24
Finished Mar 17 01:47:31 PM PDT 24
Peak memory 212120 kb
Host smart-356093c1-2ca1-49d0-8379-87ea8337de2c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3571989429 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_alert_test.3571989429
Directory /workspace/10.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/10.rom_ctrl_alert_test.4119424355
Short name T171
Test name
Test status
Simulation time 7708476280 ps
CPU time 29.91 seconds
Started Mar 17 02:40:18 PM PDT 24
Finished Mar 17 02:40:48 PM PDT 24
Peak memory 212172 kb
Host smart-05673d2d-53a9-418f-9cb9-d20d8ea9b0b3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4119424355 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_alert_test.4119424355
Directory /workspace/10.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/10.rom_ctrl_corrupt_sig_fatal_chk.1485290902
Short name T495
Test name
Test status
Simulation time 118552865490 ps
CPU time 295.7 seconds
Started Mar 17 01:46:52 PM PDT 24
Finished Mar 17 01:51:48 PM PDT 24
Peak memory 240444 kb
Host smart-3e1ab3c6-8c5e-442e-bd5e-ecee02565665
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1485290902 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_
corrupt_sig_fatal_chk.1485290902
Directory /workspace/10.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/10.rom_ctrl_corrupt_sig_fatal_chk.1657294576
Short name T621
Test name
Test status
Simulation time 59668135687 ps
CPU time 399.55 seconds
Started Mar 17 02:40:07 PM PDT 24
Finished Mar 17 02:46:47 PM PDT 24
Peak memory 236388 kb
Host smart-59a79dfc-c689-426a-a910-b134a3c2d000
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1657294576 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_
corrupt_sig_fatal_chk.1657294576
Directory /workspace/10.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/10.rom_ctrl_kmac_err_chk.2034982256
Short name T431
Test name
Test status
Simulation time 346228252 ps
CPU time 19.5 seconds
Started Mar 17 02:40:07 PM PDT 24
Finished Mar 17 02:40:27 PM PDT 24
Peak memory 214500 kb
Host smart-a9b0ba1d-93b5-47df-bb58-7163c3b9410c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2034982256 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_kmac_err_chk.2034982256
Directory /workspace/10.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/10.rom_ctrl_kmac_err_chk.690431198
Short name T442
Test name
Test status
Simulation time 7387397109 ps
CPU time 63 seconds
Started Mar 17 01:46:59 PM PDT 24
Finished Mar 17 01:48:02 PM PDT 24
Peak memory 215056 kb
Host smart-64b5f9c1-64ec-4afc-86ec-fad13f23ffeb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=690431198 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_kmac_err_chk.690431198
Directory /workspace/10.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/10.rom_ctrl_max_throughput_chk.2226385241
Short name T146
Test name
Test status
Simulation time 5046405075 ps
CPU time 16.21 seconds
Started Mar 17 01:47:00 PM PDT 24
Finished Mar 17 01:47:16 PM PDT 24
Peak memory 212816 kb
Host smart-eca1514e-bf25-41cd-9df7-27057a221614
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2226385241 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_max_throughput_chk.2226385241
Directory /workspace/10.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/10.rom_ctrl_max_throughput_chk.572051961
Short name T614
Test name
Test status
Simulation time 3891553337 ps
CPU time 21.54 seconds
Started Mar 17 02:40:18 PM PDT 24
Finished Mar 17 02:40:39 PM PDT 24
Peak memory 211236 kb
Host smart-ad596007-51c8-4f37-a38e-98d0305cb82e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=572051961 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_max_throughput_chk.572051961
Directory /workspace/10.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/10.rom_ctrl_smoke.1654340432
Short name T234
Test name
Test status
Simulation time 8756862968 ps
CPU time 70.59 seconds
Started Mar 17 02:40:18 PM PDT 24
Finished Mar 17 02:41:29 PM PDT 24
Peak memory 218172 kb
Host smart-42687479-94ec-42a6-b4d1-f1abd885533d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1654340432 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_smoke.1654340432
Directory /workspace/10.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/10.rom_ctrl_smoke.4073781480
Short name T312
Test name
Test status
Simulation time 14471887619 ps
CPU time 42.69 seconds
Started Mar 17 01:46:58 PM PDT 24
Finished Mar 17 01:47:41 PM PDT 24
Peak memory 218000 kb
Host smart-303dbcd9-8c5d-473f-98b3-e87df80713cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4073781480 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_smoke.4073781480
Directory /workspace/10.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/10.rom_ctrl_stress_all.1293198549
Short name T476
Test name
Test status
Simulation time 41962713638 ps
CPU time 45.51 seconds
Started Mar 17 01:47:03 PM PDT 24
Finished Mar 17 01:47:48 PM PDT 24
Peak memory 218284 kb
Host smart-a491d58d-9383-483d-8832-c6cdbb58687d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1293198549 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 10.rom_ctrl_stress_all.1293198549
Directory /workspace/10.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/10.rom_ctrl_stress_all.1962276908
Short name T67
Test name
Test status
Simulation time 14781718668 ps
CPU time 139.52 seconds
Started Mar 17 02:40:02 PM PDT 24
Finished Mar 17 02:42:22 PM PDT 24
Peak memory 219932 kb
Host smart-395d904c-5f58-48e2-910a-d271f8058216
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1962276908 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 10.rom_ctrl_stress_all.1962276908
Directory /workspace/10.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/11.rom_ctrl_alert_test.2063650579
Short name T459
Test name
Test status
Simulation time 1325688686 ps
CPU time 10.92 seconds
Started Mar 17 02:40:07 PM PDT 24
Finished Mar 17 02:40:18 PM PDT 24
Peak memory 211204 kb
Host smart-4df515f8-b60f-4b57-9077-e7da507a2462
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2063650579 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_alert_test.2063650579
Directory /workspace/11.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/11.rom_ctrl_alert_test.752119141
Short name T652
Test name
Test status
Simulation time 935525053 ps
CPU time 14.66 seconds
Started Mar 17 01:47:06 PM PDT 24
Finished Mar 17 01:47:21 PM PDT 24
Peak memory 211168 kb
Host smart-95b7079e-3006-4d59-8cdd-dffe72131e21
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=752119141 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_alert_test.752119141
Directory /workspace/11.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/11.rom_ctrl_corrupt_sig_fatal_chk.3907338449
Short name T159
Test name
Test status
Simulation time 14094433903 ps
CPU time 197.28 seconds
Started Mar 17 01:46:46 PM PDT 24
Finished Mar 17 01:50:04 PM PDT 24
Peak memory 228148 kb
Host smart-db88c076-130b-4897-9727-71a0549155e8
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3907338449 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_
corrupt_sig_fatal_chk.3907338449
Directory /workspace/11.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/11.rom_ctrl_kmac_err_chk.2042242715
Short name T492
Test name
Test status
Simulation time 37487032023 ps
CPU time 58.54 seconds
Started Mar 17 02:40:03 PM PDT 24
Finished Mar 17 02:41:02 PM PDT 24
Peak memory 213772 kb
Host smart-4448b081-648a-4c4d-88d4-694698d270d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2042242715 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_kmac_err_chk.2042242715
Directory /workspace/11.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/11.rom_ctrl_max_throughput_chk.1789795316
Short name T449
Test name
Test status
Simulation time 2020675314 ps
CPU time 22.52 seconds
Started Mar 17 01:47:00 PM PDT 24
Finished Mar 17 01:47:23 PM PDT 24
Peak memory 211200 kb
Host smart-d88b03b4-8903-42d9-8275-b63bd7a56546
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1789795316 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_max_throughput_chk.1789795316
Directory /workspace/11.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/11.rom_ctrl_max_throughput_chk.830382054
Short name T506
Test name
Test status
Simulation time 5916489904 ps
CPU time 27.62 seconds
Started Mar 17 02:40:02 PM PDT 24
Finished Mar 17 02:40:30 PM PDT 24
Peak memory 212428 kb
Host smart-26898a01-db3d-4345-b069-6039f709a7b4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=830382054 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_max_throughput_chk.830382054
Directory /workspace/11.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/11.rom_ctrl_smoke.1888463422
Short name T385
Test name
Test status
Simulation time 1493838421 ps
CPU time 20.12 seconds
Started Mar 17 02:40:04 PM PDT 24
Finished Mar 17 02:40:24 PM PDT 24
Peak memory 217432 kb
Host smart-15858772-89ab-4a5a-8a23-07eb53871d77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1888463422 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_smoke.1888463422
Directory /workspace/11.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/11.rom_ctrl_smoke.2597499518
Short name T3
Test name
Test status
Simulation time 28914764035 ps
CPU time 63.11 seconds
Started Mar 17 01:47:03 PM PDT 24
Finished Mar 17 01:48:06 PM PDT 24
Peak memory 217792 kb
Host smart-a58c5945-518e-4ee6-b245-89a25ee5f657
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2597499518 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_smoke.2597499518
Directory /workspace/11.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/11.rom_ctrl_stress_all.1420323620
Short name T269
Test name
Test status
Simulation time 88420118126 ps
CPU time 188.2 seconds
Started Mar 17 02:40:04 PM PDT 24
Finished Mar 17 02:43:12 PM PDT 24
Peak memory 219800 kb
Host smart-05e41910-504f-4ca2-8020-e65b23d0e132
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1420323620 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 11.rom_ctrl_stress_all.1420323620
Directory /workspace/11.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/11.rom_ctrl_stress_all.3128155090
Short name T533
Test name
Test status
Simulation time 13139345270 ps
CPU time 81.21 seconds
Started Mar 17 01:47:03 PM PDT 24
Finished Mar 17 01:48:25 PM PDT 24
Peak memory 219304 kb
Host smart-ed5cbfdd-1112-4d38-9ae1-9f0ca9c0198a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3128155090 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 11.rom_ctrl_stress_all.3128155090
Directory /workspace/11.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/12.rom_ctrl_alert_test.2060459009
Short name T199
Test name
Test status
Simulation time 4067474045 ps
CPU time 33.93 seconds
Started Mar 17 01:47:00 PM PDT 24
Finished Mar 17 01:47:34 PM PDT 24
Peak memory 211776 kb
Host smart-aad5b8d8-5719-4a66-9561-080ced13e36e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2060459009 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_alert_test.2060459009
Directory /workspace/12.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/12.rom_ctrl_alert_test.3877254329
Short name T532
Test name
Test status
Simulation time 3935389278 ps
CPU time 33.38 seconds
Started Mar 17 02:40:11 PM PDT 24
Finished Mar 17 02:40:44 PM PDT 24
Peak memory 211892 kb
Host smart-05b80ea8-165f-4fae-9c34-b26847d5f8cd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3877254329 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_alert_test.3877254329
Directory /workspace/12.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/12.rom_ctrl_corrupt_sig_fatal_chk.1379609986
Short name T636
Test name
Test status
Simulation time 86059445206 ps
CPU time 382.91 seconds
Started Mar 17 02:40:08 PM PDT 24
Finished Mar 17 02:46:31 PM PDT 24
Peak memory 225148 kb
Host smart-44f67174-9541-40a6-aa8c-35626822985b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1379609986 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_
corrupt_sig_fatal_chk.1379609986
Directory /workspace/12.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/12.rom_ctrl_corrupt_sig_fatal_chk.788393416
Short name T623
Test name
Test status
Simulation time 245913414205 ps
CPU time 471.88 seconds
Started Mar 17 01:46:53 PM PDT 24
Finished Mar 17 01:54:45 PM PDT 24
Peak memory 238548 kb
Host smart-9a23064e-7243-4d96-a7e0-cccacbece47f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=788393416 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_c
orrupt_sig_fatal_chk.788393416
Directory /workspace/12.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/12.rom_ctrl_kmac_err_chk.126751727
Short name T331
Test name
Test status
Simulation time 44913178177 ps
CPU time 43.08 seconds
Started Mar 17 01:46:57 PM PDT 24
Finished Mar 17 01:47:41 PM PDT 24
Peak memory 214848 kb
Host smart-030d547d-4e98-4e9f-94de-58bfd9c14516
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=126751727 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_kmac_err_chk.126751727
Directory /workspace/12.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/12.rom_ctrl_kmac_err_chk.177787998
Short name T381
Test name
Test status
Simulation time 332287907 ps
CPU time 19.08 seconds
Started Mar 17 02:40:10 PM PDT 24
Finished Mar 17 02:40:30 PM PDT 24
Peak memory 214508 kb
Host smart-02d5063e-ec60-4680-a8da-282a41bf94e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=177787998 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_kmac_err_chk.177787998
Directory /workspace/12.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/12.rom_ctrl_max_throughput_chk.172334678
Short name T581
Test name
Test status
Simulation time 12059693731 ps
CPU time 25.01 seconds
Started Mar 17 01:46:56 PM PDT 24
Finished Mar 17 01:47:22 PM PDT 24
Peak memory 211632 kb
Host smart-3f8b572e-ccf8-4b04-8056-680048d831e0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=172334678 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_max_throughput_chk.172334678
Directory /workspace/12.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/12.rom_ctrl_max_throughput_chk.647821204
Short name T559
Test name
Test status
Simulation time 3758612235 ps
CPU time 30.97 seconds
Started Mar 17 02:40:02 PM PDT 24
Finished Mar 17 02:40:33 PM PDT 24
Peak memory 212204 kb
Host smart-4427e5a3-5a72-4cd6-a91f-1403eb643e26
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=647821204 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_max_throughput_chk.647821204
Directory /workspace/12.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/12.rom_ctrl_smoke.2690650242
Short name T426
Test name
Test status
Simulation time 10969600797 ps
CPU time 38.95 seconds
Started Mar 17 01:46:57 PM PDT 24
Finished Mar 17 01:47:36 PM PDT 24
Peak memory 215316 kb
Host smart-3367ba5d-db2d-4cb5-8c3d-fce2717437b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2690650242 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_smoke.2690650242
Directory /workspace/12.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/12.rom_ctrl_smoke.790101194
Short name T286
Test name
Test status
Simulation time 19460852884 ps
CPU time 46.41 seconds
Started Mar 17 02:40:03 PM PDT 24
Finished Mar 17 02:40:50 PM PDT 24
Peak memory 218240 kb
Host smart-e9770591-d927-4bc3-83e7-3abb060ce4b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=790101194 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_smoke.790101194
Directory /workspace/12.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/12.rom_ctrl_stress_all.2048373807
Short name T306
Test name
Test status
Simulation time 26517710931 ps
CPU time 140.55 seconds
Started Mar 17 01:46:55 PM PDT 24
Finished Mar 17 01:49:16 PM PDT 24
Peak memory 219988 kb
Host smart-bad8b4a4-f0b3-4f35-a369-a1254e2432a9
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2048373807 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 12.rom_ctrl_stress_all.2048373807
Directory /workspace/12.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/12.rom_ctrl_stress_all.581263855
Short name T66
Test name
Test status
Simulation time 10908995040 ps
CPU time 35.13 seconds
Started Mar 17 02:40:04 PM PDT 24
Finished Mar 17 02:40:40 PM PDT 24
Peak memory 219328 kb
Host smart-f2a39006-6769-434c-9c99-1b016ea1d98d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=581263855 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 12.rom_ctrl_stress_all.581263855
Directory /workspace/12.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/12.rom_ctrl_stress_all_with_rand_reset.2713289266
Short name T555
Test name
Test status
Simulation time 43426897019 ps
CPU time 901.67 seconds
Started Mar 17 01:47:02 PM PDT 24
Finished Mar 17 02:02:04 PM PDT 24
Peak memory 235768 kb
Host smart-169c6ab1-790e-41bf-9989-fb46a82b5c57
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2713289266 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_stress_all_with_rand_reset.2713289266
Directory /workspace/12.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/13.rom_ctrl_alert_test.2093904213
Short name T530
Test name
Test status
Simulation time 1177908825 ps
CPU time 8.36 seconds
Started Mar 17 02:40:17 PM PDT 24
Finished Mar 17 02:40:25 PM PDT 24
Peak memory 211224 kb
Host smart-556095de-57c4-41b4-bcc5-644a01333ad4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2093904213 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_alert_test.2093904213
Directory /workspace/13.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/13.rom_ctrl_alert_test.3523081655
Short name T348
Test name
Test status
Simulation time 11882018237 ps
CPU time 26.84 seconds
Started Mar 17 01:46:58 PM PDT 24
Finished Mar 17 01:47:25 PM PDT 24
Peak memory 212332 kb
Host smart-53e46ccf-b4f4-48d7-8a79-ace32bc35891
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3523081655 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_alert_test.3523081655
Directory /workspace/13.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/13.rom_ctrl_corrupt_sig_fatal_chk.2485044071
Short name T185
Test name
Test status
Simulation time 326001817193 ps
CPU time 845.73 seconds
Started Mar 17 01:47:03 PM PDT 24
Finished Mar 17 02:01:09 PM PDT 24
Peak memory 217188 kb
Host smart-504f55a6-8a58-45f3-b295-695ff0355af7
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2485044071 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_
corrupt_sig_fatal_chk.2485044071
Directory /workspace/13.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/13.rom_ctrl_corrupt_sig_fatal_chk.45305295
Short name T541
Test name
Test status
Simulation time 160182831352 ps
CPU time 974.02 seconds
Started Mar 17 02:40:09 PM PDT 24
Finished Mar 17 02:56:23 PM PDT 24
Peak memory 217808 kb
Host smart-812300c9-df51-497d-90ed-444b66a66834
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=45305295 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_
sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_co
rrupt_sig_fatal_chk.45305295
Directory /workspace/13.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/13.rom_ctrl_kmac_err_chk.1410044712
Short name T589
Test name
Test status
Simulation time 3581525426 ps
CPU time 40.56 seconds
Started Mar 17 01:47:07 PM PDT 24
Finished Mar 17 01:47:48 PM PDT 24
Peak memory 214860 kb
Host smart-5ecdac32-4132-4f0b-9bed-960ffa991f1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1410044712 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_kmac_err_chk.1410044712
Directory /workspace/13.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/13.rom_ctrl_max_throughput_chk.2177202649
Short name T575
Test name
Test status
Simulation time 181796822 ps
CPU time 10.05 seconds
Started Mar 17 01:46:56 PM PDT 24
Finished Mar 17 01:47:07 PM PDT 24
Peak memory 212300 kb
Host smart-96d56c44-9a17-4349-a729-d4942dafd94d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2177202649 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_max_throughput_chk.2177202649
Directory /workspace/13.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/13.rom_ctrl_max_throughput_chk.4028077303
Short name T528
Test name
Test status
Simulation time 182665457 ps
CPU time 10.03 seconds
Started Mar 17 02:40:14 PM PDT 24
Finished Mar 17 02:40:24 PM PDT 24
Peak memory 212296 kb
Host smart-4c459ea8-3f32-4993-aac5-eee6c8546179
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4028077303 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_max_throughput_chk.4028077303
Directory /workspace/13.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/13.rom_ctrl_smoke.2767787974
Short name T455
Test name
Test status
Simulation time 17148020846 ps
CPU time 45.1 seconds
Started Mar 17 02:40:10 PM PDT 24
Finished Mar 17 02:40:56 PM PDT 24
Peak memory 217932 kb
Host smart-efeb497c-1acc-4f89-9db6-1a7cf4a0f197
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2767787974 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_smoke.2767787974
Directory /workspace/13.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/13.rom_ctrl_smoke.3627280713
Short name T157
Test name
Test status
Simulation time 4646629851 ps
CPU time 28.61 seconds
Started Mar 17 01:47:01 PM PDT 24
Finished Mar 17 01:47:30 PM PDT 24
Peak memory 216736 kb
Host smart-f7282fd5-bc1f-44fb-abaa-f4493526bf4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3627280713 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_smoke.3627280713
Directory /workspace/13.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/13.rom_ctrl_stress_all.2155796680
Short name T259
Test name
Test status
Simulation time 1072458523 ps
CPU time 29.53 seconds
Started Mar 17 01:47:05 PM PDT 24
Finished Mar 17 01:47:35 PM PDT 24
Peak memory 219180 kb
Host smart-2fb9d25c-a247-49a1-8ddb-dc00d3bdc064
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2155796680 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 13.rom_ctrl_stress_all.2155796680
Directory /workspace/13.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/13.rom_ctrl_stress_all.4224010407
Short name T198
Test name
Test status
Simulation time 7234374759 ps
CPU time 70.84 seconds
Started Mar 17 02:40:10 PM PDT 24
Finished Mar 17 02:41:21 PM PDT 24
Peak memory 217844 kb
Host smart-e260f9a5-af28-42c4-a579-5e0bb1658602
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4224010407 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 13.rom_ctrl_stress_all.4224010407
Directory /workspace/13.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/14.rom_ctrl_alert_test.1239416250
Short name T508
Test name
Test status
Simulation time 1965411715 ps
CPU time 20.1 seconds
Started Mar 17 02:40:10 PM PDT 24
Finished Mar 17 02:40:31 PM PDT 24
Peak memory 211852 kb
Host smart-7c5ca3b3-4353-4ccb-8a4b-1118044cc8ff
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1239416250 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_alert_test.1239416250
Directory /workspace/14.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/14.rom_ctrl_alert_test.2168869316
Short name T237
Test name
Test status
Simulation time 3291502833 ps
CPU time 28.16 seconds
Started Mar 17 01:46:56 PM PDT 24
Finished Mar 17 01:47:24 PM PDT 24
Peak memory 211244 kb
Host smart-1f278be6-6273-41b7-b69c-6e686a7e44b2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2168869316 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_alert_test.2168869316
Directory /workspace/14.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/14.rom_ctrl_corrupt_sig_fatal_chk.114934538
Short name T1
Test name
Test status
Simulation time 76544726173 ps
CPU time 381.86 seconds
Started Mar 17 02:40:10 PM PDT 24
Finished Mar 17 02:46:32 PM PDT 24
Peak memory 227692 kb
Host smart-84fe7791-dc8e-4ae9-ad86-e41a37a32548
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=114934538 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_c
orrupt_sig_fatal_chk.114934538
Directory /workspace/14.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/14.rom_ctrl_corrupt_sig_fatal_chk.17878734
Short name T282
Test name
Test status
Simulation time 164246879232 ps
CPU time 403.04 seconds
Started Mar 17 01:46:53 PM PDT 24
Finished Mar 17 01:53:37 PM PDT 24
Peak memory 237456 kb
Host smart-c8e6e4eb-4703-416f-a04c-dddf1bfb832f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17878734 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_
sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_co
rrupt_sig_fatal_chk.17878734
Directory /workspace/14.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/14.rom_ctrl_kmac_err_chk.215095118
Short name T673
Test name
Test status
Simulation time 8801313786 ps
CPU time 39.77 seconds
Started Mar 17 01:46:57 PM PDT 24
Finished Mar 17 01:47:37 PM PDT 24
Peak memory 215084 kb
Host smart-ce686809-80b1-48bb-afbb-1215608d180d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=215095118 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_kmac_err_chk.215095118
Directory /workspace/14.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/14.rom_ctrl_kmac_err_chk.3845772141
Short name T264
Test name
Test status
Simulation time 6854755360 ps
CPU time 57.02 seconds
Started Mar 17 02:40:14 PM PDT 24
Finished Mar 17 02:41:11 PM PDT 24
Peak memory 216888 kb
Host smart-1135f580-a65b-4bcb-bd3b-472b0b113271
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3845772141 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_kmac_err_chk.3845772141
Directory /workspace/14.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/14.rom_ctrl_max_throughput_chk.2151154989
Short name T143
Test name
Test status
Simulation time 3349435378 ps
CPU time 29.45 seconds
Started Mar 17 01:46:59 PM PDT 24
Finished Mar 17 01:47:28 PM PDT 24
Peak memory 212448 kb
Host smart-f5b90879-14ac-4b47-894f-7133d9064260
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2151154989 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_max_throughput_chk.2151154989
Directory /workspace/14.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/14.rom_ctrl_max_throughput_chk.659435301
Short name T494
Test name
Test status
Simulation time 4336918165 ps
CPU time 34.14 seconds
Started Mar 17 02:40:16 PM PDT 24
Finished Mar 17 02:40:50 PM PDT 24
Peak memory 211296 kb
Host smart-ab8b86fd-f8a0-43d5-96cb-a2d83a270672
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=659435301 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_max_throughput_chk.659435301
Directory /workspace/14.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/14.rom_ctrl_smoke.2181422790
Short name T194
Test name
Test status
Simulation time 839158159 ps
CPU time 27.56 seconds
Started Mar 17 02:40:11 PM PDT 24
Finished Mar 17 02:40:38 PM PDT 24
Peak memory 216472 kb
Host smart-fa38c655-8248-4ed0-b6b7-f33b61222e64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2181422790 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_smoke.2181422790
Directory /workspace/14.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/14.rom_ctrl_smoke.3073919548
Short name T415
Test name
Test status
Simulation time 368207337 ps
CPU time 20.74 seconds
Started Mar 17 01:47:08 PM PDT 24
Finished Mar 17 01:47:28 PM PDT 24
Peak memory 217144 kb
Host smart-04932fb7-150f-44b7-83cf-5ad87b8ddba3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3073919548 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_smoke.3073919548
Directory /workspace/14.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/14.rom_ctrl_stress_all.1842379123
Short name T388
Test name
Test status
Simulation time 48820018799 ps
CPU time 122.55 seconds
Started Mar 17 02:40:13 PM PDT 24
Finished Mar 17 02:42:15 PM PDT 24
Peak memory 219324 kb
Host smart-a425f2f7-0795-428e-bc88-61b132667146
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1842379123 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 14.rom_ctrl_stress_all.1842379123
Directory /workspace/14.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/15.rom_ctrl_alert_test.2205560022
Short name T367
Test name
Test status
Simulation time 7825651489 ps
CPU time 19.08 seconds
Started Mar 17 02:40:11 PM PDT 24
Finished Mar 17 02:40:30 PM PDT 24
Peak memory 212180 kb
Host smart-9be396dd-b3b4-4fae-b7c3-4e0927f5ae93
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2205560022 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_alert_test.2205560022
Directory /workspace/15.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/15.rom_ctrl_alert_test.897714310
Short name T229
Test name
Test status
Simulation time 168970687 ps
CPU time 8.38 seconds
Started Mar 17 01:46:58 PM PDT 24
Finished Mar 17 01:47:07 PM PDT 24
Peak memory 211244 kb
Host smart-e93cc9a6-a623-45a3-9df3-187b0a8e95a7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=897714310 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_alert_test.897714310
Directory /workspace/15.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/15.rom_ctrl_corrupt_sig_fatal_chk.1161968381
Short name T23
Test name
Test status
Simulation time 64562722017 ps
CPU time 203.52 seconds
Started Mar 17 02:40:11 PM PDT 24
Finished Mar 17 02:43:34 PM PDT 24
Peak memory 229332 kb
Host smart-cd102cd2-d33a-4b05-9bcc-aa919f83943b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1161968381 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_
corrupt_sig_fatal_chk.1161968381
Directory /workspace/15.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/15.rom_ctrl_corrupt_sig_fatal_chk.932239147
Short name T373
Test name
Test status
Simulation time 189222679103 ps
CPU time 1016.89 seconds
Started Mar 17 01:46:58 PM PDT 24
Finished Mar 17 02:03:56 PM PDT 24
Peak memory 225076 kb
Host smart-d938a77a-18a5-4ecd-b4fd-f1f4f9151122
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=932239147 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_c
orrupt_sig_fatal_chk.932239147
Directory /workspace/15.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/15.rom_ctrl_kmac_err_chk.2133581239
Short name T378
Test name
Test status
Simulation time 29356806726 ps
CPU time 54.51 seconds
Started Mar 17 01:46:58 PM PDT 24
Finished Mar 17 01:47:53 PM PDT 24
Peak memory 214936 kb
Host smart-c4dfc046-634b-48e8-9230-2425e8f637bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2133581239 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_kmac_err_chk.2133581239
Directory /workspace/15.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/15.rom_ctrl_kmac_err_chk.2721327780
Short name T341
Test name
Test status
Simulation time 4852428165 ps
CPU time 49.12 seconds
Started Mar 17 02:40:14 PM PDT 24
Finished Mar 17 02:41:03 PM PDT 24
Peak memory 214872 kb
Host smart-78fd0308-534f-4ba6-be59-018b08db3d2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2721327780 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_kmac_err_chk.2721327780
Directory /workspace/15.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/15.rom_ctrl_max_throughput_chk.1766489650
Short name T155
Test name
Test status
Simulation time 2568931787 ps
CPU time 18.87 seconds
Started Mar 17 01:47:02 PM PDT 24
Finished Mar 17 01:47:21 PM PDT 24
Peak memory 212416 kb
Host smart-b9a8289a-8dca-46c9-817d-a3f5d32ad61e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1766489650 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_max_throughput_chk.1766489650
Directory /workspace/15.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/15.rom_ctrl_max_throughput_chk.245799018
Short name T360
Test name
Test status
Simulation time 14161717462 ps
CPU time 30.97 seconds
Started Mar 17 02:40:10 PM PDT 24
Finished Mar 17 02:40:41 PM PDT 24
Peak memory 212784 kb
Host smart-0adecae2-a613-4b95-be8b-714b2bfb2768
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=245799018 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_max_throughput_chk.245799018
Directory /workspace/15.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/15.rom_ctrl_smoke.1215925393
Short name T364
Test name
Test status
Simulation time 360087955 ps
CPU time 20.24 seconds
Started Mar 17 01:47:03 PM PDT 24
Finished Mar 17 01:47:23 PM PDT 24
Peak memory 217408 kb
Host smart-755fcf4c-27b3-4842-bbd4-2f974aed4a78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1215925393 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_smoke.1215925393
Directory /workspace/15.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/15.rom_ctrl_smoke.3793436931
Short name T344
Test name
Test status
Simulation time 5141734070 ps
CPU time 55.85 seconds
Started Mar 17 02:40:12 PM PDT 24
Finished Mar 17 02:41:08 PM PDT 24
Peak memory 215620 kb
Host smart-d4c8d512-d42f-4558-b596-9fadc1302b46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3793436931 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_smoke.3793436931
Directory /workspace/15.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/15.rom_ctrl_stress_all.1448076094
Short name T65
Test name
Test status
Simulation time 4495852303 ps
CPU time 77.34 seconds
Started Mar 17 02:40:10 PM PDT 24
Finished Mar 17 02:41:28 PM PDT 24
Peak memory 219304 kb
Host smart-cbbcca0d-ab59-4528-883b-a90e5f546dc4
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1448076094 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 15.rom_ctrl_stress_all.1448076094
Directory /workspace/15.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/15.rom_ctrl_stress_all.544847350
Short name T512
Test name
Test status
Simulation time 10827031707 ps
CPU time 39.37 seconds
Started Mar 17 01:47:01 PM PDT 24
Finished Mar 17 01:47:41 PM PDT 24
Peak memory 219048 kb
Host smart-9c3aaad2-c4d6-4546-b194-efc97d85fd3a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=544847350 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 15.rom_ctrl_stress_all.544847350
Directory /workspace/15.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/16.rom_ctrl_alert_test.24261381
Short name T477
Test name
Test status
Simulation time 14982987287 ps
CPU time 30.64 seconds
Started Mar 17 02:40:12 PM PDT 24
Finished Mar 17 02:40:43 PM PDT 24
Peak memory 212020 kb
Host smart-cced8bec-07d4-4340-b365-10b40b3e77bc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24261381 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_alert_test.24261381
Directory /workspace/16.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/16.rom_ctrl_alert_test.3619440082
Short name T359
Test name
Test status
Simulation time 9998733227 ps
CPU time 22.96 seconds
Started Mar 17 01:47:02 PM PDT 24
Finished Mar 17 01:47:25 PM PDT 24
Peak memory 211216 kb
Host smart-722bd1e1-02b5-4669-b14d-fb76af6d1f54
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3619440082 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_alert_test.3619440082
Directory /workspace/16.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/16.rom_ctrl_corrupt_sig_fatal_chk.378204051
Short name T356
Test name
Test status
Simulation time 60057456496 ps
CPU time 740.37 seconds
Started Mar 17 01:47:00 PM PDT 24
Finished Mar 17 01:59:21 PM PDT 24
Peak memory 225632 kb
Host smart-0ea97fec-70d0-48b3-a445-8066b1977bf0
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=378204051 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_c
orrupt_sig_fatal_chk.378204051
Directory /workspace/16.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/16.rom_ctrl_corrupt_sig_fatal_chk.4045887100
Short name T46
Test name
Test status
Simulation time 7758369194 ps
CPU time 364.15 seconds
Started Mar 17 02:40:11 PM PDT 24
Finished Mar 17 02:46:16 PM PDT 24
Peak memory 227292 kb
Host smart-1892e5bd-fd87-4ce2-977f-0c7ecd560d3f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4045887100 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_
corrupt_sig_fatal_chk.4045887100
Directory /workspace/16.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/16.rom_ctrl_kmac_err_chk.1526205881
Short name T678
Test name
Test status
Simulation time 24989264950 ps
CPU time 50.27 seconds
Started Mar 17 01:47:01 PM PDT 24
Finished Mar 17 01:47:51 PM PDT 24
Peak memory 214988 kb
Host smart-fa09987a-3101-443a-a1c1-653b5ec5c4e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1526205881 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_kmac_err_chk.1526205881
Directory /workspace/16.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/16.rom_ctrl_kmac_err_chk.2418278898
Short name T664
Test name
Test status
Simulation time 10563346456 ps
CPU time 66.22 seconds
Started Mar 17 02:40:15 PM PDT 24
Finished Mar 17 02:41:21 PM PDT 24
Peak memory 214988 kb
Host smart-82a49557-cd05-45df-954e-d736ba5c92da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2418278898 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_kmac_err_chk.2418278898
Directory /workspace/16.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/16.rom_ctrl_max_throughput_chk.2263053028
Short name T292
Test name
Test status
Simulation time 12127943587 ps
CPU time 28.09 seconds
Started Mar 17 01:46:59 PM PDT 24
Finished Mar 17 01:47:27 PM PDT 24
Peak memory 211252 kb
Host smart-8c5d1b4d-fdac-4d08-93f2-71d071961312
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2263053028 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_max_throughput_chk.2263053028
Directory /workspace/16.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/16.rom_ctrl_max_throughput_chk.508692492
Short name T302
Test name
Test status
Simulation time 228869543 ps
CPU time 10.7 seconds
Started Mar 17 02:40:09 PM PDT 24
Finished Mar 17 02:40:19 PM PDT 24
Peak memory 212200 kb
Host smart-3dc069e2-f728-4850-8da3-8d94ef9913eb
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=508692492 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_max_throughput_chk.508692492
Directory /workspace/16.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/16.rom_ctrl_smoke.2054869657
Short name T345
Test name
Test status
Simulation time 3776540549 ps
CPU time 47.49 seconds
Started Mar 17 01:47:00 PM PDT 24
Finished Mar 17 01:47:48 PM PDT 24
Peak memory 216612 kb
Host smart-a96a0f43-f4ad-44aa-91ea-3949ef8e07fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2054869657 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_smoke.2054869657
Directory /workspace/16.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/16.rom_ctrl_smoke.904180092
Short name T425
Test name
Test status
Simulation time 6424290364 ps
CPU time 70.18 seconds
Started Mar 17 02:40:14 PM PDT 24
Finished Mar 17 02:41:24 PM PDT 24
Peak memory 217436 kb
Host smart-f05ae4d3-df70-465f-92c2-927077c30ed3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=904180092 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_smoke.904180092
Directory /workspace/16.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/16.rom_ctrl_stress_all.2689431803
Short name T305
Test name
Test status
Simulation time 12486966284 ps
CPU time 115.5 seconds
Started Mar 17 01:47:00 PM PDT 24
Finished Mar 17 01:48:55 PM PDT 24
Peak memory 219348 kb
Host smart-12a7a3e4-2685-413b-93f7-b90020f8a8fe
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2689431803 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 16.rom_ctrl_stress_all.2689431803
Directory /workspace/16.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/16.rom_ctrl_stress_all.3248679489
Short name T81
Test name
Test status
Simulation time 28336263195 ps
CPU time 93.44 seconds
Started Mar 17 02:40:11 PM PDT 24
Finished Mar 17 02:41:45 PM PDT 24
Peak memory 216444 kb
Host smart-8f59d7ef-6c1f-473d-89ef-70c288261a40
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3248679489 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 16.rom_ctrl_stress_all.3248679489
Directory /workspace/16.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/17.rom_ctrl_alert_test.1583218966
Short name T447
Test name
Test status
Simulation time 3286243428 ps
CPU time 28.47 seconds
Started Mar 17 02:40:10 PM PDT 24
Finished Mar 17 02:40:39 PM PDT 24
Peak memory 211848 kb
Host smart-3c60e4c9-d321-4901-8f44-33b7dd3c615d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1583218966 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_alert_test.1583218966
Directory /workspace/17.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/17.rom_ctrl_alert_test.2317604451
Short name T386
Test name
Test status
Simulation time 338828551 ps
CPU time 8.5 seconds
Started Mar 17 01:47:03 PM PDT 24
Finished Mar 17 01:47:11 PM PDT 24
Peak memory 211212 kb
Host smart-a79b4900-a357-4dc4-b22c-c7ac3dc2d0ff
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2317604451 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_alert_test.2317604451
Directory /workspace/17.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/17.rom_ctrl_corrupt_sig_fatal_chk.1244365766
Short name T419
Test name
Test status
Simulation time 203290921668 ps
CPU time 551.16 seconds
Started Mar 17 02:40:12 PM PDT 24
Finished Mar 17 02:49:24 PM PDT 24
Peak memory 237992 kb
Host smart-fe1480a4-7ee5-4391-9131-8b7941263667
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1244365766 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_
corrupt_sig_fatal_chk.1244365766
Directory /workspace/17.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/17.rom_ctrl_corrupt_sig_fatal_chk.3252773287
Short name T656
Test name
Test status
Simulation time 139399471610 ps
CPU time 364.45 seconds
Started Mar 17 01:47:13 PM PDT 24
Finished Mar 17 01:53:18 PM PDT 24
Peak memory 217152 kb
Host smart-1b4ee15b-36fc-42bf-96c1-92e95c9bd36a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3252773287 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_
corrupt_sig_fatal_chk.3252773287
Directory /workspace/17.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/17.rom_ctrl_kmac_err_chk.2188752312
Short name T658
Test name
Test status
Simulation time 11904884167 ps
CPU time 66.68 seconds
Started Mar 17 02:40:13 PM PDT 24
Finished Mar 17 02:41:20 PM PDT 24
Peak memory 214912 kb
Host smart-7da07a09-8777-46ab-afee-7c7279cbcf32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2188752312 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_kmac_err_chk.2188752312
Directory /workspace/17.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/17.rom_ctrl_kmac_err_chk.3503978963
Short name T563
Test name
Test status
Simulation time 11267976423 ps
CPU time 56.37 seconds
Started Mar 17 01:47:02 PM PDT 24
Finished Mar 17 01:47:58 PM PDT 24
Peak memory 215064 kb
Host smart-e463a05b-994a-463a-8c7a-7bc5801d262f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3503978963 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_kmac_err_chk.3503978963
Directory /workspace/17.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/17.rom_ctrl_max_throughput_chk.1425080631
Short name T523
Test name
Test status
Simulation time 180324456 ps
CPU time 10.97 seconds
Started Mar 17 01:47:04 PM PDT 24
Finished Mar 17 01:47:16 PM PDT 24
Peak memory 212668 kb
Host smart-614f66d4-a6b5-4ce0-a202-08ffeb01f75b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1425080631 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_max_throughput_chk.1425080631
Directory /workspace/17.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/17.rom_ctrl_max_throughput_chk.3346432054
Short name T343
Test name
Test status
Simulation time 4319182674 ps
CPU time 33.09 seconds
Started Mar 17 02:40:16 PM PDT 24
Finished Mar 17 02:40:49 PM PDT 24
Peak memory 211360 kb
Host smart-e83eb641-e219-4a33-bb23-d70e7e55ad3e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3346432054 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_max_throughput_chk.3346432054
Directory /workspace/17.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/17.rom_ctrl_smoke.1509151062
Short name T353
Test name
Test status
Simulation time 59724759843 ps
CPU time 70.02 seconds
Started Mar 17 02:40:13 PM PDT 24
Finished Mar 17 02:41:23 PM PDT 24
Peak memory 215220 kb
Host smart-706a2150-3593-4541-95a5-62599ec4431a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1509151062 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_smoke.1509151062
Directory /workspace/17.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/17.rom_ctrl_smoke.445818665
Short name T190
Test name
Test status
Simulation time 26808204213 ps
CPU time 66.99 seconds
Started Mar 17 01:47:06 PM PDT 24
Finished Mar 17 01:48:13 PM PDT 24
Peak memory 216952 kb
Host smart-f3c582a7-7ce4-4d75-8735-e827eb7bcee7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=445818665 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_smoke.445818665
Directory /workspace/17.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/17.rom_ctrl_stress_all.1714312354
Short name T304
Test name
Test status
Simulation time 3614804110 ps
CPU time 47.79 seconds
Started Mar 17 01:47:16 PM PDT 24
Finished Mar 17 01:48:04 PM PDT 24
Peak memory 219216 kb
Host smart-1c261007-f718-4de5-9b9c-56e435ad0293
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1714312354 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 17.rom_ctrl_stress_all.1714312354
Directory /workspace/17.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/17.rom_ctrl_stress_all.1750950040
Short name T611
Test name
Test status
Simulation time 365466335 ps
CPU time 23.5 seconds
Started Mar 17 02:40:13 PM PDT 24
Finished Mar 17 02:40:36 PM PDT 24
Peak memory 215564 kb
Host smart-6e9a6dff-ca4a-4aa7-a353-cfae4e6d94c7
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1750950040 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 17.rom_ctrl_stress_all.1750950040
Directory /workspace/17.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/17.rom_ctrl_stress_all_with_rand_reset.2202474847
Short name T469
Test name
Test status
Simulation time 27724004798 ps
CPU time 65.16 seconds
Started Mar 17 01:47:11 PM PDT 24
Finished Mar 17 01:48:17 PM PDT 24
Peak memory 220276 kb
Host smart-6d0f2894-fd81-4e02-bd23-0933aa07d80d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2202474847 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_stress_all_with_rand_reset.2202474847
Directory /workspace/17.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/18.rom_ctrl_alert_test.2312204902
Short name T172
Test name
Test status
Simulation time 14455123312 ps
CPU time 23.28 seconds
Started Mar 17 01:47:13 PM PDT 24
Finished Mar 17 01:47:36 PM PDT 24
Peak memory 211820 kb
Host smart-1dfda71b-888e-41d2-a92a-4f57e18db816
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2312204902 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_alert_test.2312204902
Directory /workspace/18.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/18.rom_ctrl_alert_test.3020226095
Short name T330
Test name
Test status
Simulation time 339274437 ps
CPU time 8.16 seconds
Started Mar 17 02:40:11 PM PDT 24
Finished Mar 17 02:40:19 PM PDT 24
Peak memory 211216 kb
Host smart-01e09cc1-59b2-401d-b9ea-9877ba477868
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3020226095 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_alert_test.3020226095
Directory /workspace/18.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/18.rom_ctrl_corrupt_sig_fatal_chk.1330603313
Short name T428
Test name
Test status
Simulation time 122847027829 ps
CPU time 632.18 seconds
Started Mar 17 01:47:17 PM PDT 24
Finished Mar 17 01:57:49 PM PDT 24
Peak memory 237264 kb
Host smart-20cd3881-5c80-4a37-9f5e-cdedb39e9ed9
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1330603313 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_
corrupt_sig_fatal_chk.1330603313
Directory /workspace/18.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/18.rom_ctrl_corrupt_sig_fatal_chk.1886083112
Short name T357
Test name
Test status
Simulation time 9538096810 ps
CPU time 181.16 seconds
Started Mar 17 02:40:11 PM PDT 24
Finished Mar 17 02:43:12 PM PDT 24
Peak memory 240184 kb
Host smart-58cf5114-b5f1-4334-a508-58ebbfb1a1e6
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1886083112 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_
corrupt_sig_fatal_chk.1886083112
Directory /workspace/18.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/18.rom_ctrl_kmac_err_chk.1627703284
Short name T274
Test name
Test status
Simulation time 7136377264 ps
CPU time 35.41 seconds
Started Mar 17 01:47:03 PM PDT 24
Finished Mar 17 01:47:39 PM PDT 24
Peak memory 215068 kb
Host smart-a11f0d31-67b3-434a-ba2f-2ba709bcbd2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1627703284 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_kmac_err_chk.1627703284
Directory /workspace/18.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/18.rom_ctrl_kmac_err_chk.754051623
Short name T366
Test name
Test status
Simulation time 346133091 ps
CPU time 19.65 seconds
Started Mar 17 02:40:10 PM PDT 24
Finished Mar 17 02:40:29 PM PDT 24
Peak memory 214504 kb
Host smart-5b76ed35-8bd1-4054-9e50-c0ef3d72720e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=754051623 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_kmac_err_chk.754051623
Directory /workspace/18.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/18.rom_ctrl_max_throughput_chk.1656907821
Short name T572
Test name
Test status
Simulation time 3790290168 ps
CPU time 22.15 seconds
Started Mar 17 02:40:11 PM PDT 24
Finished Mar 17 02:40:33 PM PDT 24
Peak memory 211296 kb
Host smart-078cf996-7383-4d6c-9f04-2e34db9b42d4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1656907821 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_max_throughput_chk.1656907821
Directory /workspace/18.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/18.rom_ctrl_max_throughput_chk.570167422
Short name T669
Test name
Test status
Simulation time 177978009 ps
CPU time 10.32 seconds
Started Mar 17 01:47:11 PM PDT 24
Finished Mar 17 01:47:22 PM PDT 24
Peak memory 212172 kb
Host smart-f0386503-822b-46e8-a3e9-2d9a671a0f85
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=570167422 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_max_throughput_chk.570167422
Directory /workspace/18.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/18.rom_ctrl_smoke.1783523096
Short name T578
Test name
Test status
Simulation time 8914896512 ps
CPU time 45.6 seconds
Started Mar 17 01:47:15 PM PDT 24
Finished Mar 17 01:48:01 PM PDT 24
Peak memory 218004 kb
Host smart-1bea3b64-99f4-4d8d-9841-2ff4a656e690
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1783523096 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_smoke.1783523096
Directory /workspace/18.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/18.rom_ctrl_smoke.3454074791
Short name T287
Test name
Test status
Simulation time 8780493310 ps
CPU time 69.96 seconds
Started Mar 17 02:40:11 PM PDT 24
Finished Mar 17 02:41:21 PM PDT 24
Peak memory 216584 kb
Host smart-5aa757a1-3307-49ee-b46a-175150679bb2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3454074791 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_smoke.3454074791
Directory /workspace/18.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/18.rom_ctrl_stress_all.2827369526
Short name T433
Test name
Test status
Simulation time 188697130 ps
CPU time 17.25 seconds
Started Mar 17 01:47:14 PM PDT 24
Finished Mar 17 01:47:31 PM PDT 24
Peak memory 211156 kb
Host smart-9fcb07d1-b53f-4437-9fa8-98045f3f4f18
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2827369526 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 18.rom_ctrl_stress_all.2827369526
Directory /workspace/18.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/19.rom_ctrl_alert_test.2007758450
Short name T283
Test name
Test status
Simulation time 3092388073 ps
CPU time 13.91 seconds
Started Mar 17 01:47:08 PM PDT 24
Finished Mar 17 01:47:22 PM PDT 24
Peak memory 211264 kb
Host smart-9937d52e-96cd-4b46-968f-de488db79b5b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2007758450 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_alert_test.2007758450
Directory /workspace/19.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/19.rom_ctrl_alert_test.98121960
Short name T601
Test name
Test status
Simulation time 194592640 ps
CPU time 8.34 seconds
Started Mar 17 02:40:15 PM PDT 24
Finished Mar 17 02:40:24 PM PDT 24
Peak memory 211184 kb
Host smart-588bebba-e518-4e72-86ae-c53623df4a15
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=98121960 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_alert_test.98121960
Directory /workspace/19.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/19.rom_ctrl_corrupt_sig_fatal_chk.3588494219
Short name T401
Test name
Test status
Simulation time 150191495552 ps
CPU time 480.04 seconds
Started Mar 17 01:47:13 PM PDT 24
Finished Mar 17 01:55:13 PM PDT 24
Peak memory 239464 kb
Host smart-c8ffb9f5-94b4-4de9-831d-993148c92876
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3588494219 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_
corrupt_sig_fatal_chk.3588494219
Directory /workspace/19.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/19.rom_ctrl_corrupt_sig_fatal_chk.837885909
Short name T511
Test name
Test status
Simulation time 60844156606 ps
CPU time 702.48 seconds
Started Mar 17 02:40:18 PM PDT 24
Finished Mar 17 02:52:01 PM PDT 24
Peak memory 216964 kb
Host smart-9041d4ca-d7b4-449f-82ac-755d808d30c6
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=837885909 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_c
orrupt_sig_fatal_chk.837885909
Directory /workspace/19.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/19.rom_ctrl_kmac_err_chk.1727237803
Short name T279
Test name
Test status
Simulation time 338973172 ps
CPU time 19.8 seconds
Started Mar 17 02:40:17 PM PDT 24
Finished Mar 17 02:40:37 PM PDT 24
Peak memory 214588 kb
Host smart-e2999e98-76fe-45a7-a4a6-150964090402
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1727237803 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_kmac_err_chk.1727237803
Directory /workspace/19.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/19.rom_ctrl_kmac_err_chk.3112807713
Short name T668
Test name
Test status
Simulation time 35518952293 ps
CPU time 67.51 seconds
Started Mar 17 01:47:17 PM PDT 24
Finished Mar 17 01:48:25 PM PDT 24
Peak memory 215304 kb
Host smart-e1c0fb7d-35bd-4c90-8b1b-5a392bd73935
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3112807713 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_kmac_err_chk.3112807713
Directory /workspace/19.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/19.rom_ctrl_max_throughput_chk.3599924538
Short name T628
Test name
Test status
Simulation time 186664507 ps
CPU time 10.58 seconds
Started Mar 17 01:47:18 PM PDT 24
Finished Mar 17 01:47:28 PM PDT 24
Peak memory 212336 kb
Host smart-72c0d2c3-02aa-4b3f-b6db-59479a35ff75
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3599924538 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_max_throughput_chk.3599924538
Directory /workspace/19.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/19.rom_ctrl_max_throughput_chk.4255997638
Short name T242
Test name
Test status
Simulation time 822331475 ps
CPU time 10.37 seconds
Started Mar 17 02:40:10 PM PDT 24
Finished Mar 17 02:40:21 PM PDT 24
Peak memory 212284 kb
Host smart-c0fff58e-0faa-46b6-9596-a0a0ebc5aaa4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4255997638 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_max_throughput_chk.4255997638
Directory /workspace/19.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/19.rom_ctrl_smoke.1732110189
Short name T164
Test name
Test status
Simulation time 9582492088 ps
CPU time 47.09 seconds
Started Mar 17 02:40:16 PM PDT 24
Finished Mar 17 02:41:03 PM PDT 24
Peak memory 214512 kb
Host smart-17512dd8-e30d-4817-9fd8-ae1fcb2047e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1732110189 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_smoke.1732110189
Directory /workspace/19.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/19.rom_ctrl_smoke.3632434453
Short name T285
Test name
Test status
Simulation time 6450820429 ps
CPU time 25.58 seconds
Started Mar 17 01:47:13 PM PDT 24
Finished Mar 17 01:47:39 PM PDT 24
Peak memory 217928 kb
Host smart-af480219-9911-4743-9468-cebc433dab55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3632434453 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_smoke.3632434453
Directory /workspace/19.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/19.rom_ctrl_stress_all.3891561783
Short name T569
Test name
Test status
Simulation time 2952605671 ps
CPU time 39.09 seconds
Started Mar 17 01:47:15 PM PDT 24
Finished Mar 17 01:47:54 PM PDT 24
Peak memory 212220 kb
Host smart-55ca2e9c-0dd4-4fb1-9e66-e09260376523
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3891561783 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 19.rom_ctrl_stress_all.3891561783
Directory /workspace/19.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/19.rom_ctrl_stress_all.4173223659
Short name T351
Test name
Test status
Simulation time 10059031657 ps
CPU time 53.41 seconds
Started Mar 17 02:40:16 PM PDT 24
Finished Mar 17 02:41:09 PM PDT 24
Peak memory 217740 kb
Host smart-829f31ed-e7bc-4b43-9996-0eeceaafebe2
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4173223659 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 19.rom_ctrl_stress_all.4173223659
Directory /workspace/19.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/2.rom_ctrl_alert_test.1414547033
Short name T437
Test name
Test status
Simulation time 5765902635 ps
CPU time 25.09 seconds
Started Mar 17 01:46:51 PM PDT 24
Finished Mar 17 01:47:17 PM PDT 24
Peak memory 211256 kb
Host smart-bc1580b0-706c-412e-851c-8d858a6082af
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1414547033 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_alert_test.1414547033
Directory /workspace/2.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/2.rom_ctrl_alert_test.844781740
Short name T134
Test name
Test status
Simulation time 3589804904 ps
CPU time 24.94 seconds
Started Mar 17 02:39:59 PM PDT 24
Finished Mar 17 02:40:24 PM PDT 24
Peak memory 211840 kb
Host smart-e73ab5f2-f954-48f9-a571-fd456e025fe0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=844781740 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_alert_test.844781740
Directory /workspace/2.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/2.rom_ctrl_corrupt_sig_fatal_chk.1438701708
Short name T413
Test name
Test status
Simulation time 8267903309 ps
CPU time 138.54 seconds
Started Mar 17 01:46:41 PM PDT 24
Finished Mar 17 01:49:01 PM PDT 24
Peak memory 240384 kb
Host smart-73c0dd8a-d272-43a8-903d-595dbfd03898
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1438701708 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_c
orrupt_sig_fatal_chk.1438701708
Directory /workspace/2.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/2.rom_ctrl_corrupt_sig_fatal_chk.1493340031
Short name T196
Test name
Test status
Simulation time 66118278123 ps
CPU time 593.47 seconds
Started Mar 17 02:39:59 PM PDT 24
Finished Mar 17 02:49:53 PM PDT 24
Peak memory 216448 kb
Host smart-3ff56eff-55e1-43a3-8ff3-41681bf3f482
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1493340031 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_c
orrupt_sig_fatal_chk.1493340031
Directory /workspace/2.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/2.rom_ctrl_kmac_err_chk.1408768515
Short name T220
Test name
Test status
Simulation time 15408767892 ps
CPU time 65.58 seconds
Started Mar 17 01:46:43 PM PDT 24
Finished Mar 17 01:47:50 PM PDT 24
Peak memory 214888 kb
Host smart-ee6675d0-ed46-4f8b-8b9a-d18ae03bf4ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1408768515 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_kmac_err_chk.1408768515
Directory /workspace/2.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/2.rom_ctrl_kmac_err_chk.2513219371
Short name T411
Test name
Test status
Simulation time 8586538648 ps
CPU time 33.91 seconds
Started Mar 17 02:39:59 PM PDT 24
Finished Mar 17 02:40:34 PM PDT 24
Peak memory 214960 kb
Host smart-79667341-1765-44ee-b638-4b05c3e4b619
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2513219371 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_kmac_err_chk.2513219371
Directory /workspace/2.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/2.rom_ctrl_max_throughput_chk.1751985649
Short name T231
Test name
Test status
Simulation time 684579349 ps
CPU time 10.06 seconds
Started Mar 17 01:46:37 PM PDT 24
Finished Mar 17 01:46:48 PM PDT 24
Peak memory 211160 kb
Host smart-8eeced89-daad-407d-a786-5d3e0250ffd0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1751985649 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_max_throughput_chk.1751985649
Directory /workspace/2.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/2.rom_ctrl_max_throughput_chk.2243654221
Short name T254
Test name
Test status
Simulation time 11542955558 ps
CPU time 28.31 seconds
Started Mar 17 02:39:59 PM PDT 24
Finished Mar 17 02:40:27 PM PDT 24
Peak memory 212748 kb
Host smart-942c4c3a-e4c6-4f46-a726-1a5823519018
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2243654221 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_max_throughput_chk.2243654221
Directory /workspace/2.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/2.rom_ctrl_sec_cm.2326218915
Short name T44
Test name
Test status
Simulation time 3539554973 ps
CPU time 136.81 seconds
Started Mar 17 01:46:55 PM PDT 24
Finished Mar 17 01:49:12 PM PDT 24
Peak memory 236452 kb
Host smart-fecbf0bc-81f6-445e-b89f-3cd4b29327a2
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2326218915 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_sec_cm.2326218915
Directory /workspace/2.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/2.rom_ctrl_sec_cm.3686251518
Short name T36
Test name
Test status
Simulation time 381444915 ps
CPU time 122.63 seconds
Started Mar 17 02:40:03 PM PDT 24
Finished Mar 17 02:42:06 PM PDT 24
Peak memory 236360 kb
Host smart-9e191654-6de7-4f6b-a86e-7976bc90747b
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3686251518 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_sec_cm.3686251518
Directory /workspace/2.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/2.rom_ctrl_smoke.1647905731
Short name T169
Test name
Test status
Simulation time 344957064 ps
CPU time 19.81 seconds
Started Mar 17 01:46:43 PM PDT 24
Finished Mar 17 01:47:04 PM PDT 24
Peak memory 216512 kb
Host smart-ca33ab28-bc0f-43d6-9b73-52200e828bda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1647905731 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_smoke.1647905731
Directory /workspace/2.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/2.rom_ctrl_smoke.3107157045
Short name T654
Test name
Test status
Simulation time 18688323421 ps
CPU time 43.64 seconds
Started Mar 17 02:39:56 PM PDT 24
Finished Mar 17 02:40:40 PM PDT 24
Peak memory 217148 kb
Host smart-54f4766f-04a4-4adf-b49b-853acf1ddf03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3107157045 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_smoke.3107157045
Directory /workspace/2.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/2.rom_ctrl_stress_all.218322960
Short name T452
Test name
Test status
Simulation time 1790905410 ps
CPU time 24.25 seconds
Started Mar 17 01:46:42 PM PDT 24
Finished Mar 17 01:47:09 PM PDT 24
Peak memory 212448 kb
Host smart-428b27a9-b11e-4414-a4b0-272c0223a775
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=218322960 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 2.rom_ctrl_stress_all.218322960
Directory /workspace/2.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/2.rom_ctrl_stress_all.2794109927
Short name T580
Test name
Test status
Simulation time 24160142766 ps
CPU time 212.18 seconds
Started Mar 17 02:40:02 PM PDT 24
Finished Mar 17 02:43:35 PM PDT 24
Peak memory 222312 kb
Host smart-8ad4f66d-4bce-4ba2-91b8-e2751fa61763
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2794109927 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 2.rom_ctrl_stress_all.2794109927
Directory /workspace/2.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/2.rom_ctrl_stress_all_with_rand_reset.3192867092
Short name T548
Test name
Test status
Simulation time 94037302937 ps
CPU time 3481.88 seconds
Started Mar 17 01:46:47 PM PDT 24
Finished Mar 17 02:44:50 PM PDT 24
Peak memory 252224 kb
Host smart-911a039f-9f12-44ca-a45e-497f83392ebe
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3192867092 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_stress_all_with_rand_reset.3192867092
Directory /workspace/2.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.rom_ctrl_alert_test.1860335950
Short name T58
Test name
Test status
Simulation time 8277223008 ps
CPU time 20.85 seconds
Started Mar 17 02:40:17 PM PDT 24
Finished Mar 17 02:40:38 PM PDT 24
Peak memory 211276 kb
Host smart-e81ad4d5-4428-4eb1-9b86-8b3ddfe20bfe
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1860335950 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_alert_test.1860335950
Directory /workspace/20.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/20.rom_ctrl_alert_test.782424389
Short name T410
Test name
Test status
Simulation time 3296415778 ps
CPU time 27.59 seconds
Started Mar 17 01:47:14 PM PDT 24
Finished Mar 17 01:47:42 PM PDT 24
Peak memory 211296 kb
Host smart-a382e8ab-0491-40ae-94be-8d6238249b10
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=782424389 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_alert_test.782424389
Directory /workspace/20.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/20.rom_ctrl_corrupt_sig_fatal_chk.1573919961
Short name T271
Test name
Test status
Simulation time 6302265640 ps
CPU time 168.75 seconds
Started Mar 17 02:40:15 PM PDT 24
Finished Mar 17 02:43:03 PM PDT 24
Peak memory 236520 kb
Host smart-97e9220c-dc51-443b-b34d-d6a6ec44fd7f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1573919961 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_
corrupt_sig_fatal_chk.1573919961
Directory /workspace/20.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/20.rom_ctrl_corrupt_sig_fatal_chk.344953266
Short name T551
Test name
Test status
Simulation time 406545490538 ps
CPU time 765.87 seconds
Started Mar 17 01:47:10 PM PDT 24
Finished Mar 17 01:59:56 PM PDT 24
Peak memory 216644 kb
Host smart-c0d25893-6fbb-40e6-aa2a-ba0bb262ff2e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=344953266 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_c
orrupt_sig_fatal_chk.344953266
Directory /workspace/20.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/20.rom_ctrl_kmac_err_chk.1288290708
Short name T641
Test name
Test status
Simulation time 1226913032 ps
CPU time 28.01 seconds
Started Mar 17 02:40:17 PM PDT 24
Finished Mar 17 02:40:45 PM PDT 24
Peak memory 214520 kb
Host smart-ae5b3aa0-c1b7-4b8c-b21f-b1d771b5157d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1288290708 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_kmac_err_chk.1288290708
Directory /workspace/20.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/20.rom_ctrl_kmac_err_chk.3566594086
Short name T213
Test name
Test status
Simulation time 33484319841 ps
CPU time 70.41 seconds
Started Mar 17 01:47:21 PM PDT 24
Finished Mar 17 01:48:31 PM PDT 24
Peak memory 212804 kb
Host smart-a8f3a119-4fbb-483c-aacb-b10f701220a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3566594086 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_kmac_err_chk.3566594086
Directory /workspace/20.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/20.rom_ctrl_max_throughput_chk.1349888078
Short name T653
Test name
Test status
Simulation time 2148829183 ps
CPU time 23.35 seconds
Started Mar 17 01:47:15 PM PDT 24
Finished Mar 17 01:47:38 PM PDT 24
Peak memory 211144 kb
Host smart-65cb4fdc-1b04-47a1-ab35-12a22f2ac17f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1349888078 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_max_throughput_chk.1349888078
Directory /workspace/20.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/20.rom_ctrl_max_throughput_chk.1535037623
Short name T111
Test name
Test status
Simulation time 183145454 ps
CPU time 10.48 seconds
Started Mar 17 02:40:14 PM PDT 24
Finished Mar 17 02:40:24 PM PDT 24
Peak memory 212192 kb
Host smart-808b4973-a6ea-48a5-9beb-7357c0823da5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1535037623 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_max_throughput_chk.1535037623
Directory /workspace/20.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/20.rom_ctrl_smoke.2887800903
Short name T478
Test name
Test status
Simulation time 18172735909 ps
CPU time 60.82 seconds
Started Mar 17 01:47:12 PM PDT 24
Finished Mar 17 01:48:13 PM PDT 24
Peak memory 217304 kb
Host smart-803f7e63-0ff6-4f34-b435-3dc9a9b2082b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2887800903 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_smoke.2887800903
Directory /workspace/20.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/20.rom_ctrl_smoke.2899723902
Short name T502
Test name
Test status
Simulation time 7884418815 ps
CPU time 75.89 seconds
Started Mar 17 02:40:18 PM PDT 24
Finished Mar 17 02:41:34 PM PDT 24
Peak memory 217708 kb
Host smart-e54f113e-f7d1-48fe-8426-ce319c1f11a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2899723902 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_smoke.2899723902
Directory /workspace/20.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/20.rom_ctrl_stress_all.2809546116
Short name T420
Test name
Test status
Simulation time 47172670363 ps
CPU time 147.86 seconds
Started Mar 17 02:40:15 PM PDT 24
Finished Mar 17 02:42:43 PM PDT 24
Peak memory 222244 kb
Host smart-0e2a3207-98df-410c-bee8-418097b5d144
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2809546116 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 20.rom_ctrl_stress_all.2809546116
Directory /workspace/20.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/20.rom_ctrl_stress_all.49255253
Short name T490
Test name
Test status
Simulation time 533638599 ps
CPU time 33.79 seconds
Started Mar 17 01:47:16 PM PDT 24
Finished Mar 17 01:47:50 PM PDT 24
Peak memory 219184 kb
Host smart-19bb6220-7a40-48ce-b3a4-62af4a16193c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49255253 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +U
VM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n
ame 20.rom_ctrl_stress_all.49255253
Directory /workspace/20.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/21.rom_ctrl_alert_test.1834961983
Short name T395
Test name
Test status
Simulation time 174450762 ps
CPU time 8.13 seconds
Started Mar 17 02:40:17 PM PDT 24
Finished Mar 17 02:40:25 PM PDT 24
Peak memory 211264 kb
Host smart-ae05e678-7e98-4aed-8af7-ae5e6ac69f47
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1834961983 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_alert_test.1834961983
Directory /workspace/21.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/21.rom_ctrl_alert_test.687873696
Short name T142
Test name
Test status
Simulation time 1982532631 ps
CPU time 20.53 seconds
Started Mar 17 01:47:23 PM PDT 24
Finished Mar 17 01:47:43 PM PDT 24
Peak memory 211724 kb
Host smart-681f2166-2f5a-4ecb-b70e-d7bd323ed866
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=687873696 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_alert_test.687873696
Directory /workspace/21.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/21.rom_ctrl_corrupt_sig_fatal_chk.2105386507
Short name T240
Test name
Test status
Simulation time 6272279827 ps
CPU time 304.52 seconds
Started Mar 17 01:47:15 PM PDT 24
Finished Mar 17 01:52:20 PM PDT 24
Peak memory 226416 kb
Host smart-58dac8a0-6111-4406-974f-bd428063b194
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2105386507 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_
corrupt_sig_fatal_chk.2105386507
Directory /workspace/21.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/21.rom_ctrl_corrupt_sig_fatal_chk.4140034993
Short name T319
Test name
Test status
Simulation time 392199463033 ps
CPU time 375.04 seconds
Started Mar 17 02:40:15 PM PDT 24
Finished Mar 17 02:46:30 PM PDT 24
Peak memory 225480 kb
Host smart-ab90085a-2b56-41b7-8263-8ae5797f20ff
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4140034993 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_
corrupt_sig_fatal_chk.4140034993
Directory /workspace/21.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/21.rom_ctrl_kmac_err_chk.536093504
Short name T399
Test name
Test status
Simulation time 8568465952 ps
CPU time 65.96 seconds
Started Mar 17 02:40:15 PM PDT 24
Finished Mar 17 02:41:21 PM PDT 24
Peak memory 215256 kb
Host smart-4a2a92f7-7467-4b53-8749-4e44daa5d713
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=536093504 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_kmac_err_chk.536093504
Directory /workspace/21.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/21.rom_ctrl_kmac_err_chk.975338831
Short name T180
Test name
Test status
Simulation time 8723018295 ps
CPU time 45.66 seconds
Started Mar 17 01:47:16 PM PDT 24
Finished Mar 17 01:48:02 PM PDT 24
Peak memory 214832 kb
Host smart-bf0b24d4-9c6f-45bd-8c60-d337e1bec7c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=975338831 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_kmac_err_chk.975338831
Directory /workspace/21.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/21.rom_ctrl_max_throughput_chk.1909079435
Short name T645
Test name
Test status
Simulation time 3048433440 ps
CPU time 26.43 seconds
Started Mar 17 01:47:14 PM PDT 24
Finished Mar 17 01:47:40 PM PDT 24
Peak memory 211548 kb
Host smart-70ffb3cd-bb85-4878-8ea1-2a25b54b61a3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1909079435 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_max_throughput_chk.1909079435
Directory /workspace/21.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/21.rom_ctrl_max_throughput_chk.3823076881
Short name T421
Test name
Test status
Simulation time 8920141181 ps
CPU time 24 seconds
Started Mar 17 02:40:13 PM PDT 24
Finished Mar 17 02:40:37 PM PDT 24
Peak memory 212852 kb
Host smart-2bc6c9f3-2559-46ef-b2eb-1c7601123735
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3823076881 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_max_throughput_chk.3823076881
Directory /workspace/21.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/21.rom_ctrl_smoke.30621298
Short name T487
Test name
Test status
Simulation time 14357372116 ps
CPU time 40.27 seconds
Started Mar 17 02:40:13 PM PDT 24
Finished Mar 17 02:40:53 PM PDT 24
Peak memory 217600 kb
Host smart-f8b8c8c7-9b8c-4b93-a241-9cd448d73224
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=30621298 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_smoke.30621298
Directory /workspace/21.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/21.rom_ctrl_smoke.3375822014
Short name T326
Test name
Test status
Simulation time 2027549041 ps
CPU time 24.15 seconds
Started Mar 17 01:47:13 PM PDT 24
Finished Mar 17 01:47:38 PM PDT 24
Peak memory 216348 kb
Host smart-55bf8109-c38d-4335-892b-1e246f163825
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3375822014 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_smoke.3375822014
Directory /workspace/21.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/21.rom_ctrl_stress_all.116836343
Short name T389
Test name
Test status
Simulation time 32942119691 ps
CPU time 94.77 seconds
Started Mar 17 02:40:18 PM PDT 24
Finished Mar 17 02:41:53 PM PDT 24
Peak memory 221480 kb
Host smart-4745baf6-d4c9-47e7-a793-512d91a3f15f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=116836343 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 21.rom_ctrl_stress_all.116836343
Directory /workspace/21.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/21.rom_ctrl_stress_all.1413555479
Short name T204
Test name
Test status
Simulation time 517905452 ps
CPU time 17.13 seconds
Started Mar 17 01:47:18 PM PDT 24
Finished Mar 17 01:47:36 PM PDT 24
Peak memory 211360 kb
Host smart-1beb3483-c1d2-4e44-892c-28fb7a694a9e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1413555479 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 21.rom_ctrl_stress_all.1413555479
Directory /workspace/21.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/21.rom_ctrl_stress_all_with_rand_reset.661826559
Short name T50
Test name
Test status
Simulation time 52201602036 ps
CPU time 979.84 seconds
Started Mar 17 02:40:17 PM PDT 24
Finished Mar 17 02:56:37 PM PDT 24
Peak memory 235784 kb
Host smart-80308a49-0480-4f22-a865-c188c30a51a1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=661826559 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_stress_all_with_rand_reset.661826559
Directory /workspace/21.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/22.rom_ctrl_alert_test.2239320719
Short name T177
Test name
Test status
Simulation time 3952380330 ps
CPU time 29.47 seconds
Started Mar 17 01:47:16 PM PDT 24
Finished Mar 17 01:47:46 PM PDT 24
Peak memory 211676 kb
Host smart-0a5c5659-9001-4527-8d19-870a2900fb71
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2239320719 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_alert_test.2239320719
Directory /workspace/22.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/22.rom_ctrl_alert_test.2392461287
Short name T613
Test name
Test status
Simulation time 12487048537 ps
CPU time 28.66 seconds
Started Mar 17 02:40:24 PM PDT 24
Finished Mar 17 02:40:53 PM PDT 24
Peak memory 212216 kb
Host smart-b66f25a4-3cd0-4d60-87e5-d5d60c8d305c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2392461287 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_alert_test.2392461287
Directory /workspace/22.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/22.rom_ctrl_corrupt_sig_fatal_chk.3096706681
Short name T543
Test name
Test status
Simulation time 344498148057 ps
CPU time 1006.54 seconds
Started Mar 17 02:40:13 PM PDT 24
Finished Mar 17 02:57:00 PM PDT 24
Peak memory 237184 kb
Host smart-247cea58-9c37-496c-a44d-f1af00224547
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3096706681 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_
corrupt_sig_fatal_chk.3096706681
Directory /workspace/22.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/22.rom_ctrl_corrupt_sig_fatal_chk.915968550
Short name T309
Test name
Test status
Simulation time 251724944939 ps
CPU time 737.8 seconds
Started Mar 17 01:47:31 PM PDT 24
Finished Mar 17 01:59:50 PM PDT 24
Peak memory 237344 kb
Host smart-19d21447-4601-49d1-ab62-0eaa7547228f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=915968550 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_c
orrupt_sig_fatal_chk.915968550
Directory /workspace/22.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/22.rom_ctrl_kmac_err_chk.3668986049
Short name T481
Test name
Test status
Simulation time 17809047660 ps
CPU time 45.16 seconds
Started Mar 17 02:40:15 PM PDT 24
Finished Mar 17 02:41:00 PM PDT 24
Peak memory 214056 kb
Host smart-cb4f1918-3ef1-44ce-87ac-691ddd5ec7b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3668986049 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_kmac_err_chk.3668986049
Directory /workspace/22.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/22.rom_ctrl_kmac_err_chk.4041435223
Short name T666
Test name
Test status
Simulation time 4412523133 ps
CPU time 27.32 seconds
Started Mar 17 01:47:16 PM PDT 24
Finished Mar 17 01:47:43 PM PDT 24
Peak memory 215024 kb
Host smart-f2534ab4-ef94-4d70-ac2a-e3bc534778dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4041435223 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_kmac_err_chk.4041435223
Directory /workspace/22.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/22.rom_ctrl_max_throughput_chk.2839336116
Short name T486
Test name
Test status
Simulation time 2775730611 ps
CPU time 25.58 seconds
Started Mar 17 01:47:14 PM PDT 24
Finished Mar 17 01:47:40 PM PDT 24
Peak memory 212300 kb
Host smart-d3a03b2d-54cd-4561-8db4-b8e9a6c71263
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2839336116 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_max_throughput_chk.2839336116
Directory /workspace/22.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/22.rom_ctrl_max_throughput_chk.710489820
Short name T307
Test name
Test status
Simulation time 5184064029 ps
CPU time 24.67 seconds
Started Mar 17 02:40:18 PM PDT 24
Finished Mar 17 02:40:43 PM PDT 24
Peak memory 211288 kb
Host smart-3159871d-8943-438c-8a1c-43f7912d00b2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=710489820 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_max_throughput_chk.710489820
Directory /workspace/22.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/22.rom_ctrl_smoke.490483312
Short name T246
Test name
Test status
Simulation time 26352425899 ps
CPU time 64.18 seconds
Started Mar 17 02:40:17 PM PDT 24
Finished Mar 17 02:41:21 PM PDT 24
Peak memory 215580 kb
Host smart-beb2f05a-d258-4ebc-9aae-56df67ef0f0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=490483312 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_smoke.490483312
Directory /workspace/22.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/22.rom_ctrl_smoke.636783657
Short name T414
Test name
Test status
Simulation time 8624039062 ps
CPU time 86.17 seconds
Started Mar 17 01:47:16 PM PDT 24
Finished Mar 17 01:48:42 PM PDT 24
Peak memory 215268 kb
Host smart-e8d8ca3e-c8d6-4a5e-9237-ee15de90ac60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=636783657 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_smoke.636783657
Directory /workspace/22.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/22.rom_ctrl_stress_all.1961552802
Short name T205
Test name
Test status
Simulation time 1855481194 ps
CPU time 50.19 seconds
Started Mar 17 01:47:16 PM PDT 24
Finished Mar 17 01:48:06 PM PDT 24
Peak memory 219256 kb
Host smart-73bdfde3-1f0c-4fbf-b7d3-c5bbf82da83b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1961552802 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 22.rom_ctrl_stress_all.1961552802
Directory /workspace/22.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/22.rom_ctrl_stress_all.235270320
Short name T338
Test name
Test status
Simulation time 16084871046 ps
CPU time 32.9 seconds
Started Mar 17 02:40:17 PM PDT 24
Finished Mar 17 02:40:50 PM PDT 24
Peak memory 213920 kb
Host smart-29cc78c0-f778-4b01-9d91-f6a6240d090b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=235270320 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 22.rom_ctrl_stress_all.235270320
Directory /workspace/22.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/23.rom_ctrl_alert_test.2355532006
Short name T291
Test name
Test status
Simulation time 6832361547 ps
CPU time 28.84 seconds
Started Mar 17 02:40:25 PM PDT 24
Finished Mar 17 02:40:54 PM PDT 24
Peak memory 212144 kb
Host smart-5e69d86e-efef-45bd-869f-0c0e566fdb77
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2355532006 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_alert_test.2355532006
Directory /workspace/23.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/23.rom_ctrl_alert_test.253075221
Short name T308
Test name
Test status
Simulation time 1660067254 ps
CPU time 10.72 seconds
Started Mar 17 01:47:16 PM PDT 24
Finished Mar 17 01:47:27 PM PDT 24
Peak memory 211252 kb
Host smart-cb2962e3-74da-4a31-881b-f4171293316f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=253075221 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_alert_test.253075221
Directory /workspace/23.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/23.rom_ctrl_corrupt_sig_fatal_chk.1975967046
Short name T456
Test name
Test status
Simulation time 86514494637 ps
CPU time 932.27 seconds
Started Mar 17 01:47:16 PM PDT 24
Finished Mar 17 02:02:48 PM PDT 24
Peak memory 240520 kb
Host smart-e6028eea-bf2f-4f7e-a0cd-15a9d11cb932
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1975967046 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_
corrupt_sig_fatal_chk.1975967046
Directory /workspace/23.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/23.rom_ctrl_corrupt_sig_fatal_chk.2197105140
Short name T208
Test name
Test status
Simulation time 140279382366 ps
CPU time 736.88 seconds
Started Mar 17 02:40:21 PM PDT 24
Finished Mar 17 02:52:38 PM PDT 24
Peak memory 217696 kb
Host smart-4156648b-cbad-45d3-b299-a2359b0efd5c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2197105140 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_
corrupt_sig_fatal_chk.2197105140
Directory /workspace/23.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/23.rom_ctrl_kmac_err_chk.1489223203
Short name T22
Test name
Test status
Simulation time 1319902243 ps
CPU time 19.37 seconds
Started Mar 17 02:40:24 PM PDT 24
Finished Mar 17 02:40:44 PM PDT 24
Peak memory 214664 kb
Host smart-85902324-8c44-4123-9f6d-1b607583fee3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1489223203 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_kmac_err_chk.1489223203
Directory /workspace/23.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/23.rom_ctrl_kmac_err_chk.3822009763
Short name T247
Test name
Test status
Simulation time 3277699014 ps
CPU time 25.43 seconds
Started Mar 17 01:47:17 PM PDT 24
Finished Mar 17 01:47:42 PM PDT 24
Peak memory 214552 kb
Host smart-6d29d91a-c20f-4389-b070-aa9c42b85abb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3822009763 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_kmac_err_chk.3822009763
Directory /workspace/23.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/23.rom_ctrl_max_throughput_chk.4095430059
Short name T564
Test name
Test status
Simulation time 1341691638 ps
CPU time 12.07 seconds
Started Mar 17 02:40:24 PM PDT 24
Finished Mar 17 02:40:36 PM PDT 24
Peak memory 211500 kb
Host smart-e566ffa7-0bbc-4b1c-8213-284298c8699c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4095430059 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_max_throughput_chk.4095430059
Directory /workspace/23.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/23.rom_ctrl_max_throughput_chk.495088901
Short name T276
Test name
Test status
Simulation time 4107729253 ps
CPU time 32.37 seconds
Started Mar 17 01:47:19 PM PDT 24
Finished Mar 17 01:47:51 PM PDT 24
Peak memory 212152 kb
Host smart-4fcf767b-67cc-406f-a092-274a08fb4672
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=495088901 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_max_throughput_chk.495088901
Directory /workspace/23.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/23.rom_ctrl_smoke.3383759098
Short name T390
Test name
Test status
Simulation time 26698332189 ps
CPU time 66.54 seconds
Started Mar 17 01:47:21 PM PDT 24
Finished Mar 17 01:48:27 PM PDT 24
Peak memory 216800 kb
Host smart-7b3a084f-8607-4ac0-8f4f-418d5e34807b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3383759098 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_smoke.3383759098
Directory /workspace/23.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/23.rom_ctrl_smoke.521904009
Short name T186
Test name
Test status
Simulation time 1369461532 ps
CPU time 20.08 seconds
Started Mar 17 02:40:21 PM PDT 24
Finished Mar 17 02:40:41 PM PDT 24
Peak memory 217540 kb
Host smart-ea2086a5-595d-46b6-be4a-0e9b08a7d17a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=521904009 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_smoke.521904009
Directory /workspace/23.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/23.rom_ctrl_stress_all.191051005
Short name T493
Test name
Test status
Simulation time 45404708983 ps
CPU time 143.89 seconds
Started Mar 17 02:40:23 PM PDT 24
Finished Mar 17 02:42:47 PM PDT 24
Peak memory 220924 kb
Host smart-68815b8e-0b6b-4007-aa87-72a09888e18e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=191051005 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 23.rom_ctrl_stress_all.191051005
Directory /workspace/23.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/23.rom_ctrl_stress_all.717928860
Short name T284
Test name
Test status
Simulation time 47131240675 ps
CPU time 95.36 seconds
Started Mar 17 01:47:17 PM PDT 24
Finished Mar 17 01:48:53 PM PDT 24
Peak memory 219228 kb
Host smart-43733303-b856-41cd-a917-c206984db3a0
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=717928860 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 23.rom_ctrl_stress_all.717928860
Directory /workspace/23.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/23.rom_ctrl_stress_all_with_rand_reset.2962508816
Short name T16
Test name
Test status
Simulation time 30604594198 ps
CPU time 1108.85 seconds
Started Mar 17 01:47:14 PM PDT 24
Finished Mar 17 02:05:43 PM PDT 24
Peak memory 232588 kb
Host smart-419a54cf-059e-41c1-924f-587bbd8e6e46
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2962508816 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_stress_all_with_rand_reset.2962508816
Directory /workspace/23.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/23.rom_ctrl_stress_all_with_rand_reset.925228892
Short name T15
Test name
Test status
Simulation time 271753856366 ps
CPU time 1768.65 seconds
Started Mar 17 02:40:22 PM PDT 24
Finished Mar 17 03:09:51 PM PDT 24
Peak memory 238184 kb
Host smart-c1740af1-ce54-41f3-b54c-5e15db90e490
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=925228892 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_stress_all_with_rand_reset.925228892
Directory /workspace/23.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/24.rom_ctrl_alert_test.2060880820
Short name T683
Test name
Test status
Simulation time 3686870361 ps
CPU time 17.43 seconds
Started Mar 17 01:47:21 PM PDT 24
Finished Mar 17 01:47:38 PM PDT 24
Peak memory 211244 kb
Host smart-d46e2c52-8676-494a-ad70-d84a28ab8d12
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2060880820 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_alert_test.2060880820
Directory /workspace/24.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/24.rom_ctrl_alert_test.3280193243
Short name T170
Test name
Test status
Simulation time 3988379785 ps
CPU time 31.25 seconds
Started Mar 17 02:40:22 PM PDT 24
Finished Mar 17 02:40:53 PM PDT 24
Peak memory 211904 kb
Host smart-a57c13c5-fd21-4242-90fe-a65b4021f761
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3280193243 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_alert_test.3280193243
Directory /workspace/24.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/24.rom_ctrl_corrupt_sig_fatal_chk.1165917745
Short name T206
Test name
Test status
Simulation time 366637326607 ps
CPU time 523.35 seconds
Started Mar 17 01:47:16 PM PDT 24
Finished Mar 17 01:56:00 PM PDT 24
Peak memory 240424 kb
Host smart-4d7799aa-8bb0-4550-b759-4eb74ca694bc
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1165917745 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_
corrupt_sig_fatal_chk.1165917745
Directory /workspace/24.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/24.rom_ctrl_corrupt_sig_fatal_chk.2929383468
Short name T34
Test name
Test status
Simulation time 172538429567 ps
CPU time 412.91 seconds
Started Mar 17 02:40:23 PM PDT 24
Finished Mar 17 02:47:17 PM PDT 24
Peak memory 215556 kb
Host smart-91664c34-22ca-4205-a79b-a2dcfb8ebbb0
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2929383468 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_
corrupt_sig_fatal_chk.2929383468
Directory /workspace/24.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/24.rom_ctrl_kmac_err_chk.4007486203
Short name T639
Test name
Test status
Simulation time 1384988158 ps
CPU time 28.14 seconds
Started Mar 17 01:47:15 PM PDT 24
Finished Mar 17 01:47:43 PM PDT 24
Peak memory 214552 kb
Host smart-e701f677-8c42-40c4-9724-6409fa85721d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4007486203 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_kmac_err_chk.4007486203
Directory /workspace/24.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/24.rom_ctrl_kmac_err_chk.4134151038
Short name T618
Test name
Test status
Simulation time 8039790900 ps
CPU time 43.41 seconds
Started Mar 17 02:40:23 PM PDT 24
Finished Mar 17 02:41:07 PM PDT 24
Peak memory 215228 kb
Host smart-5b674af2-50eb-4115-b691-88e229629976
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4134151038 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_kmac_err_chk.4134151038
Directory /workspace/24.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/24.rom_ctrl_max_throughput_chk.2525744212
Short name T211
Test name
Test status
Simulation time 77588527926 ps
CPU time 34.5 seconds
Started Mar 17 02:40:22 PM PDT 24
Finished Mar 17 02:40:56 PM PDT 24
Peak memory 211748 kb
Host smart-e4d4be56-0402-4e1d-80f3-2eafb9aea4e3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2525744212 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_max_throughput_chk.2525744212
Directory /workspace/24.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/24.rom_ctrl_max_throughput_chk.479340761
Short name T514
Test name
Test status
Simulation time 16351495110 ps
CPU time 32.14 seconds
Started Mar 17 01:47:18 PM PDT 24
Finished Mar 17 01:47:51 PM PDT 24
Peak memory 212636 kb
Host smart-a11e2c55-3308-4bb9-bb26-64e945090fd4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=479340761 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_max_throughput_chk.479340761
Directory /workspace/24.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/24.rom_ctrl_smoke.22023723
Short name T250
Test name
Test status
Simulation time 746989903 ps
CPU time 20.39 seconds
Started Mar 17 01:47:13 PM PDT 24
Finished Mar 17 01:47:34 PM PDT 24
Peak memory 216872 kb
Host smart-01a722e9-e209-4b9b-858b-b8f72c519ce5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=22023723 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_smoke.22023723
Directory /workspace/24.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/24.rom_ctrl_smoke.4109212170
Short name T534
Test name
Test status
Simulation time 32959119651 ps
CPU time 69.9 seconds
Started Mar 17 02:40:22 PM PDT 24
Finished Mar 17 02:41:32 PM PDT 24
Peak memory 217472 kb
Host smart-ae500c89-7a6a-4eb8-9e8e-b2265ca453bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4109212170 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_smoke.4109212170
Directory /workspace/24.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/24.rom_ctrl_stress_all.3074324526
Short name T472
Test name
Test status
Simulation time 1790035586 ps
CPU time 56.66 seconds
Started Mar 17 02:40:21 PM PDT 24
Finished Mar 17 02:41:17 PM PDT 24
Peak memory 219560 kb
Host smart-109c983e-d297-4782-8d8c-511faba54aa8
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3074324526 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 24.rom_ctrl_stress_all.3074324526
Directory /workspace/24.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/24.rom_ctrl_stress_all.4194929768
Short name T110
Test name
Test status
Simulation time 36081461838 ps
CPU time 73.63 seconds
Started Mar 17 01:47:21 PM PDT 24
Finished Mar 17 01:48:35 PM PDT 24
Peak memory 219252 kb
Host smart-dbc5ef6f-dc39-41e4-9878-f3f5110ccd98
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4194929768 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 24.rom_ctrl_stress_all.4194929768
Directory /workspace/24.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/25.rom_ctrl_alert_test.1481843090
Short name T236
Test name
Test status
Simulation time 1620721240 ps
CPU time 17.39 seconds
Started Mar 17 02:40:22 PM PDT 24
Finished Mar 17 02:40:39 PM PDT 24
Peak memory 211276 kb
Host smart-cdfa1892-d8b8-4bd6-ab3d-a413618fd91f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1481843090 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_alert_test.1481843090
Directory /workspace/25.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/25.rom_ctrl_alert_test.3450350802
Short name T648
Test name
Test status
Simulation time 1637669568 ps
CPU time 18.34 seconds
Started Mar 17 01:47:23 PM PDT 24
Finished Mar 17 01:47:41 PM PDT 24
Peak memory 211140 kb
Host smart-c51d9c63-6202-461c-b4e8-7d40cfb5f83e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3450350802 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_alert_test.3450350802
Directory /workspace/25.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/25.rom_ctrl_corrupt_sig_fatal_chk.1730565528
Short name T241
Test name
Test status
Simulation time 13239301229 ps
CPU time 220.76 seconds
Started Mar 17 01:47:16 PM PDT 24
Finished Mar 17 01:50:57 PM PDT 24
Peak memory 233428 kb
Host smart-7e9780fb-6529-4367-aa84-f66023a51d55
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1730565528 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_
corrupt_sig_fatal_chk.1730565528
Directory /workspace/25.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/25.rom_ctrl_corrupt_sig_fatal_chk.960228257
Short name T189
Test name
Test status
Simulation time 16433224468 ps
CPU time 336.64 seconds
Started Mar 17 02:40:23 PM PDT 24
Finished Mar 17 02:46:00 PM PDT 24
Peak memory 217348 kb
Host smart-8174c042-0e85-463d-84dd-a7af8ef570a9
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=960228257 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_c
orrupt_sig_fatal_chk.960228257
Directory /workspace/25.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/25.rom_ctrl_kmac_err_chk.1511484414
Short name T29
Test name
Test status
Simulation time 9478606350 ps
CPU time 47.72 seconds
Started Mar 17 02:40:24 PM PDT 24
Finished Mar 17 02:41:12 PM PDT 24
Peak memory 213948 kb
Host smart-d738f9ee-cb2b-4022-9d70-2a1041ffb098
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1511484414 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_kmac_err_chk.1511484414
Directory /workspace/25.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/25.rom_ctrl_kmac_err_chk.1702223320
Short name T629
Test name
Test status
Simulation time 15717344370 ps
CPU time 42.9 seconds
Started Mar 17 01:47:17 PM PDT 24
Finished Mar 17 01:48:00 PM PDT 24
Peak memory 214224 kb
Host smart-8e312f21-e7a4-4edf-a9f9-8dbd301c774d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1702223320 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_kmac_err_chk.1702223320
Directory /workspace/25.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/25.rom_ctrl_max_throughput_chk.2411049008
Short name T63
Test name
Test status
Simulation time 3102711226 ps
CPU time 28.56 seconds
Started Mar 17 01:47:20 PM PDT 24
Finished Mar 17 01:47:49 PM PDT 24
Peak memory 211268 kb
Host smart-2c4148ee-40bc-46c4-99b5-26babb1bb4e8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2411049008 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_max_throughput_chk.2411049008
Directory /workspace/25.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/25.rom_ctrl_max_throughput_chk.2440809640
Short name T482
Test name
Test status
Simulation time 3859555682 ps
CPU time 34.15 seconds
Started Mar 17 02:40:21 PM PDT 24
Finished Mar 17 02:40:55 PM PDT 24
Peak memory 211208 kb
Host smart-9807d126-3418-4adf-af9d-07e7bd3d82be
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2440809640 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_max_throughput_chk.2440809640
Directory /workspace/25.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/25.rom_ctrl_smoke.2616205474
Short name T453
Test name
Test status
Simulation time 18605081134 ps
CPU time 43.77 seconds
Started Mar 17 01:47:19 PM PDT 24
Finished Mar 17 01:48:03 PM PDT 24
Peak memory 217576 kb
Host smart-dfc9e579-7053-4389-a37f-287d6db9ed70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2616205474 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_smoke.2616205474
Directory /workspace/25.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/25.rom_ctrl_smoke.3166319130
Short name T595
Test name
Test status
Simulation time 3371901725 ps
CPU time 37.26 seconds
Started Mar 17 02:40:23 PM PDT 24
Finished Mar 17 02:41:01 PM PDT 24
Peak memory 215436 kb
Host smart-977c9382-5f20-4b29-b9c3-f3566e8fbf3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3166319130 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_smoke.3166319130
Directory /workspace/25.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/25.rom_ctrl_stress_all.2776680423
Short name T215
Test name
Test status
Simulation time 1090507534 ps
CPU time 62.4 seconds
Started Mar 17 02:40:22 PM PDT 24
Finished Mar 17 02:41:25 PM PDT 24
Peak memory 219520 kb
Host smart-02daa237-203a-44b9-bfbd-7664be93f299
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2776680423 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 25.rom_ctrl_stress_all.2776680423
Directory /workspace/25.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/25.rom_ctrl_stress_all.4149746963
Short name T556
Test name
Test status
Simulation time 29698097662 ps
CPU time 59.24 seconds
Started Mar 17 01:47:25 PM PDT 24
Finished Mar 17 01:48:25 PM PDT 24
Peak memory 219276 kb
Host smart-b7b242b0-00b7-42a2-a567-8c5f48a597ee
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4149746963 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 25.rom_ctrl_stress_all.4149746963
Directory /workspace/25.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/26.rom_ctrl_alert_test.20885463
Short name T230
Test name
Test status
Simulation time 2207683942 ps
CPU time 21.14 seconds
Started Mar 17 01:47:26 PM PDT 24
Finished Mar 17 01:47:48 PM PDT 24
Peak memory 211224 kb
Host smart-c9c3b883-b3fa-4b5d-886b-a163c1245c35
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20885463 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_alert_test.20885463
Directory /workspace/26.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/26.rom_ctrl_alert_test.3705329169
Short name T135
Test name
Test status
Simulation time 6528627890 ps
CPU time 19.32 seconds
Started Mar 17 02:40:24 PM PDT 24
Finished Mar 17 02:40:43 PM PDT 24
Peak memory 212088 kb
Host smart-c99a3086-6395-4286-8809-3cc4098147bf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3705329169 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_alert_test.3705329169
Directory /workspace/26.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/26.rom_ctrl_corrupt_sig_fatal_chk.150651603
Short name T491
Test name
Test status
Simulation time 115781376633 ps
CPU time 555.65 seconds
Started Mar 17 01:47:22 PM PDT 24
Finished Mar 17 01:56:38 PM PDT 24
Peak memory 217660 kb
Host smart-8602c336-0c6a-423b-930c-9bb6cdce9d1b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=150651603 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_c
orrupt_sig_fatal_chk.150651603
Directory /workspace/26.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/26.rom_ctrl_corrupt_sig_fatal_chk.347537785
Short name T256
Test name
Test status
Simulation time 26524639130 ps
CPU time 322.27 seconds
Started Mar 17 02:40:21 PM PDT 24
Finished Mar 17 02:45:43 PM PDT 24
Peak memory 236532 kb
Host smart-3696557c-edd7-473d-8422-341f2144265b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=347537785 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_c
orrupt_sig_fatal_chk.347537785
Directory /workspace/26.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/26.rom_ctrl_kmac_err_chk.1278150692
Short name T318
Test name
Test status
Simulation time 1321216085 ps
CPU time 19.22 seconds
Started Mar 17 02:40:23 PM PDT 24
Finished Mar 17 02:40:42 PM PDT 24
Peak memory 214780 kb
Host smart-d05c27d5-b53d-467a-869e-2c5418bdd871
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1278150692 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_kmac_err_chk.1278150692
Directory /workspace/26.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/26.rom_ctrl_kmac_err_chk.3951123029
Short name T407
Test name
Test status
Simulation time 7686505272 ps
CPU time 62.75 seconds
Started Mar 17 01:47:26 PM PDT 24
Finished Mar 17 01:48:29 PM PDT 24
Peak memory 216664 kb
Host smart-e2016788-37a2-4f84-ba1e-2b160ab44b7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3951123029 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_kmac_err_chk.3951123029
Directory /workspace/26.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/26.rom_ctrl_max_throughput_chk.2505597209
Short name T149
Test name
Test status
Simulation time 371183857 ps
CPU time 10.54 seconds
Started Mar 17 02:40:21 PM PDT 24
Finished Mar 17 02:40:31 PM PDT 24
Peak memory 212292 kb
Host smart-86be80f1-a9b5-481e-9f68-4d711f3e9b49
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2505597209 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_max_throughput_chk.2505597209
Directory /workspace/26.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/26.rom_ctrl_max_throughput_chk.851509384
Short name T184
Test name
Test status
Simulation time 2296630284 ps
CPU time 23.33 seconds
Started Mar 17 01:47:25 PM PDT 24
Finished Mar 17 01:47:48 PM PDT 24
Peak memory 212372 kb
Host smart-55f6c814-4da6-4e87-a444-28ad49454f8b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=851509384 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_max_throughput_chk.851509384
Directory /workspace/26.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/26.rom_ctrl_smoke.1194377551
Short name T400
Test name
Test status
Simulation time 1976910943 ps
CPU time 24.43 seconds
Started Mar 17 02:40:23 PM PDT 24
Finished Mar 17 02:40:48 PM PDT 24
Peak memory 216780 kb
Host smart-21db8d5a-ae19-48ee-a232-13c1dd7635ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1194377551 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_smoke.1194377551
Directory /workspace/26.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/26.rom_ctrl_smoke.3416280364
Short name T585
Test name
Test status
Simulation time 27276363206 ps
CPU time 61.24 seconds
Started Mar 17 01:47:27 PM PDT 24
Finished Mar 17 01:48:28 PM PDT 24
Peak memory 215116 kb
Host smart-26620b0a-770f-475f-842c-ab7e4182a4b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3416280364 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_smoke.3416280364
Directory /workspace/26.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/26.rom_ctrl_stress_all.2423198207
Short name T216
Test name
Test status
Simulation time 28768357493 ps
CPU time 79.27 seconds
Started Mar 17 02:40:24 PM PDT 24
Finished Mar 17 02:41:44 PM PDT 24
Peak memory 219168 kb
Host smart-836d281d-f54f-436f-bdd8-d19864c37fd6
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2423198207 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 26.rom_ctrl_stress_all.2423198207
Directory /workspace/26.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/26.rom_ctrl_stress_all.2828788607
Short name T166
Test name
Test status
Simulation time 21894326885 ps
CPU time 236.6 seconds
Started Mar 17 01:47:22 PM PDT 24
Finished Mar 17 01:51:19 PM PDT 24
Peak memory 230180 kb
Host smart-00154a48-d621-459d-936d-f2c7c4920908
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2828788607 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 26.rom_ctrl_stress_all.2828788607
Directory /workspace/26.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/27.rom_ctrl_alert_test.2641668844
Short name T272
Test name
Test status
Simulation time 1982811424 ps
CPU time 12.32 seconds
Started Mar 17 02:40:40 PM PDT 24
Finished Mar 17 02:40:52 PM PDT 24
Peak memory 211216 kb
Host smart-f6f6771d-2a4c-43d1-be09-00a2bb401c37
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2641668844 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_alert_test.2641668844
Directory /workspace/27.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/27.rom_ctrl_alert_test.810513606
Short name T133
Test name
Test status
Simulation time 4301267031 ps
CPU time 33.86 seconds
Started Mar 17 01:47:27 PM PDT 24
Finished Mar 17 01:48:01 PM PDT 24
Peak memory 212032 kb
Host smart-f4fe5e41-5673-4e75-a812-c568e863dc9e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=810513606 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_alert_test.810513606
Directory /workspace/27.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/27.rom_ctrl_corrupt_sig_fatal_chk.1098129694
Short name T675
Test name
Test status
Simulation time 4246703256 ps
CPU time 320.04 seconds
Started Mar 17 02:40:40 PM PDT 24
Finished Mar 17 02:46:00 PM PDT 24
Peak memory 239744 kb
Host smart-623dfc77-c3dc-4f31-a72b-f8a164215115
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1098129694 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_
corrupt_sig_fatal_chk.1098129694
Directory /workspace/27.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/27.rom_ctrl_corrupt_sig_fatal_chk.233351130
Short name T334
Test name
Test status
Simulation time 179058014361 ps
CPU time 422.64 seconds
Started Mar 17 01:47:23 PM PDT 24
Finished Mar 17 01:54:25 PM PDT 24
Peak memory 224648 kb
Host smart-f8bfb873-46bf-486e-8912-7875b3713b3a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=233351130 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_c
orrupt_sig_fatal_chk.233351130
Directory /workspace/27.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/27.rom_ctrl_kmac_err_chk.1467700456
Short name T270
Test name
Test status
Simulation time 7446749105 ps
CPU time 57.73 seconds
Started Mar 17 02:40:30 PM PDT 24
Finished Mar 17 02:41:29 PM PDT 24
Peak memory 214880 kb
Host smart-1f14f634-34de-41ca-aa13-9a192304f2c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1467700456 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_kmac_err_chk.1467700456
Directory /workspace/27.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/27.rom_ctrl_kmac_err_chk.3182887304
Short name T604
Test name
Test status
Simulation time 5575234314 ps
CPU time 52.99 seconds
Started Mar 17 01:47:21 PM PDT 24
Finished Mar 17 01:48:14 PM PDT 24
Peak memory 215128 kb
Host smart-266d8827-563f-466e-8996-334bd8eb4453
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3182887304 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_kmac_err_chk.3182887304
Directory /workspace/27.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/27.rom_ctrl_max_throughput_chk.1004660525
Short name T504
Test name
Test status
Simulation time 23458749136 ps
CPU time 31.23 seconds
Started Mar 17 02:40:32 PM PDT 24
Finished Mar 17 02:41:03 PM PDT 24
Peak memory 212672 kb
Host smart-d7cba7b1-efbe-4fb4-985b-230652ab6069
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1004660525 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_max_throughput_chk.1004660525
Directory /workspace/27.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/27.rom_ctrl_max_throughput_chk.1708427863
Short name T660
Test name
Test status
Simulation time 246780670 ps
CPU time 10.08 seconds
Started Mar 17 01:47:19 PM PDT 24
Finished Mar 17 01:47:30 PM PDT 24
Peak memory 212224 kb
Host smart-883f8c66-dfd0-47b5-aff2-c619142ce4a2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1708427863 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_max_throughput_chk.1708427863
Directory /workspace/27.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/27.rom_ctrl_smoke.2573535963
Short name T450
Test name
Test status
Simulation time 1434911721 ps
CPU time 20.3 seconds
Started Mar 17 01:47:20 PM PDT 24
Finished Mar 17 01:47:41 PM PDT 24
Peak memory 217600 kb
Host smart-34ea448c-6dba-48fa-9f4e-b2ebb9fddac7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2573535963 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_smoke.2573535963
Directory /workspace/27.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/27.rom_ctrl_smoke.360464244
Short name T147
Test name
Test status
Simulation time 3459894053 ps
CPU time 45.45 seconds
Started Mar 17 02:40:29 PM PDT 24
Finished Mar 17 02:41:14 PM PDT 24
Peak memory 217444 kb
Host smart-e292d24c-e62f-4fdf-9036-4cd7dcd24266
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=360464244 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_smoke.360464244
Directory /workspace/27.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/27.rom_ctrl_stress_all.1246979370
Short name T377
Test name
Test status
Simulation time 5130525211 ps
CPU time 44.37 seconds
Started Mar 17 02:40:30 PM PDT 24
Finished Mar 17 02:41:14 PM PDT 24
Peak memory 219304 kb
Host smart-d533a11b-cc1a-4cd9-9af6-6c34ca2f1fff
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1246979370 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 27.rom_ctrl_stress_all.1246979370
Directory /workspace/27.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/27.rom_ctrl_stress_all.3259904057
Short name T427
Test name
Test status
Simulation time 13406303347 ps
CPU time 123.08 seconds
Started Mar 17 01:47:21 PM PDT 24
Finished Mar 17 01:49:24 PM PDT 24
Peak memory 219284 kb
Host smart-b77b315c-b020-4a2c-b23f-470d49bcc142
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3259904057 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 27.rom_ctrl_stress_all.3259904057
Directory /workspace/27.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/28.rom_ctrl_alert_test.1379805345
Short name T599
Test name
Test status
Simulation time 3889143599 ps
CPU time 31.33 seconds
Started Mar 17 02:40:32 PM PDT 24
Finished Mar 17 02:41:04 PM PDT 24
Peak memory 211284 kb
Host smart-b94e53a5-feca-478e-bcef-9dfc21f02b49
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1379805345 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_alert_test.1379805345
Directory /workspace/28.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/28.rom_ctrl_alert_test.2522691858
Short name T140
Test name
Test status
Simulation time 16420408031 ps
CPU time 20.58 seconds
Started Mar 17 01:47:19 PM PDT 24
Finished Mar 17 01:47:39 PM PDT 24
Peak memory 211228 kb
Host smart-4df6b737-37c2-424e-89ee-6b5860c89ccd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2522691858 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_alert_test.2522691858
Directory /workspace/28.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/28.rom_ctrl_corrupt_sig_fatal_chk.3945861087
Short name T676
Test name
Test status
Simulation time 28887536259 ps
CPU time 305.15 seconds
Started Mar 17 01:47:28 PM PDT 24
Finished Mar 17 01:52:33 PM PDT 24
Peak memory 227672 kb
Host smart-4fae9bdd-da67-44e1-b865-574ad99149d4
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3945861087 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_
corrupt_sig_fatal_chk.3945861087
Directory /workspace/28.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/28.rom_ctrl_corrupt_sig_fatal_chk.570752613
Short name T227
Test name
Test status
Simulation time 49760209129 ps
CPU time 594.09 seconds
Started Mar 17 02:40:29 PM PDT 24
Finished Mar 17 02:50:23 PM PDT 24
Peak memory 236916 kb
Host smart-971df2d6-e6c7-4165-ac5c-09ec4d0291fc
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=570752613 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_c
orrupt_sig_fatal_chk.570752613
Directory /workspace/28.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/28.rom_ctrl_kmac_err_chk.3203751513
Short name T539
Test name
Test status
Simulation time 1371933588 ps
CPU time 28.1 seconds
Started Mar 17 01:47:20 PM PDT 24
Finished Mar 17 01:47:48 PM PDT 24
Peak memory 214464 kb
Host smart-73406274-15ee-4e00-81c9-e755e03cb2c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3203751513 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_kmac_err_chk.3203751513
Directory /workspace/28.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/28.rom_ctrl_kmac_err_chk.411130365
Short name T518
Test name
Test status
Simulation time 846982941 ps
CPU time 24.45 seconds
Started Mar 17 02:40:26 PM PDT 24
Finished Mar 17 02:40:51 PM PDT 24
Peak memory 214596 kb
Host smart-d22cd7da-a2be-4520-b40e-cc182d4d9005
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=411130365 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_kmac_err_chk.411130365
Directory /workspace/28.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/28.rom_ctrl_max_throughput_chk.1736163633
Short name T6
Test name
Test status
Simulation time 1990175901 ps
CPU time 21.68 seconds
Started Mar 17 02:40:33 PM PDT 24
Finished Mar 17 02:40:55 PM PDT 24
Peak memory 212408 kb
Host smart-64112710-b773-4267-bce4-05fb953384fd
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1736163633 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_max_throughput_chk.1736163633
Directory /workspace/28.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/28.rom_ctrl_max_throughput_chk.2792153414
Short name T633
Test name
Test status
Simulation time 7941656746 ps
CPU time 32.41 seconds
Started Mar 17 01:47:19 PM PDT 24
Finished Mar 17 01:47:52 PM PDT 24
Peak memory 211580 kb
Host smart-fb6257e1-c8c4-4539-877b-5171f13f7960
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2792153414 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_max_throughput_chk.2792153414
Directory /workspace/28.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/28.rom_ctrl_smoke.1704570311
Short name T642
Test name
Test status
Simulation time 2789587898 ps
CPU time 37.97 seconds
Started Mar 17 02:40:32 PM PDT 24
Finished Mar 17 02:41:10 PM PDT 24
Peak memory 215036 kb
Host smart-f6efb5a1-5d46-49c2-9c0e-d205c9820a7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1704570311 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_smoke.1704570311
Directory /workspace/28.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/28.rom_ctrl_smoke.1825753140
Short name T424
Test name
Test status
Simulation time 33985217343 ps
CPU time 51.37 seconds
Started Mar 17 01:47:25 PM PDT 24
Finished Mar 17 01:48:17 PM PDT 24
Peak memory 215756 kb
Host smart-4cac897e-1861-48f4-a85e-e335ed533ff0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1825753140 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_smoke.1825753140
Directory /workspace/28.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/28.rom_ctrl_stress_all.1447025926
Short name T467
Test name
Test status
Simulation time 1520023870 ps
CPU time 45.7 seconds
Started Mar 17 02:40:29 PM PDT 24
Finished Mar 17 02:41:15 PM PDT 24
Peak memory 218756 kb
Host smart-98d1a72e-aac3-43dc-aeba-8a4576d54ac8
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1447025926 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 28.rom_ctrl_stress_all.1447025926
Directory /workspace/28.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/28.rom_ctrl_stress_all.4253125491
Short name T145
Test name
Test status
Simulation time 45337787417 ps
CPU time 147.82 seconds
Started Mar 17 01:47:22 PM PDT 24
Finished Mar 17 01:49:50 PM PDT 24
Peak memory 221812 kb
Host smart-4249e347-6a0f-4714-bcc7-e455e4237e0f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4253125491 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 28.rom_ctrl_stress_all.4253125491
Directory /workspace/28.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/29.rom_ctrl_alert_test.3126388178
Short name T560
Test name
Test status
Simulation time 1961085630 ps
CPU time 21.14 seconds
Started Mar 17 02:40:40 PM PDT 24
Finished Mar 17 02:41:01 PM PDT 24
Peak memory 211244 kb
Host smart-93ce1d07-ea96-4154-8d78-ad5ebb13912c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3126388178 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_alert_test.3126388178
Directory /workspace/29.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/29.rom_ctrl_alert_test.3734633894
Short name T405
Test name
Test status
Simulation time 11795234054 ps
CPU time 25.66 seconds
Started Mar 17 01:47:20 PM PDT 24
Finished Mar 17 01:47:46 PM PDT 24
Peak memory 212056 kb
Host smart-919221ef-69bc-4437-b7a9-32bb2dded3f7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3734633894 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_alert_test.3734633894
Directory /workspace/29.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/29.rom_ctrl_corrupt_sig_fatal_chk.2920557973
Short name T243
Test name
Test status
Simulation time 6815524143 ps
CPU time 264.1 seconds
Started Mar 17 01:47:21 PM PDT 24
Finished Mar 17 01:51:46 PM PDT 24
Peak memory 217264 kb
Host smart-20f0ac68-de5f-4009-a756-ffd22e5f81f6
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2920557973 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_
corrupt_sig_fatal_chk.2920557973
Directory /workspace/29.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/29.rom_ctrl_corrupt_sig_fatal_chk.3955552430
Short name T258
Test name
Test status
Simulation time 8420686004 ps
CPU time 302.52 seconds
Started Mar 17 02:40:29 PM PDT 24
Finished Mar 17 02:45:32 PM PDT 24
Peak memory 239284 kb
Host smart-02f565ff-a665-4592-beda-48ad522aad63
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3955552430 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_
corrupt_sig_fatal_chk.3955552430
Directory /workspace/29.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/29.rom_ctrl_kmac_err_chk.2132951103
Short name T474
Test name
Test status
Simulation time 7035616914 ps
CPU time 61.32 seconds
Started Mar 17 02:40:32 PM PDT 24
Finished Mar 17 02:41:34 PM PDT 24
Peak memory 214860 kb
Host smart-2a156894-e699-466d-b88f-740d265f2e73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2132951103 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_kmac_err_chk.2132951103
Directory /workspace/29.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/29.rom_ctrl_kmac_err_chk.3789032306
Short name T465
Test name
Test status
Simulation time 16439188900 ps
CPU time 26.18 seconds
Started Mar 17 01:47:23 PM PDT 24
Finished Mar 17 01:47:49 PM PDT 24
Peak memory 215240 kb
Host smart-bb372485-3ee9-44c4-844d-ed045124972c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3789032306 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_kmac_err_chk.3789032306
Directory /workspace/29.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/29.rom_ctrl_max_throughput_chk.1088517969
Short name T257
Test name
Test status
Simulation time 4372963968 ps
CPU time 23.4 seconds
Started Mar 17 02:40:32 PM PDT 24
Finished Mar 17 02:40:56 PM PDT 24
Peak memory 211620 kb
Host smart-3a4b2ba8-18ee-44de-aa61-1114a86cb139
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1088517969 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_max_throughput_chk.1088517969
Directory /workspace/29.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/29.rom_ctrl_max_throughput_chk.883339466
Short name T483
Test name
Test status
Simulation time 6891086021 ps
CPU time 20.62 seconds
Started Mar 17 01:47:26 PM PDT 24
Finished Mar 17 01:47:46 PM PDT 24
Peak memory 211516 kb
Host smart-818fc0a8-3cfa-442d-96d9-eaf65973cf15
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=883339466 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_max_throughput_chk.883339466
Directory /workspace/29.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/29.rom_ctrl_smoke.1828218163
Short name T354
Test name
Test status
Simulation time 931969044 ps
CPU time 19.4 seconds
Started Mar 17 01:47:25 PM PDT 24
Finished Mar 17 01:47:45 PM PDT 24
Peak memory 216740 kb
Host smart-3d613e4b-2542-4d80-9345-e7303d31e7f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1828218163 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_smoke.1828218163
Directory /workspace/29.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/29.rom_ctrl_smoke.3687593779
Short name T244
Test name
Test status
Simulation time 11092153662 ps
CPU time 53.29 seconds
Started Mar 17 02:40:30 PM PDT 24
Finished Mar 17 02:41:23 PM PDT 24
Peak memory 218172 kb
Host smart-2dd45471-9d36-4945-996b-2bfbb3358bb6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3687593779 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_smoke.3687593779
Directory /workspace/29.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/29.rom_ctrl_stress_all.1381163408
Short name T255
Test name
Test status
Simulation time 3862922593 ps
CPU time 59.65 seconds
Started Mar 17 02:40:33 PM PDT 24
Finished Mar 17 02:41:33 PM PDT 24
Peak memory 215048 kb
Host smart-25360d79-9699-44b8-94fd-54c1ac074eb0
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1381163408 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 29.rom_ctrl_stress_all.1381163408
Directory /workspace/29.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/29.rom_ctrl_stress_all.2880986789
Short name T78
Test name
Test status
Simulation time 8430726388 ps
CPU time 107.95 seconds
Started Mar 17 01:47:20 PM PDT 24
Finished Mar 17 01:49:08 PM PDT 24
Peak memory 217760 kb
Host smart-abc10b66-3356-4a99-9de9-55e1ac0a0f10
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2880986789 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 29.rom_ctrl_stress_all.2880986789
Directory /workspace/29.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/3.rom_ctrl_alert_test.1978712706
Short name T278
Test name
Test status
Simulation time 12235668253 ps
CPU time 25.58 seconds
Started Mar 17 01:46:47 PM PDT 24
Finished Mar 17 01:47:13 PM PDT 24
Peak memory 211328 kb
Host smart-000ea00f-2c8d-4a48-ae90-3d3bafb4f03c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1978712706 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_alert_test.1978712706
Directory /workspace/3.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/3.rom_ctrl_alert_test.4069271542
Short name T288
Test name
Test status
Simulation time 1711388738 ps
CPU time 19.03 seconds
Started Mar 17 02:40:03 PM PDT 24
Finished Mar 17 02:40:22 PM PDT 24
Peak memory 211220 kb
Host smart-f8ac8db1-5b87-4923-992c-e4e131ff530b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4069271542 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_alert_test.4069271542
Directory /workspace/3.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/3.rom_ctrl_corrupt_sig_fatal_chk.840438625
Short name T333
Test name
Test status
Simulation time 17363236130 ps
CPU time 430.79 seconds
Started Mar 17 02:39:59 PM PDT 24
Finished Mar 17 02:47:10 PM PDT 24
Peak memory 233464 kb
Host smart-79a495d6-4608-4434-9c56-e8cca3117877
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=840438625 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_co
rrupt_sig_fatal_chk.840438625
Directory /workspace/3.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/3.rom_ctrl_kmac_err_chk.3416561793
Short name T161
Test name
Test status
Simulation time 6398632076 ps
CPU time 58.07 seconds
Started Mar 17 01:46:48 PM PDT 24
Finished Mar 17 01:47:46 PM PDT 24
Peak memory 214832 kb
Host smart-813b5dde-31fd-4ee3-bc47-b74edfe90e28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3416561793 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_kmac_err_chk.3416561793
Directory /workspace/3.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/3.rom_ctrl_kmac_err_chk.3798772453
Short name T379
Test name
Test status
Simulation time 5995102991 ps
CPU time 38.9 seconds
Started Mar 17 02:39:58 PM PDT 24
Finished Mar 17 02:40:37 PM PDT 24
Peak memory 213936 kb
Host smart-cc9b7d22-9d2a-4856-a5c4-bc6163859560
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3798772453 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_kmac_err_chk.3798772453
Directory /workspace/3.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/3.rom_ctrl_max_throughput_chk.1472651997
Short name T516
Test name
Test status
Simulation time 2919720535 ps
CPU time 16.92 seconds
Started Mar 17 02:39:59 PM PDT 24
Finished Mar 17 02:40:17 PM PDT 24
Peak memory 211464 kb
Host smart-5a290e74-23a3-40d2-84d4-fe85a3bd607e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1472651997 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_max_throughput_chk.1472651997
Directory /workspace/3.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/3.rom_ctrl_max_throughput_chk.1496824215
Short name T542
Test name
Test status
Simulation time 868906925 ps
CPU time 10.23 seconds
Started Mar 17 01:46:52 PM PDT 24
Finished Mar 17 01:47:02 PM PDT 24
Peak memory 212484 kb
Host smart-a86556f8-bb8f-4c26-913c-0aedbc09bcf3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1496824215 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_max_throughput_chk.1496824215
Directory /workspace/3.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/3.rom_ctrl_sec_cm.2846640419
Short name T40
Test name
Test status
Simulation time 14330609871 ps
CPU time 249.13 seconds
Started Mar 17 01:46:53 PM PDT 24
Finished Mar 17 01:51:03 PM PDT 24
Peak memory 238112 kb
Host smart-35c6f829-6b4f-4e7a-bd19-a1b795cfc755
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2846640419 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_sec_cm.2846640419
Directory /workspace/3.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/3.rom_ctrl_smoke.2383036922
Short name T260
Test name
Test status
Simulation time 16068696365 ps
CPU time 63.5 seconds
Started Mar 17 01:46:50 PM PDT 24
Finished Mar 17 01:47:53 PM PDT 24
Peak memory 217408 kb
Host smart-80d5bf9d-bf49-4297-80ea-c8094e759861
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2383036922 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_smoke.2383036922
Directory /workspace/3.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/3.rom_ctrl_smoke.506758330
Short name T168
Test name
Test status
Simulation time 2432247196 ps
CPU time 36.83 seconds
Started Mar 17 02:40:00 PM PDT 24
Finished Mar 17 02:40:38 PM PDT 24
Peak memory 217756 kb
Host smart-a0f0c4b5-c6f3-4cde-9da8-9082f5f89e79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=506758330 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_smoke.506758330
Directory /workspace/3.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/3.rom_ctrl_stress_all.3375755403
Short name T436
Test name
Test status
Simulation time 4615443872 ps
CPU time 20.68 seconds
Started Mar 17 02:39:58 PM PDT 24
Finished Mar 17 02:40:19 PM PDT 24
Peak memory 211936 kb
Host smart-33fb5beb-b2eb-4d4e-b434-ecce3d4207d7
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3375755403 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 3.rom_ctrl_stress_all.3375755403
Directory /workspace/3.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/3.rom_ctrl_stress_all.3456632376
Short name T245
Test name
Test status
Simulation time 53884995047 ps
CPU time 94.63 seconds
Started Mar 17 01:46:50 PM PDT 24
Finished Mar 17 01:48:24 PM PDT 24
Peak memory 220088 kb
Host smart-d0144175-298c-4b9a-ad7e-c1a64e4941db
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3456632376 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 3.rom_ctrl_stress_all.3456632376
Directory /workspace/3.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/3.rom_ctrl_stress_all_with_rand_reset.1675983747
Short name T52
Test name
Test status
Simulation time 80327648282 ps
CPU time 1046.07 seconds
Started Mar 17 02:39:59 PM PDT 24
Finished Mar 17 02:57:25 PM PDT 24
Peak memory 231584 kb
Host smart-99969744-4601-4297-af5b-b3e18ed37061
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1675983747 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_stress_all_with_rand_reset.1675983747
Directory /workspace/3.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.rom_ctrl_stress_all_with_rand_reset.3509622978
Short name T644
Test name
Test status
Simulation time 57276901717 ps
CPU time 2184.98 seconds
Started Mar 17 01:46:51 PM PDT 24
Finished Mar 17 02:23:17 PM PDT 24
Peak memory 244884 kb
Host smart-abcabcf5-c003-4aa7-b02a-c70420b5f33d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3509622978 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_stress_all_with_rand_reset.3509622978
Directory /workspace/3.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.rom_ctrl_alert_test.1336966907
Short name T152
Test name
Test status
Simulation time 9074923850 ps
CPU time 23.25 seconds
Started Mar 17 01:47:25 PM PDT 24
Finished Mar 17 01:47:48 PM PDT 24
Peak memory 212064 kb
Host smart-135b524f-eda6-4767-92cf-113a4ffa3df1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1336966907 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_alert_test.1336966907
Directory /workspace/30.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/30.rom_ctrl_alert_test.639809905
Short name T62
Test name
Test status
Simulation time 2686340911 ps
CPU time 16.81 seconds
Started Mar 17 02:40:26 PM PDT 24
Finished Mar 17 02:40:43 PM PDT 24
Peak memory 211868 kb
Host smart-20316cea-22e8-4194-ac7f-d8eb0ad93730
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=639809905 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_alert_test.639809905
Directory /workspace/30.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/30.rom_ctrl_corrupt_sig_fatal_chk.2979779279
Short name T290
Test name
Test status
Simulation time 10189885608 ps
CPU time 172.12 seconds
Started Mar 17 02:40:30 PM PDT 24
Finished Mar 17 02:43:22 PM PDT 24
Peak memory 236564 kb
Host smart-a73a3b4e-f00d-4381-a06f-f46e3d65a105
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2979779279 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_
corrupt_sig_fatal_chk.2979779279
Directory /workspace/30.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/30.rom_ctrl_kmac_err_chk.2657225938
Short name T454
Test name
Test status
Simulation time 2797020603 ps
CPU time 36.63 seconds
Started Mar 17 01:47:20 PM PDT 24
Finished Mar 17 01:47:57 PM PDT 24
Peak memory 214912 kb
Host smart-6a2d910a-52a9-4444-8a29-3ac99f255791
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2657225938 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_kmac_err_chk.2657225938
Directory /workspace/30.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/30.rom_ctrl_kmac_err_chk.3196510489
Short name T391
Test name
Test status
Simulation time 26775472903 ps
CPU time 56.24 seconds
Started Mar 17 02:40:35 PM PDT 24
Finished Mar 17 02:41:32 PM PDT 24
Peak memory 215048 kb
Host smart-778de4e9-8308-4b1b-b4de-26dbcb8c7e7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3196510489 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_kmac_err_chk.3196510489
Directory /workspace/30.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/30.rom_ctrl_max_throughput_chk.1329747368
Short name T412
Test name
Test status
Simulation time 748103631 ps
CPU time 15.83 seconds
Started Mar 17 02:40:30 PM PDT 24
Finished Mar 17 02:40:47 PM PDT 24
Peak memory 211228 kb
Host smart-9c613da5-68ab-4002-8826-f19de7be893f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1329747368 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_max_throughput_chk.1329747368
Directory /workspace/30.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/30.rom_ctrl_max_throughput_chk.817433151
Short name T195
Test name
Test status
Simulation time 1801841250 ps
CPU time 20.6 seconds
Started Mar 17 01:47:18 PM PDT 24
Finished Mar 17 01:47:39 PM PDT 24
Peak memory 212164 kb
Host smart-f352b2c3-caa5-49f8-b037-33021c260eee
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=817433151 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_max_throughput_chk.817433151
Directory /workspace/30.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/30.rom_ctrl_smoke.1384290523
Short name T387
Test name
Test status
Simulation time 11463771319 ps
CPU time 61.62 seconds
Started Mar 17 02:40:30 PM PDT 24
Finished Mar 17 02:41:32 PM PDT 24
Peak memory 217992 kb
Host smart-0d864353-62fc-42cf-9b15-e5c3383cb029
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1384290523 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_smoke.1384290523
Directory /workspace/30.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/30.rom_ctrl_smoke.1393438296
Short name T299
Test name
Test status
Simulation time 10958751202 ps
CPU time 40.07 seconds
Started Mar 17 01:47:25 PM PDT 24
Finished Mar 17 01:48:05 PM PDT 24
Peak memory 218020 kb
Host smart-57070ff2-7d53-4387-91c2-c8aa73c38b11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1393438296 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_smoke.1393438296
Directory /workspace/30.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/30.rom_ctrl_stress_all.1127615059
Short name T471
Test name
Test status
Simulation time 7735845300 ps
CPU time 22.64 seconds
Started Mar 17 01:47:25 PM PDT 24
Finished Mar 17 01:47:48 PM PDT 24
Peak memory 214060 kb
Host smart-aeff49c6-d6a1-469a-862b-e9b24955e789
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1127615059 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 30.rom_ctrl_stress_all.1127615059
Directory /workspace/30.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/30.rom_ctrl_stress_all.1192789297
Short name T178
Test name
Test status
Simulation time 16452730417 ps
CPU time 35.29 seconds
Started Mar 17 02:40:30 PM PDT 24
Finished Mar 17 02:41:05 PM PDT 24
Peak memory 218436 kb
Host smart-86c1eb3e-7085-4236-bf60-085bf82a1f8f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1192789297 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 30.rom_ctrl_stress_all.1192789297
Directory /workspace/30.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/31.rom_ctrl_alert_test.1097112016
Short name T439
Test name
Test status
Simulation time 1167098508 ps
CPU time 12.39 seconds
Started Mar 17 02:40:31 PM PDT 24
Finished Mar 17 02:40:44 PM PDT 24
Peak memory 211252 kb
Host smart-91a2fc78-1b0c-4b3b-b5c2-2335db425314
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1097112016 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_alert_test.1097112016
Directory /workspace/31.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/31.rom_ctrl_alert_test.3338914675
Short name T498
Test name
Test status
Simulation time 2557190462 ps
CPU time 23.58 seconds
Started Mar 17 01:47:22 PM PDT 24
Finished Mar 17 01:47:45 PM PDT 24
Peak memory 211952 kb
Host smart-07b26c7c-2078-4020-8fcc-c548d20cf054
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3338914675 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_alert_test.3338914675
Directory /workspace/31.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/31.rom_ctrl_corrupt_sig_fatal_chk.2089153837
Short name T45
Test name
Test status
Simulation time 87048502018 ps
CPU time 506.54 seconds
Started Mar 17 02:40:40 PM PDT 24
Finished Mar 17 02:49:07 PM PDT 24
Peak memory 224164 kb
Host smart-ebbbcf9d-f5e8-4784-b3ff-6bd9dd7dc332
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2089153837 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_
corrupt_sig_fatal_chk.2089153837
Directory /workspace/31.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/31.rom_ctrl_corrupt_sig_fatal_chk.3402979682
Short name T513
Test name
Test status
Simulation time 16548128428 ps
CPU time 162.59 seconds
Started Mar 17 01:47:27 PM PDT 24
Finished Mar 17 01:50:10 PM PDT 24
Peak memory 233436 kb
Host smart-909bba6d-2df7-4e43-9875-75065d21fbff
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3402979682 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_
corrupt_sig_fatal_chk.3402979682
Directory /workspace/31.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/31.rom_ctrl_kmac_err_chk.1997728195
Short name T27
Test name
Test status
Simulation time 4842587555 ps
CPU time 47 seconds
Started Mar 17 01:47:22 PM PDT 24
Finished Mar 17 01:48:09 PM PDT 24
Peak memory 215336 kb
Host smart-e99054c8-3148-4e06-8375-ca254417084a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1997728195 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_kmac_err_chk.1997728195
Directory /workspace/31.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/31.rom_ctrl_kmac_err_chk.3673336883
Short name T393
Test name
Test status
Simulation time 1382027999 ps
CPU time 28.55 seconds
Started Mar 17 02:40:33 PM PDT 24
Finished Mar 17 02:41:02 PM PDT 24
Peak memory 215256 kb
Host smart-bd1cee00-1245-4518-b43b-bfafa094976a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3673336883 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_kmac_err_chk.3673336883
Directory /workspace/31.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/31.rom_ctrl_max_throughput_chk.3170356319
Short name T112
Test name
Test status
Simulation time 3728099765 ps
CPU time 31.13 seconds
Started Mar 17 02:40:40 PM PDT 24
Finished Mar 17 02:41:11 PM PDT 24
Peak memory 210904 kb
Host smart-324e1b88-e00d-4743-ae58-0c03d5ae7320
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3170356319 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_max_throughput_chk.3170356319
Directory /workspace/31.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/31.rom_ctrl_max_throughput_chk.4017094556
Short name T536
Test name
Test status
Simulation time 9917209248 ps
CPU time 19.89 seconds
Started Mar 17 01:47:24 PM PDT 24
Finished Mar 17 01:47:44 PM PDT 24
Peak memory 212692 kb
Host smart-3b72e6ef-7f18-4f71-b05d-6e3ca769b2a5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4017094556 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_max_throughput_chk.4017094556
Directory /workspace/31.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/31.rom_ctrl_smoke.1072094419
Short name T228
Test name
Test status
Simulation time 4588553564 ps
CPU time 48.01 seconds
Started Mar 17 02:40:31 PM PDT 24
Finished Mar 17 02:41:19 PM PDT 24
Peak memory 217504 kb
Host smart-6b3ef863-167d-40a8-9410-853c370602b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1072094419 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_smoke.1072094419
Directory /workspace/31.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/31.rom_ctrl_smoke.4178099381
Short name T607
Test name
Test status
Simulation time 1048770653 ps
CPU time 29.25 seconds
Started Mar 17 01:47:21 PM PDT 24
Finished Mar 17 01:47:50 PM PDT 24
Peak memory 215480 kb
Host smart-71101fae-6ec2-41e4-a098-77daaa0b2750
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4178099381 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_smoke.4178099381
Directory /workspace/31.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/31.rom_ctrl_stress_all.1229921449
Short name T212
Test name
Test status
Simulation time 6680627272 ps
CPU time 21.44 seconds
Started Mar 17 02:40:30 PM PDT 24
Finished Mar 17 02:40:51 PM PDT 24
Peak memory 213924 kb
Host smart-f5daf545-4e61-40dd-bd19-f1cf9c6c0cfb
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1229921449 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 31.rom_ctrl_stress_all.1229921449
Directory /workspace/31.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/31.rom_ctrl_stress_all.841538716
Short name T321
Test name
Test status
Simulation time 4827347851 ps
CPU time 62.95 seconds
Started Mar 17 01:47:26 PM PDT 24
Finished Mar 17 01:48:29 PM PDT 24
Peak memory 215168 kb
Host smart-00cc2871-a83a-45c0-a69a-0a7ec3f96565
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=841538716 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 31.rom_ctrl_stress_all.841538716
Directory /workspace/31.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/31.rom_ctrl_stress_all_with_rand_reset.3159674815
Short name T627
Test name
Test status
Simulation time 96091353511 ps
CPU time 7958.22 seconds
Started Mar 17 02:40:33 PM PDT 24
Finished Mar 17 04:53:13 PM PDT 24
Peak memory 232704 kb
Host smart-b20b416e-daa7-4e77-9160-70476d4ce6fd
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3159674815 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_stress_all_with_rand_reset.3159674815
Directory /workspace/31.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.rom_ctrl_alert_test.1122507339
Short name T162
Test name
Test status
Simulation time 7926826898 ps
CPU time 21.67 seconds
Started Mar 17 02:40:31 PM PDT 24
Finished Mar 17 02:40:53 PM PDT 24
Peak memory 212148 kb
Host smart-0c9c2a31-0f99-4428-94bb-fe1cee70919f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1122507339 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_alert_test.1122507339
Directory /workspace/32.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/32.rom_ctrl_alert_test.652611626
Short name T397
Test name
Test status
Simulation time 17774699967 ps
CPU time 31.19 seconds
Started Mar 17 01:47:23 PM PDT 24
Finished Mar 17 01:47:54 PM PDT 24
Peak memory 212176 kb
Host smart-7cc9fbf5-4981-4324-9303-b05950c0eb08
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=652611626 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_alert_test.652611626
Directory /workspace/32.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/32.rom_ctrl_corrupt_sig_fatal_chk.3804496793
Short name T462
Test name
Test status
Simulation time 6954233305 ps
CPU time 132.52 seconds
Started Mar 17 02:40:32 PM PDT 24
Finished Mar 17 02:42:45 PM PDT 24
Peak memory 239584 kb
Host smart-c4793a96-5fcd-4981-b461-e77fcf297dd1
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3804496793 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_
corrupt_sig_fatal_chk.3804496793
Directory /workspace/32.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/32.rom_ctrl_corrupt_sig_fatal_chk.801107161
Short name T583
Test name
Test status
Simulation time 12086579413 ps
CPU time 307.89 seconds
Started Mar 17 01:47:21 PM PDT 24
Finished Mar 17 01:52:29 PM PDT 24
Peak memory 217144 kb
Host smart-f06f64d3-dbec-4c27-804e-b7951904b5c6
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=801107161 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_c
orrupt_sig_fatal_chk.801107161
Directory /workspace/32.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/32.rom_ctrl_kmac_err_chk.1942133173
Short name T574
Test name
Test status
Simulation time 1319016371 ps
CPU time 19.36 seconds
Started Mar 17 02:40:33 PM PDT 24
Finished Mar 17 02:40:53 PM PDT 24
Peak memory 214676 kb
Host smart-a618d03d-b02f-468c-9a7f-dbf5e1861758
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1942133173 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_kmac_err_chk.1942133173
Directory /workspace/32.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/32.rom_ctrl_kmac_err_chk.2681542035
Short name T217
Test name
Test status
Simulation time 14735149096 ps
CPU time 63.87 seconds
Started Mar 17 01:47:27 PM PDT 24
Finished Mar 17 01:48:31 PM PDT 24
Peak memory 214948 kb
Host smart-72913af1-9ad5-4594-842b-d064085e57f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2681542035 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_kmac_err_chk.2681542035
Directory /workspace/32.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/32.rom_ctrl_max_throughput_chk.1409483846
Short name T500
Test name
Test status
Simulation time 2978079511 ps
CPU time 28.04 seconds
Started Mar 17 02:40:31 PM PDT 24
Finished Mar 17 02:40:59 PM PDT 24
Peak memory 211360 kb
Host smart-f8d3dbbc-5df7-49ee-87d6-c2f1fd87f05f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1409483846 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_max_throughput_chk.1409483846
Directory /workspace/32.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/32.rom_ctrl_max_throughput_chk.4171836678
Short name T223
Test name
Test status
Simulation time 3691979248 ps
CPU time 30.22 seconds
Started Mar 17 01:47:27 PM PDT 24
Finished Mar 17 01:47:58 PM PDT 24
Peak memory 211516 kb
Host smart-2150ecf9-fb67-479f-929c-33bbe6099e03
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4171836678 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_max_throughput_chk.4171836678
Directory /workspace/32.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/32.rom_ctrl_smoke.236878993
Short name T505
Test name
Test status
Simulation time 39311955245 ps
CPU time 61.38 seconds
Started Mar 17 01:47:26 PM PDT 24
Finished Mar 17 01:48:27 PM PDT 24
Peak memory 218304 kb
Host smart-faedc039-935b-4e7f-8aa7-aeb5bdc85156
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=236878993 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_smoke.236878993
Directory /workspace/32.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/32.rom_ctrl_smoke.3711064171
Short name T253
Test name
Test status
Simulation time 68051195972 ps
CPU time 60.67 seconds
Started Mar 17 02:40:31 PM PDT 24
Finished Mar 17 02:41:32 PM PDT 24
Peak memory 217336 kb
Host smart-a0747b97-a94e-4795-85e4-10b632fbfdee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3711064171 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_smoke.3711064171
Directory /workspace/32.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/32.rom_ctrl_stress_all.3297353743
Short name T297
Test name
Test status
Simulation time 430724996 ps
CPU time 11.83 seconds
Started Mar 17 02:40:30 PM PDT 24
Finished Mar 17 02:40:42 PM PDT 24
Peak memory 213500 kb
Host smart-3d6ccd0a-0a74-4733-9e6c-bdeb416e96dd
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3297353743 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 32.rom_ctrl_stress_all.3297353743
Directory /workspace/32.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/32.rom_ctrl_stress_all.530333708
Short name T681
Test name
Test status
Simulation time 2593763428 ps
CPU time 45.05 seconds
Started Mar 17 01:47:28 PM PDT 24
Finished Mar 17 01:48:13 PM PDT 24
Peak memory 219272 kb
Host smart-7ed2ef41-0fa5-4722-b4bd-df74c19d1ded
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=530333708 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 32.rom_ctrl_stress_all.530333708
Directory /workspace/32.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/32.rom_ctrl_stress_all_with_rand_reset.1022859616
Short name T48
Test name
Test status
Simulation time 147806449518 ps
CPU time 1556.83 seconds
Started Mar 17 01:47:22 PM PDT 24
Finished Mar 17 02:13:19 PM PDT 24
Peak memory 238492 kb
Host smart-e99e923d-d536-417a-9446-36b1a021280c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1022859616 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_stress_all_with_rand_reset.1022859616
Directory /workspace/32.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.rom_ctrl_alert_test.1350762471
Short name T327
Test name
Test status
Simulation time 337608758 ps
CPU time 10.74 seconds
Started Mar 17 02:40:31 PM PDT 24
Finished Mar 17 02:40:42 PM PDT 24
Peak memory 211204 kb
Host smart-3188c023-7a25-4bb3-8c7b-3f4cae9421a9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1350762471 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_alert_test.1350762471
Directory /workspace/33.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/33.rom_ctrl_alert_test.3097167213
Short name T268
Test name
Test status
Simulation time 689511355 ps
CPU time 8.05 seconds
Started Mar 17 01:47:32 PM PDT 24
Finished Mar 17 01:47:41 PM PDT 24
Peak memory 211180 kb
Host smart-924b71ee-ff45-4b55-ae7e-eaba9628efb8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3097167213 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_alert_test.3097167213
Directory /workspace/33.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/33.rom_ctrl_corrupt_sig_fatal_chk.2071910246
Short name T47
Test name
Test status
Simulation time 40251280275 ps
CPU time 442.41 seconds
Started Mar 17 01:47:29 PM PDT 24
Finished Mar 17 01:54:53 PM PDT 24
Peak memory 237568 kb
Host smart-d35cca81-78ea-4d70-a6fa-2f71ab999ade
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2071910246 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_
corrupt_sig_fatal_chk.2071910246
Directory /workspace/33.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/33.rom_ctrl_corrupt_sig_fatal_chk.2669282809
Short name T219
Test name
Test status
Simulation time 285900837411 ps
CPU time 326.04 seconds
Started Mar 17 02:40:32 PM PDT 24
Finished Mar 17 02:45:59 PM PDT 24
Peak memory 240148 kb
Host smart-ecd7c76d-08cf-45d4-959e-e964416bba86
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2669282809 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_
corrupt_sig_fatal_chk.2669282809
Directory /workspace/33.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/33.rom_ctrl_kmac_err_chk.1934857389
Short name T251
Test name
Test status
Simulation time 3929517281 ps
CPU time 43.37 seconds
Started Mar 17 02:40:30 PM PDT 24
Finished Mar 17 02:41:15 PM PDT 24
Peak memory 213548 kb
Host smart-2740f038-01f0-4416-bf40-c2b8e0110dbe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1934857389 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_kmac_err_chk.1934857389
Directory /workspace/33.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/33.rom_ctrl_max_throughput_chk.1349684012
Short name T193
Test name
Test status
Simulation time 1174109409 ps
CPU time 17.43 seconds
Started Mar 17 01:47:27 PM PDT 24
Finished Mar 17 01:47:44 PM PDT 24
Peak memory 212480 kb
Host smart-2016e534-4a43-4d4c-8a47-02e321caf939
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1349684012 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_max_throughput_chk.1349684012
Directory /workspace/33.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/33.rom_ctrl_max_throughput_chk.3705531220
Short name T320
Test name
Test status
Simulation time 3861093281 ps
CPU time 31.75 seconds
Started Mar 17 02:40:33 PM PDT 24
Finished Mar 17 02:41:05 PM PDT 24
Peak memory 211368 kb
Host smart-bad6796a-8185-4879-ae19-82271cd196e2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3705531220 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_max_throughput_chk.3705531220
Directory /workspace/33.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/33.rom_ctrl_smoke.2103624300
Short name T136
Test name
Test status
Simulation time 721555570 ps
CPU time 20.35 seconds
Started Mar 17 02:40:30 PM PDT 24
Finished Mar 17 02:40:50 PM PDT 24
Peak memory 216572 kb
Host smart-54173fca-550c-4669-9492-7d800e82d045
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2103624300 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_smoke.2103624300
Directory /workspace/33.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/33.rom_ctrl_stress_all.160699749
Short name T651
Test name
Test status
Simulation time 35971522778 ps
CPU time 97.22 seconds
Started Mar 17 02:40:32 PM PDT 24
Finished Mar 17 02:42:10 PM PDT 24
Peak memory 219212 kb
Host smart-8bb9ef27-5062-4b45-8dab-1c5b8e383dcc
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=160699749 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 33.rom_ctrl_stress_all.160699749
Directory /workspace/33.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/33.rom_ctrl_stress_all.2995585140
Short name T80
Test name
Test status
Simulation time 20042016484 ps
CPU time 98.9 seconds
Started Mar 17 01:47:21 PM PDT 24
Finished Mar 17 01:48:59 PM PDT 24
Peak memory 219168 kb
Host smart-2690c584-8e27-4e66-8c66-cda59b302c83
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2995585140 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 33.rom_ctrl_stress_all.2995585140
Directory /workspace/33.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/33.rom_ctrl_stress_all_with_rand_reset.1190729426
Short name T114
Test name
Test status
Simulation time 15009515353 ps
CPU time 593.19 seconds
Started Mar 17 02:40:40 PM PDT 24
Finished Mar 17 02:50:33 PM PDT 24
Peak memory 235756 kb
Host smart-9190679a-8890-42a7-b1ac-0c08aa2b5802
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1190729426 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_stress_all_with_rand_reset.1190729426
Directory /workspace/33.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.rom_ctrl_alert_test.2582558424
Short name T615
Test name
Test status
Simulation time 7450968013 ps
CPU time 28.93 seconds
Started Mar 17 01:47:32 PM PDT 24
Finished Mar 17 01:48:02 PM PDT 24
Peak memory 212192 kb
Host smart-43475650-c92d-4a64-82e2-d6e2ff1802b3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2582558424 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_alert_test.2582558424
Directory /workspace/34.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/34.rom_ctrl_alert_test.3868060379
Short name T497
Test name
Test status
Simulation time 4154886457 ps
CPU time 31.38 seconds
Started Mar 17 02:40:35 PM PDT 24
Finished Mar 17 02:41:07 PM PDT 24
Peak memory 211784 kb
Host smart-ad616481-26b5-4d66-bb35-09523c5b742b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3868060379 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_alert_test.3868060379
Directory /workspace/34.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/34.rom_ctrl_corrupt_sig_fatal_chk.1514901959
Short name T188
Test name
Test status
Simulation time 89749651096 ps
CPU time 218.28 seconds
Started Mar 17 02:40:33 PM PDT 24
Finished Mar 17 02:44:11 PM PDT 24
Peak memory 236372 kb
Host smart-11384bc3-8208-4b3d-9871-b22e51131245
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1514901959 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_
corrupt_sig_fatal_chk.1514901959
Directory /workspace/34.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/34.rom_ctrl_corrupt_sig_fatal_chk.292694162
Short name T201
Test name
Test status
Simulation time 6385925092 ps
CPU time 192.6 seconds
Started Mar 17 01:47:31 PM PDT 24
Finished Mar 17 01:50:44 PM PDT 24
Peak memory 240452 kb
Host smart-f6cf5744-d65c-45a6-8a21-cdc7f6a53d2c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=292694162 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_c
orrupt_sig_fatal_chk.292694162
Directory /workspace/34.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/34.rom_ctrl_kmac_err_chk.3353494901
Short name T156
Test name
Test status
Simulation time 9361007241 ps
CPU time 47.08 seconds
Started Mar 17 01:47:27 PM PDT 24
Finished Mar 17 01:48:15 PM PDT 24
Peak memory 214776 kb
Host smart-0c505f9d-9279-4b55-bd81-48c9fa4468d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3353494901 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_kmac_err_chk.3353494901
Directory /workspace/34.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/34.rom_ctrl_kmac_err_chk.3773384252
Short name T26
Test name
Test status
Simulation time 2230502178 ps
CPU time 33.36 seconds
Started Mar 17 02:40:37 PM PDT 24
Finished Mar 17 02:41:10 PM PDT 24
Peak memory 214992 kb
Host smart-80b1e99e-edd7-4148-9fdc-5012aefd8489
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3773384252 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_kmac_err_chk.3773384252
Directory /workspace/34.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/34.rom_ctrl_max_throughput_chk.2712581785
Short name T262
Test name
Test status
Simulation time 8037662371 ps
CPU time 28.51 seconds
Started Mar 17 01:47:32 PM PDT 24
Finished Mar 17 01:48:02 PM PDT 24
Peak memory 211384 kb
Host smart-f48f22e1-5529-4da4-a984-1f9ac8a93b74
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2712581785 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_max_throughput_chk.2712581785
Directory /workspace/34.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/34.rom_ctrl_max_throughput_chk.952707992
Short name T458
Test name
Test status
Simulation time 184389986 ps
CPU time 10.54 seconds
Started Mar 17 02:40:37 PM PDT 24
Finished Mar 17 02:40:48 PM PDT 24
Peak memory 212572 kb
Host smart-72d07e01-6b4b-4e10-a727-a7e440971c04
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=952707992 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_max_throughput_chk.952707992
Directory /workspace/34.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/34.rom_ctrl_smoke.1810180636
Short name T517
Test name
Test status
Simulation time 7711936889 ps
CPU time 27.56 seconds
Started Mar 17 02:40:30 PM PDT 24
Finished Mar 17 02:40:58 PM PDT 24
Peak memory 217712 kb
Host smart-e8eda769-9283-4210-b066-ac4cbda826be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1810180636 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_smoke.1810180636
Directory /workspace/34.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/34.rom_ctrl_smoke.2987527743
Short name T249
Test name
Test status
Simulation time 9444405959 ps
CPU time 30.91 seconds
Started Mar 17 01:47:32 PM PDT 24
Finished Mar 17 01:48:04 PM PDT 24
Peak memory 218104 kb
Host smart-38655ae2-4123-44ac-b49c-890aa5796b64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2987527743 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_smoke.2987527743
Directory /workspace/34.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/34.rom_ctrl_stress_all.1385260629
Short name T535
Test name
Test status
Simulation time 100361235948 ps
CPU time 241.08 seconds
Started Mar 17 01:47:26 PM PDT 24
Finished Mar 17 01:51:27 PM PDT 24
Peak memory 220324 kb
Host smart-95866ef6-ac69-43f7-b06e-36c884004d33
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1385260629 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 34.rom_ctrl_stress_all.1385260629
Directory /workspace/34.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/34.rom_ctrl_stress_all.1864607412
Short name T417
Test name
Test status
Simulation time 7877873637 ps
CPU time 46.3 seconds
Started Mar 17 02:40:32 PM PDT 24
Finished Mar 17 02:41:18 PM PDT 24
Peak memory 220736 kb
Host smart-ac6774bb-6bb9-454d-8d61-cfd781003ee6
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1864607412 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 34.rom_ctrl_stress_all.1864607412
Directory /workspace/34.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/35.rom_ctrl_alert_test.1054781806
Short name T187
Test name
Test status
Simulation time 338548390 ps
CPU time 8.44 seconds
Started Mar 17 02:40:36 PM PDT 24
Finished Mar 17 02:40:45 PM PDT 24
Peak memory 211156 kb
Host smart-15356cea-20cc-4d5f-8856-c5d04826763a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1054781806 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_alert_test.1054781806
Directory /workspace/35.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/35.rom_ctrl_alert_test.3274342574
Short name T406
Test name
Test status
Simulation time 81746702825 ps
CPU time 33.47 seconds
Started Mar 17 01:47:30 PM PDT 24
Finished Mar 17 01:48:04 PM PDT 24
Peak memory 212124 kb
Host smart-6ab4f530-3e04-4b5a-bc9d-e8f685973f19
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3274342574 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_alert_test.3274342574
Directory /workspace/35.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/35.rom_ctrl_corrupt_sig_fatal_chk.1522044188
Short name T30
Test name
Test status
Simulation time 4001842789 ps
CPU time 305.93 seconds
Started Mar 17 01:47:28 PM PDT 24
Finished Mar 17 01:52:34 PM PDT 24
Peak memory 239464 kb
Host smart-a4cf24b3-68ed-42cd-b257-ea3011ab6ba7
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1522044188 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_
corrupt_sig_fatal_chk.1522044188
Directory /workspace/35.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/35.rom_ctrl_corrupt_sig_fatal_chk.1886138500
Short name T587
Test name
Test status
Simulation time 12033004976 ps
CPU time 201.48 seconds
Started Mar 17 02:40:35 PM PDT 24
Finished Mar 17 02:43:57 PM PDT 24
Peak memory 233924 kb
Host smart-f8c08bee-f70c-4908-bc60-5c309b0c31de
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1886138500 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_
corrupt_sig_fatal_chk.1886138500
Directory /workspace/35.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/35.rom_ctrl_kmac_err_chk.109707246
Short name T20
Test name
Test status
Simulation time 3000459275 ps
CPU time 19.08 seconds
Started Mar 17 02:40:36 PM PDT 24
Finished Mar 17 02:40:55 PM PDT 24
Peak memory 214576 kb
Host smart-906c8347-cf35-4d04-87f1-72a1702cdaee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=109707246 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_kmac_err_chk.109707246
Directory /workspace/35.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/35.rom_ctrl_kmac_err_chk.2058010633
Short name T616
Test name
Test status
Simulation time 37219370622 ps
CPU time 68.76 seconds
Started Mar 17 01:47:30 PM PDT 24
Finished Mar 17 01:48:40 PM PDT 24
Peak memory 214968 kb
Host smart-643ac05f-4a9d-43b6-bb60-0085f3d55655
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2058010633 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_kmac_err_chk.2058010633
Directory /workspace/35.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/35.rom_ctrl_max_throughput_chk.122784733
Short name T576
Test name
Test status
Simulation time 5573849096 ps
CPU time 15.04 seconds
Started Mar 17 01:47:27 PM PDT 24
Finished Mar 17 01:47:43 PM PDT 24
Peak memory 211684 kb
Host smart-ba723391-fe3c-4acd-8b68-fc7c8d6f1771
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=122784733 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_max_throughput_chk.122784733
Directory /workspace/35.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/35.rom_ctrl_max_throughput_chk.3183521257
Short name T460
Test name
Test status
Simulation time 214398823 ps
CPU time 10.52 seconds
Started Mar 17 02:40:36 PM PDT 24
Finished Mar 17 02:40:46 PM PDT 24
Peak memory 212164 kb
Host smart-cce58b86-a20e-4872-b195-1a356da0ea1a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3183521257 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_max_throughput_chk.3183521257
Directory /workspace/35.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/35.rom_ctrl_smoke.1788034836
Short name T600
Test name
Test status
Simulation time 29664696262 ps
CPU time 63.96 seconds
Started Mar 17 01:47:30 PM PDT 24
Finished Mar 17 01:48:35 PM PDT 24
Peak memory 217744 kb
Host smart-0639792a-b996-433e-b1a1-52bb820c0d36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1788034836 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_smoke.1788034836
Directory /workspace/35.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/35.rom_ctrl_smoke.2991550188
Short name T328
Test name
Test status
Simulation time 10094930137 ps
CPU time 55.33 seconds
Started Mar 17 02:40:37 PM PDT 24
Finished Mar 17 02:41:33 PM PDT 24
Peak memory 218208 kb
Host smart-e91aed2e-50cf-4907-894d-a3b94d554924
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2991550188 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_smoke.2991550188
Directory /workspace/35.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/35.rom_ctrl_stress_all.2670541293
Short name T374
Test name
Test status
Simulation time 38059589891 ps
CPU time 169.13 seconds
Started Mar 17 02:40:36 PM PDT 24
Finished Mar 17 02:43:25 PM PDT 24
Peak memory 222308 kb
Host smart-cf27e6dc-a7c1-4af6-bb04-be0c16ee08ef
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2670541293 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 35.rom_ctrl_stress_all.2670541293
Directory /workspace/35.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/35.rom_ctrl_stress_all.2995874450
Short name T380
Test name
Test status
Simulation time 10686889518 ps
CPU time 62.65 seconds
Started Mar 17 01:47:28 PM PDT 24
Finished Mar 17 01:48:31 PM PDT 24
Peak memory 218456 kb
Host smart-f782a24a-a014-49e6-bcf6-848553c170ef
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2995874450 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 35.rom_ctrl_stress_all.2995874450
Directory /workspace/35.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/36.rom_ctrl_alert_test.3723471030
Short name T612
Test name
Test status
Simulation time 2389641990 ps
CPU time 22.89 seconds
Started Mar 17 02:40:37 PM PDT 24
Finished Mar 17 02:41:00 PM PDT 24
Peak memory 211800 kb
Host smart-7720e106-eed9-4210-982b-84019d8de967
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3723471030 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_alert_test.3723471030
Directory /workspace/36.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/36.rom_ctrl_alert_test.83040278
Short name T586
Test name
Test status
Simulation time 169207287 ps
CPU time 8.43 seconds
Started Mar 17 01:47:31 PM PDT 24
Finished Mar 17 01:47:40 PM PDT 24
Peak memory 211096 kb
Host smart-21b1e453-eca5-45f8-8c7a-d8bac4b9aaf7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=83040278 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_alert_test.83040278
Directory /workspace/36.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/36.rom_ctrl_corrupt_sig_fatal_chk.2014590296
Short name T610
Test name
Test status
Simulation time 34432916380 ps
CPU time 211.43 seconds
Started Mar 17 01:47:28 PM PDT 24
Finished Mar 17 01:50:59 PM PDT 24
Peak memory 229320 kb
Host smart-86acbf4f-8bf8-4cfc-90d3-bd3aa533ee21
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2014590296 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_
corrupt_sig_fatal_chk.2014590296
Directory /workspace/36.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/36.rom_ctrl_corrupt_sig_fatal_chk.2699904816
Short name T301
Test name
Test status
Simulation time 64645572919 ps
CPU time 675.4 seconds
Started Mar 17 02:40:33 PM PDT 24
Finished Mar 17 02:51:49 PM PDT 24
Peak memory 238416 kb
Host smart-95b4003a-7cd9-464f-bd11-3185b35d3ad0
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2699904816 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_
corrupt_sig_fatal_chk.2699904816
Directory /workspace/36.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/36.rom_ctrl_kmac_err_chk.121728810
Short name T314
Test name
Test status
Simulation time 7213672227 ps
CPU time 62.03 seconds
Started Mar 17 02:40:36 PM PDT 24
Finished Mar 17 02:41:38 PM PDT 24
Peak memory 214888 kb
Host smart-3da8899a-4528-409b-a70a-df68321b2bac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=121728810 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_kmac_err_chk.121728810
Directory /workspace/36.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/36.rom_ctrl_kmac_err_chk.1819515625
Short name T384
Test name
Test status
Simulation time 14675619791 ps
CPU time 61.07 seconds
Started Mar 17 01:47:31 PM PDT 24
Finished Mar 17 01:48:33 PM PDT 24
Peak memory 213952 kb
Host smart-4b5d84fc-53d3-4ab3-911b-e5a511f01e4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1819515625 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_kmac_err_chk.1819515625
Directory /workspace/36.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/36.rom_ctrl_max_throughput_chk.1617573658
Short name T222
Test name
Test status
Simulation time 434766794 ps
CPU time 13.63 seconds
Started Mar 17 01:47:27 PM PDT 24
Finished Mar 17 01:47:40 PM PDT 24
Peak memory 211180 kb
Host smart-880448bc-0330-4c3d-90e0-5dacf75590b3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1617573658 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_max_throughput_chk.1617573658
Directory /workspace/36.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/36.rom_ctrl_max_throughput_chk.599967493
Short name T674
Test name
Test status
Simulation time 186890795 ps
CPU time 10.5 seconds
Started Mar 17 02:40:35 PM PDT 24
Finished Mar 17 02:40:46 PM PDT 24
Peak memory 212320 kb
Host smart-baf3e866-466d-4662-9da1-e035e3a9a54d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=599967493 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_max_throughput_chk.599967493
Directory /workspace/36.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/36.rom_ctrl_smoke.1035671148
Short name T682
Test name
Test status
Simulation time 8504648188 ps
CPU time 78.55 seconds
Started Mar 17 01:47:30 PM PDT 24
Finished Mar 17 01:48:50 PM PDT 24
Peak memory 214788 kb
Host smart-804db42d-b413-4990-8b96-2dcdaa7a998a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1035671148 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_smoke.1035671148
Directory /workspace/36.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/36.rom_ctrl_smoke.1530500880
Short name T418
Test name
Test status
Simulation time 14338597093 ps
CPU time 62.36 seconds
Started Mar 17 02:40:36 PM PDT 24
Finished Mar 17 02:41:38 PM PDT 24
Peak memory 217324 kb
Host smart-39e57b57-54da-43da-9965-821adc210bc7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1530500880 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_smoke.1530500880
Directory /workspace/36.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/36.rom_ctrl_stress_all.1297362106
Short name T372
Test name
Test status
Simulation time 74109360270 ps
CPU time 68.69 seconds
Started Mar 17 02:40:34 PM PDT 24
Finished Mar 17 02:41:43 PM PDT 24
Peak memory 216764 kb
Host smart-24fc00aa-0dba-4bcd-8817-ab65fc9af417
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1297362106 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 36.rom_ctrl_stress_all.1297362106
Directory /workspace/36.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/36.rom_ctrl_stress_all.2682448637
Short name T519
Test name
Test status
Simulation time 3102026074 ps
CPU time 42.5 seconds
Started Mar 17 01:47:28 PM PDT 24
Finished Mar 17 01:48:10 PM PDT 24
Peak memory 218700 kb
Host smart-897091c5-ec55-40f1-b773-b88a6ec03a53
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2682448637 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 36.rom_ctrl_stress_all.2682448637
Directory /workspace/36.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/37.rom_ctrl_alert_test.3210466238
Short name T558
Test name
Test status
Simulation time 4038565001 ps
CPU time 31.49 seconds
Started Mar 17 01:47:33 PM PDT 24
Finished Mar 17 01:48:05 PM PDT 24
Peak memory 211736 kb
Host smart-fbac582b-be88-4a7f-9d7d-7d1e90323e70
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3210466238 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_alert_test.3210466238
Directory /workspace/37.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/37.rom_ctrl_alert_test.3726160739
Short name T60
Test name
Test status
Simulation time 4104026944 ps
CPU time 33.45 seconds
Started Mar 17 02:40:35 PM PDT 24
Finished Mar 17 02:41:09 PM PDT 24
Peak memory 211292 kb
Host smart-7ddcfa40-2060-44a9-a936-9b6dc1c7cbf8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3726160739 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_alert_test.3726160739
Directory /workspace/37.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/37.rom_ctrl_corrupt_sig_fatal_chk.2753074898
Short name T527
Test name
Test status
Simulation time 8531948085 ps
CPU time 302.86 seconds
Started Mar 17 02:40:36 PM PDT 24
Finished Mar 17 02:45:39 PM PDT 24
Peak memory 238576 kb
Host smart-5f6fd2c6-7287-4621-9b6c-cfd03926106b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2753074898 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_
corrupt_sig_fatal_chk.2753074898
Directory /workspace/37.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/37.rom_ctrl_corrupt_sig_fatal_chk.919363898
Short name T281
Test name
Test status
Simulation time 3752478831 ps
CPU time 231.77 seconds
Started Mar 17 01:47:30 PM PDT 24
Finished Mar 17 01:51:23 PM PDT 24
Peak memory 228300 kb
Host smart-29359ed3-0842-4fc7-b0ec-68da19379655
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=919363898 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_c
orrupt_sig_fatal_chk.919363898
Directory /workspace/37.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/37.rom_ctrl_kmac_err_chk.1835433341
Short name T446
Test name
Test status
Simulation time 2063343749 ps
CPU time 21.9 seconds
Started Mar 17 01:47:31 PM PDT 24
Finished Mar 17 01:47:54 PM PDT 24
Peak memory 214556 kb
Host smart-2a723970-b793-4723-b6a9-e0d4c82e61ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1835433341 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_kmac_err_chk.1835433341
Directory /workspace/37.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/37.rom_ctrl_kmac_err_chk.679397703
Short name T605
Test name
Test status
Simulation time 8794769500 ps
CPU time 69.39 seconds
Started Mar 17 02:40:37 PM PDT 24
Finished Mar 17 02:41:46 PM PDT 24
Peak memory 214856 kb
Host smart-03d7fff5-5aad-46a0-a654-9dd7772ba3dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=679397703 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_kmac_err_chk.679397703
Directory /workspace/37.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/37.rom_ctrl_max_throughput_chk.1524998046
Short name T396
Test name
Test status
Simulation time 6253602016 ps
CPU time 20.57 seconds
Started Mar 17 02:40:33 PM PDT 24
Finished Mar 17 02:40:54 PM PDT 24
Peak memory 212724 kb
Host smart-a38db7ea-6499-443e-95d2-8725b8a54950
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1524998046 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_max_throughput_chk.1524998046
Directory /workspace/37.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/37.rom_ctrl_max_throughput_chk.3727216281
Short name T207
Test name
Test status
Simulation time 7570082813 ps
CPU time 21.74 seconds
Started Mar 17 01:47:28 PM PDT 24
Finished Mar 17 01:47:50 PM PDT 24
Peak memory 212772 kb
Host smart-ec580ddd-6b1a-491c-b838-a5a2470c7386
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3727216281 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_max_throughput_chk.3727216281
Directory /workspace/37.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/37.rom_ctrl_smoke.3939235022
Short name T403
Test name
Test status
Simulation time 5065694048 ps
CPU time 41.32 seconds
Started Mar 17 01:47:28 PM PDT 24
Finished Mar 17 01:48:09 PM PDT 24
Peak memory 218112 kb
Host smart-135425e9-5d55-4bab-b7e1-18f57c640fb2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3939235022 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_smoke.3939235022
Directory /workspace/37.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/37.rom_ctrl_smoke.479819965
Short name T485
Test name
Test status
Simulation time 3821531576 ps
CPU time 20.43 seconds
Started Mar 17 02:40:36 PM PDT 24
Finished Mar 17 02:40:57 PM PDT 24
Peak memory 217332 kb
Host smart-e32f1b24-e31b-41f9-8a3f-3e9539110eea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=479819965 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_smoke.479819965
Directory /workspace/37.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/37.rom_ctrl_stress_all.1431840814
Short name T82
Test name
Test status
Simulation time 5500591977 ps
CPU time 22.63 seconds
Started Mar 17 01:47:30 PM PDT 24
Finished Mar 17 01:47:54 PM PDT 24
Peak memory 214016 kb
Host smart-997f4d96-a94a-409f-be2c-6ec4c859b4e7
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1431840814 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 37.rom_ctrl_stress_all.1431840814
Directory /workspace/37.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/37.rom_ctrl_stress_all.2343136129
Short name T593
Test name
Test status
Simulation time 1477845513 ps
CPU time 43.12 seconds
Started Mar 17 02:40:35 PM PDT 24
Finished Mar 17 02:41:19 PM PDT 24
Peak memory 219196 kb
Host smart-4ddc9dee-6211-476f-acb7-df055cd0f09d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2343136129 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 37.rom_ctrl_stress_all.2343136129
Directory /workspace/37.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/38.rom_ctrl_alert_test.594385658
Short name T435
Test name
Test status
Simulation time 1441428938 ps
CPU time 10.72 seconds
Started Mar 17 01:47:33 PM PDT 24
Finished Mar 17 01:47:44 PM PDT 24
Peak memory 211120 kb
Host smart-822a1203-dad4-459d-8d5b-a3f74f167d2a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=594385658 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_alert_test.594385658
Directory /workspace/38.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/38.rom_ctrl_alert_test.628427917
Short name T132
Test name
Test status
Simulation time 689035104 ps
CPU time 8.48 seconds
Started Mar 17 02:40:34 PM PDT 24
Finished Mar 17 02:40:43 PM PDT 24
Peak memory 211244 kb
Host smart-481c1c8c-25e5-4188-b223-4d939f655f35
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=628427917 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_alert_test.628427917
Directory /workspace/38.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/38.rom_ctrl_corrupt_sig_fatal_chk.243224321
Short name T524
Test name
Test status
Simulation time 7922524018 ps
CPU time 262.42 seconds
Started Mar 17 01:47:27 PM PDT 24
Finished Mar 17 01:51:50 PM PDT 24
Peak memory 218604 kb
Host smart-70030053-8308-42a9-a7f4-d508317961a6
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=243224321 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_c
orrupt_sig_fatal_chk.243224321
Directory /workspace/38.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/38.rom_ctrl_corrupt_sig_fatal_chk.3965932707
Short name T235
Test name
Test status
Simulation time 345719240468 ps
CPU time 837.62 seconds
Started Mar 17 02:40:34 PM PDT 24
Finished Mar 17 02:54:32 PM PDT 24
Peak memory 233444 kb
Host smart-78b0588b-797a-4c90-835d-a45859545379
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3965932707 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_
corrupt_sig_fatal_chk.3965932707
Directory /workspace/38.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/38.rom_ctrl_kmac_err_chk.123063650
Short name T332
Test name
Test status
Simulation time 36418465096 ps
CPU time 40.69 seconds
Started Mar 17 01:47:31 PM PDT 24
Finished Mar 17 01:48:13 PM PDT 24
Peak memory 215428 kb
Host smart-4a72dc05-900a-401e-b77e-0c429f291700
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=123063650 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_kmac_err_chk.123063650
Directory /workspace/38.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/38.rom_ctrl_kmac_err_chk.2962342642
Short name T355
Test name
Test status
Simulation time 6816387663 ps
CPU time 40.67 seconds
Started Mar 17 02:40:33 PM PDT 24
Finished Mar 17 02:41:14 PM PDT 24
Peak memory 215140 kb
Host smart-a16a6cbc-1528-4c8a-9ab4-f00b524a519b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2962342642 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_kmac_err_chk.2962342642
Directory /workspace/38.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/38.rom_ctrl_max_throughput_chk.2870986372
Short name T370
Test name
Test status
Simulation time 13147712973 ps
CPU time 26.75 seconds
Started Mar 17 01:47:27 PM PDT 24
Finished Mar 17 01:47:54 PM PDT 24
Peak memory 211784 kb
Host smart-ffed35b7-43cc-4476-a9c8-d99d0fbbd40b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2870986372 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_max_throughput_chk.2870986372
Directory /workspace/38.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/38.rom_ctrl_max_throughput_chk.799580919
Short name T657
Test name
Test status
Simulation time 190106931 ps
CPU time 10.36 seconds
Started Mar 17 02:40:35 PM PDT 24
Finished Mar 17 02:40:46 PM PDT 24
Peak memory 211384 kb
Host smart-50c6ca5b-d28c-4fed-bb25-b2ff23d89296
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=799580919 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_max_throughput_chk.799580919
Directory /workspace/38.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/38.rom_ctrl_smoke.1296778783
Short name T226
Test name
Test status
Simulation time 358596814 ps
CPU time 19.7 seconds
Started Mar 17 01:47:31 PM PDT 24
Finished Mar 17 01:47:51 PM PDT 24
Peak memory 216560 kb
Host smart-84df8c29-b479-42e2-8e6d-11a2fad723c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1296778783 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_smoke.1296778783
Directory /workspace/38.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/38.rom_ctrl_smoke.1603233928
Short name T488
Test name
Test status
Simulation time 22570566039 ps
CPU time 54.86 seconds
Started Mar 17 02:40:34 PM PDT 24
Finished Mar 17 02:41:30 PM PDT 24
Peak memory 215900 kb
Host smart-cf238cf2-6701-4dda-9146-f078a3fba888
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1603233928 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_smoke.1603233928
Directory /workspace/38.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/38.rom_ctrl_stress_all.2496176729
Short name T138
Test name
Test status
Simulation time 11389782584 ps
CPU time 93.15 seconds
Started Mar 17 01:47:30 PM PDT 24
Finished Mar 17 01:49:04 PM PDT 24
Peak memory 219568 kb
Host smart-80b54be2-13ee-4d2a-a7de-b19bc701f6d0
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2496176729 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 38.rom_ctrl_stress_all.2496176729
Directory /workspace/38.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/38.rom_ctrl_stress_all.575289563
Short name T557
Test name
Test status
Simulation time 23652361962 ps
CPU time 49.13 seconds
Started Mar 17 02:40:35 PM PDT 24
Finished Mar 17 02:41:25 PM PDT 24
Peak memory 218024 kb
Host smart-8e029e35-0736-4d59-bb29-4b9b75f9e371
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=575289563 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 38.rom_ctrl_stress_all.575289563
Directory /workspace/38.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/39.rom_ctrl_alert_test.106641693
Short name T335
Test name
Test status
Simulation time 1202281632 ps
CPU time 16.23 seconds
Started Mar 17 01:47:31 PM PDT 24
Finished Mar 17 01:47:48 PM PDT 24
Peak memory 211116 kb
Host smart-3aa3aac6-033b-42ad-b8e1-e13371b0c1ab
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=106641693 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_alert_test.106641693
Directory /workspace/39.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/39.rom_ctrl_alert_test.1386767986
Short name T416
Test name
Test status
Simulation time 1657036380 ps
CPU time 18.41 seconds
Started Mar 17 02:40:43 PM PDT 24
Finished Mar 17 02:41:02 PM PDT 24
Peak memory 211704 kb
Host smart-52c6b41f-5877-479d-902c-3f558986c6ca
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1386767986 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_alert_test.1386767986
Directory /workspace/39.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/39.rom_ctrl_corrupt_sig_fatal_chk.2747890618
Short name T382
Test name
Test status
Simulation time 27674934777 ps
CPU time 488.75 seconds
Started Mar 17 01:47:30 PM PDT 24
Finished Mar 17 01:55:40 PM PDT 24
Peak memory 225448 kb
Host smart-cd20a000-a42a-432e-8f5c-a00d5e5ff4c4
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2747890618 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_
corrupt_sig_fatal_chk.2747890618
Directory /workspace/39.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/39.rom_ctrl_corrupt_sig_fatal_chk.4246393366
Short name T588
Test name
Test status
Simulation time 1653952021 ps
CPU time 135.54 seconds
Started Mar 17 02:40:34 PM PDT 24
Finished Mar 17 02:42:50 PM PDT 24
Peak memory 228124 kb
Host smart-d3129a48-183c-41f1-bb44-cce72e7effde
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4246393366 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_
corrupt_sig_fatal_chk.4246393366
Directory /workspace/39.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/39.rom_ctrl_kmac_err_chk.2779990699
Short name T590
Test name
Test status
Simulation time 5068491722 ps
CPU time 49.41 seconds
Started Mar 17 01:47:26 PM PDT 24
Finished Mar 17 01:48:15 PM PDT 24
Peak memory 215128 kb
Host smart-d952236a-abf8-4b65-9a36-0d7ad9885b75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2779990699 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_kmac_err_chk.2779990699
Directory /workspace/39.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/39.rom_ctrl_kmac_err_chk.3411254349
Short name T480
Test name
Test status
Simulation time 32723816663 ps
CPU time 65.67 seconds
Started Mar 17 02:40:37 PM PDT 24
Finished Mar 17 02:41:43 PM PDT 24
Peak memory 214840 kb
Host smart-ce0946e2-aee4-40b3-89ad-5e28f8250871
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3411254349 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_kmac_err_chk.3411254349
Directory /workspace/39.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/39.rom_ctrl_max_throughput_chk.1884410532
Short name T175
Test name
Test status
Simulation time 613391482 ps
CPU time 14.61 seconds
Started Mar 17 02:40:36 PM PDT 24
Finished Mar 17 02:40:51 PM PDT 24
Peak memory 211456 kb
Host smart-76b350e8-0671-4a23-9a90-821f98f10b6c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1884410532 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_max_throughput_chk.1884410532
Directory /workspace/39.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/39.rom_ctrl_max_throughput_chk.449797677
Short name T570
Test name
Test status
Simulation time 2280842070 ps
CPU time 23.99 seconds
Started Mar 17 01:47:27 PM PDT 24
Finished Mar 17 01:47:51 PM PDT 24
Peak memory 211252 kb
Host smart-4ebc8806-c2ee-49bf-a3de-d232a0855809
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=449797677 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_max_throughput_chk.449797677
Directory /workspace/39.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/39.rom_ctrl_smoke.147338449
Short name T438
Test name
Test status
Simulation time 26427758509 ps
CPU time 71.48 seconds
Started Mar 17 02:40:36 PM PDT 24
Finished Mar 17 02:41:48 PM PDT 24
Peak memory 218372 kb
Host smart-56fd9523-92e4-4968-92d1-01a00a3f3750
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=147338449 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_smoke.147338449
Directory /workspace/39.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/39.rom_ctrl_smoke.2188923409
Short name T8
Test name
Test status
Simulation time 363603554 ps
CPU time 19.57 seconds
Started Mar 17 01:47:30 PM PDT 24
Finished Mar 17 01:47:51 PM PDT 24
Peak memory 217320 kb
Host smart-3cf0f8e4-a57b-425f-9ce7-97e68dbadbea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2188923409 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_smoke.2188923409
Directory /workspace/39.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/39.rom_ctrl_stress_all.2266408181
Short name T617
Test name
Test status
Simulation time 3050801498 ps
CPU time 62.65 seconds
Started Mar 17 01:47:28 PM PDT 24
Finished Mar 17 01:48:31 PM PDT 24
Peak memory 220776 kb
Host smart-5b8ba2c0-29b7-457f-8617-49ad08ba30d2
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2266408181 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 39.rom_ctrl_stress_all.2266408181
Directory /workspace/39.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/39.rom_ctrl_stress_all.3575409000
Short name T151
Test name
Test status
Simulation time 42919659122 ps
CPU time 111.25 seconds
Started Mar 17 02:40:33 PM PDT 24
Finished Mar 17 02:42:25 PM PDT 24
Peak memory 219308 kb
Host smart-1dc66694-b0e3-4966-b1fc-c6b682dcc48d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3575409000 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 39.rom_ctrl_stress_all.3575409000
Directory /workspace/39.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/4.rom_ctrl_alert_test.624282526
Short name T197
Test name
Test status
Simulation time 174430054 ps
CPU time 8.43 seconds
Started Mar 17 02:39:57 PM PDT 24
Finished Mar 17 02:40:06 PM PDT 24
Peak memory 211248 kb
Host smart-f365fe4a-c94e-468b-bef8-a9ee383baa16
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=624282526 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_alert_test.624282526
Directory /workspace/4.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/4.rom_ctrl_alert_test.692755966
Short name T503
Test name
Test status
Simulation time 661696115 ps
CPU time 8.49 seconds
Started Mar 17 01:46:54 PM PDT 24
Finished Mar 17 01:47:03 PM PDT 24
Peak memory 211216 kb
Host smart-3b233217-1666-4aa2-a0ed-463f0230af54
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=692755966 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_alert_test.692755966
Directory /workspace/4.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/4.rom_ctrl_corrupt_sig_fatal_chk.3636886620
Short name T365
Test name
Test status
Simulation time 370644225952 ps
CPU time 948.7 seconds
Started Mar 17 02:40:01 PM PDT 24
Finished Mar 17 02:55:50 PM PDT 24
Peak memory 224760 kb
Host smart-bb125bbd-9417-4c57-bb67-5805eb136f1c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3636886620 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_c
orrupt_sig_fatal_chk.3636886620
Directory /workspace/4.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/4.rom_ctrl_corrupt_sig_fatal_chk.3790584674
Short name T499
Test name
Test status
Simulation time 193262807289 ps
CPU time 391.22 seconds
Started Mar 17 01:46:45 PM PDT 24
Finished Mar 17 01:53:18 PM PDT 24
Peak memory 227316 kb
Host smart-26d31376-a16b-4576-ba56-b9951b9e9b28
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3790584674 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_c
orrupt_sig_fatal_chk.3790584674
Directory /workspace/4.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/4.rom_ctrl_kmac_err_chk.1072518909
Short name T163
Test name
Test status
Simulation time 35625060079 ps
CPU time 68.81 seconds
Started Mar 17 02:40:00 PM PDT 24
Finished Mar 17 02:41:09 PM PDT 24
Peak memory 214956 kb
Host smart-018c0092-c633-4272-ad08-9259d14f4bcc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1072518909 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_kmac_err_chk.1072518909
Directory /workspace/4.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/4.rom_ctrl_kmac_err_chk.110458807
Short name T620
Test name
Test status
Simulation time 332648737 ps
CPU time 19.85 seconds
Started Mar 17 01:46:54 PM PDT 24
Finished Mar 17 01:47:14 PM PDT 24
Peak memory 214520 kb
Host smart-931f1585-80cd-4d1b-a277-e4712a14d339
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=110458807 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_kmac_err_chk.110458807
Directory /workspace/4.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/4.rom_ctrl_max_throughput_chk.3261047164
Short name T598
Test name
Test status
Simulation time 1167739665 ps
CPU time 16.81 seconds
Started Mar 17 02:39:59 PM PDT 24
Finished Mar 17 02:40:16 PM PDT 24
Peak memory 211316 kb
Host smart-a94981ae-9974-446e-84c4-d24aca818f4a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3261047164 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_max_throughput_chk.3261047164
Directory /workspace/4.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/4.rom_ctrl_max_throughput_chk.500773448
Short name T214
Test name
Test status
Simulation time 4740763337 ps
CPU time 23.87 seconds
Started Mar 17 01:46:58 PM PDT 24
Finished Mar 17 01:47:22 PM PDT 24
Peak memory 211296 kb
Host smart-72e18df1-bc22-430e-b450-fa4d9497a1e1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=500773448 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_max_throughput_chk.500773448
Directory /workspace/4.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/4.rom_ctrl_sec_cm.2604208619
Short name T39
Test name
Test status
Simulation time 3715002390 ps
CPU time 142.32 seconds
Started Mar 17 02:39:58 PM PDT 24
Finished Mar 17 02:42:20 PM PDT 24
Peak memory 238992 kb
Host smart-3b76c7a9-ad2b-43f2-93e2-a4e2dc0321c1
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2604208619 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_sec_cm.2604208619
Directory /workspace/4.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/4.rom_ctrl_sec_cm.3818856956
Short name T43
Test name
Test status
Simulation time 2013454252 ps
CPU time 236.99 seconds
Started Mar 17 01:46:50 PM PDT 24
Finished Mar 17 01:50:48 PM PDT 24
Peak memory 236364 kb
Host smart-f83460c3-62f9-42d1-af94-8e04d952d5a9
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3818856956 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_sec_cm.3818856956
Directory /workspace/4.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/4.rom_ctrl_smoke.1925404294
Short name T479
Test name
Test status
Simulation time 2174636396 ps
CPU time 37.41 seconds
Started Mar 17 02:40:00 PM PDT 24
Finished Mar 17 02:40:38 PM PDT 24
Peak memory 216356 kb
Host smart-770803fb-4775-4361-bb17-368b2e21993e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1925404294 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_smoke.1925404294
Directory /workspace/4.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/4.rom_ctrl_stress_all.148420439
Short name T679
Test name
Test status
Simulation time 26776885631 ps
CPU time 69.42 seconds
Started Mar 17 01:46:47 PM PDT 24
Finished Mar 17 01:47:57 PM PDT 24
Peak memory 219328 kb
Host smart-695b0853-767c-4a05-acd1-90527801eeb1
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=148420439 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 4.rom_ctrl_stress_all.148420439
Directory /workspace/4.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/4.rom_ctrl_stress_all.3636311419
Short name T342
Test name
Test status
Simulation time 1460593871 ps
CPU time 40.67 seconds
Started Mar 17 02:39:57 PM PDT 24
Finished Mar 17 02:40:38 PM PDT 24
Peak memory 219272 kb
Host smart-13c61eab-aaf8-434b-95ca-90942a63aac1
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3636311419 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 4.rom_ctrl_stress_all.3636311419
Directory /workspace/4.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/40.rom_ctrl_alert_test.1281200223
Short name T398
Test name
Test status
Simulation time 338561748 ps
CPU time 8.38 seconds
Started Mar 17 01:47:31 PM PDT 24
Finished Mar 17 01:47:40 PM PDT 24
Peak memory 211180 kb
Host smart-f3c8a166-7461-463f-9506-ac3543557ca2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1281200223 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_alert_test.1281200223
Directory /workspace/40.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/40.rom_ctrl_alert_test.4209461288
Short name T183
Test name
Test status
Simulation time 1374219795 ps
CPU time 8.19 seconds
Started Mar 17 02:40:42 PM PDT 24
Finished Mar 17 02:40:51 PM PDT 24
Peak memory 211244 kb
Host smart-1c801917-c9f8-40ac-a283-4cf19a6fe438
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4209461288 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_alert_test.4209461288
Directory /workspace/40.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/40.rom_ctrl_corrupt_sig_fatal_chk.1112714244
Short name T432
Test name
Test status
Simulation time 3401825575 ps
CPU time 258.62 seconds
Started Mar 17 02:40:34 PM PDT 24
Finished Mar 17 02:44:53 PM PDT 24
Peak memory 239496 kb
Host smart-d9ed71e6-2ceb-4e3b-bb29-7ebbe2fa34ed
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1112714244 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_
corrupt_sig_fatal_chk.1112714244
Directory /workspace/40.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/40.rom_ctrl_corrupt_sig_fatal_chk.1632768453
Short name T322
Test name
Test status
Simulation time 23402603375 ps
CPU time 379.2 seconds
Started Mar 17 01:47:29 PM PDT 24
Finished Mar 17 01:53:49 PM PDT 24
Peak memory 237576 kb
Host smart-67e2d11a-76cd-4fcd-a414-046756fd4e20
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1632768453 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_
corrupt_sig_fatal_chk.1632768453
Directory /workspace/40.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/40.rom_ctrl_kmac_err_chk.2300925265
Short name T634
Test name
Test status
Simulation time 1163949012 ps
CPU time 27.6 seconds
Started Mar 17 01:47:30 PM PDT 24
Finished Mar 17 01:47:59 PM PDT 24
Peak memory 214636 kb
Host smart-e40790da-aeaf-452b-a5f6-7c10314b6980
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2300925265 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_kmac_err_chk.2300925265
Directory /workspace/40.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/40.rom_ctrl_kmac_err_chk.708825785
Short name T430
Test name
Test status
Simulation time 5074501148 ps
CPU time 50.7 seconds
Started Mar 17 02:40:34 PM PDT 24
Finished Mar 17 02:41:26 PM PDT 24
Peak memory 214268 kb
Host smart-80feb3ed-e10d-4ab2-8465-de29242e3871
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=708825785 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_kmac_err_chk.708825785
Directory /workspace/40.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/40.rom_ctrl_max_throughput_chk.136842461
Short name T646
Test name
Test status
Simulation time 11810882251 ps
CPU time 28.32 seconds
Started Mar 17 01:47:32 PM PDT 24
Finished Mar 17 01:48:02 PM PDT 24
Peak memory 211284 kb
Host smart-3ba27d6e-c60f-4fcc-938b-12d0fd64b6c1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=136842461 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_max_throughput_chk.136842461
Directory /workspace/40.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/40.rom_ctrl_max_throughput_chk.1655488741
Short name T606
Test name
Test status
Simulation time 12744379874 ps
CPU time 28.28 seconds
Started Mar 17 02:40:36 PM PDT 24
Finished Mar 17 02:41:04 PM PDT 24
Peak memory 211324 kb
Host smart-e96c51f3-333b-4f92-b6aa-709012c4c4a2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1655488741 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_max_throughput_chk.1655488741
Directory /workspace/40.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/40.rom_ctrl_smoke.1478595303
Short name T79
Test name
Test status
Simulation time 7867098424 ps
CPU time 75.9 seconds
Started Mar 17 02:40:35 PM PDT 24
Finished Mar 17 02:41:51 PM PDT 24
Peak memory 215268 kb
Host smart-754f7e7a-7e33-4d31-83f8-90a24d929997
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1478595303 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_smoke.1478595303
Directory /workspace/40.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/40.rom_ctrl_smoke.3056788341
Short name T315
Test name
Test status
Simulation time 2827627994 ps
CPU time 22.94 seconds
Started Mar 17 01:47:32 PM PDT 24
Finished Mar 17 01:47:56 PM PDT 24
Peak memory 217688 kb
Host smart-f8d73936-2f41-4bc9-ac28-f7f0b62e0211
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3056788341 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_smoke.3056788341
Directory /workspace/40.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/40.rom_ctrl_stress_all.1574056538
Short name T470
Test name
Test status
Simulation time 117742593273 ps
CPU time 161.19 seconds
Started Mar 17 01:47:29 PM PDT 24
Finished Mar 17 01:50:10 PM PDT 24
Peak memory 219988 kb
Host smart-2b7a564a-df26-49ea-834e-6ce2e40406f3
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1574056538 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 40.rom_ctrl_stress_all.1574056538
Directory /workspace/40.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/40.rom_ctrl_stress_all.1630590013
Short name T680
Test name
Test status
Simulation time 2450244053 ps
CPU time 15.96 seconds
Started Mar 17 02:40:36 PM PDT 24
Finished Mar 17 02:40:52 PM PDT 24
Peak memory 212376 kb
Host smart-2073b7c3-2b31-468e-82b4-e64f6868d108
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1630590013 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 40.rom_ctrl_stress_all.1630590013
Directory /workspace/40.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/41.rom_ctrl_alert_test.1812965629
Short name T409
Test name
Test status
Simulation time 496715633 ps
CPU time 9.88 seconds
Started Mar 17 01:47:29 PM PDT 24
Finished Mar 17 01:47:39 PM PDT 24
Peak memory 211244 kb
Host smart-a6d410dc-ba1f-4eae-bd84-8e87310fe670
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1812965629 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_alert_test.1812965629
Directory /workspace/41.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/41.rom_ctrl_alert_test.1922387871
Short name T263
Test name
Test status
Simulation time 4589526442 ps
CPU time 15.56 seconds
Started Mar 17 02:40:45 PM PDT 24
Finished Mar 17 02:41:01 PM PDT 24
Peak memory 211236 kb
Host smart-644801f9-3ae4-4a6e-9249-7354d3569206
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1922387871 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_alert_test.1922387871
Directory /workspace/41.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/41.rom_ctrl_corrupt_sig_fatal_chk.1790576930
Short name T672
Test name
Test status
Simulation time 98403124918 ps
CPU time 344.28 seconds
Started Mar 17 01:47:32 PM PDT 24
Finished Mar 17 01:53:17 PM PDT 24
Peak memory 227436 kb
Host smart-09e7e564-1400-411e-bc07-e17517f02f59
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1790576930 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_
corrupt_sig_fatal_chk.1790576930
Directory /workspace/41.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/41.rom_ctrl_corrupt_sig_fatal_chk.3045265104
Short name T298
Test name
Test status
Simulation time 11797318162 ps
CPU time 310.89 seconds
Started Mar 17 02:40:39 PM PDT 24
Finished Mar 17 02:45:50 PM PDT 24
Peak memory 228908 kb
Host smart-237b487a-4ff9-4c66-92ed-4c0f095f4cda
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3045265104 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_
corrupt_sig_fatal_chk.3045265104
Directory /workspace/41.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/41.rom_ctrl_kmac_err_chk.3218541206
Short name T444
Test name
Test status
Simulation time 353338019 ps
CPU time 18.76 seconds
Started Mar 17 02:40:42 PM PDT 24
Finished Mar 17 02:41:01 PM PDT 24
Peak memory 214564 kb
Host smart-4beb65be-a668-4fff-9cee-35a710ebebf7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3218541206 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_kmac_err_chk.3218541206
Directory /workspace/41.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/41.rom_ctrl_kmac_err_chk.43857929
Short name T273
Test name
Test status
Simulation time 21734461407 ps
CPU time 53.47 seconds
Started Mar 17 01:47:31 PM PDT 24
Finished Mar 17 01:48:26 PM PDT 24
Peak memory 214956 kb
Host smart-534c02e7-44e3-4bb0-8717-29faad6bfa64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=43857929 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_kmac_err_chk.43857929
Directory /workspace/41.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/41.rom_ctrl_max_throughput_chk.1768958795
Short name T549
Test name
Test status
Simulation time 732358436 ps
CPU time 10.28 seconds
Started Mar 17 02:40:38 PM PDT 24
Finished Mar 17 02:40:49 PM PDT 24
Peak memory 212136 kb
Host smart-e4bdc2ce-3171-40b9-936b-69588a891f84
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1768958795 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_max_throughput_chk.1768958795
Directory /workspace/41.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/41.rom_ctrl_max_throughput_chk.2761339928
Short name T638
Test name
Test status
Simulation time 916688574 ps
CPU time 16.71 seconds
Started Mar 17 01:47:28 PM PDT 24
Finished Mar 17 01:47:45 PM PDT 24
Peak memory 212160 kb
Host smart-397d8baf-98fc-4158-883e-9dbad3eea2e0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2761339928 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_max_throughput_chk.2761339928
Directory /workspace/41.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/41.rom_ctrl_smoke.3393064237
Short name T154
Test name
Test status
Simulation time 3433655012 ps
CPU time 20.11 seconds
Started Mar 17 01:47:33 PM PDT 24
Finished Mar 17 01:47:54 PM PDT 24
Peak memory 217356 kb
Host smart-43770586-c40b-4409-b671-61e4b7a39982
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3393064237 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_smoke.3393064237
Directory /workspace/41.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/41.rom_ctrl_smoke.4075105920
Short name T566
Test name
Test status
Simulation time 349299783 ps
CPU time 19.9 seconds
Started Mar 17 02:40:41 PM PDT 24
Finished Mar 17 02:41:01 PM PDT 24
Peak memory 216816 kb
Host smart-23670b44-f96a-49e7-8bd5-b15adf2fe943
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4075105920 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_smoke.4075105920
Directory /workspace/41.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/41.rom_ctrl_stress_all.1746702539
Short name T300
Test name
Test status
Simulation time 59325963869 ps
CPU time 136.03 seconds
Started Mar 17 02:40:43 PM PDT 24
Finished Mar 17 02:42:59 PM PDT 24
Peak memory 220028 kb
Host smart-49069a35-b019-413c-af42-0a9dc14b2ca0
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1746702539 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 41.rom_ctrl_stress_all.1746702539
Directory /workspace/41.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/41.rom_ctrl_stress_all.3639066912
Short name T640
Test name
Test status
Simulation time 15969290073 ps
CPU time 92.88 seconds
Started Mar 17 01:47:30 PM PDT 24
Finished Mar 17 01:49:04 PM PDT 24
Peak memory 221380 kb
Host smart-ffebb76b-7f10-4697-b64a-6b09c148a598
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3639066912 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 41.rom_ctrl_stress_all.3639066912
Directory /workspace/41.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/41.rom_ctrl_stress_all_with_rand_reset.3814850810
Short name T113
Test name
Test status
Simulation time 97217837563 ps
CPU time 924.37 seconds
Started Mar 17 01:47:28 PM PDT 24
Finished Mar 17 02:02:52 PM PDT 24
Peak memory 235756 kb
Host smart-f8f1597e-e064-4de0-907c-2d87dc2c46fd
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3814850810 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_stress_all_with_rand_reset.3814850810
Directory /workspace/41.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.rom_ctrl_alert_test.1727859714
Short name T141
Test name
Test status
Simulation time 689563234 ps
CPU time 8.07 seconds
Started Mar 17 02:40:45 PM PDT 24
Finished Mar 17 02:40:53 PM PDT 24
Peak memory 211248 kb
Host smart-99f0b0e0-a6ed-480e-a90f-6d0a443884a1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1727859714 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_alert_test.1727859714
Directory /workspace/42.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/42.rom_ctrl_alert_test.627657252
Short name T181
Test name
Test status
Simulation time 6745684628 ps
CPU time 24.51 seconds
Started Mar 17 01:47:27 PM PDT 24
Finished Mar 17 01:47:52 PM PDT 24
Peak memory 212260 kb
Host smart-05cbb883-12c5-4346-9981-da6a627d6fe8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=627657252 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_alert_test.627657252
Directory /workspace/42.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/42.rom_ctrl_corrupt_sig_fatal_chk.1262535780
Short name T484
Test name
Test status
Simulation time 84602496870 ps
CPU time 822.52 seconds
Started Mar 17 01:47:31 PM PDT 24
Finished Mar 17 02:01:15 PM PDT 24
Peak memory 216924 kb
Host smart-c958f42e-265b-4bc1-abb8-7fc29e5c822c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1262535780 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_
corrupt_sig_fatal_chk.1262535780
Directory /workspace/42.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/42.rom_ctrl_corrupt_sig_fatal_chk.1605080548
Short name T295
Test name
Test status
Simulation time 149599693425 ps
CPU time 752.96 seconds
Started Mar 17 02:40:43 PM PDT 24
Finished Mar 17 02:53:16 PM PDT 24
Peak memory 237504 kb
Host smart-b8a437a8-3f39-499d-a745-06eccb1080a9
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1605080548 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_
corrupt_sig_fatal_chk.1605080548
Directory /workspace/42.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/42.rom_ctrl_kmac_err_chk.1315086219
Short name T202
Test name
Test status
Simulation time 108665963236 ps
CPU time 53.93 seconds
Started Mar 17 01:47:31 PM PDT 24
Finished Mar 17 01:48:26 PM PDT 24
Peak memory 213860 kb
Host smart-e466f108-3512-49dc-95ff-fbef618c6578
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1315086219 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_kmac_err_chk.1315086219
Directory /workspace/42.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/42.rom_ctrl_kmac_err_chk.3635163074
Short name T515
Test name
Test status
Simulation time 661266751 ps
CPU time 19.41 seconds
Started Mar 17 02:40:44 PM PDT 24
Finished Mar 17 02:41:04 PM PDT 24
Peak memory 214580 kb
Host smart-56e7c4c6-5527-414d-84d2-4151ed765fc7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3635163074 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_kmac_err_chk.3635163074
Directory /workspace/42.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/42.rom_ctrl_max_throughput_chk.2559046768
Short name T346
Test name
Test status
Simulation time 5896588164 ps
CPU time 16.01 seconds
Started Mar 17 02:40:43 PM PDT 24
Finished Mar 17 02:40:59 PM PDT 24
Peak memory 211732 kb
Host smart-3365aa63-9f88-4661-a018-e8e1a5733532
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2559046768 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_max_throughput_chk.2559046768
Directory /workspace/42.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/42.rom_ctrl_max_throughput_chk.2740637187
Short name T293
Test name
Test status
Simulation time 1320338399 ps
CPU time 19.26 seconds
Started Mar 17 01:47:33 PM PDT 24
Finished Mar 17 01:47:53 PM PDT 24
Peak memory 211332 kb
Host smart-72b69daa-83e9-4a60-a973-a440d9bdfd3f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2740637187 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_max_throughput_chk.2740637187
Directory /workspace/42.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/42.rom_ctrl_smoke.1525561292
Short name T19
Test name
Test status
Simulation time 4926893826 ps
CPU time 56.31 seconds
Started Mar 17 02:40:44 PM PDT 24
Finished Mar 17 02:41:41 PM PDT 24
Peak memory 217292 kb
Host smart-5b611bc5-755b-465c-ba9d-08a74eca6e3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1525561292 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_smoke.1525561292
Directory /workspace/42.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/42.rom_ctrl_smoke.2266120384
Short name T83
Test name
Test status
Simulation time 21447087188 ps
CPU time 58.79 seconds
Started Mar 17 01:47:32 PM PDT 24
Finished Mar 17 01:48:31 PM PDT 24
Peak memory 217200 kb
Host smart-ffd5628d-9101-4798-9961-4cf987ab4405
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2266120384 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_smoke.2266120384
Directory /workspace/42.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/42.rom_ctrl_stress_all.2117458378
Short name T310
Test name
Test status
Simulation time 6596369503 ps
CPU time 77.27 seconds
Started Mar 17 02:40:44 PM PDT 24
Finished Mar 17 02:42:02 PM PDT 24
Peak memory 227468 kb
Host smart-7899e762-8297-42d8-8ba6-e0e4c6e38e75
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2117458378 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 42.rom_ctrl_stress_all.2117458378
Directory /workspace/42.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/42.rom_ctrl_stress_all.588947730
Short name T496
Test name
Test status
Simulation time 58147307956 ps
CPU time 159.33 seconds
Started Mar 17 01:47:32 PM PDT 24
Finished Mar 17 01:50:12 PM PDT 24
Peak memory 219304 kb
Host smart-eba00ec0-d392-4cb4-992f-01f219e1c8a0
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=588947730 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 42.rom_ctrl_stress_all.588947730
Directory /workspace/42.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/42.rom_ctrl_stress_all_with_rand_reset.3312978026
Short name T12
Test name
Test status
Simulation time 164091041488 ps
CPU time 1429.22 seconds
Started Mar 17 01:47:27 PM PDT 24
Finished Mar 17 02:11:16 PM PDT 24
Peak memory 236768 kb
Host smart-9f39108e-bce2-49ae-9367-a6e08a48d547
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3312978026 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_stress_all_with_rand_reset.3312978026
Directory /workspace/42.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.rom_ctrl_alert_test.2705456378
Short name T137
Test name
Test status
Simulation time 8185143210 ps
CPU time 15.07 seconds
Started Mar 17 01:47:35 PM PDT 24
Finished Mar 17 01:47:50 PM PDT 24
Peak memory 211260 kb
Host smart-b99f5515-0287-4374-8daa-03c67e765c8f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2705456378 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_alert_test.2705456378
Directory /workspace/43.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/43.rom_ctrl_alert_test.849436702
Short name T176
Test name
Test status
Simulation time 3293502676 ps
CPU time 28.09 seconds
Started Mar 17 02:40:54 PM PDT 24
Finished Mar 17 02:41:23 PM PDT 24
Peak memory 211768 kb
Host smart-b1332061-1e5e-4bb9-9aa8-463de63e3093
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=849436702 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_alert_test.849436702
Directory /workspace/43.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/43.rom_ctrl_corrupt_sig_fatal_chk.305233011
Short name T594
Test name
Test status
Simulation time 53933466459 ps
CPU time 611.39 seconds
Started Mar 17 02:40:47 PM PDT 24
Finished Mar 17 02:50:59 PM PDT 24
Peak memory 217532 kb
Host smart-61c05d8c-2966-4591-8866-9eb92c006e76
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=305233011 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_c
orrupt_sig_fatal_chk.305233011
Directory /workspace/43.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/43.rom_ctrl_corrupt_sig_fatal_chk.4283440974
Short name T649
Test name
Test status
Simulation time 19889589366 ps
CPU time 399.82 seconds
Started Mar 17 01:47:29 PM PDT 24
Finished Mar 17 01:54:09 PM PDT 24
Peak memory 217504 kb
Host smart-94f107b9-2f62-4055-9bb8-16d587ffe3c5
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4283440974 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_
corrupt_sig_fatal_chk.4283440974
Directory /workspace/43.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/43.rom_ctrl_kmac_err_chk.3039359797
Short name T663
Test name
Test status
Simulation time 5054064307 ps
CPU time 47.88 seconds
Started Mar 17 01:47:35 PM PDT 24
Finished Mar 17 01:48:23 PM PDT 24
Peak memory 215044 kb
Host smart-3f3bdd28-1c0b-4faa-a768-417bee1a59fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3039359797 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_kmac_err_chk.3039359797
Directory /workspace/43.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/43.rom_ctrl_kmac_err_chk.3777291389
Short name T632
Test name
Test status
Simulation time 45531564409 ps
CPU time 68.71 seconds
Started Mar 17 02:40:54 PM PDT 24
Finished Mar 17 02:42:03 PM PDT 24
Peak memory 215100 kb
Host smart-19e771c9-bc27-429e-be5a-3b139e4d3010
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3777291389 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_kmac_err_chk.3777291389
Directory /workspace/43.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/43.rom_ctrl_max_throughput_chk.3513911018
Short name T358
Test name
Test status
Simulation time 14838588979 ps
CPU time 31.75 seconds
Started Mar 17 02:40:50 PM PDT 24
Finished Mar 17 02:41:22 PM PDT 24
Peak memory 211712 kb
Host smart-207bb166-b868-4f32-910f-752361631f22
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3513911018 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_max_throughput_chk.3513911018
Directory /workspace/43.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/43.rom_ctrl_max_throughput_chk.3854990451
Short name T525
Test name
Test status
Simulation time 7708102490 ps
CPU time 31.7 seconds
Started Mar 17 01:47:28 PM PDT 24
Finished Mar 17 01:47:59 PM PDT 24
Peak memory 211288 kb
Host smart-e2001008-f049-4b92-8233-c01e12095ba6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3854990451 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_max_throughput_chk.3854990451
Directory /workspace/43.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/43.rom_ctrl_smoke.557107176
Short name T266
Test name
Test status
Simulation time 1315323642 ps
CPU time 19.04 seconds
Started Mar 17 01:47:29 PM PDT 24
Finished Mar 17 01:47:48 PM PDT 24
Peak memory 216080 kb
Host smart-cd43a2c7-50e0-4113-a935-04c089dbf152
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=557107176 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_smoke.557107176
Directory /workspace/43.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/43.rom_ctrl_smoke.991925221
Short name T473
Test name
Test status
Simulation time 9997937767 ps
CPU time 47.21 seconds
Started Mar 17 02:40:48 PM PDT 24
Finished Mar 17 02:41:35 PM PDT 24
Peak memory 214816 kb
Host smart-ba1e8e5d-2137-4dd9-84fc-e9405ee93fb9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=991925221 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_smoke.991925221
Directory /workspace/43.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/43.rom_ctrl_stress_all.2250337625
Short name T591
Test name
Test status
Simulation time 41071096686 ps
CPU time 228.1 seconds
Started Mar 17 01:47:29 PM PDT 24
Finished Mar 17 01:51:18 PM PDT 24
Peak memory 221132 kb
Host smart-40f5ff5c-2481-45c8-9bfc-25c1244e0dc6
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2250337625 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 43.rom_ctrl_stress_all.2250337625
Directory /workspace/43.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/43.rom_ctrl_stress_all.2342361870
Short name T404
Test name
Test status
Simulation time 16528874015 ps
CPU time 72.88 seconds
Started Mar 17 02:40:49 PM PDT 24
Finished Mar 17 02:42:02 PM PDT 24
Peak memory 219280 kb
Host smart-21e5a9c4-3a26-4ff3-9ed0-22df0c6ac3db
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2342361870 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 43.rom_ctrl_stress_all.2342361870
Directory /workspace/43.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/43.rom_ctrl_stress_all_with_rand_reset.323610231
Short name T51
Test name
Test status
Simulation time 24180400780 ps
CPU time 8944.71 seconds
Started Mar 17 01:47:32 PM PDT 24
Finished Mar 17 04:16:38 PM PDT 24
Peak memory 235836 kb
Host smart-30c16b22-a486-4be5-a564-c73dc888b197
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=323610231 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_stress_all_with_rand_reset.323610231
Directory /workspace/43.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.rom_ctrl_alert_test.1568502333
Short name T520
Test name
Test status
Simulation time 26284318632 ps
CPU time 31.9 seconds
Started Mar 17 01:47:34 PM PDT 24
Finished Mar 17 01:48:06 PM PDT 24
Peak memory 212096 kb
Host smart-f1c2f67b-4989-4d65-911c-96182bf55328
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1568502333 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_alert_test.1568502333
Directory /workspace/44.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/44.rom_ctrl_corrupt_sig_fatal_chk.1934519169
Short name T461
Test name
Test status
Simulation time 57419425275 ps
CPU time 574.56 seconds
Started Mar 17 01:47:35 PM PDT 24
Finished Mar 17 01:57:09 PM PDT 24
Peak memory 229948 kb
Host smart-0c4ba2a7-8404-4664-837d-066b68d4edcb
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1934519169 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_
corrupt_sig_fatal_chk.1934519169
Directory /workspace/44.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/44.rom_ctrl_corrupt_sig_fatal_chk.1954449238
Short name T677
Test name
Test status
Simulation time 87190933358 ps
CPU time 667.49 seconds
Started Mar 17 02:40:56 PM PDT 24
Finished Mar 17 02:52:04 PM PDT 24
Peak memory 219332 kb
Host smart-4af4c9b0-6115-4bef-99e4-23e8a7d5f844
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1954449238 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_
corrupt_sig_fatal_chk.1954449238
Directory /workspace/44.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/44.rom_ctrl_kmac_err_chk.14315246
Short name T622
Test name
Test status
Simulation time 13053941606 ps
CPU time 59.23 seconds
Started Mar 17 02:40:54 PM PDT 24
Finished Mar 17 02:41:54 PM PDT 24
Peak memory 214852 kb
Host smart-0a5966ec-7672-4257-8aa9-4a1558910b66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=14315246 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_kmac_err_chk.14315246
Directory /workspace/44.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/44.rom_ctrl_kmac_err_chk.2100316837
Short name T596
Test name
Test status
Simulation time 8488093146 ps
CPU time 71.51 seconds
Started Mar 17 01:47:35 PM PDT 24
Finished Mar 17 01:48:47 PM PDT 24
Peak memory 215180 kb
Host smart-7d22faac-c547-4b64-a9c2-d23d17242bc9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2100316837 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_kmac_err_chk.2100316837
Directory /workspace/44.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/44.rom_ctrl_max_throughput_chk.2988253292
Short name T568
Test name
Test status
Simulation time 3795227836 ps
CPU time 32.65 seconds
Started Mar 17 02:40:55 PM PDT 24
Finished Mar 17 02:41:28 PM PDT 24
Peak memory 212344 kb
Host smart-5e1d834f-862d-4459-a43d-e1debb15ce55
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2988253292 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_max_throughput_chk.2988253292
Directory /workspace/44.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/44.rom_ctrl_max_throughput_chk.507771838
Short name T352
Test name
Test status
Simulation time 3413943782 ps
CPU time 29.31 seconds
Started Mar 17 01:47:32 PM PDT 24
Finished Mar 17 01:48:03 PM PDT 24
Peak memory 212316 kb
Host smart-a7b3d98c-b99f-4d86-a246-f8ff7de01c47
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=507771838 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_max_throughput_chk.507771838
Directory /workspace/44.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/44.rom_ctrl_smoke.3751991968
Short name T602
Test name
Test status
Simulation time 20460160332 ps
CPU time 64.65 seconds
Started Mar 17 02:40:55 PM PDT 24
Finished Mar 17 02:42:00 PM PDT 24
Peak memory 217340 kb
Host smart-04bceb0f-7d73-49ec-99b4-6d8cf35b8bf7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3751991968 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_smoke.3751991968
Directory /workspace/44.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/44.rom_ctrl_smoke.4273261807
Short name T402
Test name
Test status
Simulation time 59549940971 ps
CPU time 69.72 seconds
Started Mar 17 01:47:40 PM PDT 24
Finished Mar 17 01:48:50 PM PDT 24
Peak memory 216412 kb
Host smart-ae466c54-002d-4f8a-8aeb-05e6dc91e7b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4273261807 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_smoke.4273261807
Directory /workspace/44.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/44.rom_ctrl_stress_all.2666253571
Short name T526
Test name
Test status
Simulation time 8022060841 ps
CPU time 69.73 seconds
Started Mar 17 01:47:33 PM PDT 24
Finished Mar 17 01:48:43 PM PDT 24
Peak memory 217796 kb
Host smart-a077246d-816b-4a80-9369-6ebfd0fc5aba
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2666253571 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 44.rom_ctrl_stress_all.2666253571
Directory /workspace/44.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/44.rom_ctrl_stress_all.4046104506
Short name T667
Test name
Test status
Simulation time 7553494813 ps
CPU time 96.98 seconds
Started Mar 17 02:40:53 PM PDT 24
Finished Mar 17 02:42:31 PM PDT 24
Peak memory 220504 kb
Host smart-ce3875d8-78f5-43be-acef-59981b985f92
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4046104506 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 44.rom_ctrl_stress_all.4046104506
Directory /workspace/44.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/45.rom_ctrl_alert_test.1920106575
Short name T59
Test name
Test status
Simulation time 20201623712 ps
CPU time 23.06 seconds
Started Mar 17 02:40:58 PM PDT 24
Finished Mar 17 02:41:22 PM PDT 24
Peak memory 212176 kb
Host smart-c63a77f0-4d21-4fdb-84ca-b2929dea0ad4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1920106575 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_alert_test.1920106575
Directory /workspace/45.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/45.rom_ctrl_alert_test.879831930
Short name T552
Test name
Test status
Simulation time 2589809100 ps
CPU time 15.24 seconds
Started Mar 17 01:47:40 PM PDT 24
Finished Mar 17 01:47:55 PM PDT 24
Peak memory 211300 kb
Host smart-0b209983-8805-4ad6-8b7a-695d2c576a76
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=879831930 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_alert_test.879831930
Directory /workspace/45.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/45.rom_ctrl_corrupt_sig_fatal_chk.293977193
Short name T561
Test name
Test status
Simulation time 377772556733 ps
CPU time 1040.52 seconds
Started Mar 17 01:47:33 PM PDT 24
Finished Mar 17 02:04:54 PM PDT 24
Peak memory 225140 kb
Host smart-a20aafbd-d329-4db3-b7fd-4c052778e8c6
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=293977193 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_c
orrupt_sig_fatal_chk.293977193
Directory /workspace/45.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/45.rom_ctrl_corrupt_sig_fatal_chk.3609388573
Short name T445
Test name
Test status
Simulation time 89571565711 ps
CPU time 276.12 seconds
Started Mar 17 02:40:59 PM PDT 24
Finished Mar 17 02:45:35 PM PDT 24
Peak memory 216596 kb
Host smart-c88a4255-b897-45e2-a91c-0414c9f07cfd
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3609388573 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_
corrupt_sig_fatal_chk.3609388573
Directory /workspace/45.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/45.rom_ctrl_kmac_err_chk.2105432010
Short name T248
Test name
Test status
Simulation time 8224522973 ps
CPU time 27.84 seconds
Started Mar 17 01:47:35 PM PDT 24
Finished Mar 17 01:48:03 PM PDT 24
Peak memory 213112 kb
Host smart-8bb89d8f-00f7-497c-b8c3-38b698e14dc6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2105432010 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_kmac_err_chk.2105432010
Directory /workspace/45.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/45.rom_ctrl_kmac_err_chk.3997215734
Short name T158
Test name
Test status
Simulation time 17796219569 ps
CPU time 47.19 seconds
Started Mar 17 02:41:00 PM PDT 24
Finished Mar 17 02:41:47 PM PDT 24
Peak memory 213956 kb
Host smart-f40442b1-e88d-43f9-9c3c-85d0b724cbcc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3997215734 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_kmac_err_chk.3997215734
Directory /workspace/45.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/45.rom_ctrl_max_throughput_chk.4042563328
Short name T659
Test name
Test status
Simulation time 2504792862 ps
CPU time 25.22 seconds
Started Mar 17 02:41:00 PM PDT 24
Finished Mar 17 02:41:26 PM PDT 24
Peak memory 211284 kb
Host smart-00287a78-a85b-40e9-9017-c6ea5535ae2c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4042563328 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_max_throughput_chk.4042563328
Directory /workspace/45.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/45.rom_ctrl_max_throughput_chk.847000190
Short name T626
Test name
Test status
Simulation time 726879933 ps
CPU time 10.39 seconds
Started Mar 17 01:47:38 PM PDT 24
Finished Mar 17 01:47:49 PM PDT 24
Peak memory 212152 kb
Host smart-d356142f-aaf1-4617-8254-5c83dbe5f60a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=847000190 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_max_throughput_chk.847000190
Directory /workspace/45.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/45.rom_ctrl_smoke.1282133861
Short name T507
Test name
Test status
Simulation time 7869386769 ps
CPU time 56.08 seconds
Started Mar 17 02:40:54 PM PDT 24
Finished Mar 17 02:41:50 PM PDT 24
Peak memory 215468 kb
Host smart-33179d63-ba00-40e6-ad0b-500f599d4ee1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1282133861 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_smoke.1282133861
Directory /workspace/45.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/45.rom_ctrl_smoke.3852354785
Short name T531
Test name
Test status
Simulation time 3858032398 ps
CPU time 46.09 seconds
Started Mar 17 01:47:36 PM PDT 24
Finished Mar 17 01:48:23 PM PDT 24
Peak memory 216844 kb
Host smart-071e4bb6-5b82-42a2-a98b-52dd7d2524f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3852354785 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_smoke.3852354785
Directory /workspace/45.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/45.rom_ctrl_stress_all.204387757
Short name T218
Test name
Test status
Simulation time 11346125424 ps
CPU time 55.06 seconds
Started Mar 17 02:40:54 PM PDT 24
Finished Mar 17 02:41:50 PM PDT 24
Peak memory 218308 kb
Host smart-3e95875d-97d0-4d48-acf7-9141e3de33fe
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=204387757 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 45.rom_ctrl_stress_all.204387757
Directory /workspace/45.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/45.rom_ctrl_stress_all.474553574
Short name T130
Test name
Test status
Simulation time 1865111809 ps
CPU time 59.35 seconds
Started Mar 17 01:47:35 PM PDT 24
Finished Mar 17 01:48:34 PM PDT 24
Peak memory 219152 kb
Host smart-acbe2f01-461d-4620-bcf5-9186e7ed53c1
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=474553574 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 45.rom_ctrl_stress_all.474553574
Directory /workspace/45.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/46.rom_ctrl_alert_test.3580104270
Short name T265
Test name
Test status
Simulation time 12141430098 ps
CPU time 27.9 seconds
Started Mar 17 01:47:34 PM PDT 24
Finished Mar 17 01:48:02 PM PDT 24
Peak memory 211600 kb
Host smart-32a4badb-601c-49a5-a4d7-32d205d8ad04
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3580104270 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_alert_test.3580104270
Directory /workspace/46.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/46.rom_ctrl_alert_test.3705327814
Short name T661
Test name
Test status
Simulation time 717952575 ps
CPU time 8.31 seconds
Started Mar 17 02:40:59 PM PDT 24
Finished Mar 17 02:41:07 PM PDT 24
Peak memory 211208 kb
Host smart-fe63905b-998f-4088-a075-2efedcb99bab
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3705327814 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_alert_test.3705327814
Directory /workspace/46.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/46.rom_ctrl_corrupt_sig_fatal_chk.206186684
Short name T24
Test name
Test status
Simulation time 346746292485 ps
CPU time 507.92 seconds
Started Mar 17 01:47:35 PM PDT 24
Finished Mar 17 01:56:04 PM PDT 24
Peak memory 233432 kb
Host smart-e657eab3-1662-4839-a08b-a91a193c0bb8
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=206186684 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_c
orrupt_sig_fatal_chk.206186684
Directory /workspace/46.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/46.rom_ctrl_corrupt_sig_fatal_chk.482390757
Short name T349
Test name
Test status
Simulation time 25478531320 ps
CPU time 303.74 seconds
Started Mar 17 02:41:01 PM PDT 24
Finished Mar 17 02:46:05 PM PDT 24
Peak memory 216660 kb
Host smart-68b0cae3-44f2-41d2-a455-8d1a662ebe60
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=482390757 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_c
orrupt_sig_fatal_chk.482390757
Directory /workspace/46.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/46.rom_ctrl_kmac_err_chk.1369445431
Short name T239
Test name
Test status
Simulation time 3784749579 ps
CPU time 33.34 seconds
Started Mar 17 02:41:02 PM PDT 24
Finished Mar 17 02:41:35 PM PDT 24
Peak memory 215600 kb
Host smart-655a78c7-902b-4c61-a3fa-2a893a2abbc9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1369445431 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_kmac_err_chk.1369445431
Directory /workspace/46.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/46.rom_ctrl_kmac_err_chk.2240675140
Short name T468
Test name
Test status
Simulation time 3464026753 ps
CPU time 42.08 seconds
Started Mar 17 01:47:39 PM PDT 24
Finished Mar 17 01:48:21 PM PDT 24
Peak memory 214560 kb
Host smart-f36d83b2-2662-45f9-9594-ae4c97ec85eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2240675140 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_kmac_err_chk.2240675140
Directory /workspace/46.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/46.rom_ctrl_max_throughput_chk.1143694316
Short name T9
Test name
Test status
Simulation time 3829325978 ps
CPU time 21.98 seconds
Started Mar 17 02:41:01 PM PDT 24
Finished Mar 17 02:41:23 PM PDT 24
Peak memory 211424 kb
Host smart-fac13b01-d811-4e4d-b13d-9bde0d815900
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1143694316 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_max_throughput_chk.1143694316
Directory /workspace/46.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/46.rom_ctrl_max_throughput_chk.3792165739
Short name T631
Test name
Test status
Simulation time 3295345949 ps
CPU time 29.73 seconds
Started Mar 17 01:47:34 PM PDT 24
Finished Mar 17 01:48:04 PM PDT 24
Peak memory 211348 kb
Host smart-9385053c-a19f-4a1c-8599-bff609f985b6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3792165739 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_max_throughput_chk.3792165739
Directory /workspace/46.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/46.rom_ctrl_smoke.3018244148
Short name T562
Test name
Test status
Simulation time 51419633024 ps
CPU time 46.96 seconds
Started Mar 17 01:47:34 PM PDT 24
Finished Mar 17 01:48:21 PM PDT 24
Peak memory 218296 kb
Host smart-987b9e86-a2fd-4eab-bee9-c452ec41e652
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3018244148 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_smoke.3018244148
Directory /workspace/46.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/46.rom_ctrl_smoke.3781466824
Short name T383
Test name
Test status
Simulation time 4906483741 ps
CPU time 54.91 seconds
Started Mar 17 02:41:00 PM PDT 24
Finished Mar 17 02:41:55 PM PDT 24
Peak memory 217864 kb
Host smart-a0b0b0a4-40f4-46a7-8147-af33187cb220
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3781466824 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_smoke.3781466824
Directory /workspace/46.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/46.rom_ctrl_stress_all.1276246620
Short name T650
Test name
Test status
Simulation time 5701307683 ps
CPU time 41.92 seconds
Started Mar 17 01:47:34 PM PDT 24
Finished Mar 17 01:48:17 PM PDT 24
Peak memory 213696 kb
Host smart-61c55112-01ff-429d-af3e-abb245457497
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1276246620 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 46.rom_ctrl_stress_all.1276246620
Directory /workspace/46.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/46.rom_ctrl_stress_all.3258827751
Short name T509
Test name
Test status
Simulation time 173643479 ps
CPU time 13.43 seconds
Started Mar 17 02:40:58 PM PDT 24
Finished Mar 17 02:41:13 PM PDT 24
Peak memory 211316 kb
Host smart-9cb82a09-6594-4f08-9de3-6c854e9661ae
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3258827751 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 46.rom_ctrl_stress_all.3258827751
Directory /workspace/46.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/46.rom_ctrl_stress_all_with_rand_reset.3827568484
Short name T49
Test name
Test status
Simulation time 68252912110 ps
CPU time 1278.5 seconds
Started Mar 17 02:41:01 PM PDT 24
Finished Mar 17 03:02:20 PM PDT 24
Peak memory 235848 kb
Host smart-abe59681-2f7d-408a-b941-6b0b4817e939
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3827568484 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_stress_all_with_rand_reset.3827568484
Directory /workspace/46.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.rom_ctrl_alert_test.2758451610
Short name T233
Test name
Test status
Simulation time 11802198014 ps
CPU time 26.05 seconds
Started Mar 17 02:41:07 PM PDT 24
Finished Mar 17 02:41:34 PM PDT 24
Peak memory 211296 kb
Host smart-959e49c3-7c08-4857-acbd-d9108040bf09
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2758451610 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_alert_test.2758451610
Directory /workspace/47.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/47.rom_ctrl_alert_test.3039022255
Short name T61
Test name
Test status
Simulation time 612597939 ps
CPU time 8.33 seconds
Started Mar 17 01:47:37 PM PDT 24
Finished Mar 17 01:47:46 PM PDT 24
Peak memory 211244 kb
Host smart-82cd07f1-fc16-438b-bf40-ee8cb7c8abea
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3039022255 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_alert_test.3039022255
Directory /workspace/47.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/47.rom_ctrl_corrupt_sig_fatal_chk.1844338333
Short name T325
Test name
Test status
Simulation time 86979996671 ps
CPU time 266.11 seconds
Started Mar 17 02:41:00 PM PDT 24
Finished Mar 17 02:45:26 PM PDT 24
Peak memory 236460 kb
Host smart-89105bd3-430a-4d6e-9716-69bf5d24918f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1844338333 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_
corrupt_sig_fatal_chk.1844338333
Directory /workspace/47.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/47.rom_ctrl_corrupt_sig_fatal_chk.2459149447
Short name T369
Test name
Test status
Simulation time 27288993489 ps
CPU time 250.24 seconds
Started Mar 17 01:47:33 PM PDT 24
Finished Mar 17 01:51:44 PM PDT 24
Peak memory 238508 kb
Host smart-4af50108-c282-4503-b54b-94feb8da93e8
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2459149447 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_
corrupt_sig_fatal_chk.2459149447
Directory /workspace/47.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/47.rom_ctrl_kmac_err_chk.4146989075
Short name T311
Test name
Test status
Simulation time 662009322 ps
CPU time 19.19 seconds
Started Mar 17 01:47:34 PM PDT 24
Finished Mar 17 01:47:53 PM PDT 24
Peak memory 214560 kb
Host smart-2bb2ebd8-e9f6-4d2f-86b4-f40ddd65295e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4146989075 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_kmac_err_chk.4146989075
Directory /workspace/47.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/47.rom_ctrl_kmac_err_chk.840914161
Short name T547
Test name
Test status
Simulation time 18053715802 ps
CPU time 42.37 seconds
Started Mar 17 02:41:06 PM PDT 24
Finished Mar 17 02:41:48 PM PDT 24
Peak memory 213856 kb
Host smart-daa7c241-4d66-4fff-9200-61d37f116ca9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=840914161 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_kmac_err_chk.840914161
Directory /workspace/47.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/47.rom_ctrl_max_throughput_chk.2588758552
Short name T261
Test name
Test status
Simulation time 224370439 ps
CPU time 10.34 seconds
Started Mar 17 01:47:37 PM PDT 24
Finished Mar 17 01:47:48 PM PDT 24
Peak memory 212352 kb
Host smart-6477b138-ece7-474d-ae18-b463bd20094a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2588758552 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_max_throughput_chk.2588758552
Directory /workspace/47.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/47.rom_ctrl_max_throughput_chk.2875998730
Short name T550
Test name
Test status
Simulation time 3170628242 ps
CPU time 28.7 seconds
Started Mar 17 02:41:05 PM PDT 24
Finished Mar 17 02:41:34 PM PDT 24
Peak memory 211348 kb
Host smart-39254a1c-fa4f-4af5-af07-b647e004aa7f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2875998730 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_max_throughput_chk.2875998730
Directory /workspace/47.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/47.rom_ctrl_smoke.29920595
Short name T340
Test name
Test status
Simulation time 6375807927 ps
CPU time 57.24 seconds
Started Mar 17 02:40:59 PM PDT 24
Finished Mar 17 02:41:56 PM PDT 24
Peak memory 217924 kb
Host smart-a8857b07-ae2e-4f74-983c-15f214844b9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=29920595 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_smoke.29920595
Directory /workspace/47.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/47.rom_ctrl_smoke.4159508487
Short name T329
Test name
Test status
Simulation time 9265299790 ps
CPU time 34.65 seconds
Started Mar 17 01:47:32 PM PDT 24
Finished Mar 17 01:48:08 PM PDT 24
Peak memory 218552 kb
Host smart-64b8d50a-7a07-403c-899e-4a231944f59d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4159508487 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_smoke.4159508487
Directory /workspace/47.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/47.rom_ctrl_stress_all.2626012880
Short name T434
Test name
Test status
Simulation time 119026811707 ps
CPU time 83.4 seconds
Started Mar 17 01:47:36 PM PDT 24
Finished Mar 17 01:48:59 PM PDT 24
Peak memory 219080 kb
Host smart-776785c5-5b4a-45c6-ade4-94d06577fee4
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2626012880 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 47.rom_ctrl_stress_all.2626012880
Directory /workspace/47.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/47.rom_ctrl_stress_all.3342771873
Short name T376
Test name
Test status
Simulation time 106814948361 ps
CPU time 306.47 seconds
Started Mar 17 02:41:07 PM PDT 24
Finished Mar 17 02:46:14 PM PDT 24
Peak memory 221248 kb
Host smart-34a666e7-aa0a-465c-9201-eed59fd19b7c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3342771873 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 47.rom_ctrl_stress_all.3342771873
Directory /workspace/47.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/47.rom_ctrl_stress_all_with_rand_reset.2059753241
Short name T647
Test name
Test status
Simulation time 65037664695 ps
CPU time 747.07 seconds
Started Mar 17 02:40:59 PM PDT 24
Finished Mar 17 02:53:27 PM PDT 24
Peak memory 232640 kb
Host smart-4dd62701-a2b2-40f6-b4b8-238ddc85bd8b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2059753241 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_stress_all_with_rand_reset.2059753241
Directory /workspace/47.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.rom_ctrl_alert_test.1569566136
Short name T457
Test name
Test status
Simulation time 331911499 ps
CPU time 10.82 seconds
Started Mar 17 02:41:04 PM PDT 24
Finished Mar 17 02:41:15 PM PDT 24
Peak memory 211288 kb
Host smart-08be50d4-2a38-45d0-be1c-ec5e12ed582c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1569566136 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_alert_test.1569566136
Directory /workspace/48.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/48.rom_ctrl_alert_test.3736121834
Short name T670
Test name
Test status
Simulation time 7237690078 ps
CPU time 30.22 seconds
Started Mar 17 01:47:39 PM PDT 24
Finished Mar 17 01:48:09 PM PDT 24
Peak memory 212096 kb
Host smart-ceb70ac8-1abb-45ea-8212-7be30204d012
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3736121834 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_alert_test.3736121834
Directory /workspace/48.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/48.rom_ctrl_corrupt_sig_fatal_chk.1876612172
Short name T174
Test name
Test status
Simulation time 39109944970 ps
CPU time 300.34 seconds
Started Mar 17 01:47:38 PM PDT 24
Finished Mar 17 01:52:39 PM PDT 24
Peak memory 216852 kb
Host smart-d82d91cf-6d22-4655-8a9b-9851ace5da24
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1876612172 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_
corrupt_sig_fatal_chk.1876612172
Directory /workspace/48.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/48.rom_ctrl_corrupt_sig_fatal_chk.493920474
Short name T4
Test name
Test status
Simulation time 3528557211 ps
CPU time 245.96 seconds
Started Mar 17 02:41:04 PM PDT 24
Finished Mar 17 02:45:10 PM PDT 24
Peak memory 228316 kb
Host smart-4490f7c9-41a7-4a34-8ffb-ff86abc50813
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=493920474 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_c
orrupt_sig_fatal_chk.493920474
Directory /workspace/48.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/48.rom_ctrl_kmac_err_chk.1590508557
Short name T275
Test name
Test status
Simulation time 36139322455 ps
CPU time 53.97 seconds
Started Mar 17 02:41:04 PM PDT 24
Finished Mar 17 02:41:58 PM PDT 24
Peak memory 213876 kb
Host smart-4b62a8c1-b41d-4fe4-bc93-761d22d86347
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1590508557 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_kmac_err_chk.1590508557
Directory /workspace/48.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/48.rom_ctrl_kmac_err_chk.3582660535
Short name T224
Test name
Test status
Simulation time 90059002177 ps
CPU time 63.15 seconds
Started Mar 17 01:47:39 PM PDT 24
Finished Mar 17 01:48:42 PM PDT 24
Peak memory 215264 kb
Host smart-08256ca5-3402-4f88-a2df-15a4fa8760bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3582660535 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_kmac_err_chk.3582660535
Directory /workspace/48.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/48.rom_ctrl_max_throughput_chk.2524954884
Short name T635
Test name
Test status
Simulation time 6342202273 ps
CPU time 27.24 seconds
Started Mar 17 02:40:59 PM PDT 24
Finished Mar 17 02:41:27 PM PDT 24
Peak memory 211756 kb
Host smart-1b4c0a31-211f-4543-b0be-9af4ebc23fd2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2524954884 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_max_throughput_chk.2524954884
Directory /workspace/48.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/48.rom_ctrl_max_throughput_chk.4140239702
Short name T571
Test name
Test status
Simulation time 14638577266 ps
CPU time 25.77 seconds
Started Mar 17 01:47:39 PM PDT 24
Finished Mar 17 01:48:05 PM PDT 24
Peak memory 212684 kb
Host smart-29e30092-f3bc-4197-9381-da190222dce6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4140239702 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_max_throughput_chk.4140239702
Directory /workspace/48.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/48.rom_ctrl_smoke.1888279327
Short name T167
Test name
Test status
Simulation time 72957024330 ps
CPU time 50.62 seconds
Started Mar 17 01:47:37 PM PDT 24
Finished Mar 17 01:48:28 PM PDT 24
Peak memory 217252 kb
Host smart-d96f80b2-a5f0-4663-bdfc-1c63fae229ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1888279327 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_smoke.1888279327
Directory /workspace/48.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/48.rom_ctrl_smoke.2229659688
Short name T210
Test name
Test status
Simulation time 3858579567 ps
CPU time 48.05 seconds
Started Mar 17 02:40:58 PM PDT 24
Finished Mar 17 02:41:47 PM PDT 24
Peak memory 217100 kb
Host smart-c55bd2a7-7a40-4534-a1a4-d7b312ea25ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2229659688 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_smoke.2229659688
Directory /workspace/48.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/48.rom_ctrl_stress_all.1590634055
Short name T238
Test name
Test status
Simulation time 100727104519 ps
CPU time 132.74 seconds
Started Mar 17 01:47:32 PM PDT 24
Finished Mar 17 01:49:46 PM PDT 24
Peak memory 219216 kb
Host smart-b8ef27a9-310e-49c8-9828-22b3e44971a7
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1590634055 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 48.rom_ctrl_stress_all.1590634055
Directory /workspace/48.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/48.rom_ctrl_stress_all.3013546689
Short name T139
Test name
Test status
Simulation time 6757538364 ps
CPU time 57.45 seconds
Started Mar 17 02:41:01 PM PDT 24
Finished Mar 17 02:41:59 PM PDT 24
Peak memory 219832 kb
Host smart-15fe2c3f-7dad-4ba7-9dd0-7ab8587aeffc
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3013546689 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 48.rom_ctrl_stress_all.3013546689
Directory /workspace/48.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/49.rom_ctrl_alert_test.1223124309
Short name T554
Test name
Test status
Simulation time 1760375700 ps
CPU time 13.61 seconds
Started Mar 17 01:47:40 PM PDT 24
Finished Mar 17 01:47:54 PM PDT 24
Peak memory 211204 kb
Host smart-472ee8eb-4b76-46e0-ab30-0827a8806d20
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1223124309 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_alert_test.1223124309
Directory /workspace/49.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/49.rom_ctrl_alert_test.756214596
Short name T537
Test name
Test status
Simulation time 4770379103 ps
CPU time 29.48 seconds
Started Mar 17 02:41:05 PM PDT 24
Finished Mar 17 02:41:35 PM PDT 24
Peak memory 212072 kb
Host smart-58cd785c-2126-4cc3-acf5-f5833c55d70a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=756214596 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_alert_test.756214596
Directory /workspace/49.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/49.rom_ctrl_corrupt_sig_fatal_chk.2203235830
Short name T592
Test name
Test status
Simulation time 68914462250 ps
CPU time 774.23 seconds
Started Mar 17 02:41:11 PM PDT 24
Finished Mar 17 02:54:06 PM PDT 24
Peak memory 237304 kb
Host smart-53f33cb4-63b0-4f01-aac4-88ac91e87377
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2203235830 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_
corrupt_sig_fatal_chk.2203235830
Directory /workspace/49.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/49.rom_ctrl_corrupt_sig_fatal_chk.3962361048
Short name T451
Test name
Test status
Simulation time 3566505737 ps
CPU time 218.09 seconds
Started Mar 17 01:47:43 PM PDT 24
Finished Mar 17 01:51:21 PM PDT 24
Peak memory 216792 kb
Host smart-37def807-43d6-44b2-977a-264cada405f0
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3962361048 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_
corrupt_sig_fatal_chk.3962361048
Directory /workspace/49.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/49.rom_ctrl_kmac_err_chk.2996623626
Short name T609
Test name
Test status
Simulation time 1974291483 ps
CPU time 32.38 seconds
Started Mar 17 02:41:03 PM PDT 24
Finished Mar 17 02:41:36 PM PDT 24
Peak memory 214776 kb
Host smart-e5d58d5f-8802-46d7-9bb4-ccfa52de719a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2996623626 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_kmac_err_chk.2996623626
Directory /workspace/49.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/49.rom_ctrl_kmac_err_chk.3263155672
Short name T371
Test name
Test status
Simulation time 1376595062 ps
CPU time 19.29 seconds
Started Mar 17 01:47:45 PM PDT 24
Finished Mar 17 01:48:05 PM PDT 24
Peak memory 214820 kb
Host smart-1200d79d-b3c5-4736-bd0a-76c202b506d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3263155672 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_kmac_err_chk.3263155672
Directory /workspace/49.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/49.rom_ctrl_max_throughput_chk.2056252615
Short name T475
Test name
Test status
Simulation time 2063973518 ps
CPU time 22.63 seconds
Started Mar 17 01:47:38 PM PDT 24
Finished Mar 17 01:48:01 PM PDT 24
Peak memory 212108 kb
Host smart-1f37b3d5-c96f-4b70-9c93-1fd20181a219
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2056252615 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_max_throughput_chk.2056252615
Directory /workspace/49.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/49.rom_ctrl_max_throughput_chk.3307992841
Short name T584
Test name
Test status
Simulation time 5101844010 ps
CPU time 25.37 seconds
Started Mar 17 02:41:05 PM PDT 24
Finished Mar 17 02:41:30 PM PDT 24
Peak memory 211628 kb
Host smart-fd5ee8e4-800a-418f-8363-e16995321e43
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3307992841 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_max_throughput_chk.3307992841
Directory /workspace/49.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/49.rom_ctrl_smoke.3050865516
Short name T317
Test name
Test status
Simulation time 2803284253 ps
CPU time 40.65 seconds
Started Mar 17 01:47:38 PM PDT 24
Finished Mar 17 01:48:19 PM PDT 24
Peak memory 217612 kb
Host smart-3b829f43-dbc1-40a6-9f8f-9a543d9e3f06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3050865516 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_smoke.3050865516
Directory /workspace/49.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/49.rom_ctrl_smoke.707425955
Short name T209
Test name
Test status
Simulation time 21810867444 ps
CPU time 53.08 seconds
Started Mar 17 02:41:05 PM PDT 24
Finished Mar 17 02:41:58 PM PDT 24
Peak memory 216524 kb
Host smart-eeb65df3-34d3-4b67-8ad3-0fd145384728
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=707425955 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_smoke.707425955
Directory /workspace/49.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/49.rom_ctrl_stress_all.2410184143
Short name T361
Test name
Test status
Simulation time 2175494265 ps
CPU time 34.51 seconds
Started Mar 17 02:41:05 PM PDT 24
Finished Mar 17 02:41:40 PM PDT 24
Peak memory 211496 kb
Host smart-519fb7b6-fc82-46d8-8509-975709a06bf4
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2410184143 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 49.rom_ctrl_stress_all.2410184143
Directory /workspace/49.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/49.rom_ctrl_stress_all.492017356
Short name T565
Test name
Test status
Simulation time 5956857603 ps
CPU time 82.81 seconds
Started Mar 17 01:47:41 PM PDT 24
Finished Mar 17 01:49:04 PM PDT 24
Peak memory 220104 kb
Host smart-b01c74a9-a120-4d41-a9a3-bb71e16ed862
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=492017356 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 49.rom_ctrl_stress_all.492017356
Directory /workspace/49.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/5.rom_ctrl_alert_test.2675291830
Short name T153
Test name
Test status
Simulation time 2746443436 ps
CPU time 24.23 seconds
Started Mar 17 01:46:56 PM PDT 24
Finished Mar 17 01:47:20 PM PDT 24
Peak memory 211336 kb
Host smart-f6fb9a08-53ee-430f-8cf2-f4cfa6780e5c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2675291830 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_alert_test.2675291830
Directory /workspace/5.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/5.rom_ctrl_alert_test.775818977
Short name T665
Test name
Test status
Simulation time 3614061759 ps
CPU time 30.12 seconds
Started Mar 17 02:40:01 PM PDT 24
Finished Mar 17 02:40:32 PM PDT 24
Peak memory 211888 kb
Host smart-fe2d0452-335f-4832-b36b-bade2f1a493f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=775818977 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_alert_test.775818977
Directory /workspace/5.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/5.rom_ctrl_corrupt_sig_fatal_chk.1013751463
Short name T221
Test name
Test status
Simulation time 121886894400 ps
CPU time 451.86 seconds
Started Mar 17 01:46:58 PM PDT 24
Finished Mar 17 01:54:30 PM PDT 24
Peak memory 239984 kb
Host smart-ad3df7d8-79fa-4998-b1dd-9b4893b37853
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1013751463 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_c
orrupt_sig_fatal_chk.1013751463
Directory /workspace/5.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/5.rom_ctrl_corrupt_sig_fatal_chk.1983194620
Short name T422
Test name
Test status
Simulation time 221809641695 ps
CPU time 504.48 seconds
Started Mar 17 02:39:59 PM PDT 24
Finished Mar 17 02:48:24 PM PDT 24
Peak memory 239064 kb
Host smart-9652ed91-8b44-4641-93ad-d16fa6fbad75
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1983194620 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_c
orrupt_sig_fatal_chk.1983194620
Directory /workspace/5.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/5.rom_ctrl_kmac_err_chk.1730421237
Short name T501
Test name
Test status
Simulation time 4588651858 ps
CPU time 34.78 seconds
Started Mar 17 02:40:05 PM PDT 24
Finished Mar 17 02:40:40 PM PDT 24
Peak memory 214824 kb
Host smart-843c7c55-dd6d-4967-b04c-7c10ddc05548
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1730421237 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_kmac_err_chk.1730421237
Directory /workspace/5.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/5.rom_ctrl_kmac_err_chk.3039904224
Short name T28
Test name
Test status
Simulation time 4355101697 ps
CPU time 34.31 seconds
Started Mar 17 01:46:44 PM PDT 24
Finished Mar 17 01:47:20 PM PDT 24
Peak memory 214856 kb
Host smart-8ae4cd3f-7d07-4a47-8a32-5b81e11adcb2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3039904224 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_kmac_err_chk.3039904224
Directory /workspace/5.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/5.rom_ctrl_max_throughput_chk.2232043384
Short name T553
Test name
Test status
Simulation time 13208566662 ps
CPU time 18.85 seconds
Started Mar 17 01:46:45 PM PDT 24
Finished Mar 17 01:47:06 PM PDT 24
Peak memory 211740 kb
Host smart-aa9961c8-8e80-4377-a09c-adcd9c915143
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2232043384 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_max_throughput_chk.2232043384
Directory /workspace/5.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/5.rom_ctrl_max_throughput_chk.3012556957
Short name T392
Test name
Test status
Simulation time 7551683370 ps
CPU time 33.56 seconds
Started Mar 17 02:40:04 PM PDT 24
Finished Mar 17 02:40:38 PM PDT 24
Peak memory 212700 kb
Host smart-1b063b5b-43e1-4f38-b462-0372a6b6b6c8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3012556957 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_max_throughput_chk.3012556957
Directory /workspace/5.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/5.rom_ctrl_smoke.4082844217
Short name T323
Test name
Test status
Simulation time 15174277014 ps
CPU time 48.09 seconds
Started Mar 17 01:46:55 PM PDT 24
Finished Mar 17 01:47:43 PM PDT 24
Peak memory 217776 kb
Host smart-d918016b-974e-4b0a-acdb-9d220977d47a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4082844217 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_smoke.4082844217
Directory /workspace/5.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/5.rom_ctrl_smoke.768207890
Short name T630
Test name
Test status
Simulation time 17789814496 ps
CPU time 52.87 seconds
Started Mar 17 02:39:59 PM PDT 24
Finished Mar 17 02:40:52 PM PDT 24
Peak memory 217532 kb
Host smart-77d9d19b-0f2a-4f10-b6bd-bec655bd1145
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=768207890 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_smoke.768207890
Directory /workspace/5.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/5.rom_ctrl_stress_all.1852713659
Short name T347
Test name
Test status
Simulation time 51537962267 ps
CPU time 222.59 seconds
Started Mar 17 01:46:50 PM PDT 24
Finished Mar 17 01:50:33 PM PDT 24
Peak memory 219308 kb
Host smart-dc129b8a-4e02-41bf-8e24-b71d53fea946
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1852713659 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 5.rom_ctrl_stress_all.1852713659
Directory /workspace/5.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/6.rom_ctrl_alert_test.2179242920
Short name T655
Test name
Test status
Simulation time 3533681720 ps
CPU time 30.19 seconds
Started Mar 17 02:40:00 PM PDT 24
Finished Mar 17 02:40:31 PM PDT 24
Peak memory 211304 kb
Host smart-a1d0e95e-b295-43b4-be54-f4eb8de3981a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2179242920 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_alert_test.2179242920
Directory /workspace/6.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/6.rom_ctrl_alert_test.2885050269
Short name T597
Test name
Test status
Simulation time 2524778770 ps
CPU time 13.07 seconds
Started Mar 17 01:46:52 PM PDT 24
Finished Mar 17 01:47:06 PM PDT 24
Peak memory 211336 kb
Host smart-3e199a56-a002-4c3c-b12b-d820525703df
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2885050269 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_alert_test.2885050269
Directory /workspace/6.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/6.rom_ctrl_corrupt_sig_fatal_chk.2813287805
Short name T573
Test name
Test status
Simulation time 86909410316 ps
CPU time 221.44 seconds
Started Mar 17 01:46:43 PM PDT 24
Finished Mar 17 01:50:26 PM PDT 24
Peak memory 235856 kb
Host smart-95ae1058-a222-4891-90ec-65b2f86f8cee
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2813287805 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_c
orrupt_sig_fatal_chk.2813287805
Directory /workspace/6.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/6.rom_ctrl_corrupt_sig_fatal_chk.648046840
Short name T32
Test name
Test status
Simulation time 49933844181 ps
CPU time 290.64 seconds
Started Mar 17 02:40:01 PM PDT 24
Finished Mar 17 02:44:52 PM PDT 24
Peak memory 218640 kb
Host smart-feb060dc-dc81-44ba-a802-bc58881f24ce
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=648046840 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_co
rrupt_sig_fatal_chk.648046840
Directory /workspace/6.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/6.rom_ctrl_kmac_err_chk.1056494834
Short name T173
Test name
Test status
Simulation time 7794779678 ps
CPU time 56.48 seconds
Started Mar 17 01:46:56 PM PDT 24
Finished Mar 17 01:47:53 PM PDT 24
Peak memory 214256 kb
Host smart-1a8d97d2-6a99-4715-a469-9c057b3338c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1056494834 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_kmac_err_chk.1056494834
Directory /workspace/6.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/6.rom_ctrl_kmac_err_chk.1337149818
Short name T182
Test name
Test status
Simulation time 3273937712 ps
CPU time 39.88 seconds
Started Mar 17 02:40:00 PM PDT 24
Finished Mar 17 02:40:40 PM PDT 24
Peak memory 213760 kb
Host smart-3968a242-30b5-4081-91f9-56c7fbec7d37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1337149818 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_kmac_err_chk.1337149818
Directory /workspace/6.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/6.rom_ctrl_max_throughput_chk.1771140815
Short name T684
Test name
Test status
Simulation time 1646347860 ps
CPU time 20.49 seconds
Started Mar 17 02:40:03 PM PDT 24
Finished Mar 17 02:40:23 PM PDT 24
Peak memory 212188 kb
Host smart-0893c5bf-15e2-4b65-a08d-db6b16a158b8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1771140815 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_max_throughput_chk.1771140815
Directory /workspace/6.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/6.rom_ctrl_max_throughput_chk.4179996982
Short name T545
Test name
Test status
Simulation time 2907694719 ps
CPU time 26.48 seconds
Started Mar 17 01:46:55 PM PDT 24
Finished Mar 17 01:47:22 PM PDT 24
Peak memory 211208 kb
Host smart-6d51cc52-1447-4ea0-9e37-72c19ffbe991
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4179996982 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_max_throughput_chk.4179996982
Directory /workspace/6.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/6.rom_ctrl_smoke.2068568944
Short name T339
Test name
Test status
Simulation time 15792740345 ps
CPU time 48.36 seconds
Started Mar 17 01:46:43 PM PDT 24
Finished Mar 17 01:47:34 PM PDT 24
Peak memory 217872 kb
Host smart-a75592bd-1d57-4e1a-8182-d894e5acb7d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2068568944 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_smoke.2068568944
Directory /workspace/6.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/6.rom_ctrl_smoke.645092798
Short name T637
Test name
Test status
Simulation time 5239443906 ps
CPU time 49.32 seconds
Started Mar 17 02:39:58 PM PDT 24
Finished Mar 17 02:40:48 PM PDT 24
Peak memory 216788 kb
Host smart-c0244c35-e31d-4468-9c9f-e51bc4de612b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=645092798 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_smoke.645092798
Directory /workspace/6.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/6.rom_ctrl_stress_all.1778804779
Short name T303
Test name
Test status
Simulation time 2203735858 ps
CPU time 32.94 seconds
Started Mar 17 01:46:55 PM PDT 24
Finished Mar 17 01:47:28 PM PDT 24
Peak memory 218264 kb
Host smart-c266474a-acf0-4748-b5bf-7f37712d7b9a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1778804779 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 6.rom_ctrl_stress_all.1778804779
Directory /workspace/6.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/6.rom_ctrl_stress_all.280992595
Short name T540
Test name
Test status
Simulation time 59792238900 ps
CPU time 95.8 seconds
Started Mar 17 02:40:03 PM PDT 24
Finished Mar 17 02:41:39 PM PDT 24
Peak memory 219332 kb
Host smart-ca31c849-7591-4992-85b6-2c7d4c05803c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=280992595 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 6.rom_ctrl_stress_all.280992595
Directory /workspace/6.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/6.rom_ctrl_stress_all_with_rand_reset.1902698889
Short name T489
Test name
Test status
Simulation time 137672164831 ps
CPU time 395.82 seconds
Started Mar 17 02:40:06 PM PDT 24
Finished Mar 17 02:46:42 PM PDT 24
Peak memory 235784 kb
Host smart-77910943-ffcb-4af2-8adf-0492255b616c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1902698889 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_stress_all_with_rand_reset.1902698889
Directory /workspace/6.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.rom_ctrl_alert_test.1434605617
Short name T441
Test name
Test status
Simulation time 12784865382 ps
CPU time 27.22 seconds
Started Mar 17 01:46:56 PM PDT 24
Finished Mar 17 01:47:24 PM PDT 24
Peak memory 212060 kb
Host smart-2243ded4-5661-42cb-8d89-7d2e19721055
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1434605617 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_alert_test.1434605617
Directory /workspace/7.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/7.rom_ctrl_alert_test.811983885
Short name T7
Test name
Test status
Simulation time 9303487709 ps
CPU time 30.97 seconds
Started Mar 17 02:40:04 PM PDT 24
Finished Mar 17 02:40:35 PM PDT 24
Peak memory 212108 kb
Host smart-7d471d6e-68ff-48f1-97b3-c5f5c4fb038b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=811983885 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_alert_test.811983885
Directory /workspace/7.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/7.rom_ctrl_corrupt_sig_fatal_chk.3186257348
Short name T33
Test name
Test status
Simulation time 363681662954 ps
CPU time 750.31 seconds
Started Mar 17 01:46:53 PM PDT 24
Finished Mar 17 01:59:23 PM PDT 24
Peak memory 224780 kb
Host smart-65174a3f-ba10-459a-b22c-c88d40ae72bd
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3186257348 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_c
orrupt_sig_fatal_chk.3186257348
Directory /workspace/7.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/7.rom_ctrl_corrupt_sig_fatal_chk.3233975892
Short name T324
Test name
Test status
Simulation time 4324936846 ps
CPU time 139.11 seconds
Started Mar 17 02:39:59 PM PDT 24
Finished Mar 17 02:42:19 PM PDT 24
Peak memory 239892 kb
Host smart-9a6a6bc0-8c0b-47b3-9a43-48b34593bd3b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3233975892 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_c
orrupt_sig_fatal_chk.3233975892
Directory /workspace/7.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/7.rom_ctrl_kmac_err_chk.3523329169
Short name T448
Test name
Test status
Simulation time 19868964963 ps
CPU time 47.38 seconds
Started Mar 17 01:46:51 PM PDT 24
Finished Mar 17 01:47:39 PM PDT 24
Peak memory 215200 kb
Host smart-dd4285c8-7b3c-4de9-ba34-f3e181be18b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3523329169 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_kmac_err_chk.3523329169
Directory /workspace/7.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/7.rom_ctrl_kmac_err_chk.3576114620
Short name T671
Test name
Test status
Simulation time 23838821606 ps
CPU time 54.17 seconds
Started Mar 17 02:40:03 PM PDT 24
Finished Mar 17 02:40:57 PM PDT 24
Peak memory 214848 kb
Host smart-509cc87e-1fb9-4fd0-92de-be199de1f241
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3576114620 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_kmac_err_chk.3576114620
Directory /workspace/7.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/7.rom_ctrl_max_throughput_chk.1364460262
Short name T267
Test name
Test status
Simulation time 6886800070 ps
CPU time 26.21 seconds
Started Mar 17 02:39:59 PM PDT 24
Finished Mar 17 02:40:26 PM PDT 24
Peak memory 211844 kb
Host smart-19f57368-950a-4d38-a2d5-68ddac2cc120
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1364460262 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_max_throughput_chk.1364460262
Directory /workspace/7.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/7.rom_ctrl_max_throughput_chk.951692117
Short name T160
Test name
Test status
Simulation time 47179875732 ps
CPU time 31.76 seconds
Started Mar 17 01:46:56 PM PDT 24
Finished Mar 17 01:47:28 PM PDT 24
Peak memory 211592 kb
Host smart-7ee6ab03-f3bb-425f-90f6-df3092efc96f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=951692117 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_max_throughput_chk.951692117
Directory /workspace/7.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/7.rom_ctrl_smoke.3664747650
Short name T277
Test name
Test status
Simulation time 20202130838 ps
CPU time 48.58 seconds
Started Mar 17 01:46:58 PM PDT 24
Finished Mar 17 01:47:47 PM PDT 24
Peak memory 217964 kb
Host smart-0c46de2e-3bd1-4285-9513-4a566568e5c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3664747650 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_smoke.3664747650
Directory /workspace/7.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/7.rom_ctrl_smoke.3989831737
Short name T464
Test name
Test status
Simulation time 15701716313 ps
CPU time 43.7 seconds
Started Mar 17 02:39:58 PM PDT 24
Finished Mar 17 02:40:42 PM PDT 24
Peak memory 218084 kb
Host smart-f6a5fd93-619e-45e1-a5e9-2c48c82b336a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3989831737 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_smoke.3989831737
Directory /workspace/7.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/7.rom_ctrl_stress_all.1705012602
Short name T423
Test name
Test status
Simulation time 11091437085 ps
CPU time 104.89 seconds
Started Mar 17 01:46:55 PM PDT 24
Finished Mar 17 01:48:40 PM PDT 24
Peak memory 219708 kb
Host smart-6c315c39-18e7-4e32-9a10-2c20553c6dc3
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1705012602 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 7.rom_ctrl_stress_all.1705012602
Directory /workspace/7.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/7.rom_ctrl_stress_all.320211972
Short name T336
Test name
Test status
Simulation time 8285671947 ps
CPU time 91.46 seconds
Started Mar 17 02:40:04 PM PDT 24
Finished Mar 17 02:41:36 PM PDT 24
Peak memory 219156 kb
Host smart-82b484d1-556b-4c19-a1cf-954407e33cc2
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=320211972 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 7.rom_ctrl_stress_all.320211972
Directory /workspace/7.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/8.rom_ctrl_alert_test.2682069598
Short name T232
Test name
Test status
Simulation time 2221141165 ps
CPU time 22.2 seconds
Started Mar 17 02:40:04 PM PDT 24
Finished Mar 17 02:40:26 PM PDT 24
Peak memory 211344 kb
Host smart-a6a8f19e-e240-4cf2-b69c-1050248f43f2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2682069598 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_alert_test.2682069598
Directory /workspace/8.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/8.rom_ctrl_alert_test.4207627820
Short name T529
Test name
Test status
Simulation time 167684823 ps
CPU time 8.23 seconds
Started Mar 17 01:47:00 PM PDT 24
Finished Mar 17 01:47:09 PM PDT 24
Peak memory 211216 kb
Host smart-7a44da87-12da-49e1-9f92-49bb05d40a05
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4207627820 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_alert_test.4207627820
Directory /workspace/8.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/8.rom_ctrl_corrupt_sig_fatal_chk.2525157950
Short name T577
Test name
Test status
Simulation time 112906875924 ps
CPU time 454.74 seconds
Started Mar 17 01:46:53 PM PDT 24
Finished Mar 17 01:54:28 PM PDT 24
Peak memory 224612 kb
Host smart-4fb9a43d-61dd-4c8a-894c-fbbc2dddd78a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2525157950 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_c
orrupt_sig_fatal_chk.2525157950
Directory /workspace/8.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/8.rom_ctrl_corrupt_sig_fatal_chk.3228605205
Short name T192
Test name
Test status
Simulation time 95926347231 ps
CPU time 457.59 seconds
Started Mar 17 02:40:02 PM PDT 24
Finished Mar 17 02:47:40 PM PDT 24
Peak memory 217024 kb
Host smart-44715b7a-f851-4d80-b493-51b27ec66cc6
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3228605205 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_c
orrupt_sig_fatal_chk.3228605205
Directory /workspace/8.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/8.rom_ctrl_kmac_err_chk.2394478456
Short name T624
Test name
Test status
Simulation time 332409581 ps
CPU time 18.69 seconds
Started Mar 17 02:40:18 PM PDT 24
Finished Mar 17 02:40:37 PM PDT 24
Peak memory 214516 kb
Host smart-431edf6a-5b5f-4c3d-b4f6-fc2f6ae505cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2394478456 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_kmac_err_chk.2394478456
Directory /workspace/8.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/8.rom_ctrl_kmac_err_chk.2880870677
Short name T394
Test name
Test status
Simulation time 22540972391 ps
CPU time 51.79 seconds
Started Mar 17 01:47:09 PM PDT 24
Finished Mar 17 01:48:01 PM PDT 24
Peak memory 214916 kb
Host smart-dd2c179a-845c-4be3-9adb-3484eb73b0f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2880870677 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_kmac_err_chk.2880870677
Directory /workspace/8.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/8.rom_ctrl_max_throughput_chk.1196976522
Short name T579
Test name
Test status
Simulation time 24532732109 ps
CPU time 25.98 seconds
Started Mar 17 02:40:09 PM PDT 24
Finished Mar 17 02:40:35 PM PDT 24
Peak memory 212764 kb
Host smart-bc6d8026-21bf-42d5-9f2f-21d12fa841dc
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1196976522 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_max_throughput_chk.1196976522
Directory /workspace/8.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/8.rom_ctrl_max_throughput_chk.3598411175
Short name T546
Test name
Test status
Simulation time 4505426479 ps
CPU time 17.36 seconds
Started Mar 17 01:47:05 PM PDT 24
Finished Mar 17 01:47:23 PM PDT 24
Peak memory 211728 kb
Host smart-86d35543-bd83-4df4-8981-577c33f4fbd9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3598411175 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_max_throughput_chk.3598411175
Directory /workspace/8.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/8.rom_ctrl_smoke.2650806287
Short name T131
Test name
Test status
Simulation time 10696571303 ps
CPU time 49.09 seconds
Started Mar 17 02:40:07 PM PDT 24
Finished Mar 17 02:40:57 PM PDT 24
Peak memory 217924 kb
Host smart-cd2a342f-c3c2-42f4-a8d4-a2de8c2a4bbd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2650806287 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_smoke.2650806287
Directory /workspace/8.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/8.rom_ctrl_smoke.610453105
Short name T603
Test name
Test status
Simulation time 1692990244 ps
CPU time 32.87 seconds
Started Mar 17 01:46:53 PM PDT 24
Finished Mar 17 01:47:26 PM PDT 24
Peak memory 217136 kb
Host smart-73ede4c7-d21f-4087-b6d7-5cb475ffff9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=610453105 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_smoke.610453105
Directory /workspace/8.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/8.rom_ctrl_stress_all.3597355867
Short name T463
Test name
Test status
Simulation time 725570744 ps
CPU time 48.66 seconds
Started Mar 17 02:40:07 PM PDT 24
Finished Mar 17 02:40:55 PM PDT 24
Peak memory 219444 kb
Host smart-372f3b90-b5d8-4034-8c7d-69e4d284e3d8
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3597355867 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 8.rom_ctrl_stress_all.3597355867
Directory /workspace/8.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/8.rom_ctrl_stress_all.524316719
Short name T429
Test name
Test status
Simulation time 1839459488 ps
CPU time 35.14 seconds
Started Mar 17 01:47:00 PM PDT 24
Finished Mar 17 01:47:35 PM PDT 24
Peak memory 217024 kb
Host smart-5bfd01d9-d959-4c74-aa34-14da2a0e9380
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=524316719 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 8.rom_ctrl_stress_all.524316719
Directory /workspace/8.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/9.rom_ctrl_alert_test.3619466278
Short name T200
Test name
Test status
Simulation time 4874666873 ps
CPU time 21.63 seconds
Started Mar 17 01:46:57 PM PDT 24
Finished Mar 17 01:47:20 PM PDT 24
Peak memory 211260 kb
Host smart-7fa4cb16-be4e-46c7-8d2d-6006b61cc6d7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3619466278 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_alert_test.3619466278
Directory /workspace/9.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/9.rom_ctrl_alert_test.3854201094
Short name T280
Test name
Test status
Simulation time 3696779446 ps
CPU time 13.77 seconds
Started Mar 17 02:40:07 PM PDT 24
Finished Mar 17 02:40:21 PM PDT 24
Peak memory 211224 kb
Host smart-3d796589-7f27-4fc0-ae54-45db42cde433
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3854201094 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_alert_test.3854201094
Directory /workspace/9.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/9.rom_ctrl_corrupt_sig_fatal_chk.3415285070
Short name T538
Test name
Test status
Simulation time 97066526686 ps
CPU time 438.44 seconds
Started Mar 17 02:40:18 PM PDT 24
Finished Mar 17 02:47:36 PM PDT 24
Peak memory 228212 kb
Host smart-da0643a8-dec8-4029-9fae-9dfbd8649c2b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3415285070 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_c
orrupt_sig_fatal_chk.3415285070
Directory /workspace/9.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/9.rom_ctrl_corrupt_sig_fatal_chk.4266855072
Short name T662
Test name
Test status
Simulation time 31519342857 ps
CPU time 380.03 seconds
Started Mar 17 01:46:53 PM PDT 24
Finished Mar 17 01:53:13 PM PDT 24
Peak memory 239764 kb
Host smart-a5282815-a598-4883-b568-c594bdd541b6
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4266855072 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_c
orrupt_sig_fatal_chk.4266855072
Directory /workspace/9.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/9.rom_ctrl_kmac_err_chk.1405723446
Short name T619
Test name
Test status
Simulation time 28458340461 ps
CPU time 57.08 seconds
Started Mar 17 01:46:58 PM PDT 24
Finished Mar 17 01:47:55 PM PDT 24
Peak memory 213820 kb
Host smart-52caa56c-eeee-4066-9518-5758a79fb1a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1405723446 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_kmac_err_chk.1405723446
Directory /workspace/9.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/9.rom_ctrl_kmac_err_chk.2350587055
Short name T510
Test name
Test status
Simulation time 7351971057 ps
CPU time 40.61 seconds
Started Mar 17 02:40:06 PM PDT 24
Finished Mar 17 02:40:47 PM PDT 24
Peak memory 214992 kb
Host smart-02db9a3a-756b-4e4b-972e-ce21914f3418
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2350587055 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_kmac_err_chk.2350587055
Directory /workspace/9.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/9.rom_ctrl_max_throughput_chk.2956995920
Short name T165
Test name
Test status
Simulation time 4218831937 ps
CPU time 22.75 seconds
Started Mar 17 02:40:18 PM PDT 24
Finished Mar 17 02:40:41 PM PDT 24
Peak memory 211436 kb
Host smart-6ce6c492-ba9f-4f26-89ef-19c75c62e04a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2956995920 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_max_throughput_chk.2956995920
Directory /workspace/9.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/9.rom_ctrl_max_throughput_chk.3871318900
Short name T337
Test name
Test status
Simulation time 17081739637 ps
CPU time 35.31 seconds
Started Mar 17 01:46:57 PM PDT 24
Finished Mar 17 01:47:33 PM PDT 24
Peak memory 211328 kb
Host smart-dd8d43ba-5a1e-461f-8f79-cdac03a49141
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3871318900 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_max_throughput_chk.3871318900
Directory /workspace/9.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/9.rom_ctrl_smoke.1588278855
Short name T350
Test name
Test status
Simulation time 20069397047 ps
CPU time 45 seconds
Started Mar 17 01:46:50 PM PDT 24
Finished Mar 17 01:47:35 PM PDT 24
Peak memory 217856 kb
Host smart-9b4e76c1-ad1e-4055-b3ec-8c59b2915bfa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1588278855 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_smoke.1588278855
Directory /workspace/9.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/9.rom_ctrl_smoke.2369960580
Short name T466
Test name
Test status
Simulation time 70031024949 ps
CPU time 73.25 seconds
Started Mar 17 02:40:03 PM PDT 24
Finished Mar 17 02:41:16 PM PDT 24
Peak memory 216884 kb
Host smart-8eaf4196-1b9f-43e8-a7f1-97191a75355a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2369960580 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_smoke.2369960580
Directory /workspace/9.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/9.rom_ctrl_stress_all.1974511372
Short name T148
Test name
Test status
Simulation time 10017917676 ps
CPU time 31.49 seconds
Started Mar 17 01:46:53 PM PDT 24
Finished Mar 17 01:47:25 PM PDT 24
Peak memory 214112 kb
Host smart-e3f91e91-fa64-4185-81ab-4cfaf0bec0c4
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1974511372 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 9.rom_ctrl_stress_all.1974511372
Directory /workspace/9.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/9.rom_ctrl_stress_all.3015988498
Short name T567
Test name
Test status
Simulation time 15629942227 ps
CPU time 170.27 seconds
Started Mar 17 02:40:02 PM PDT 24
Finished Mar 17 02:42:53 PM PDT 24
Peak memory 220020 kb
Host smart-8881591d-ee12-4a58-b39e-1688d37317e2
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3015988498 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 9.rom_ctrl_stress_all.3015988498
Directory /workspace/9.rom_ctrl_stress_all/latest
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