| T546 |
/workspace/coverage/default/39.rom_ctrl_corrupt_sig_fatal_chk.1309182422 |
|
|
Apr 02 12:49:17 PM PDT 24 |
Apr 02 12:51:38 PM PDT 24 |
4957646770 ps |
| T547 |
/workspace/coverage/default/6.rom_ctrl_max_throughput_chk.2217169358 |
|
|
Apr 02 12:33:48 PM PDT 24 |
Apr 02 12:34:21 PM PDT 24 |
11302215874 ps |
| T548 |
/workspace/coverage/default/6.rom_ctrl_smoke.2570090370 |
|
|
Apr 02 12:33:51 PM PDT 24 |
Apr 02 12:34:11 PM PDT 24 |
699705069 ps |
| T549 |
/workspace/coverage/default/7.rom_ctrl_smoke.4223277755 |
|
|
Apr 02 12:33:42 PM PDT 24 |
Apr 02 12:34:20 PM PDT 24 |
3287280001 ps |
| T550 |
/workspace/coverage/default/41.rom_ctrl_alert_test.3272631418 |
|
|
Apr 02 12:34:53 PM PDT 24 |
Apr 02 12:35:21 PM PDT 24 |
23882944252 ps |
| T551 |
/workspace/coverage/default/32.rom_ctrl_kmac_err_chk.1727731155 |
|
|
Apr 02 12:34:31 PM PDT 24 |
Apr 02 12:35:13 PM PDT 24 |
14509577421 ps |
| T552 |
/workspace/coverage/default/20.rom_ctrl_corrupt_sig_fatal_chk.3730100528 |
|
|
Apr 02 12:48:37 PM PDT 24 |
Apr 02 12:53:58 PM PDT 24 |
196994424770 ps |
| T553 |
/workspace/coverage/default/44.rom_ctrl_alert_test.2123227572 |
|
|
Apr 02 12:34:58 PM PDT 24 |
Apr 02 12:35:30 PM PDT 24 |
4263636929 ps |
| T554 |
/workspace/coverage/default/2.rom_ctrl_smoke.474043889 |
|
|
Apr 02 12:33:34 PM PDT 24 |
Apr 02 12:34:43 PM PDT 24 |
22468775720 ps |
| T555 |
/workspace/coverage/default/11.rom_ctrl_smoke.3724885551 |
|
|
Apr 02 12:48:12 PM PDT 24 |
Apr 02 12:48:33 PM PDT 24 |
677589515 ps |
| T556 |
/workspace/coverage/default/38.rom_ctrl_max_throughput_chk.2758648522 |
|
|
Apr 02 12:34:48 PM PDT 24 |
Apr 02 12:35:19 PM PDT 24 |
7826096203 ps |
| T557 |
/workspace/coverage/default/31.rom_ctrl_stress_all_with_rand_reset.1384791564 |
|
|
Apr 02 12:34:30 PM PDT 24 |
Apr 02 01:19:30 PM PDT 24 |
63290956809 ps |
| T558 |
/workspace/coverage/default/3.rom_ctrl_alert_test.3934514469 |
|
|
Apr 02 12:47:58 PM PDT 24 |
Apr 02 12:48:22 PM PDT 24 |
2634056840 ps |
| T559 |
/workspace/coverage/default/33.rom_ctrl_smoke.2834118574 |
|
|
Apr 02 12:34:30 PM PDT 24 |
Apr 02 12:35:55 PM PDT 24 |
7693769028 ps |
| T560 |
/workspace/coverage/default/16.rom_ctrl_smoke.932003322 |
|
|
Apr 02 12:34:02 PM PDT 24 |
Apr 02 12:34:44 PM PDT 24 |
8033966158 ps |
| T561 |
/workspace/coverage/default/24.rom_ctrl_kmac_err_chk.2023270708 |
|
|
Apr 02 12:34:09 PM PDT 24 |
Apr 02 12:34:55 PM PDT 24 |
18413172805 ps |
| T562 |
/workspace/coverage/default/30.rom_ctrl_smoke.3139367465 |
|
|
Apr 02 12:48:54 PM PDT 24 |
Apr 02 12:49:51 PM PDT 24 |
4633108765 ps |
| T563 |
/workspace/coverage/default/26.rom_ctrl_corrupt_sig_fatal_chk.3120219303 |
|
|
Apr 02 12:48:41 PM PDT 24 |
Apr 02 12:53:57 PM PDT 24 |
74660551377 ps |
| T564 |
/workspace/coverage/default/45.rom_ctrl_kmac_err_chk.2007158737 |
|
|
Apr 02 12:34:56 PM PDT 24 |
Apr 02 12:35:37 PM PDT 24 |
7536043512 ps |
| T565 |
/workspace/coverage/default/27.rom_ctrl_stress_all.1757000558 |
|
|
Apr 02 12:34:21 PM PDT 24 |
Apr 02 12:36:14 PM PDT 24 |
13924663954 ps |
| T566 |
/workspace/coverage/default/14.rom_ctrl_corrupt_sig_fatal_chk.2298876704 |
|
|
Apr 02 12:33:57 PM PDT 24 |
Apr 02 12:39:11 PM PDT 24 |
14348522542 ps |
| T567 |
/workspace/coverage/default/8.rom_ctrl_stress_all.1884926607 |
|
|
Apr 02 12:33:48 PM PDT 24 |
Apr 02 12:34:06 PM PDT 24 |
2528088724 ps |
| T568 |
/workspace/coverage/default/17.rom_ctrl_kmac_err_chk.733133593 |
|
|
Apr 02 12:48:26 PM PDT 24 |
Apr 02 12:48:51 PM PDT 24 |
2568421745 ps |
| T569 |
/workspace/coverage/default/5.rom_ctrl_corrupt_sig_fatal_chk.2743568395 |
|
|
Apr 02 12:33:42 PM PDT 24 |
Apr 02 12:36:49 PM PDT 24 |
3784684991 ps |
| T570 |
/workspace/coverage/default/12.rom_ctrl_max_throughput_chk.3803098930 |
|
|
Apr 02 12:33:51 PM PDT 24 |
Apr 02 12:34:21 PM PDT 24 |
3616966235 ps |
| T571 |
/workspace/coverage/default/37.rom_ctrl_max_throughput_chk.826555874 |
|
|
Apr 02 12:34:42 PM PDT 24 |
Apr 02 12:35:08 PM PDT 24 |
10166335868 ps |
| T572 |
/workspace/coverage/default/16.rom_ctrl_alert_test.478661467 |
|
|
Apr 02 12:34:02 PM PDT 24 |
Apr 02 12:34:23 PM PDT 24 |
7873049832 ps |
| T573 |
/workspace/coverage/default/5.rom_ctrl_stress_all.3857257391 |
|
|
Apr 02 12:48:05 PM PDT 24 |
Apr 02 12:48:44 PM PDT 24 |
2188830482 ps |
| T574 |
/workspace/coverage/default/27.rom_ctrl_alert_test.1555745894 |
|
|
Apr 02 12:34:16 PM PDT 24 |
Apr 02 12:34:25 PM PDT 24 |
169220692 ps |
| T575 |
/workspace/coverage/default/44.rom_ctrl_smoke.589554479 |
|
|
Apr 02 12:49:25 PM PDT 24 |
Apr 02 12:50:16 PM PDT 24 |
15857376105 ps |
| T576 |
/workspace/coverage/default/43.rom_ctrl_stress_all.4054413321 |
|
|
Apr 02 12:34:57 PM PDT 24 |
Apr 02 12:35:12 PM PDT 24 |
222072975 ps |
| T577 |
/workspace/coverage/default/5.rom_ctrl_alert_test.3452528773 |
|
|
Apr 02 12:33:45 PM PDT 24 |
Apr 02 12:34:09 PM PDT 24 |
11175017584 ps |
| T578 |
/workspace/coverage/default/12.rom_ctrl_alert_test.3197164777 |
|
|
Apr 02 12:48:18 PM PDT 24 |
Apr 02 12:48:28 PM PDT 24 |
249485603 ps |
| T579 |
/workspace/coverage/default/34.rom_ctrl_alert_test.2346567414 |
|
|
Apr 02 12:49:04 PM PDT 24 |
Apr 02 12:49:34 PM PDT 24 |
2650766876 ps |
| T580 |
/workspace/coverage/default/4.rom_ctrl_stress_all.3096649910 |
|
|
Apr 02 12:48:06 PM PDT 24 |
Apr 02 12:50:53 PM PDT 24 |
28047957102 ps |
| T581 |
/workspace/coverage/default/46.rom_ctrl_smoke.677075777 |
|
|
Apr 02 12:34:57 PM PDT 24 |
Apr 02 12:35:16 PM PDT 24 |
1419816226 ps |
| T582 |
/workspace/coverage/default/1.rom_ctrl_alert_test.2816913907 |
|
|
Apr 02 12:47:56 PM PDT 24 |
Apr 02 12:48:12 PM PDT 24 |
4936160511 ps |
| T583 |
/workspace/coverage/default/29.rom_ctrl_max_throughput_chk.2238030020 |
|
|
Apr 02 12:48:48 PM PDT 24 |
Apr 02 12:49:08 PM PDT 24 |
11706823186 ps |
| T584 |
/workspace/coverage/default/45.rom_ctrl_alert_test.3614738026 |
|
|
Apr 02 12:34:58 PM PDT 24 |
Apr 02 12:35:30 PM PDT 24 |
4003846024 ps |
| T585 |
/workspace/coverage/default/6.rom_ctrl_smoke.3164722247 |
|
|
Apr 02 12:48:04 PM PDT 24 |
Apr 02 12:48:55 PM PDT 24 |
5306880174 ps |
| T586 |
/workspace/coverage/default/24.rom_ctrl_alert_test.3327763684 |
|
|
Apr 02 12:48:32 PM PDT 24 |
Apr 02 12:48:58 PM PDT 24 |
2646795429 ps |
| T587 |
/workspace/coverage/default/44.rom_ctrl_corrupt_sig_fatal_chk.345365217 |
|
|
Apr 02 12:49:26 PM PDT 24 |
Apr 02 01:01:07 PM PDT 24 |
116285271349 ps |
| T588 |
/workspace/coverage/default/2.rom_ctrl_max_throughput_chk.2945631593 |
|
|
Apr 02 12:47:55 PM PDT 24 |
Apr 02 12:48:05 PM PDT 24 |
2461559210 ps |
| T589 |
/workspace/coverage/default/23.rom_ctrl_corrupt_sig_fatal_chk.964202030 |
|
|
Apr 02 12:48:28 PM PDT 24 |
Apr 02 12:50:25 PM PDT 24 |
7614977568 ps |
| T590 |
/workspace/coverage/default/28.rom_ctrl_smoke.4270090938 |
|
|
Apr 02 12:48:44 PM PDT 24 |
Apr 02 12:49:50 PM PDT 24 |
8391821142 ps |
| T591 |
/workspace/coverage/default/12.rom_ctrl_max_throughput_chk.3359455016 |
|
|
Apr 02 12:48:16 PM PDT 24 |
Apr 02 12:48:34 PM PDT 24 |
1088186084 ps |
| T592 |
/workspace/coverage/default/23.rom_ctrl_smoke.1720863131 |
|
|
Apr 02 12:34:21 PM PDT 24 |
Apr 02 12:35:41 PM PDT 24 |
31642809868 ps |
| T593 |
/workspace/coverage/default/33.rom_ctrl_corrupt_sig_fatal_chk.3942406569 |
|
|
Apr 02 12:34:33 PM PDT 24 |
Apr 02 12:37:42 PM PDT 24 |
13059293657 ps |
| T594 |
/workspace/coverage/default/40.rom_ctrl_stress_all.3064985780 |
|
|
Apr 02 12:49:21 PM PDT 24 |
Apr 02 12:50:46 PM PDT 24 |
19707633836 ps |
| T595 |
/workspace/coverage/default/9.rom_ctrl_stress_all.1710668814 |
|
|
Apr 02 12:33:46 PM PDT 24 |
Apr 02 12:34:16 PM PDT 24 |
4121487924 ps |
| T596 |
/workspace/coverage/default/11.rom_ctrl_max_throughput_chk.1072086700 |
|
|
Apr 02 12:48:16 PM PDT 24 |
Apr 02 12:48:48 PM PDT 24 |
7035709715 ps |
| T597 |
/workspace/coverage/default/20.rom_ctrl_stress_all.1952512381 |
|
|
Apr 02 12:48:29 PM PDT 24 |
Apr 02 12:49:31 PM PDT 24 |
16862256975 ps |
| T598 |
/workspace/coverage/default/26.rom_ctrl_corrupt_sig_fatal_chk.544894809 |
|
|
Apr 02 12:34:08 PM PDT 24 |
Apr 02 12:38:42 PM PDT 24 |
16252220717 ps |
| T599 |
/workspace/coverage/default/28.rom_ctrl_corrupt_sig_fatal_chk.1167836488 |
|
|
Apr 02 12:34:17 PM PDT 24 |
Apr 02 12:37:02 PM PDT 24 |
2686771152 ps |
| T600 |
/workspace/coverage/default/17.rom_ctrl_smoke.3498481149 |
|
|
Apr 02 12:34:03 PM PDT 24 |
Apr 02 12:34:24 PM PDT 24 |
384914985 ps |
| T601 |
/workspace/coverage/default/21.rom_ctrl_max_throughput_chk.617551192 |
|
|
Apr 02 12:34:09 PM PDT 24 |
Apr 02 12:34:37 PM PDT 24 |
5168511842 ps |
| T602 |
/workspace/coverage/default/18.rom_ctrl_max_throughput_chk.2451902734 |
|
|
Apr 02 12:34:02 PM PDT 24 |
Apr 02 12:34:30 PM PDT 24 |
9455285149 ps |
| T603 |
/workspace/coverage/default/5.rom_ctrl_corrupt_sig_fatal_chk.1545481375 |
|
|
Apr 02 12:48:07 PM PDT 24 |
Apr 02 12:53:14 PM PDT 24 |
4686121079 ps |
| T604 |
/workspace/coverage/default/43.rom_ctrl_alert_test.617138656 |
|
|
Apr 02 12:34:56 PM PDT 24 |
Apr 02 12:35:17 PM PDT 24 |
7824139029 ps |
| T120 |
/workspace/coverage/default/44.rom_ctrl_stress_all_with_rand_reset.3958524397 |
|
|
Apr 02 12:34:57 PM PDT 24 |
Apr 02 12:54:09 PM PDT 24 |
29093682755 ps |
| T605 |
/workspace/coverage/default/46.rom_ctrl_max_throughput_chk.2307799685 |
|
|
Apr 02 12:35:01 PM PDT 24 |
Apr 02 12:35:21 PM PDT 24 |
5804121898 ps |
| T606 |
/workspace/coverage/default/4.rom_ctrl_max_throughput_chk.2533391396 |
|
|
Apr 02 12:33:38 PM PDT 24 |
Apr 02 12:34:00 PM PDT 24 |
3550290786 ps |
| T607 |
/workspace/coverage/default/47.rom_ctrl_kmac_err_chk.2151175430 |
|
|
Apr 02 12:49:32 PM PDT 24 |
Apr 02 12:50:38 PM PDT 24 |
33411891105 ps |
| T608 |
/workspace/coverage/default/27.rom_ctrl_smoke.2621814248 |
|
|
Apr 02 12:34:20 PM PDT 24 |
Apr 02 12:34:52 PM PDT 24 |
7274977313 ps |
| T609 |
/workspace/coverage/default/21.rom_ctrl_max_throughput_chk.2568468932 |
|
|
Apr 02 12:48:27 PM PDT 24 |
Apr 02 12:48:46 PM PDT 24 |
4018491872 ps |
| T610 |
/workspace/coverage/default/36.rom_ctrl_alert_test.3659752930 |
|
|
Apr 02 12:49:07 PM PDT 24 |
Apr 02 12:49:36 PM PDT 24 |
6531885543 ps |
| T611 |
/workspace/coverage/default/30.rom_ctrl_max_throughput_chk.2146035359 |
|
|
Apr 02 12:34:23 PM PDT 24 |
Apr 02 12:34:56 PM PDT 24 |
16076979482 ps |
| T612 |
/workspace/coverage/default/12.rom_ctrl_corrupt_sig_fatal_chk.2217317163 |
|
|
Apr 02 12:33:50 PM PDT 24 |
Apr 02 12:49:49 PM PDT 24 |
97554002129 ps |
| T613 |
/workspace/coverage/default/49.rom_ctrl_kmac_err_chk.2930422048 |
|
|
Apr 02 12:49:38 PM PDT 24 |
Apr 02 12:50:44 PM PDT 24 |
7744607246 ps |
| T614 |
/workspace/coverage/default/0.rom_ctrl_alert_test.923018942 |
|
|
Apr 02 12:47:55 PM PDT 24 |
Apr 02 12:48:19 PM PDT 24 |
10151150371 ps |
| T615 |
/workspace/coverage/default/24.rom_ctrl_alert_test.1526319528 |
|
|
Apr 02 12:34:10 PM PDT 24 |
Apr 02 12:34:38 PM PDT 24 |
3509930699 ps |
| T616 |
/workspace/coverage/default/26.rom_ctrl_alert_test.662413319 |
|
|
Apr 02 12:34:10 PM PDT 24 |
Apr 02 12:34:30 PM PDT 24 |
2050761164 ps |
| T617 |
/workspace/coverage/default/13.rom_ctrl_alert_test.3409621473 |
|
|
Apr 02 12:33:57 PM PDT 24 |
Apr 02 12:34:08 PM PDT 24 |
1977823720 ps |
| T618 |
/workspace/coverage/default/2.rom_ctrl_alert_test.192718863 |
|
|
Apr 02 12:47:59 PM PDT 24 |
Apr 02 12:48:22 PM PDT 24 |
8476093136 ps |
| T619 |
/workspace/coverage/default/38.rom_ctrl_kmac_err_chk.534633646 |
|
|
Apr 02 12:49:15 PM PDT 24 |
Apr 02 12:49:35 PM PDT 24 |
735282482 ps |
| T620 |
/workspace/coverage/default/29.rom_ctrl_stress_all.2171569558 |
|
|
Apr 02 12:48:48 PM PDT 24 |
Apr 02 12:49:26 PM PDT 24 |
3192455503 ps |
| T621 |
/workspace/coverage/default/4.rom_ctrl_alert_test.609216310 |
|
|
Apr 02 12:48:05 PM PDT 24 |
Apr 02 12:48:16 PM PDT 24 |
2997630466 ps |
| T622 |
/workspace/coverage/default/10.rom_ctrl_corrupt_sig_fatal_chk.2427567546 |
|
|
Apr 02 12:33:52 PM PDT 24 |
Apr 02 12:39:17 PM PDT 24 |
14362382546 ps |
| T623 |
/workspace/coverage/default/7.rom_ctrl_corrupt_sig_fatal_chk.3541441231 |
|
|
Apr 02 12:33:42 PM PDT 24 |
Apr 02 12:44:37 PM PDT 24 |
222352285349 ps |
| T624 |
/workspace/coverage/default/25.rom_ctrl_kmac_err_chk.4021364571 |
|
|
Apr 02 12:34:11 PM PDT 24 |
Apr 02 12:34:41 PM PDT 24 |
6153418248 ps |
| T625 |
/workspace/coverage/default/11.rom_ctrl_stress_all_with_rand_reset.2489978091 |
|
|
Apr 02 12:48:15 PM PDT 24 |
Apr 02 01:43:42 PM PDT 24 |
83773330862 ps |
| T626 |
/workspace/coverage/default/22.rom_ctrl_corrupt_sig_fatal_chk.2065716489 |
|
|
Apr 02 12:48:26 PM PDT 24 |
Apr 02 12:52:47 PM PDT 24 |
14894049020 ps |
| T627 |
/workspace/coverage/default/46.rom_ctrl_max_throughput_chk.420710194 |
|
|
Apr 02 12:49:32 PM PDT 24 |
Apr 02 12:49:54 PM PDT 24 |
2251657370 ps |
| T628 |
/workspace/coverage/default/24.rom_ctrl_corrupt_sig_fatal_chk.2943762044 |
|
|
Apr 02 12:48:28 PM PDT 24 |
Apr 02 12:55:09 PM PDT 24 |
60410820182 ps |
| T629 |
/workspace/coverage/default/22.rom_ctrl_kmac_err_chk.104226907 |
|
|
Apr 02 12:34:21 PM PDT 24 |
Apr 02 12:35:29 PM PDT 24 |
8663753088 ps |
| T630 |
/workspace/coverage/default/46.rom_ctrl_corrupt_sig_fatal_chk.3346540319 |
|
|
Apr 02 12:49:32 PM PDT 24 |
Apr 02 12:55:30 PM PDT 24 |
17240382664 ps |
| T631 |
/workspace/coverage/default/34.rom_ctrl_kmac_err_chk.25915945 |
|
|
Apr 02 12:49:02 PM PDT 24 |
Apr 02 12:49:54 PM PDT 24 |
14053952042 ps |
| T632 |
/workspace/coverage/default/31.rom_ctrl_stress_all.3378089365 |
|
|
Apr 02 12:34:26 PM PDT 24 |
Apr 02 12:35:33 PM PDT 24 |
28523839765 ps |
| T633 |
/workspace/coverage/default/0.rom_ctrl_stress_all.307665403 |
|
|
Apr 02 12:47:55 PM PDT 24 |
Apr 02 12:48:10 PM PDT 24 |
6914310130 ps |
| T634 |
/workspace/coverage/default/35.rom_ctrl_smoke.2525436870 |
|
|
Apr 02 12:49:02 PM PDT 24 |
Apr 02 12:50:04 PM PDT 24 |
19917583089 ps |
| T635 |
/workspace/coverage/default/5.rom_ctrl_alert_test.1357145697 |
|
|
Apr 02 12:48:04 PM PDT 24 |
Apr 02 12:48:15 PM PDT 24 |
1034510299 ps |
| T636 |
/workspace/coverage/default/35.rom_ctrl_smoke.3651399959 |
|
|
Apr 02 12:34:38 PM PDT 24 |
Apr 02 12:35:21 PM PDT 24 |
3482964535 ps |
| T637 |
/workspace/coverage/default/42.rom_ctrl_stress_all.260754395 |
|
|
Apr 02 12:49:19 PM PDT 24 |
Apr 02 12:49:34 PM PDT 24 |
252509758 ps |
| T638 |
/workspace/coverage/default/29.rom_ctrl_smoke.1301899276 |
|
|
Apr 02 12:34:18 PM PDT 24 |
Apr 02 12:34:49 PM PDT 24 |
16590986400 ps |
| T639 |
/workspace/coverage/default/4.rom_ctrl_alert_test.3029107282 |
|
|
Apr 02 12:33:37 PM PDT 24 |
Apr 02 12:33:45 PM PDT 24 |
1032656840 ps |
| T640 |
/workspace/coverage/default/1.rom_ctrl_kmac_err_chk.1254517557 |
|
|
Apr 02 12:47:57 PM PDT 24 |
Apr 02 12:49:05 PM PDT 24 |
19041673075 ps |
| T641 |
/workspace/coverage/default/37.rom_ctrl_kmac_err_chk.773004894 |
|
|
Apr 02 12:49:11 PM PDT 24 |
Apr 02 12:49:58 PM PDT 24 |
4676329812 ps |
| T642 |
/workspace/coverage/default/15.rom_ctrl_smoke.3888997223 |
|
|
Apr 02 12:48:22 PM PDT 24 |
Apr 02 12:49:32 PM PDT 24 |
26724066546 ps |
| T643 |
/workspace/coverage/default/46.rom_ctrl_corrupt_sig_fatal_chk.3534217005 |
|
|
Apr 02 12:35:00 PM PDT 24 |
Apr 02 12:40:56 PM PDT 24 |
258524289867 ps |
| T644 |
/workspace/coverage/default/6.rom_ctrl_kmac_err_chk.2364124071 |
|
|
Apr 02 12:33:42 PM PDT 24 |
Apr 02 12:34:35 PM PDT 24 |
22988323828 ps |
| T645 |
/workspace/coverage/default/6.rom_ctrl_max_throughput_chk.3902899001 |
|
|
Apr 02 12:48:03 PM PDT 24 |
Apr 02 12:48:26 PM PDT 24 |
4048000944 ps |
| T646 |
/workspace/coverage/default/35.rom_ctrl_corrupt_sig_fatal_chk.796530950 |
|
|
Apr 02 12:49:08 PM PDT 24 |
Apr 02 12:52:51 PM PDT 24 |
3113214826 ps |
| T647 |
/workspace/coverage/default/40.rom_ctrl_max_throughput_chk.593919893 |
|
|
Apr 02 12:49:21 PM PDT 24 |
Apr 02 12:49:50 PM PDT 24 |
39008271778 ps |
| T648 |
/workspace/coverage/default/4.rom_ctrl_corrupt_sig_fatal_chk.1843808903 |
|
|
Apr 02 12:48:08 PM PDT 24 |
Apr 02 12:54:26 PM PDT 24 |
155192340389 ps |
| T649 |
/workspace/coverage/default/25.rom_ctrl_corrupt_sig_fatal_chk.1681628138 |
|
|
Apr 02 12:48:34 PM PDT 24 |
Apr 02 12:50:27 PM PDT 24 |
1761465298 ps |
| T650 |
/workspace/coverage/default/34.rom_ctrl_max_throughput_chk.3665158550 |
|
|
Apr 02 12:49:01 PM PDT 24 |
Apr 02 12:49:32 PM PDT 24 |
7922463765 ps |
| T651 |
/workspace/coverage/default/7.rom_ctrl_max_throughput_chk.2869002858 |
|
|
Apr 02 12:48:10 PM PDT 24 |
Apr 02 12:48:45 PM PDT 24 |
3956743841 ps |
| T652 |
/workspace/coverage/default/43.rom_ctrl_max_throughput_chk.3660835608 |
|
|
Apr 02 12:49:27 PM PDT 24 |
Apr 02 12:49:46 PM PDT 24 |
2796054891 ps |
| T653 |
/workspace/coverage/default/26.rom_ctrl_stress_all.83119205 |
|
|
Apr 02 12:48:42 PM PDT 24 |
Apr 02 12:49:19 PM PDT 24 |
1085442065 ps |
| T654 |
/workspace/coverage/default/8.rom_ctrl_max_throughput_chk.3022204203 |
|
|
Apr 02 12:48:08 PM PDT 24 |
Apr 02 12:48:32 PM PDT 24 |
2062104575 ps |
| T655 |
/workspace/coverage/default/14.rom_ctrl_max_throughput_chk.340904258 |
|
|
Apr 02 12:33:54 PM PDT 24 |
Apr 02 12:34:08 PM PDT 24 |
609578247 ps |
| T28 |
/workspace/coverage/default/48.rom_ctrl_kmac_err_chk.1331639724 |
|
|
Apr 02 12:49:37 PM PDT 24 |
Apr 02 12:50:40 PM PDT 24 |
13723881399 ps |
| T656 |
/workspace/coverage/default/37.rom_ctrl_alert_test.536324263 |
|
|
Apr 02 12:49:12 PM PDT 24 |
Apr 02 12:49:43 PM PDT 24 |
3749581130 ps |
| T657 |
/workspace/coverage/default/43.rom_ctrl_max_throughput_chk.2156329033 |
|
|
Apr 02 12:34:55 PM PDT 24 |
Apr 02 12:35:06 PM PDT 24 |
864360045 ps |
| T658 |
/workspace/coverage/default/31.rom_ctrl_kmac_err_chk.3034750180 |
|
|
Apr 02 12:34:33 PM PDT 24 |
Apr 02 12:35:32 PM PDT 24 |
6704455014 ps |
| T659 |
/workspace/coverage/default/47.rom_ctrl_alert_test.1093963694 |
|
|
Apr 02 12:35:04 PM PDT 24 |
Apr 02 12:35:18 PM PDT 24 |
1646278963 ps |
| T660 |
/workspace/coverage/default/9.rom_ctrl_corrupt_sig_fatal_chk.2653002239 |
|
|
Apr 02 12:48:12 PM PDT 24 |
Apr 02 01:01:17 PM PDT 24 |
70445990118 ps |
| T661 |
/workspace/coverage/default/25.rom_ctrl_corrupt_sig_fatal_chk.2398058681 |
|
|
Apr 02 12:34:10 PM PDT 24 |
Apr 02 12:38:35 PM PDT 24 |
52106322110 ps |
| T662 |
/workspace/coverage/default/15.rom_ctrl_kmac_err_chk.1794110964 |
|
|
Apr 02 12:34:00 PM PDT 24 |
Apr 02 12:34:19 PM PDT 24 |
1737638938 ps |
| T663 |
/workspace/coverage/default/14.rom_ctrl_stress_all.1775375576 |
|
|
Apr 02 12:48:26 PM PDT 24 |
Apr 02 12:49:15 PM PDT 24 |
18885287628 ps |
| T664 |
/workspace/coverage/default/21.rom_ctrl_stress_all.4184555905 |
|
|
Apr 02 12:34:03 PM PDT 24 |
Apr 02 12:34:27 PM PDT 24 |
3041743361 ps |
| T665 |
/workspace/coverage/default/41.rom_ctrl_smoke.3931764173 |
|
|
Apr 02 12:34:49 PM PDT 24 |
Apr 02 12:35:12 PM PDT 24 |
689340826 ps |
| T666 |
/workspace/coverage/default/9.rom_ctrl_stress_all.313615922 |
|
|
Apr 02 12:48:12 PM PDT 24 |
Apr 02 12:48:42 PM PDT 24 |
10388531783 ps |
| T667 |
/workspace/coverage/default/47.rom_ctrl_kmac_err_chk.1163358827 |
|
|
Apr 02 12:35:01 PM PDT 24 |
Apr 02 12:35:26 PM PDT 24 |
663493011 ps |
| T134 |
/workspace/coverage/default/16.rom_ctrl_stress_all.2230306888 |
|
|
Apr 02 12:48:25 PM PDT 24 |
Apr 02 12:49:20 PM PDT 24 |
1839138711 ps |
| T668 |
/workspace/coverage/default/41.rom_ctrl_alert_test.1082175641 |
|
|
Apr 02 12:49:21 PM PDT 24 |
Apr 02 12:49:30 PM PDT 24 |
331952513 ps |
| T669 |
/workspace/coverage/default/0.rom_ctrl_alert_test.2861861914 |
|
|
Apr 02 12:33:40 PM PDT 24 |
Apr 02 12:34:00 PM PDT 24 |
2125568860 ps |
| T65 |
/workspace/coverage/cover_reg_top/1.rom_ctrl_csr_aliasing.1811276047 |
|
|
Apr 02 12:35:15 PM PDT 24 |
Apr 02 12:35:34 PM PDT 24 |
3414567354 ps |
| T66 |
/workspace/coverage/cover_reg_top/4.rom_ctrl_same_csr_outstanding.2996387526 |
|
|
Apr 02 12:35:24 PM PDT 24 |
Apr 02 12:35:32 PM PDT 24 |
718569980 ps |
| T62 |
/workspace/coverage/cover_reg_top/8.rom_ctrl_tl_intg_err.462490867 |
|
|
Apr 02 12:35:32 PM PDT 24 |
Apr 02 12:38:11 PM PDT 24 |
1697140844 ps |
| T105 |
/workspace/coverage/cover_reg_top/6.rom_ctrl_same_csr_outstanding.1594195341 |
|
|
Apr 02 12:35:30 PM PDT 24 |
Apr 02 12:36:06 PM PDT 24 |
4143130752 ps |
| T670 |
/workspace/coverage/cover_reg_top/1.rom_ctrl_csr_mem_rw_with_rand_reset.728766230 |
|
|
Apr 02 12:35:14 PM PDT 24 |
Apr 02 12:35:26 PM PDT 24 |
2076171221 ps |
| T671 |
/workspace/coverage/cover_reg_top/1.rom_ctrl_mem_walk.837779125 |
|
|
Apr 02 12:35:08 PM PDT 24 |
Apr 02 12:35:34 PM PDT 24 |
55673117429 ps |
| T672 |
/workspace/coverage/cover_reg_top/4.rom_ctrl_mem_partial_access.3761724297 |
|
|
Apr 02 12:35:20 PM PDT 24 |
Apr 02 12:35:47 PM PDT 24 |
3469371656 ps |
| T63 |
/workspace/coverage/cover_reg_top/18.rom_ctrl_tl_intg_err.181866684 |
|
|
Apr 02 12:35:53 PM PDT 24 |
Apr 02 12:37:14 PM PDT 24 |
503927113 ps |
| T72 |
/workspace/coverage/cover_reg_top/1.rom_ctrl_csr_rw.995117264 |
|
|
Apr 02 12:35:12 PM PDT 24 |
Apr 02 12:35:46 PM PDT 24 |
4316446098 ps |
| T673 |
/workspace/coverage/cover_reg_top/11.rom_ctrl_tl_errors.3752210335 |
|
|
Apr 02 12:35:38 PM PDT 24 |
Apr 02 12:35:50 PM PDT 24 |
174307594 ps |
| T674 |
/workspace/coverage/cover_reg_top/9.rom_ctrl_csr_mem_rw_with_rand_reset.823027633 |
|
|
Apr 02 12:35:35 PM PDT 24 |
Apr 02 12:35:59 PM PDT 24 |
2813033700 ps |
| T106 |
/workspace/coverage/cover_reg_top/1.rom_ctrl_passthru_mem_tl_intg_err.1179488327 |
|
|
Apr 02 12:35:08 PM PDT 24 |
Apr 02 12:37:04 PM PDT 24 |
27436056499 ps |
| T64 |
/workspace/coverage/cover_reg_top/3.rom_ctrl_tl_intg_err.1270058968 |
|
|
Apr 02 12:35:17 PM PDT 24 |
Apr 02 12:36:43 PM PDT 24 |
12655073537 ps |
| T107 |
/workspace/coverage/cover_reg_top/7.rom_ctrl_same_csr_outstanding.1530586479 |
|
|
Apr 02 12:35:33 PM PDT 24 |
Apr 02 12:36:04 PM PDT 24 |
16087182973 ps |
| T675 |
/workspace/coverage/cover_reg_top/0.rom_ctrl_tl_errors.3313993225 |
|
|
Apr 02 12:35:05 PM PDT 24 |
Apr 02 12:35:44 PM PDT 24 |
4201122504 ps |
| T676 |
/workspace/coverage/cover_reg_top/4.rom_ctrl_csr_mem_rw_with_rand_reset.1051077083 |
|
|
Apr 02 12:35:26 PM PDT 24 |
Apr 02 12:35:52 PM PDT 24 |
5714182252 ps |
| T73 |
/workspace/coverage/cover_reg_top/5.rom_ctrl_same_csr_outstanding.2805493345 |
|
|
Apr 02 12:35:28 PM PDT 24 |
Apr 02 12:35:58 PM PDT 24 |
12765578444 ps |
| T122 |
/workspace/coverage/cover_reg_top/10.rom_ctrl_tl_intg_err.3323338656 |
|
|
Apr 02 12:35:43 PM PDT 24 |
Apr 02 12:37:01 PM PDT 24 |
510291221 ps |
| T74 |
/workspace/coverage/cover_reg_top/12.rom_ctrl_passthru_mem_tl_intg_err.2995989353 |
|
|
Apr 02 12:35:41 PM PDT 24 |
Apr 02 12:38:24 PM PDT 24 |
37920970524 ps |
| T677 |
/workspace/coverage/cover_reg_top/3.rom_ctrl_csr_bit_bash.2625887381 |
|
|
Apr 02 12:35:16 PM PDT 24 |
Apr 02 12:35:47 PM PDT 24 |
15986368939 ps |
| T678 |
/workspace/coverage/cover_reg_top/16.rom_ctrl_tl_errors.1508828981 |
|
|
Apr 02 12:35:48 PM PDT 24 |
Apr 02 12:36:10 PM PDT 24 |
1546560145 ps |
| T679 |
/workspace/coverage/cover_reg_top/5.rom_ctrl_csr_mem_rw_with_rand_reset.1059467701 |
|
|
Apr 02 12:35:29 PM PDT 24 |
Apr 02 12:35:57 PM PDT 24 |
18286579419 ps |
| T75 |
/workspace/coverage/cover_reg_top/9.rom_ctrl_same_csr_outstanding.4246321950 |
|
|
Apr 02 12:35:35 PM PDT 24 |
Apr 02 12:35:55 PM PDT 24 |
4762148355 ps |
| T108 |
/workspace/coverage/cover_reg_top/2.rom_ctrl_same_csr_outstanding.2583736516 |
|
|
Apr 02 12:35:16 PM PDT 24 |
Apr 02 12:35:25 PM PDT 24 |
174551422 ps |
| T124 |
/workspace/coverage/cover_reg_top/11.rom_ctrl_tl_intg_err.3343399787 |
|
|
Apr 02 12:35:48 PM PDT 24 |
Apr 02 12:37:14 PM PDT 24 |
777175098 ps |
| T680 |
/workspace/coverage/cover_reg_top/10.rom_ctrl_tl_errors.260119553 |
|
|
Apr 02 12:35:49 PM PDT 24 |
Apr 02 12:35:59 PM PDT 24 |
425111825 ps |
| T76 |
/workspace/coverage/cover_reg_top/11.rom_ctrl_passthru_mem_tl_intg_err.2253296475 |
|
|
Apr 02 12:35:49 PM PDT 24 |
Apr 02 12:36:43 PM PDT 24 |
2767454121 ps |
| T129 |
/workspace/coverage/cover_reg_top/5.rom_ctrl_tl_intg_err.3079156027 |
|
|
Apr 02 12:35:23 PM PDT 24 |
Apr 02 12:37:08 PM PDT 24 |
4317337111 ps |
| T681 |
/workspace/coverage/cover_reg_top/2.rom_ctrl_mem_partial_access.3198087218 |
|
|
Apr 02 12:35:15 PM PDT 24 |
Apr 02 12:35:23 PM PDT 24 |
331764310 ps |
| T682 |
/workspace/coverage/cover_reg_top/3.rom_ctrl_csr_mem_rw_with_rand_reset.2123272101 |
|
|
Apr 02 12:35:18 PM PDT 24 |
Apr 02 12:35:34 PM PDT 24 |
14322615233 ps |
| T683 |
/workspace/coverage/cover_reg_top/11.rom_ctrl_csr_mem_rw_with_rand_reset.3204739348 |
|
|
Apr 02 12:35:41 PM PDT 24 |
Apr 02 12:35:50 PM PDT 24 |
192885485 ps |
| T684 |
/workspace/coverage/cover_reg_top/1.rom_ctrl_mem_partial_access.2447588533 |
|
|
Apr 02 12:35:09 PM PDT 24 |
Apr 02 12:35:24 PM PDT 24 |
1111308838 ps |
| T109 |
/workspace/coverage/cover_reg_top/1.rom_ctrl_same_csr_outstanding.243588280 |
|
|
Apr 02 12:35:12 PM PDT 24 |
Apr 02 12:35:21 PM PDT 24 |
661550701 ps |
| T685 |
/workspace/coverage/cover_reg_top/3.rom_ctrl_mem_walk.556052525 |
|
|
Apr 02 12:35:16 PM PDT 24 |
Apr 02 12:35:44 PM PDT 24 |
6363271534 ps |
| T686 |
/workspace/coverage/cover_reg_top/3.rom_ctrl_mem_partial_access.2971406917 |
|
|
Apr 02 12:35:21 PM PDT 24 |
Apr 02 12:35:42 PM PDT 24 |
2244083659 ps |
| T121 |
/workspace/coverage/cover_reg_top/15.rom_ctrl_tl_intg_err.609064843 |
|
|
Apr 02 12:35:51 PM PDT 24 |
Apr 02 12:38:37 PM PDT 24 |
2711157961 ps |
| T687 |
/workspace/coverage/cover_reg_top/17.rom_ctrl_csr_mem_rw_with_rand_reset.204361611 |
|
|
Apr 02 12:35:53 PM PDT 24 |
Apr 02 12:36:01 PM PDT 24 |
342811392 ps |
| T688 |
/workspace/coverage/cover_reg_top/3.rom_ctrl_tl_errors.628912729 |
|
|
Apr 02 12:35:21 PM PDT 24 |
Apr 02 12:35:37 PM PDT 24 |
993029302 ps |
| T689 |
/workspace/coverage/cover_reg_top/8.rom_ctrl_tl_errors.4050922849 |
|
|
Apr 02 12:35:34 PM PDT 24 |
Apr 02 12:35:47 PM PDT 24 |
1030966819 ps |
| T690 |
/workspace/coverage/cover_reg_top/14.rom_ctrl_passthru_mem_tl_intg_err.3997045474 |
|
|
Apr 02 12:35:44 PM PDT 24 |
Apr 02 12:37:49 PM PDT 24 |
15708301018 ps |
| T77 |
/workspace/coverage/cover_reg_top/7.rom_ctrl_passthru_mem_tl_intg_err.422910773 |
|
|
Apr 02 12:35:29 PM PDT 24 |
Apr 02 12:37:32 PM PDT 24 |
11872390826 ps |
| T691 |
/workspace/coverage/cover_reg_top/0.rom_ctrl_csr_bit_bash.3003715894 |
|
|
Apr 02 12:35:09 PM PDT 24 |
Apr 02 12:35:40 PM PDT 24 |
4073121100 ps |
| T126 |
/workspace/coverage/cover_reg_top/19.rom_ctrl_tl_intg_err.3808100433 |
|
|
Apr 02 12:35:57 PM PDT 24 |
Apr 02 12:38:30 PM PDT 24 |
340987469 ps |
| T692 |
/workspace/coverage/cover_reg_top/2.rom_ctrl_csr_rw.4104051043 |
|
|
Apr 02 12:35:12 PM PDT 24 |
Apr 02 12:35:40 PM PDT 24 |
6543773710 ps |
| T78 |
/workspace/coverage/cover_reg_top/14.rom_ctrl_same_csr_outstanding.3791088124 |
|
|
Apr 02 12:35:51 PM PDT 24 |
Apr 02 12:36:02 PM PDT 24 |
178022687 ps |
| T693 |
/workspace/coverage/cover_reg_top/15.rom_ctrl_csr_mem_rw_with_rand_reset.2388271657 |
|
|
Apr 02 12:35:51 PM PDT 24 |
Apr 02 12:36:17 PM PDT 24 |
3182787092 ps |
| T79 |
/workspace/coverage/cover_reg_top/10.rom_ctrl_csr_rw.3387605282 |
|
|
Apr 02 12:35:40 PM PDT 24 |
Apr 02 12:36:06 PM PDT 24 |
3152084466 ps |
| T694 |
/workspace/coverage/cover_reg_top/7.rom_ctrl_csr_rw.1840423591 |
|
|
Apr 02 12:35:28 PM PDT 24 |
Apr 02 12:35:50 PM PDT 24 |
2194966806 ps |
| T695 |
/workspace/coverage/cover_reg_top/2.rom_ctrl_mem_walk.1780410603 |
|
|
Apr 02 12:35:12 PM PDT 24 |
Apr 02 12:35:37 PM PDT 24 |
11672399386 ps |
| T696 |
/workspace/coverage/cover_reg_top/0.rom_ctrl_csr_rw.2620544216 |
|
|
Apr 02 12:35:08 PM PDT 24 |
Apr 02 12:35:17 PM PDT 24 |
176050919 ps |
| T697 |
/workspace/coverage/cover_reg_top/0.rom_ctrl_csr_mem_rw_with_rand_reset.3362403343 |
|
|
Apr 02 12:35:08 PM PDT 24 |
Apr 02 12:35:41 PM PDT 24 |
16447859557 ps |
| T125 |
/workspace/coverage/cover_reg_top/13.rom_ctrl_tl_intg_err.1819355568 |
|
|
Apr 02 12:35:44 PM PDT 24 |
Apr 02 12:38:36 PM PDT 24 |
32014895504 ps |
| T123 |
/workspace/coverage/cover_reg_top/7.rom_ctrl_tl_intg_err.4000355291 |
|
|
Apr 02 12:35:28 PM PDT 24 |
Apr 02 12:37:10 PM PDT 24 |
4263446285 ps |
| T84 |
/workspace/coverage/cover_reg_top/2.rom_ctrl_passthru_mem_tl_intg_err.445774206 |
|
|
Apr 02 12:35:13 PM PDT 24 |
Apr 02 12:37:15 PM PDT 24 |
31501906359 ps |
| T698 |
/workspace/coverage/cover_reg_top/19.rom_ctrl_passthru_mem_tl_intg_err.92259641 |
|
|
Apr 02 12:35:56 PM PDT 24 |
Apr 02 12:37:58 PM PDT 24 |
22163952418 ps |
| T699 |
/workspace/coverage/cover_reg_top/1.rom_ctrl_csr_bit_bash.1237736318 |
|
|
Apr 02 12:35:12 PM PDT 24 |
Apr 02 12:35:29 PM PDT 24 |
6635764903 ps |
| T128 |
/workspace/coverage/cover_reg_top/2.rom_ctrl_tl_intg_err.440527330 |
|
|
Apr 02 12:35:16 PM PDT 24 |
Apr 02 12:38:14 PM PDT 24 |
4255285995 ps |
| T85 |
/workspace/coverage/cover_reg_top/15.rom_ctrl_passthru_mem_tl_intg_err.4020160328 |
|
|
Apr 02 12:35:48 PM PDT 24 |
Apr 02 12:37:25 PM PDT 24 |
26816555293 ps |
| T86 |
/workspace/coverage/cover_reg_top/9.rom_ctrl_passthru_mem_tl_intg_err.3267431007 |
|
|
Apr 02 12:35:41 PM PDT 24 |
Apr 02 12:36:41 PM PDT 24 |
3644451422 ps |
| T700 |
/workspace/coverage/cover_reg_top/3.rom_ctrl_csr_aliasing.3190833210 |
|
|
Apr 02 12:35:18 PM PDT 24 |
Apr 02 12:35:50 PM PDT 24 |
10061074459 ps |
| T701 |
/workspace/coverage/cover_reg_top/12.rom_ctrl_csr_rw.540601874 |
|
|
Apr 02 12:35:44 PM PDT 24 |
Apr 02 12:36:09 PM PDT 24 |
2535383955 ps |
| T702 |
/workspace/coverage/cover_reg_top/9.rom_ctrl_tl_errors.2022011580 |
|
|
Apr 02 12:35:38 PM PDT 24 |
Apr 02 12:36:10 PM PDT 24 |
12049487216 ps |
| T703 |
/workspace/coverage/cover_reg_top/8.rom_ctrl_passthru_mem_tl_intg_err.3752681170 |
|
|
Apr 02 12:35:34 PM PDT 24 |
Apr 02 12:37:44 PM PDT 24 |
31521294205 ps |
| T704 |
/workspace/coverage/cover_reg_top/3.rom_ctrl_csr_rw.3591078256 |
|
|
Apr 02 12:35:18 PM PDT 24 |
Apr 02 12:35:42 PM PDT 24 |
9070174157 ps |
| T705 |
/workspace/coverage/cover_reg_top/2.rom_ctrl_tl_errors.1744968305 |
|
|
Apr 02 12:35:14 PM PDT 24 |
Apr 02 12:35:51 PM PDT 24 |
16937090959 ps |
| T706 |
/workspace/coverage/cover_reg_top/13.rom_ctrl_csr_rw.1002891541 |
|
|
Apr 02 12:35:43 PM PDT 24 |
Apr 02 12:36:15 PM PDT 24 |
4111911671 ps |
| T707 |
/workspace/coverage/cover_reg_top/1.rom_ctrl_tl_errors.1374071034 |
|
|
Apr 02 12:35:11 PM PDT 24 |
Apr 02 12:35:37 PM PDT 24 |
1943284960 ps |
| T127 |
/workspace/coverage/cover_reg_top/1.rom_ctrl_tl_intg_err.627910811 |
|
|
Apr 02 12:35:13 PM PDT 24 |
Apr 02 12:36:41 PM PDT 24 |
29096511559 ps |
| T708 |
/workspace/coverage/cover_reg_top/6.rom_ctrl_csr_rw.898135120 |
|
|
Apr 02 12:35:29 PM PDT 24 |
Apr 02 12:35:48 PM PDT 24 |
6833209361 ps |
| T709 |
/workspace/coverage/cover_reg_top/5.rom_ctrl_tl_errors.2181476230 |
|
|
Apr 02 12:35:24 PM PDT 24 |
Apr 02 12:36:00 PM PDT 24 |
9075410175 ps |
| T710 |
/workspace/coverage/cover_reg_top/14.rom_ctrl_csr_mem_rw_with_rand_reset.121135225 |
|
|
Apr 02 12:35:48 PM PDT 24 |
Apr 02 12:36:04 PM PDT 24 |
1244486750 ps |
| T131 |
/workspace/coverage/cover_reg_top/6.rom_ctrl_tl_intg_err.2776793908 |
|
|
Apr 02 12:35:31 PM PDT 24 |
Apr 02 12:36:52 PM PDT 24 |
976758090 ps |
| T711 |
/workspace/coverage/cover_reg_top/4.rom_ctrl_csr_bit_bash.1327598139 |
|
|
Apr 02 12:35:20 PM PDT 24 |
Apr 02 12:35:29 PM PDT 24 |
687957357 ps |
| T712 |
/workspace/coverage/cover_reg_top/18.rom_ctrl_passthru_mem_tl_intg_err.1574263043 |
|
|
Apr 02 12:35:52 PM PDT 24 |
Apr 02 12:36:30 PM PDT 24 |
693963472 ps |
| T130 |
/workspace/coverage/cover_reg_top/14.rom_ctrl_tl_intg_err.70471271 |
|
|
Apr 02 12:35:48 PM PDT 24 |
Apr 02 12:38:32 PM PDT 24 |
925913361 ps |
| T87 |
/workspace/coverage/cover_reg_top/0.rom_ctrl_csr_hw_reset.3158456862 |
|
|
Apr 02 12:35:08 PM PDT 24 |
Apr 02 12:35:38 PM PDT 24 |
9396910593 ps |
| T713 |
/workspace/coverage/cover_reg_top/3.rom_ctrl_csr_hw_reset.1279094260 |
|
|
Apr 02 12:35:17 PM PDT 24 |
Apr 02 12:35:54 PM PDT 24 |
3495924098 ps |
| T714 |
/workspace/coverage/cover_reg_top/3.rom_ctrl_passthru_mem_tl_intg_err.4220680194 |
|
|
Apr 02 12:35:16 PM PDT 24 |
Apr 02 12:36:32 PM PDT 24 |
6244808852 ps |
| T715 |
/workspace/coverage/cover_reg_top/15.rom_ctrl_csr_rw.274463233 |
|
|
Apr 02 12:35:51 PM PDT 24 |
Apr 02 12:35:59 PM PDT 24 |
787503245 ps |
| T716 |
/workspace/coverage/cover_reg_top/0.rom_ctrl_csr_aliasing.1137617456 |
|
|
Apr 02 12:35:07 PM PDT 24 |
Apr 02 12:35:28 PM PDT 24 |
8182447713 ps |
| T717 |
/workspace/coverage/cover_reg_top/4.rom_ctrl_tl_intg_err.2401377023 |
|
|
Apr 02 12:35:21 PM PDT 24 |
Apr 02 12:37:57 PM PDT 24 |
393587897 ps |
| T718 |
/workspace/coverage/cover_reg_top/17.rom_ctrl_tl_errors.21323842 |
|
|
Apr 02 12:35:50 PM PDT 24 |
Apr 02 12:36:06 PM PDT 24 |
1782655760 ps |
| T719 |
/workspace/coverage/cover_reg_top/18.rom_ctrl_csr_rw.336431540 |
|
|
Apr 02 12:35:54 PM PDT 24 |
Apr 02 12:36:12 PM PDT 24 |
6551877488 ps |
| T720 |
/workspace/coverage/cover_reg_top/0.rom_ctrl_passthru_mem_tl_intg_err.3247075771 |
|
|
Apr 02 12:35:05 PM PDT 24 |
Apr 02 12:37:58 PM PDT 24 |
19308317582 ps |
| T721 |
/workspace/coverage/cover_reg_top/4.rom_ctrl_tl_errors.1723217117 |
|
|
Apr 02 12:35:16 PM PDT 24 |
Apr 02 12:35:35 PM PDT 24 |
1026862839 ps |
| T722 |
/workspace/coverage/cover_reg_top/0.rom_ctrl_same_csr_outstanding.575217486 |
|
|
Apr 02 12:35:11 PM PDT 24 |
Apr 02 12:35:24 PM PDT 24 |
673826906 ps |
| T723 |
/workspace/coverage/cover_reg_top/17.rom_ctrl_passthru_mem_tl_intg_err.2709226785 |
|
|
Apr 02 12:35:52 PM PDT 24 |
Apr 02 12:37:11 PM PDT 24 |
7793752545 ps |
| T724 |
/workspace/coverage/cover_reg_top/4.rom_ctrl_csr_hw_reset.2697916765 |
|
|
Apr 02 12:35:21 PM PDT 24 |
Apr 02 12:35:33 PM PDT 24 |
599884702 ps |
| T88 |
/workspace/coverage/cover_reg_top/4.rom_ctrl_passthru_mem_tl_intg_err.3683837990 |
|
|
Apr 02 12:35:18 PM PDT 24 |
Apr 02 12:35:57 PM PDT 24 |
2735231786 ps |
| T133 |
/workspace/coverage/cover_reg_top/0.rom_ctrl_tl_intg_err.267138359 |
|
|
Apr 02 12:35:10 PM PDT 24 |
Apr 02 12:38:04 PM PDT 24 |
15187460819 ps |
| T725 |
/workspace/coverage/cover_reg_top/7.rom_ctrl_tl_errors.1526981183 |
|
|
Apr 02 12:35:28 PM PDT 24 |
Apr 02 12:35:52 PM PDT 24 |
4498016862 ps |
| T726 |
/workspace/coverage/cover_reg_top/6.rom_ctrl_tl_errors.1675283413 |
|
|
Apr 02 12:35:29 PM PDT 24 |
Apr 02 12:35:50 PM PDT 24 |
4233952847 ps |
| T727 |
/workspace/coverage/cover_reg_top/16.rom_ctrl_csr_mem_rw_with_rand_reset.1492694254 |
|
|
Apr 02 12:35:47 PM PDT 24 |
Apr 02 12:36:08 PM PDT 24 |
5405407254 ps |
| T89 |
/workspace/coverage/cover_reg_top/2.rom_ctrl_csr_hw_reset.1164055313 |
|
|
Apr 02 12:35:12 PM PDT 24 |
Apr 02 12:35:52 PM PDT 24 |
8902270298 ps |
| T728 |
/workspace/coverage/cover_reg_top/18.rom_ctrl_tl_errors.1086770875 |
|
|
Apr 02 12:35:54 PM PDT 24 |
Apr 02 12:36:07 PM PDT 24 |
605760074 ps |
| T729 |
/workspace/coverage/cover_reg_top/19.rom_ctrl_tl_errors.2763316253 |
|
|
Apr 02 12:35:58 PM PDT 24 |
Apr 02 12:36:14 PM PDT 24 |
3919598283 ps |
| T91 |
/workspace/coverage/cover_reg_top/9.rom_ctrl_csr_rw.971017122 |
|
|
Apr 02 12:35:36 PM PDT 24 |
Apr 02 12:35:45 PM PDT 24 |
517369696 ps |
| T92 |
/workspace/coverage/cover_reg_top/2.rom_ctrl_csr_bit_bash.168263924 |
|
|
Apr 02 12:35:14 PM PDT 24 |
Apr 02 12:35:32 PM PDT 24 |
5884043140 ps |
| T730 |
/workspace/coverage/cover_reg_top/0.rom_ctrl_mem_partial_access.2435432343 |
|
|
Apr 02 12:35:08 PM PDT 24 |
Apr 02 12:35:27 PM PDT 24 |
7188837821 ps |
| T90 |
/workspace/coverage/cover_reg_top/17.rom_ctrl_csr_rw.4241373660 |
|
|
Apr 02 12:35:52 PM PDT 24 |
Apr 02 12:36:07 PM PDT 24 |
2469566891 ps |
| T731 |
/workspace/coverage/cover_reg_top/8.rom_ctrl_same_csr_outstanding.3961158714 |
|
|
Apr 02 12:35:31 PM PDT 24 |
Apr 02 12:35:52 PM PDT 24 |
1241668106 ps |
| T732 |
/workspace/coverage/cover_reg_top/3.rom_ctrl_same_csr_outstanding.3962811298 |
|
|
Apr 02 12:35:19 PM PDT 24 |
Apr 02 12:35:42 PM PDT 24 |
5258676475 ps |
| T733 |
/workspace/coverage/cover_reg_top/11.rom_ctrl_same_csr_outstanding.382943568 |
|
|
Apr 02 12:35:41 PM PDT 24 |
Apr 02 12:36:13 PM PDT 24 |
3934767280 ps |
| T734 |
/workspace/coverage/cover_reg_top/10.rom_ctrl_csr_mem_rw_with_rand_reset.4223530828 |
|
|
Apr 02 12:35:39 PM PDT 24 |
Apr 02 12:36:10 PM PDT 24 |
7842696505 ps |
| T735 |
/workspace/coverage/cover_reg_top/19.rom_ctrl_csr_mem_rw_with_rand_reset.1839761677 |
|
|
Apr 02 12:35:57 PM PDT 24 |
Apr 02 12:36:05 PM PDT 24 |
363673301 ps |
| T736 |
/workspace/coverage/cover_reg_top/12.rom_ctrl_same_csr_outstanding.2843060338 |
|
|
Apr 02 12:35:43 PM PDT 24 |
Apr 02 12:36:04 PM PDT 24 |
35596253252 ps |
| T737 |
/workspace/coverage/cover_reg_top/19.rom_ctrl_csr_rw.4293010 |
|
|
Apr 02 12:35:56 PM PDT 24 |
Apr 02 12:36:16 PM PDT 24 |
1970759101 ps |
| T738 |
/workspace/coverage/cover_reg_top/12.rom_ctrl_csr_mem_rw_with_rand_reset.421259498 |
|
|
Apr 02 12:35:45 PM PDT 24 |
Apr 02 12:36:13 PM PDT 24 |
5724947525 ps |
| T739 |
/workspace/coverage/cover_reg_top/10.rom_ctrl_same_csr_outstanding.2790931043 |
|
|
Apr 02 12:35:49 PM PDT 24 |
Apr 02 12:36:16 PM PDT 24 |
3158420853 ps |
| T132 |
/workspace/coverage/cover_reg_top/17.rom_ctrl_tl_intg_err.1145058347 |
|
|
Apr 02 12:35:49 PM PDT 24 |
Apr 02 12:38:32 PM PDT 24 |
3323502136 ps |
| T740 |
/workspace/coverage/cover_reg_top/2.rom_ctrl_csr_mem_rw_with_rand_reset.2050809717 |
|
|
Apr 02 12:35:17 PM PDT 24 |
Apr 02 12:35:48 PM PDT 24 |
14671257462 ps |
| T741 |
/workspace/coverage/cover_reg_top/12.rom_ctrl_tl_errors.2844876148 |
|
|
Apr 02 12:35:44 PM PDT 24 |
Apr 02 12:36:05 PM PDT 24 |
1286931513 ps |
| T742 |
/workspace/coverage/cover_reg_top/7.rom_ctrl_csr_mem_rw_with_rand_reset.1326053575 |
|
|
Apr 02 12:35:31 PM PDT 24 |
Apr 02 12:35:50 PM PDT 24 |
2127421093 ps |
| T743 |
/workspace/coverage/cover_reg_top/9.rom_ctrl_tl_intg_err.448216138 |
|
|
Apr 02 12:35:36 PM PDT 24 |
Apr 02 12:36:56 PM PDT 24 |
254363507 ps |
| T744 |
/workspace/coverage/cover_reg_top/13.rom_ctrl_same_csr_outstanding.3611443576 |
|
|
Apr 02 12:35:44 PM PDT 24 |
Apr 02 12:36:01 PM PDT 24 |
4896731770 ps |
| T93 |
/workspace/coverage/cover_reg_top/4.rom_ctrl_csr_rw.4135749301 |
|
|
Apr 02 12:35:19 PM PDT 24 |
Apr 02 12:35:42 PM PDT 24 |
2574091643 ps |
| T745 |
/workspace/coverage/cover_reg_top/18.rom_ctrl_same_csr_outstanding.1348096794 |
|
|
Apr 02 12:35:53 PM PDT 24 |
Apr 02 12:36:04 PM PDT 24 |
720379713 ps |
| T746 |
/workspace/coverage/cover_reg_top/17.rom_ctrl_same_csr_outstanding.594758641 |
|
|
Apr 02 12:35:54 PM PDT 24 |
Apr 02 12:36:21 PM PDT 24 |
2466876754 ps |
| T747 |
/workspace/coverage/cover_reg_top/1.rom_ctrl_csr_hw_reset.2334004100 |
|
|
Apr 02 12:35:12 PM PDT 24 |
Apr 02 12:35:43 PM PDT 24 |
9463416892 ps |
| T748 |
/workspace/coverage/cover_reg_top/8.rom_ctrl_csr_rw.4047900076 |
|
|
Apr 02 12:35:34 PM PDT 24 |
Apr 02 12:36:01 PM PDT 24 |
3404606866 ps |
| T749 |
/workspace/coverage/cover_reg_top/15.rom_ctrl_same_csr_outstanding.3570148676 |
|
|
Apr 02 12:35:48 PM PDT 24 |
Apr 02 12:36:04 PM PDT 24 |
5131129277 ps |
| T750 |
/workspace/coverage/cover_reg_top/8.rom_ctrl_csr_mem_rw_with_rand_reset.520851917 |
|
|
Apr 02 12:35:38 PM PDT 24 |
Apr 02 12:36:10 PM PDT 24 |
4164011080 ps |
| T751 |
/workspace/coverage/cover_reg_top/16.rom_ctrl_same_csr_outstanding.3114778063 |
|
|
Apr 02 12:35:50 PM PDT 24 |
Apr 02 12:36:10 PM PDT 24 |
1243778420 ps |