| T308 |
/workspace/coverage/default/21.rom_ctrl_max_throughput_chk.2609460680 |
|
|
Apr 15 12:34:23 PM PDT 24 |
Apr 15 12:34:41 PM PDT 24 |
1896056076 ps |
| T309 |
/workspace/coverage/default/36.rom_ctrl_kmac_err_chk.1563591580 |
|
|
Apr 15 12:34:46 PM PDT 24 |
Apr 15 12:35:51 PM PDT 24 |
10828277669 ps |
| T310 |
/workspace/coverage/default/19.rom_ctrl_max_throughput_chk.1528649721 |
|
|
Apr 15 12:34:37 PM PDT 24 |
Apr 15 12:34:48 PM PDT 24 |
662378857 ps |
| T311 |
/workspace/coverage/default/16.rom_ctrl_smoke.3313746970 |
|
|
Apr 15 12:34:07 PM PDT 24 |
Apr 15 12:34:40 PM PDT 24 |
2117207939 ps |
| T312 |
/workspace/coverage/default/47.rom_ctrl_kmac_err_chk.2022742302 |
|
|
Apr 15 12:34:52 PM PDT 24 |
Apr 15 12:35:40 PM PDT 24 |
18428351473 ps |
| T313 |
/workspace/coverage/default/21.rom_ctrl_alert_test.3136350581 |
|
|
Apr 15 12:34:42 PM PDT 24 |
Apr 15 12:35:10 PM PDT 24 |
13255552378 ps |
| T314 |
/workspace/coverage/default/21.rom_ctrl_corrupt_sig_fatal_chk.3206174934 |
|
|
Apr 15 12:34:20 PM PDT 24 |
Apr 15 12:40:56 PM PDT 24 |
59475842970 ps |
| T315 |
/workspace/coverage/default/43.rom_ctrl_corrupt_sig_fatal_chk.540978800 |
|
|
Apr 15 12:34:57 PM PDT 24 |
Apr 15 12:48:32 PM PDT 24 |
81939240196 ps |
| T316 |
/workspace/coverage/default/14.rom_ctrl_max_throughput_chk.3272438539 |
|
|
Apr 15 12:34:41 PM PDT 24 |
Apr 15 12:35:08 PM PDT 24 |
9533537987 ps |
| T317 |
/workspace/coverage/default/41.rom_ctrl_max_throughput_chk.2721403144 |
|
|
Apr 15 12:34:47 PM PDT 24 |
Apr 15 12:35:04 PM PDT 24 |
848211276 ps |
| T318 |
/workspace/coverage/default/40.rom_ctrl_kmac_err_chk.258405884 |
|
|
Apr 15 12:34:55 PM PDT 24 |
Apr 15 12:36:02 PM PDT 24 |
16078811890 ps |
| T319 |
/workspace/coverage/default/20.rom_ctrl_stress_all.2806471523 |
|
|
Apr 15 12:34:20 PM PDT 24 |
Apr 15 12:35:07 PM PDT 24 |
4077844932 ps |
| T320 |
/workspace/coverage/default/2.rom_ctrl_stress_all.4272827218 |
|
|
Apr 15 12:34:08 PM PDT 24 |
Apr 15 12:34:45 PM PDT 24 |
4162011006 ps |
| T321 |
/workspace/coverage/default/42.rom_ctrl_max_throughput_chk.281220283 |
|
|
Apr 15 12:34:59 PM PDT 24 |
Apr 15 12:35:11 PM PDT 24 |
366003303 ps |
| T322 |
/workspace/coverage/default/46.rom_ctrl_stress_all.770086639 |
|
|
Apr 15 12:34:47 PM PDT 24 |
Apr 15 12:35:41 PM PDT 24 |
8306705261 ps |
| T323 |
/workspace/coverage/default/18.rom_ctrl_kmac_err_chk.2260842739 |
|
|
Apr 15 12:34:15 PM PDT 24 |
Apr 15 12:34:50 PM PDT 24 |
2338778420 ps |
| T324 |
/workspace/coverage/default/19.rom_ctrl_kmac_err_chk.1375987982 |
|
|
Apr 15 12:34:19 PM PDT 24 |
Apr 15 12:34:42 PM PDT 24 |
524288804 ps |
| T325 |
/workspace/coverage/default/39.rom_ctrl_corrupt_sig_fatal_chk.1908192492 |
|
|
Apr 15 12:34:59 PM PDT 24 |
Apr 15 12:48:38 PM PDT 24 |
154775986866 ps |
| T326 |
/workspace/coverage/default/20.rom_ctrl_kmac_err_chk.690618774 |
|
|
Apr 15 12:34:22 PM PDT 24 |
Apr 15 12:34:42 PM PDT 24 |
1648040543 ps |
| T327 |
/workspace/coverage/default/18.rom_ctrl_alert_test.1063588535 |
|
|
Apr 15 12:34:15 PM PDT 24 |
Apr 15 12:34:34 PM PDT 24 |
2995615634 ps |
| T328 |
/workspace/coverage/default/2.rom_ctrl_kmac_err_chk.4124912461 |
|
|
Apr 15 12:34:08 PM PDT 24 |
Apr 15 12:34:29 PM PDT 24 |
3297375907 ps |
| T329 |
/workspace/coverage/default/18.rom_ctrl_smoke.4140555143 |
|
|
Apr 15 12:34:31 PM PDT 24 |
Apr 15 12:35:31 PM PDT 24 |
7491252139 ps |
| T330 |
/workspace/coverage/default/49.rom_ctrl_corrupt_sig_fatal_chk.1790758838 |
|
|
Apr 15 12:34:59 PM PDT 24 |
Apr 15 12:39:18 PM PDT 24 |
6966136453 ps |
| T331 |
/workspace/coverage/default/22.rom_ctrl_stress_all.3031027076 |
|
|
Apr 15 12:34:21 PM PDT 24 |
Apr 15 12:36:36 PM PDT 24 |
72369742815 ps |
| T332 |
/workspace/coverage/default/36.rom_ctrl_corrupt_sig_fatal_chk.2864633201 |
|
|
Apr 15 12:34:48 PM PDT 24 |
Apr 15 12:39:21 PM PDT 24 |
41468202129 ps |
| T333 |
/workspace/coverage/default/34.rom_ctrl_kmac_err_chk.103906174 |
|
|
Apr 15 12:34:55 PM PDT 24 |
Apr 15 12:35:15 PM PDT 24 |
332568982 ps |
| T334 |
/workspace/coverage/default/33.rom_ctrl_alert_test.143303978 |
|
|
Apr 15 12:35:00 PM PDT 24 |
Apr 15 12:35:30 PM PDT 24 |
12558167422 ps |
| T335 |
/workspace/coverage/default/11.rom_ctrl_alert_test.2031482736 |
|
|
Apr 15 12:34:10 PM PDT 24 |
Apr 15 12:34:29 PM PDT 24 |
1267990888 ps |
| T47 |
/workspace/coverage/default/20.rom_ctrl_stress_all_with_rand_reset.2186805002 |
|
|
Apr 15 12:34:22 PM PDT 24 |
Apr 15 01:55:49 PM PDT 24 |
21207418839 ps |
| T336 |
/workspace/coverage/default/31.rom_ctrl_smoke.4027576897 |
|
|
Apr 15 12:34:55 PM PDT 24 |
Apr 15 12:35:22 PM PDT 24 |
671379621 ps |
| T337 |
/workspace/coverage/default/0.rom_ctrl_alert_test.1266469773 |
|
|
Apr 15 12:34:07 PM PDT 24 |
Apr 15 12:34:42 PM PDT 24 |
15689551681 ps |
| T338 |
/workspace/coverage/default/43.rom_ctrl_kmac_err_chk.2257455724 |
|
|
Apr 15 12:34:52 PM PDT 24 |
Apr 15 12:35:22 PM PDT 24 |
1537526395 ps |
| T339 |
/workspace/coverage/default/1.rom_ctrl_corrupt_sig_fatal_chk.3516697876 |
|
|
Apr 15 12:34:40 PM PDT 24 |
Apr 15 12:43:39 PM PDT 24 |
219136364157 ps |
| T340 |
/workspace/coverage/default/16.rom_ctrl_corrupt_sig_fatal_chk.188843955 |
|
|
Apr 15 12:34:16 PM PDT 24 |
Apr 15 12:44:46 PM PDT 24 |
905422590778 ps |
| T341 |
/workspace/coverage/default/34.rom_ctrl_smoke.878334143 |
|
|
Apr 15 12:34:49 PM PDT 24 |
Apr 15 12:35:08 PM PDT 24 |
362172049 ps |
| T342 |
/workspace/coverage/default/8.rom_ctrl_alert_test.2938949738 |
|
|
Apr 15 12:34:09 PM PDT 24 |
Apr 15 12:34:37 PM PDT 24 |
7152869593 ps |
| T343 |
/workspace/coverage/default/31.rom_ctrl_max_throughput_chk.1577886702 |
|
|
Apr 15 12:34:55 PM PDT 24 |
Apr 15 12:35:15 PM PDT 24 |
11395671419 ps |
| T344 |
/workspace/coverage/default/23.rom_ctrl_stress_all.4214781763 |
|
|
Apr 15 12:34:37 PM PDT 24 |
Apr 15 12:34:58 PM PDT 24 |
683936917 ps |
| T345 |
/workspace/coverage/default/19.rom_ctrl_corrupt_sig_fatal_chk.660560845 |
|
|
Apr 15 12:34:28 PM PDT 24 |
Apr 15 12:41:22 PM PDT 24 |
34833705886 ps |
| T346 |
/workspace/coverage/default/1.rom_ctrl_smoke.1262411070 |
|
|
Apr 15 12:34:08 PM PDT 24 |
Apr 15 12:34:37 PM PDT 24 |
1786872167 ps |
| T347 |
/workspace/coverage/default/27.rom_ctrl_smoke.426381711 |
|
|
Apr 15 12:34:53 PM PDT 24 |
Apr 15 12:35:29 PM PDT 24 |
2204630505 ps |
| T348 |
/workspace/coverage/default/9.rom_ctrl_smoke.3795976717 |
|
|
Apr 15 12:34:04 PM PDT 24 |
Apr 15 12:34:54 PM PDT 24 |
25087353222 ps |
| T349 |
/workspace/coverage/default/25.rom_ctrl_corrupt_sig_fatal_chk.3421762164 |
|
|
Apr 15 12:34:33 PM PDT 24 |
Apr 15 12:40:31 PM PDT 24 |
23551466945 ps |
| T48 |
/workspace/coverage/default/14.rom_ctrl_stress_all_with_rand_reset.3064425055 |
|
|
Apr 15 12:34:09 PM PDT 24 |
Apr 15 02:55:48 PM PDT 24 |
23902244846 ps |
| T350 |
/workspace/coverage/default/36.rom_ctrl_alert_test.3382700451 |
|
|
Apr 15 12:34:48 PM PDT 24 |
Apr 15 12:35:20 PM PDT 24 |
4061066704 ps |
| T49 |
/workspace/coverage/default/1.rom_ctrl_stress_all_with_rand_reset.2840754334 |
|
|
Apr 15 12:34:02 PM PDT 24 |
Apr 15 12:47:53 PM PDT 24 |
51800262548 ps |
| T351 |
/workspace/coverage/default/30.rom_ctrl_alert_test.3361180050 |
|
|
Apr 15 12:34:39 PM PDT 24 |
Apr 15 12:34:54 PM PDT 24 |
4364261755 ps |
| T352 |
/workspace/coverage/default/40.rom_ctrl_alert_test.1380453047 |
|
|
Apr 15 12:34:45 PM PDT 24 |
Apr 15 12:34:59 PM PDT 24 |
665085028 ps |
| T353 |
/workspace/coverage/default/13.rom_ctrl_max_throughput_chk.1577614439 |
|
|
Apr 15 12:34:08 PM PDT 24 |
Apr 15 12:34:28 PM PDT 24 |
2513441575 ps |
| T354 |
/workspace/coverage/default/30.rom_ctrl_smoke.2066435083 |
|
|
Apr 15 12:34:55 PM PDT 24 |
Apr 15 12:35:42 PM PDT 24 |
7587720996 ps |
| T355 |
/workspace/coverage/default/42.rom_ctrl_corrupt_sig_fatal_chk.1332625325 |
|
|
Apr 15 12:34:58 PM PDT 24 |
Apr 15 12:41:24 PM PDT 24 |
34887679101 ps |
| T356 |
/workspace/coverage/default/22.rom_ctrl_smoke.4148684320 |
|
|
Apr 15 12:34:45 PM PDT 24 |
Apr 15 12:35:46 PM PDT 24 |
23012928560 ps |
| T357 |
/workspace/coverage/default/28.rom_ctrl_stress_all.2349749579 |
|
|
Apr 15 12:34:45 PM PDT 24 |
Apr 15 12:35:37 PM PDT 24 |
9845058628 ps |
| T358 |
/workspace/coverage/default/37.rom_ctrl_max_throughput_chk.1603269463 |
|
|
Apr 15 12:34:56 PM PDT 24 |
Apr 15 12:35:09 PM PDT 24 |
429802813 ps |
| T359 |
/workspace/coverage/default/15.rom_ctrl_max_throughput_chk.1448119286 |
|
|
Apr 15 12:34:10 PM PDT 24 |
Apr 15 12:34:24 PM PDT 24 |
184163051 ps |
| T360 |
/workspace/coverage/default/44.rom_ctrl_max_throughput_chk.1098839531 |
|
|
Apr 15 12:35:05 PM PDT 24 |
Apr 15 12:35:25 PM PDT 24 |
6841343919 ps |
| T50 |
/workspace/coverage/default/30.rom_ctrl_stress_all_with_rand_reset.2767876203 |
|
|
Apr 15 12:34:53 PM PDT 24 |
Apr 15 12:39:05 PM PDT 24 |
11316727008 ps |
| T33 |
/workspace/coverage/default/4.rom_ctrl_sec_cm.3409395593 |
|
|
Apr 15 12:34:12 PM PDT 24 |
Apr 15 12:38:10 PM PDT 24 |
3870955699 ps |
| T361 |
/workspace/coverage/default/37.rom_ctrl_stress_all.781426105 |
|
|
Apr 15 12:34:59 PM PDT 24 |
Apr 15 12:35:36 PM PDT 24 |
7332695074 ps |
| T362 |
/workspace/coverage/default/3.rom_ctrl_kmac_err_chk.1247669285 |
|
|
Apr 15 12:34:07 PM PDT 24 |
Apr 15 12:34:29 PM PDT 24 |
332129851 ps |
| T363 |
/workspace/coverage/default/31.rom_ctrl_kmac_err_chk.2847196347 |
|
|
Apr 15 12:34:55 PM PDT 24 |
Apr 15 12:35:29 PM PDT 24 |
3467848647 ps |
| T364 |
/workspace/coverage/default/32.rom_ctrl_kmac_err_chk.3053838773 |
|
|
Apr 15 12:34:48 PM PDT 24 |
Apr 15 12:35:38 PM PDT 24 |
15993482561 ps |
| T365 |
/workspace/coverage/default/45.rom_ctrl_alert_test.2261915646 |
|
|
Apr 15 12:34:58 PM PDT 24 |
Apr 15 12:35:20 PM PDT 24 |
1811375604 ps |
| T59 |
/workspace/coverage/cover_reg_top/1.rom_ctrl_passthru_mem_tl_intg_err.136565125 |
|
|
Apr 15 12:23:49 PM PDT 24 |
Apr 15 12:25:49 PM PDT 24 |
13914676095 ps |
| T60 |
/workspace/coverage/cover_reg_top/0.rom_ctrl_csr_hw_reset.55550312 |
|
|
Apr 15 12:26:10 PM PDT 24 |
Apr 15 12:26:46 PM PDT 24 |
3212357794 ps |
| T61 |
/workspace/coverage/cover_reg_top/14.rom_ctrl_csr_mem_rw_with_rand_reset.3044037045 |
|
|
Apr 15 12:24:12 PM PDT 24 |
Apr 15 12:24:33 PM PDT 24 |
7565882859 ps |
| T63 |
/workspace/coverage/cover_reg_top/0.rom_ctrl_passthru_mem_tl_intg_err.3638374003 |
|
|
Apr 15 12:24:56 PM PDT 24 |
Apr 15 12:26:51 PM PDT 24 |
20696105426 ps |
| T366 |
/workspace/coverage/cover_reg_top/1.rom_ctrl_csr_mem_rw_with_rand_reset.2596509837 |
|
|
Apr 15 12:26:21 PM PDT 24 |
Apr 15 12:26:40 PM PDT 24 |
16727022991 ps |
| T64 |
/workspace/coverage/cover_reg_top/14.rom_ctrl_same_csr_outstanding.4280431440 |
|
|
Apr 15 12:26:35 PM PDT 24 |
Apr 15 12:26:47 PM PDT 24 |
716194613 ps |
| T65 |
/workspace/coverage/cover_reg_top/12.rom_ctrl_csr_rw.972209447 |
|
|
Apr 15 12:24:11 PM PDT 24 |
Apr 15 12:24:39 PM PDT 24 |
3498609787 ps |
| T106 |
/workspace/coverage/cover_reg_top/14.rom_ctrl_passthru_mem_tl_intg_err.4101142905 |
|
|
Apr 15 12:24:20 PM PDT 24 |
Apr 15 12:25:35 PM PDT 24 |
6261593212 ps |
| T367 |
/workspace/coverage/cover_reg_top/16.rom_ctrl_tl_errors.3996186267 |
|
|
Apr 15 12:26:38 PM PDT 24 |
Apr 15 12:26:54 PM PDT 24 |
254920336 ps |
| T368 |
/workspace/coverage/cover_reg_top/4.rom_ctrl_mem_walk.1594858495 |
|
|
Apr 15 12:25:20 PM PDT 24 |
Apr 15 12:25:51 PM PDT 24 |
7998700041 ps |
| T66 |
/workspace/coverage/cover_reg_top/1.rom_ctrl_csr_aliasing.548749365 |
|
|
Apr 15 12:26:15 PM PDT 24 |
Apr 15 12:26:27 PM PDT 24 |
1501464010 ps |
| T67 |
/workspace/coverage/cover_reg_top/19.rom_ctrl_passthru_mem_tl_intg_err.650730663 |
|
|
Apr 15 12:26:42 PM PDT 24 |
Apr 15 12:30:02 PM PDT 24 |
125308512151 ps |
| T107 |
/workspace/coverage/cover_reg_top/9.rom_ctrl_csr_rw.1684629831 |
|
|
Apr 15 12:24:13 PM PDT 24 |
Apr 15 12:24:42 PM PDT 24 |
11233910628 ps |
| T369 |
/workspace/coverage/cover_reg_top/8.rom_ctrl_csr_mem_rw_with_rand_reset.607677247 |
|
|
Apr 15 12:23:58 PM PDT 24 |
Apr 15 12:24:28 PM PDT 24 |
7055676952 ps |
| T56 |
/workspace/coverage/cover_reg_top/8.rom_ctrl_tl_intg_err.3388215894 |
|
|
Apr 15 12:26:28 PM PDT 24 |
Apr 15 12:29:20 PM PDT 24 |
8616212186 ps |
| T57 |
/workspace/coverage/cover_reg_top/5.rom_ctrl_tl_intg_err.836181113 |
|
|
Apr 15 12:26:21 PM PDT 24 |
Apr 15 12:29:14 PM PDT 24 |
3497210325 ps |
| T370 |
/workspace/coverage/cover_reg_top/16.rom_ctrl_csr_mem_rw_with_rand_reset.2605177428 |
|
|
Apr 15 12:26:36 PM PDT 24 |
Apr 15 12:26:45 PM PDT 24 |
372460069 ps |
| T68 |
/workspace/coverage/cover_reg_top/1.rom_ctrl_csr_rw.2510423560 |
|
|
Apr 15 12:26:12 PM PDT 24 |
Apr 15 12:26:42 PM PDT 24 |
7000548812 ps |
| T108 |
/workspace/coverage/cover_reg_top/18.rom_ctrl_csr_rw.2068512938 |
|
|
Apr 15 12:24:29 PM PDT 24 |
Apr 15 12:24:39 PM PDT 24 |
174529214 ps |
| T69 |
/workspace/coverage/cover_reg_top/5.rom_ctrl_passthru_mem_tl_intg_err.3186306637 |
|
|
Apr 15 12:24:04 PM PDT 24 |
Apr 15 12:25:38 PM PDT 24 |
51894655076 ps |
| T371 |
/workspace/coverage/cover_reg_top/2.rom_ctrl_csr_mem_rw_with_rand_reset.3467667740 |
|
|
Apr 15 12:26:18 PM PDT 24 |
Apr 15 12:26:36 PM PDT 24 |
1440834731 ps |
| T104 |
/workspace/coverage/cover_reg_top/19.rom_ctrl_same_csr_outstanding.2756059331 |
|
|
Apr 15 12:24:23 PM PDT 24 |
Apr 15 12:24:53 PM PDT 24 |
15346535494 ps |
| T372 |
/workspace/coverage/cover_reg_top/4.rom_ctrl_csr_mem_rw_with_rand_reset.648042488 |
|
|
Apr 15 12:26:27 PM PDT 24 |
Apr 15 12:26:55 PM PDT 24 |
3185448785 ps |
| T70 |
/workspace/coverage/cover_reg_top/14.rom_ctrl_passthru_mem_tl_intg_err.2571760816 |
|
|
Apr 15 12:26:42 PM PDT 24 |
Apr 15 12:27:21 PM PDT 24 |
1005175005 ps |
| T373 |
/workspace/coverage/cover_reg_top/2.rom_ctrl_mem_partial_access.1227996835 |
|
|
Apr 15 12:26:15 PM PDT 24 |
Apr 15 12:26:48 PM PDT 24 |
8560900143 ps |
| T58 |
/workspace/coverage/cover_reg_top/2.rom_ctrl_tl_intg_err.1060849903 |
|
|
Apr 15 12:26:18 PM PDT 24 |
Apr 15 12:28:04 PM PDT 24 |
4277651774 ps |
| T374 |
/workspace/coverage/cover_reg_top/2.rom_ctrl_csr_aliasing.2520265174 |
|
|
Apr 15 12:26:18 PM PDT 24 |
Apr 15 12:26:52 PM PDT 24 |
4430604657 ps |
| T375 |
/workspace/coverage/cover_reg_top/8.rom_ctrl_csr_rw.2441909142 |
|
|
Apr 15 12:24:16 PM PDT 24 |
Apr 15 12:24:37 PM PDT 24 |
8232680233 ps |
| T376 |
/workspace/coverage/cover_reg_top/1.rom_ctrl_mem_partial_access.2215725870 |
|
|
Apr 15 12:26:12 PM PDT 24 |
Apr 15 12:26:36 PM PDT 24 |
2663846283 ps |
| T377 |
/workspace/coverage/cover_reg_top/0.rom_ctrl_csr_bit_bash.3827178284 |
|
|
Apr 15 12:24:08 PM PDT 24 |
Apr 15 12:24:34 PM PDT 24 |
12145427164 ps |
| T378 |
/workspace/coverage/cover_reg_top/7.rom_ctrl_csr_rw.1921759700 |
|
|
Apr 15 12:26:30 PM PDT 24 |
Apr 15 12:26:58 PM PDT 24 |
12152431644 ps |
| T77 |
/workspace/coverage/cover_reg_top/2.rom_ctrl_passthru_mem_tl_intg_err.1471502812 |
|
|
Apr 15 12:24:08 PM PDT 24 |
Apr 15 12:25:30 PM PDT 24 |
7269706802 ps |
| T115 |
/workspace/coverage/cover_reg_top/0.rom_ctrl_tl_intg_err.2197332877 |
|
|
Apr 15 12:26:11 PM PDT 24 |
Apr 15 12:27:43 PM PDT 24 |
2310476954 ps |
| T379 |
/workspace/coverage/cover_reg_top/3.rom_ctrl_tl_errors.2950912581 |
|
|
Apr 15 12:25:18 PM PDT 24 |
Apr 15 12:25:29 PM PDT 24 |
1828568792 ps |
| T380 |
/workspace/coverage/cover_reg_top/5.rom_ctrl_passthru_mem_tl_intg_err.3991082248 |
|
|
Apr 15 12:26:28 PM PDT 24 |
Apr 15 12:27:41 PM PDT 24 |
11455672720 ps |
| T105 |
/workspace/coverage/cover_reg_top/6.rom_ctrl_same_csr_outstanding.3893186300 |
|
|
Apr 15 12:26:28 PM PDT 24 |
Apr 15 12:26:43 PM PDT 24 |
984244706 ps |
| T78 |
/workspace/coverage/cover_reg_top/10.rom_ctrl_csr_rw.4282297882 |
|
|
Apr 15 12:26:32 PM PDT 24 |
Apr 15 12:26:45 PM PDT 24 |
7177081413 ps |
| T381 |
/workspace/coverage/cover_reg_top/11.rom_ctrl_csr_mem_rw_with_rand_reset.2827425145 |
|
|
Apr 15 12:23:54 PM PDT 24 |
Apr 15 12:24:07 PM PDT 24 |
2384801113 ps |
| T382 |
/workspace/coverage/cover_reg_top/3.rom_ctrl_csr_mem_rw_with_rand_reset.4178680558 |
|
|
Apr 15 12:23:54 PM PDT 24 |
Apr 15 12:24:24 PM PDT 24 |
3269782509 ps |
| T112 |
/workspace/coverage/cover_reg_top/12.rom_ctrl_tl_intg_err.2578485098 |
|
|
Apr 15 12:24:13 PM PDT 24 |
Apr 15 12:25:44 PM PDT 24 |
6665933964 ps |
| T383 |
/workspace/coverage/cover_reg_top/19.rom_ctrl_csr_mem_rw_with_rand_reset.1480950114 |
|
|
Apr 15 12:26:50 PM PDT 24 |
Apr 15 12:27:16 PM PDT 24 |
15447828595 ps |
| T384 |
/workspace/coverage/cover_reg_top/3.rom_ctrl_csr_rw.1035414112 |
|
|
Apr 15 12:23:40 PM PDT 24 |
Apr 15 12:24:12 PM PDT 24 |
16479381149 ps |
| T385 |
/workspace/coverage/cover_reg_top/5.rom_ctrl_csr_rw.2793323770 |
|
|
Apr 15 12:23:50 PM PDT 24 |
Apr 15 12:24:18 PM PDT 24 |
8454405414 ps |
| T386 |
/workspace/coverage/cover_reg_top/5.rom_ctrl_csr_mem_rw_with_rand_reset.2432921078 |
|
|
Apr 15 12:24:04 PM PDT 24 |
Apr 15 12:24:14 PM PDT 24 |
1347357236 ps |
| T88 |
/workspace/coverage/cover_reg_top/2.rom_ctrl_passthru_mem_tl_intg_err.3709806769 |
|
|
Apr 15 12:26:18 PM PDT 24 |
Apr 15 12:28:55 PM PDT 24 |
68919373135 ps |
| T387 |
/workspace/coverage/cover_reg_top/14.rom_ctrl_csr_mem_rw_with_rand_reset.3721425804 |
|
|
Apr 15 12:26:34 PM PDT 24 |
Apr 15 12:26:59 PM PDT 24 |
5474018057 ps |
| T388 |
/workspace/coverage/cover_reg_top/3.rom_ctrl_csr_rw.496543865 |
|
|
Apr 15 12:26:17 PM PDT 24 |
Apr 15 12:26:50 PM PDT 24 |
8155368282 ps |
| T89 |
/workspace/coverage/cover_reg_top/1.rom_ctrl_passthru_mem_tl_intg_err.3402742533 |
|
|
Apr 15 12:26:12 PM PDT 24 |
Apr 15 12:26:50 PM PDT 24 |
3464992067 ps |
| T389 |
/workspace/coverage/cover_reg_top/9.rom_ctrl_same_csr_outstanding.3003362206 |
|
|
Apr 15 12:26:27 PM PDT 24 |
Apr 15 12:26:36 PM PDT 24 |
1098964802 ps |
| T390 |
/workspace/coverage/cover_reg_top/3.rom_ctrl_csr_mem_rw_with_rand_reset.1383052108 |
|
|
Apr 15 12:26:16 PM PDT 24 |
Apr 15 12:26:25 PM PDT 24 |
391197594 ps |
| T391 |
/workspace/coverage/cover_reg_top/13.rom_ctrl_same_csr_outstanding.1582569507 |
|
|
Apr 15 12:24:08 PM PDT 24 |
Apr 15 12:24:36 PM PDT 24 |
20734935878 ps |
| T392 |
/workspace/coverage/cover_reg_top/12.rom_ctrl_tl_errors.2024408586 |
|
|
Apr 15 12:26:42 PM PDT 24 |
Apr 15 12:26:56 PM PDT 24 |
338922189 ps |
| T113 |
/workspace/coverage/cover_reg_top/15.rom_ctrl_tl_intg_err.2897895169 |
|
|
Apr 15 12:26:39 PM PDT 24 |
Apr 15 12:29:21 PM PDT 24 |
1676113671 ps |
| T393 |
/workspace/coverage/cover_reg_top/1.rom_ctrl_csr_mem_rw_with_rand_reset.4035361524 |
|
|
Apr 15 12:24:16 PM PDT 24 |
Apr 15 12:24:40 PM PDT 24 |
24965763201 ps |
| T394 |
/workspace/coverage/cover_reg_top/3.rom_ctrl_mem_partial_access.451181388 |
|
|
Apr 15 12:24:08 PM PDT 24 |
Apr 15 12:24:29 PM PDT 24 |
2198520400 ps |
| T395 |
/workspace/coverage/cover_reg_top/3.rom_ctrl_csr_hw_reset.342796654 |
|
|
Apr 15 12:26:21 PM PDT 24 |
Apr 15 12:26:37 PM PDT 24 |
1703027186 ps |
| T80 |
/workspace/coverage/cover_reg_top/4.rom_ctrl_passthru_mem_tl_intg_err.12491728 |
|
|
Apr 15 12:26:16 PM PDT 24 |
Apr 15 12:29:02 PM PDT 24 |
72992848793 ps |
| T396 |
/workspace/coverage/cover_reg_top/3.rom_ctrl_csr_hw_reset.579966953 |
|
|
Apr 15 12:24:06 PM PDT 24 |
Apr 15 12:24:28 PM PDT 24 |
1525856639 ps |
| T397 |
/workspace/coverage/cover_reg_top/0.rom_ctrl_mem_walk.1075016513 |
|
|
Apr 15 12:26:11 PM PDT 24 |
Apr 15 12:26:32 PM PDT 24 |
2066907394 ps |
| T398 |
/workspace/coverage/cover_reg_top/0.rom_ctrl_csr_aliasing.3172175659 |
|
|
Apr 15 12:25:03 PM PDT 24 |
Apr 15 12:25:11 PM PDT 24 |
174284088 ps |
| T399 |
/workspace/coverage/cover_reg_top/18.rom_ctrl_csr_rw.1465068083 |
|
|
Apr 15 12:26:39 PM PDT 24 |
Apr 15 12:26:48 PM PDT 24 |
211043140 ps |
| T400 |
/workspace/coverage/cover_reg_top/10.rom_ctrl_tl_errors.2862846000 |
|
|
Apr 15 12:24:14 PM PDT 24 |
Apr 15 12:24:27 PM PDT 24 |
688886292 ps |
| T401 |
/workspace/coverage/cover_reg_top/2.rom_ctrl_csr_hw_reset.2096532491 |
|
|
Apr 15 12:26:18 PM PDT 24 |
Apr 15 12:26:29 PM PDT 24 |
3326436814 ps |
| T402 |
/workspace/coverage/cover_reg_top/10.rom_ctrl_passthru_mem_tl_intg_err.3594811537 |
|
|
Apr 15 12:26:28 PM PDT 24 |
Apr 15 12:27:07 PM PDT 24 |
1422217311 ps |
| T403 |
/workspace/coverage/cover_reg_top/1.rom_ctrl_csr_bit_bash.2395784980 |
|
|
Apr 15 12:26:10 PM PDT 24 |
Apr 15 12:26:19 PM PDT 24 |
918406256 ps |
| T124 |
/workspace/coverage/cover_reg_top/19.rom_ctrl_tl_intg_err.2810346014 |
|
|
Apr 15 12:24:23 PM PDT 24 |
Apr 15 12:26:54 PM PDT 24 |
1158944831 ps |
| T404 |
/workspace/coverage/cover_reg_top/15.rom_ctrl_same_csr_outstanding.87514222 |
|
|
Apr 15 12:26:38 PM PDT 24 |
Apr 15 12:27:06 PM PDT 24 |
3318327023 ps |
| T405 |
/workspace/coverage/cover_reg_top/5.rom_ctrl_tl_errors.1256808907 |
|
|
Apr 15 12:26:23 PM PDT 24 |
Apr 15 12:26:35 PM PDT 24 |
917692271 ps |
| T406 |
/workspace/coverage/cover_reg_top/17.rom_ctrl_tl_errors.140432404 |
|
|
Apr 15 12:26:41 PM PDT 24 |
Apr 15 12:27:01 PM PDT 24 |
2621743310 ps |
| T407 |
/workspace/coverage/cover_reg_top/13.rom_ctrl_tl_errors.414216269 |
|
|
Apr 15 12:23:57 PM PDT 24 |
Apr 15 12:24:23 PM PDT 24 |
9878420524 ps |
| T408 |
/workspace/coverage/cover_reg_top/6.rom_ctrl_same_csr_outstanding.2930853364 |
|
|
Apr 15 12:24:09 PM PDT 24 |
Apr 15 12:24:33 PM PDT 24 |
9869092890 ps |
| T90 |
/workspace/coverage/cover_reg_top/3.rom_ctrl_passthru_mem_tl_intg_err.3149158759 |
|
|
Apr 15 12:26:18 PM PDT 24 |
Apr 15 12:28:35 PM PDT 24 |
39137659432 ps |
| T409 |
/workspace/coverage/cover_reg_top/0.rom_ctrl_mem_partial_access.213921414 |
|
|
Apr 15 12:26:14 PM PDT 24 |
Apr 15 12:26:46 PM PDT 24 |
15524536708 ps |
| T410 |
/workspace/coverage/cover_reg_top/3.rom_ctrl_csr_bit_bash.1451650779 |
|
|
Apr 15 12:26:21 PM PDT 24 |
Apr 15 12:26:42 PM PDT 24 |
2051384025 ps |
| T91 |
/workspace/coverage/cover_reg_top/0.rom_ctrl_passthru_mem_tl_intg_err.2209432928 |
|
|
Apr 15 12:26:11 PM PDT 24 |
Apr 15 12:27:09 PM PDT 24 |
4308624921 ps |
| T411 |
/workspace/coverage/cover_reg_top/19.rom_ctrl_same_csr_outstanding.1283871247 |
|
|
Apr 15 12:26:51 PM PDT 24 |
Apr 15 12:27:00 PM PDT 24 |
172895093 ps |
| T412 |
/workspace/coverage/cover_reg_top/4.rom_ctrl_csr_hw_reset.1502817537 |
|
|
Apr 15 12:23:54 PM PDT 24 |
Apr 15 12:24:31 PM PDT 24 |
3480151390 ps |
| T413 |
/workspace/coverage/cover_reg_top/11.rom_ctrl_tl_intg_err.3780887949 |
|
|
Apr 15 12:24:12 PM PDT 24 |
Apr 15 12:27:02 PM PDT 24 |
6896036863 ps |
| T414 |
/workspace/coverage/cover_reg_top/1.rom_ctrl_csr_hw_reset.1568928110 |
|
|
Apr 15 12:26:16 PM PDT 24 |
Apr 15 12:26:52 PM PDT 24 |
4217948956 ps |
| T415 |
/workspace/coverage/cover_reg_top/13.rom_ctrl_passthru_mem_tl_intg_err.1037409012 |
|
|
Apr 15 12:24:18 PM PDT 24 |
Apr 15 12:26:08 PM PDT 24 |
24892126960 ps |
| T416 |
/workspace/coverage/cover_reg_top/6.rom_ctrl_tl_errors.2266616507 |
|
|
Apr 15 12:24:12 PM PDT 24 |
Apr 15 12:24:33 PM PDT 24 |
1566022265 ps |
| T417 |
/workspace/coverage/cover_reg_top/11.rom_ctrl_passthru_mem_tl_intg_err.2989262392 |
|
|
Apr 15 12:26:33 PM PDT 24 |
Apr 15 12:29:29 PM PDT 24 |
23417450958 ps |
| T418 |
/workspace/coverage/cover_reg_top/12.rom_ctrl_csr_mem_rw_with_rand_reset.331850648 |
|
|
Apr 15 12:26:34 PM PDT 24 |
Apr 15 12:26:45 PM PDT 24 |
1817972812 ps |
| T419 |
/workspace/coverage/cover_reg_top/5.rom_ctrl_same_csr_outstanding.203376583 |
|
|
Apr 15 12:26:24 PM PDT 24 |
Apr 15 12:26:40 PM PDT 24 |
14012813842 ps |
| T420 |
/workspace/coverage/cover_reg_top/3.rom_ctrl_mem_partial_access.4177637633 |
|
|
Apr 15 12:26:19 PM PDT 24 |
Apr 15 12:26:37 PM PDT 24 |
6249082694 ps |
| T421 |
/workspace/coverage/cover_reg_top/4.rom_ctrl_csr_hw_reset.3445010197 |
|
|
Apr 15 12:26:22 PM PDT 24 |
Apr 15 12:26:45 PM PDT 24 |
20632648189 ps |
| T422 |
/workspace/coverage/cover_reg_top/11.rom_ctrl_csr_rw.1373754571 |
|
|
Apr 15 12:26:35 PM PDT 24 |
Apr 15 12:26:43 PM PDT 24 |
660736748 ps |
| T116 |
/workspace/coverage/cover_reg_top/17.rom_ctrl_tl_intg_err.3834578952 |
|
|
Apr 15 12:26:41 PM PDT 24 |
Apr 15 12:28:18 PM PDT 24 |
3320676447 ps |
| T423 |
/workspace/coverage/cover_reg_top/0.rom_ctrl_csr_mem_rw_with_rand_reset.3223078001 |
|
|
Apr 15 12:24:16 PM PDT 24 |
Apr 15 12:24:42 PM PDT 24 |
3034572947 ps |
| T117 |
/workspace/coverage/cover_reg_top/5.rom_ctrl_tl_intg_err.3023124272 |
|
|
Apr 15 12:23:51 PM PDT 24 |
Apr 15 12:26:29 PM PDT 24 |
2532313339 ps |
| T424 |
/workspace/coverage/cover_reg_top/11.rom_ctrl_tl_intg_err.2071313247 |
|
|
Apr 15 12:26:33 PM PDT 24 |
Apr 15 12:28:06 PM PDT 24 |
7803909261 ps |
| T425 |
/workspace/coverage/cover_reg_top/3.rom_ctrl_mem_walk.4275358083 |
|
|
Apr 15 12:23:50 PM PDT 24 |
Apr 15 12:24:16 PM PDT 24 |
21421626418 ps |
| T426 |
/workspace/coverage/cover_reg_top/4.rom_ctrl_csr_mem_rw_with_rand_reset.1666155746 |
|
|
Apr 15 12:23:48 PM PDT 24 |
Apr 15 12:24:22 PM PDT 24 |
26515164417 ps |
| T427 |
/workspace/coverage/cover_reg_top/14.rom_ctrl_csr_rw.2562339645 |
|
|
Apr 15 12:26:31 PM PDT 24 |
Apr 15 12:26:40 PM PDT 24 |
612285911 ps |
| T428 |
/workspace/coverage/cover_reg_top/0.rom_ctrl_csr_mem_rw_with_rand_reset.2885253807 |
|
|
Apr 15 12:26:14 PM PDT 24 |
Apr 15 12:26:39 PM PDT 24 |
12097679934 ps |
| T429 |
/workspace/coverage/cover_reg_top/15.rom_ctrl_csr_rw.1409133742 |
|
|
Apr 15 12:26:39 PM PDT 24 |
Apr 15 12:26:48 PM PDT 24 |
533447781 ps |
| T430 |
/workspace/coverage/cover_reg_top/3.rom_ctrl_csr_aliasing.1507355377 |
|
|
Apr 15 12:24:12 PM PDT 24 |
Apr 15 12:24:37 PM PDT 24 |
11593823182 ps |
| T431 |
/workspace/coverage/cover_reg_top/10.rom_ctrl_same_csr_outstanding.1976874872 |
|
|
Apr 15 12:26:33 PM PDT 24 |
Apr 15 12:26:45 PM PDT 24 |
3470510943 ps |
| T432 |
/workspace/coverage/cover_reg_top/2.rom_ctrl_tl_errors.1016280546 |
|
|
Apr 15 12:24:55 PM PDT 24 |
Apr 15 12:25:32 PM PDT 24 |
42909413556 ps |
| T81 |
/workspace/coverage/cover_reg_top/2.rom_ctrl_csr_aliasing.824144211 |
|
|
Apr 15 12:24:21 PM PDT 24 |
Apr 15 12:24:44 PM PDT 24 |
21413267637 ps |
| T92 |
/workspace/coverage/cover_reg_top/9.rom_ctrl_passthru_mem_tl_intg_err.3718924286 |
|
|
Apr 15 12:26:29 PM PDT 24 |
Apr 15 12:28:28 PM PDT 24 |
10357893249 ps |
| T433 |
/workspace/coverage/cover_reg_top/3.rom_ctrl_same_csr_outstanding.1263596768 |
|
|
Apr 15 12:25:09 PM PDT 24 |
Apr 15 12:25:18 PM PDT 24 |
167548260 ps |
| T434 |
/workspace/coverage/cover_reg_top/8.rom_ctrl_same_csr_outstanding.2649997475 |
|
|
Apr 15 12:24:15 PM PDT 24 |
Apr 15 12:24:37 PM PDT 24 |
8578525761 ps |
| T435 |
/workspace/coverage/cover_reg_top/8.rom_ctrl_tl_errors.456584647 |
|
|
Apr 15 12:24:13 PM PDT 24 |
Apr 15 12:24:32 PM PDT 24 |
3702870874 ps |
| T436 |
/workspace/coverage/cover_reg_top/9.rom_ctrl_tl_errors.943831423 |
|
|
Apr 15 12:26:28 PM PDT 24 |
Apr 15 12:27:04 PM PDT 24 |
29927016601 ps |
| T437 |
/workspace/coverage/cover_reg_top/14.rom_ctrl_tl_errors.3139941222 |
|
|
Apr 15 12:26:33 PM PDT 24 |
Apr 15 12:27:07 PM PDT 24 |
4226877354 ps |
| T438 |
/workspace/coverage/cover_reg_top/13.rom_ctrl_csr_mem_rw_with_rand_reset.694908251 |
|
|
Apr 15 12:24:20 PM PDT 24 |
Apr 15 12:24:31 PM PDT 24 |
1628174306 ps |
| T118 |
/workspace/coverage/cover_reg_top/7.rom_ctrl_tl_intg_err.1584796660 |
|
|
Apr 15 12:26:31 PM PDT 24 |
Apr 15 12:29:08 PM PDT 24 |
1474385091 ps |
| T439 |
/workspace/coverage/cover_reg_top/6.rom_ctrl_csr_rw.2729883249 |
|
|
Apr 15 12:26:25 PM PDT 24 |
Apr 15 12:26:50 PM PDT 24 |
5861655187 ps |
| T440 |
/workspace/coverage/cover_reg_top/1.rom_ctrl_csr_rw.147665400 |
|
|
Apr 15 12:25:17 PM PDT 24 |
Apr 15 12:25:43 PM PDT 24 |
5871846609 ps |
| T441 |
/workspace/coverage/cover_reg_top/0.rom_ctrl_mem_walk.804387884 |
|
|
Apr 15 12:25:18 PM PDT 24 |
Apr 15 12:25:27 PM PDT 24 |
176098229 ps |
| T442 |
/workspace/coverage/cover_reg_top/4.rom_ctrl_same_csr_outstanding.1403467402 |
|
|
Apr 15 12:26:28 PM PDT 24 |
Apr 15 12:26:37 PM PDT 24 |
447232595 ps |
| T443 |
/workspace/coverage/cover_reg_top/2.rom_ctrl_csr_bit_bash.337844695 |
|
|
Apr 15 12:26:18 PM PDT 24 |
Apr 15 12:26:48 PM PDT 24 |
9206066509 ps |
| T444 |
/workspace/coverage/cover_reg_top/6.rom_ctrl_tl_intg_err.2192882779 |
|
|
Apr 15 12:23:49 PM PDT 24 |
Apr 15 12:26:22 PM PDT 24 |
2191562994 ps |
| T445 |
/workspace/coverage/cover_reg_top/19.rom_ctrl_tl_errors.2384676040 |
|
|
Apr 15 12:26:43 PM PDT 24 |
Apr 15 12:26:56 PM PDT 24 |
185693423 ps |
| T446 |
/workspace/coverage/cover_reg_top/12.rom_ctrl_csr_rw.2244180457 |
|
|
Apr 15 12:26:33 PM PDT 24 |
Apr 15 12:27:04 PM PDT 24 |
18032719927 ps |
| T447 |
/workspace/coverage/cover_reg_top/1.rom_ctrl_csr_hw_reset.1683138422 |
|
|
Apr 15 12:25:08 PM PDT 24 |
Apr 15 12:25:32 PM PDT 24 |
8255813897 ps |
| T448 |
/workspace/coverage/cover_reg_top/5.rom_ctrl_same_csr_outstanding.805863624 |
|
|
Apr 15 12:24:20 PM PDT 24 |
Apr 15 12:24:37 PM PDT 24 |
2395590610 ps |
| T449 |
/workspace/coverage/cover_reg_top/11.rom_ctrl_tl_errors.3993311365 |
|
|
Apr 15 12:26:34 PM PDT 24 |
Apr 15 12:26:54 PM PDT 24 |
1255467141 ps |
| T450 |
/workspace/coverage/cover_reg_top/17.rom_ctrl_csr_mem_rw_with_rand_reset.675888899 |
|
|
Apr 15 12:24:21 PM PDT 24 |
Apr 15 12:24:49 PM PDT 24 |
3263717417 ps |
| T451 |
/workspace/coverage/cover_reg_top/18.rom_ctrl_tl_errors.376923685 |
|
|
Apr 15 12:24:15 PM PDT 24 |
Apr 15 12:24:41 PM PDT 24 |
2536289898 ps |
| T452 |
/workspace/coverage/cover_reg_top/1.rom_ctrl_mem_walk.4097192943 |
|
|
Apr 15 12:23:40 PM PDT 24 |
Apr 15 12:24:14 PM PDT 24 |
46425734056 ps |
| T453 |
/workspace/coverage/cover_reg_top/9.rom_ctrl_csr_mem_rw_with_rand_reset.3062200466 |
|
|
Apr 15 12:26:28 PM PDT 24 |
Apr 15 12:26:51 PM PDT 24 |
2311832040 ps |
| T454 |
/workspace/coverage/cover_reg_top/17.rom_ctrl_same_csr_outstanding.2724288463 |
|
|
Apr 15 12:24:16 PM PDT 24 |
Apr 15 12:24:29 PM PDT 24 |
186351076 ps |
| T455 |
/workspace/coverage/cover_reg_top/0.rom_ctrl_csr_hw_reset.1874467278 |
|
|
Apr 15 12:24:08 PM PDT 24 |
Apr 15 12:24:33 PM PDT 24 |
3874405050 ps |
| T456 |
/workspace/coverage/cover_reg_top/4.rom_ctrl_csr_rw.3325582423 |
|
|
Apr 15 12:24:06 PM PDT 24 |
Apr 15 12:24:31 PM PDT 24 |
18042988894 ps |
| T457 |
/workspace/coverage/cover_reg_top/6.rom_ctrl_csr_mem_rw_with_rand_reset.263968295 |
|
|
Apr 15 12:24:07 PM PDT 24 |
Apr 15 12:24:41 PM PDT 24 |
4736008803 ps |
| T458 |
/workspace/coverage/cover_reg_top/15.rom_ctrl_csr_mem_rw_with_rand_reset.3177866281 |
|
|
Apr 15 12:26:38 PM PDT 24 |
Apr 15 12:26:52 PM PDT 24 |
2122631333 ps |
| T459 |
/workspace/coverage/cover_reg_top/15.rom_ctrl_passthru_mem_tl_intg_err.3947273378 |
|
|
Apr 15 12:24:31 PM PDT 24 |
Apr 15 12:26:01 PM PDT 24 |
38119637756 ps |
| T460 |
/workspace/coverage/cover_reg_top/18.rom_ctrl_same_csr_outstanding.152802797 |
|
|
Apr 15 12:24:25 PM PDT 24 |
Apr 15 12:24:45 PM PDT 24 |
1159531723 ps |
| T461 |
/workspace/coverage/cover_reg_top/19.rom_ctrl_csr_rw.2759445711 |
|
|
Apr 15 12:24:27 PM PDT 24 |
Apr 15 12:24:59 PM PDT 24 |
16396608753 ps |
| T462 |
/workspace/coverage/cover_reg_top/18.rom_ctrl_passthru_mem_tl_intg_err.1739275216 |
|
|
Apr 15 12:26:40 PM PDT 24 |
Apr 15 12:29:51 PM PDT 24 |
24116535133 ps |
| T463 |
/workspace/coverage/cover_reg_top/15.rom_ctrl_tl_errors.1707646004 |
|
|
Apr 15 12:26:36 PM PDT 24 |
Apr 15 12:27:03 PM PDT 24 |
8471715552 ps |
| T114 |
/workspace/coverage/cover_reg_top/18.rom_ctrl_tl_intg_err.2434645193 |
|
|
Apr 15 12:24:13 PM PDT 24 |
Apr 15 12:27:06 PM PDT 24 |
15714154231 ps |
| T464 |
/workspace/coverage/cover_reg_top/10.rom_ctrl_tl_intg_err.1745803606 |
|
|
Apr 15 12:26:28 PM PDT 24 |
Apr 15 12:27:52 PM PDT 24 |
969655325 ps |
| T465 |
/workspace/coverage/cover_reg_top/14.rom_ctrl_tl_errors.868126569 |
|
|
Apr 15 12:24:06 PM PDT 24 |
Apr 15 12:24:33 PM PDT 24 |
11269106635 ps |
| T466 |
/workspace/coverage/cover_reg_top/15.rom_ctrl_same_csr_outstanding.17656651 |
|
|
Apr 15 12:24:17 PM PDT 24 |
Apr 15 12:24:43 PM PDT 24 |
2861807232 ps |
| T125 |
/workspace/coverage/cover_reg_top/1.rom_ctrl_tl_intg_err.944118311 |
|
|
Apr 15 12:23:41 PM PDT 24 |
Apr 15 12:26:41 PM PDT 24 |
4397299882 ps |
| T467 |
/workspace/coverage/cover_reg_top/6.rom_ctrl_csr_mem_rw_with_rand_reset.1614451615 |
|
|
Apr 15 12:26:26 PM PDT 24 |
Apr 15 12:26:35 PM PDT 24 |
362290802 ps |
| T468 |
/workspace/coverage/cover_reg_top/2.rom_ctrl_mem_partial_access.3537309910 |
|
|
Apr 15 12:24:15 PM PDT 24 |
Apr 15 12:24:23 PM PDT 24 |
170739749 ps |
| T469 |
/workspace/coverage/cover_reg_top/11.rom_ctrl_passthru_mem_tl_intg_err.2729682815 |
|
|
Apr 15 12:23:52 PM PDT 24 |
Apr 15 12:25:35 PM PDT 24 |
43180238345 ps |
| T470 |
/workspace/coverage/cover_reg_top/2.rom_ctrl_tl_intg_err.2693596218 |
|
|
Apr 15 12:25:09 PM PDT 24 |
Apr 15 12:26:35 PM PDT 24 |
1048339930 ps |
| T471 |
/workspace/coverage/cover_reg_top/7.rom_ctrl_same_csr_outstanding.365378151 |
|
|
Apr 15 12:23:48 PM PDT 24 |
Apr 15 12:24:18 PM PDT 24 |
12714012790 ps |
| T93 |
/workspace/coverage/cover_reg_top/12.rom_ctrl_passthru_mem_tl_intg_err.2348595430 |
|
|
Apr 15 12:26:32 PM PDT 24 |
Apr 15 12:27:38 PM PDT 24 |
4699091904 ps |
| T472 |
/workspace/coverage/cover_reg_top/9.rom_ctrl_tl_intg_err.3954205079 |
|
|
Apr 15 12:26:29 PM PDT 24 |
Apr 15 12:29:21 PM PDT 24 |
3154571029 ps |
| T473 |
/workspace/coverage/cover_reg_top/12.rom_ctrl_tl_intg_err.1137032830 |
|
|
Apr 15 12:26:42 PM PDT 24 |
Apr 15 12:28:05 PM PDT 24 |
288012418 ps |
| T82 |
/workspace/coverage/cover_reg_top/8.rom_ctrl_csr_rw.1436633549 |
|
|
Apr 15 12:26:27 PM PDT 24 |
Apr 15 12:26:44 PM PDT 24 |
1196598496 ps |
| T474 |
/workspace/coverage/cover_reg_top/1.rom_ctrl_same_csr_outstanding.3937870995 |
|
|
Apr 15 12:24:48 PM PDT 24 |
Apr 15 12:25:17 PM PDT 24 |
3417602126 ps |
| T475 |
/workspace/coverage/cover_reg_top/9.rom_ctrl_tl_intg_err.3918965978 |
|
|
Apr 15 12:24:15 PM PDT 24 |
Apr 15 12:25:36 PM PDT 24 |
1062280809 ps |
| T476 |
/workspace/coverage/cover_reg_top/4.rom_ctrl_csr_bit_bash.1781740851 |
|
|
Apr 15 12:26:20 PM PDT 24 |
Apr 15 12:26:40 PM PDT 24 |
2002561997 ps |
| T477 |
/workspace/coverage/cover_reg_top/3.rom_ctrl_same_csr_outstanding.2035112881 |
|
|
Apr 15 12:26:19 PM PDT 24 |
Apr 15 12:26:42 PM PDT 24 |
2376257235 ps |
| T478 |
/workspace/coverage/cover_reg_top/0.rom_ctrl_same_csr_outstanding.3192813256 |
|
|
Apr 15 12:26:11 PM PDT 24 |
Apr 15 12:26:43 PM PDT 24 |
4107705055 ps |
| T479 |
/workspace/coverage/cover_reg_top/0.rom_ctrl_mem_partial_access.2819112555 |
|
|
Apr 15 12:23:57 PM PDT 24 |
Apr 15 12:24:25 PM PDT 24 |
6643935442 ps |
| T480 |
/workspace/coverage/cover_reg_top/13.rom_ctrl_passthru_mem_tl_intg_err.597930639 |
|
|
Apr 15 12:26:49 PM PDT 24 |
Apr 15 12:29:47 PM PDT 24 |
147565177516 ps |
| T119 |
/workspace/coverage/cover_reg_top/4.rom_ctrl_tl_intg_err.4095078125 |
|
|
Apr 15 12:26:18 PM PDT 24 |
Apr 15 12:29:16 PM PDT 24 |
17265609819 ps |
| T481 |
/workspace/coverage/cover_reg_top/0.rom_ctrl_tl_intg_err.2813372035 |
|
|
Apr 15 12:23:44 PM PDT 24 |
Apr 15 12:26:27 PM PDT 24 |
2502871232 ps |
| T121 |
/workspace/coverage/cover_reg_top/15.rom_ctrl_tl_intg_err.1275101142 |
|
|
Apr 15 12:24:10 PM PDT 24 |
Apr 15 12:26:44 PM PDT 24 |
1046998792 ps |
| T482 |
/workspace/coverage/cover_reg_top/1.rom_ctrl_same_csr_outstanding.4257695599 |
|
|
Apr 15 12:26:12 PM PDT 24 |
Apr 15 12:26:35 PM PDT 24 |
2285765668 ps |
| T483 |
/workspace/coverage/cover_reg_top/9.rom_ctrl_csr_rw.2185540470 |
|
|
Apr 15 12:26:26 PM PDT 24 |
Apr 15 12:26:38 PM PDT 24 |
1029016354 ps |
| T484 |
/workspace/coverage/cover_reg_top/8.rom_ctrl_tl_intg_err.2668804968 |
|
|
Apr 15 12:23:49 PM PDT 24 |
Apr 15 12:25:15 PM PDT 24 |
11758692707 ps |
| T485 |
/workspace/coverage/cover_reg_top/19.rom_ctrl_passthru_mem_tl_intg_err.2304584793 |
|
|
Apr 15 12:24:20 PM PDT 24 |
Apr 15 12:25:47 PM PDT 24 |
8016515209 ps |
| T486 |
/workspace/coverage/cover_reg_top/14.rom_ctrl_same_csr_outstanding.4016990392 |
|
|
Apr 15 12:24:11 PM PDT 24 |
Apr 15 12:24:31 PM PDT 24 |
2011339076 ps |
| T487 |
/workspace/coverage/cover_reg_top/3.rom_ctrl_tl_intg_err.2082729124 |
|
|
Apr 15 12:26:17 PM PDT 24 |
Apr 15 12:27:58 PM PDT 24 |
14420796313 ps |
| T488 |
/workspace/coverage/cover_reg_top/18.rom_ctrl_same_csr_outstanding.1204927351 |
|
|
Apr 15 12:26:38 PM PDT 24 |
Apr 15 12:26:47 PM PDT 24 |
1375288983 ps |
| T489 |
/workspace/coverage/cover_reg_top/7.rom_ctrl_passthru_mem_tl_intg_err.1187905435 |
|
|
Apr 15 12:23:56 PM PDT 24 |
Apr 15 12:27:00 PM PDT 24 |
22146518453 ps |
| T490 |
/workspace/coverage/cover_reg_top/2.rom_ctrl_csr_rw.2031091266 |
|
|
Apr 15 12:26:18 PM PDT 24 |
Apr 15 12:26:27 PM PDT 24 |
174178184 ps |
| T491 |
/workspace/coverage/cover_reg_top/17.rom_ctrl_tl_intg_err.2700891747 |
|
|
Apr 15 12:24:31 PM PDT 24 |
Apr 15 12:25:57 PM PDT 24 |
3183565192 ps |
| T492 |
/workspace/coverage/cover_reg_top/7.rom_ctrl_passthru_mem_tl_intg_err.224062572 |
|
|
Apr 15 12:26:25 PM PDT 24 |
Apr 15 12:29:24 PM PDT 24 |
132210836177 ps |
| T493 |
/workspace/coverage/cover_reg_top/19.rom_ctrl_tl_errors.3220093379 |
|
|
Apr 15 12:24:22 PM PDT 24 |
Apr 15 12:24:58 PM PDT 24 |
22481918414 ps |
| T494 |
/workspace/coverage/cover_reg_top/2.rom_ctrl_tl_errors.2298198323 |
|
|
Apr 15 12:26:16 PM PDT 24 |
Apr 15 12:26:45 PM PDT 24 |
3036528647 ps |
| T495 |
/workspace/coverage/cover_reg_top/12.rom_ctrl_same_csr_outstanding.21926426 |
|
|
Apr 15 12:26:31 PM PDT 24 |
Apr 15 12:27:03 PM PDT 24 |
3245805669 ps |
| T496 |
/workspace/coverage/cover_reg_top/0.rom_ctrl_csr_bit_bash.1295609781 |
|
|
Apr 15 12:26:12 PM PDT 24 |
Apr 15 12:26:46 PM PDT 24 |
4068384583 ps |
| T497 |
/workspace/coverage/cover_reg_top/7.rom_ctrl_tl_intg_err.686581773 |
|
|
Apr 15 12:24:06 PM PDT 24 |
Apr 15 12:25:45 PM PDT 24 |
3242264336 ps |
| T498 |
/workspace/coverage/cover_reg_top/2.rom_ctrl_csr_bit_bash.3608064414 |
|
|
Apr 15 12:24:07 PM PDT 24 |
Apr 15 12:24:23 PM PDT 24 |
937652261 ps |
| T499 |
/workspace/coverage/cover_reg_top/3.rom_ctrl_csr_aliasing.3921876001 |
|
|
Apr 15 12:26:19 PM PDT 24 |
Apr 15 12:26:27 PM PDT 24 |
172585486 ps |
| T500 |
/workspace/coverage/cover_reg_top/5.rom_ctrl_tl_errors.3394095191 |
|
|
Apr 15 12:24:02 PM PDT 24 |
Apr 15 12:24:36 PM PDT 24 |
15317159074 ps |
| T501 |
/workspace/coverage/cover_reg_top/3.rom_ctrl_csr_bit_bash.3596014388 |
|
|
Apr 15 12:24:10 PM PDT 24 |
Apr 15 12:24:36 PM PDT 24 |
43755298766 ps |
| T502 |
/workspace/coverage/cover_reg_top/14.rom_ctrl_tl_intg_err.2819378106 |
|
|
Apr 15 12:26:33 PM PDT 24 |
Apr 15 12:27:54 PM PDT 24 |
619616297 ps |
| T503 |
/workspace/coverage/cover_reg_top/7.rom_ctrl_csr_mem_rw_with_rand_reset.2852351563 |
|
|
Apr 15 12:23:50 PM PDT 24 |
Apr 15 12:24:22 PM PDT 24 |
15729461928 ps |
| T504 |
/workspace/coverage/cover_reg_top/7.rom_ctrl_csr_rw.2120491467 |
|
|
Apr 15 12:24:06 PM PDT 24 |
Apr 15 12:24:35 PM PDT 24 |
16451906040 ps |
| T505 |
/workspace/coverage/cover_reg_top/13.rom_ctrl_csr_rw.1763373261 |
|
|
Apr 15 12:26:32 PM PDT 24 |
Apr 15 12:26:41 PM PDT 24 |
869759743 ps |
| T506 |
/workspace/coverage/cover_reg_top/4.rom_ctrl_csr_aliasing.1063270063 |
|
|
Apr 15 12:25:09 PM PDT 24 |
Apr 15 12:25:42 PM PDT 24 |
16529076182 ps |
| T507 |
/workspace/coverage/cover_reg_top/16.rom_ctrl_same_csr_outstanding.3236118615 |
|
|
Apr 15 12:24:24 PM PDT 24 |
Apr 15 12:24:33 PM PDT 24 |
172452159 ps |
| T508 |
/workspace/coverage/cover_reg_top/2.rom_ctrl_same_csr_outstanding.1656907405 |
|
|
Apr 15 12:26:17 PM PDT 24 |
Apr 15 12:26:26 PM PDT 24 |
172856042 ps |
| T509 |
/workspace/coverage/cover_reg_top/9.rom_ctrl_csr_mem_rw_with_rand_reset.3511482418 |
|
|
Apr 15 12:24:03 PM PDT 24 |
Apr 15 12:24:33 PM PDT 24 |
7965960449 ps |
| T510 |
/workspace/coverage/cover_reg_top/8.rom_ctrl_tl_errors.3514012837 |
|
|
Apr 15 12:26:28 PM PDT 24 |
Apr 15 12:26:51 PM PDT 24 |
2951678062 ps |
| T511 |
/workspace/coverage/cover_reg_top/0.rom_ctrl_tl_errors.1823545252 |
|
|
Apr 15 12:26:14 PM PDT 24 |
Apr 15 12:26:41 PM PDT 24 |
2417475996 ps |