ROM_CTRL Simulation Results

Saturday October 16 2021 01:18:40 UTC

GitHub Revision: 727f1312e

Branch: master

Testplan

Simulator: VCS

Test Results

Milestone Name Tests Passing Total Pass Rate
V1 smoke rom_ctrl_smoke 50 50 100.00
V1 csr_hw_reset rom_ctrl_csr_hw_reset 5 5 100.00
V1 csr_rw rom_ctrl_csr_rw 20 20 100.00
V1 csr_bit_bash rom_ctrl_csr_bit_bash 5 5 100.00
V1 csr_aliasing rom_ctrl_csr_aliasing 5 5 100.00
V1 csr_mem_rw_with_rand_reset rom_ctrl_csr_mem_rw_with_rand_reset 20 20 100.00
V1 mem_walk rom_ctrl_mem_walk 5 5 100.00
V1 mem_partial_access rom_ctrl_mem_partial_access 5 5 100.00
V1 TOTAL 115 115 100.00
V2 multiple_reset multiple_reset 0 0 --
V2 mem_tl_errors mem_tl_errors 0 0 --
V2 alert_test rom_ctrl_alert_test 50 50 100.00
V2 tl_d_oob_addr_access rom_ctrl_tl_errors 16 20 80.00
V2 tl_d_illegal_access rom_ctrl_tl_errors 16 20 80.00
V2 tl_d_outstanding_access rom_ctrl_csr_hw_reset 5 5 100.00
rom_ctrl_csr_rw 20 20 100.00
rom_ctrl_csr_aliasing 5 5 100.00
rom_ctrl_same_csr_outstanding 20 20 100.00
V2 tl_d_partial_access rom_ctrl_csr_hw_reset 5 5 100.00
rom_ctrl_csr_rw 20 20 100.00
rom_ctrl_csr_aliasing 5 5 100.00
rom_ctrl_same_csr_outstanding 20 20 100.00
V2 TOTAL 86 90 95.56
V2S TOTAL 0 0 --
V3 ecc_mem_fault ecc_mem_fault 0 0 --
V3 tl_intg_err rom_ctrl_tl_intg_err 0 20 0.00
V3 TOTAL 0 20 0.00
Unmapped tests rom_ctrl_stress_all 0 50 0.00
rom_ctrl_stress_all_with_rand_reset 0 50 0.00
TOTAL 201 325 61.85

Testplan Progress

Items Total Written Passing Progress
N.A. 2 2 0 0.00
V1 8 8 8 100.00
V2 5 3 2 40.00
V3 2 1 0 0.00

Coverage Results

Coverage Dashboard

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP
77.47 98.54 80.25 96.47 0.00 91.23 96.74 79.07

Failure Buckets

Past Results