ROM_CTRL Lint Results

Friday June 21 2024 23:02:45 UTC

GitHub Revision: de38ce313c

Branch: os_regression

Tool: ASCENTLINT

Build Mode Flow Infos Flow Warnings Flow Errors Lint Infos Lint Warnings Lint Errors
default 0 0 0 195 0 0

Messages for Build Mode 'default'

Lint Infos

I   BLOCK_DECL:   prim_util_memload.svh:58   Declaration of 'show_mem_paths' encountered in a begin-end block                 New                            

I   FSM_DEFAULT_REQ:   prim_diff_decode.sv:158   Next state register 'gen_async.state_d' has no assignment in the default branch of the case statement for this finite state machine                 New                            

I   NESTED_SUBPROG:   prim_cipher_pkg.sv:113   Function 'prince_nibble_red16' is called from within a function                               New                            

I   NESTED_SUBPROG:   prim_cipher_pkg.sv:114   Function 'prince_nibble_red16' is called from within a function                               New                            

I   NESTED_SUBPROG:   prim_cipher_pkg.sv:115   Function 'prince_nibble_red16' is called from within a function                               New                            

I   NESTED_SUBPROG:   prim_cipher_pkg.sv:116   Function 'prince_nibble_red16' is called from within a function                               New                            

I   NESTED_SUBPROG:   prim_cipher_pkg.sv:118   Function 'prince_nibble_red16' is called from within a function                               New                            

I   NESTED_SUBPROG:   prim_cipher_pkg.sv:119   Function 'prince_nibble_red16' is called from within a function                               New                            

I   NESTED_SUBPROG:   prim_cipher_pkg.sv:120   Function 'prince_nibble_red16' is called from within a function                               New                            

I   NESTED_SUBPROG:   prim_cipher_pkg.sv:121   Function 'prince_nibble_red16' is called from within a function                               New                            

I   NESTED_SUBPROG:   prim_cipher_pkg.sv:123   Function 'prince_nibble_red16' is called from within a function                               New                            

I   NESTED_SUBPROG:   prim_cipher_pkg.sv:124   Function 'prince_nibble_red16' is called from within a function                               New                            

I   NESTED_SUBPROG:   prim_cipher_pkg.sv:125   Function 'prince_nibble_red16' is called from within a function                               New                            

I   NESTED_SUBPROG:   prim_cipher_pkg.sv:126   Function 'prince_nibble_red16' is called from within a function                               New                            

I   NESTED_SUBPROG:   prim_cipher_pkg.sv:128   Function 'prince_nibble_red16' is called from within a function                               New                            

I   NESTED_SUBPROG:   prim_cipher_pkg.sv:129   Function 'prince_nibble_red16' is called from within a function                               New                            

I   NESTED_SUBPROG:   prim_cipher_pkg.sv:130   Function 'prince_nibble_red16' is called from within a function                               New                            

I   NESTED_SUBPROG:   prim_cipher_pkg.sv:131   Function 'prince_nibble_red16' is called from within a function                               New                            

I   NESTED_SUBPROG:   prim_cipher_pkg.sv:356   Function 'sbox4_8bit' is called from within a function                                        New                            

I   NESTED_SUBPROG:   prim_mubi_pkg.sv:125     Function 'mubi4_or' is called from within a function                                          New                            

I   NESTED_SUBPROG:   tlul_pkg.sv:143          Function 'prim_mubi_pkg::mubi4_test_invalid' is called from within a function                 New                            

I   VAR_INDEX_WRITE:   prim_subst_perm.sv:69      Variable range select expression 'gen_round[0:1].data_state_sbox[k * 4 +: 4]' encountered                  New                            

I   VAR_INDEX_WRITE:   prim_cipher_pkg.sv:83      Variable range select expression 'state_out[k * 4 +: 4]' encountered                                       New                            

I   VAR_INDEX_WRITE:   prim_cipher_pkg.sv:329     Variable range select expression 'state_out[k * 4 +: 4]' encountered                                       New                            

I   VAR_INDEX_WRITE:   prim_cipher_pkg.sv:356     Variable range select expression 'state_out[k * 8 +: 8]' encountered                                       New                            

I   VAR_INDEX_WRITE:   prim_fifo_sync.sv:124      Variable index expression 'gen_normal_fifo.storage[gen_normal_fifo.fifo_wptr]' encountered                 New                            

I   VAR_INDEX_WRITE:   tlul_adapter_sram.sv:439   Variable index expression 'wmask_intg[woffset]' encountered                                                New                            

I   VAR_INDEX_WRITE:   tlul_adapter_sram.sv:440   Variable index expression 'wdata_intg[woffset]' encountered                                                New                            

I   CASE_INC:   rom_ctrl_compare.sv:90     Case statement tag not specified for value 'b00000 and 28 other values                        New                            

I   CASE_INC:   rom_ctrl_fsm.sv:144        Case statement tag not specified for value 'b0000000000 and many other values                 New                            

I   CASE_INC:   rom_ctrl_fsm.sv:154        Case statement tag not specified for value 'b00                                               New                            

I   CASE_INC:   prim_alert_sender.sv:199   Case statement tag not specified for value 'b111                                              New                            

I   CASE_INC:   prim_diff_decode.sv:115    Case statement tag not specified for value 'b11                                               New                            

I   CASE_INC:   tlul_err.sv:62             Case statement tag not specified for value 'h3                                                New                            

I   ONE_BIT_VEC:   rom_ctrl.sv:12                  Declaration range '[NumAlerts - 1:0]' ([0:0]) of 'AlertAsyncOn' has a length of one, instance 'rom_ctrl' of module 'rom_ctrl' (NumAlerts=1)                                                                                                                                                                                                                                         New                            

I   ONE_BIT_VEC:   rom_ctrl.sv:36                  Declaration range '[NumAlerts - 1:0]' ([0:0]) of 'alert_rx_i' has a length of one, instance 'rom_ctrl' of module 'rom_ctrl' (NumAlerts=1)                                                                                                                                                                                                                                           New                            

I   ONE_BIT_VEC:   rom_ctrl.sv:37                  Declaration range '[NumAlerts - 1:0]' ([0:0]) of 'alert_tx_o' has a length of one, instance 'rom_ctrl' of module 'rom_ctrl' (NumAlerts=1)                                                                                                                                                                                                                                           New                            

I   ONE_BIT_VEC:   rom_ctrl.sv:437                 Declaration range '[NumAlerts - 1:0]' ([0:0]) of 'alert_test' has a length of one, instance 'rom_ctrl' of module 'rom_ctrl' (NumAlerts=1)                                                                                                                                                                                                                                           New                            

I   ONE_BIT_VEC:   rom_ctrl.sv:441                 Declaration range '[NumAlerts - 1:0]' ([0:0]) of 'alerts' has a length of one, instance 'rom_ctrl' of module 'rom_ctrl' (NumAlerts=1)                                                                                                                                                                                                                                               New                            

I   ONE_BIT_VEC:   rom_ctrl_regs_reg_top.sv:148    Declaration range '[0:0]' of 'alert_test_flds_we' has a length of one                                                                                                                                                                                                                                                                                                               New                            

I   ONE_BIT_VEC:   prim_buf.sv:24                  Declaration range '[Width - 1:0]' ([0:0]) of 'in_i' has a length of one, instance 'rom_ctrl.gen_alert_tx[0].u_alert_sender.u_prim_buf_in_req.u_secure_anchor_buf' of module 'prim_buf' (Width=1)                                                                                                                                                                                    New                            

I   ONE_BIT_VEC:   prim_buf.sv:25                  Declaration range '[Width - 1:0]' ([0:0]) of 'out_o' has a length of one, instance 'rom_ctrl.gen_alert_tx[0].u_alert_sender.u_prim_buf_in_req.u_secure_anchor_buf' of module 'prim_buf' (Width=1)                                                                                                                                                                                   New                            

I   ONE_BIT_VEC:   prim_flop.sv:22                 Declaration range '[Width - 1:0]' ([0:0]) of 'ResetValue' has a length of one, instance 'rom_ctrl.gen_alert_tx[0].u_alert_sender.u_decode_ping.gen_async.i_sync_p.gen_generic.u_impl_generic.u_sync_1' of module 'prim_flop' (Width=1)                                                                                                                                              New                            

I   ONE_BIT_VEC:   prim_flop.sv:27                 Declaration range '[Width - 1:0]' ([0:0]) of 'd_i' has a length of one, instance 'rom_ctrl.gen_alert_tx[0].u_alert_sender.u_decode_ping.gen_async.i_sync_p.gen_generic.u_impl_generic.u_sync_1' of module 'prim_flop' (Width=1)                                                                                                                                                     New                            

I   ONE_BIT_VEC:   prim_flop.sv:28                 Declaration range '[Width - 1:0]' ([0:0]) of 'q_o' has a length of one, instance 'rom_ctrl.gen_alert_tx[0].u_alert_sender.u_decode_ping.gen_async.i_sync_p.gen_generic.u_impl_generic.u_sync_1' of module 'prim_flop' (Width=1)                                                                                                                                                     New                            

I   ONE_BIT_VEC:   prim_flop_2sync.sv:19           Declaration range '[Width - 1:0]' ([0:0]) of 'ResetValue' has a length of one, instance 'rom_ctrl.gen_alert_tx[0].u_alert_sender.u_decode_ping.gen_async.i_sync_p' of module 'prim_flop_2sync' (Width=1)                                                                                                                                                                            New                            

I   ONE_BIT_VEC:   prim_flop_2sync.sv:25           Declaration range '[Width - 1:0]' ([0:0]) of 'd_i' has a length of one, instance 'rom_ctrl.gen_alert_tx[0].u_alert_sender.u_decode_ping.gen_async.i_sync_p' of module 'prim_flop_2sync' (Width=1)                                                                                                                                                                                   New                            

I   ONE_BIT_VEC:   prim_flop_2sync.sv:26           Declaration range '[Width - 1:0]' ([0:0]) of 'q_o' has a length of one, instance 'rom_ctrl.gen_alert_tx[0].u_alert_sender.u_decode_ping.gen_async.i_sync_p' of module 'prim_flop_2sync' (Width=1)                                                                                                                                                                                   New                            

I   ONE_BIT_VEC:   prim_fifo_sync.sv:63            Declaration range '[gen_normal_fifo.PtrW - 1:0]' ([0:0]) of 'gen_normal_fifo.fifo_wptr' has a length of one, instance 'rom_ctrl.u_tl_adapter_rom.u_reqfifo' of module 'prim_fifo_sync' (Depth=2,gen_normal_fifo.PtrW=1 ('prim_util_pkg::vbits(Depth)'))                                                                                                                             New                            

I   ONE_BIT_VEC:   prim_fifo_sync_cnt.sv:25        Declaration range '[PtrW - 1:0]' ([0:0]) of 'wptr_o' has a length of one, instance 'rom_ctrl.u_tl_adapter_rom.u_reqfifo.gen_normal_fifo.u_fifo_cnt' of module 'prim_fifo_sync_cnt' (Depth=2,PtrW=1 ('prim_util_pkg::vbits(Depth)'))                                                                                                                                                 New                            

I   ONE_BIT_VEC:   prim_fifo_sync_cnt.sv:26        Declaration range '[PtrW - 1:0]' ([0:0]) of 'rptr_o' has a length of one, instance 'rom_ctrl.u_tl_adapter_rom.u_reqfifo.gen_normal_fifo.u_fifo_cnt' of module 'prim_fifo_sync_cnt' (Depth=2,PtrW=1 ('prim_util_pkg::vbits(Depth)'))                                                                                                                                                 New                            

I   ONE_BIT_VEC:   prim_generic_buf.sv:10          Declaration range '[Width - 1:0]' ([0:0]) of 'in_i' has a length of one, instance 'rom_ctrl.gen_alert_tx[0].u_alert_sender.u_prim_buf_in_req.u_secure_anchor_buf.gen_generic.u_impl_generic' of module 'prim_generic_buf' (Width=1)                                                                                                                                                 New                            

I   ONE_BIT_VEC:   prim_generic_buf.sv:11          Declaration range '[Width - 1:0]' ([0:0]) of 'out_o' has a length of one, instance 'rom_ctrl.gen_alert_tx[0].u_alert_sender.u_prim_buf_in_req.u_secure_anchor_buf.gen_generic.u_impl_generic' of module 'prim_generic_buf' (Width=1)                                                                                                                                                New                            

I   ONE_BIT_VEC:   prim_generic_buf.sv:14          Declaration range '[Width - 1:0]' ([0:0]) of 'inv' has a length of one, instance 'rom_ctrl.gen_alert_tx[0].u_alert_sender.u_prim_buf_in_req.u_secure_anchor_buf.gen_generic.u_impl_generic' of module 'prim_generic_buf' (Width=1)                                                                                                                                                  New                            

I   ONE_BIT_VEC:   prim_generic_flop.sv:9          Declaration range '[Width - 1:0]' ([0:0]) of 'ResetValue' has a length of one, instance 'rom_ctrl.gen_alert_tx[0].u_alert_sender.u_decode_ping.gen_async.i_sync_p.gen_generic.u_impl_generic.u_sync_1.gen_generic.u_impl_generic' of module 'prim_generic_flop' (Width=1)                                                                                                           New                            

I   ONE_BIT_VEC:   prim_generic_flop.sv:13         Declaration range '[Width - 1:0]' ([0:0]) of 'd_i' has a length of one, instance 'rom_ctrl.gen_alert_tx[0].u_alert_sender.u_decode_ping.gen_async.i_sync_p.gen_generic.u_impl_generic.u_sync_1.gen_generic.u_impl_generic' of module 'prim_generic_flop' (Width=1)                                                                                                                  New                            

I   ONE_BIT_VEC:   prim_generic_flop.sv:14         Declaration range '[Width - 1:0]' ([0:0]) of 'q_o' has a length of one, instance 'rom_ctrl.gen_alert_tx[0].u_alert_sender.u_decode_ping.gen_async.i_sync_p.gen_generic.u_impl_generic.u_sync_1.gen_generic.u_impl_generic' of module 'prim_generic_flop' (Width=1)                                                                                                                  New                            

I   ONE_BIT_VEC:   prim_generic_flop_2sync.sv:9    Declaration range '[Width - 1:0]' ([0:0]) of 'ResetValue' has a length of one, instance 'rom_ctrl.gen_alert_tx[0].u_alert_sender.u_decode_ping.gen_async.i_sync_p.gen_generic.u_impl_generic' of module 'prim_generic_flop_2sync' (Width=1)                                                                                                                                         New                            

I   ONE_BIT_VEC:   prim_generic_flop_2sync.sv:14   Declaration range '[Width - 1:0]' ([0:0]) of 'd_i' has a length of one, instance 'rom_ctrl.gen_alert_tx[0].u_alert_sender.u_decode_ping.gen_async.i_sync_p.gen_generic.u_impl_generic' of module 'prim_generic_flop_2sync' (Width=1)                                                                                                                                                New                            

I   ONE_BIT_VEC:   prim_generic_flop_2sync.sv:15   Declaration range '[Width - 1:0]' ([0:0]) of 'q_o' has a length of one, instance 'rom_ctrl.gen_alert_tx[0].u_alert_sender.u_decode_ping.gen_async.i_sync_p.gen_generic.u_impl_generic' of module 'prim_generic_flop_2sync' (Width=1)                                                                                                                                                New                            

I   ONE_BIT_VEC:   prim_generic_flop_2sync.sv:18   Declaration range '[Width - 1:0]' ([0:0]) of 'd_o' has a length of one, instance 'rom_ctrl.gen_alert_tx[0].u_alert_sender.u_decode_ping.gen_async.i_sync_p.gen_generic.u_impl_generic' of module 'prim_generic_flop_2sync' (Width=1)                                                                                                                                                New                            

I   ONE_BIT_VEC:   prim_generic_flop_2sync.sv:19   Declaration range '[Width - 1:0]' ([0:0]) of 'intq' has a length of one, instance 'rom_ctrl.gen_alert_tx[0].u_alert_sender.u_decode_ping.gen_async.i_sync_p.gen_generic.u_impl_generic' of module 'prim_generic_flop_2sync' (Width=1)                                                                                                                                               New                            

I   ONE_BIT_VEC:   prim_sec_anchor_buf.sv:10       Declaration range '[Width - 1:0]' ([0:0]) of 'in_i' has a length of one, instance 'rom_ctrl.gen_alert_tx[0].u_alert_sender.u_prim_buf_in_req' of module 'prim_sec_anchor_buf' (Width=1)                                                                                                                                                                                             New                            

I   ONE_BIT_VEC:   prim_sec_anchor_buf.sv:11       Declaration range '[Width - 1:0]' ([0:0]) of 'out_o' has a length of one, instance 'rom_ctrl.gen_alert_tx[0].u_alert_sender.u_prim_buf_in_req' of module 'prim_sec_anchor_buf' (Width=1)                                                                                                                                                                                            New                            

I   ONE_BIT_VEC:   prim_subreg.sv:12               Declaration range '[DW - 1:0]' ([0:0]) of 'RESVAL' has a length of one, instance 'rom_ctrl.u_reg_regs.u_fatal_alert_cause_checker_error' of module 'prim_subreg' (DW=1)                                                                                                                                                                                                             New                            

I   ONE_BIT_VEC:   prim_subreg.sv:21               Declaration range '[DW - 1:0]' ([0:0]) of 'wd' has a length of one, instance 'rom_ctrl.u_reg_regs.u_fatal_alert_cause_checker_error' of module 'prim_subreg' (DW=1)                                                                                                                                                                                                                 New                            

I   ONE_BIT_VEC:   prim_subreg.sv:25               Declaration range '[DW - 1:0]' ([0:0]) of 'd' has a length of one, instance 'rom_ctrl.u_reg_regs.u_fatal_alert_cause_checker_error' of module 'prim_subreg' (DW=1)                                                                                                                                                                                                                  New                            

I   ONE_BIT_VEC:   prim_subreg.sv:29               Declaration range '[DW - 1:0]' ([0:0]) of 'q' has a length of one, instance 'rom_ctrl.u_reg_regs.u_fatal_alert_cause_checker_error' of module 'prim_subreg' (DW=1)                                                                                                                                                                                                                  New                            

I   ONE_BIT_VEC:   prim_subreg.sv:34               Declaration range '[DW - 1:0]' ([0:0]) of 'ds' has a length of one, instance 'rom_ctrl.u_reg_regs.u_fatal_alert_cause_checker_error' of module 'prim_subreg' (DW=1)                                                                                                                                                                                                                 New                            

I   ONE_BIT_VEC:   prim_subreg.sv:35               Declaration range '[DW - 1:0]' ([0:0]) of 'qs' has a length of one, instance 'rom_ctrl.u_reg_regs.u_fatal_alert_cause_checker_error' of module 'prim_subreg' (DW=1)                                                                                                                                                                                                                 New                            

I   ONE_BIT_VEC:   prim_subreg.sv:39               Declaration range '[DW - 1:0]' ([0:0]) of 'wr_data' has a length of one, instance 'rom_ctrl.u_reg_regs.u_fatal_alert_cause_checker_error' of module 'prim_subreg' (DW=1)                                                                                                                                                                                                            New                            

I   ONE_BIT_VEC:   prim_subreg_arb.sv:17           Declaration range '[DW - 1:0]' ([0:0]) of 'wd' has a length of one, instance 'rom_ctrl.u_reg_regs.u_fatal_alert_cause_checker_error.wr_en_data_arb' of module 'prim_subreg_arb' (DW=1)                                                                                                                                                                                              New                            

I   ONE_BIT_VEC:   prim_subreg_arb.sv:21           Declaration range '[DW - 1:0]' ([0:0]) of 'd' has a length of one, instance 'rom_ctrl.u_reg_regs.u_fatal_alert_cause_checker_error.wr_en_data_arb' of module 'prim_subreg_arb' (DW=1)                                                                                                                                                                                               New                            

I   ONE_BIT_VEC:   prim_subreg_arb.sv:24           Declaration range '[DW - 1:0]' ([0:0]) of 'q' has a length of one, instance 'rom_ctrl.u_reg_regs.u_fatal_alert_cause_checker_error.wr_en_data_arb' of module 'prim_subreg_arb' (DW=1)                                                                                                                                                                                               New                            

I   ONE_BIT_VEC:   prim_subreg_arb.sv:28           Declaration range '[DW - 1:0]' ([0:0]) of 'wr_data' has a length of one, instance 'rom_ctrl.u_reg_regs.u_fatal_alert_cause_checker_error.wr_en_data_arb' of module 'prim_subreg_arb' (DW=1)                                                                                                                                                                                         New                            

I   ONE_BIT_VEC:   prim_subreg_arb.sv:47           Declaration range '[DW - 1:0]' ([0:0]) of 'gen_ro.unused_wd' has a length of one, instance 'rom_ctrl.u_reg_regs.u_fatal_alert_cause_checker_error.wr_en_data_arb' of module 'prim_subreg_arb' (DW=1)                                                                                                                                                                                New                            

I   ONE_BIT_VEC:   prim_subreg_arb.sv:48           Declaration range '[DW - 1:0]' ([0:0]) of 'gen_ro.unused_q' has a length of one, instance 'rom_ctrl.u_reg_regs.u_fatal_alert_cause_checker_error.wr_en_data_arb' of module 'prim_subreg_arb' (DW=1)                                                                                                                                                                                 New                            

I   ONE_BIT_VEC:   prim_subreg_ext.sv:12           Declaration range '[DW - 1:0]' ([0:0]) of 'wd' has a length of one, instance 'rom_ctrl.u_reg_regs.u_alert_test' of module 'prim_subreg_ext' (DW=1)                                                                                                                                                                                                                                  New                            

I   ONE_BIT_VEC:   prim_subreg_ext.sv:14           Declaration range '[DW - 1:0]' ([0:0]) of 'd' has a length of one, instance 'rom_ctrl.u_reg_regs.u_alert_test' of module 'prim_subreg_ext' (DW=1)                                                                                                                                                                                                                                   New                            

I   ONE_BIT_VEC:   prim_subreg_ext.sv:19           Declaration range '[DW - 1:0]' ([0:0]) of 'q' has a length of one, instance 'rom_ctrl.u_reg_regs.u_alert_test' of module 'prim_subreg_ext' (DW=1)                                                                                                                                                                                                                                   New                            

I   ONE_BIT_VEC:   prim_subreg_ext.sv:20           Declaration range '[DW - 1:0]' ([0:0]) of 'ds' has a length of one, instance 'rom_ctrl.u_reg_regs.u_alert_test' of module 'prim_subreg_ext' (DW=1)                                                                                                                                                                                                                                  New                            

I   ONE_BIT_VEC:   prim_subreg_ext.sv:21           Declaration range '[DW - 1:0]' ([0:0]) of 'qs' has a length of one, instance 'rom_ctrl.u_reg_regs.u_alert_test' of module 'prim_subreg_ext' (DW=1)                                                                                                                                                                                                                                  New                            

I   ONE_BIT_VEC:   tlul_adapter_sram.sv:221        Declaration range '[WoffsetWidth - 1:0]' ([0:0]) of 'sram_req_t' has a length of one, instance 'rom_ctrl.u_tl_adapter_rom' of module 'tlul_adapter_sram' (DataBitWidth=2 ('prim_util_pkg::vbits(SramByte)'),SramByte=4 ('SramDw / 8'),SramDw=32,WoffsetWidth=1 ('(SramByte == top_pkg::TL_DBW) ? 1 : DataBitWidth - prim_util_pkg::vbits(top_pkg::TL_DBW)'))                        New                            

I   ONE_BIT_VEC:   tlul_adapter_sram.sv:221        Declaration range '[WoffsetWidth - 1:0]' ([0:0]) of 'sramreqfifo_wdata' has a length of one, instance 'rom_ctrl.u_tl_adapter_rom' of module 'tlul_adapter_sram' (DataBitWidth=2 ('prim_util_pkg::vbits(SramByte)'),SramByte=4 ('SramDw / 8'),SramDw=32,WoffsetWidth=1 ('(SramByte == top_pkg::TL_DBW) ? 1 : DataBitWidth - prim_util_pkg::vbits(top_pkg::TL_DBW)'))                 New                            

I   ONE_BIT_VEC:   tlul_adapter_sram.sv:221        Declaration range '[WoffsetWidth - 1:0]' ([0:0]) of 'woffset' has a length of one, instance 'rom_ctrl.u_tl_adapter_rom' of module 'tlul_adapter_sram' (DataBitWidth=2 ('prim_util_pkg::vbits(SramByte)'),SramByte=4 ('SramDw / 8'),SramDw=32,WoffsetWidth=1 ('(SramByte == top_pkg::TL_DBW) ? 1 : DataBitWidth - prim_util_pkg::vbits(top_pkg::TL_DBW)'))                           New                            

I   ONE_BIT_VEC:   tlul_adapter_sram.sv:398        Declaration range '[WoffsetWidth - 1:0]' ([0:0]) of 'woffset' has a length of one, instance 'rom_ctrl.u_tl_adapter_rom' of module 'tlul_adapter_sram' (DataBitWidth=2 ('prim_util_pkg::vbits(SramByte)'),SramByte=4 ('SramDw / 8'),SramDw=32,WoffsetWidth=1 ('(SramByte == top_pkg::TL_DBW) ? 1 : DataBitWidth - prim_util_pkg::vbits(top_pkg::TL_DBW)'))                           New                            

I   ONE_BIT_VEC:   tlul_adapter_sram.sv:411        Declaration range '[WidthMult - 1:0]' ([0:0]) of 'wmask_combined' has a length of one, instance 'rom_ctrl.u_tl_adapter_rom' of module 'tlul_adapter_sram' (DataIntgWidth=7,DataWidth=39 ('EnableDataIntgPt ? top_pkg::TL_DW + DataIntgWidth : top_pkg::TL_DW'),EnableDataIntgPt=1'b1,SramDw=32,WidthMult=1 ('SramDw / top_pkg::TL_DW'))                                             New                            

I   ONE_BIT_VEC:   tlul_adapter_sram.sv:412        Declaration range '[WidthMult - 1:0]' ([0:0]) of 'wdata_combined' has a length of one, instance 'rom_ctrl.u_tl_adapter_rom' of module 'tlul_adapter_sram' (DataIntgWidth=7,DataWidth=39 ('EnableDataIntgPt ? top_pkg::TL_DW + DataIntgWidth : top_pkg::TL_DW'),EnableDataIntgPt=1'b1,SramDw=32,WidthMult=1 ('SramDw / top_pkg::TL_DW'))                                             New                            

I   ONE_BIT_VEC:   tlul_adapter_sram.sv:415        Declaration range '[WidthMult - 1:0]' ([0:0]) of 'wmask_int' has a length of one, instance 'rom_ctrl.u_tl_adapter_rom' of module 'tlul_adapter_sram' (SramDw=32,WidthMult=1 ('SramDw / top_pkg::TL_DW'))                                                                                                                                                                            New                            

I   ONE_BIT_VEC:   tlul_adapter_sram.sv:416        Declaration range '[WidthMult - 1:0]' ([0:0]) of 'wdata_int' has a length of one, instance 'rom_ctrl.u_tl_adapter_rom' of module 'tlul_adapter_sram' (SramDw=32,WidthMult=1 ('SramDw / top_pkg::TL_DW'))                                                                                                                                                                            New                            

I   ONE_BIT_VEC:   tlul_adapter_sram.sv:419        Declaration range '[WidthMult - 1:0]' ([0:0]) of 'wmask_intg' has a length of one, instance 'rom_ctrl.u_tl_adapter_rom' of module 'tlul_adapter_sram' (DataIntgWidth=7,SramDw=32,WidthMult=1 ('SramDw / top_pkg::TL_DW'))                                                                                                                                                           New                            

I   ONE_BIT_VEC:   tlul_adapter_sram.sv:420        Declaration range '[WidthMult - 1:0]' ([0:0]) of 'wdata_intg' has a length of one, instance 'rom_ctrl.u_tl_adapter_rom' of module 'tlul_adapter_sram' (DataIntgWidth=7,SramDw=32,WidthMult=1 ('SramDw / top_pkg::TL_DW'))                                                                                                                                                           New                            

I   ONE_BIT_VEC:   tlul_adapter_sram.sv:482        Declaration range '[WidthMult - 1:0]' ([0:0]) of 'rdata_reshaped' has a length of one, instance 'rom_ctrl.u_tl_adapter_rom' of module 'tlul_adapter_sram' (DataIntgWidth=7,DataWidth=39 ('EnableDataIntgPt ? top_pkg::TL_DW + DataIntgWidth : top_pkg::TL_DW'),EnableDataIntgPt=1'b1,SramDw=32,WidthMult=1 ('SramDw / top_pkg::TL_DW'))                                             New                            

I   ONE_BIT_VEC:   tlul_pkg.sv:111                 Declaration range '[top_pkg::TL_DIW - 1:0]' ([0:0]) of 'd_sink' has a length of one                                                                                                                                                                                                                                                                                                 New                            

I   ONE_BIT_VEC:   tlul_pkg.sv:111                 Declaration range '[top_pkg::TL_DIW - 1:0]' ([0:0]) of 'regs_tl_o' has a length of one                                                                                                                                                                                                                                                                                              New                            

I   ONE_BIT_VEC:   tlul_pkg.sv:111                 Declaration range '[top_pkg::TL_DIW - 1:0]' ([0:0]) of 'rom_tl_o' has a length of one                                                                                                                                                                                                                                                                                               New                            

I   ONE_BIT_VEC:   tlul_pkg.sv:111                 Declaration range '[top_pkg::TL_DIW - 1:0]' ([0:0]) of 'tl' has a length of one                                                                                                                                                                                                                                                                                                     New                            

I   ONE_BIT_VEC:   tlul_pkg.sv:111                 Declaration range '[top_pkg::TL_DIW - 1:0]' ([0:0]) of 'tl_d2h_t' has a length of one                                                                                                                                                                                                                                                                                               New                            

I   ONE_BIT_VEC:   tlul_pkg.sv:111                 Declaration range '[top_pkg::TL_DIW - 1:0]' ([0:0]) of 'tl_i' has a length of one                                                                                                                                                                                                                                                                                                   New                            

I   ONE_BIT_VEC:   tlul_pkg.sv:111                 Declaration range '[top_pkg::TL_DIW - 1:0]' ([0:0]) of 'tl_o' has a length of one                                                                                                                                                                                                                                                                                                   New                            

I   ONE_BIT_VEC:   tlul_pkg.sv:111                 Declaration range '[top_pkg::TL_DIW - 1:0]' ([0:0]) of 'tl_o_int' has a length of one                                                                                                                                                                                                                                                                                               New                            

I   ONE_BIT_VEC:   tlul_pkg.sv:111                 Declaration range '[top_pkg::TL_DIW - 1:0]' ([0:0]) of 'tl_o_pre' has a length of one                                                                                                                                                                                                                                                                                               New                            

I   ONE_BIT_VEC:   tlul_pkg.sv:111                 Declaration range '[top_pkg::TL_DIW - 1:0]' ([0:0]) of 'tl_out' has a length of one                                                                                                                                                                                                                                                                                                 New                            

I   ONE_BIT_VEC:   tlul_pkg.sv:111                 Declaration range '[top_pkg::TL_DIW - 1:0]' ([0:0]) of 'tl_reg_d2h' has a length of one                                                                                                                                                                                                                                                                                             New                            

I   ONE_BIT_VEC:   tlul_pkg.sv:111                 Declaration range '[top_pkg::TL_DIW - 1:0]' ([0:0]) of 'tl_sram_i' has a length of one                                                                                                                                                                                                                                                                                              New                            

I   EXPLICIT_BITLEN:   rom_ctrl_compare.sv:139    Bit length not specified for constant '1'                   New                            

I   EXPLICIT_BITLEN:   rom_ctrl_fsm.sv:266        Bit length not specified for constant '1'                   New                            

I   EXPLICIT_BITLEN:   prim_fifo_sync_cnt.sv:51   Bit length not specified for constant '1'                   New                            

I   EXPLICIT_BITLEN:   prim_fifo_sync_cnt.sv:52   Bit length not specified for constant '1'                   New                            

I   EXPLICIT_BITLEN:   prim_util_pkg.sv:85        Bit length not specified for constant '1'                   New                            

I   EXPLICIT_BITLEN:   tlul_sram_byte.sv:297      Bit length not specified for constant '1'                   New                            

I   EXPLICIT_BITLEN:   tlul_sram_byte.sv:330      Bit length not specified for constant '1'                   New                            

I   EXPLICIT_BITLEN:   tlul_sram_byte.sv:395      Bit length not specified for constant '1'                   New                            

I   EXPLICIT_BITLEN:   tlul_sram_byte.sv:459      Bit length not specified for constant '1'                   New                            

I   EXPLICIT_BITLEN:   tlul_err.sv:69             Bit length not specified for constant "'h1"                 New                            

I   EXPLICIT_BITLEN:   tlul_err.sv:77             Bit length not specified for constant "'h2"                 New                            

I   INSIDE_OP_CONTEXT:   rom_ctrl_fsm.sv:277        'inside' operator is not within an always block or subprogram                 New                            

I   INSIDE_OP_CONTEXT:   tlul_adapter_sram.sv:392   'inside' operator is not within an always block or subprogram                 New                            

I   MIN_NAME_LEN:   rom_ctrl_reg_pkg.sv:21     Name 'q' is shorter than minimum length 2                 New                            

I   MIN_NAME_LEN:   rom_ctrl_reg_pkg.sv:26     Name 'q' is shorter than minimum length 2                 New                            

I   MIN_NAME_LEN:   rom_ctrl_reg_pkg.sv:30     Name 'q' is shorter than minimum length 2                 New                            

I   MIN_NAME_LEN:   rom_ctrl_reg_pkg.sv:35     Name 'd' is shorter than minimum length 2                 New                            

I   MIN_NAME_LEN:   rom_ctrl_reg_pkg.sv:39     Name 'd' is shorter than minimum length 2                 New                            

I   MIN_NAME_LEN:   rom_ctrl_reg_pkg.sv:45     Name 'd' is shorter than minimum length 2                 New                            

I   MIN_NAME_LEN:   rom_ctrl_reg_pkg.sv:50     Name 'd' is shorter than minimum length 2                 New                            

I   MIN_NAME_LEN:   prim_subst_perm.sv:46      Name 'k' is shorter than minimum length 2                 New                            

I   MIN_NAME_LEN:   prim_subst_perm.sv:51      Name 'k' is shorter than minimum length 2                 New                            

I   MIN_NAME_LEN:   prim_subst_perm.sv:55      Name 'k' is shorter than minimum length 2                 New                            

I   MIN_NAME_LEN:   prim_subst_perm.sv:68      Name 'k' is shorter than minimum length 2                 New                            

I   MIN_NAME_LEN:   prim_subst_perm.sv:72      Name 'k' is shorter than minimum length 2                 New                            

I   MIN_NAME_LEN:   prim_subst_perm.sv:79      Name 'k' is shorter than minimum length 2                 New                            

I   MIN_NAME_LEN:   prim_cipher_pkg.sv:71      Name 'k' is shorter than minimum length 2                 New                            

I   MIN_NAME_LEN:   prim_cipher_pkg.sv:82      Name 'k' is shorter than minimum length 2                 New                            

I   MIN_NAME_LEN:   prim_cipher_pkg.sv:328     Name 'k' is shorter than minimum length 2                 New                            

I   MIN_NAME_LEN:   prim_cipher_pkg.sv:346     Name 'k' is shorter than minimum length 2                 New                            

I   MIN_NAME_LEN:   prim_cipher_pkg.sv:355     Name 'k' is shorter than minimum length 2                 New                            

I   MIN_NAME_LEN:   prim_mubi_pkg.sv:80        Name 'a' is shorter than minimum length 2                 New                            

I   MIN_NAME_LEN:   prim_mubi_pkg.sv:80        Name 'b' is shorter than minimum length 2                 New                            

I   MIN_NAME_LEN:   prim_mubi_pkg.sv:85        Name 'k' is shorter than minimum length 2                 New                            

I   MIN_NAME_LEN:   prim_mubi_pkg.sv:106       Name 'a' is shorter than minimum length 2                 New                            

I   MIN_NAME_LEN:   prim_mubi_pkg.sv:106       Name 'b' is shorter than minimum length 2                 New                            

I   MIN_NAME_LEN:   prim_mubi_pkg.sv:111       Name 'k' is shorter than minimum length 2                 New                            

I   MIN_NAME_LEN:   prim_mubi_pkg.sv:124       Name 'a' is shorter than minimum length 2                 New                            

I   MIN_NAME_LEN:   prim_mubi_pkg.sv:124       Name 'b' is shorter than minimum length 2                 New                            

I   MIN_NAME_LEN:   prim_mubi_pkg.sv:131       Name 'a' is shorter than minimum length 2                 New                            

I   MIN_NAME_LEN:   prim_mubi_pkg.sv:131       Name 'b' is shorter than minimum length 2                 New                            

I   MIN_NAME_LEN:   prim_mubi_pkg.sv:212       Name 'a' is shorter than minimum length 2                 New                            

I   MIN_NAME_LEN:   prim_mubi_pkg.sv:212       Name 'b' is shorter than minimum length 2                 New                            

I   MIN_NAME_LEN:   prim_mubi_pkg.sv:217       Name 'k' is shorter than minimum length 2                 New                            

I   MIN_NAME_LEN:   prim_mubi_pkg.sv:238       Name 'a' is shorter than minimum length 2                 New                            

I   MIN_NAME_LEN:   prim_mubi_pkg.sv:238       Name 'b' is shorter than minimum length 2                 New                            

I   MIN_NAME_LEN:   prim_mubi_pkg.sv:243       Name 'k' is shorter than minimum length 2                 New                            

I   MIN_NAME_LEN:   prim_mubi_pkg.sv:256       Name 'a' is shorter than minimum length 2                 New                            

I   MIN_NAME_LEN:   prim_mubi_pkg.sv:256       Name 'b' is shorter than minimum length 2                 New                            

I   MIN_NAME_LEN:   prim_mubi_pkg.sv:263       Name 'a' is shorter than minimum length 2                 New                            

I   MIN_NAME_LEN:   prim_mubi_pkg.sv:263       Name 'b' is shorter than minimum length 2                 New                            

I   MIN_NAME_LEN:   prim_mubi_pkg.sv:344       Name 'a' is shorter than minimum length 2                 New                            

I   MIN_NAME_LEN:   prim_mubi_pkg.sv:344       Name 'b' is shorter than minimum length 2                 New                            

I   MIN_NAME_LEN:   prim_mubi_pkg.sv:349       Name 'k' is shorter than minimum length 2                 New                            

I   MIN_NAME_LEN:   prim_mubi_pkg.sv:370       Name 'a' is shorter than minimum length 2                 New                            

I   MIN_NAME_LEN:   prim_mubi_pkg.sv:370       Name 'b' is shorter than minimum length 2                 New                            

I   MIN_NAME_LEN:   prim_mubi_pkg.sv:375       Name 'k' is shorter than minimum length 2                 New                            

I   MIN_NAME_LEN:   prim_mubi_pkg.sv:388       Name 'a' is shorter than minimum length 2                 New                            

I   MIN_NAME_LEN:   prim_mubi_pkg.sv:388       Name 'b' is shorter than minimum length 2                 New                            

I   MIN_NAME_LEN:   prim_mubi_pkg.sv:395       Name 'a' is shorter than minimum length 2                 New                            

I   MIN_NAME_LEN:   prim_mubi_pkg.sv:395       Name 'b' is shorter than minimum length 2                 New                            

I   MIN_NAME_LEN:   prim_mubi_pkg.sv:476       Name 'a' is shorter than minimum length 2                 New                            

I   MIN_NAME_LEN:   prim_mubi_pkg.sv:476       Name 'b' is shorter than minimum length 2                 New                            

I   MIN_NAME_LEN:   prim_mubi_pkg.sv:481       Name 'k' is shorter than minimum length 2                 New                            

I   MIN_NAME_LEN:   prim_mubi_pkg.sv:502       Name 'a' is shorter than minimum length 2                 New                            

I   MIN_NAME_LEN:   prim_mubi_pkg.sv:502       Name 'b' is shorter than minimum length 2                 New                            

I   MIN_NAME_LEN:   prim_mubi_pkg.sv:507       Name 'k' is shorter than minimum length 2                 New                            

I   MIN_NAME_LEN:   prim_mubi_pkg.sv:520       Name 'a' is shorter than minimum length 2                 New                            

I   MIN_NAME_LEN:   prim_mubi_pkg.sv:520       Name 'b' is shorter than minimum length 2                 New                            

I   MIN_NAME_LEN:   prim_mubi_pkg.sv:527       Name 'a' is shorter than minimum length 2                 New                            

I   MIN_NAME_LEN:   prim_mubi_pkg.sv:527       Name 'b' is shorter than minimum length 2                 New                            

I   MIN_NAME_LEN:   prim_subreg.sv:25          Name 'd' is shorter than minimum length 2                 New                            

I   MIN_NAME_LEN:   prim_subreg.sv:29          Name 'q' is shorter than minimum length 2                 New                            

I   MIN_NAME_LEN:   prim_subreg_arb.sv:21      Name 'd' is shorter than minimum length 2                 New                            

I   MIN_NAME_LEN:   prim_subreg_arb.sv:24      Name 'q' is shorter than minimum length 2                 New                            

I   MIN_NAME_LEN:   prim_subreg_ext.sv:14      Name 'd' is shorter than minimum length 2                 New                            

I   MIN_NAME_LEN:   prim_subreg_ext.sv:19      Name 'q' is shorter than minimum length 2                 New                            

I   MIN_NAME_LEN:   tlul_adapter_sram.sv:427   Name 'i' is shorter than minimum length 2                 New                            

I   MIN_NAME_LEN:   tlul_adapter_sram.sv:518   Name 'i' is shorter than minimum length 2                 New                            

I   MIN_NAME_LEN:   tlul_sram_byte.sv:553      Name 'i' is shorter than minimum length 2                 New                            

I   STRING_VAL:   prim_util_memload.svh:64   Parameter 'MemInitFile' with string value "" used as a constant, instance 'rom_ctrl.gen_rom_scramble_enabled.u_rom.u_rom.u_prim_rom.gen_generic.u_impl_generic' of module 'prim_generic_rom' (MemInitFile="")                 New                            

I   STRING_VAL:   prim_util_memload.svh:64   String value "" used as a constant                                                                                                                                                                                            New                            

I   CONST_OUTPUT:   rom_ctrl.sv:120            Output 'kmac_data_o.data[63:39]' is driven by constant zeros                                                                                                                                                                                                                              New                            

I   CONST_OUTPUT:   rom_ctrl.sv:120            Output 'kmac_data_o.strb' is driven by constant 8'b00011111                                                                                                                                                                                                                               New                            

I   CONST_OUTPUT:   tlul_adapter_reg.sv:91     Output 'addr_o[1:0]' is driven by constant zeros in module 'tlul_adapter_reg' (RegAw=7)                                                                                                                                                                                                   New                            

I   CONST_OUTPUT:   tlul_adapter_reg.sv:195    Output 'intg_error_o' is driven by constant zero in module 'tlul_adapter_reg' (RegAw=7)                                                                                                                                                                                                   New                            

I   CONST_OUTPUT:   tlul_adapter_sram.sv:114   Output 'readback_error_o' is driven by constant zero in module 'tlul_adapter_sram' (SramAw=32'hd,Outstanding=2,ByteAccess=0,ErrOnWrite=1,CmdIntgCheck=1,EnableRspIntgGen=1,EnableDataIntgPt=1'h1,SecFifoPtr=1)                                                                            New                            

I   CONST_OUTPUT:   tlul_adapter_sram.sv:199   Output 'compound_txn_in_progress_o' is driven by constant zero by port 'u_sram_byte.compound_txn_in_progress_o' in module 'tlul_adapter_sram' (SramAw=32'hd,Outstanding=2,ByteAccess=0,ErrOnWrite=1,CmdIntgCheck=1,EnableRspIntgGen=1,EnableDataIntgPt=1'h1,SecFifoPtr=1)                 New                            

I   CONST_OUTPUT:   tlul_sram_byte.sv:705      Output 'alert_o' is driven by constant zero in module 'tlul_sram_byte' (Outstanding=2)                                                                                                                                                                                                    New                            

I   CONST_OUTPUT:   tlul_sram_byte.sv:706      Output 'compound_txn_in_progress_o' is driven by constant zero in module 'tlul_sram_byte' (Outstanding=2)                                                                                                                                                                                 New                            

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