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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
97.59 96.97 93.01 97.88 100.00 98.37 98.04 98.83


Total test records in report: 462
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html
T303 /workspace/coverage/default/39.rom_ctrl_max_throughput_chk.2421154720 Apr 21 12:24:25 PM PDT 24 Apr 21 12:24:42 PM PDT 24 2137635447 ps
T304 /workspace/coverage/default/5.rom_ctrl_max_throughput_chk.3977799341 Apr 21 12:23:36 PM PDT 24 Apr 21 12:23:49 PM PDT 24 5467295226 ps
T305 /workspace/coverage/default/29.rom_ctrl_alert_test.3144111718 Apr 21 12:24:27 PM PDT 24 Apr 21 12:24:35 PM PDT 24 347018377 ps
T306 /workspace/coverage/default/42.rom_ctrl_alert_test.2636917410 Apr 21 12:24:53 PM PDT 24 Apr 21 12:24:58 PM PDT 24 332990954 ps
T307 /workspace/coverage/default/4.rom_ctrl_alert_test.3074412665 Apr 21 12:23:30 PM PDT 24 Apr 21 12:23:34 PM PDT 24 334318810 ps
T308 /workspace/coverage/default/13.rom_ctrl_alert_test.3015929933 Apr 21 12:23:57 PM PDT 24 Apr 21 12:24:14 PM PDT 24 40790343717 ps
T38 /workspace/coverage/default/0.rom_ctrl_sec_cm.1693864249 Apr 21 12:24:09 PM PDT 24 Apr 21 12:25:48 PM PDT 24 473403262 ps
T309 /workspace/coverage/default/43.rom_ctrl_kmac_err_chk.3107234074 Apr 21 12:24:34 PM PDT 24 Apr 21 12:24:59 PM PDT 24 15181738227 ps
T310 /workspace/coverage/default/39.rom_ctrl_alert_test.3126218318 Apr 21 12:24:38 PM PDT 24 Apr 21 12:24:52 PM PDT 24 22851479398 ps
T311 /workspace/coverage/default/3.rom_ctrl_kmac_err_chk.3030864131 Apr 21 12:23:45 PM PDT 24 Apr 21 12:23:54 PM PDT 24 173770707 ps
T312 /workspace/coverage/default/44.rom_ctrl_max_throughput_chk.3773420139 Apr 21 12:24:49 PM PDT 24 Apr 21 12:24:58 PM PDT 24 1932822845 ps
T313 /workspace/coverage/default/40.rom_ctrl_alert_test.2235502559 Apr 21 12:24:38 PM PDT 24 Apr 21 12:24:42 PM PDT 24 518520187 ps
T132 /workspace/coverage/default/32.rom_ctrl_stress_all_with_rand_reset.561509292 Apr 21 12:25:00 PM PDT 24 Apr 21 01:01:07 PM PDT 24 61377314663 ps
T314 /workspace/coverage/default/37.rom_ctrl_max_throughput_chk.4204336830 Apr 21 12:24:44 PM PDT 24 Apr 21 12:25:01 PM PDT 24 7763074793 ps
T315 /workspace/coverage/default/16.rom_ctrl_stress_all.1526523048 Apr 21 12:24:07 PM PDT 24 Apr 21 12:24:24 PM PDT 24 1773288634 ps
T316 /workspace/coverage/default/21.rom_ctrl_corrupt_sig_fatal_chk.3002785735 Apr 21 12:24:13 PM PDT 24 Apr 21 12:27:25 PM PDT 24 41631209837 ps
T317 /workspace/coverage/default/9.rom_ctrl_max_throughput_chk.1373116583 Apr 21 12:23:57 PM PDT 24 Apr 21 12:24:13 PM PDT 24 3715297301 ps
T318 /workspace/coverage/default/23.rom_ctrl_stress_all.1396610497 Apr 21 12:24:03 PM PDT 24 Apr 21 12:24:25 PM PDT 24 5918444732 ps
T24 /workspace/coverage/default/23.rom_ctrl_corrupt_sig_fatal_chk.1000551735 Apr 21 12:24:06 PM PDT 24 Apr 21 12:30:31 PM PDT 24 43051110828 ps
T319 /workspace/coverage/default/3.rom_ctrl_alert_test.2394040403 Apr 21 12:23:37 PM PDT 24 Apr 21 12:23:49 PM PDT 24 5477440438 ps
T320 /workspace/coverage/default/7.rom_ctrl_stress_all.3742551696 Apr 21 12:23:37 PM PDT 24 Apr 21 12:23:47 PM PDT 24 199030066 ps
T321 /workspace/coverage/default/24.rom_ctrl_alert_test.718454719 Apr 21 12:24:30 PM PDT 24 Apr 21 12:24:39 PM PDT 24 4119864274 ps
T322 /workspace/coverage/default/41.rom_ctrl_smoke.562759341 Apr 21 12:24:51 PM PDT 24 Apr 21 12:25:14 PM PDT 24 29764416357 ps
T323 /workspace/coverage/default/7.rom_ctrl_alert_test.3056159280 Apr 21 12:23:39 PM PDT 24 Apr 21 12:23:55 PM PDT 24 7711410965 ps
T324 /workspace/coverage/default/39.rom_ctrl_smoke.1055678190 Apr 21 12:24:35 PM PDT 24 Apr 21 12:24:46 PM PDT 24 190305990 ps
T325 /workspace/coverage/default/39.rom_ctrl_kmac_err_chk.2635778759 Apr 21 12:24:19 PM PDT 24 Apr 21 12:24:38 PM PDT 24 7767103429 ps
T326 /workspace/coverage/default/35.rom_ctrl_stress_all_with_rand_reset.4083848289 Apr 21 12:24:37 PM PDT 24 Apr 21 01:00:09 PM PDT 24 316888140120 ps
T327 /workspace/coverage/default/29.rom_ctrl_stress_all.2396385865 Apr 21 12:24:29 PM PDT 24 Apr 21 12:25:54 PM PDT 24 120521950828 ps
T328 /workspace/coverage/default/16.rom_ctrl_corrupt_sig_fatal_chk.3082482944 Apr 21 12:24:01 PM PDT 24 Apr 21 12:25:37 PM PDT 24 1739216510 ps
T329 /workspace/coverage/default/45.rom_ctrl_stress_all.3812252569 Apr 21 12:24:59 PM PDT 24 Apr 21 12:25:27 PM PDT 24 1878544687 ps
T330 /workspace/coverage/default/3.rom_ctrl_corrupt_sig_fatal_chk.3822468537 Apr 21 12:24:08 PM PDT 24 Apr 21 12:27:59 PM PDT 24 89092866572 ps
T331 /workspace/coverage/default/42.rom_ctrl_max_throughput_chk.1114203369 Apr 21 12:24:55 PM PDT 24 Apr 21 12:25:14 PM PDT 24 2178680668 ps
T332 /workspace/coverage/default/11.rom_ctrl_smoke.51890135 Apr 21 12:23:47 PM PDT 24 Apr 21 12:24:02 PM PDT 24 526892589 ps
T333 /workspace/coverage/default/34.rom_ctrl_alert_test.886562556 Apr 21 12:24:24 PM PDT 24 Apr 21 12:24:28 PM PDT 24 85632022 ps
T334 /workspace/coverage/default/35.rom_ctrl_stress_all.3517613567 Apr 21 12:24:29 PM PDT 24 Apr 21 12:25:12 PM PDT 24 59078426818 ps
T335 /workspace/coverage/default/22.rom_ctrl_alert_test.3920266751 Apr 21 12:24:19 PM PDT 24 Apr 21 12:24:30 PM PDT 24 4421853391 ps
T336 /workspace/coverage/default/30.rom_ctrl_smoke.3421253951 Apr 21 12:24:09 PM PDT 24 Apr 21 12:24:47 PM PDT 24 31584211206 ps
T337 /workspace/coverage/default/17.rom_ctrl_smoke.532377528 Apr 21 12:24:25 PM PDT 24 Apr 21 12:25:01 PM PDT 24 44163918262 ps
T338 /workspace/coverage/default/14.rom_ctrl_smoke.1912030298 Apr 21 12:23:59 PM PDT 24 Apr 21 12:24:09 PM PDT 24 1495058480 ps
T339 /workspace/coverage/default/11.rom_ctrl_stress_all.2461765245 Apr 21 12:23:55 PM PDT 24 Apr 21 12:25:29 PM PDT 24 21145067739 ps
T340 /workspace/coverage/default/49.rom_ctrl_corrupt_sig_fatal_chk.2533123950 Apr 21 12:24:55 PM PDT 24 Apr 21 12:30:04 PM PDT 24 26784570854 ps
T341 /workspace/coverage/default/32.rom_ctrl_alert_test.2052811036 Apr 21 12:24:16 PM PDT 24 Apr 21 12:24:21 PM PDT 24 86261273 ps
T342 /workspace/coverage/default/30.rom_ctrl_alert_test.789669397 Apr 21 12:24:53 PM PDT 24 Apr 21 12:24:58 PM PDT 24 278216178 ps
T343 /workspace/coverage/default/20.rom_ctrl_smoke.3923955803 Apr 21 12:24:16 PM PDT 24 Apr 21 12:24:33 PM PDT 24 5648577330 ps
T344 /workspace/coverage/default/8.rom_ctrl_smoke.3519398579 Apr 21 12:23:34 PM PDT 24 Apr 21 12:23:44 PM PDT 24 183304286 ps
T345 /workspace/coverage/default/32.rom_ctrl_smoke.3243708535 Apr 21 12:24:56 PM PDT 24 Apr 21 12:25:30 PM PDT 24 4269067217 ps
T346 /workspace/coverage/default/34.rom_ctrl_max_throughput_chk.640847379 Apr 21 12:24:39 PM PDT 24 Apr 21 12:24:49 PM PDT 24 2775498396 ps
T347 /workspace/coverage/default/19.rom_ctrl_max_throughput_chk.1971244641 Apr 21 12:24:10 PM PDT 24 Apr 21 12:24:23 PM PDT 24 2349013386 ps
T348 /workspace/coverage/default/18.rom_ctrl_stress_all.680906427 Apr 21 12:23:55 PM PDT 24 Apr 21 12:24:28 PM PDT 24 2140773105 ps
T349 /workspace/coverage/default/40.rom_ctrl_smoke.1594113586 Apr 21 12:24:35 PM PDT 24 Apr 21 12:25:17 PM PDT 24 4140273529 ps
T350 /workspace/coverage/default/3.rom_ctrl_smoke.2719086520 Apr 21 12:23:35 PM PDT 24 Apr 21 12:23:52 PM PDT 24 2429074391 ps
T351 /workspace/coverage/default/46.rom_ctrl_smoke.338516069 Apr 21 12:24:40 PM PDT 24 Apr 21 12:25:05 PM PDT 24 6949284241 ps
T352 /workspace/coverage/default/11.rom_ctrl_corrupt_sig_fatal_chk.3027083901 Apr 21 12:23:56 PM PDT 24 Apr 21 12:25:12 PM PDT 24 4073124328 ps
T353 /workspace/coverage/default/15.rom_ctrl_kmac_err_chk.60378484 Apr 21 12:24:13 PM PDT 24 Apr 21 12:24:48 PM PDT 24 25163308863 ps
T354 /workspace/coverage/default/25.rom_ctrl_corrupt_sig_fatal_chk.2130369666 Apr 21 12:24:17 PM PDT 24 Apr 21 12:27:00 PM PDT 24 3166027971 ps
T355 /workspace/coverage/default/36.rom_ctrl_corrupt_sig_fatal_chk.730489127 Apr 21 12:24:15 PM PDT 24 Apr 21 12:29:07 PM PDT 24 28350769319 ps
T356 /workspace/coverage/default/32.rom_ctrl_kmac_err_chk.2172291350 Apr 21 12:24:25 PM PDT 24 Apr 21 12:24:49 PM PDT 24 10197014927 ps
T357 /workspace/coverage/default/4.rom_ctrl_kmac_err_chk.946099920 Apr 21 12:23:42 PM PDT 24 Apr 21 12:24:08 PM PDT 24 11553273998 ps
T358 /workspace/coverage/default/44.rom_ctrl_smoke.3895399603 Apr 21 12:24:33 PM PDT 24 Apr 21 12:24:54 PM PDT 24 6138876616 ps
T359 /workspace/coverage/default/9.rom_ctrl_corrupt_sig_fatal_chk.2831739536 Apr 21 12:23:36 PM PDT 24 Apr 21 12:27:58 PM PDT 24 28579588603 ps
T360 /workspace/coverage/default/26.rom_ctrl_max_throughput_chk.1033018476 Apr 21 12:24:51 PM PDT 24 Apr 21 12:24:57 PM PDT 24 98038304 ps
T361 /workspace/coverage/default/8.rom_ctrl_corrupt_sig_fatal_chk.996778196 Apr 21 12:23:40 PM PDT 24 Apr 21 12:26:07 PM PDT 24 4769788848 ps
T362 /workspace/coverage/default/5.rom_ctrl_kmac_err_chk.442179191 Apr 21 12:23:57 PM PDT 24 Apr 21 12:24:07 PM PDT 24 327821535 ps
T363 /workspace/coverage/default/5.rom_ctrl_corrupt_sig_fatal_chk.4057569071 Apr 21 12:23:38 PM PDT 24 Apr 21 12:25:15 PM PDT 24 3319063854 ps
T364 /workspace/coverage/default/16.rom_ctrl_kmac_err_chk.150807191 Apr 21 12:24:06 PM PDT 24 Apr 21 12:24:23 PM PDT 24 1153702942 ps
T365 /workspace/coverage/default/45.rom_ctrl_alert_test.1171957217 Apr 21 12:24:35 PM PDT 24 Apr 21 12:24:44 PM PDT 24 6843977969 ps
T366 /workspace/coverage/default/48.rom_ctrl_stress_all.1863440771 Apr 21 12:24:38 PM PDT 24 Apr 21 12:25:20 PM PDT 24 4955221217 ps
T367 /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_errors.2399134394 Apr 21 12:38:22 PM PDT 24 Apr 21 12:38:31 PM PDT 24 532594353 ps
T62 /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_rw.23591880 Apr 21 12:38:19 PM PDT 24 Apr 21 12:38:26 PM PDT 24 1508278075 ps
T63 /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_mem_rw_with_rand_reset.1817197081 Apr 21 12:38:05 PM PDT 24 Apr 21 12:38:22 PM PDT 24 3990164079 ps
T64 /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_rw.1071441467 Apr 21 12:38:32 PM PDT 24 Apr 21 12:38:49 PM PDT 24 2198969734 ps
T69 /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_rw.3604863573 Apr 21 12:38:22 PM PDT 24 Apr 21 12:38:30 PM PDT 24 1701982122 ps
T368 /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_errors.590200140 Apr 21 12:38:00 PM PDT 24 Apr 21 12:38:15 PM PDT 24 1912893536 ps
T70 /workspace/coverage/cover_reg_top/3.rom_ctrl_passthru_mem_tl_intg_err.315281344 Apr 21 12:37:57 PM PDT 24 Apr 21 12:38:50 PM PDT 24 6008666049 ps
T111 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_aliasing.924694438 Apr 21 12:38:18 PM PDT 24 Apr 21 12:38:26 PM PDT 24 2307117949 ps
T112 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_rw.2871297341 Apr 21 12:38:08 PM PDT 24 Apr 21 12:38:13 PM PDT 24 88174847 ps
T71 /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_rw.1674338736 Apr 21 12:38:36 PM PDT 24 Apr 21 12:38:45 PM PDT 24 726108494 ps
T369 /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_partial_access.55530800 Apr 21 12:37:46 PM PDT 24 Apr 21 12:37:54 PM PDT 24 461837844 ps
T59 /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_intg_err.3689811813 Apr 21 12:38:25 PM PDT 24 Apr 21 12:39:02 PM PDT 24 468522729 ps
T370 /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_partial_access.1448813843 Apr 21 12:38:27 PM PDT 24 Apr 21 12:38:32 PM PDT 24 114484519 ps
T72 /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_rw.1943542025 Apr 21 12:38:15 PM PDT 24 Apr 21 12:38:22 PM PDT 24 1200075332 ps
T60 /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_intg_err.472383957 Apr 21 12:38:01 PM PDT 24 Apr 21 12:39:15 PM PDT 24 2137634995 ps
T106 /workspace/coverage/cover_reg_top/11.rom_ctrl_same_csr_outstanding.1632281984 Apr 21 12:38:25 PM PDT 24 Apr 21 12:38:41 PM PDT 24 5994959471 ps
T61 /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_intg_err.3111874480 Apr 21 12:38:20 PM PDT 24 Apr 21 12:39:31 PM PDT 24 1764025964 ps
T118 /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_intg_err.2566309105 Apr 21 12:38:13 PM PDT 24 Apr 21 12:39:31 PM PDT 24 11857396206 ps
T371 /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_partial_access.2050790386 Apr 21 12:38:02 PM PDT 24 Apr 21 12:38:16 PM PDT 24 3278640956 ps
T73 /workspace/coverage/cover_reg_top/8.rom_ctrl_passthru_mem_tl_intg_err.4028474274 Apr 21 12:38:04 PM PDT 24 Apr 21 12:38:32 PM PDT 24 550189831 ps
T372 /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_walk.4075412800 Apr 21 12:38:06 PM PDT 24 Apr 21 12:38:10 PM PDT 24 88978272 ps
T373 /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_errors.4097808204 Apr 21 12:38:30 PM PDT 24 Apr 21 12:38:44 PM PDT 24 838029710 ps
T374 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_hw_reset.2031863932 Apr 21 12:38:36 PM PDT 24 Apr 21 12:38:49 PM PDT 24 945060065 ps
T375 /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_mem_rw_with_rand_reset.715465490 Apr 21 12:38:16 PM PDT 24 Apr 21 12:38:26 PM PDT 24 3268667691 ps
T121 /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_intg_err.1432735221 Apr 21 12:38:12 PM PDT 24 Apr 21 12:38:59 PM PDT 24 3576405080 ps
T119 /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_intg_err.339182198 Apr 21 12:37:57 PM PDT 24 Apr 21 12:39:22 PM PDT 24 2156591038 ps
T74 /workspace/coverage/cover_reg_top/10.rom_ctrl_passthru_mem_tl_intg_err.2853834196 Apr 21 12:38:16 PM PDT 24 Apr 21 12:38:45 PM PDT 24 2103273163 ps
T116 /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_intg_err.2037098595 Apr 21 12:38:11 PM PDT 24 Apr 21 12:39:23 PM PDT 24 1945805886 ps
T107 /workspace/coverage/cover_reg_top/17.rom_ctrl_same_csr_outstanding.1902775419 Apr 21 12:38:24 PM PDT 24 Apr 21 12:38:28 PM PDT 24 168143832 ps
T376 /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_errors.946902681 Apr 21 12:38:19 PM PDT 24 Apr 21 12:38:31 PM PDT 24 2237506124 ps
T108 /workspace/coverage/cover_reg_top/6.rom_ctrl_same_csr_outstanding.93199098 Apr 21 12:38:26 PM PDT 24 Apr 21 12:38:37 PM PDT 24 989231277 ps
T109 /workspace/coverage/cover_reg_top/11.rom_ctrl_passthru_mem_tl_intg_err.873648091 Apr 21 12:38:26 PM PDT 24 Apr 21 12:40:03 PM PDT 24 34514351570 ps
T377 /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_errors.1858454731 Apr 21 12:38:24 PM PDT 24 Apr 21 12:38:42 PM PDT 24 10376512276 ps
T378 /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_errors.1131569951 Apr 21 12:38:20 PM PDT 24 Apr 21 12:38:35 PM PDT 24 1498166078 ps
T379 /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_walk.3778008675 Apr 21 12:38:23 PM PDT 24 Apr 21 12:38:28 PM PDT 24 653043151 ps
T380 /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_errors.4247750364 Apr 21 12:38:16 PM PDT 24 Apr 21 12:38:25 PM PDT 24 5804775950 ps
T75 /workspace/coverage/cover_reg_top/12.rom_ctrl_same_csr_outstanding.3732481936 Apr 21 12:38:15 PM PDT 24 Apr 21 12:38:30 PM PDT 24 1676585613 ps
T381 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_mem_rw_with_rand_reset.589310372 Apr 21 12:38:17 PM PDT 24 Apr 21 12:38:22 PM PDT 24 99831811 ps
T382 /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_errors.2629537603 Apr 21 12:37:55 PM PDT 24 Apr 21 12:38:12 PM PDT 24 1865671690 ps
T383 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_mem_rw_with_rand_reset.3196952978 Apr 21 12:38:16 PM PDT 24 Apr 21 12:38:32 PM PDT 24 1939305871 ps
T384 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_mem_rw_with_rand_reset.1274331678 Apr 21 12:38:09 PM PDT 24 Apr 21 12:38:17 PM PDT 24 3044960774 ps
T385 /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_errors.1640305543 Apr 21 12:37:55 PM PDT 24 Apr 21 12:38:06 PM PDT 24 1063835389 ps
T386 /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_errors.3577831562 Apr 21 12:38:27 PM PDT 24 Apr 21 12:38:35 PM PDT 24 191261926 ps
T110 /workspace/coverage/cover_reg_top/1.rom_ctrl_same_csr_outstanding.3319023572 Apr 21 12:37:51 PM PDT 24 Apr 21 12:37:56 PM PDT 24 168507722 ps
T387 /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_errors.279262293 Apr 21 12:38:04 PM PDT 24 Apr 21 12:38:11 PM PDT 24 128166970 ps
T388 /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_partial_access.561017716 Apr 21 12:38:02 PM PDT 24 Apr 21 12:38:07 PM PDT 24 333909510 ps
T130 /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_intg_err.3158798172 Apr 21 12:38:18 PM PDT 24 Apr 21 12:38:57 PM PDT 24 498782289 ps
T389 /workspace/coverage/cover_reg_top/13.rom_ctrl_same_csr_outstanding.3774491981 Apr 21 12:38:25 PM PDT 24 Apr 21 12:38:29 PM PDT 24 175657646 ps
T390 /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_intg_err.1823794245 Apr 21 12:38:04 PM PDT 24 Apr 21 12:39:14 PM PDT 24 323835725 ps
T391 /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_walk.2282074507 Apr 21 12:38:22 PM PDT 24 Apr 21 12:38:26 PM PDT 24 87197503 ps
T392 /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_errors.1518097627 Apr 21 12:38:34 PM PDT 24 Apr 21 12:38:49 PM PDT 24 954693384 ps
T393 /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_mem_rw_with_rand_reset.348664097 Apr 21 12:38:13 PM PDT 24 Apr 21 12:38:28 PM PDT 24 6882073093 ps
T394 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_rw.2173288941 Apr 21 12:38:14 PM PDT 24 Apr 21 12:38:19 PM PDT 24 1381110965 ps
T76 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_aliasing.465168319 Apr 21 12:38:11 PM PDT 24 Apr 21 12:38:25 PM PDT 24 6463932981 ps
T125 /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_intg_err.1890049817 Apr 21 12:38:23 PM PDT 24 Apr 21 12:39:08 PM PDT 24 11131421785 ps
T395 /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_mem_rw_with_rand_reset.193620124 Apr 21 12:38:21 PM PDT 24 Apr 21 12:38:29 PM PDT 24 539748111 ps
T114 /workspace/coverage/cover_reg_top/14.rom_ctrl_passthru_mem_tl_intg_err.3317350309 Apr 21 12:38:17 PM PDT 24 Apr 21 12:39:27 PM PDT 24 7181380462 ps
T77 /workspace/coverage/cover_reg_top/17.rom_ctrl_passthru_mem_tl_intg_err.1306371673 Apr 21 12:38:25 PM PDT 24 Apr 21 12:39:38 PM PDT 24 8264267032 ps
T396 /workspace/coverage/cover_reg_top/9.rom_ctrl_passthru_mem_tl_intg_err.3011149695 Apr 21 12:38:04 PM PDT 24 Apr 21 12:38:38 PM PDT 24 992875368 ps
T128 /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_intg_err.2222257327 Apr 21 12:38:06 PM PDT 24 Apr 21 12:38:46 PM PDT 24 3200608413 ps
T397 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_mem_rw_with_rand_reset.1356437716 Apr 21 12:38:02 PM PDT 24 Apr 21 12:38:08 PM PDT 24 94738938 ps
T78 /workspace/coverage/cover_reg_top/4.rom_ctrl_same_csr_outstanding.2265745961 Apr 21 12:38:08 PM PDT 24 Apr 21 12:38:21 PM PDT 24 9445774549 ps
T398 /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_mem_rw_with_rand_reset.1710648789 Apr 21 12:38:13 PM PDT 24 Apr 21 12:38:19 PM PDT 24 386302013 ps
T399 /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_rw.2781665655 Apr 21 12:38:15 PM PDT 24 Apr 21 12:38:32 PM PDT 24 7580053909 ps
T126 /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_intg_err.2239254797 Apr 21 12:38:10 PM PDT 24 Apr 21 12:39:19 PM PDT 24 1829113854 ps
T400 /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_rw.454093152 Apr 21 12:38:21 PM PDT 24 Apr 21 12:38:34 PM PDT 24 1531642633 ps
T401 /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_errors.1851275701 Apr 21 12:38:27 PM PDT 24 Apr 21 12:38:45 PM PDT 24 3974287530 ps
T129 /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_intg_err.3684481823 Apr 21 12:37:49 PM PDT 24 Apr 21 12:38:35 PM PDT 24 1754089458 ps
T402 /workspace/coverage/cover_reg_top/6.rom_ctrl_passthru_mem_tl_intg_err.1539574098 Apr 21 12:38:17 PM PDT 24 Apr 21 12:39:20 PM PDT 24 15135158807 ps
T403 /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_intg_err.2643554089 Apr 21 12:38:10 PM PDT 24 Apr 21 12:38:54 PM PDT 24 1990678395 ps
T404 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_rw.1099398017 Apr 21 12:38:04 PM PDT 24 Apr 21 12:38:14 PM PDT 24 712108428 ps
T405 /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_mem_rw_with_rand_reset.1974598911 Apr 21 12:37:59 PM PDT 24 Apr 21 12:38:14 PM PDT 24 2278142851 ps
T406 /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_rw.3046700809 Apr 21 12:38:26 PM PDT 24 Apr 21 12:38:42 PM PDT 24 2157635852 ps
T117 /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_intg_err.1697081183 Apr 21 12:38:06 PM PDT 24 Apr 21 12:39:24 PM PDT 24 3696476093 ps
T407 /workspace/coverage/cover_reg_top/0.rom_ctrl_same_csr_outstanding.593040169 Apr 21 12:38:05 PM PDT 24 Apr 21 12:38:18 PM PDT 24 6104844861 ps
T408 /workspace/coverage/cover_reg_top/2.rom_ctrl_passthru_mem_tl_intg_err.2427101489 Apr 21 12:38:16 PM PDT 24 Apr 21 12:39:02 PM PDT 24 18459126945 ps
T409 /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_errors.2846164369 Apr 21 12:38:11 PM PDT 24 Apr 21 12:38:21 PM PDT 24 1309248398 ps
T410 /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_mem_rw_with_rand_reset.1111944152 Apr 21 12:37:56 PM PDT 24 Apr 21 12:38:03 PM PDT 24 200725980 ps
T411 /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_walk.2356269136 Apr 21 12:38:07 PM PDT 24 Apr 21 12:38:23 PM PDT 24 2087905104 ps
T122 /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_intg_err.254288301 Apr 21 12:38:06 PM PDT 24 Apr 21 12:38:46 PM PDT 24 1486411687 ps
T412 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_bit_bash.892820606 Apr 21 12:38:20 PM PDT 24 Apr 21 12:38:37 PM PDT 24 8883484613 ps
T413 /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_errors.1255154839 Apr 21 12:38:16 PM PDT 24 Apr 21 12:38:31 PM PDT 24 2732090047 ps
T86 /workspace/coverage/cover_reg_top/16.rom_ctrl_passthru_mem_tl_intg_err.1854929961 Apr 21 12:38:10 PM PDT 24 Apr 21 12:39:48 PM PDT 24 50517837759 ps
T414 /workspace/coverage/cover_reg_top/15.rom_ctrl_same_csr_outstanding.2287545043 Apr 21 12:38:15 PM PDT 24 Apr 21 12:38:22 PM PDT 24 1331527574 ps
T415 /workspace/coverage/cover_reg_top/9.rom_ctrl_same_csr_outstanding.3455550006 Apr 21 12:38:10 PM PDT 24 Apr 21 12:38:20 PM PDT 24 810692749 ps
T87 /workspace/coverage/cover_reg_top/4.rom_ctrl_passthru_mem_tl_intg_err.3086858944 Apr 21 12:37:55 PM PDT 24 Apr 21 12:38:55 PM PDT 24 14077686611 ps
T416 /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_errors.4149738443 Apr 21 12:38:10 PM PDT 24 Apr 21 12:38:30 PM PDT 24 3409674364 ps
T417 /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_mem_rw_with_rand_reset.1050151405 Apr 21 12:38:28 PM PDT 24 Apr 21 12:38:38 PM PDT 24 1419728552 ps
T418 /workspace/coverage/cover_reg_top/7.rom_ctrl_same_csr_outstanding.3715182151 Apr 21 12:37:50 PM PDT 24 Apr 21 12:38:05 PM PDT 24 1684643726 ps
T419 /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_mem_rw_with_rand_reset.2250544745 Apr 21 12:38:13 PM PDT 24 Apr 21 12:38:24 PM PDT 24 10343244674 ps
T420 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_hw_reset.1009590632 Apr 21 12:38:21 PM PDT 24 Apr 21 12:38:32 PM PDT 24 526097631 ps
T421 /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_partial_access.810264499 Apr 21 12:38:01 PM PDT 24 Apr 21 12:38:13 PM PDT 24 1197228257 ps
T422 /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_mem_rw_with_rand_reset.2414674922 Apr 21 12:38:26 PM PDT 24 Apr 21 12:38:42 PM PDT 24 1934327689 ps
T423 /workspace/coverage/cover_reg_top/18.rom_ctrl_passthru_mem_tl_intg_err.2292630935 Apr 21 12:38:40 PM PDT 24 Apr 21 12:39:20 PM PDT 24 3390028260 ps
T424 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_bit_bash.3653594536 Apr 21 12:38:01 PM PDT 24 Apr 21 12:38:13 PM PDT 24 9504185541 ps
T425 /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_rw.2222480633 Apr 21 12:38:04 PM PDT 24 Apr 21 12:38:09 PM PDT 24 822584824 ps
T426 /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_mem_rw_with_rand_reset.2588417823 Apr 21 12:38:33 PM PDT 24 Apr 21 12:38:39 PM PDT 24 710539353 ps
T427 /workspace/coverage/cover_reg_top/10.rom_ctrl_same_csr_outstanding.1779527806 Apr 21 12:38:37 PM PDT 24 Apr 21 12:38:42 PM PDT 24 89006398 ps
T428 /workspace/coverage/cover_reg_top/3.rom_ctrl_same_csr_outstanding.244455403 Apr 21 12:38:17 PM PDT 24 Apr 21 12:38:34 PM PDT 24 2088451465 ps
T127 /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_intg_err.2595816250 Apr 21 12:38:21 PM PDT 24 Apr 21 12:39:30 PM PDT 24 232649518 ps
T88 /workspace/coverage/cover_reg_top/15.rom_ctrl_passthru_mem_tl_intg_err.1157503120 Apr 21 12:38:11 PM PDT 24 Apr 21 12:38:53 PM PDT 24 12769682613 ps
T429 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_bit_bash.1718287631 Apr 21 12:37:51 PM PDT 24 Apr 21 12:38:02 PM PDT 24 3941362949 ps
T94 /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_rw.1496426615 Apr 21 12:38:04 PM PDT 24 Apr 21 12:38:12 PM PDT 24 2048118776 ps
T89 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_hw_reset.1060858265 Apr 21 12:38:05 PM PDT 24 Apr 21 12:38:12 PM PDT 24 708334930 ps
T430 /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_mem_rw_with_rand_reset.1625020393 Apr 21 12:38:22 PM PDT 24 Apr 21 12:38:32 PM PDT 24 3549819198 ps
T120 /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_intg_err.3506624951 Apr 21 12:38:15 PM PDT 24 Apr 21 12:39:01 PM PDT 24 1692796344 ps
T431 /workspace/coverage/cover_reg_top/13.rom_ctrl_passthru_mem_tl_intg_err.2136628145 Apr 21 12:38:24 PM PDT 24 Apr 21 12:38:52 PM PDT 24 3019843542 ps
T90 /workspace/coverage/cover_reg_top/12.rom_ctrl_passthru_mem_tl_intg_err.2349312211 Apr 21 12:38:22 PM PDT 24 Apr 21 12:39:52 PM PDT 24 11708446081 ps
T432 /workspace/coverage/cover_reg_top/5.rom_ctrl_passthru_mem_tl_intg_err.2126387895 Apr 21 12:37:57 PM PDT 24 Apr 21 12:39:04 PM PDT 24 33643187345 ps
T433 /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_rw.2301951893 Apr 21 12:37:55 PM PDT 24 Apr 21 12:38:10 PM PDT 24 6648266885 ps
T434 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_hw_reset.2484741904 Apr 21 12:38:26 PM PDT 24 Apr 21 12:38:34 PM PDT 24 262896876 ps
T435 /workspace/coverage/cover_reg_top/16.rom_ctrl_same_csr_outstanding.778400507 Apr 21 12:38:19 PM PDT 24 Apr 21 12:38:30 PM PDT 24 1072669283 ps
T436 /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_mem_rw_with_rand_reset.2230169262 Apr 21 12:38:11 PM PDT 24 Apr 21 12:38:16 PM PDT 24 134384832 ps
T437 /workspace/coverage/cover_reg_top/8.rom_ctrl_same_csr_outstanding.3123944794 Apr 21 12:38:18 PM PDT 24 Apr 21 12:38:30 PM PDT 24 2379870812 ps
T438 /workspace/coverage/cover_reg_top/14.rom_ctrl_same_csr_outstanding.758902426 Apr 21 12:38:23 PM PDT 24 Apr 21 12:38:32 PM PDT 24 4309623113 ps
T439 /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_mem_rw_with_rand_reset.692472377 Apr 21 12:37:59 PM PDT 24 Apr 21 12:38:09 PM PDT 24 926680563 ps
T440 /workspace/coverage/cover_reg_top/19.rom_ctrl_same_csr_outstanding.3802115641 Apr 21 12:38:13 PM PDT 24 Apr 21 12:38:21 PM PDT 24 836886781 ps
T91 /workspace/coverage/cover_reg_top/7.rom_ctrl_passthru_mem_tl_intg_err.1067125572 Apr 21 12:37:52 PM PDT 24 Apr 21 12:38:44 PM PDT 24 17328962818 ps
T441 /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_mem_rw_with_rand_reset.901480394 Apr 21 12:38:13 PM PDT 24 Apr 21 12:38:30 PM PDT 24 3916250436 ps
T442 /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_errors.811723540 Apr 21 12:38:07 PM PDT 24 Apr 21 12:38:20 PM PDT 24 3927298777 ps
T443 /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_rw.1475658005 Apr 21 12:38:40 PM PDT 24 Apr 21 12:38:49 PM PDT 24 3382654869 ps
T444 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_aliasing.97226217 Apr 21 12:38:34 PM PDT 24 Apr 21 12:38:51 PM PDT 24 2035603004 ps
T445 /workspace/coverage/cover_reg_top/1.rom_ctrl_passthru_mem_tl_intg_err.3177444485 Apr 21 12:38:07 PM PDT 24 Apr 21 12:38:52 PM PDT 24 37401381594 ps
T446 /workspace/coverage/cover_reg_top/0.rom_ctrl_passthru_mem_tl_intg_err.2726443360 Apr 21 12:38:15 PM PDT 24 Apr 21 12:39:01 PM PDT 24 17097412553 ps
T447 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_hw_reset.283706879 Apr 21 12:38:04 PM PDT 24 Apr 21 12:38:17 PM PDT 24 2645692097 ps
T95 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_rw.2311330251 Apr 21 12:38:02 PM PDT 24 Apr 21 12:38:14 PM PDT 24 4065098583 ps
T92 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_aliasing.1192214805 Apr 21 12:38:03 PM PDT 24 Apr 21 12:38:17 PM PDT 24 7144224614 ps
T448 /workspace/coverage/cover_reg_top/2.rom_ctrl_same_csr_outstanding.899132744 Apr 21 12:38:09 PM PDT 24 Apr 21 12:38:15 PM PDT 24 813108140 ps
T449 /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_rw.1953761648 Apr 21 12:38:26 PM PDT 24 Apr 21 12:38:35 PM PDT 24 1177212357 ps
T450 /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_errors.881990894 Apr 21 12:38:17 PM PDT 24 Apr 21 12:38:28 PM PDT 24 1314467623 ps
T451 /workspace/coverage/cover_reg_top/19.rom_ctrl_passthru_mem_tl_intg_err.507310366 Apr 21 12:38:08 PM PDT 24 Apr 21 12:39:31 PM PDT 24 43429145338 ps
T452 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_aliasing.1600628840 Apr 21 12:38:12 PM PDT 24 Apr 21 12:38:21 PM PDT 24 654333684 ps
T453 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_mem_rw_with_rand_reset.710912052 Apr 21 12:38:16 PM PDT 24 Apr 21 12:38:26 PM PDT 24 1417956327 ps
T454 /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_walk.1360233607 Apr 21 12:38:11 PM PDT 24 Apr 21 12:38:26 PM PDT 24 12935728517 ps
T455 /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_rw.734762685 Apr 21 12:38:14 PM PDT 24 Apr 21 12:38:25 PM PDT 24 1031542935 ps
T456 /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_errors.2509689837 Apr 21 12:38:01 PM PDT 24 Apr 21 12:38:09 PM PDT 24 213516296 ps
T457 /workspace/coverage/cover_reg_top/18.rom_ctrl_same_csr_outstanding.2096356193 Apr 21 12:38:13 PM PDT 24 Apr 21 12:38:21 PM PDT 24 4538617764 ps
T124 /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_intg_err.1801493108 Apr 21 12:38:21 PM PDT 24 Apr 21 12:38:58 PM PDT 24 393990565 ps
T458 /workspace/coverage/cover_reg_top/5.rom_ctrl_same_csr_outstanding.462007455 Apr 21 12:38:21 PM PDT 24 Apr 21 12:38:37 PM PDT 24 1770309376 ps
T459 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_bit_bash.3297815877 Apr 21 12:38:14 PM PDT 24 Apr 21 12:38:20 PM PDT 24 220582308 ps
T460 /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_rw.1726001648 Apr 21 12:38:15 PM PDT 24 Apr 21 12:38:32 PM PDT 24 4349449990 ps
T461 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_bit_bash.1705423768 Apr 21 12:38:00 PM PDT 24 Apr 21 12:38:08 PM PDT 24 2052923960 ps
T93 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_rw.204791831 Apr 21 12:37:51 PM PDT 24 Apr 21 12:38:08 PM PDT 24 18668707862 ps
T462 /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_errors.1301112845 Apr 21 12:37:52 PM PDT 24 Apr 21 12:38:05 PM PDT 24 986004596 ps
T123 /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_intg_err.1998281257 Apr 21 12:38:23 PM PDT 24 Apr 21 12:39:05 PM PDT 24 944965901 ps

Test location /workspace/coverage/default/37.rom_ctrl_stress_all_with_rand_reset.1328366276
Short name T2
Test name
Test status
Simulation time 287803855723 ps
CPU time 2546.25 seconds
Started Apr 21 12:24:31 PM PDT 24
Finished Apr 21 01:06:58 PM PDT 24
Peak memory 244572 kb
Host smart-5185e6b7-996e-4bc0-bf2c-998da08cd72c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1328366276 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_stress_all_with_rand_reset.1328366276
Directory /workspace/37.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/24.rom_ctrl_corrupt_sig_fatal_chk.2162062540
Short name T22
Test name
Test status
Simulation time 36243825077 ps
CPU time 344.34 seconds
Started Apr 21 12:24:20 PM PDT 24
Finished Apr 21 12:30:05 PM PDT 24
Peak memory 229752 kb
Host smart-7acec043-3301-4ab3-9c1b-979b1ae8eb89
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2162062540 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_
corrupt_sig_fatal_chk.2162062540
Directory /workspace/24.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/34.rom_ctrl_kmac_err_chk.3757570473
Short name T9
Test name
Test status
Simulation time 29752594355 ps
CPU time 19.78 seconds
Started Apr 21 12:24:18 PM PDT 24
Finished Apr 21 12:24:38 PM PDT 24
Peak memory 212764 kb
Host smart-5e0c5a75-d85f-4a40-9f9e-dfeec4962d9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3757570473 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_kmac_err_chk.3757570473
Directory /workspace/34.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_intg_err.2566309105
Short name T118
Test name
Test status
Simulation time 11857396206 ps
CPU time 78.08 seconds
Started Apr 21 12:38:13 PM PDT 24
Finished Apr 21 12:39:31 PM PDT 24
Peak memory 213032 kb
Host smart-bc1cc235-a775-4e98-adb0-d9dd87dea0e3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2566309105 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_tl_in
tg_err.2566309105
Directory /workspace/8.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/30.rom_ctrl_stress_all.1520116205
Short name T36
Test name
Test status
Simulation time 1081311751 ps
CPU time 34.9 seconds
Started Apr 21 12:24:20 PM PDT 24
Finished Apr 21 12:24:56 PM PDT 24
Peak memory 215072 kb
Host smart-cfeefa6a-06a3-4eda-9273-32595645c2cd
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1520116205 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 30.rom_ctrl_stress_all.1520116205
Directory /workspace/30.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/3.rom_ctrl_sec_cm.3415222520
Short name T31
Test name
Test status
Simulation time 235832693 ps
CPU time 98.08 seconds
Started Apr 21 12:23:57 PM PDT 24
Finished Apr 21 12:25:36 PM PDT 24
Peak memory 238428 kb
Host smart-f6264489-6e16-482d-b9e0-40613cad9d83
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3415222520 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_sec_cm.3415222520
Directory /workspace/3.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_passthru_mem_tl_intg_err.2853834196
Short name T74
Test name
Test status
Simulation time 2103273163 ps
CPU time 28.18 seconds
Started Apr 21 12:38:16 PM PDT 24
Finished Apr 21 12:38:45 PM PDT 24
Peak memory 210908 kb
Host smart-5db892f1-3b16-4e8d-94b4-87282a6c0385
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2853834196 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_p
assthru_mem_tl_intg_err.2853834196
Directory /workspace/10.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/default/6.rom_ctrl_corrupt_sig_fatal_chk.3750787421
Short name T12
Test name
Test status
Simulation time 19768918177 ps
CPU time 245.36 seconds
Started Apr 21 12:23:50 PM PDT 24
Finished Apr 21 12:27:56 PM PDT 24
Peak memory 220104 kb
Host smart-406b5c32-2929-4036-92ab-1387ed60ac27
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3750787421 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_c
orrupt_sig_fatal_chk.3750787421
Directory /workspace/6.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/18.rom_ctrl_smoke.651718784
Short name T83
Test name
Test status
Simulation time 1744966247 ps
CPU time 24.27 seconds
Started Apr 21 12:24:05 PM PDT 24
Finished Apr 21 12:24:29 PM PDT 24
Peak memory 214180 kb
Host smart-0bcbdcf6-37de-44f5-a790-c7ea1849ca6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=651718784 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_smoke.651718784
Directory /workspace/18.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/36.rom_ctrl_alert_test.2999219588
Short name T67
Test name
Test status
Simulation time 615829114 ps
CPU time 7.73 seconds
Started Apr 21 12:24:50 PM PDT 24
Finished Apr 21 12:24:59 PM PDT 24
Peak memory 211668 kb
Host smart-07363404-15d7-43ee-9232-3c9ced613051
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2999219588 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_alert_test.2999219588
Directory /workspace/36.rom_ctrl_alert_test/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_intg_err.1697081183
Short name T117
Test name
Test status
Simulation time 3696476093 ps
CPU time 77.26 seconds
Started Apr 21 12:38:06 PM PDT 24
Finished Apr 21 12:39:24 PM PDT 24
Peak memory 211600 kb
Host smart-ee85f25b-54d0-43c0-9d84-a913f7ea406a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1697081183 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_tl_i
ntg_err.1697081183
Directory /workspace/15.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/32.rom_ctrl_stress_all_with_rand_reset.561509292
Short name T132
Test name
Test status
Simulation time 61377314663 ps
CPU time 2165.42 seconds
Started Apr 21 12:25:00 PM PDT 24
Finished Apr 21 01:01:07 PM PDT 24
Peak memory 237276 kb
Host smart-c42c3fb0-b6d5-4b76-befb-f6d5e3601dfb
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=561509292 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_stress_all_with_rand_reset.561509292
Directory /workspace/32.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_passthru_mem_tl_intg_err.4028474274
Short name T73
Test name
Test status
Simulation time 550189831 ps
CPU time 27.36 seconds
Started Apr 21 12:38:04 PM PDT 24
Finished Apr 21 12:38:32 PM PDT 24
Peak memory 210780 kb
Host smart-4d4fc2bc-bbdb-4024-9280-06b5685441a3
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4028474274 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_pa
ssthru_mem_tl_intg_err.4028474274
Directory /workspace/8.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/default/19.rom_ctrl_kmac_err_chk.3048322878
Short name T171
Test name
Test status
Simulation time 15440603931 ps
CPU time 32.17 seconds
Started Apr 21 12:24:18 PM PDT 24
Finished Apr 21 12:24:51 PM PDT 24
Peak memory 212704 kb
Host smart-e3dcc5de-34f0-44b5-9704-335d8c2509c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3048322878 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_kmac_err_chk.3048322878
Directory /workspace/19.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_intg_err.1890049817
Short name T125
Test name
Test status
Simulation time 11131421785 ps
CPU time 43.66 seconds
Started Apr 21 12:38:23 PM PDT 24
Finished Apr 21 12:39:08 PM PDT 24
Peak memory 219124 kb
Host smart-bced20d7-24ee-4ead-a00c-3a73c0b9131e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1890049817 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_tl_i
ntg_err.1890049817
Directory /workspace/10.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_intg_err.1998281257
Short name T123
Test name
Test status
Simulation time 944965901 ps
CPU time 41.4 seconds
Started Apr 21 12:38:23 PM PDT 24
Finished Apr 21 12:39:05 PM PDT 24
Peak memory 210924 kb
Host smart-90a5f5ae-70e1-4cf7-b3ce-717ebf829964
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1998281257 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_tl_in
tg_err.1998281257
Directory /workspace/1.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/20.rom_ctrl_stress_all_with_rand_reset.2037749730
Short name T18
Test name
Test status
Simulation time 213802593336 ps
CPU time 3871.01 seconds
Started Apr 21 12:24:20 PM PDT 24
Finished Apr 21 01:28:52 PM PDT 24
Peak memory 247328 kb
Host smart-df3d7889-0d05-479b-9f23-66e443db3e71
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2037749730 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_stress_all_with_rand_reset.2037749730
Directory /workspace/20.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_aliasing.1192214805
Short name T92
Test name
Test status
Simulation time 7144224614 ps
CPU time 13.18 seconds
Started Apr 21 12:38:03 PM PDT 24
Finished Apr 21 12:38:17 PM PDT 24
Peak memory 210944 kb
Host smart-6137dfaa-2260-4255-97e8-1d553f06fa77
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1192214805 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_alia
sing.1192214805
Directory /workspace/0.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/default/33.rom_ctrl_max_throughput_chk.922967687
Short name T96
Test name
Test status
Simulation time 1964494271 ps
CPU time 7.08 seconds
Started Apr 21 12:24:39 PM PDT 24
Finished Apr 21 12:24:46 PM PDT 24
Peak memory 211548 kb
Host smart-db2ebb97-437a-4814-b85d-9e6da90c85ee
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=922967687 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_max_throughput_chk.922967687
Directory /workspace/33.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_aliasing.924694438
Short name T111
Test name
Test status
Simulation time 2307117949 ps
CPU time 7.9 seconds
Started Apr 21 12:38:18 PM PDT 24
Finished Apr 21 12:38:26 PM PDT 24
Peak memory 210796 kb
Host smart-f71d9f23-9a9d-46dd-9615-42b0eafb7a99
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=924694438 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_alias
ing.924694438
Directory /workspace/1.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/default/1.rom_ctrl_stress_all.3108507958
Short name T10
Test name
Test status
Simulation time 22547864569 ps
CPU time 40.52 seconds
Started Apr 21 12:23:36 PM PDT 24
Finished Apr 21 12:24:17 PM PDT 24
Peak memory 218384 kb
Host smart-18e693ef-f889-468d-bb59-84f0c0f846a6
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3108507958 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 1.rom_ctrl_stress_all.3108507958
Directory /workspace/1.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/13.rom_ctrl_smoke.955123160
Short name T170
Test name
Test status
Simulation time 190293267 ps
CPU time 9.92 seconds
Started Apr 21 12:24:05 PM PDT 24
Finished Apr 21 12:24:16 PM PDT 24
Peak memory 213504 kb
Host smart-12ed8de2-05d5-4ce5-8654-729a47bb3ad0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=955123160 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_smoke.955123160
Directory /workspace/13.rom_ctrl_smoke/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_bit_bash.3653594536
Short name T424
Test name
Test status
Simulation time 9504185541 ps
CPU time 11.76 seconds
Started Apr 21 12:38:01 PM PDT 24
Finished Apr 21 12:38:13 PM PDT 24
Peak memory 210832 kb
Host smart-c99ab860-aba5-4462-99da-80d5bcc8bc6d
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3653594536 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_bit_
bash.3653594536
Directory /workspace/0.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_hw_reset.2484741904
Short name T434
Test name
Test status
Simulation time 262896876 ps
CPU time 7.4 seconds
Started Apr 21 12:38:26 PM PDT 24
Finished Apr 21 12:38:34 PM PDT 24
Peak memory 210784 kb
Host smart-5529a36c-f6cd-44d5-86b0-6499ab25ca9e
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2484741904 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_hw_r
eset.2484741904
Directory /workspace/0.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_mem_rw_with_rand_reset.3196952978
Short name T383
Test name
Test status
Simulation time 1939305871 ps
CPU time 15.88 seconds
Started Apr 21 12:38:16 PM PDT 24
Finished Apr 21 12:38:32 PM PDT 24
Peak memory 218988 kb
Host smart-69e414c4-6a27-4258-8323-dbe38ffdc202
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3196952978 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 0.rom_ctrl_csr_mem_rw_with_rand_reset.3196952978
Directory /workspace/0.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_rw.2311330251
Short name T95
Test name
Test status
Simulation time 4065098583 ps
CPU time 10.3 seconds
Started Apr 21 12:38:02 PM PDT 24
Finished Apr 21 12:38:14 PM PDT 24
Peak memory 210892 kb
Host smart-92ba135c-a0df-4114-bc4b-88fe74e83843
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2311330251 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_rw.2311330251
Directory /workspace/0.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_partial_access.561017716
Short name T388
Test name
Test status
Simulation time 333909510 ps
CPU time 4.05 seconds
Started Apr 21 12:38:02 PM PDT 24
Finished Apr 21 12:38:07 PM PDT 24
Peak memory 210656 kb
Host smart-6974de12-ac88-4624-8650-48583ee0ddfb
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=561017716 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl
_mem_partial_access.561017716
Directory /workspace/0.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_walk.1360233607
Short name T454
Test name
Test status
Simulation time 12935728517 ps
CPU time 14.26 seconds
Started Apr 21 12:38:11 PM PDT 24
Finished Apr 21 12:38:26 PM PDT 24
Peak memory 210700 kb
Host smart-de1d41fd-fe33-42b6-b2a1-461a1ab0f3b1
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1360233607 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_mem_walk
.1360233607
Directory /workspace/0.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_passthru_mem_tl_intg_err.2726443360
Short name T446
Test name
Test status
Simulation time 17097412553 ps
CPU time 44.99 seconds
Started Apr 21 12:38:15 PM PDT 24
Finished Apr 21 12:39:01 PM PDT 24
Peak memory 210900 kb
Host smart-1c0f4801-a0a5-4757-bebb-e068a705bd49
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2726443360 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_pa
ssthru_mem_tl_intg_err.2726443360
Directory /workspace/0.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_same_csr_outstanding.593040169
Short name T407
Test name
Test status
Simulation time 6104844861 ps
CPU time 12.75 seconds
Started Apr 21 12:38:05 PM PDT 24
Finished Apr 21 12:38:18 PM PDT 24
Peak memory 210824 kb
Host smart-8dd864ba-cccd-46d7-82f9-e23e8a31ef6a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=593040169 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ct
rl_same_csr_outstanding.593040169
Directory /workspace/0.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_errors.1255154839
Short name T413
Test name
Test status
Simulation time 2732090047 ps
CPU time 14.89 seconds
Started Apr 21 12:38:16 PM PDT 24
Finished Apr 21 12:38:31 PM PDT 24
Peak memory 216560 kb
Host smart-4845f68e-5b49-4a5a-b781-255e2d723718
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1255154839 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_tl_errors.1255154839
Directory /workspace/0.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_intg_err.1432735221
Short name T121
Test name
Test status
Simulation time 3576405080 ps
CPU time 46.59 seconds
Started Apr 21 12:38:12 PM PDT 24
Finished Apr 21 12:38:59 PM PDT 24
Peak memory 211544 kb
Host smart-1402c2ee-e70a-4197-aa1d-4c761f3e7d06
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1432735221 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_tl_in
tg_err.1432735221
Directory /workspace/0.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_bit_bash.1718287631
Short name T429
Test name
Test status
Simulation time 3941362949 ps
CPU time 10.51 seconds
Started Apr 21 12:37:51 PM PDT 24
Finished Apr 21 12:38:02 PM PDT 24
Peak memory 210936 kb
Host smart-f0129acc-d0e9-4dea-b57c-dd4fe0882bc1
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1718287631 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_bit_
bash.1718287631
Directory /workspace/1.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_hw_reset.1060858265
Short name T89
Test name
Test status
Simulation time 708334930 ps
CPU time 5.75 seconds
Started Apr 21 12:38:05 PM PDT 24
Finished Apr 21 12:38:12 PM PDT 24
Peak memory 210824 kb
Host smart-a2bc31c7-e718-4161-8363-f29a01a3ecaa
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1060858265 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_hw_r
eset.1060858265
Directory /workspace/1.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_mem_rw_with_rand_reset.1356437716
Short name T397
Test name
Test status
Simulation time 94738938 ps
CPU time 4.65 seconds
Started Apr 21 12:38:02 PM PDT 24
Finished Apr 21 12:38:08 PM PDT 24
Peak memory 212860 kb
Host smart-3ff05fec-cea3-42eb-813b-9abb0cfdb27a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1356437716 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 1.rom_ctrl_csr_mem_rw_with_rand_reset.1356437716
Directory /workspace/1.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_rw.204791831
Short name T93
Test name
Test status
Simulation time 18668707862 ps
CPU time 16.67 seconds
Started Apr 21 12:37:51 PM PDT 24
Finished Apr 21 12:38:08 PM PDT 24
Peak memory 210988 kb
Host smart-8aab3608-d19f-4c0c-a622-6a729d68506f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=204791831 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_rw.204791831
Directory /workspace/1.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_partial_access.810264499
Short name T421
Test name
Test status
Simulation time 1197228257 ps
CPU time 11.28 seconds
Started Apr 21 12:38:01 PM PDT 24
Finished Apr 21 12:38:13 PM PDT 24
Peak memory 210720 kb
Host smart-2b77f94f-4541-486a-8233-99ebf77153a8
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=810264499 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl
_mem_partial_access.810264499
Directory /workspace/1.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_walk.2282074507
Short name T391
Test name
Test status
Simulation time 87197503 ps
CPU time 4.19 seconds
Started Apr 21 12:38:22 PM PDT 24
Finished Apr 21 12:38:26 PM PDT 24
Peak memory 210780 kb
Host smart-186e40f2-68a9-4d7c-acbb-c02243cf0b24
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2282074507 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_mem_walk
.2282074507
Directory /workspace/1.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_passthru_mem_tl_intg_err.3177444485
Short name T445
Test name
Test status
Simulation time 37401381594 ps
CPU time 44.92 seconds
Started Apr 21 12:38:07 PM PDT 24
Finished Apr 21 12:38:52 PM PDT 24
Peak memory 210864 kb
Host smart-4e4dc8b1-4c11-4985-9f2e-339d1d84fe66
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3177444485 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_pa
ssthru_mem_tl_intg_err.3177444485
Directory /workspace/1.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_same_csr_outstanding.3319023572
Short name T110
Test name
Test status
Simulation time 168507722 ps
CPU time 4.29 seconds
Started Apr 21 12:37:51 PM PDT 24
Finished Apr 21 12:37:56 PM PDT 24
Peak memory 210740 kb
Host smart-63f43a6a-32bf-45f5-bb93-5da0e9374cb6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3319023572 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_c
trl_same_csr_outstanding.3319023572
Directory /workspace/1.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_errors.2629537603
Short name T382
Test name
Test status
Simulation time 1865671690 ps
CPU time 17.44 seconds
Started Apr 21 12:37:55 PM PDT 24
Finished Apr 21 12:38:12 PM PDT 24
Peak memory 214900 kb
Host smart-57e8da11-ae12-4593-8b0c-fd25268eff19
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2629537603 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_tl_errors.2629537603
Directory /workspace/1.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_mem_rw_with_rand_reset.348664097
Short name T393
Test name
Test status
Simulation time 6882073093 ps
CPU time 14.58 seconds
Started Apr 21 12:38:13 PM PDT 24
Finished Apr 21 12:38:28 PM PDT 24
Peak memory 215996 kb
Host smart-eaec92bc-a369-4af4-8615-ad50fc2cf40d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=348664097 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 10.rom_ctrl_csr_mem_rw_with_rand_reset.348664097
Directory /workspace/10.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_rw.2301951893
Short name T433
Test name
Test status
Simulation time 6648266885 ps
CPU time 14.5 seconds
Started Apr 21 12:37:55 PM PDT 24
Finished Apr 21 12:38:10 PM PDT 24
Peak memory 210836 kb
Host smart-ac290b51-92d1-45aa-aae2-102968418494
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2301951893 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_csr_rw.2301951893
Directory /workspace/10.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_same_csr_outstanding.1779527806
Short name T427
Test name
Test status
Simulation time 89006398 ps
CPU time 4.26 seconds
Started Apr 21 12:38:37 PM PDT 24
Finished Apr 21 12:38:42 PM PDT 24
Peak memory 210788 kb
Host smart-97ad56e1-b6b1-47cf-8753-a97e1a580a37
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1779527806 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_
ctrl_same_csr_outstanding.1779527806
Directory /workspace/10.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_errors.279262293
Short name T387
Test name
Test status
Simulation time 128166970 ps
CPU time 6.78 seconds
Started Apr 21 12:38:04 PM PDT 24
Finished Apr 21 12:38:11 PM PDT 24
Peak memory 215260 kb
Host smart-8bbb41a9-8943-4481-b394-3fc94ed19034
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=279262293 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_tl_errors.279262293
Directory /workspace/10.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_mem_rw_with_rand_reset.1111944152
Short name T410
Test name
Test status
Simulation time 200725980 ps
CPU time 6.37 seconds
Started Apr 21 12:37:56 PM PDT 24
Finished Apr 21 12:38:03 PM PDT 24
Peak memory 214852 kb
Host smart-37598614-673d-46f6-8392-9412737a5414
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1111944152 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 11.rom_ctrl_csr_mem_rw_with_rand_reset.1111944152
Directory /workspace/11.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_rw.1943542025
Short name T72
Test name
Test status
Simulation time 1200075332 ps
CPU time 6.26 seconds
Started Apr 21 12:38:15 PM PDT 24
Finished Apr 21 12:38:22 PM PDT 24
Peak memory 210880 kb
Host smart-7c41a319-f789-4009-b995-6f0093277736
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1943542025 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_csr_rw.1943542025
Directory /workspace/11.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_passthru_mem_tl_intg_err.873648091
Short name T109
Test name
Test status
Simulation time 34514351570 ps
CPU time 96.08 seconds
Started Apr 21 12:38:26 PM PDT 24
Finished Apr 21 12:40:03 PM PDT 24
Peak memory 211012 kb
Host smart-4c53e38a-aad7-4dcb-8eb6-300ab032d584
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=873648091 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_pa
ssthru_mem_tl_intg_err.873648091
Directory /workspace/11.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_same_csr_outstanding.1632281984
Short name T106
Test name
Test status
Simulation time 5994959471 ps
CPU time 15.26 seconds
Started Apr 21 12:38:25 PM PDT 24
Finished Apr 21 12:38:41 PM PDT 24
Peak memory 210988 kb
Host smart-204c11f4-6e53-4006-8cbe-6f199ae1be94
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1632281984 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_
ctrl_same_csr_outstanding.1632281984
Directory /workspace/11.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_errors.4097808204
Short name T373
Test name
Test status
Simulation time 838029710 ps
CPU time 12.86 seconds
Started Apr 21 12:38:30 PM PDT 24
Finished Apr 21 12:38:44 PM PDT 24
Peak memory 219148 kb
Host smart-aa31144c-e303-4894-a6c0-42e0201d8da1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4097808204 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_tl_errors.4097808204
Directory /workspace/11.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_intg_err.2222257327
Short name T128
Test name
Test status
Simulation time 3200608413 ps
CPU time 40.21 seconds
Started Apr 21 12:38:06 PM PDT 24
Finished Apr 21 12:38:46 PM PDT 24
Peak memory 211720 kb
Host smart-d6299d2d-405c-4168-9e58-8ce9172015e2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2222257327 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_tl_i
ntg_err.2222257327
Directory /workspace/11.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_mem_rw_with_rand_reset.1710648789
Short name T398
Test name
Test status
Simulation time 386302013 ps
CPU time 4.85 seconds
Started Apr 21 12:38:13 PM PDT 24
Finished Apr 21 12:38:19 PM PDT 24
Peak memory 213100 kb
Host smart-10c552dd-eef8-4f90-a3fb-b0f52718a606
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1710648789 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 12.rom_ctrl_csr_mem_rw_with_rand_reset.1710648789
Directory /workspace/12.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_rw.2781665655
Short name T399
Test name
Test status
Simulation time 7580053909 ps
CPU time 16.24 seconds
Started Apr 21 12:38:15 PM PDT 24
Finished Apr 21 12:38:32 PM PDT 24
Peak memory 210828 kb
Host smart-0e0524b3-5d9e-4d41-b12b-fc76d5d3af28
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2781665655 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_csr_rw.2781665655
Directory /workspace/12.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_passthru_mem_tl_intg_err.2349312211
Short name T90
Test name
Test status
Simulation time 11708446081 ps
CPU time 90.12 seconds
Started Apr 21 12:38:22 PM PDT 24
Finished Apr 21 12:39:52 PM PDT 24
Peak memory 210920 kb
Host smart-563e5eb5-3e8c-4c7c-aea3-8be779eba6c0
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2349312211 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_p
assthru_mem_tl_intg_err.2349312211
Directory /workspace/12.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_same_csr_outstanding.3732481936
Short name T75
Test name
Test status
Simulation time 1676585613 ps
CPU time 14.54 seconds
Started Apr 21 12:38:15 PM PDT 24
Finished Apr 21 12:38:30 PM PDT 24
Peak memory 210828 kb
Host smart-a07b72b3-c30c-4338-aa3f-7d3986d712ab
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3732481936 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_
ctrl_same_csr_outstanding.3732481936
Directory /workspace/12.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_errors.2509689837
Short name T456
Test name
Test status
Simulation time 213516296 ps
CPU time 7.8 seconds
Started Apr 21 12:38:01 PM PDT 24
Finished Apr 21 12:38:09 PM PDT 24
Peak memory 215004 kb
Host smart-ae8a420a-0463-4f33-a53e-2b02df90c479
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2509689837 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_tl_errors.2509689837
Directory /workspace/12.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_intg_err.472383957
Short name T60
Test name
Test status
Simulation time 2137634995 ps
CPU time 73.1 seconds
Started Apr 21 12:38:01 PM PDT 24
Finished Apr 21 12:39:15 PM PDT 24
Peak memory 211116 kb
Host smart-2a25f9fc-1d08-409d-a9ae-a43812ceed52
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=472383957 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_tl_in
tg_err.472383957
Directory /workspace/12.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_mem_rw_with_rand_reset.193620124
Short name T395
Test name
Test status
Simulation time 539748111 ps
CPU time 7.4 seconds
Started Apr 21 12:38:21 PM PDT 24
Finished Apr 21 12:38:29 PM PDT 24
Peak memory 212000 kb
Host smart-32151ed8-815a-42b9-8e56-c2cb291fb82f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=193620124 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 13.rom_ctrl_csr_mem_rw_with_rand_reset.193620124
Directory /workspace/13.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_rw.23591880
Short name T62
Test name
Test status
Simulation time 1508278075 ps
CPU time 6.77 seconds
Started Apr 21 12:38:19 PM PDT 24
Finished Apr 21 12:38:26 PM PDT 24
Peak memory 210744 kb
Host smart-5af881d6-9cef-4e59-a67d-abdbff1f791f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23591880 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_csr_rw.23591880
Directory /workspace/13.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_passthru_mem_tl_intg_err.2136628145
Short name T431
Test name
Test status
Simulation time 3019843542 ps
CPU time 27.39 seconds
Started Apr 21 12:38:24 PM PDT 24
Finished Apr 21 12:38:52 PM PDT 24
Peak memory 210916 kb
Host smart-4aac156a-bafb-4899-9c19-f37fc5512f0b
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2136628145 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_p
assthru_mem_tl_intg_err.2136628145
Directory /workspace/13.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_same_csr_outstanding.3774491981
Short name T389
Test name
Test status
Simulation time 175657646 ps
CPU time 4.09 seconds
Started Apr 21 12:38:25 PM PDT 24
Finished Apr 21 12:38:29 PM PDT 24
Peak memory 210780 kb
Host smart-6b089e69-cb03-4f2f-bb18-5f37fe09244e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3774491981 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_
ctrl_same_csr_outstanding.3774491981
Directory /workspace/13.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_errors.4149738443
Short name T416
Test name
Test status
Simulation time 3409674364 ps
CPU time 19.35 seconds
Started Apr 21 12:38:10 PM PDT 24
Finished Apr 21 12:38:30 PM PDT 24
Peak memory 219244 kb
Host smart-26998f9e-a00c-472d-9d2e-8dc026f95613
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4149738443 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_tl_errors.4149738443
Directory /workspace/13.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_intg_err.3111874480
Short name T61
Test name
Test status
Simulation time 1764025964 ps
CPU time 70.96 seconds
Started Apr 21 12:38:20 PM PDT 24
Finished Apr 21 12:39:31 PM PDT 24
Peak memory 219056 kb
Host smart-734353a7-1b54-4a5c-9e30-7e46b8bde975
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3111874480 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_tl_i
ntg_err.3111874480
Directory /workspace/13.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_mem_rw_with_rand_reset.1974598911
Short name T405
Test name
Test status
Simulation time 2278142851 ps
CPU time 14.7 seconds
Started Apr 21 12:37:59 PM PDT 24
Finished Apr 21 12:38:14 PM PDT 24
Peak memory 216224 kb
Host smart-415c3b65-a5d0-4d73-b6ba-c6128dbf8495
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1974598911 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 14.rom_ctrl_csr_mem_rw_with_rand_reset.1974598911
Directory /workspace/14.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_rw.1674338736
Short name T71
Test name
Test status
Simulation time 726108494 ps
CPU time 8.39 seconds
Started Apr 21 12:38:36 PM PDT 24
Finished Apr 21 12:38:45 PM PDT 24
Peak memory 210892 kb
Host smart-cf6c73af-72ff-4c68-8293-b20295c4f844
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1674338736 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_csr_rw.1674338736
Directory /workspace/14.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_passthru_mem_tl_intg_err.3317350309
Short name T114
Test name
Test status
Simulation time 7181380462 ps
CPU time 69.18 seconds
Started Apr 21 12:38:17 PM PDT 24
Finished Apr 21 12:39:27 PM PDT 24
Peak memory 210948 kb
Host smart-240e0291-8969-46ee-ada9-e4f217ecccb1
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3317350309 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_p
assthru_mem_tl_intg_err.3317350309
Directory /workspace/14.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_same_csr_outstanding.758902426
Short name T438
Test name
Test status
Simulation time 4309623113 ps
CPU time 9.33 seconds
Started Apr 21 12:38:23 PM PDT 24
Finished Apr 21 12:38:32 PM PDT 24
Peak memory 210892 kb
Host smart-a78f703d-420a-44e1-8f50-f4e6e9116f1a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=758902426 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_c
trl_same_csr_outstanding.758902426
Directory /workspace/14.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_errors.1858454731
Short name T377
Test name
Test status
Simulation time 10376512276 ps
CPU time 17.91 seconds
Started Apr 21 12:38:24 PM PDT 24
Finished Apr 21 12:38:42 PM PDT 24
Peak memory 219096 kb
Host smart-1a685aec-4bf1-4a0e-8401-620bbb763d04
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1858454731 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_tl_errors.1858454731
Directory /workspace/14.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_intg_err.3158798172
Short name T130
Test name
Test status
Simulation time 498782289 ps
CPU time 38.53 seconds
Started Apr 21 12:38:18 PM PDT 24
Finished Apr 21 12:38:57 PM PDT 24
Peak memory 211468 kb
Host smart-d3424af9-39b6-43e1-a0fb-147c09436e92
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3158798172 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_tl_i
ntg_err.3158798172
Directory /workspace/14.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_mem_rw_with_rand_reset.2414674922
Short name T422
Test name
Test status
Simulation time 1934327689 ps
CPU time 15.05 seconds
Started Apr 21 12:38:26 PM PDT 24
Finished Apr 21 12:38:42 PM PDT 24
Peak memory 215876 kb
Host smart-f9dbc630-c11a-49a8-9d2f-4593bc9fa05a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2414674922 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 15.rom_ctrl_csr_mem_rw_with_rand_reset.2414674922
Directory /workspace/15.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_rw.1726001648
Short name T460
Test name
Test status
Simulation time 4349449990 ps
CPU time 16.83 seconds
Started Apr 21 12:38:15 PM PDT 24
Finished Apr 21 12:38:32 PM PDT 24
Peak memory 210984 kb
Host smart-0e8dde88-d7da-4030-b5ed-78c513fbb52a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1726001648 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_csr_rw.1726001648
Directory /workspace/15.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_passthru_mem_tl_intg_err.1157503120
Short name T88
Test name
Test status
Simulation time 12769682613 ps
CPU time 35.75 seconds
Started Apr 21 12:38:11 PM PDT 24
Finished Apr 21 12:38:53 PM PDT 24
Peak memory 210924 kb
Host smart-47e207d1-a904-45b9-89ea-1202489e8549
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1157503120 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_p
assthru_mem_tl_intg_err.1157503120
Directory /workspace/15.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_same_csr_outstanding.2287545043
Short name T414
Test name
Test status
Simulation time 1331527574 ps
CPU time 6.56 seconds
Started Apr 21 12:38:15 PM PDT 24
Finished Apr 21 12:38:22 PM PDT 24
Peak memory 210820 kb
Host smart-b8a38608-7a67-4fb1-a789-47bfcf61384b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2287545043 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_
ctrl_same_csr_outstanding.2287545043
Directory /workspace/15.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_errors.2399134394
Short name T367
Test name
Test status
Simulation time 532594353 ps
CPU time 9.41 seconds
Started Apr 21 12:38:22 PM PDT 24
Finished Apr 21 12:38:31 PM PDT 24
Peak memory 219016 kb
Host smart-c91ccd17-8e74-4b1b-aa93-17a31f757674
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2399134394 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_tl_errors.2399134394
Directory /workspace/15.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_mem_rw_with_rand_reset.1050151405
Short name T417
Test name
Test status
Simulation time 1419728552 ps
CPU time 9.69 seconds
Started Apr 21 12:38:28 PM PDT 24
Finished Apr 21 12:38:38 PM PDT 24
Peak memory 219020 kb
Host smart-4ed3dab2-f34f-47d6-9c92-5c029a65df55
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1050151405 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 16.rom_ctrl_csr_mem_rw_with_rand_reset.1050151405
Directory /workspace/16.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_rw.454093152
Short name T400
Test name
Test status
Simulation time 1531642633 ps
CPU time 12.71 seconds
Started Apr 21 12:38:21 PM PDT 24
Finished Apr 21 12:38:34 PM PDT 24
Peak memory 210884 kb
Host smart-39fd6470-6251-4fc3-a235-1a0e8dba2aa1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=454093152 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_csr_rw.454093152
Directory /workspace/16.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_passthru_mem_tl_intg_err.1854929961
Short name T86
Test name
Test status
Simulation time 50517837759 ps
CPU time 97.91 seconds
Started Apr 21 12:38:10 PM PDT 24
Finished Apr 21 12:39:48 PM PDT 24
Peak memory 211012 kb
Host smart-86dd010e-c1aa-4358-bf17-7d6b254ab27b
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1854929961 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_p
assthru_mem_tl_intg_err.1854929961
Directory /workspace/16.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_same_csr_outstanding.778400507
Short name T435
Test name
Test status
Simulation time 1072669283 ps
CPU time 10.42 seconds
Started Apr 21 12:38:19 PM PDT 24
Finished Apr 21 12:38:30 PM PDT 24
Peak memory 210716 kb
Host smart-9b70a529-c5ce-4c8c-97be-c532c4405615
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=778400507 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_c
trl_same_csr_outstanding.778400507
Directory /workspace/16.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_errors.1518097627
Short name T392
Test name
Test status
Simulation time 954693384 ps
CPU time 14.04 seconds
Started Apr 21 12:38:34 PM PDT 24
Finished Apr 21 12:38:49 PM PDT 24
Peak memory 215252 kb
Host smart-5216864f-5954-4777-b15a-f2e72918d80e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1518097627 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_tl_errors.1518097627
Directory /workspace/16.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_intg_err.2037098595
Short name T116
Test name
Test status
Simulation time 1945805886 ps
CPU time 71.07 seconds
Started Apr 21 12:38:11 PM PDT 24
Finished Apr 21 12:39:23 PM PDT 24
Peak memory 218724 kb
Host smart-d235744a-2661-4e76-aa58-c041b4cfa1fb
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2037098595 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_tl_i
ntg_err.2037098595
Directory /workspace/16.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_mem_rw_with_rand_reset.2588417823
Short name T426
Test name
Test status
Simulation time 710539353 ps
CPU time 5.33 seconds
Started Apr 21 12:38:33 PM PDT 24
Finished Apr 21 12:38:39 PM PDT 24
Peak memory 219052 kb
Host smart-0867cc0f-6db1-44ee-87a4-cea9993c4f65
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2588417823 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 17.rom_ctrl_csr_mem_rw_with_rand_reset.2588417823
Directory /workspace/17.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_rw.1475658005
Short name T443
Test name
Test status
Simulation time 3382654869 ps
CPU time 9.34 seconds
Started Apr 21 12:38:40 PM PDT 24
Finished Apr 21 12:38:49 PM PDT 24
Peak memory 210980 kb
Host smart-7a29925c-0b42-4c9a-afe0-cb70d317bc9b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1475658005 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_csr_rw.1475658005
Directory /workspace/17.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_passthru_mem_tl_intg_err.1306371673
Short name T77
Test name
Test status
Simulation time 8264267032 ps
CPU time 72.64 seconds
Started Apr 21 12:38:25 PM PDT 24
Finished Apr 21 12:39:38 PM PDT 24
Peak memory 210960 kb
Host smart-f3dcf1a2-3668-405d-b80c-dd076d7f618e
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1306371673 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_p
assthru_mem_tl_intg_err.1306371673
Directory /workspace/17.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_same_csr_outstanding.1902775419
Short name T107
Test name
Test status
Simulation time 168143832 ps
CPU time 4.27 seconds
Started Apr 21 12:38:24 PM PDT 24
Finished Apr 21 12:38:28 PM PDT 24
Peak memory 210780 kb
Host smart-a4a66a95-ba90-443a-b158-c4c2a8e905e3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1902775419 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_
ctrl_same_csr_outstanding.1902775419
Directory /workspace/17.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_errors.3577831562
Short name T386
Test name
Test status
Simulation time 191261926 ps
CPU time 6.49 seconds
Started Apr 21 12:38:27 PM PDT 24
Finished Apr 21 12:38:35 PM PDT 24
Peak memory 219136 kb
Host smart-be300712-661b-4b4b-bc4d-5dd0265f0b68
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3577831562 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_tl_errors.3577831562
Directory /workspace/17.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_intg_err.2239254797
Short name T126
Test name
Test status
Simulation time 1829113854 ps
CPU time 68.29 seconds
Started Apr 21 12:38:10 PM PDT 24
Finished Apr 21 12:39:19 PM PDT 24
Peak memory 210860 kb
Host smart-e0546154-c006-46cd-9e8d-09c74d702d41
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2239254797 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_tl_i
ntg_err.2239254797
Directory /workspace/17.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_mem_rw_with_rand_reset.1817197081
Short name T63
Test name
Test status
Simulation time 3990164079 ps
CPU time 16.01 seconds
Started Apr 21 12:38:05 PM PDT 24
Finished Apr 21 12:38:22 PM PDT 24
Peak memory 218924 kb
Host smart-b70e807f-a32d-4f75-be47-fd19c48a5dfe
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1817197081 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 18.rom_ctrl_csr_mem_rw_with_rand_reset.1817197081
Directory /workspace/18.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_rw.2222480633
Short name T425
Test name
Test status
Simulation time 822584824 ps
CPU time 5.33 seconds
Started Apr 21 12:38:04 PM PDT 24
Finished Apr 21 12:38:09 PM PDT 24
Peak memory 210868 kb
Host smart-c8d81bf4-90b9-40fb-b0fb-97981867cace
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2222480633 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_csr_rw.2222480633
Directory /workspace/18.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_passthru_mem_tl_intg_err.2292630935
Short name T423
Test name
Test status
Simulation time 3390028260 ps
CPU time 39.4 seconds
Started Apr 21 12:38:40 PM PDT 24
Finished Apr 21 12:39:20 PM PDT 24
Peak memory 210960 kb
Host smart-bc2b026f-ca24-45f8-ae86-baa6176ee6f8
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2292630935 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_p
assthru_mem_tl_intg_err.2292630935
Directory /workspace/18.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_same_csr_outstanding.2096356193
Short name T457
Test name
Test status
Simulation time 4538617764 ps
CPU time 7.27 seconds
Started Apr 21 12:38:13 PM PDT 24
Finished Apr 21 12:38:21 PM PDT 24
Peak memory 210616 kb
Host smart-945755b6-8f0a-41c6-a4c0-5afb74786e89
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2096356193 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_
ctrl_same_csr_outstanding.2096356193
Directory /workspace/18.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_errors.881990894
Short name T450
Test name
Test status
Simulation time 1314467623 ps
CPU time 10.16 seconds
Started Apr 21 12:38:17 PM PDT 24
Finished Apr 21 12:38:28 PM PDT 24
Peak memory 219020 kb
Host smart-29c266de-b095-4439-8712-c0606bcda03a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=881990894 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_tl_errors.881990894
Directory /workspace/18.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_intg_err.2595816250
Short name T127
Test name
Test status
Simulation time 232649518 ps
CPU time 68.02 seconds
Started Apr 21 12:38:21 PM PDT 24
Finished Apr 21 12:39:30 PM PDT 24
Peak memory 212960 kb
Host smart-2e210d53-eb84-4d60-a49a-4e9c5c6c83f3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2595816250 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_tl_i
ntg_err.2595816250
Directory /workspace/18.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_mem_rw_with_rand_reset.715465490
Short name T375
Test name
Test status
Simulation time 3268667691 ps
CPU time 9.25 seconds
Started Apr 21 12:38:16 PM PDT 24
Finished Apr 21 12:38:26 PM PDT 24
Peak memory 212148 kb
Host smart-6e7ff504-4b2d-4d8e-b785-7c649c8a1f34
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=715465490 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 19.rom_ctrl_csr_mem_rw_with_rand_reset.715465490
Directory /workspace/19.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_rw.3046700809
Short name T406
Test name
Test status
Simulation time 2157635852 ps
CPU time 14.95 seconds
Started Apr 21 12:38:26 PM PDT 24
Finished Apr 21 12:38:42 PM PDT 24
Peak memory 210952 kb
Host smart-20b36db0-3886-4904-af94-3671915b2f28
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3046700809 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_csr_rw.3046700809
Directory /workspace/19.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_passthru_mem_tl_intg_err.507310366
Short name T451
Test name
Test status
Simulation time 43429145338 ps
CPU time 82.23 seconds
Started Apr 21 12:38:08 PM PDT 24
Finished Apr 21 12:39:31 PM PDT 24
Peak memory 210884 kb
Host smart-549785b2-328c-44ba-8a02-b11defce4a05
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=507310366 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_pa
ssthru_mem_tl_intg_err.507310366
Directory /workspace/19.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_same_csr_outstanding.3802115641
Short name T440
Test name
Test status
Simulation time 836886781 ps
CPU time 7.16 seconds
Started Apr 21 12:38:13 PM PDT 24
Finished Apr 21 12:38:21 PM PDT 24
Peak memory 210888 kb
Host smart-1f19d1ec-9f2f-4a0c-84ec-b727794d9107
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3802115641 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_
ctrl_same_csr_outstanding.3802115641
Directory /workspace/19.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_errors.4247750364
Short name T380
Test name
Test status
Simulation time 5804775950 ps
CPU time 8.38 seconds
Started Apr 21 12:38:16 PM PDT 24
Finished Apr 21 12:38:25 PM PDT 24
Peak memory 219072 kb
Host smart-da951a4f-b8aa-4e4b-a74b-cdb392d610e7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4247750364 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_tl_errors.4247750364
Directory /workspace/19.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_intg_err.1801493108
Short name T124
Test name
Test status
Simulation time 393990565 ps
CPU time 36.46 seconds
Started Apr 21 12:38:21 PM PDT 24
Finished Apr 21 12:38:58 PM PDT 24
Peak memory 211392 kb
Host smart-0f73e598-63b9-4e51-809b-75a8178bafb9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1801493108 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_tl_i
ntg_err.1801493108
Directory /workspace/19.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_aliasing.465168319
Short name T76
Test name
Test status
Simulation time 6463932981 ps
CPU time 12.7 seconds
Started Apr 21 12:38:11 PM PDT 24
Finished Apr 21 12:38:25 PM PDT 24
Peak memory 210976 kb
Host smart-046b9171-ca87-494e-84c8-df84970bd2c4
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=465168319 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_alias
ing.465168319
Directory /workspace/2.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_bit_bash.892820606
Short name T412
Test name
Test status
Simulation time 8883484613 ps
CPU time 16.82 seconds
Started Apr 21 12:38:20 PM PDT 24
Finished Apr 21 12:38:37 PM PDT 24
Peak memory 210844 kb
Host smart-743ec5fa-6fc0-4856-94be-be0ae60962c8
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=892820606 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_bit_b
ash.892820606
Directory /workspace/2.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_hw_reset.283706879
Short name T447
Test name
Test status
Simulation time 2645692097 ps
CPU time 13.42 seconds
Started Apr 21 12:38:04 PM PDT 24
Finished Apr 21 12:38:17 PM PDT 24
Peak memory 210876 kb
Host smart-4f581ac6-1496-45cc-9b03-964e1e1eb397
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=283706879 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_hw_re
set.283706879
Directory /workspace/2.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_mem_rw_with_rand_reset.1274331678
Short name T384
Test name
Test status
Simulation time 3044960774 ps
CPU time 8.27 seconds
Started Apr 21 12:38:09 PM PDT 24
Finished Apr 21 12:38:17 PM PDT 24
Peak memory 212832 kb
Host smart-5b9e6412-c707-4073-a6f3-5c5df3e6912d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1274331678 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 2.rom_ctrl_csr_mem_rw_with_rand_reset.1274331678
Directory /workspace/2.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_rw.2173288941
Short name T394
Test name
Test status
Simulation time 1381110965 ps
CPU time 4.23 seconds
Started Apr 21 12:38:14 PM PDT 24
Finished Apr 21 12:38:19 PM PDT 24
Peak memory 210880 kb
Host smart-7ccd81fa-8037-4022-8112-aab42a984a10
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2173288941 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_rw.2173288941
Directory /workspace/2.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_partial_access.2050790386
Short name T371
Test name
Test status
Simulation time 3278640956 ps
CPU time 13.71 seconds
Started Apr 21 12:38:02 PM PDT 24
Finished Apr 21 12:38:16 PM PDT 24
Peak memory 210740 kb
Host smart-5cd5ae3e-aecb-41d6-a677-91e962bfb638
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2050790386 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctr
l_mem_partial_access.2050790386
Directory /workspace/2.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_walk.3778008675
Short name T379
Test name
Test status
Simulation time 653043151 ps
CPU time 4.77 seconds
Started Apr 21 12:38:23 PM PDT 24
Finished Apr 21 12:38:28 PM PDT 24
Peak memory 210760 kb
Host smart-3fad0d59-5c9f-43fb-953e-1ccbf7231e30
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3778008675 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_mem_walk
.3778008675
Directory /workspace/2.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_passthru_mem_tl_intg_err.2427101489
Short name T408
Test name
Test status
Simulation time 18459126945 ps
CPU time 45.26 seconds
Started Apr 21 12:38:16 PM PDT 24
Finished Apr 21 12:39:02 PM PDT 24
Peak memory 211012 kb
Host smart-caa39fe0-ac71-4a39-b906-b636af512645
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2427101489 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_pa
ssthru_mem_tl_intg_err.2427101489
Directory /workspace/2.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_same_csr_outstanding.899132744
Short name T448
Test name
Test status
Simulation time 813108140 ps
CPU time 5.86 seconds
Started Apr 21 12:38:09 PM PDT 24
Finished Apr 21 12:38:15 PM PDT 24
Peak memory 210784 kb
Host smart-a396d308-9627-4d37-ab66-4a35790288ff
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=899132744 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ct
rl_same_csr_outstanding.899132744
Directory /workspace/2.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_errors.2846164369
Short name T409
Test name
Test status
Simulation time 1309248398 ps
CPU time 8.69 seconds
Started Apr 21 12:38:11 PM PDT 24
Finished Apr 21 12:38:21 PM PDT 24
Peak memory 219044 kb
Host smart-f9e6f026-1261-4827-9330-01f33df96d86
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2846164369 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_tl_errors.2846164369
Directory /workspace/2.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_intg_err.3684481823
Short name T129
Test name
Test status
Simulation time 1754089458 ps
CPU time 45.55 seconds
Started Apr 21 12:37:49 PM PDT 24
Finished Apr 21 12:38:35 PM PDT 24
Peak memory 212256 kb
Host smart-f5db5d46-e322-4094-8468-ec7d3356e6fe
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3684481823 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_tl_in
tg_err.3684481823
Directory /workspace/2.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_aliasing.97226217
Short name T444
Test name
Test status
Simulation time 2035603004 ps
CPU time 15.67 seconds
Started Apr 21 12:38:34 PM PDT 24
Finished Apr 21 12:38:51 PM PDT 24
Peak memory 210804 kb
Host smart-9c78717e-3076-4730-9bf4-fc39780abe1f
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=97226217 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_aliasi
ng.97226217
Directory /workspace/3.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_bit_bash.3297815877
Short name T459
Test name
Test status
Simulation time 220582308 ps
CPU time 5.88 seconds
Started Apr 21 12:38:14 PM PDT 24
Finished Apr 21 12:38:20 PM PDT 24
Peak memory 210784 kb
Host smart-17c4d3fe-9dba-4c42-a97e-6fed97001b02
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3297815877 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_bit_
bash.3297815877
Directory /workspace/3.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_hw_reset.1009590632
Short name T420
Test name
Test status
Simulation time 526097631 ps
CPU time 9.87 seconds
Started Apr 21 12:38:21 PM PDT 24
Finished Apr 21 12:38:32 PM PDT 24
Peak memory 210804 kb
Host smart-fb554961-0434-4b2d-b0a1-6bfb92835b7a
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1009590632 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_hw_r
eset.1009590632
Directory /workspace/3.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_mem_rw_with_rand_reset.589310372
Short name T381
Test name
Test status
Simulation time 99831811 ps
CPU time 4.37 seconds
Started Apr 21 12:38:17 PM PDT 24
Finished Apr 21 12:38:22 PM PDT 24
Peak memory 212084 kb
Host smart-aed14e31-2594-4f2e-8865-2cf5fcda7a4f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=589310372 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 3.rom_ctrl_csr_mem_rw_with_rand_reset.589310372
Directory /workspace/3.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_rw.2871297341
Short name T112
Test name
Test status
Simulation time 88174847 ps
CPU time 4.38 seconds
Started Apr 21 12:38:08 PM PDT 24
Finished Apr 21 12:38:13 PM PDT 24
Peak memory 210820 kb
Host smart-fda9f212-ae29-4898-aa0c-325d74c2948c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2871297341 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_rw.2871297341
Directory /workspace/3.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_partial_access.55530800
Short name T369
Test name
Test status
Simulation time 461837844 ps
CPU time 7.15 seconds
Started Apr 21 12:37:46 PM PDT 24
Finished Apr 21 12:37:54 PM PDT 24
Peak memory 210620 kb
Host smart-dabab77f-c062-4b6c-ab75-5174d997ac8a
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=55530800 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_c
trl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_
mem_partial_access.55530800
Directory /workspace/3.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_walk.4075412800
Short name T372
Test name
Test status
Simulation time 88978272 ps
CPU time 4.17 seconds
Started Apr 21 12:38:06 PM PDT 24
Finished Apr 21 12:38:10 PM PDT 24
Peak memory 210720 kb
Host smart-f4807509-ea1c-4161-a309-fa005a005277
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4075412800 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_mem_walk
.4075412800
Directory /workspace/3.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_passthru_mem_tl_intg_err.315281344
Short name T70
Test name
Test status
Simulation time 6008666049 ps
CPU time 52.72 seconds
Started Apr 21 12:37:57 PM PDT 24
Finished Apr 21 12:38:50 PM PDT 24
Peak memory 211004 kb
Host smart-3ac235aa-dfc8-4421-b441-f6e68731a9cb
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=315281344 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_pas
sthru_mem_tl_intg_err.315281344
Directory /workspace/3.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_same_csr_outstanding.244455403
Short name T428
Test name
Test status
Simulation time 2088451465 ps
CPU time 16.07 seconds
Started Apr 21 12:38:17 PM PDT 24
Finished Apr 21 12:38:34 PM PDT 24
Peak memory 210888 kb
Host smart-01e20c80-9d65-4b56-b109-1203b7afe6b7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=244455403 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ct
rl_same_csr_outstanding.244455403
Directory /workspace/3.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_errors.1640305543
Short name T385
Test name
Test status
Simulation time 1063835389 ps
CPU time 10.27 seconds
Started Apr 21 12:37:55 PM PDT 24
Finished Apr 21 12:38:06 PM PDT 24
Peak memory 215216 kb
Host smart-95a951b8-3a9e-4c8e-be69-5218ba83724f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1640305543 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_tl_errors.1640305543
Directory /workspace/3.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_intg_err.2643554089
Short name T403
Test name
Test status
Simulation time 1990678395 ps
CPU time 42.94 seconds
Started Apr 21 12:38:10 PM PDT 24
Finished Apr 21 12:38:54 PM PDT 24
Peak memory 210796 kb
Host smart-718fec6d-bb73-41e0-a8bf-4abbe043fe39
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2643554089 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_tl_in
tg_err.2643554089
Directory /workspace/3.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_aliasing.1600628840
Short name T452
Test name
Test status
Simulation time 654333684 ps
CPU time 8.4 seconds
Started Apr 21 12:38:12 PM PDT 24
Finished Apr 21 12:38:21 PM PDT 24
Peak memory 210860 kb
Host smart-5135d77b-e6e5-4189-9850-06729164ae2c
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1600628840 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_alia
sing.1600628840
Directory /workspace/4.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_bit_bash.1705423768
Short name T461
Test name
Test status
Simulation time 2052923960 ps
CPU time 7.7 seconds
Started Apr 21 12:38:00 PM PDT 24
Finished Apr 21 12:38:08 PM PDT 24
Peak memory 210888 kb
Host smart-4aab00d7-c349-48bc-be91-ac21b2a3877f
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1705423768 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_bit_
bash.1705423768
Directory /workspace/4.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_hw_reset.2031863932
Short name T374
Test name
Test status
Simulation time 945060065 ps
CPU time 12.47 seconds
Started Apr 21 12:38:36 PM PDT 24
Finished Apr 21 12:38:49 PM PDT 24
Peak memory 210932 kb
Host smart-7d15a830-9fd5-424a-a66a-6f5fd200675f
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2031863932 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_hw_r
eset.2031863932
Directory /workspace/4.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_mem_rw_with_rand_reset.710912052
Short name T453
Test name
Test status
Simulation time 1417956327 ps
CPU time 8.95 seconds
Started Apr 21 12:38:16 PM PDT 24
Finished Apr 21 12:38:26 PM PDT 24
Peak memory 214384 kb
Host smart-a09798e5-c92c-40e7-a5c4-6b0c0d4dc17d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=710912052 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 4.rom_ctrl_csr_mem_rw_with_rand_reset.710912052
Directory /workspace/4.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_rw.1099398017
Short name T404
Test name
Test status
Simulation time 712108428 ps
CPU time 8.93 seconds
Started Apr 21 12:38:04 PM PDT 24
Finished Apr 21 12:38:14 PM PDT 24
Peak memory 210816 kb
Host smart-6964c110-b4ab-47ed-83d4-ea9ede8c3a71
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1099398017 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_rw.1099398017
Directory /workspace/4.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_partial_access.1448813843
Short name T370
Test name
Test status
Simulation time 114484519 ps
CPU time 4.13 seconds
Started Apr 21 12:38:27 PM PDT 24
Finished Apr 21 12:38:32 PM PDT 24
Peak memory 210656 kb
Host smart-bb92ee2f-933f-415c-81db-0aee6e2afbcf
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1448813843 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctr
l_mem_partial_access.1448813843
Directory /workspace/4.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_walk.2356269136
Short name T411
Test name
Test status
Simulation time 2087905104 ps
CPU time 16.08 seconds
Started Apr 21 12:38:07 PM PDT 24
Finished Apr 21 12:38:23 PM PDT 24
Peak memory 210832 kb
Host smart-b50ed0a0-179c-4246-8ff6-40256ca4bcf0
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2356269136 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_mem_walk
.2356269136
Directory /workspace/4.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_passthru_mem_tl_intg_err.3086858944
Short name T87
Test name
Test status
Simulation time 14077686611 ps
CPU time 58.72 seconds
Started Apr 21 12:37:55 PM PDT 24
Finished Apr 21 12:38:55 PM PDT 24
Peak memory 210900 kb
Host smart-70f1ed06-3b48-4655-8286-c1cd8968c7ba
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3086858944 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_pa
ssthru_mem_tl_intg_err.3086858944
Directory /workspace/4.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_same_csr_outstanding.2265745961
Short name T78
Test name
Test status
Simulation time 9445774549 ps
CPU time 12.58 seconds
Started Apr 21 12:38:08 PM PDT 24
Finished Apr 21 12:38:21 PM PDT 24
Peak memory 210792 kb
Host smart-20e2b6d3-cf3b-4aaf-b979-5af96bdd1250
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2265745961 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_c
trl_same_csr_outstanding.2265745961
Directory /workspace/4.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_errors.946902681
Short name T376
Test name
Test status
Simulation time 2237506124 ps
CPU time 12.13 seconds
Started Apr 21 12:38:19 PM PDT 24
Finished Apr 21 12:38:31 PM PDT 24
Peak memory 219432 kb
Host smart-c3717638-3a96-4aa6-9d9e-c720b1606ace
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=946902681 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_tl_errors.946902681
Directory /workspace/4.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_intg_err.339182198
Short name T119
Test name
Test status
Simulation time 2156591038 ps
CPU time 78.64 seconds
Started Apr 21 12:37:57 PM PDT 24
Finished Apr 21 12:39:22 PM PDT 24
Peak memory 211648 kb
Host smart-cc52632a-0980-42f4-a810-3fe0dd6bf24e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=339182198 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_tl_int
g_err.339182198
Directory /workspace/4.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_mem_rw_with_rand_reset.692472377
Short name T439
Test name
Test status
Simulation time 926680563 ps
CPU time 10.07 seconds
Started Apr 21 12:37:59 PM PDT 24
Finished Apr 21 12:38:09 PM PDT 24
Peak memory 214132 kb
Host smart-2cb0aace-de6c-45c5-978b-d79243d9e6c3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=692472377 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 5.rom_ctrl_csr_mem_rw_with_rand_reset.692472377
Directory /workspace/5.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_rw.1071441467
Short name T64
Test name
Test status
Simulation time 2198969734 ps
CPU time 16.65 seconds
Started Apr 21 12:38:32 PM PDT 24
Finished Apr 21 12:38:49 PM PDT 24
Peak memory 210880 kb
Host smart-888eac21-c593-4657-9c7f-4a7d7ffd8564
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1071441467 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_csr_rw.1071441467
Directory /workspace/5.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_passthru_mem_tl_intg_err.2126387895
Short name T432
Test name
Test status
Simulation time 33643187345 ps
CPU time 67.09 seconds
Started Apr 21 12:37:57 PM PDT 24
Finished Apr 21 12:39:04 PM PDT 24
Peak memory 210908 kb
Host smart-d979cd84-af37-4ad6-9eb6-471ce26f91a4
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2126387895 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_pa
ssthru_mem_tl_intg_err.2126387895
Directory /workspace/5.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_same_csr_outstanding.462007455
Short name T458
Test name
Test status
Simulation time 1770309376 ps
CPU time 15 seconds
Started Apr 21 12:38:21 PM PDT 24
Finished Apr 21 12:38:37 PM PDT 24
Peak memory 210760 kb
Host smart-3a54472e-7a67-47f3-9bd7-9b4f538f438b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=462007455 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ct
rl_same_csr_outstanding.462007455
Directory /workspace/5.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_errors.1131569951
Short name T378
Test name
Test status
Simulation time 1498166078 ps
CPU time 14.77 seconds
Started Apr 21 12:38:20 PM PDT 24
Finished Apr 21 12:38:35 PM PDT 24
Peak memory 215020 kb
Host smart-55a5edb8-252f-4c68-bea3-bfa3327ea311
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1131569951 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_tl_errors.1131569951
Directory /workspace/5.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_intg_err.1823794245
Short name T390
Test name
Test status
Simulation time 323835725 ps
CPU time 70.06 seconds
Started Apr 21 12:38:04 PM PDT 24
Finished Apr 21 12:39:14 PM PDT 24
Peak memory 210816 kb
Host smart-832871b5-ec11-4993-9c34-60e4c41d812b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1823794245 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_tl_in
tg_err.1823794245
Directory /workspace/5.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_mem_rw_with_rand_reset.2230169262
Short name T436
Test name
Test status
Simulation time 134384832 ps
CPU time 4.82 seconds
Started Apr 21 12:38:11 PM PDT 24
Finished Apr 21 12:38:16 PM PDT 24
Peak memory 214112 kb
Host smart-bc41d23b-229d-4518-9c55-81cfaac098f5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2230169262 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 6.rom_ctrl_csr_mem_rw_with_rand_reset.2230169262
Directory /workspace/6.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_rw.734762685
Short name T455
Test name
Test status
Simulation time 1031542935 ps
CPU time 10.34 seconds
Started Apr 21 12:38:14 PM PDT 24
Finished Apr 21 12:38:25 PM PDT 24
Peak memory 210760 kb
Host smart-2420bedd-8203-475d-9cbc-2bfff8f28063
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=734762685 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_csr_rw.734762685
Directory /workspace/6.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_passthru_mem_tl_intg_err.1539574098
Short name T402
Test name
Test status
Simulation time 15135158807 ps
CPU time 62.82 seconds
Started Apr 21 12:38:17 PM PDT 24
Finished Apr 21 12:39:20 PM PDT 24
Peak memory 211024 kb
Host smart-1ab1f8e5-405c-47cf-b790-308a21454a09
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1539574098 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_pa
ssthru_mem_tl_intg_err.1539574098
Directory /workspace/6.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_same_csr_outstanding.93199098
Short name T108
Test name
Test status
Simulation time 989231277 ps
CPU time 10.41 seconds
Started Apr 21 12:38:26 PM PDT 24
Finished Apr 21 12:38:37 PM PDT 24
Peak memory 210824 kb
Host smart-d8565184-26e2-410a-98df-1a0051da3e51
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=93199098 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctr
l_same_csr_outstanding.93199098
Directory /workspace/6.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_errors.590200140
Short name T368
Test name
Test status
Simulation time 1912893536 ps
CPU time 14.72 seconds
Started Apr 21 12:38:00 PM PDT 24
Finished Apr 21 12:38:15 PM PDT 24
Peak memory 219040 kb
Host smart-ae116676-ed2d-46bd-b5c1-0aa0ec646a15
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=590200140 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_tl_errors.590200140
Directory /workspace/6.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_intg_err.254288301
Short name T122
Test name
Test status
Simulation time 1486411687 ps
CPU time 38.86 seconds
Started Apr 21 12:38:06 PM PDT 24
Finished Apr 21 12:38:46 PM PDT 24
Peak memory 210112 kb
Host smart-fa19cd22-7312-4073-b579-b1caa6bced2c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=254288301 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_tl_int
g_err.254288301
Directory /workspace/6.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_mem_rw_with_rand_reset.2250544745
Short name T419
Test name
Test status
Simulation time 10343244674 ps
CPU time 9.92 seconds
Started Apr 21 12:38:13 PM PDT 24
Finished Apr 21 12:38:24 PM PDT 24
Peak memory 219076 kb
Host smart-e2c77312-6487-4226-80b1-d48b20360a46
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2250544745 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 7.rom_ctrl_csr_mem_rw_with_rand_reset.2250544745
Directory /workspace/7.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_rw.3604863573
Short name T69
Test name
Test status
Simulation time 1701982122 ps
CPU time 7.55 seconds
Started Apr 21 12:38:22 PM PDT 24
Finished Apr 21 12:38:30 PM PDT 24
Peak memory 210728 kb
Host smart-e297a6f4-4f70-4ce8-9ada-1f01b5b10c30
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3604863573 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_csr_rw.3604863573
Directory /workspace/7.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_passthru_mem_tl_intg_err.1067125572
Short name T91
Test name
Test status
Simulation time 17328962818 ps
CPU time 52.28 seconds
Started Apr 21 12:37:52 PM PDT 24
Finished Apr 21 12:38:44 PM PDT 24
Peak memory 210980 kb
Host smart-f07cff04-890f-4567-8396-7e194a2e14a4
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1067125572 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_pa
ssthru_mem_tl_intg_err.1067125572
Directory /workspace/7.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_same_csr_outstanding.3715182151
Short name T418
Test name
Test status
Simulation time 1684643726 ps
CPU time 9.55 seconds
Started Apr 21 12:37:50 PM PDT 24
Finished Apr 21 12:38:05 PM PDT 24
Peak memory 210916 kb
Host smart-d7dd48b6-3a98-41ec-9fcf-4ee3e542d8a9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3715182151 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_c
trl_same_csr_outstanding.3715182151
Directory /workspace/7.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_errors.1851275701
Short name T401
Test name
Test status
Simulation time 3974287530 ps
CPU time 17.73 seconds
Started Apr 21 12:38:27 PM PDT 24
Finished Apr 21 12:38:45 PM PDT 24
Peak memory 219204 kb
Host smart-8d99413e-63d9-4dac-98a9-db583a6bfefa
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1851275701 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_tl_errors.1851275701
Directory /workspace/7.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_intg_err.3689811813
Short name T59
Test name
Test status
Simulation time 468522729 ps
CPU time 36.52 seconds
Started Apr 21 12:38:25 PM PDT 24
Finished Apr 21 12:39:02 PM PDT 24
Peak memory 211800 kb
Host smart-cf9f1956-32fc-4352-85a0-29b4db9f3b6f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3689811813 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_tl_in
tg_err.3689811813
Directory /workspace/7.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_mem_rw_with_rand_reset.1625020393
Short name T430
Test name
Test status
Simulation time 3549819198 ps
CPU time 9.84 seconds
Started Apr 21 12:38:22 PM PDT 24
Finished Apr 21 12:38:32 PM PDT 24
Peak memory 213684 kb
Host smart-4e64f71a-ff1a-4a96-9750-59f1330d9c73
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1625020393 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 8.rom_ctrl_csr_mem_rw_with_rand_reset.1625020393
Directory /workspace/8.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_rw.1496426615
Short name T94
Test name
Test status
Simulation time 2048118776 ps
CPU time 7.47 seconds
Started Apr 21 12:38:04 PM PDT 24
Finished Apr 21 12:38:12 PM PDT 24
Peak memory 210828 kb
Host smart-17fc849e-fd6d-4d3e-9c28-b6430e5dd12a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1496426615 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_csr_rw.1496426615
Directory /workspace/8.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_same_csr_outstanding.3123944794
Short name T437
Test name
Test status
Simulation time 2379870812 ps
CPU time 11.75 seconds
Started Apr 21 12:38:18 PM PDT 24
Finished Apr 21 12:38:30 PM PDT 24
Peak memory 210876 kb
Host smart-59a976d7-7a83-48cc-ae72-1c16d1fb3a41
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3123944794 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_c
trl_same_csr_outstanding.3123944794
Directory /workspace/8.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_errors.1301112845
Short name T462
Test name
Test status
Simulation time 986004596 ps
CPU time 12.67 seconds
Started Apr 21 12:37:52 PM PDT 24
Finished Apr 21 12:38:05 PM PDT 24
Peak memory 215076 kb
Host smart-0ece398e-a2d2-474f-9e6c-000626d664f9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1301112845 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_tl_errors.1301112845
Directory /workspace/8.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_mem_rw_with_rand_reset.901480394
Short name T441
Test name
Test status
Simulation time 3916250436 ps
CPU time 16.4 seconds
Started Apr 21 12:38:13 PM PDT 24
Finished Apr 21 12:38:30 PM PDT 24
Peak memory 219200 kb
Host smart-9116b754-f5b7-47e7-951f-dd83bdd100d6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=901480394 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 9.rom_ctrl_csr_mem_rw_with_rand_reset.901480394
Directory /workspace/9.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_rw.1953761648
Short name T449
Test name
Test status
Simulation time 1177212357 ps
CPU time 8.23 seconds
Started Apr 21 12:38:26 PM PDT 24
Finished Apr 21 12:38:35 PM PDT 24
Peak memory 210920 kb
Host smart-eebbb793-ca16-47ea-a639-6d341cd87ffd
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1953761648 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_csr_rw.1953761648
Directory /workspace/9.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_passthru_mem_tl_intg_err.3011149695
Short name T396
Test name
Test status
Simulation time 992875368 ps
CPU time 32.9 seconds
Started Apr 21 12:38:04 PM PDT 24
Finished Apr 21 12:38:38 PM PDT 24
Peak memory 210852 kb
Host smart-cb2118f2-6767-4aad-b7d8-a76ac33151d8
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3011149695 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_pa
ssthru_mem_tl_intg_err.3011149695
Directory /workspace/9.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_same_csr_outstanding.3455550006
Short name T415
Test name
Test status
Simulation time 810692749 ps
CPU time 9.26 seconds
Started Apr 21 12:38:10 PM PDT 24
Finished Apr 21 12:38:20 PM PDT 24
Peak memory 210820 kb
Host smart-a5a1daa3-883c-4707-896c-9131b75779fc
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3455550006 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_c
trl_same_csr_outstanding.3455550006
Directory /workspace/9.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_errors.811723540
Short name T442
Test name
Test status
Simulation time 3927298777 ps
CPU time 12.32 seconds
Started Apr 21 12:38:07 PM PDT 24
Finished Apr 21 12:38:20 PM PDT 24
Peak memory 214972 kb
Host smart-59ecacc6-cd8c-43a8-bd3d-762813d5f6ad
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=811723540 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_tl_errors.811723540
Directory /workspace/9.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_intg_err.3506624951
Short name T120
Test name
Test status
Simulation time 1692796344 ps
CPU time 46.15 seconds
Started Apr 21 12:38:15 PM PDT 24
Finished Apr 21 12:39:01 PM PDT 24
Peak memory 211712 kb
Host smart-49708a5c-cf86-4231-895b-716bf58c2f88
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3506624951 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_tl_in
tg_err.3506624951
Directory /workspace/9.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/0.rom_ctrl_alert_test.1134201042
Short name T232
Test name
Test status
Simulation time 2887905170 ps
CPU time 7.49 seconds
Started Apr 21 12:23:54 PM PDT 24
Finished Apr 21 12:24:02 PM PDT 24
Peak memory 211756 kb
Host smart-a1764909-d47c-464c-a5d5-22b5d81eb838
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1134201042 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_alert_test.1134201042
Directory /workspace/0.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/0.rom_ctrl_corrupt_sig_fatal_chk.207230754
Short name T298
Test name
Test status
Simulation time 183792631803 ps
CPU time 448.27 seconds
Started Apr 21 12:23:52 PM PDT 24
Finished Apr 21 12:31:20 PM PDT 24
Peak memory 237324 kb
Host smart-1787c596-7974-4326-ac76-28c1fb06a446
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=207230754 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_co
rrupt_sig_fatal_chk.207230754
Directory /workspace/0.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/0.rom_ctrl_kmac_err_chk.4083237184
Short name T235
Test name
Test status
Simulation time 999449195 ps
CPU time 10.52 seconds
Started Apr 21 12:23:56 PM PDT 24
Finished Apr 21 12:24:07 PM PDT 24
Peak memory 212136 kb
Host smart-a7b6f153-cbd4-454c-9f48-b3d671deef22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4083237184 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_kmac_err_chk.4083237184
Directory /workspace/0.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/0.rom_ctrl_max_throughput_chk.1799397872
Short name T217
Test name
Test status
Simulation time 3878747283 ps
CPU time 14.22 seconds
Started Apr 21 12:23:31 PM PDT 24
Finished Apr 21 12:23:46 PM PDT 24
Peak memory 211660 kb
Host smart-45004d8a-bea9-4a46-83f4-869f919a99d7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1799397872 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_max_throughput_chk.1799397872
Directory /workspace/0.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/0.rom_ctrl_sec_cm.1693864249
Short name T38
Test name
Test status
Simulation time 473403262 ps
CPU time 98.73 seconds
Started Apr 21 12:24:09 PM PDT 24
Finished Apr 21 12:25:48 PM PDT 24
Peak memory 234292 kb
Host smart-011ae766-40b3-4078-a959-461740c106ce
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1693864249 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_sec_cm.1693864249
Directory /workspace/0.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/0.rom_ctrl_smoke.3501571855
Short name T281
Test name
Test status
Simulation time 1781790856 ps
CPU time 10.65 seconds
Started Apr 21 12:23:38 PM PDT 24
Finished Apr 21 12:23:49 PM PDT 24
Peak memory 219200 kb
Host smart-33b87c79-d7a4-4a9f-b2f5-f1398b499287
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3501571855 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_smoke.3501571855
Directory /workspace/0.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/0.rom_ctrl_stress_all.17437633
Short name T51
Test name
Test status
Simulation time 12464247292 ps
CPU time 32.76 seconds
Started Apr 21 12:23:51 PM PDT 24
Finished Apr 21 12:24:24 PM PDT 24
Peak memory 219808 kb
Host smart-9be7adf3-8bc2-434e-917c-baea58679625
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17437633 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +U
VM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n
ame 0.rom_ctrl_stress_all.17437633
Directory /workspace/0.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/0.rom_ctrl_stress_all_with_rand_reset.1593277017
Short name T58
Test name
Test status
Simulation time 24938686820 ps
CPU time 953.17 seconds
Started Apr 21 12:24:08 PM PDT 24
Finished Apr 21 12:40:02 PM PDT 24
Peak memory 229152 kb
Host smart-ba110635-bfeb-45cb-ae55-67f8cfd90ea4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1593277017 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_stress_all_with_rand_reset.1593277017
Directory /workspace/0.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.rom_ctrl_alert_test.316451880
Short name T163
Test name
Test status
Simulation time 334377082 ps
CPU time 4.33 seconds
Started Apr 21 12:23:34 PM PDT 24
Finished Apr 21 12:23:38 PM PDT 24
Peak memory 211640 kb
Host smart-a27b0d35-30bd-4cf6-bc8e-3761d0f61319
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=316451880 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_alert_test.316451880
Directory /workspace/1.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/1.rom_ctrl_corrupt_sig_fatal_chk.2604853065
Short name T49
Test name
Test status
Simulation time 40794685805 ps
CPU time 360.29 seconds
Started Apr 21 12:23:26 PM PDT 24
Finished Apr 21 12:29:27 PM PDT 24
Peak memory 230356 kb
Host smart-f73728d8-f530-4125-8c86-8d0f85868e39
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2604853065 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_c
orrupt_sig_fatal_chk.2604853065
Directory /workspace/1.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/1.rom_ctrl_kmac_err_chk.2979792432
Short name T215
Test name
Test status
Simulation time 4112445557 ps
CPU time 32.61 seconds
Started Apr 21 12:23:35 PM PDT 24
Finished Apr 21 12:24:08 PM PDT 24
Peak memory 212200 kb
Host smart-93dbbc41-233a-405f-9197-f54f545f76e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2979792432 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_kmac_err_chk.2979792432
Directory /workspace/1.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/1.rom_ctrl_max_throughput_chk.2334795181
Short name T140
Test name
Test status
Simulation time 1004435254 ps
CPU time 11.23 seconds
Started Apr 21 12:23:42 PM PDT 24
Finished Apr 21 12:23:53 PM PDT 24
Peak memory 211540 kb
Host smart-793a119f-4a1c-4a54-a08d-7913fc1d974b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2334795181 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_max_throughput_chk.2334795181
Directory /workspace/1.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/1.rom_ctrl_sec_cm.916618960
Short name T32
Test name
Test status
Simulation time 1569716264 ps
CPU time 59.41 seconds
Started Apr 21 12:23:54 PM PDT 24
Finished Apr 21 12:24:54 PM PDT 24
Peak memory 229864 kb
Host smart-17f8bea8-b9c6-46f8-8748-098d0914ade1
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=916618960 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_sec_cm.916618960
Directory /workspace/1.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/1.rom_ctrl_smoke.3714169458
Short name T85
Test name
Test status
Simulation time 2037381585 ps
CPU time 23.14 seconds
Started Apr 21 12:23:41 PM PDT 24
Finished Apr 21 12:24:04 PM PDT 24
Peak memory 215112 kb
Host smart-cfd0743a-cff7-4b5d-8126-3da8ad1ccccf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3714169458 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_smoke.3714169458
Directory /workspace/1.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/10.rom_ctrl_alert_test.1970708046
Short name T195
Test name
Test status
Simulation time 397393080 ps
CPU time 4.17 seconds
Started Apr 21 12:23:50 PM PDT 24
Finished Apr 21 12:24:00 PM PDT 24
Peak memory 211600 kb
Host smart-b846972b-9b03-46a9-a77f-1b862a465b9a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1970708046 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_alert_test.1970708046
Directory /workspace/10.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/10.rom_ctrl_corrupt_sig_fatal_chk.301600278
Short name T239
Test name
Test status
Simulation time 56065158511 ps
CPU time 142.14 seconds
Started Apr 21 12:23:54 PM PDT 24
Finished Apr 21 12:26:17 PM PDT 24
Peak memory 213084 kb
Host smart-0f913053-e2ad-470d-a4d5-a96afcce0f6b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=301600278 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_c
orrupt_sig_fatal_chk.301600278
Directory /workspace/10.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/10.rom_ctrl_kmac_err_chk.3295781428
Short name T242
Test name
Test status
Simulation time 11012338353 ps
CPU time 25.42 seconds
Started Apr 21 12:23:42 PM PDT 24
Finished Apr 21 12:24:08 PM PDT 24
Peak memory 212644 kb
Host smart-9e56b4b3-9c7b-41aa-ba57-8b87f1f11d7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3295781428 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_kmac_err_chk.3295781428
Directory /workspace/10.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/10.rom_ctrl_max_throughput_chk.2439373769
Short name T148
Test name
Test status
Simulation time 4202211416 ps
CPU time 16.87 seconds
Started Apr 21 12:23:39 PM PDT 24
Finished Apr 21 12:23:56 PM PDT 24
Peak memory 211572 kb
Host smart-6382bd3d-0f75-470b-a140-93ad66882c48
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2439373769 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_max_throughput_chk.2439373769
Directory /workspace/10.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/10.rom_ctrl_smoke.601325123
Short name T145
Test name
Test status
Simulation time 207445480 ps
CPU time 9.73 seconds
Started Apr 21 12:23:50 PM PDT 24
Finished Apr 21 12:24:05 PM PDT 24
Peak memory 219704 kb
Host smart-752e7a51-88a6-46e5-8cbf-c88749cd7a9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=601325123 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_smoke.601325123
Directory /workspace/10.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/10.rom_ctrl_stress_all.2176142753
Short name T196
Test name
Test status
Simulation time 5684416566 ps
CPU time 60.35 seconds
Started Apr 21 12:23:51 PM PDT 24
Finished Apr 21 12:24:52 PM PDT 24
Peak memory 217296 kb
Host smart-12f39702-e609-4590-9a13-67d7fe4eb1b4
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2176142753 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 10.rom_ctrl_stress_all.2176142753
Directory /workspace/10.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/11.rom_ctrl_alert_test.2175523485
Short name T212
Test name
Test status
Simulation time 346796577 ps
CPU time 4.17 seconds
Started Apr 21 12:23:52 PM PDT 24
Finished Apr 21 12:23:57 PM PDT 24
Peak memory 211656 kb
Host smart-8d0c7a15-e3d3-484c-9f41-45dda91d3283
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2175523485 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_alert_test.2175523485
Directory /workspace/11.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/11.rom_ctrl_corrupt_sig_fatal_chk.3027083901
Short name T352
Test name
Test status
Simulation time 4073124328 ps
CPU time 74.98 seconds
Started Apr 21 12:23:56 PM PDT 24
Finished Apr 21 12:25:12 PM PDT 24
Peak memory 225372 kb
Host smart-7cbb8c07-95d1-4122-84fa-6e96610e293e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3027083901 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_
corrupt_sig_fatal_chk.3027083901
Directory /workspace/11.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/11.rom_ctrl_kmac_err_chk.3982834041
Short name T194
Test name
Test status
Simulation time 3851975711 ps
CPU time 31.78 seconds
Started Apr 21 12:24:04 PM PDT 24
Finished Apr 21 12:24:36 PM PDT 24
Peak memory 212396 kb
Host smart-e4e21469-3fbd-4e49-8599-3a965d946d04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3982834041 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_kmac_err_chk.3982834041
Directory /workspace/11.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/11.rom_ctrl_max_throughput_chk.3823717475
Short name T7
Test name
Test status
Simulation time 193161381 ps
CPU time 5.66 seconds
Started Apr 21 12:23:53 PM PDT 24
Finished Apr 21 12:23:59 PM PDT 24
Peak memory 211524 kb
Host smart-56fbcc69-fa58-463d-9a03-8fd774c07ae0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3823717475 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_max_throughput_chk.3823717475
Directory /workspace/11.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/11.rom_ctrl_smoke.51890135
Short name T332
Test name
Test status
Simulation time 526892589 ps
CPU time 14.57 seconds
Started Apr 21 12:23:47 PM PDT 24
Finished Apr 21 12:24:02 PM PDT 24
Peak memory 213496 kb
Host smart-7c98625f-5542-434a-ad2b-7e92cb553758
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=51890135 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_smoke.51890135
Directory /workspace/11.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/11.rom_ctrl_stress_all.2461765245
Short name T339
Test name
Test status
Simulation time 21145067739 ps
CPU time 93.87 seconds
Started Apr 21 12:23:55 PM PDT 24
Finished Apr 21 12:25:29 PM PDT 24
Peak memory 219788 kb
Host smart-0ca5f17f-953b-4e79-90e6-6981aea24e49
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2461765245 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 11.rom_ctrl_stress_all.2461765245
Directory /workspace/11.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/12.rom_ctrl_alert_test.2340432790
Short name T231
Test name
Test status
Simulation time 88094971 ps
CPU time 4.17 seconds
Started Apr 21 12:24:04 PM PDT 24
Finished Apr 21 12:24:08 PM PDT 24
Peak memory 211656 kb
Host smart-b99e2919-f825-42db-8e57-4fa89d9f3fb4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2340432790 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_alert_test.2340432790
Directory /workspace/12.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/12.rom_ctrl_kmac_err_chk.1093466864
Short name T257
Test name
Test status
Simulation time 3101335194 ps
CPU time 26.61 seconds
Started Apr 21 12:24:02 PM PDT 24
Finished Apr 21 12:24:29 PM PDT 24
Peak memory 212548 kb
Host smart-fd4803e5-363b-4730-bf60-216f4b06cd1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1093466864 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_kmac_err_chk.1093466864
Directory /workspace/12.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/12.rom_ctrl_max_throughput_chk.1392224832
Short name T300
Test name
Test status
Simulation time 386337900 ps
CPU time 5.67 seconds
Started Apr 21 12:24:00 PM PDT 24
Finished Apr 21 12:24:06 PM PDT 24
Peak memory 211528 kb
Host smart-2eebe3ef-7607-4096-a595-2f573598c03f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1392224832 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_max_throughput_chk.1392224832
Directory /workspace/12.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/12.rom_ctrl_smoke.1766273259
Short name T162
Test name
Test status
Simulation time 8550323389 ps
CPU time 36.38 seconds
Started Apr 21 12:24:04 PM PDT 24
Finished Apr 21 12:24:41 PM PDT 24
Peak memory 219792 kb
Host smart-9b3a2b53-7a40-45b0-a677-c96ed2748d33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1766273259 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_smoke.1766273259
Directory /workspace/12.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/12.rom_ctrl_stress_all.2393113737
Short name T99
Test name
Test status
Simulation time 2667805561 ps
CPU time 30.12 seconds
Started Apr 21 12:24:04 PM PDT 24
Finished Apr 21 12:24:34 PM PDT 24
Peak memory 219796 kb
Host smart-373cd70b-c342-418e-a821-8185c6db23dd
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2393113737 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 12.rom_ctrl_stress_all.2393113737
Directory /workspace/12.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/13.rom_ctrl_alert_test.3015929933
Short name T308
Test name
Test status
Simulation time 40790343717 ps
CPU time 16.81 seconds
Started Apr 21 12:23:57 PM PDT 24
Finished Apr 21 12:24:14 PM PDT 24
Peak memory 211760 kb
Host smart-fe2934e9-8bb3-4a45-9d36-6215b8372bb2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3015929933 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_alert_test.3015929933
Directory /workspace/13.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/13.rom_ctrl_corrupt_sig_fatal_chk.3030063008
Short name T277
Test name
Test status
Simulation time 28758282484 ps
CPU time 236.25 seconds
Started Apr 21 12:23:54 PM PDT 24
Finished Apr 21 12:27:51 PM PDT 24
Peak memory 237184 kb
Host smart-b43d8ef2-27f4-4a73-b179-c7e57db69f1d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3030063008 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_
corrupt_sig_fatal_chk.3030063008
Directory /workspace/13.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/13.rom_ctrl_kmac_err_chk.879720128
Short name T279
Test name
Test status
Simulation time 668014819 ps
CPU time 9.58 seconds
Started Apr 21 12:23:54 PM PDT 24
Finished Apr 21 12:24:05 PM PDT 24
Peak memory 212956 kb
Host smart-b123c488-230d-4d12-acfb-4b74ecf884f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=879720128 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_kmac_err_chk.879720128
Directory /workspace/13.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/13.rom_ctrl_max_throughput_chk.1498692493
Short name T278
Test name
Test status
Simulation time 3401993761 ps
CPU time 15.85 seconds
Started Apr 21 12:24:01 PM PDT 24
Finished Apr 21 12:24:17 PM PDT 24
Peak memory 211664 kb
Host smart-0a12a0c7-10ee-4c83-aecf-eec5253e7f92
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1498692493 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_max_throughput_chk.1498692493
Directory /workspace/13.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/13.rom_ctrl_stress_all.1459164979
Short name T105
Test name
Test status
Simulation time 8062323375 ps
CPU time 76.59 seconds
Started Apr 21 12:24:08 PM PDT 24
Finished Apr 21 12:25:30 PM PDT 24
Peak memory 217288 kb
Host smart-180204b4-cdce-4377-a7fb-c794abefeba0
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1459164979 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 13.rom_ctrl_stress_all.1459164979
Directory /workspace/13.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/13.rom_ctrl_stress_all_with_rand_reset.153561752
Short name T55
Test name
Test status
Simulation time 263320712114 ps
CPU time 1801.68 seconds
Started Apr 21 12:23:56 PM PDT 24
Finished Apr 21 12:53:58 PM PDT 24
Peak memory 237176 kb
Host smart-c14fd9c2-7bdd-43ca-a4f8-7257190c76a7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=153561752 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_stress_all_with_rand_reset.153561752
Directory /workspace/13.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/14.rom_ctrl_alert_test.3717487792
Short name T236
Test name
Test status
Simulation time 5538242506 ps
CPU time 10.47 seconds
Started Apr 21 12:24:07 PM PDT 24
Finished Apr 21 12:24:17 PM PDT 24
Peak memory 211776 kb
Host smart-66b6f830-0109-4966-a9d8-8b1668422e96
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3717487792 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_alert_test.3717487792
Directory /workspace/14.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/14.rom_ctrl_corrupt_sig_fatal_chk.4031536701
Short name T161
Test name
Test status
Simulation time 12767437676 ps
CPU time 143.85 seconds
Started Apr 21 12:24:05 PM PDT 24
Finished Apr 21 12:26:29 PM PDT 24
Peak memory 229008 kb
Host smart-7b32a451-d86e-4777-b134-6011f401c967
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4031536701 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_
corrupt_sig_fatal_chk.4031536701
Directory /workspace/14.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/14.rom_ctrl_max_throughput_chk.2994375524
Short name T223
Test name
Test status
Simulation time 356587650 ps
CPU time 6.72 seconds
Started Apr 21 12:23:58 PM PDT 24
Finished Apr 21 12:24:05 PM PDT 24
Peak memory 211524 kb
Host smart-f30478d6-0c40-4024-9af2-7f73a6133ba8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2994375524 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_max_throughput_chk.2994375524
Directory /workspace/14.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/14.rom_ctrl_smoke.1912030298
Short name T338
Test name
Test status
Simulation time 1495058480 ps
CPU time 9.87 seconds
Started Apr 21 12:23:59 PM PDT 24
Finished Apr 21 12:24:09 PM PDT 24
Peak memory 214016 kb
Host smart-8f1c09a8-6d28-4ac1-9d53-cd3c4070b401
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1912030298 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_smoke.1912030298
Directory /workspace/14.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/14.rom_ctrl_stress_all.1732653891
Short name T211
Test name
Test status
Simulation time 12752471054 ps
CPU time 31.2 seconds
Started Apr 21 12:24:11 PM PDT 24
Finished Apr 21 12:24:42 PM PDT 24
Peak memory 219828 kb
Host smart-ad987743-40d1-4ce4-95bf-615c7db4928c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1732653891 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 14.rom_ctrl_stress_all.1732653891
Directory /workspace/14.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/14.rom_ctrl_stress_all_with_rand_reset.3305435728
Short name T54
Test name
Test status
Simulation time 25162640030 ps
CPU time 523.01 seconds
Started Apr 21 12:24:04 PM PDT 24
Finished Apr 21 12:32:48 PM PDT 24
Peak memory 233904 kb
Host smart-acb4bca6-0e6d-403b-85a0-99baebf909e9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3305435728 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_stress_all_with_rand_reset.3305435728
Directory /workspace/14.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/15.rom_ctrl_alert_test.3016532097
Short name T184
Test name
Test status
Simulation time 1148657310 ps
CPU time 6.25 seconds
Started Apr 21 12:24:00 PM PDT 24
Finished Apr 21 12:24:06 PM PDT 24
Peak memory 211640 kb
Host smart-2edf2281-3b23-4bee-a422-3c10d436d668
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3016532097 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_alert_test.3016532097
Directory /workspace/15.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/15.rom_ctrl_corrupt_sig_fatal_chk.382825899
Short name T43
Test name
Test status
Simulation time 24162546834 ps
CPU time 255.03 seconds
Started Apr 21 12:24:08 PM PDT 24
Finished Apr 21 12:28:23 PM PDT 24
Peak memory 228616 kb
Host smart-562957ff-0894-4450-9ae0-79cb57320e43
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=382825899 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_c
orrupt_sig_fatal_chk.382825899
Directory /workspace/15.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/15.rom_ctrl_kmac_err_chk.60378484
Short name T353
Test name
Test status
Simulation time 25163308863 ps
CPU time 34.85 seconds
Started Apr 21 12:24:13 PM PDT 24
Finished Apr 21 12:24:48 PM PDT 24
Peak memory 212840 kb
Host smart-fa96a6d4-754b-4283-ae58-e69f74b92634
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=60378484 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_kmac_err_chk.60378484
Directory /workspace/15.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/15.rom_ctrl_max_throughput_chk.3460803953
Short name T299
Test name
Test status
Simulation time 380907384 ps
CPU time 5.42 seconds
Started Apr 21 12:23:56 PM PDT 24
Finished Apr 21 12:24:02 PM PDT 24
Peak memory 211512 kb
Host smart-3fb24630-1b39-4e4b-9aaa-80a8b66b19ee
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3460803953 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_max_throughput_chk.3460803953
Directory /workspace/15.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/15.rom_ctrl_smoke.3918469823
Short name T138
Test name
Test status
Simulation time 19946082355 ps
CPU time 24.95 seconds
Started Apr 21 12:24:20 PM PDT 24
Finished Apr 21 12:24:45 PM PDT 24
Peak memory 219828 kb
Host smart-c94cd696-d188-4500-bf98-2c70820c11ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3918469823 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_smoke.3918469823
Directory /workspace/15.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/15.rom_ctrl_stress_all.1156721721
Short name T40
Test name
Test status
Simulation time 2718989207 ps
CPU time 34.03 seconds
Started Apr 21 12:23:50 PM PDT 24
Finished Apr 21 12:24:30 PM PDT 24
Peak memory 219932 kb
Host smart-21be0bdc-d23e-4349-ab60-a8cb57c1b999
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1156721721 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 15.rom_ctrl_stress_all.1156721721
Directory /workspace/15.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/16.rom_ctrl_alert_test.2312034400
Short name T237
Test name
Test status
Simulation time 4636960409 ps
CPU time 10.62 seconds
Started Apr 21 12:24:17 PM PDT 24
Finished Apr 21 12:24:28 PM PDT 24
Peak memory 211828 kb
Host smart-4738c39b-d824-485a-9587-38f4a2f5ce2b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2312034400 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_alert_test.2312034400
Directory /workspace/16.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/16.rom_ctrl_corrupt_sig_fatal_chk.3082482944
Short name T328
Test name
Test status
Simulation time 1739216510 ps
CPU time 96.44 seconds
Started Apr 21 12:24:01 PM PDT 24
Finished Apr 21 12:25:37 PM PDT 24
Peak memory 238144 kb
Host smart-19747ab7-fcc9-4b7f-9bea-1a49cf095ea6
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3082482944 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_
corrupt_sig_fatal_chk.3082482944
Directory /workspace/16.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/16.rom_ctrl_kmac_err_chk.150807191
Short name T364
Test name
Test status
Simulation time 1153702942 ps
CPU time 16.36 seconds
Started Apr 21 12:24:06 PM PDT 24
Finished Apr 21 12:24:23 PM PDT 24
Peak memory 212856 kb
Host smart-9cad1cc3-1915-4799-bdd7-36a6a43b9711
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=150807191 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_kmac_err_chk.150807191
Directory /workspace/16.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/16.rom_ctrl_max_throughput_chk.3257394622
Short name T143
Test name
Test status
Simulation time 97657184 ps
CPU time 5.59 seconds
Started Apr 21 12:24:05 PM PDT 24
Finished Apr 21 12:24:11 PM PDT 24
Peak memory 211476 kb
Host smart-f7b30588-22c0-4b06-9d52-7add52249b1b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3257394622 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_max_throughput_chk.3257394622
Directory /workspace/16.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/16.rom_ctrl_smoke.3263012694
Short name T267
Test name
Test status
Simulation time 752565349 ps
CPU time 10.11 seconds
Started Apr 21 12:24:04 PM PDT 24
Finished Apr 21 12:24:15 PM PDT 24
Peak memory 219716 kb
Host smart-8396fe12-6b17-4ed4-807e-16ed5d3f1dea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3263012694 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_smoke.3263012694
Directory /workspace/16.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/16.rom_ctrl_stress_all.1526523048
Short name T315
Test name
Test status
Simulation time 1773288634 ps
CPU time 17.15 seconds
Started Apr 21 12:24:07 PM PDT 24
Finished Apr 21 12:24:24 PM PDT 24
Peak memory 212092 kb
Host smart-43083f75-e601-4483-9459-ccc55fab1c7e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1526523048 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 16.rom_ctrl_stress_all.1526523048
Directory /workspace/16.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/17.rom_ctrl_alert_test.1134915421
Short name T151
Test name
Test status
Simulation time 85763346 ps
CPU time 4.25 seconds
Started Apr 21 12:23:57 PM PDT 24
Finished Apr 21 12:24:01 PM PDT 24
Peak memory 211628 kb
Host smart-3f275cee-3ccb-4632-9411-b6c495b71d2e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1134915421 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_alert_test.1134915421
Directory /workspace/17.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/17.rom_ctrl_corrupt_sig_fatal_chk.1039778603
Short name T191
Test name
Test status
Simulation time 139491592197 ps
CPU time 378.18 seconds
Started Apr 21 12:24:08 PM PDT 24
Finished Apr 21 12:30:27 PM PDT 24
Peak memory 241780 kb
Host smart-4b12023c-b17b-41eb-b678-4a9bf98635c2
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1039778603 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_
corrupt_sig_fatal_chk.1039778603
Directory /workspace/17.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/17.rom_ctrl_kmac_err_chk.3511163326
Short name T219
Test name
Test status
Simulation time 3480033314 ps
CPU time 30.33 seconds
Started Apr 21 12:23:55 PM PDT 24
Finished Apr 21 12:24:26 PM PDT 24
Peak memory 212356 kb
Host smart-12bf1b6b-2c98-47a0-95fd-af58eb473808
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3511163326 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_kmac_err_chk.3511163326
Directory /workspace/17.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/17.rom_ctrl_max_throughput_chk.2128095205
Short name T102
Test name
Test status
Simulation time 10412844864 ps
CPU time 14.68 seconds
Started Apr 21 12:23:56 PM PDT 24
Finished Apr 21 12:24:11 PM PDT 24
Peak memory 211640 kb
Host smart-067169a9-1457-4c52-abaa-d0a6c66a25bf
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2128095205 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_max_throughput_chk.2128095205
Directory /workspace/17.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/17.rom_ctrl_smoke.532377528
Short name T337
Test name
Test status
Simulation time 44163918262 ps
CPU time 35.77 seconds
Started Apr 21 12:24:25 PM PDT 24
Finished Apr 21 12:25:01 PM PDT 24
Peak memory 214300 kb
Host smart-38321cc7-bb86-4638-ba48-37ffb398ddbc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=532377528 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_smoke.532377528
Directory /workspace/17.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/17.rom_ctrl_stress_all.2386190843
Short name T243
Test name
Test status
Simulation time 3248739910 ps
CPU time 21.44 seconds
Started Apr 21 12:23:55 PM PDT 24
Finished Apr 21 12:24:17 PM PDT 24
Peak memory 214604 kb
Host smart-5d10dc87-8d64-47a6-91fd-dd0e222f5b55
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2386190843 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 17.rom_ctrl_stress_all.2386190843
Directory /workspace/17.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/18.rom_ctrl_alert_test.812206829
Short name T226
Test name
Test status
Simulation time 90106751 ps
CPU time 4.23 seconds
Started Apr 21 12:24:19 PM PDT 24
Finished Apr 21 12:24:23 PM PDT 24
Peak memory 211760 kb
Host smart-9c821af9-2492-4559-b6b5-0a3af0c06b84
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=812206829 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_alert_test.812206829
Directory /workspace/18.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/18.rom_ctrl_corrupt_sig_fatal_chk.598410345
Short name T29
Test name
Test status
Simulation time 68107421801 ps
CPU time 171.49 seconds
Started Apr 21 12:23:57 PM PDT 24
Finished Apr 21 12:26:49 PM PDT 24
Peak memory 220084 kb
Host smart-3c54e599-6156-4097-b1b1-aca72a2a65f2
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=598410345 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_c
orrupt_sig_fatal_chk.598410345
Directory /workspace/18.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/18.rom_ctrl_kmac_err_chk.2122159945
Short name T248
Test name
Test status
Simulation time 2256181523 ps
CPU time 23.22 seconds
Started Apr 21 12:24:07 PM PDT 24
Finished Apr 21 12:24:30 PM PDT 24
Peak memory 212376 kb
Host smart-9dc112bd-7c74-406d-8c1c-f9a5fecaedf1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2122159945 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_kmac_err_chk.2122159945
Directory /workspace/18.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/18.rom_ctrl_max_throughput_chk.78737774
Short name T201
Test name
Test status
Simulation time 5455676939 ps
CPU time 13.81 seconds
Started Apr 21 12:24:06 PM PDT 24
Finished Apr 21 12:24:20 PM PDT 24
Peak memory 211632 kb
Host smart-1bfc3f26-cbee-448e-a1bc-b020bc07a0f8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=78737774 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_max_throughput_chk.78737774
Directory /workspace/18.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/18.rom_ctrl_stress_all.680906427
Short name T348
Test name
Test status
Simulation time 2140773105 ps
CPU time 27.85 seconds
Started Apr 21 12:23:55 PM PDT 24
Finished Apr 21 12:24:28 PM PDT 24
Peak memory 213432 kb
Host smart-cd1c857f-c776-4d78-8a36-007c1aedb7ce
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=680906427 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 18.rom_ctrl_stress_all.680906427
Directory /workspace/18.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/19.rom_ctrl_alert_test.720274640
Short name T225
Test name
Test status
Simulation time 334540194 ps
CPU time 6.24 seconds
Started Apr 21 12:24:09 PM PDT 24
Finished Apr 21 12:24:15 PM PDT 24
Peak memory 211616 kb
Host smart-23bcb3e3-55d1-4145-b8da-5ac22b2ebf79
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=720274640 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_alert_test.720274640
Directory /workspace/19.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/19.rom_ctrl_corrupt_sig_fatal_chk.904906784
Short name T101
Test name
Test status
Simulation time 46730294164 ps
CPU time 253.13 seconds
Started Apr 21 12:24:08 PM PDT 24
Finished Apr 21 12:28:22 PM PDT 24
Peak memory 237228 kb
Host smart-407b3b54-ae87-428e-8bab-ce74db3b6513
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=904906784 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_c
orrupt_sig_fatal_chk.904906784
Directory /workspace/19.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/19.rom_ctrl_max_throughput_chk.1971244641
Short name T347
Test name
Test status
Simulation time 2349013386 ps
CPU time 12.15 seconds
Started Apr 21 12:24:10 PM PDT 24
Finished Apr 21 12:24:23 PM PDT 24
Peak memory 211656 kb
Host smart-fdb5a0c9-51f1-438e-b63e-767dd362c41a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1971244641 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_max_throughput_chk.1971244641
Directory /workspace/19.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/19.rom_ctrl_smoke.1439195177
Short name T155
Test name
Test status
Simulation time 22787571008 ps
CPU time 26.53 seconds
Started Apr 21 12:24:11 PM PDT 24
Finished Apr 21 12:24:38 PM PDT 24
Peak memory 214584 kb
Host smart-b7d5a6f9-30cc-44a9-b3c5-390ff7fc6b29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1439195177 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_smoke.1439195177
Directory /workspace/19.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/19.rom_ctrl_stress_all.1429298269
Short name T172
Test name
Test status
Simulation time 1258021843 ps
CPU time 29.76 seconds
Started Apr 21 12:24:04 PM PDT 24
Finished Apr 21 12:24:34 PM PDT 24
Peak memory 216808 kb
Host smart-0a963911-583a-4758-a801-c2562f90c019
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1429298269 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 19.rom_ctrl_stress_all.1429298269
Directory /workspace/19.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/19.rom_ctrl_stress_all_with_rand_reset.3488385614
Short name T17
Test name
Test status
Simulation time 39972883249 ps
CPU time 3994.77 seconds
Started Apr 21 12:24:06 PM PDT 24
Finished Apr 21 01:30:42 PM PDT 24
Peak memory 230024 kb
Host smart-07878351-4c94-49f6-b320-3817c1274080
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3488385614 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_stress_all_with_rand_reset.3488385614
Directory /workspace/19.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.rom_ctrl_alert_test.3441540489
Short name T160
Test name
Test status
Simulation time 683537034 ps
CPU time 6.36 seconds
Started Apr 21 12:23:55 PM PDT 24
Finished Apr 21 12:24:02 PM PDT 24
Peak memory 211636 kb
Host smart-e48e65f6-5c54-41aa-b690-2d871679e138
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3441540489 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_alert_test.3441540489
Directory /workspace/2.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/2.rom_ctrl_corrupt_sig_fatal_chk.2325546976
Short name T27
Test name
Test status
Simulation time 104871261394 ps
CPU time 153.61 seconds
Started Apr 21 12:23:37 PM PDT 24
Finished Apr 21 12:26:11 PM PDT 24
Peak memory 228040 kb
Host smart-39a1e323-83d8-455b-818a-83b49d6ffeec
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2325546976 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_c
orrupt_sig_fatal_chk.2325546976
Directory /workspace/2.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/2.rom_ctrl_kmac_err_chk.2877115334
Short name T181
Test name
Test status
Simulation time 3117681620 ps
CPU time 27.84 seconds
Started Apr 21 12:23:51 PM PDT 24
Finished Apr 21 12:24:19 PM PDT 24
Peak memory 212328 kb
Host smart-30ce1f19-f162-4e46-af36-0cdf53054aca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2877115334 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_kmac_err_chk.2877115334
Directory /workspace/2.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/2.rom_ctrl_max_throughput_chk.11063356
Short name T97
Test name
Test status
Simulation time 3861614021 ps
CPU time 15.62 seconds
Started Apr 21 12:23:39 PM PDT 24
Finished Apr 21 12:23:55 PM PDT 24
Peak memory 211468 kb
Host smart-0b5bc653-2e4b-4080-9ae1-68c656a36db6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=11063356 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_max_throughput_chk.11063356
Directory /workspace/2.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/2.rom_ctrl_sec_cm.3566943075
Short name T33
Test name
Test status
Simulation time 1740642322 ps
CPU time 56.05 seconds
Started Apr 21 12:23:29 PM PDT 24
Finished Apr 21 12:24:25 PM PDT 24
Peak memory 236808 kb
Host smart-f36c75c2-abe2-496f-bbdc-aad0d2d029c5
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3566943075 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_sec_cm.3566943075
Directory /workspace/2.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/2.rom_ctrl_smoke.526664332
Short name T178
Test name
Test status
Simulation time 3844474665 ps
CPU time 12.31 seconds
Started Apr 21 12:23:33 PM PDT 24
Finished Apr 21 12:23:46 PM PDT 24
Peak memory 219820 kb
Host smart-dc406d3b-9d49-4dba-a82b-0e90d294b8b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=526664332 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_smoke.526664332
Directory /workspace/2.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/2.rom_ctrl_stress_all.2728343070
Short name T169
Test name
Test status
Simulation time 32200404228 ps
CPU time 76.3 seconds
Started Apr 21 12:23:39 PM PDT 24
Finished Apr 21 12:24:56 PM PDT 24
Peak memory 219828 kb
Host smart-f42714f7-a6c6-4251-80ee-c522a70f2ec6
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2728343070 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 2.rom_ctrl_stress_all.2728343070
Directory /workspace/2.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/20.rom_ctrl_alert_test.622842438
Short name T247
Test name
Test status
Simulation time 3799980984 ps
CPU time 15.49 seconds
Started Apr 21 12:24:12 PM PDT 24
Finished Apr 21 12:24:27 PM PDT 24
Peak memory 211788 kb
Host smart-55bfec2d-76ac-43b3-988b-fa6755efabfd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=622842438 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_alert_test.622842438
Directory /workspace/20.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/20.rom_ctrl_corrupt_sig_fatal_chk.2273907120
Short name T222
Test name
Test status
Simulation time 61668816097 ps
CPU time 344.3 seconds
Started Apr 21 12:24:12 PM PDT 24
Finished Apr 21 12:29:57 PM PDT 24
Peak memory 238628 kb
Host smart-0436c060-e0e0-47fe-ab6c-bc323c2da9e5
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2273907120 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_
corrupt_sig_fatal_chk.2273907120
Directory /workspace/20.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/20.rom_ctrl_kmac_err_chk.459681643
Short name T158
Test name
Test status
Simulation time 7848616594 ps
CPU time 30.32 seconds
Started Apr 21 12:24:05 PM PDT 24
Finished Apr 21 12:24:36 PM PDT 24
Peak memory 212624 kb
Host smart-0186b96a-58de-45fb-8848-535e912cb08b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=459681643 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_kmac_err_chk.459681643
Directory /workspace/20.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/20.rom_ctrl_max_throughput_chk.2505990128
Short name T250
Test name
Test status
Simulation time 443273818 ps
CPU time 8.05 seconds
Started Apr 21 12:24:08 PM PDT 24
Finished Apr 21 12:24:16 PM PDT 24
Peak memory 211548 kb
Host smart-681ce9ee-6e8a-41c6-ac5f-8d4115800688
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2505990128 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_max_throughput_chk.2505990128
Directory /workspace/20.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/20.rom_ctrl_smoke.3923955803
Short name T343
Test name
Test status
Simulation time 5648577330 ps
CPU time 15.57 seconds
Started Apr 21 12:24:16 PM PDT 24
Finished Apr 21 12:24:33 PM PDT 24
Peak memory 214304 kb
Host smart-4242fc5a-45e8-46b1-a73b-0eb6eaa2fcda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3923955803 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_smoke.3923955803
Directory /workspace/20.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/20.rom_ctrl_stress_all.3258102424
Short name T286
Test name
Test status
Simulation time 1765747960 ps
CPU time 28.7 seconds
Started Apr 21 12:24:10 PM PDT 24
Finished Apr 21 12:24:39 PM PDT 24
Peak memory 214740 kb
Host smart-7a74562b-a6fa-4516-ad32-b4856cd4bafc
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3258102424 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 20.rom_ctrl_stress_all.3258102424
Directory /workspace/20.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/21.rom_ctrl_alert_test.3730222746
Short name T42
Test name
Test status
Simulation time 347139893 ps
CPU time 4.23 seconds
Started Apr 21 12:24:21 PM PDT 24
Finished Apr 21 12:24:25 PM PDT 24
Peak memory 211660 kb
Host smart-41cf40d8-6512-4571-9ed2-95a97ec1fb16
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3730222746 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_alert_test.3730222746
Directory /workspace/21.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/21.rom_ctrl_corrupt_sig_fatal_chk.3002785735
Short name T316
Test name
Test status
Simulation time 41631209837 ps
CPU time 191.36 seconds
Started Apr 21 12:24:13 PM PDT 24
Finished Apr 21 12:27:25 PM PDT 24
Peak memory 229812 kb
Host smart-9932bc32-e617-46cc-b3ad-e33fccb65109
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3002785735 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_
corrupt_sig_fatal_chk.3002785735
Directory /workspace/21.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/21.rom_ctrl_kmac_err_chk.2483836934
Short name T209
Test name
Test status
Simulation time 168491926 ps
CPU time 9.85 seconds
Started Apr 21 12:24:04 PM PDT 24
Finished Apr 21 12:24:14 PM PDT 24
Peak memory 212416 kb
Host smart-47c22f62-b24e-497a-9e3e-58bcb52944e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2483836934 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_kmac_err_chk.2483836934
Directory /workspace/21.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/21.rom_ctrl_max_throughput_chk.1919393483
Short name T255
Test name
Test status
Simulation time 1595874461 ps
CPU time 14.49 seconds
Started Apr 21 12:24:15 PM PDT 24
Finished Apr 21 12:24:30 PM PDT 24
Peak memory 211440 kb
Host smart-e9a7e2f1-019c-49a3-98ce-83f88e189899
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1919393483 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_max_throughput_chk.1919393483
Directory /workspace/21.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/21.rom_ctrl_smoke.18357711
Short name T295
Test name
Test status
Simulation time 861837131 ps
CPU time 15.69 seconds
Started Apr 21 12:24:33 PM PDT 24
Finished Apr 21 12:24:50 PM PDT 24
Peak memory 214212 kb
Host smart-3cfede00-7705-41b6-9a09-8df7c7ad832f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=18357711 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_smoke.18357711
Directory /workspace/21.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/21.rom_ctrl_stress_all.1153777346
Short name T146
Test name
Test status
Simulation time 919556252 ps
CPU time 21.1 seconds
Started Apr 21 12:24:12 PM PDT 24
Finished Apr 21 12:24:33 PM PDT 24
Peak memory 219700 kb
Host smart-fe8c7fed-d4e7-46b4-8208-3a4712e09128
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1153777346 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 21.rom_ctrl_stress_all.1153777346
Directory /workspace/21.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/22.rom_ctrl_alert_test.3920266751
Short name T335
Test name
Test status
Simulation time 4421853391 ps
CPU time 10.61 seconds
Started Apr 21 12:24:19 PM PDT 24
Finished Apr 21 12:24:30 PM PDT 24
Peak memory 211800 kb
Host smart-ff798e91-adae-4887-8fc9-554245da2391
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3920266751 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_alert_test.3920266751
Directory /workspace/22.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/22.rom_ctrl_corrupt_sig_fatal_chk.1565035168
Short name T244
Test name
Test status
Simulation time 20079519895 ps
CPU time 219.78 seconds
Started Apr 21 12:24:11 PM PDT 24
Finished Apr 21 12:27:51 PM PDT 24
Peak memory 237548 kb
Host smart-39f63ca1-b50d-4c67-a7fa-08f7527f034d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1565035168 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_
corrupt_sig_fatal_chk.1565035168
Directory /workspace/22.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/22.rom_ctrl_kmac_err_chk.1196471763
Short name T285
Test name
Test status
Simulation time 4751129143 ps
CPU time 22.81 seconds
Started Apr 21 12:24:07 PM PDT 24
Finished Apr 21 12:24:30 PM PDT 24
Peak memory 212700 kb
Host smart-539f7db4-7a8d-4c86-b56c-af634faeac23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1196471763 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_kmac_err_chk.1196471763
Directory /workspace/22.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/22.rom_ctrl_max_throughput_chk.17647783
Short name T246
Test name
Test status
Simulation time 3786843482 ps
CPU time 11.22 seconds
Started Apr 21 12:24:08 PM PDT 24
Finished Apr 21 12:24:20 PM PDT 24
Peak memory 210864 kb
Host smart-b0993ade-59b0-4be6-9423-55873abbcd7f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=17647783 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_max_throughput_chk.17647783
Directory /workspace/22.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/22.rom_ctrl_smoke.2159934217
Short name T44
Test name
Test status
Simulation time 355970215 ps
CPU time 9.83 seconds
Started Apr 21 12:24:08 PM PDT 24
Finished Apr 21 12:24:19 PM PDT 24
Peak memory 219692 kb
Host smart-c8373e08-bf00-4491-b7a7-5ff16543b9d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2159934217 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_smoke.2159934217
Directory /workspace/22.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/22.rom_ctrl_stress_all.3535897000
Short name T258
Test name
Test status
Simulation time 1068177145 ps
CPU time 15 seconds
Started Apr 21 12:24:12 PM PDT 24
Finished Apr 21 12:24:27 PM PDT 24
Peak memory 215344 kb
Host smart-4d5ee647-4e3a-4943-a997-26eccc9ad401
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3535897000 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 22.rom_ctrl_stress_all.3535897000
Directory /workspace/22.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/23.rom_ctrl_alert_test.1562107042
Short name T173
Test name
Test status
Simulation time 3603823336 ps
CPU time 14.72 seconds
Started Apr 21 12:24:11 PM PDT 24
Finished Apr 21 12:24:26 PM PDT 24
Peak memory 211880 kb
Host smart-a86d10f0-fc3a-4783-be63-1249675444b0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1562107042 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_alert_test.1562107042
Directory /workspace/23.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/23.rom_ctrl_corrupt_sig_fatal_chk.1000551735
Short name T24
Test name
Test status
Simulation time 43051110828 ps
CPU time 385.21 seconds
Started Apr 21 12:24:06 PM PDT 24
Finished Apr 21 12:30:31 PM PDT 24
Peak memory 229080 kb
Host smart-bd04c047-8296-4e1f-ab01-ab35c32c9562
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1000551735 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_
corrupt_sig_fatal_chk.1000551735
Directory /workspace/23.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/23.rom_ctrl_kmac_err_chk.1545644429
Short name T142
Test name
Test status
Simulation time 8040254433 ps
CPU time 31.96 seconds
Started Apr 21 12:24:16 PM PDT 24
Finished Apr 21 12:24:49 PM PDT 24
Peak memory 212448 kb
Host smart-f6e710eb-35e9-4253-9e1c-df66da266063
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1545644429 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_kmac_err_chk.1545644429
Directory /workspace/23.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/23.rom_ctrl_max_throughput_chk.2397297921
Short name T202
Test name
Test status
Simulation time 2939617215 ps
CPU time 9.49 seconds
Started Apr 21 12:24:07 PM PDT 24
Finished Apr 21 12:24:17 PM PDT 24
Peak memory 211640 kb
Host smart-d66e3b6a-3b55-4657-b35c-8c0a9e1d3f59
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2397297921 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_max_throughput_chk.2397297921
Directory /workspace/23.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/23.rom_ctrl_smoke.4001522683
Short name T79
Test name
Test status
Simulation time 17170375187 ps
CPU time 35.62 seconds
Started Apr 21 12:24:23 PM PDT 24
Finished Apr 21 12:24:59 PM PDT 24
Peak memory 219848 kb
Host smart-e8a8fa92-e856-46dd-8039-a17e2fe0c81b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4001522683 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_smoke.4001522683
Directory /workspace/23.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/23.rom_ctrl_stress_all.1396610497
Short name T318
Test name
Test status
Simulation time 5918444732 ps
CPU time 21 seconds
Started Apr 21 12:24:03 PM PDT 24
Finished Apr 21 12:24:25 PM PDT 24
Peak memory 219840 kb
Host smart-39003a77-129a-4536-a366-72a82bc4cc45
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1396610497 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 23.rom_ctrl_stress_all.1396610497
Directory /workspace/23.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/24.rom_ctrl_alert_test.718454719
Short name T321
Test name
Test status
Simulation time 4119864274 ps
CPU time 8.04 seconds
Started Apr 21 12:24:30 PM PDT 24
Finished Apr 21 12:24:39 PM PDT 24
Peak memory 211756 kb
Host smart-6a349e62-36dd-41b6-b361-43e0fdffcb75
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=718454719 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_alert_test.718454719
Directory /workspace/24.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/24.rom_ctrl_kmac_err_chk.2595173333
Short name T1
Test name
Test status
Simulation time 5471628032 ps
CPU time 18.08 seconds
Started Apr 21 12:24:18 PM PDT 24
Finished Apr 21 12:24:36 PM PDT 24
Peak memory 213136 kb
Host smart-23692bac-8728-4f25-b711-0382351c9df5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2595173333 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_kmac_err_chk.2595173333
Directory /workspace/24.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/24.rom_ctrl_max_throughput_chk.3280022044
Short name T270
Test name
Test status
Simulation time 1704775332 ps
CPU time 9.87 seconds
Started Apr 21 12:24:15 PM PDT 24
Finished Apr 21 12:24:25 PM PDT 24
Peak memory 211516 kb
Host smart-ebdd9640-37cd-4016-bfb7-a34ce784588b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3280022044 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_max_throughput_chk.3280022044
Directory /workspace/24.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/24.rom_ctrl_smoke.1580520450
Short name T41
Test name
Test status
Simulation time 7890716580 ps
CPU time 31.6 seconds
Started Apr 21 12:24:14 PM PDT 24
Finished Apr 21 12:24:46 PM PDT 24
Peak memory 214584 kb
Host smart-388d7d9d-2aa5-4041-a518-1840bb1fabf9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1580520450 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_smoke.1580520450
Directory /workspace/24.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/24.rom_ctrl_stress_all.3350199958
Short name T186
Test name
Test status
Simulation time 1075885188 ps
CPU time 21.92 seconds
Started Apr 21 12:24:08 PM PDT 24
Finished Apr 21 12:24:30 PM PDT 24
Peak memory 219684 kb
Host smart-0a22056a-2129-4b72-9ee3-5d4e65b95984
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3350199958 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 24.rom_ctrl_stress_all.3350199958
Directory /workspace/24.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/25.rom_ctrl_alert_test.538748225
Short name T66
Test name
Test status
Simulation time 2411747912 ps
CPU time 7.03 seconds
Started Apr 21 12:24:32 PM PDT 24
Finished Apr 21 12:24:39 PM PDT 24
Peak memory 211768 kb
Host smart-277555a3-2258-435b-961a-586abb2dff44
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=538748225 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_alert_test.538748225
Directory /workspace/25.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/25.rom_ctrl_corrupt_sig_fatal_chk.2130369666
Short name T354
Test name
Test status
Simulation time 3166027971 ps
CPU time 163.25 seconds
Started Apr 21 12:24:17 PM PDT 24
Finished Apr 21 12:27:00 PM PDT 24
Peak memory 234172 kb
Host smart-92088943-da1b-42b3-8a14-3ba83095e843
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2130369666 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_
corrupt_sig_fatal_chk.2130369666
Directory /workspace/25.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/25.rom_ctrl_kmac_err_chk.3866340080
Short name T291
Test name
Test status
Simulation time 17006571270 ps
CPU time 27.11 seconds
Started Apr 21 12:24:13 PM PDT 24
Finished Apr 21 12:24:41 PM PDT 24
Peak memory 212608 kb
Host smart-42018bd6-1394-4cb8-93a7-a0962c514f3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3866340080 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_kmac_err_chk.3866340080
Directory /workspace/25.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/25.rom_ctrl_max_throughput_chk.3392776150
Short name T189
Test name
Test status
Simulation time 618228888 ps
CPU time 5.52 seconds
Started Apr 21 12:24:29 PM PDT 24
Finished Apr 21 12:24:35 PM PDT 24
Peak memory 211548 kb
Host smart-7db93eb5-df35-48ff-9c68-52aefa9bed5b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3392776150 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_max_throughput_chk.3392776150
Directory /workspace/25.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/25.rom_ctrl_smoke.2636385292
Short name T193
Test name
Test status
Simulation time 3177223938 ps
CPU time 27.31 seconds
Started Apr 21 12:24:06 PM PDT 24
Finished Apr 21 12:24:34 PM PDT 24
Peak memory 213768 kb
Host smart-38a34c00-ce2d-478c-a2d8-55cb3382f6ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2636385292 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_smoke.2636385292
Directory /workspace/25.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/25.rom_ctrl_stress_all.3907728232
Short name T80
Test name
Test status
Simulation time 16304506347 ps
CPU time 39.11 seconds
Started Apr 21 12:24:16 PM PDT 24
Finished Apr 21 12:24:55 PM PDT 24
Peak memory 219256 kb
Host smart-3a792048-2eba-4b52-83ce-bbadce2bec81
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3907728232 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 25.rom_ctrl_stress_all.3907728232
Directory /workspace/25.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/25.rom_ctrl_stress_all_with_rand_reset.74647176
Short name T53
Test name
Test status
Simulation time 103268102363 ps
CPU time 1077.04 seconds
Started Apr 21 12:24:14 PM PDT 24
Finished Apr 21 12:42:11 PM PDT 24
Peak memory 233352 kb
Host smart-c703a479-0df9-45b8-ba01-6c405633a482
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74647176 -assert nopos
tproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_stress_all_with_rand_reset.74647176
Directory /workspace/25.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/26.rom_ctrl_alert_test.2697741813
Short name T168
Test name
Test status
Simulation time 7730763266 ps
CPU time 12.46 seconds
Started Apr 21 12:24:31 PM PDT 24
Finished Apr 21 12:24:44 PM PDT 24
Peak memory 211760 kb
Host smart-1acbb010-1702-4a7d-9197-685666b4a022
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2697741813 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_alert_test.2697741813
Directory /workspace/26.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/26.rom_ctrl_corrupt_sig_fatal_chk.3087743209
Short name T47
Test name
Test status
Simulation time 1923282673 ps
CPU time 122.45 seconds
Started Apr 21 12:24:21 PM PDT 24
Finished Apr 21 12:26:24 PM PDT 24
Peak memory 230680 kb
Host smart-4c4af546-0dce-4b55-b1b0-328b677eff84
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3087743209 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_
corrupt_sig_fatal_chk.3087743209
Directory /workspace/26.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/26.rom_ctrl_kmac_err_chk.2628813489
Short name T164
Test name
Test status
Simulation time 2557134560 ps
CPU time 24.57 seconds
Started Apr 21 12:24:27 PM PDT 24
Finished Apr 21 12:24:52 PM PDT 24
Peak memory 212480 kb
Host smart-d51170e4-3762-4c32-ac78-f0356810bbab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2628813489 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_kmac_err_chk.2628813489
Directory /workspace/26.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/26.rom_ctrl_max_throughput_chk.1033018476
Short name T360
Test name
Test status
Simulation time 98038304 ps
CPU time 5.5 seconds
Started Apr 21 12:24:51 PM PDT 24
Finished Apr 21 12:24:57 PM PDT 24
Peak memory 211664 kb
Host smart-896d92f6-67a8-4d67-b2d2-7686b043aecc
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1033018476 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_max_throughput_chk.1033018476
Directory /workspace/26.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/26.rom_ctrl_smoke.3152326433
Short name T260
Test name
Test status
Simulation time 3345929021 ps
CPU time 20.28 seconds
Started Apr 21 12:24:10 PM PDT 24
Finished Apr 21 12:24:31 PM PDT 24
Peak memory 213540 kb
Host smart-a35aeb4c-5280-4ca2-b7fb-5e5a5017616f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3152326433 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_smoke.3152326433
Directory /workspace/26.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/26.rom_ctrl_stress_all.141408520
Short name T134
Test name
Test status
Simulation time 283445065 ps
CPU time 15.75 seconds
Started Apr 21 12:24:10 PM PDT 24
Finished Apr 21 12:24:26 PM PDT 24
Peak memory 219756 kb
Host smart-e0d2cf30-b753-45c8-8a98-2d9833dd4c66
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=141408520 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 26.rom_ctrl_stress_all.141408520
Directory /workspace/26.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/27.rom_ctrl_alert_test.1419001901
Short name T269
Test name
Test status
Simulation time 435922750 ps
CPU time 7.12 seconds
Started Apr 21 12:24:52 PM PDT 24
Finished Apr 21 12:25:00 PM PDT 24
Peak memory 211736 kb
Host smart-e9d65616-c334-4513-a75a-0ecfdcb58efb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1419001901 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_alert_test.1419001901
Directory /workspace/27.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/27.rom_ctrl_corrupt_sig_fatal_chk.3285795293
Short name T229
Test name
Test status
Simulation time 162128429332 ps
CPU time 249.32 seconds
Started Apr 21 12:24:12 PM PDT 24
Finished Apr 21 12:28:22 PM PDT 24
Peak memory 230056 kb
Host smart-0f4b1f53-5f57-4bc8-8a1c-8944e110a180
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3285795293 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_
corrupt_sig_fatal_chk.3285795293
Directory /workspace/27.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/27.rom_ctrl_kmac_err_chk.604618038
Short name T25
Test name
Test status
Simulation time 2989935029 ps
CPU time 26.54 seconds
Started Apr 21 12:24:19 PM PDT 24
Finished Apr 21 12:24:46 PM PDT 24
Peak memory 211632 kb
Host smart-2a64c7a6-b98e-485e-950f-39758c1f1af3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=604618038 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_kmac_err_chk.604618038
Directory /workspace/27.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/27.rom_ctrl_max_throughput_chk.1729625408
Short name T6
Test name
Test status
Simulation time 6017902885 ps
CPU time 13.51 seconds
Started Apr 21 12:24:15 PM PDT 24
Finished Apr 21 12:24:29 PM PDT 24
Peak memory 211644 kb
Host smart-5d099ff3-4588-4941-9540-2d7b3d5f9238
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1729625408 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_max_throughput_chk.1729625408
Directory /workspace/27.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/27.rom_ctrl_smoke.1855802257
Short name T84
Test name
Test status
Simulation time 4350971113 ps
CPU time 45.36 seconds
Started Apr 21 12:24:16 PM PDT 24
Finished Apr 21 12:25:02 PM PDT 24
Peak memory 213616 kb
Host smart-6ea10768-bb68-4dae-967c-e6cc49f83eb5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1855802257 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_smoke.1855802257
Directory /workspace/27.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/27.rom_ctrl_stress_all.3510797202
Short name T133
Test name
Test status
Simulation time 30609765326 ps
CPU time 28.86 seconds
Started Apr 21 12:24:36 PM PDT 24
Finished Apr 21 12:25:05 PM PDT 24
Peak memory 219940 kb
Host smart-0896332c-40fd-44a2-ba43-9c150d7f4bc5
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3510797202 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 27.rom_ctrl_stress_all.3510797202
Directory /workspace/27.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/28.rom_ctrl_alert_test.125531329
Short name T141
Test name
Test status
Simulation time 7504115332 ps
CPU time 15.57 seconds
Started Apr 21 12:24:30 PM PDT 24
Finished Apr 21 12:24:46 PM PDT 24
Peak memory 211756 kb
Host smart-ccc65938-8395-4bad-9200-c67ed2bd7ae2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=125531329 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_alert_test.125531329
Directory /workspace/28.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/28.rom_ctrl_corrupt_sig_fatal_chk.3969848568
Short name T252
Test name
Test status
Simulation time 48040934485 ps
CPU time 428.04 seconds
Started Apr 21 12:24:13 PM PDT 24
Finished Apr 21 12:31:21 PM PDT 24
Peak memory 228944 kb
Host smart-67d784dd-f79a-40c7-836f-a1148733e6e9
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3969848568 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_
corrupt_sig_fatal_chk.3969848568
Directory /workspace/28.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/28.rom_ctrl_kmac_err_chk.3957416010
Short name T139
Test name
Test status
Simulation time 168520987 ps
CPU time 9.21 seconds
Started Apr 21 12:24:58 PM PDT 24
Finished Apr 21 12:25:08 PM PDT 24
Peak memory 212180 kb
Host smart-b42d50b0-0786-49c0-bea9-67d810bb56c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3957416010 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_kmac_err_chk.3957416010
Directory /workspace/28.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/28.rom_ctrl_max_throughput_chk.2468930923
Short name T224
Test name
Test status
Simulation time 2885673343 ps
CPU time 13.31 seconds
Started Apr 21 12:24:34 PM PDT 24
Finished Apr 21 12:24:48 PM PDT 24
Peak memory 211668 kb
Host smart-4993090c-d2b9-4e37-8c0a-f26b941dbd40
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2468930923 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_max_throughput_chk.2468930923
Directory /workspace/28.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/28.rom_ctrl_smoke.1543714821
Short name T144
Test name
Test status
Simulation time 2212256857 ps
CPU time 16.18 seconds
Started Apr 21 12:24:39 PM PDT 24
Finished Apr 21 12:24:56 PM PDT 24
Peak memory 219824 kb
Host smart-ef6f738b-2e5a-4bce-a97c-b00ed1ea59cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1543714821 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_smoke.1543714821
Directory /workspace/28.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/28.rom_ctrl_stress_all.1836802565
Short name T292
Test name
Test status
Simulation time 20243251104 ps
CPU time 43.01 seconds
Started Apr 21 12:24:48 PM PDT 24
Finished Apr 21 12:25:31 PM PDT 24
Peak memory 219824 kb
Host smart-6c560c61-2a6b-46b3-b4f1-5b015bb338d5
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1836802565 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 28.rom_ctrl_stress_all.1836802565
Directory /workspace/28.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/29.rom_ctrl_alert_test.3144111718
Short name T305
Test name
Test status
Simulation time 347018377 ps
CPU time 6.78 seconds
Started Apr 21 12:24:27 PM PDT 24
Finished Apr 21 12:24:35 PM PDT 24
Peak memory 211672 kb
Host smart-7acfa0a6-7ec8-4d59-b9ac-84072aef08b7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3144111718 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_alert_test.3144111718
Directory /workspace/29.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/29.rom_ctrl_corrupt_sig_fatal_chk.2167261040
Short name T48
Test name
Test status
Simulation time 17548817007 ps
CPU time 118.26 seconds
Started Apr 21 12:24:51 PM PDT 24
Finished Apr 21 12:26:51 PM PDT 24
Peak memory 238252 kb
Host smart-29dfb276-98b9-4d62-96ef-681526fc7a7d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2167261040 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_
corrupt_sig_fatal_chk.2167261040
Directory /workspace/29.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/29.rom_ctrl_kmac_err_chk.2680166621
Short name T52
Test name
Test status
Simulation time 2991619961 ps
CPU time 27.57 seconds
Started Apr 21 12:24:09 PM PDT 24
Finished Apr 21 12:24:37 PM PDT 24
Peak memory 212056 kb
Host smart-edba7e73-883f-4553-904c-013b8757a4d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2680166621 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_kmac_err_chk.2680166621
Directory /workspace/29.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/29.rom_ctrl_max_throughput_chk.2041914195
Short name T256
Test name
Test status
Simulation time 344891602 ps
CPU time 5.13 seconds
Started Apr 21 12:24:46 PM PDT 24
Finished Apr 21 12:24:52 PM PDT 24
Peak memory 211536 kb
Host smart-9667e7d4-33df-43ef-be99-1a80bd9c9a61
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2041914195 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_max_throughput_chk.2041914195
Directory /workspace/29.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/29.rom_ctrl_smoke.983409610
Short name T4
Test name
Test status
Simulation time 10364363569 ps
CPU time 24.42 seconds
Started Apr 21 12:24:45 PM PDT 24
Finished Apr 21 12:25:10 PM PDT 24
Peak memory 214472 kb
Host smart-c17f1668-333e-4ca4-b045-6ea7d34a33fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=983409610 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_smoke.983409610
Directory /workspace/29.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/29.rom_ctrl_stress_all.2396385865
Short name T327
Test name
Test status
Simulation time 120521950828 ps
CPU time 84.06 seconds
Started Apr 21 12:24:29 PM PDT 24
Finished Apr 21 12:25:54 PM PDT 24
Peak memory 219804 kb
Host smart-3fd1ddd7-6faa-484c-a004-ed21452386e0
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2396385865 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 29.rom_ctrl_stress_all.2396385865
Directory /workspace/29.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/3.rom_ctrl_alert_test.2394040403
Short name T319
Test name
Test status
Simulation time 5477440438 ps
CPU time 11.97 seconds
Started Apr 21 12:23:37 PM PDT 24
Finished Apr 21 12:23:49 PM PDT 24
Peak memory 211700 kb
Host smart-a781809f-8ae8-4ffd-95be-6d08250786bc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2394040403 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_alert_test.2394040403
Directory /workspace/3.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/3.rom_ctrl_corrupt_sig_fatal_chk.3822468537
Short name T330
Test name
Test status
Simulation time 89092866572 ps
CPU time 230.63 seconds
Started Apr 21 12:24:08 PM PDT 24
Finished Apr 21 12:27:59 PM PDT 24
Peak memory 230032 kb
Host smart-5f46f9aa-4814-47d5-8c0a-2c3f7e11063c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3822468537 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_c
orrupt_sig_fatal_chk.3822468537
Directory /workspace/3.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/3.rom_ctrl_kmac_err_chk.3030864131
Short name T311
Test name
Test status
Simulation time 173770707 ps
CPU time 9.07 seconds
Started Apr 21 12:23:45 PM PDT 24
Finished Apr 21 12:23:54 PM PDT 24
Peak memory 212320 kb
Host smart-c0bbe198-7dfd-46c6-9d01-a92bd8782d8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3030864131 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_kmac_err_chk.3030864131
Directory /workspace/3.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/3.rom_ctrl_max_throughput_chk.329603831
Short name T210
Test name
Test status
Simulation time 8604106504 ps
CPU time 14.9 seconds
Started Apr 21 12:23:36 PM PDT 24
Finished Apr 21 12:23:51 PM PDT 24
Peak memory 211596 kb
Host smart-96760572-7374-41b0-9b92-d2bbc1218162
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=329603831 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_max_throughput_chk.329603831
Directory /workspace/3.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/3.rom_ctrl_smoke.2719086520
Short name T350
Test name
Test status
Simulation time 2429074391 ps
CPU time 16.86 seconds
Started Apr 21 12:23:35 PM PDT 24
Finished Apr 21 12:23:52 PM PDT 24
Peak memory 214028 kb
Host smart-1789bdfc-db76-4156-b1a0-5d522592945d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2719086520 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_smoke.2719086520
Directory /workspace/3.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/3.rom_ctrl_stress_all.3458395552
Short name T167
Test name
Test status
Simulation time 2189090772 ps
CPU time 23.08 seconds
Started Apr 21 12:23:53 PM PDT 24
Finished Apr 21 12:24:16 PM PDT 24
Peak memory 214284 kb
Host smart-afd310b9-65ce-48f7-bc4e-7535327753ff
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3458395552 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 3.rom_ctrl_stress_all.3458395552
Directory /workspace/3.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/30.rom_ctrl_alert_test.789669397
Short name T342
Test name
Test status
Simulation time 278216178 ps
CPU time 4.06 seconds
Started Apr 21 12:24:53 PM PDT 24
Finished Apr 21 12:24:58 PM PDT 24
Peak memory 211604 kb
Host smart-1198a29c-4490-4e1a-9343-6e00fca11d82
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=789669397 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_alert_test.789669397
Directory /workspace/30.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/30.rom_ctrl_corrupt_sig_fatal_chk.138406340
Short name T183
Test name
Test status
Simulation time 13679610713 ps
CPU time 188.38 seconds
Started Apr 21 12:24:51 PM PDT 24
Finished Apr 21 12:28:00 PM PDT 24
Peak memory 240488 kb
Host smart-440e11f3-e470-49bf-86a6-b208e01d2bef
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=138406340 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_c
orrupt_sig_fatal_chk.138406340
Directory /workspace/30.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/30.rom_ctrl_kmac_err_chk.607267668
Short name T254
Test name
Test status
Simulation time 1550121399 ps
CPU time 18.62 seconds
Started Apr 21 12:24:06 PM PDT 24
Finished Apr 21 12:24:25 PM PDT 24
Peak memory 212416 kb
Host smart-efe8fbca-4405-448b-8961-cc22b175bdb0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=607267668 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_kmac_err_chk.607267668
Directory /workspace/30.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/30.rom_ctrl_max_throughput_chk.4158795589
Short name T204
Test name
Test status
Simulation time 4154142539 ps
CPU time 11.32 seconds
Started Apr 21 12:24:31 PM PDT 24
Finished Apr 21 12:24:42 PM PDT 24
Peak memory 211632 kb
Host smart-872a864a-db95-419c-b66e-73b933864f35
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4158795589 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_max_throughput_chk.4158795589
Directory /workspace/30.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/30.rom_ctrl_smoke.3421253951
Short name T336
Test name
Test status
Simulation time 31584211206 ps
CPU time 37.95 seconds
Started Apr 21 12:24:09 PM PDT 24
Finished Apr 21 12:24:47 PM PDT 24
Peak memory 214200 kb
Host smart-36721889-d2b6-4a4b-bb39-d036d201d0d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3421253951 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_smoke.3421253951
Directory /workspace/30.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/31.rom_ctrl_alert_test.4106697223
Short name T188
Test name
Test status
Simulation time 347587041 ps
CPU time 4.1 seconds
Started Apr 21 12:24:28 PM PDT 24
Finished Apr 21 12:24:33 PM PDT 24
Peak memory 211668 kb
Host smart-1969b315-39d4-4890-b075-7864ddead3b5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4106697223 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_alert_test.4106697223
Directory /workspace/31.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/31.rom_ctrl_corrupt_sig_fatal_chk.842137655
Short name T131
Test name
Test status
Simulation time 19258856429 ps
CPU time 191.34 seconds
Started Apr 21 12:24:16 PM PDT 24
Finished Apr 21 12:27:28 PM PDT 24
Peak memory 237756 kb
Host smart-1fd4793f-d741-4f6e-a2c7-317a15cc60ee
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=842137655 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_c
orrupt_sig_fatal_chk.842137655
Directory /workspace/31.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/31.rom_ctrl_kmac_err_chk.437258566
Short name T293
Test name
Test status
Simulation time 4419621089 ps
CPU time 16.29 seconds
Started Apr 21 12:24:13 PM PDT 24
Finished Apr 21 12:24:29 PM PDT 24
Peak memory 211696 kb
Host smart-b68f553b-5a0a-4227-b4a8-a5341a846762
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=437258566 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_kmac_err_chk.437258566
Directory /workspace/31.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/31.rom_ctrl_max_throughput_chk.1288569267
Short name T180
Test name
Test status
Simulation time 5451889608 ps
CPU time 13.41 seconds
Started Apr 21 12:24:27 PM PDT 24
Finished Apr 21 12:24:40 PM PDT 24
Peak memory 211680 kb
Host smart-5ccd0218-8149-469d-8a8a-511403a88244
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1288569267 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_max_throughput_chk.1288569267
Directory /workspace/31.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/31.rom_ctrl_smoke.1734533527
Short name T11
Test name
Test status
Simulation time 2132727216 ps
CPU time 22.49 seconds
Started Apr 21 12:24:15 PM PDT 24
Finished Apr 21 12:24:38 PM PDT 24
Peak memory 219196 kb
Host smart-40484df3-7213-4e67-ab09-27da0753a025
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1734533527 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_smoke.1734533527
Directory /workspace/31.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/31.rom_ctrl_stress_all.604419466
Short name T157
Test name
Test status
Simulation time 7857415462 ps
CPU time 39.9 seconds
Started Apr 21 12:24:13 PM PDT 24
Finished Apr 21 12:24:53 PM PDT 24
Peak memory 219876 kb
Host smart-8afa64bf-427d-4324-afc4-079c732659a4
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=604419466 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 31.rom_ctrl_stress_all.604419466
Directory /workspace/31.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/31.rom_ctrl_stress_all_with_rand_reset.3280923713
Short name T56
Test name
Test status
Simulation time 53321918982 ps
CPU time 9265.39 seconds
Started Apr 21 12:24:39 PM PDT 24
Finished Apr 21 02:59:06 PM PDT 24
Peak memory 236324 kb
Host smart-26a887b4-77bb-47aa-a1f7-f16f22c05ca5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3280923713 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_stress_all_with_rand_reset.3280923713
Directory /workspace/31.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.rom_ctrl_alert_test.2052811036
Short name T341
Test name
Test status
Simulation time 86261273 ps
CPU time 4.31 seconds
Started Apr 21 12:24:16 PM PDT 24
Finished Apr 21 12:24:21 PM PDT 24
Peak memory 211652 kb
Host smart-5aff58d2-6fc5-48a9-87da-04cc2442b62d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2052811036 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_alert_test.2052811036
Directory /workspace/32.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/32.rom_ctrl_corrupt_sig_fatal_chk.1833032311
Short name T26
Test name
Test status
Simulation time 53841786604 ps
CPU time 148.05 seconds
Started Apr 21 12:24:14 PM PDT 24
Finished Apr 21 12:26:42 PM PDT 24
Peak memory 236876 kb
Host smart-679c733a-980a-4068-b1e1-e9d5d2d9af25
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1833032311 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_
corrupt_sig_fatal_chk.1833032311
Directory /workspace/32.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/32.rom_ctrl_kmac_err_chk.2172291350
Short name T356
Test name
Test status
Simulation time 10197014927 ps
CPU time 24.15 seconds
Started Apr 21 12:24:25 PM PDT 24
Finished Apr 21 12:24:49 PM PDT 24
Peak memory 212892 kb
Host smart-d1e55628-ddbe-4a2d-8760-bb60a25e1466
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2172291350 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_kmac_err_chk.2172291350
Directory /workspace/32.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/32.rom_ctrl_max_throughput_chk.3829188921
Short name T283
Test name
Test status
Simulation time 1992936144 ps
CPU time 8.26 seconds
Started Apr 21 12:24:26 PM PDT 24
Finished Apr 21 12:24:35 PM PDT 24
Peak memory 211512 kb
Host smart-3312a0f2-6ae3-4273-b675-fb7ad68cd657
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3829188921 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_max_throughput_chk.3829188921
Directory /workspace/32.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/32.rom_ctrl_smoke.3243708535
Short name T345
Test name
Test status
Simulation time 4269067217 ps
CPU time 32.9 seconds
Started Apr 21 12:24:56 PM PDT 24
Finished Apr 21 12:25:30 PM PDT 24
Peak memory 213552 kb
Host smart-71db216b-b691-4715-9a88-4c8259f7a7de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3243708535 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_smoke.3243708535
Directory /workspace/32.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/32.rom_ctrl_stress_all.1136221089
Short name T166
Test name
Test status
Simulation time 14392500971 ps
CPU time 80.48 seconds
Started Apr 21 12:24:39 PM PDT 24
Finished Apr 21 12:26:00 PM PDT 24
Peak memory 219832 kb
Host smart-49ee298d-efb0-4a74-a9af-c6c2a39c2987
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1136221089 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 32.rom_ctrl_stress_all.1136221089
Directory /workspace/32.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/33.rom_ctrl_alert_test.1071970053
Short name T34
Test name
Test status
Simulation time 1866302906 ps
CPU time 7.36 seconds
Started Apr 21 12:24:18 PM PDT 24
Finished Apr 21 12:24:26 PM PDT 24
Peak memory 211632 kb
Host smart-dedbf781-74cb-4ea6-a732-c65787061b94
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1071970053 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_alert_test.1071970053
Directory /workspace/33.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/33.rom_ctrl_corrupt_sig_fatal_chk.649701974
Short name T206
Test name
Test status
Simulation time 57799947672 ps
CPU time 309.09 seconds
Started Apr 21 12:24:06 PM PDT 24
Finished Apr 21 12:29:16 PM PDT 24
Peak memory 241636 kb
Host smart-0b9d5b54-9f7e-4754-9fc2-68c079772e84
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=649701974 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_c
orrupt_sig_fatal_chk.649701974
Directory /workspace/33.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/33.rom_ctrl_kmac_err_chk.2179479585
Short name T21
Test name
Test status
Simulation time 9598215470 ps
CPU time 29.51 seconds
Started Apr 21 12:24:34 PM PDT 24
Finished Apr 21 12:25:04 PM PDT 24
Peak memory 212516 kb
Host smart-f580ba6f-fef1-419b-94d6-936ebe7273f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2179479585 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_kmac_err_chk.2179479585
Directory /workspace/33.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/33.rom_ctrl_smoke.160833489
Short name T13
Test name
Test status
Simulation time 178748133 ps
CPU time 9.67 seconds
Started Apr 21 12:24:47 PM PDT 24
Finished Apr 21 12:24:58 PM PDT 24
Peak memory 212176 kb
Host smart-94771558-5151-4263-af82-116f23d7e642
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=160833489 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_smoke.160833489
Directory /workspace/33.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/33.rom_ctrl_stress_all.4244622413
Short name T81
Test name
Test status
Simulation time 320734622 ps
CPU time 16.56 seconds
Started Apr 21 12:24:38 PM PDT 24
Finished Apr 21 12:24:55 PM PDT 24
Peak memory 215244 kb
Host smart-6af63f60-c32d-44e3-a5a1-6713bdaa9f98
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4244622413 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 33.rom_ctrl_stress_all.4244622413
Directory /workspace/33.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/34.rom_ctrl_alert_test.886562556
Short name T333
Test name
Test status
Simulation time 85632022 ps
CPU time 4.31 seconds
Started Apr 21 12:24:24 PM PDT 24
Finished Apr 21 12:24:28 PM PDT 24
Peak memory 211636 kb
Host smart-fcdeb996-6800-4bbb-bc4a-6e5beca6ee99
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=886562556 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_alert_test.886562556
Directory /workspace/34.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/34.rom_ctrl_corrupt_sig_fatal_chk.2100011765
Short name T28
Test name
Test status
Simulation time 2146866394 ps
CPU time 123.55 seconds
Started Apr 21 12:24:46 PM PDT 24
Finished Apr 21 12:26:51 PM PDT 24
Peak memory 219940 kb
Host smart-82dc0731-4d28-48ef-a3e9-3548355e5034
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2100011765 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_
corrupt_sig_fatal_chk.2100011765
Directory /workspace/34.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/34.rom_ctrl_max_throughput_chk.640847379
Short name T346
Test name
Test status
Simulation time 2775498396 ps
CPU time 9.33 seconds
Started Apr 21 12:24:39 PM PDT 24
Finished Apr 21 12:24:49 PM PDT 24
Peak memory 211656 kb
Host smart-273adeec-de53-4e54-b6eb-1839538ff349
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=640847379 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_max_throughput_chk.640847379
Directory /workspace/34.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/34.rom_ctrl_smoke.689584356
Short name T198
Test name
Test status
Simulation time 4030261130 ps
CPU time 22.19 seconds
Started Apr 21 12:24:17 PM PDT 24
Finished Apr 21 12:24:39 PM PDT 24
Peak memory 219928 kb
Host smart-16757d92-b12b-45b9-baab-b6f4e8098b4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=689584356 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_smoke.689584356
Directory /workspace/34.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/34.rom_ctrl_stress_all.2132661453
Short name T136
Test name
Test status
Simulation time 2141686628 ps
CPU time 30.16 seconds
Started Apr 21 12:24:45 PM PDT 24
Finished Apr 21 12:25:16 PM PDT 24
Peak memory 215636 kb
Host smart-f751c940-170b-4aa1-8fb8-1eaa254011e5
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2132661453 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 34.rom_ctrl_stress_all.2132661453
Directory /workspace/34.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/35.rom_ctrl_alert_test.526658314
Short name T3
Test name
Test status
Simulation time 86462737 ps
CPU time 4.18 seconds
Started Apr 21 12:24:21 PM PDT 24
Finished Apr 21 12:24:25 PM PDT 24
Peak memory 211576 kb
Host smart-85402287-64f3-4b4b-9412-ebca12c266a9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=526658314 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_alert_test.526658314
Directory /workspace/35.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/35.rom_ctrl_corrupt_sig_fatal_chk.2034319553
Short name T104
Test name
Test status
Simulation time 15501782853 ps
CPU time 162.75 seconds
Started Apr 21 12:24:22 PM PDT 24
Finished Apr 21 12:27:06 PM PDT 24
Peak memory 238224 kb
Host smart-41753ca4-09aa-481a-94a7-f7312daa74a6
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2034319553 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_
corrupt_sig_fatal_chk.2034319553
Directory /workspace/35.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/35.rom_ctrl_kmac_err_chk.3354868115
Short name T156
Test name
Test status
Simulation time 3112802799 ps
CPU time 27.6 seconds
Started Apr 21 12:24:39 PM PDT 24
Finished Apr 21 12:25:07 PM PDT 24
Peak memory 212180 kb
Host smart-b0d5d3d3-99e8-481a-90e5-e99e45626c0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3354868115 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_kmac_err_chk.3354868115
Directory /workspace/35.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/35.rom_ctrl_max_throughput_chk.470829366
Short name T276
Test name
Test status
Simulation time 1005851776 ps
CPU time 5.27 seconds
Started Apr 21 12:24:27 PM PDT 24
Finished Apr 21 12:24:33 PM PDT 24
Peak memory 211524 kb
Host smart-1d15c46a-f22e-467b-9188-c77653eb6ffb
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=470829366 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_max_throughput_chk.470829366
Directory /workspace/35.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/35.rom_ctrl_smoke.1482963998
Short name T103
Test name
Test status
Simulation time 190594463 ps
CPU time 10.07 seconds
Started Apr 21 12:24:19 PM PDT 24
Finished Apr 21 12:24:30 PM PDT 24
Peak memory 213352 kb
Host smart-9264f121-e237-4e46-9c18-1d41d2898414
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1482963998 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_smoke.1482963998
Directory /workspace/35.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/35.rom_ctrl_stress_all.3517613567
Short name T334
Test name
Test status
Simulation time 59078426818 ps
CPU time 41.59 seconds
Started Apr 21 12:24:29 PM PDT 24
Finished Apr 21 12:25:12 PM PDT 24
Peak memory 219828 kb
Host smart-06de6567-0404-4dcd-9ac0-49905b22edf0
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3517613567 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 35.rom_ctrl_stress_all.3517613567
Directory /workspace/35.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/35.rom_ctrl_stress_all_with_rand_reset.4083848289
Short name T326
Test name
Test status
Simulation time 316888140120 ps
CPU time 2131.28 seconds
Started Apr 21 12:24:37 PM PDT 24
Finished Apr 21 01:00:09 PM PDT 24
Peak memory 238368 kb
Host smart-ddb7f2d7-3ffa-44d7-9f5b-7f8c2aed3e19
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4083848289 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_stress_all_with_rand_reset.4083848289
Directory /workspace/35.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.rom_ctrl_corrupt_sig_fatal_chk.730489127
Short name T355
Test name
Test status
Simulation time 28350769319 ps
CPU time 291.37 seconds
Started Apr 21 12:24:15 PM PDT 24
Finished Apr 21 12:29:07 PM PDT 24
Peak memory 212376 kb
Host smart-7695f5be-b2d4-40af-9174-680cd32291e2
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=730489127 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_c
orrupt_sig_fatal_chk.730489127
Directory /workspace/36.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/36.rom_ctrl_kmac_err_chk.2537180283
Short name T253
Test name
Test status
Simulation time 9186471918 ps
CPU time 27.79 seconds
Started Apr 21 12:24:40 PM PDT 24
Finished Apr 21 12:25:08 PM PDT 24
Peak memory 213016 kb
Host smart-c5f7d7ff-53b3-4cc0-8531-c201e26fb26e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2537180283 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_kmac_err_chk.2537180283
Directory /workspace/36.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/36.rom_ctrl_max_throughput_chk.492264500
Short name T263
Test name
Test status
Simulation time 6868270158 ps
CPU time 14.75 seconds
Started Apr 21 12:24:33 PM PDT 24
Finished Apr 21 12:24:48 PM PDT 24
Peak memory 211768 kb
Host smart-9d52beee-9e4c-4fdc-bb1c-3454dcabfe62
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=492264500 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_max_throughput_chk.492264500
Directory /workspace/36.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/36.rom_ctrl_smoke.3870577072
Short name T301
Test name
Test status
Simulation time 2132173164 ps
CPU time 13.03 seconds
Started Apr 21 12:24:19 PM PDT 24
Finished Apr 21 12:24:33 PM PDT 24
Peak memory 214220 kb
Host smart-380548dd-16e8-41db-84ed-81b02e7f5688
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3870577072 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_smoke.3870577072
Directory /workspace/36.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/36.rom_ctrl_stress_all.2250838027
Short name T271
Test name
Test status
Simulation time 915548692 ps
CPU time 14.69 seconds
Started Apr 21 12:24:26 PM PDT 24
Finished Apr 21 12:24:41 PM PDT 24
Peak memory 219584 kb
Host smart-ee7ace10-ae32-4a7f-a10c-990a8a540a14
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2250838027 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 36.rom_ctrl_stress_all.2250838027
Directory /workspace/36.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/37.rom_ctrl_alert_test.933896429
Short name T190
Test name
Test status
Simulation time 17529984465 ps
CPU time 14.78 seconds
Started Apr 21 12:24:34 PM PDT 24
Finished Apr 21 12:24:49 PM PDT 24
Peak memory 211768 kb
Host smart-ce808f9d-b05d-4abb-9ff2-65e3ee239370
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=933896429 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_alert_test.933896429
Directory /workspace/37.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/37.rom_ctrl_corrupt_sig_fatal_chk.411010948
Short name T179
Test name
Test status
Simulation time 1246301520 ps
CPU time 73.13 seconds
Started Apr 21 12:24:34 PM PDT 24
Finished Apr 21 12:25:53 PM PDT 24
Peak memory 230100 kb
Host smart-c1106150-c840-40a9-a11e-e2590cac966b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=411010948 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_c
orrupt_sig_fatal_chk.411010948
Directory /workspace/37.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/37.rom_ctrl_kmac_err_chk.2830489902
Short name T20
Test name
Test status
Simulation time 6671726040 ps
CPU time 28.12 seconds
Started Apr 21 12:24:27 PM PDT 24
Finished Apr 21 12:24:55 PM PDT 24
Peak memory 212348 kb
Host smart-4901a68f-9efa-42d3-8242-dc0ccbd05924
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2830489902 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_kmac_err_chk.2830489902
Directory /workspace/37.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/37.rom_ctrl_max_throughput_chk.4204336830
Short name T314
Test name
Test status
Simulation time 7763074793 ps
CPU time 15.96 seconds
Started Apr 21 12:24:44 PM PDT 24
Finished Apr 21 12:25:01 PM PDT 24
Peak memory 211640 kb
Host smart-a3f04b88-37cb-4436-9580-626b1a6a2342
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4204336830 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_max_throughput_chk.4204336830
Directory /workspace/37.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/37.rom_ctrl_smoke.390944293
Short name T259
Test name
Test status
Simulation time 6222350807 ps
CPU time 28.05 seconds
Started Apr 21 12:24:43 PM PDT 24
Finished Apr 21 12:25:12 PM PDT 24
Peak memory 214328 kb
Host smart-af83a5c4-e771-4d48-8983-ec6ee65edbaf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=390944293 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_smoke.390944293
Directory /workspace/37.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/37.rom_ctrl_stress_all.2279782829
Short name T200
Test name
Test status
Simulation time 1434157912 ps
CPU time 25.47 seconds
Started Apr 21 12:24:31 PM PDT 24
Finished Apr 21 12:24:57 PM PDT 24
Peak memory 219700 kb
Host smart-4a161560-0aa6-40d0-a7a2-1a0d0cafdac3
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2279782829 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 37.rom_ctrl_stress_all.2279782829
Directory /workspace/37.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/38.rom_ctrl_alert_test.4000659651
Short name T249
Test name
Test status
Simulation time 761452285 ps
CPU time 8.82 seconds
Started Apr 21 12:24:55 PM PDT 24
Finished Apr 21 12:25:05 PM PDT 24
Peak memory 211672 kb
Host smart-e19cd4f7-987e-4c91-a750-854450b52e47
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4000659651 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_alert_test.4000659651
Directory /workspace/38.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/38.rom_ctrl_corrupt_sig_fatal_chk.516876862
Short name T220
Test name
Test status
Simulation time 54449418208 ps
CPU time 195.77 seconds
Started Apr 21 12:24:44 PM PDT 24
Finished Apr 21 12:28:01 PM PDT 24
Peak memory 241316 kb
Host smart-4c3ab159-6607-4c8d-b316-b9a4c7bcd233
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=516876862 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_c
orrupt_sig_fatal_chk.516876862
Directory /workspace/38.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/38.rom_ctrl_kmac_err_chk.2143832875
Short name T39
Test name
Test status
Simulation time 1504558633 ps
CPU time 14.7 seconds
Started Apr 21 12:24:19 PM PDT 24
Finished Apr 21 12:24:34 PM PDT 24
Peak memory 212136 kb
Host smart-52ded166-71ce-4df1-aaa7-6e894e4d99d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2143832875 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_kmac_err_chk.2143832875
Directory /workspace/38.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/38.rom_ctrl_max_throughput_chk.3508360743
Short name T218
Test name
Test status
Simulation time 190829914 ps
CPU time 5.59 seconds
Started Apr 21 12:24:53 PM PDT 24
Finished Apr 21 12:24:59 PM PDT 24
Peak memory 211536 kb
Host smart-3cfb05ea-4067-4e19-be03-86b337a8c008
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3508360743 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_max_throughput_chk.3508360743
Directory /workspace/38.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/38.rom_ctrl_smoke.2533056139
Short name T213
Test name
Test status
Simulation time 674999295 ps
CPU time 15.36 seconds
Started Apr 21 12:24:50 PM PDT 24
Finished Apr 21 12:25:06 PM PDT 24
Peak memory 214300 kb
Host smart-9a35681d-c29c-48c0-8492-e5ac6a94d19c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2533056139 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_smoke.2533056139
Directory /workspace/38.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/38.rom_ctrl_stress_all.1085378550
Short name T14
Test name
Test status
Simulation time 1732783250 ps
CPU time 17.28 seconds
Started Apr 21 12:24:24 PM PDT 24
Finished Apr 21 12:24:41 PM PDT 24
Peak memory 212152 kb
Host smart-898de615-169d-4757-9080-72d7a00097a3
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1085378550 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 38.rom_ctrl_stress_all.1085378550
Directory /workspace/38.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/39.rom_ctrl_alert_test.3126218318
Short name T310
Test name
Test status
Simulation time 22851479398 ps
CPU time 14.1 seconds
Started Apr 21 12:24:38 PM PDT 24
Finished Apr 21 12:24:52 PM PDT 24
Peak memory 211756 kb
Host smart-01ead7c1-dced-4ed7-a056-25d06657d252
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3126218318 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_alert_test.3126218318
Directory /workspace/39.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/39.rom_ctrl_corrupt_sig_fatal_chk.990853565
Short name T266
Test name
Test status
Simulation time 22139975263 ps
CPU time 206.49 seconds
Started Apr 21 12:24:46 PM PDT 24
Finished Apr 21 12:28:13 PM PDT 24
Peak memory 220080 kb
Host smart-d0e68497-9953-46ea-b560-d53e28770344
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=990853565 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_c
orrupt_sig_fatal_chk.990853565
Directory /workspace/39.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/39.rom_ctrl_kmac_err_chk.2635778759
Short name T325
Test name
Test status
Simulation time 7767103429 ps
CPU time 19.28 seconds
Started Apr 21 12:24:19 PM PDT 24
Finished Apr 21 12:24:38 PM PDT 24
Peak memory 212908 kb
Host smart-bee9002f-d6e7-4128-8ec6-03127a6f78ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2635778759 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_kmac_err_chk.2635778759
Directory /workspace/39.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/39.rom_ctrl_max_throughput_chk.2421154720
Short name T303
Test name
Test status
Simulation time 2137635447 ps
CPU time 16.75 seconds
Started Apr 21 12:24:25 PM PDT 24
Finished Apr 21 12:24:42 PM PDT 24
Peak memory 211536 kb
Host smart-106a438f-466e-4eef-b0bb-f4dc7877266f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2421154720 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_max_throughput_chk.2421154720
Directory /workspace/39.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/39.rom_ctrl_smoke.1055678190
Short name T324
Test name
Test status
Simulation time 190305990 ps
CPU time 10 seconds
Started Apr 21 12:24:35 PM PDT 24
Finished Apr 21 12:24:46 PM PDT 24
Peak memory 219696 kb
Host smart-bb7428fe-26a8-4d18-8af3-93ef8773335e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1055678190 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_smoke.1055678190
Directory /workspace/39.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/39.rom_ctrl_stress_all.224459683
Short name T176
Test name
Test status
Simulation time 74683386287 ps
CPU time 68.01 seconds
Started Apr 21 12:24:22 PM PDT 24
Finished Apr 21 12:25:30 PM PDT 24
Peak memory 219756 kb
Host smart-73b3fc72-fab3-4d54-81c0-c5daae0d235b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=224459683 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 39.rom_ctrl_stress_all.224459683
Directory /workspace/39.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/4.rom_ctrl_alert_test.3074412665
Short name T307
Test name
Test status
Simulation time 334318810 ps
CPU time 4.15 seconds
Started Apr 21 12:23:30 PM PDT 24
Finished Apr 21 12:23:34 PM PDT 24
Peak memory 211444 kb
Host smart-08bfabd6-9c96-4ccf-9218-e89207e61373
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3074412665 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_alert_test.3074412665
Directory /workspace/4.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/4.rom_ctrl_corrupt_sig_fatal_chk.2826112717
Short name T30
Test name
Test status
Simulation time 18730959973 ps
CPU time 210.84 seconds
Started Apr 21 12:23:57 PM PDT 24
Finished Apr 21 12:27:29 PM PDT 24
Peak memory 237424 kb
Host smart-c1c0a5c6-aa51-4f30-b40a-c7e782c708ce
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2826112717 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_c
orrupt_sig_fatal_chk.2826112717
Directory /workspace/4.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/4.rom_ctrl_kmac_err_chk.946099920
Short name T357
Test name
Test status
Simulation time 11553273998 ps
CPU time 25.38 seconds
Started Apr 21 12:23:42 PM PDT 24
Finished Apr 21 12:24:08 PM PDT 24
Peak memory 212692 kb
Host smart-091465de-ee5f-4aa2-ab21-c1a77fee7591
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=946099920 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_kmac_err_chk.946099920
Directory /workspace/4.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/4.rom_ctrl_max_throughput_chk.3808894828
Short name T228
Test name
Test status
Simulation time 2112599231 ps
CPU time 17.2 seconds
Started Apr 21 12:23:38 PM PDT 24
Finished Apr 21 12:23:55 PM PDT 24
Peak memory 211452 kb
Host smart-1c5f285c-0c59-4281-94c5-32c7833be327
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3808894828 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_max_throughput_chk.3808894828
Directory /workspace/4.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/4.rom_ctrl_sec_cm.867067825
Short name T37
Test name
Test status
Simulation time 2493974946 ps
CPU time 106.01 seconds
Started Apr 21 12:23:39 PM PDT 24
Finished Apr 21 12:25:25 PM PDT 24
Peak memory 234144 kb
Host smart-3d7dc7aa-049b-46c5-bc24-2077695342ca
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=867067825 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_sec_cm.867067825
Directory /workspace/4.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/4.rom_ctrl_smoke.320405560
Short name T68
Test name
Test status
Simulation time 278070029 ps
CPU time 9.77 seconds
Started Apr 21 12:23:40 PM PDT 24
Finished Apr 21 12:23:50 PM PDT 24
Peak memory 219660 kb
Host smart-91be2976-2ff5-4ac5-af01-c55d43a30e2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=320405560 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_smoke.320405560
Directory /workspace/4.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/4.rom_ctrl_stress_all.327186029
Short name T238
Test name
Test status
Simulation time 5689468745 ps
CPU time 23.75 seconds
Started Apr 21 12:23:34 PM PDT 24
Finished Apr 21 12:23:58 PM PDT 24
Peak memory 219636 kb
Host smart-4cd40737-2eea-4847-94ef-a7a1beb87816
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=327186029 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 4.rom_ctrl_stress_all.327186029
Directory /workspace/4.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/40.rom_ctrl_alert_test.2235502559
Short name T313
Test name
Test status
Simulation time 518520187 ps
CPU time 4.05 seconds
Started Apr 21 12:24:38 PM PDT 24
Finished Apr 21 12:24:42 PM PDT 24
Peak memory 211644 kb
Host smart-6c39505d-a9ea-4817-ad6e-1c866e6758ae
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2235502559 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_alert_test.2235502559
Directory /workspace/40.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/40.rom_ctrl_corrupt_sig_fatal_chk.404340514
Short name T280
Test name
Test status
Simulation time 22591144702 ps
CPU time 264.1 seconds
Started Apr 21 12:24:30 PM PDT 24
Finished Apr 21 12:28:55 PM PDT 24
Peak memory 234164 kb
Host smart-51d4d8e5-93f6-464f-a165-248a841bd32e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=404340514 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_c
orrupt_sig_fatal_chk.404340514
Directory /workspace/40.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/40.rom_ctrl_kmac_err_chk.2500580166
Short name T262
Test name
Test status
Simulation time 4861954701 ps
CPU time 22.11 seconds
Started Apr 21 12:24:22 PM PDT 24
Finished Apr 21 12:24:44 PM PDT 24
Peak memory 212612 kb
Host smart-3f6073fb-be82-462e-aec3-e10c3946be1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2500580166 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_kmac_err_chk.2500580166
Directory /workspace/40.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/40.rom_ctrl_max_throughput_chk.1506009120
Short name T208
Test name
Test status
Simulation time 1851837396 ps
CPU time 14.99 seconds
Started Apr 21 12:24:34 PM PDT 24
Finished Apr 21 12:24:49 PM PDT 24
Peak memory 211536 kb
Host smart-0375b9e3-3098-4ca4-b5b9-756c3d189c2d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1506009120 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_max_throughput_chk.1506009120
Directory /workspace/40.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/40.rom_ctrl_smoke.1594113586
Short name T349
Test name
Test status
Simulation time 4140273529 ps
CPU time 41.87 seconds
Started Apr 21 12:24:35 PM PDT 24
Finished Apr 21 12:25:17 PM PDT 24
Peak memory 213216 kb
Host smart-9de2a759-07b2-4a15-a352-dcef5dc8a527
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1594113586 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_smoke.1594113586
Directory /workspace/40.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/40.rom_ctrl_stress_all.2172405329
Short name T182
Test name
Test status
Simulation time 1338164063 ps
CPU time 11.15 seconds
Started Apr 21 12:24:29 PM PDT 24
Finished Apr 21 12:24:41 PM PDT 24
Peak memory 211472 kb
Host smart-e61b6138-ddd9-47a1-acd9-e78e9f1476b5
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2172405329 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 40.rom_ctrl_stress_all.2172405329
Directory /workspace/40.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/41.rom_ctrl_alert_test.2165859267
Short name T154
Test name
Test status
Simulation time 85805121 ps
CPU time 4.23 seconds
Started Apr 21 12:24:30 PM PDT 24
Finished Apr 21 12:24:35 PM PDT 24
Peak memory 211648 kb
Host smart-f3f909f2-6ac3-4cde-bce8-a50e85c18b27
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2165859267 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_alert_test.2165859267
Directory /workspace/41.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/41.rom_ctrl_corrupt_sig_fatal_chk.3930723809
Short name T264
Test name
Test status
Simulation time 176040203047 ps
CPU time 257.42 seconds
Started Apr 21 12:24:35 PM PDT 24
Finished Apr 21 12:28:53 PM PDT 24
Peak memory 220172 kb
Host smart-7a5505d0-99c8-45be-8f05-0eb89b036812
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3930723809 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_
corrupt_sig_fatal_chk.3930723809
Directory /workspace/41.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/41.rom_ctrl_kmac_err_chk.2051808172
Short name T19
Test name
Test status
Simulation time 1661914958 ps
CPU time 9.45 seconds
Started Apr 21 12:24:40 PM PDT 24
Finished Apr 21 12:24:50 PM PDT 24
Peak memory 213204 kb
Host smart-26d9c04e-77ef-4bad-83a6-c5c3c9b1a837
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2051808172 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_kmac_err_chk.2051808172
Directory /workspace/41.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/41.rom_ctrl_max_throughput_chk.868039697
Short name T288
Test name
Test status
Simulation time 1024919808 ps
CPU time 11.47 seconds
Started Apr 21 12:24:25 PM PDT 24
Finished Apr 21 12:24:37 PM PDT 24
Peak memory 211624 kb
Host smart-546ed1c2-10ab-4402-8ff5-e710e8fb4790
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=868039697 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_max_throughput_chk.868039697
Directory /workspace/41.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/41.rom_ctrl_smoke.562759341
Short name T322
Test name
Test status
Simulation time 29764416357 ps
CPU time 23.05 seconds
Started Apr 21 12:24:51 PM PDT 24
Finished Apr 21 12:25:14 PM PDT 24
Peak memory 219820 kb
Host smart-0af4437f-0d5e-454f-a3ee-dcfb0384b1ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=562759341 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_smoke.562759341
Directory /workspace/41.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/41.rom_ctrl_stress_all.840062612
Short name T245
Test name
Test status
Simulation time 2660374595 ps
CPU time 15.73 seconds
Started Apr 21 12:24:39 PM PDT 24
Finished Apr 21 12:24:55 PM PDT 24
Peak memory 211732 kb
Host smart-39df8287-e5a7-4c33-9520-c2bb39890fa0
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=840062612 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 41.rom_ctrl_stress_all.840062612
Directory /workspace/41.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/41.rom_ctrl_stress_all_with_rand_reset.3398828672
Short name T16
Test name
Test status
Simulation time 230819914833 ps
CPU time 2148.23 seconds
Started Apr 21 12:24:52 PM PDT 24
Finished Apr 21 01:00:41 PM PDT 24
Peak memory 231220 kb
Host smart-e995fbd8-20b5-4543-b410-f469e27602d8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3398828672 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_stress_all_with_rand_reset.3398828672
Directory /workspace/41.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.rom_ctrl_alert_test.2636917410
Short name T306
Test name
Test status
Simulation time 332990954 ps
CPU time 4.09 seconds
Started Apr 21 12:24:53 PM PDT 24
Finished Apr 21 12:24:58 PM PDT 24
Peak memory 211668 kb
Host smart-c3e11383-dbd8-45bc-b6f9-2b3b54e7b27c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2636917410 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_alert_test.2636917410
Directory /workspace/42.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/42.rom_ctrl_corrupt_sig_fatal_chk.2197096887
Short name T294
Test name
Test status
Simulation time 118915145375 ps
CPU time 306.36 seconds
Started Apr 21 12:24:38 PM PDT 24
Finished Apr 21 12:29:45 PM PDT 24
Peak memory 213976 kb
Host smart-7f8f71c4-18b5-4261-9262-2ffdb2a1f2ba
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2197096887 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_
corrupt_sig_fatal_chk.2197096887
Directory /workspace/42.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/42.rom_ctrl_kmac_err_chk.3698921093
Short name T268
Test name
Test status
Simulation time 4570489773 ps
CPU time 22.43 seconds
Started Apr 21 12:24:34 PM PDT 24
Finished Apr 21 12:24:57 PM PDT 24
Peak memory 212580 kb
Host smart-46de5a5d-f79c-47fa-9350-335cffc395ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3698921093 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_kmac_err_chk.3698921093
Directory /workspace/42.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/42.rom_ctrl_max_throughput_chk.1114203369
Short name T331
Test name
Test status
Simulation time 2178680668 ps
CPU time 17.52 seconds
Started Apr 21 12:24:55 PM PDT 24
Finished Apr 21 12:25:14 PM PDT 24
Peak memory 211656 kb
Host smart-b8c1f4e0-6a05-4236-b5c0-271234deddef
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1114203369 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_max_throughput_chk.1114203369
Directory /workspace/42.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/42.rom_ctrl_smoke.2391298108
Short name T135
Test name
Test status
Simulation time 668817271 ps
CPU time 9.27 seconds
Started Apr 21 12:24:42 PM PDT 24
Finished Apr 21 12:24:52 PM PDT 24
Peak memory 213408 kb
Host smart-4b737e37-71dd-449a-a758-b8f414cf1592
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2391298108 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_smoke.2391298108
Directory /workspace/42.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/42.rom_ctrl_stress_all.1110730903
Short name T221
Test name
Test status
Simulation time 396878048 ps
CPU time 13.07 seconds
Started Apr 21 12:24:44 PM PDT 24
Finished Apr 21 12:24:57 PM PDT 24
Peak memory 219688 kb
Host smart-21a239da-e0a6-4d9f-9161-9ed8d6a72ff0
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1110730903 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 42.rom_ctrl_stress_all.1110730903
Directory /workspace/42.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/43.rom_ctrl_alert_test.3173610948
Short name T207
Test name
Test status
Simulation time 7630155160 ps
CPU time 15.15 seconds
Started Apr 21 12:24:31 PM PDT 24
Finished Apr 21 12:24:47 PM PDT 24
Peak memory 211784 kb
Host smart-cedc7a19-20a7-48a9-afe3-542e3c14549b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3173610948 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_alert_test.3173610948
Directory /workspace/43.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/43.rom_ctrl_corrupt_sig_fatal_chk.2542926556
Short name T241
Test name
Test status
Simulation time 8698950020 ps
CPU time 144.26 seconds
Started Apr 21 12:24:30 PM PDT 24
Finished Apr 21 12:26:55 PM PDT 24
Peak memory 238292 kb
Host smart-bc4f6a70-c895-474b-9131-e713bb655714
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2542926556 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_
corrupt_sig_fatal_chk.2542926556
Directory /workspace/43.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/43.rom_ctrl_kmac_err_chk.3107234074
Short name T309
Test name
Test status
Simulation time 15181738227 ps
CPU time 23.89 seconds
Started Apr 21 12:24:34 PM PDT 24
Finished Apr 21 12:24:59 PM PDT 24
Peak memory 212672 kb
Host smart-4890788a-c97f-45b3-b15e-6b7421ebf6cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3107234074 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_kmac_err_chk.3107234074
Directory /workspace/43.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/43.rom_ctrl_max_throughput_chk.1562223552
Short name T227
Test name
Test status
Simulation time 1113665846 ps
CPU time 11.79 seconds
Started Apr 21 12:24:29 PM PDT 24
Finished Apr 21 12:24:46 PM PDT 24
Peak memory 211556 kb
Host smart-29ff4232-1fcd-4bf0-ac59-80b848aaf471
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1562223552 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_max_throughput_chk.1562223552
Directory /workspace/43.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/43.rom_ctrl_smoke.4090508907
Short name T174
Test name
Test status
Simulation time 3649120989 ps
CPU time 27.16 seconds
Started Apr 21 12:24:45 PM PDT 24
Finished Apr 21 12:25:13 PM PDT 24
Peak memory 213640 kb
Host smart-ad7517fc-6590-4a55-8a00-5b179304e0bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4090508907 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_smoke.4090508907
Directory /workspace/43.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/43.rom_ctrl_stress_all.3580999084
Short name T23
Test name
Test status
Simulation time 3273139275 ps
CPU time 24.91 seconds
Started Apr 21 12:24:25 PM PDT 24
Finished Apr 21 12:24:51 PM PDT 24
Peak memory 215592 kb
Host smart-b9acdb5e-a9d2-4c5f-aad3-fef4d5d90f81
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3580999084 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 43.rom_ctrl_stress_all.3580999084
Directory /workspace/43.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/43.rom_ctrl_stress_all_with_rand_reset.4104034035
Short name T57
Test name
Test status
Simulation time 68740668099 ps
CPU time 2536.09 seconds
Started Apr 21 12:24:54 PM PDT 24
Finished Apr 21 01:07:11 PM PDT 24
Peak memory 238180 kb
Host smart-bd53596b-0201-4cb6-8733-eefe394933a5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4104034035 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_stress_all_with_rand_reset.4104034035
Directory /workspace/43.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.rom_ctrl_alert_test.563116387
Short name T35
Test name
Test status
Simulation time 168014744 ps
CPU time 4.31 seconds
Started Apr 21 12:24:28 PM PDT 24
Finished Apr 21 12:24:33 PM PDT 24
Peak memory 211648 kb
Host smart-adb39221-0546-4824-8938-70a27b70977c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=563116387 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_alert_test.563116387
Directory /workspace/44.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/44.rom_ctrl_corrupt_sig_fatal_chk.2870407673
Short name T296
Test name
Test status
Simulation time 2926976801 ps
CPU time 95.13 seconds
Started Apr 21 12:24:51 PM PDT 24
Finished Apr 21 12:26:27 PM PDT 24
Peak memory 225044 kb
Host smart-04c33559-6836-4c83-b9cc-b82dc945ff63
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2870407673 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_
corrupt_sig_fatal_chk.2870407673
Directory /workspace/44.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/44.rom_ctrl_kmac_err_chk.1642730958
Short name T45
Test name
Test status
Simulation time 1594661874 ps
CPU time 19.81 seconds
Started Apr 21 12:24:58 PM PDT 24
Finished Apr 21 12:25:18 PM PDT 24
Peak memory 211688 kb
Host smart-5a7c0493-cb68-4587-9d78-62935241d14f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1642730958 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_kmac_err_chk.1642730958
Directory /workspace/44.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/44.rom_ctrl_max_throughput_chk.3773420139
Short name T312
Test name
Test status
Simulation time 1932822845 ps
CPU time 8.13 seconds
Started Apr 21 12:24:49 PM PDT 24
Finished Apr 21 12:24:58 PM PDT 24
Peak memory 211544 kb
Host smart-5c9704f5-b4c2-45e6-b53f-c0d252609bd0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3773420139 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_max_throughput_chk.3773420139
Directory /workspace/44.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/44.rom_ctrl_smoke.3895399603
Short name T358
Test name
Test status
Simulation time 6138876616 ps
CPU time 20.53 seconds
Started Apr 21 12:24:33 PM PDT 24
Finished Apr 21 12:24:54 PM PDT 24
Peak memory 219832 kb
Host smart-556efa94-3b06-4254-b7c2-ee78ce13884b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3895399603 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_smoke.3895399603
Directory /workspace/44.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/44.rom_ctrl_stress_all.3795214780
Short name T137
Test name
Test status
Simulation time 4378995417 ps
CPU time 34.7 seconds
Started Apr 21 12:24:51 PM PDT 24
Finished Apr 21 12:25:26 PM PDT 24
Peak memory 214376 kb
Host smart-35f840fc-2e86-4719-bba7-ac0873cf6371
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3795214780 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 44.rom_ctrl_stress_all.3795214780
Directory /workspace/44.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/45.rom_ctrl_alert_test.1171957217
Short name T365
Test name
Test status
Simulation time 6843977969 ps
CPU time 8.26 seconds
Started Apr 21 12:24:35 PM PDT 24
Finished Apr 21 12:24:44 PM PDT 24
Peak memory 211812 kb
Host smart-dd57efef-e65c-4f2d-8009-94f5d6cd7877
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1171957217 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_alert_test.1171957217
Directory /workspace/45.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/45.rom_ctrl_corrupt_sig_fatal_chk.2776801344
Short name T234
Test name
Test status
Simulation time 1716065059 ps
CPU time 102.13 seconds
Started Apr 21 12:24:40 PM PDT 24
Finished Apr 21 12:26:23 PM PDT 24
Peak memory 225208 kb
Host smart-24a320c8-1530-4d75-b966-8f722d0eb830
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2776801344 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_
corrupt_sig_fatal_chk.2776801344
Directory /workspace/45.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/45.rom_ctrl_kmac_err_chk.24561473
Short name T261
Test name
Test status
Simulation time 173826058 ps
CPU time 9.53 seconds
Started Apr 21 12:24:46 PM PDT 24
Finished Apr 21 12:24:57 PM PDT 24
Peak memory 212108 kb
Host smart-d66c0ee6-d737-40f6-860e-bd8c45f62f9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=24561473 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_kmac_err_chk.24561473
Directory /workspace/45.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/45.rom_ctrl_max_throughput_chk.1846822774
Short name T233
Test name
Test status
Simulation time 6792004707 ps
CPU time 15.53 seconds
Started Apr 21 12:24:44 PM PDT 24
Finished Apr 21 12:25:00 PM PDT 24
Peak memory 211676 kb
Host smart-26483279-8856-479d-9945-b17e30d80f19
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1846822774 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_max_throughput_chk.1846822774
Directory /workspace/45.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/45.rom_ctrl_smoke.2501544229
Short name T147
Test name
Test status
Simulation time 3475132879 ps
CPU time 26.58 seconds
Started Apr 21 12:25:15 PM PDT 24
Finished Apr 21 12:25:42 PM PDT 24
Peak memory 219852 kb
Host smart-537aa93f-da26-4823-92ff-8134f62bf196
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2501544229 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_smoke.2501544229
Directory /workspace/45.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/45.rom_ctrl_stress_all.3812252569
Short name T329
Test name
Test status
Simulation time 1878544687 ps
CPU time 27.06 seconds
Started Apr 21 12:24:59 PM PDT 24
Finished Apr 21 12:25:27 PM PDT 24
Peak memory 219720 kb
Host smart-206c98f2-0475-4db8-b711-01cb3f2ea737
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3812252569 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 45.rom_ctrl_stress_all.3812252569
Directory /workspace/45.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/45.rom_ctrl_stress_all_with_rand_reset.2484725867
Short name T115
Test name
Test status
Simulation time 89602224085 ps
CPU time 6808.56 seconds
Started Apr 21 12:25:18 PM PDT 24
Finished Apr 21 02:18:48 PM PDT 24
Peak memory 249480 kb
Host smart-509043d8-8553-4adf-ac20-9d1acdbc55af
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2484725867 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_stress_all_with_rand_reset.2484725867
Directory /workspace/45.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.rom_ctrl_alert_test.3720801469
Short name T192
Test name
Test status
Simulation time 1198325788 ps
CPU time 11.61 seconds
Started Apr 21 12:25:24 PM PDT 24
Finished Apr 21 12:25:36 PM PDT 24
Peak memory 211668 kb
Host smart-9d4a53f5-0669-4fb5-911f-e6f638df8730
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3720801469 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_alert_test.3720801469
Directory /workspace/46.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/46.rom_ctrl_corrupt_sig_fatal_chk.996223165
Short name T185
Test name
Test status
Simulation time 41643128954 ps
CPU time 277.31 seconds
Started Apr 21 12:24:25 PM PDT 24
Finished Apr 21 12:29:03 PM PDT 24
Peak memory 231276 kb
Host smart-b8b28463-501e-4302-8652-544d519a74df
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=996223165 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_c
orrupt_sig_fatal_chk.996223165
Directory /workspace/46.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/46.rom_ctrl_kmac_err_chk.4283199947
Short name T165
Test name
Test status
Simulation time 5520069063 ps
CPU time 26.13 seconds
Started Apr 21 12:24:53 PM PDT 24
Finished Apr 21 12:25:20 PM PDT 24
Peak memory 212684 kb
Host smart-e95f61b9-da45-411a-b901-7f33d2c0d55c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4283199947 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_kmac_err_chk.4283199947
Directory /workspace/46.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/46.rom_ctrl_max_throughput_chk.3531761084
Short name T199
Test name
Test status
Simulation time 1355646739 ps
CPU time 7.78 seconds
Started Apr 21 12:25:01 PM PDT 24
Finished Apr 21 12:25:09 PM PDT 24
Peak memory 211568 kb
Host smart-02aa6256-ab3e-4c2d-aa58-167826a416af
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3531761084 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_max_throughput_chk.3531761084
Directory /workspace/46.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/46.rom_ctrl_smoke.338516069
Short name T351
Test name
Test status
Simulation time 6949284241 ps
CPU time 24.27 seconds
Started Apr 21 12:24:40 PM PDT 24
Finished Apr 21 12:25:05 PM PDT 24
Peak memory 214472 kb
Host smart-3fcf6e5d-3aac-455e-b7bc-e7f3712defea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=338516069 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_smoke.338516069
Directory /workspace/46.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/46.rom_ctrl_stress_all.558646738
Short name T5
Test name
Test status
Simulation time 6073556233 ps
CPU time 52.27 seconds
Started Apr 21 12:24:45 PM PDT 24
Finished Apr 21 12:25:39 PM PDT 24
Peak memory 219896 kb
Host smart-65249c9c-c9bd-49ee-a836-aa5ff1b03f59
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=558646738 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 46.rom_ctrl_stress_all.558646738
Directory /workspace/46.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/47.rom_ctrl_alert_test.2839466544
Short name T240
Test name
Test status
Simulation time 190735419 ps
CPU time 4.11 seconds
Started Apr 21 12:24:47 PM PDT 24
Finished Apr 21 12:24:52 PM PDT 24
Peak memory 211672 kb
Host smart-5de23d4a-899d-4b2c-807d-e0bc7f7cd913
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2839466544 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_alert_test.2839466544
Directory /workspace/47.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/47.rom_ctrl_corrupt_sig_fatal_chk.3042410875
Short name T290
Test name
Test status
Simulation time 6261175436 ps
CPU time 95.9 seconds
Started Apr 21 12:24:45 PM PDT 24
Finished Apr 21 12:26:22 PM PDT 24
Peak memory 230340 kb
Host smart-fcbf432f-6317-4c2e-a652-ad2346d8213b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3042410875 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_
corrupt_sig_fatal_chk.3042410875
Directory /workspace/47.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/47.rom_ctrl_kmac_err_chk.1161683109
Short name T282
Test name
Test status
Simulation time 11141627931 ps
CPU time 19.62 seconds
Started Apr 21 12:24:41 PM PDT 24
Finished Apr 21 12:25:01 PM PDT 24
Peak memory 212608 kb
Host smart-e55798d2-dd3f-4251-9f6d-52f9d2d10e96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1161683109 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_kmac_err_chk.1161683109
Directory /workspace/47.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/47.rom_ctrl_max_throughput_chk.3801601875
Short name T152
Test name
Test status
Simulation time 2076894035 ps
CPU time 11.34 seconds
Started Apr 21 12:24:42 PM PDT 24
Finished Apr 21 12:24:54 PM PDT 24
Peak memory 211532 kb
Host smart-8d7fc4c8-89d0-4046-8bcd-3e8546f8632e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3801601875 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_max_throughput_chk.3801601875
Directory /workspace/47.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/47.rom_ctrl_smoke.3032610346
Short name T275
Test name
Test status
Simulation time 9978768529 ps
CPU time 25.3 seconds
Started Apr 21 12:24:54 PM PDT 24
Finished Apr 21 12:25:20 PM PDT 24
Peak memory 219824 kb
Host smart-2cdc2b62-c911-4abb-a263-49b90f87a042
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3032610346 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_smoke.3032610346
Directory /workspace/47.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/47.rom_ctrl_stress_all.365374958
Short name T113
Test name
Test status
Simulation time 2936886485 ps
CPU time 44.83 seconds
Started Apr 21 12:24:34 PM PDT 24
Finished Apr 21 12:25:20 PM PDT 24
Peak memory 215976 kb
Host smart-0ecdaf6a-4ac9-417b-808b-5d8e7ade05ba
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=365374958 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 47.rom_ctrl_stress_all.365374958
Directory /workspace/47.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/48.rom_ctrl_alert_test.822010406
Short name T216
Test name
Test status
Simulation time 1980804137 ps
CPU time 15.65 seconds
Started Apr 21 12:24:50 PM PDT 24
Finished Apr 21 12:25:06 PM PDT 24
Peak memory 211636 kb
Host smart-d97e31cc-8807-4d71-b982-ab39f0dcaf22
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=822010406 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_alert_test.822010406
Directory /workspace/48.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/48.rom_ctrl_corrupt_sig_fatal_chk.3765970390
Short name T287
Test name
Test status
Simulation time 19831243608 ps
CPU time 211.47 seconds
Started Apr 21 12:24:48 PM PDT 24
Finished Apr 21 12:28:20 PM PDT 24
Peak memory 229996 kb
Host smart-dc43c898-3dfa-49f6-b404-e3cf69ee5f8f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3765970390 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_
corrupt_sig_fatal_chk.3765970390
Directory /workspace/48.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/48.rom_ctrl_kmac_err_chk.1357500868
Short name T187
Test name
Test status
Simulation time 14740523327 ps
CPU time 31.26 seconds
Started Apr 21 12:24:47 PM PDT 24
Finished Apr 21 12:25:19 PM PDT 24
Peak memory 212672 kb
Host smart-f3d12881-b863-4b7b-99cd-4ecd34f526e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1357500868 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_kmac_err_chk.1357500868
Directory /workspace/48.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/48.rom_ctrl_max_throughput_chk.1581936501
Short name T251
Test name
Test status
Simulation time 15605430009 ps
CPU time 13.54 seconds
Started Apr 21 12:24:47 PM PDT 24
Finished Apr 21 12:25:02 PM PDT 24
Peak memory 211784 kb
Host smart-156f1a04-7828-4d5e-8de1-7ea3617d488e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1581936501 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_max_throughput_chk.1581936501
Directory /workspace/48.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/48.rom_ctrl_smoke.2168181560
Short name T175
Test name
Test status
Simulation time 2887996349 ps
CPU time 31.91 seconds
Started Apr 21 12:24:23 PM PDT 24
Finished Apr 21 12:24:55 PM PDT 24
Peak memory 213568 kb
Host smart-0d2b9333-2fc7-4db6-adbf-912b6bb12cf7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2168181560 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_smoke.2168181560
Directory /workspace/48.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/48.rom_ctrl_stress_all.1863440771
Short name T366
Test name
Test status
Simulation time 4955221217 ps
CPU time 41.26 seconds
Started Apr 21 12:24:38 PM PDT 24
Finished Apr 21 12:25:20 PM PDT 24
Peak memory 219816 kb
Host smart-4309c891-f671-470a-89e2-a0a538ccacc0
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1863440771 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 48.rom_ctrl_stress_all.1863440771
Directory /workspace/48.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/49.rom_ctrl_alert_test.3074818600
Short name T65
Test name
Test status
Simulation time 8742252492 ps
CPU time 15.11 seconds
Started Apr 21 12:24:45 PM PDT 24
Finished Apr 21 12:25:01 PM PDT 24
Peak memory 211908 kb
Host smart-26830133-61a6-43bc-8b4c-8d5d3238b993
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3074818600 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_alert_test.3074818600
Directory /workspace/49.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/49.rom_ctrl_corrupt_sig_fatal_chk.2533123950
Short name T340
Test name
Test status
Simulation time 26784570854 ps
CPU time 307.87 seconds
Started Apr 21 12:24:55 PM PDT 24
Finished Apr 21 12:30:04 PM PDT 24
Peak memory 213008 kb
Host smart-d8b5d59c-23a5-4cdc-994e-55736090a6cb
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2533123950 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_
corrupt_sig_fatal_chk.2533123950
Directory /workspace/49.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/49.rom_ctrl_kmac_err_chk.1472257708
Short name T177
Test name
Test status
Simulation time 16812724981 ps
CPU time 31.79 seconds
Started Apr 21 12:24:34 PM PDT 24
Finished Apr 21 12:25:06 PM PDT 24
Peak memory 212620 kb
Host smart-c4453bd0-2cc4-442d-ae2b-3267b1a22389
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1472257708 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_kmac_err_chk.1472257708
Directory /workspace/49.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/49.rom_ctrl_max_throughput_chk.2189803154
Short name T272
Test name
Test status
Simulation time 98040829 ps
CPU time 5.33 seconds
Started Apr 21 12:24:39 PM PDT 24
Finished Apr 21 12:24:44 PM PDT 24
Peak memory 211476 kb
Host smart-6512a518-0263-4890-a4e0-f9920e4b5b10
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2189803154 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_max_throughput_chk.2189803154
Directory /workspace/49.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/49.rom_ctrl_smoke.3301039320
Short name T203
Test name
Test status
Simulation time 1128718076 ps
CPU time 17.79 seconds
Started Apr 21 12:24:49 PM PDT 24
Finished Apr 21 12:25:08 PM PDT 24
Peak memory 213768 kb
Host smart-d85047ab-5260-4491-90b8-79ba4253ced7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3301039320 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_smoke.3301039320
Directory /workspace/49.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/49.rom_ctrl_stress_all.1076887662
Short name T159
Test name
Test status
Simulation time 332060218 ps
CPU time 17.76 seconds
Started Apr 21 12:24:36 PM PDT 24
Finished Apr 21 12:24:54 PM PDT 24
Peak memory 219684 kb
Host smart-63cf228f-102e-467a-ba3b-43ad5094438b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1076887662 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 49.rom_ctrl_stress_all.1076887662
Directory /workspace/49.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/5.rom_ctrl_alert_test.1645235351
Short name T214
Test name
Test status
Simulation time 86475422 ps
CPU time 4.07 seconds
Started Apr 21 12:23:36 PM PDT 24
Finished Apr 21 12:23:40 PM PDT 24
Peak memory 211548 kb
Host smart-255e1064-4ad7-4fbe-9193-9ba8150911f9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1645235351 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_alert_test.1645235351
Directory /workspace/5.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/5.rom_ctrl_corrupt_sig_fatal_chk.4057569071
Short name T363
Test name
Test status
Simulation time 3319063854 ps
CPU time 95.64 seconds
Started Apr 21 12:23:38 PM PDT 24
Finished Apr 21 12:25:15 PM PDT 24
Peak memory 212908 kb
Host smart-a9c89110-f179-4907-ad20-dc5e5461e8e3
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4057569071 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_c
orrupt_sig_fatal_chk.4057569071
Directory /workspace/5.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/5.rom_ctrl_kmac_err_chk.442179191
Short name T362
Test name
Test status
Simulation time 327821535 ps
CPU time 9.58 seconds
Started Apr 21 12:23:57 PM PDT 24
Finished Apr 21 12:24:07 PM PDT 24
Peak memory 212124 kb
Host smart-e6048da9-2648-4a89-a57f-464c4131962f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=442179191 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_kmac_err_chk.442179191
Directory /workspace/5.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/5.rom_ctrl_max_throughput_chk.3977799341
Short name T304
Test name
Test status
Simulation time 5467295226 ps
CPU time 13.68 seconds
Started Apr 21 12:23:36 PM PDT 24
Finished Apr 21 12:23:49 PM PDT 24
Peak memory 211596 kb
Host smart-a9cb3d28-6855-4a4d-84ac-9816f7ea9cab
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3977799341 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_max_throughput_chk.3977799341
Directory /workspace/5.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/5.rom_ctrl_smoke.1842537993
Short name T150
Test name
Test status
Simulation time 9287888481 ps
CPU time 22.98 seconds
Started Apr 21 12:23:55 PM PDT 24
Finished Apr 21 12:24:18 PM PDT 24
Peak memory 219832 kb
Host smart-359f3ec9-8a96-451f-8fe0-7da1f1ba17a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1842537993 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_smoke.1842537993
Directory /workspace/5.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/5.rom_ctrl_stress_all.839518188
Short name T82
Test name
Test status
Simulation time 371670885 ps
CPU time 11.43 seconds
Started Apr 21 12:23:50 PM PDT 24
Finished Apr 21 12:24:07 PM PDT 24
Peak memory 211520 kb
Host smart-aa33c6dd-81b1-4499-8b28-6956cb7b1745
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=839518188 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 5.rom_ctrl_stress_all.839518188
Directory /workspace/5.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/6.rom_ctrl_alert_test.3829397702
Short name T274
Test name
Test status
Simulation time 837270837 ps
CPU time 9.43 seconds
Started Apr 21 12:23:38 PM PDT 24
Finished Apr 21 12:23:48 PM PDT 24
Peak memory 211624 kb
Host smart-e9b4fa26-1649-4453-bf61-e660437d02b8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3829397702 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_alert_test.3829397702
Directory /workspace/6.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/6.rom_ctrl_kmac_err_chk.3876295309
Short name T273
Test name
Test status
Simulation time 4598644107 ps
CPU time 17.28 seconds
Started Apr 21 12:23:53 PM PDT 24
Finished Apr 21 12:24:11 PM PDT 24
Peak memory 212552 kb
Host smart-3591665e-c06d-4dc0-8dc9-ac4c22058d0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3876295309 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_kmac_err_chk.3876295309
Directory /workspace/6.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/6.rom_ctrl_max_throughput_chk.1696130443
Short name T15
Test name
Test status
Simulation time 2143445406 ps
CPU time 7.03 seconds
Started Apr 21 12:24:02 PM PDT 24
Finished Apr 21 12:24:09 PM PDT 24
Peak memory 211532 kb
Host smart-18007451-0a4f-4899-a32b-8c3761e20b94
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1696130443 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_max_throughput_chk.1696130443
Directory /workspace/6.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/6.rom_ctrl_smoke.720482208
Short name T205
Test name
Test status
Simulation time 4850733595 ps
CPU time 18.97 seconds
Started Apr 21 12:23:42 PM PDT 24
Finished Apr 21 12:24:02 PM PDT 24
Peak memory 213820 kb
Host smart-a1f66513-d0b5-4009-b7f3-d884bb5685bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=720482208 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_smoke.720482208
Directory /workspace/6.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/6.rom_ctrl_stress_all.1968518730
Short name T197
Test name
Test status
Simulation time 1411582503 ps
CPU time 35.39 seconds
Started Apr 21 12:23:51 PM PDT 24
Finished Apr 21 12:24:27 PM PDT 24
Peak memory 216368 kb
Host smart-1a27c4b2-3477-43d0-8e15-8484d5739825
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1968518730 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 6.rom_ctrl_stress_all.1968518730
Directory /workspace/6.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/7.rom_ctrl_alert_test.3056159280
Short name T323
Test name
Test status
Simulation time 7711410965 ps
CPU time 15.32 seconds
Started Apr 21 12:23:39 PM PDT 24
Finished Apr 21 12:23:55 PM PDT 24
Peak memory 211752 kb
Host smart-6bb37f3f-3745-49ca-8081-2e2c3f56a8d2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3056159280 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_alert_test.3056159280
Directory /workspace/7.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/7.rom_ctrl_corrupt_sig_fatal_chk.1482324260
Short name T153
Test name
Test status
Simulation time 2793032158 ps
CPU time 81.81 seconds
Started Apr 21 12:24:01 PM PDT 24
Finished Apr 21 12:25:23 PM PDT 24
Peak memory 228724 kb
Host smart-efbca224-b34d-4313-81e1-421ee6a3ff55
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1482324260 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_c
orrupt_sig_fatal_chk.1482324260
Directory /workspace/7.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/7.rom_ctrl_kmac_err_chk.2489439702
Short name T284
Test name
Test status
Simulation time 363257802 ps
CPU time 9.35 seconds
Started Apr 21 12:23:40 PM PDT 24
Finished Apr 21 12:23:49 PM PDT 24
Peak memory 212180 kb
Host smart-5b4d198d-e23d-41ac-a209-b13ebf6ee7f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2489439702 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_kmac_err_chk.2489439702
Directory /workspace/7.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/7.rom_ctrl_max_throughput_chk.1279532841
Short name T50
Test name
Test status
Simulation time 390875290 ps
CPU time 5.4 seconds
Started Apr 21 12:23:43 PM PDT 24
Finished Apr 21 12:23:49 PM PDT 24
Peak memory 211512 kb
Host smart-ef955a31-2ffc-4f29-be8b-70e8c4b40918
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1279532841 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_max_throughput_chk.1279532841
Directory /workspace/7.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/7.rom_ctrl_smoke.1005490772
Short name T230
Test name
Test status
Simulation time 7540708653 ps
CPU time 22.51 seconds
Started Apr 21 12:23:56 PM PDT 24
Finished Apr 21 12:24:19 PM PDT 24
Peak memory 214612 kb
Host smart-5c31c889-83d6-4a92-91d7-3ba4770656c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1005490772 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_smoke.1005490772
Directory /workspace/7.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/7.rom_ctrl_stress_all.3742551696
Short name T320
Test name
Test status
Simulation time 199030066 ps
CPU time 9.92 seconds
Started Apr 21 12:23:37 PM PDT 24
Finished Apr 21 12:23:47 PM PDT 24
Peak memory 214856 kb
Host smart-5317fc3f-109a-43ed-8ec9-eb4e720591f0
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3742551696 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 7.rom_ctrl_stress_all.3742551696
Directory /workspace/7.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/8.rom_ctrl_alert_test.220226964
Short name T100
Test name
Test status
Simulation time 1153722599 ps
CPU time 8.14 seconds
Started Apr 21 12:23:53 PM PDT 24
Finished Apr 21 12:24:02 PM PDT 24
Peak memory 211612 kb
Host smart-62f90aaf-463b-459b-a2dc-a33c892ca897
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=220226964 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_alert_test.220226964
Directory /workspace/8.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/8.rom_ctrl_corrupt_sig_fatal_chk.996778196
Short name T361
Test name
Test status
Simulation time 4769788848 ps
CPU time 146.68 seconds
Started Apr 21 12:23:40 PM PDT 24
Finished Apr 21 12:26:07 PM PDT 24
Peak memory 221908 kb
Host smart-a2c483e5-061a-4cb6-8531-8be3f67b1c0f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=996778196 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_co
rrupt_sig_fatal_chk.996778196
Directory /workspace/8.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/8.rom_ctrl_kmac_err_chk.422870083
Short name T149
Test name
Test status
Simulation time 175487462 ps
CPU time 9.33 seconds
Started Apr 21 12:23:54 PM PDT 24
Finished Apr 21 12:24:03 PM PDT 24
Peak memory 212180 kb
Host smart-81f9b8e1-f288-4384-8433-7fcf5dc2624f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=422870083 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_kmac_err_chk.422870083
Directory /workspace/8.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/8.rom_ctrl_max_throughput_chk.3260192698
Short name T297
Test name
Test status
Simulation time 31370910893 ps
CPU time 14.54 seconds
Started Apr 21 12:23:40 PM PDT 24
Finished Apr 21 12:23:54 PM PDT 24
Peak memory 211684 kb
Host smart-5ce0cc2c-c007-49d4-8c14-e55b845372e1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3260192698 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_max_throughput_chk.3260192698
Directory /workspace/8.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/8.rom_ctrl_smoke.3519398579
Short name T344
Test name
Test status
Simulation time 183304286 ps
CPU time 9.6 seconds
Started Apr 21 12:23:34 PM PDT 24
Finished Apr 21 12:23:44 PM PDT 24
Peak memory 213604 kb
Host smart-e7c8f52a-6f9e-46d3-9ff8-31ed7bf68a26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3519398579 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_smoke.3519398579
Directory /workspace/8.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/8.rom_ctrl_stress_all.217660223
Short name T289
Test name
Test status
Simulation time 9111392514 ps
CPU time 62.78 seconds
Started Apr 21 12:23:47 PM PDT 24
Finished Apr 21 12:24:50 PM PDT 24
Peak memory 219808 kb
Host smart-89c1051f-8af2-4c21-9620-ba7389c653a1
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=217660223 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 8.rom_ctrl_stress_all.217660223
Directory /workspace/8.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/9.rom_ctrl_alert_test.3774741699
Short name T98
Test name
Test status
Simulation time 1936110187 ps
CPU time 15.68 seconds
Started Apr 21 12:23:42 PM PDT 24
Finished Apr 21 12:23:58 PM PDT 24
Peak memory 211644 kb
Host smart-07827154-40ef-4258-9c2f-88bc857373c4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3774741699 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_alert_test.3774741699
Directory /workspace/9.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/9.rom_ctrl_corrupt_sig_fatal_chk.2831739536
Short name T359
Test name
Test status
Simulation time 28579588603 ps
CPU time 261.64 seconds
Started Apr 21 12:23:36 PM PDT 24
Finished Apr 21 12:27:58 PM PDT 24
Peak memory 212924 kb
Host smart-99ada8b0-b695-41b8-a67f-8f366316030f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2831739536 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_c
orrupt_sig_fatal_chk.2831739536
Directory /workspace/9.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/9.rom_ctrl_kmac_err_chk.302407221
Short name T46
Test name
Test status
Simulation time 10438262368 ps
CPU time 23.17 seconds
Started Apr 21 12:23:55 PM PDT 24
Finished Apr 21 12:24:19 PM PDT 24
Peak memory 212508 kb
Host smart-e39b6c88-0e2d-483d-b682-9fa62c2e4a62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=302407221 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_kmac_err_chk.302407221
Directory /workspace/9.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/9.rom_ctrl_max_throughput_chk.1373116583
Short name T317
Test name
Test status
Simulation time 3715297301 ps
CPU time 16.13 seconds
Started Apr 21 12:23:57 PM PDT 24
Finished Apr 21 12:24:13 PM PDT 24
Peak memory 211684 kb
Host smart-3a1b2198-b274-41a3-8ed4-4aaf8cf947f1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1373116583 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_max_throughput_chk.1373116583
Directory /workspace/9.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/9.rom_ctrl_smoke.1581426399
Short name T265
Test name
Test status
Simulation time 3935320055 ps
CPU time 35.89 seconds
Started Apr 21 12:23:50 PM PDT 24
Finished Apr 21 12:24:26 PM PDT 24
Peak memory 213536 kb
Host smart-a27b3376-6d19-480c-be45-e2207e744d70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1581426399 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_smoke.1581426399
Directory /workspace/9.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/9.rom_ctrl_stress_all.3134673072
Short name T8
Test name
Test status
Simulation time 2140400566 ps
CPU time 34.21 seconds
Started Apr 21 12:23:41 PM PDT 24
Finished Apr 21 12:24:15 PM PDT 24
Peak memory 219608 kb
Host smart-d51d26ac-6a65-4fe7-8f8b-c5a0252fb005
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3134673072 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 9.rom_ctrl_stress_all.3134673072
Directory /workspace/9.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/9.rom_ctrl_stress_all_with_rand_reset.3025350794
Short name T302
Test name
Test status
Simulation time 49929717743 ps
CPU time 1825.36 seconds
Started Apr 21 12:23:49 PM PDT 24
Finished Apr 21 12:54:15 PM PDT 24
Peak memory 232032 kb
Host smart-f5db2661-decc-4554-a5c5-74e0fabc0689
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3025350794 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_stress_all_with_rand_reset.3025350794
Directory /workspace/9.rom_ctrl_stress_all_with_rand_reset/latest
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