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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
97.61 96.97 93.44 97.88 100.00 98.69 97.88 98.37


Total test records in report: 461
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html
T301 /workspace/coverage/default/23.rom_ctrl_alert_test.1592707967 Apr 25 12:37:19 PM PDT 24 Apr 25 12:37:39 PM PDT 24 7701253128 ps
T302 /workspace/coverage/default/11.rom_ctrl_max_throughput_chk.2446299723 Apr 25 12:37:02 PM PDT 24 Apr 25 12:37:20 PM PDT 24 7627627558 ps
T303 /workspace/coverage/default/12.rom_ctrl_max_throughput_chk.3721788952 Apr 25 12:37:12 PM PDT 24 Apr 25 12:37:23 PM PDT 24 1069197922 ps
T42 /workspace/coverage/default/8.rom_ctrl_stress_all_with_rand_reset.794234392 Apr 25 12:36:45 PM PDT 24 Apr 25 01:06:30 PM PDT 24 576838389953 ps
T304 /workspace/coverage/default/9.rom_ctrl_smoke.1340603107 Apr 25 12:36:58 PM PDT 24 Apr 25 12:37:10 PM PDT 24 747613207 ps
T305 /workspace/coverage/default/24.rom_ctrl_smoke.1471065111 Apr 25 12:37:12 PM PDT 24 Apr 25 12:37:37 PM PDT 24 3798523536 ps
T306 /workspace/coverage/default/21.rom_ctrl_smoke.3312364365 Apr 25 12:37:16 PM PDT 24 Apr 25 12:37:58 PM PDT 24 4021987248 ps
T307 /workspace/coverage/default/31.rom_ctrl_smoke.1523205059 Apr 25 12:37:18 PM PDT 24 Apr 25 12:37:34 PM PDT 24 347986937 ps
T308 /workspace/coverage/default/5.rom_ctrl_smoke.1649835843 Apr 25 12:37:02 PM PDT 24 Apr 25 12:37:27 PM PDT 24 17062477585 ps
T309 /workspace/coverage/default/4.rom_ctrl_max_throughput_chk.3785211958 Apr 25 12:37:03 PM PDT 24 Apr 25 12:37:14 PM PDT 24 640894486 ps
T310 /workspace/coverage/default/39.rom_ctrl_smoke.647894380 Apr 25 12:37:25 PM PDT 24 Apr 25 12:37:58 PM PDT 24 7699894606 ps
T311 /workspace/coverage/default/48.rom_ctrl_corrupt_sig_fatal_chk.1372283308 Apr 25 12:37:17 PM PDT 24 Apr 25 12:38:44 PM PDT 24 7756660922 ps
T312 /workspace/coverage/default/8.rom_ctrl_max_throughput_chk.2448773027 Apr 25 12:36:42 PM PDT 24 Apr 25 12:36:48 PM PDT 24 358257501 ps
T313 /workspace/coverage/default/48.rom_ctrl_stress_all.978625782 Apr 25 12:37:32 PM PDT 24 Apr 25 12:38:06 PM PDT 24 3502106722 ps
T314 /workspace/coverage/default/38.rom_ctrl_stress_all.203609772 Apr 25 12:37:39 PM PDT 24 Apr 25 12:38:47 PM PDT 24 14792119371 ps
T315 /workspace/coverage/default/45.rom_ctrl_smoke.1300287170 Apr 25 12:37:37 PM PDT 24 Apr 25 12:38:02 PM PDT 24 3805514764 ps
T316 /workspace/coverage/default/28.rom_ctrl_max_throughput_chk.2823601977 Apr 25 12:37:27 PM PDT 24 Apr 25 12:37:35 PM PDT 24 372217368 ps
T317 /workspace/coverage/default/15.rom_ctrl_stress_all.3536951640 Apr 25 12:37:08 PM PDT 24 Apr 25 12:37:46 PM PDT 24 9212812165 ps
T318 /workspace/coverage/default/30.rom_ctrl_stress_all.2868117741 Apr 25 12:37:18 PM PDT 24 Apr 25 12:37:36 PM PDT 24 1865956443 ps
T319 /workspace/coverage/default/39.rom_ctrl_max_throughput_chk.2703829348 Apr 25 12:37:21 PM PDT 24 Apr 25 12:37:40 PM PDT 24 1976786802 ps
T320 /workspace/coverage/default/20.rom_ctrl_smoke.1950218320 Apr 25 12:37:07 PM PDT 24 Apr 25 12:37:46 PM PDT 24 23984822410 ps
T321 /workspace/coverage/default/13.rom_ctrl_kmac_err_chk.3534603459 Apr 25 12:37:09 PM PDT 24 Apr 25 12:37:39 PM PDT 24 11385698899 ps
T322 /workspace/coverage/default/34.rom_ctrl_alert_test.3996708792 Apr 25 12:37:18 PM PDT 24 Apr 25 12:37:30 PM PDT 24 1292687134 ps
T323 /workspace/coverage/default/10.rom_ctrl_kmac_err_chk.2765127965 Apr 25 12:37:08 PM PDT 24 Apr 25 12:37:29 PM PDT 24 1369424622 ps
T43 /workspace/coverage/default/19.rom_ctrl_stress_all_with_rand_reset.208693590 Apr 25 12:37:16 PM PDT 24 Apr 25 12:57:16 PM PDT 24 15481846011 ps
T324 /workspace/coverage/default/48.rom_ctrl_smoke.895260909 Apr 25 12:37:19 PM PDT 24 Apr 25 12:37:51 PM PDT 24 8580868349 ps
T325 /workspace/coverage/default/40.rom_ctrl_alert_test.349982464 Apr 25 12:37:18 PM PDT 24 Apr 25 12:37:34 PM PDT 24 1491591385 ps
T326 /workspace/coverage/default/23.rom_ctrl_stress_all.2419727543 Apr 25 12:37:18 PM PDT 24 Apr 25 12:37:32 PM PDT 24 148574275 ps
T327 /workspace/coverage/default/45.rom_ctrl_corrupt_sig_fatal_chk.4176034410 Apr 25 12:37:31 PM PDT 24 Apr 25 12:45:13 PM PDT 24 182371435438 ps
T328 /workspace/coverage/default/12.rom_ctrl_smoke.1058314869 Apr 25 12:36:58 PM PDT 24 Apr 25 12:37:18 PM PDT 24 1331769323 ps
T329 /workspace/coverage/default/37.rom_ctrl_alert_test.695030855 Apr 25 12:37:18 PM PDT 24 Apr 25 12:37:35 PM PDT 24 1714576470 ps
T330 /workspace/coverage/default/34.rom_ctrl_smoke.2411174865 Apr 25 12:37:14 PM PDT 24 Apr 25 12:37:38 PM PDT 24 1726857893 ps
T331 /workspace/coverage/default/2.rom_ctrl_corrupt_sig_fatal_chk.4208991030 Apr 25 12:36:52 PM PDT 24 Apr 25 12:41:01 PM PDT 24 104714760780 ps
T332 /workspace/coverage/default/19.rom_ctrl_corrupt_sig_fatal_chk.1446089352 Apr 25 12:37:25 PM PDT 24 Apr 25 12:46:57 PM PDT 24 238963279633 ps
T333 /workspace/coverage/default/24.rom_ctrl_stress_all.2185336031 Apr 25 12:37:14 PM PDT 24 Apr 25 12:37:24 PM PDT 24 245054501 ps
T334 /workspace/coverage/default/16.rom_ctrl_max_throughput_chk.3141955764 Apr 25 12:37:02 PM PDT 24 Apr 25 12:37:09 PM PDT 24 616698465 ps
T335 /workspace/coverage/default/10.rom_ctrl_max_throughput_chk.3569026661 Apr 25 12:36:59 PM PDT 24 Apr 25 12:37:08 PM PDT 24 1082352011 ps
T336 /workspace/coverage/default/17.rom_ctrl_max_throughput_chk.1672809289 Apr 25 12:37:18 PM PDT 24 Apr 25 12:37:30 PM PDT 24 2627065882 ps
T337 /workspace/coverage/default/26.rom_ctrl_alert_test.2566252943 Apr 25 12:37:06 PM PDT 24 Apr 25 12:37:16 PM PDT 24 940586945 ps
T338 /workspace/coverage/default/14.rom_ctrl_max_throughput_chk.3816716663 Apr 25 12:37:09 PM PDT 24 Apr 25 12:37:22 PM PDT 24 861231543 ps
T339 /workspace/coverage/default/25.rom_ctrl_stress_all.1357196055 Apr 25 12:37:16 PM PDT 24 Apr 25 12:37:33 PM PDT 24 5029241858 ps
T340 /workspace/coverage/default/49.rom_ctrl_corrupt_sig_fatal_chk.3619297746 Apr 25 12:37:24 PM PDT 24 Apr 25 12:42:16 PM PDT 24 28133090772 ps
T341 /workspace/coverage/default/41.rom_ctrl_stress_all.2331787579 Apr 25 12:37:36 PM PDT 24 Apr 25 12:37:58 PM PDT 24 4992728683 ps
T342 /workspace/coverage/default/40.rom_ctrl_smoke.2093628617 Apr 25 12:37:40 PM PDT 24 Apr 25 12:38:06 PM PDT 24 2146593736 ps
T343 /workspace/coverage/default/37.rom_ctrl_smoke.3692797315 Apr 25 12:37:14 PM PDT 24 Apr 25 12:37:37 PM PDT 24 7242473500 ps
T344 /workspace/coverage/default/28.rom_ctrl_smoke.450197062 Apr 25 12:37:07 PM PDT 24 Apr 25 12:37:30 PM PDT 24 3029541853 ps
T345 /workspace/coverage/default/28.rom_ctrl_stress_all.4238431808 Apr 25 12:37:16 PM PDT 24 Apr 25 12:37:37 PM PDT 24 307388743 ps
T346 /workspace/coverage/default/32.rom_ctrl_stress_all_with_rand_reset.2561614436 Apr 25 12:37:28 PM PDT 24 Apr 25 12:58:13 PM PDT 24 70452739338 ps
T347 /workspace/coverage/default/17.rom_ctrl_smoke.2917686841 Apr 25 12:37:12 PM PDT 24 Apr 25 12:37:50 PM PDT 24 4205166568 ps
T348 /workspace/coverage/default/16.rom_ctrl_stress_all.3162032114 Apr 25 12:37:04 PM PDT 24 Apr 25 12:38:06 PM PDT 24 11040996947 ps
T349 /workspace/coverage/default/20.rom_ctrl_corrupt_sig_fatal_chk.2570801034 Apr 25 12:37:10 PM PDT 24 Apr 25 12:43:36 PM PDT 24 144770265222 ps
T350 /workspace/coverage/default/44.rom_ctrl_corrupt_sig_fatal_chk.14669443 Apr 25 12:37:32 PM PDT 24 Apr 25 12:45:19 PM PDT 24 693237363481 ps
T351 /workspace/coverage/default/15.rom_ctrl_alert_test.3075365517 Apr 25 12:37:01 PM PDT 24 Apr 25 12:37:12 PM PDT 24 2418743547 ps
T352 /workspace/coverage/default/26.rom_ctrl_max_throughput_chk.2134428974 Apr 25 12:37:12 PM PDT 24 Apr 25 12:37:23 PM PDT 24 340401665 ps
T353 /workspace/coverage/default/26.rom_ctrl_kmac_err_chk.4026365020 Apr 25 12:37:07 PM PDT 24 Apr 25 12:37:42 PM PDT 24 15619638457 ps
T354 /workspace/coverage/default/48.rom_ctrl_max_throughput_chk.2294173068 Apr 25 12:38:28 PM PDT 24 Apr 25 12:38:47 PM PDT 24 8740396704 ps
T355 /workspace/coverage/default/47.rom_ctrl_smoke.2917634093 Apr 25 12:37:28 PM PDT 24 Apr 25 12:37:45 PM PDT 24 708372610 ps
T356 /workspace/coverage/default/19.rom_ctrl_stress_all.129424195 Apr 25 12:37:07 PM PDT 24 Apr 25 12:38:02 PM PDT 24 9761254576 ps
T357 /workspace/coverage/default/32.rom_ctrl_corrupt_sig_fatal_chk.2457320784 Apr 25 12:37:16 PM PDT 24 Apr 25 12:39:35 PM PDT 24 3695949988 ps
T358 /workspace/coverage/default/47.rom_ctrl_corrupt_sig_fatal_chk.353643684 Apr 25 12:37:25 PM PDT 24 Apr 25 12:40:38 PM PDT 24 77642099067 ps
T359 /workspace/coverage/default/48.rom_ctrl_kmac_err_chk.4167454351 Apr 25 12:37:24 PM PDT 24 Apr 25 12:37:35 PM PDT 24 451286030 ps
T360 /workspace/coverage/default/35.rom_ctrl_alert_test.465075509 Apr 25 12:37:18 PM PDT 24 Apr 25 12:37:27 PM PDT 24 334110583 ps
T361 /workspace/coverage/default/27.rom_ctrl_max_throughput_chk.846443279 Apr 25 12:37:04 PM PDT 24 Apr 25 12:37:23 PM PDT 24 8235039955 ps
T362 /workspace/coverage/default/13.rom_ctrl_alert_test.4128098186 Apr 25 12:36:55 PM PDT 24 Apr 25 12:37:06 PM PDT 24 2550897326 ps
T363 /workspace/coverage/default/29.rom_ctrl_smoke.1753340446 Apr 25 12:37:13 PM PDT 24 Apr 25 12:37:46 PM PDT 24 17084258347 ps
T364 /workspace/coverage/default/16.rom_ctrl_kmac_err_chk.3281420996 Apr 25 12:37:12 PM PDT 24 Apr 25 12:37:40 PM PDT 24 2647041707 ps
T365 /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_walk.775063614 Apr 25 12:33:08 PM PDT 24 Apr 25 12:33:24 PM PDT 24 1792245723 ps
T47 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_aliasing.1713912 Apr 25 12:33:12 PM PDT 24 Apr 25 12:33:18 PM PDT 24 233171678 ps
T44 /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_intg_err.4113027662 Apr 25 12:33:28 PM PDT 24 Apr 25 12:34:47 PM PDT 24 1866734252 ps
T48 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_rw.2762155969 Apr 25 12:33:11 PM PDT 24 Apr 25 12:33:28 PM PDT 24 9497971360 ps
T54 /workspace/coverage/cover_reg_top/13.rom_ctrl_passthru_mem_tl_intg_err.3888538813 Apr 25 12:33:21 PM PDT 24 Apr 25 12:34:01 PM PDT 24 6543499816 ps
T89 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_aliasing.1921554686 Apr 25 12:33:10 PM PDT 24 Apr 25 12:33:27 PM PDT 24 1984768794 ps
T90 /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_rw.4180941854 Apr 25 12:33:27 PM PDT 24 Apr 25 12:33:39 PM PDT 24 1190446650 ps
T55 /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_rw.3043901290 Apr 25 12:33:27 PM PDT 24 Apr 25 12:33:34 PM PDT 24 750606186 ps
T79 /workspace/coverage/cover_reg_top/8.rom_ctrl_same_csr_outstanding.3289452495 Apr 25 12:33:19 PM PDT 24 Apr 25 12:33:36 PM PDT 24 4050758027 ps
T366 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_bit_bash.1106761963 Apr 25 12:33:09 PM PDT 24 Apr 25 12:33:26 PM PDT 24 10425577498 ps
T367 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_mem_rw_with_rand_reset.3204413496 Apr 25 12:33:10 PM PDT 24 Apr 25 12:33:21 PM PDT 24 2955337082 ps
T56 /workspace/coverage/cover_reg_top/2.rom_ctrl_passthru_mem_tl_intg_err.1751390584 Apr 25 12:33:09 PM PDT 24 Apr 25 12:34:21 PM PDT 24 7197779749 ps
T57 /workspace/coverage/cover_reg_top/10.rom_ctrl_passthru_mem_tl_intg_err.1250971221 Apr 25 12:33:21 PM PDT 24 Apr 25 12:34:03 PM PDT 24 19229650460 ps
T45 /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_intg_err.2638921167 Apr 25 12:33:11 PM PDT 24 Apr 25 12:33:59 PM PDT 24 2080817906 ps
T80 /workspace/coverage/cover_reg_top/11.rom_ctrl_same_csr_outstanding.185069492 Apr 25 12:33:23 PM PDT 24 Apr 25 12:33:39 PM PDT 24 3734146314 ps
T368 /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_errors.3778770387 Apr 25 12:33:18 PM PDT 24 Apr 25 12:33:32 PM PDT 24 1145834114 ps
T58 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_aliasing.1577412676 Apr 25 12:33:22 PM PDT 24 Apr 25 12:33:34 PM PDT 24 4617251648 ps
T369 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_mem_rw_with_rand_reset.2037665537 Apr 25 12:33:10 PM PDT 24 Apr 25 12:33:17 PM PDT 24 125822856 ps
T46 /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_intg_err.232310545 Apr 25 12:33:16 PM PDT 24 Apr 25 12:33:55 PM PDT 24 944194794 ps
T93 /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_intg_err.3760722476 Apr 25 12:33:15 PM PDT 24 Apr 25 12:34:27 PM PDT 24 658972976 ps
T370 /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_mem_rw_with_rand_reset.4184074353 Apr 25 12:33:25 PM PDT 24 Apr 25 12:33:39 PM PDT 24 14155093036 ps
T81 /workspace/coverage/cover_reg_top/15.rom_ctrl_same_csr_outstanding.1445715475 Apr 25 12:33:28 PM PDT 24 Apr 25 12:33:35 PM PDT 24 813617567 ps
T59 /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_rw.4215891288 Apr 25 12:33:22 PM PDT 24 Apr 25 12:33:27 PM PDT 24 332729401 ps
T371 /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_mem_rw_with_rand_reset.3541670774 Apr 25 12:33:27 PM PDT 24 Apr 25 12:33:46 PM PDT 24 2194586904 ps
T60 /workspace/coverage/cover_reg_top/1.rom_ctrl_passthru_mem_tl_intg_err.3797843725 Apr 25 12:33:05 PM PDT 24 Apr 25 12:34:36 PM PDT 24 11117835508 ps
T372 /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_errors.3741944160 Apr 25 12:33:26 PM PDT 24 Apr 25 12:33:41 PM PDT 24 3927755637 ps
T373 /workspace/coverage/cover_reg_top/6.rom_ctrl_passthru_mem_tl_intg_err.2447018161 Apr 25 12:33:55 PM PDT 24 Apr 25 12:34:48 PM PDT 24 6198323819 ps
T374 /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_mem_rw_with_rand_reset.1919152543 Apr 25 12:33:21 PM PDT 24 Apr 25 12:33:36 PM PDT 24 1477135562 ps
T94 /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_intg_err.3158814100 Apr 25 12:33:23 PM PDT 24 Apr 25 12:34:38 PM PDT 24 1319758071 ps
T95 /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_intg_err.708516008 Apr 25 12:33:27 PM PDT 24 Apr 25 12:34:06 PM PDT 24 1756686282 ps
T82 /workspace/coverage/cover_reg_top/6.rom_ctrl_same_csr_outstanding.3933728976 Apr 25 12:33:21 PM PDT 24 Apr 25 12:33:27 PM PDT 24 1655535368 ps
T375 /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_rw.2706937549 Apr 25 12:33:25 PM PDT 24 Apr 25 12:33:40 PM PDT 24 6002388258 ps
T61 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_rw.2088296585 Apr 25 12:33:10 PM PDT 24 Apr 25 12:33:17 PM PDT 24 270695944 ps
T376 /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_errors.3271386297 Apr 25 12:33:10 PM PDT 24 Apr 25 12:33:21 PM PDT 24 416492571 ps
T69 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_aliasing.2453100906 Apr 25 12:33:12 PM PDT 24 Apr 25 12:33:22 PM PDT 24 3537577395 ps
T83 /workspace/coverage/cover_reg_top/18.rom_ctrl_same_csr_outstanding.1837290155 Apr 25 12:33:30 PM PDT 24 Apr 25 12:33:47 PM PDT 24 3600898726 ps
T377 /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_mem_rw_with_rand_reset.758404501 Apr 25 12:33:21 PM PDT 24 Apr 25 12:33:37 PM PDT 24 3303782214 ps
T378 /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_mem_rw_with_rand_reset.1864342057 Apr 25 12:33:26 PM PDT 24 Apr 25 12:33:41 PM PDT 24 2596565746 ps
T379 /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_errors.4105802339 Apr 25 12:33:09 PM PDT 24 Apr 25 12:33:28 PM PDT 24 7340188281 ps
T84 /workspace/coverage/cover_reg_top/19.rom_ctrl_same_csr_outstanding.2900852501 Apr 25 12:33:32 PM PDT 24 Apr 25 12:33:51 PM PDT 24 6430156248 ps
T70 /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_rw.2575510232 Apr 25 12:33:31 PM PDT 24 Apr 25 12:33:46 PM PDT 24 5261067776 ps
T380 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_mem_rw_with_rand_reset.4239669984 Apr 25 12:33:11 PM PDT 24 Apr 25 12:33:19 PM PDT 24 522375649 ps
T381 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_bit_bash.3582066964 Apr 25 12:33:10 PM PDT 24 Apr 25 12:33:17 PM PDT 24 825741096 ps
T382 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_hw_reset.3777938433 Apr 25 12:33:11 PM PDT 24 Apr 25 12:33:20 PM PDT 24 404381300 ps
T71 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_hw_reset.925000910 Apr 25 12:33:10 PM PDT 24 Apr 25 12:33:22 PM PDT 24 525748646 ps
T383 /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_partial_access.2171339437 Apr 25 12:33:17 PM PDT 24 Apr 25 12:33:27 PM PDT 24 894417438 ps
T85 /workspace/coverage/cover_reg_top/5.rom_ctrl_same_csr_outstanding.4046545426 Apr 25 12:33:19 PM PDT 24 Apr 25 12:33:31 PM PDT 24 16558739860 ps
T384 /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_errors.2075236433 Apr 25 12:33:23 PM PDT 24 Apr 25 12:33:41 PM PDT 24 2349410363 ps
T385 /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_mem_rw_with_rand_reset.2669952831 Apr 25 12:33:18 PM PDT 24 Apr 25 12:33:29 PM PDT 24 2837572882 ps
T386 /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_errors.1477755344 Apr 25 12:33:23 PM PDT 24 Apr 25 12:33:44 PM PDT 24 2089629201 ps
T86 /workspace/coverage/cover_reg_top/1.rom_ctrl_same_csr_outstanding.649821714 Apr 25 12:33:09 PM PDT 24 Apr 25 12:33:24 PM PDT 24 7782511560 ps
T96 /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_intg_err.4203190735 Apr 25 12:33:32 PM PDT 24 Apr 25 12:34:50 PM PDT 24 3500432193 ps
T387 /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_mem_rw_with_rand_reset.1828423923 Apr 25 12:33:21 PM PDT 24 Apr 25 12:33:37 PM PDT 24 3620626293 ps
T87 /workspace/coverage/cover_reg_top/4.rom_ctrl_same_csr_outstanding.942252291 Apr 25 12:33:16 PM PDT 24 Apr 25 12:33:28 PM PDT 24 1857010097 ps
T92 /workspace/coverage/cover_reg_top/3.rom_ctrl_passthru_mem_tl_intg_err.3997488550 Apr 25 12:33:11 PM PDT 24 Apr 25 12:33:42 PM PDT 24 1591744905 ps
T72 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_hw_reset.4066974707 Apr 25 12:33:21 PM PDT 24 Apr 25 12:33:37 PM PDT 24 2865522356 ps
T388 /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_errors.3890222547 Apr 25 12:33:44 PM PDT 24 Apr 25 12:34:04 PM PDT 24 1948467568 ps
T77 /workspace/coverage/cover_reg_top/7.rom_ctrl_passthru_mem_tl_intg_err.547141892 Apr 25 12:33:17 PM PDT 24 Apr 25 12:33:46 PM PDT 24 8934490804 ps
T389 /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_intg_err.1238611135 Apr 25 12:33:02 PM PDT 24 Apr 25 12:33:43 PM PDT 24 5765914976 ps
T88 /workspace/coverage/cover_reg_top/0.rom_ctrl_passthru_mem_tl_intg_err.1922772456 Apr 25 12:33:05 PM PDT 24 Apr 25 12:34:34 PM PDT 24 43207361473 ps
T390 /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_errors.2004125589 Apr 25 12:33:26 PM PDT 24 Apr 25 12:33:42 PM PDT 24 1451889553 ps
T391 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_hw_reset.1558170698 Apr 25 12:33:13 PM PDT 24 Apr 25 12:33:31 PM PDT 24 10034301039 ps
T392 /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_mem_rw_with_rand_reset.2618153591 Apr 25 12:33:36 PM PDT 24 Apr 25 12:33:48 PM PDT 24 264367050 ps
T393 /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_mem_rw_with_rand_reset.1544206953 Apr 25 12:33:21 PM PDT 24 Apr 25 12:33:30 PM PDT 24 934702761 ps
T394 /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_rw.662308535 Apr 25 12:33:23 PM PDT 24 Apr 25 12:33:29 PM PDT 24 346808572 ps
T395 /workspace/coverage/cover_reg_top/18.rom_ctrl_passthru_mem_tl_intg_err.2492864201 Apr 25 12:33:23 PM PDT 24 Apr 25 12:33:52 PM PDT 24 1342978594 ps
T73 /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_rw.2135872016 Apr 25 12:33:19 PM PDT 24 Apr 25 12:33:35 PM PDT 24 9783785403 ps
T97 /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_intg_err.2530182352 Apr 25 12:33:23 PM PDT 24 Apr 25 12:34:12 PM PDT 24 15701219919 ps
T396 /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_intg_err.2383450554 Apr 25 12:33:19 PM PDT 24 Apr 25 12:34:00 PM PDT 24 2664120233 ps
T397 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_hw_reset.1020378352 Apr 25 12:33:12 PM PDT 24 Apr 25 12:33:24 PM PDT 24 3094632544 ps
T398 /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_partial_access.314221623 Apr 25 12:33:10 PM PDT 24 Apr 25 12:33:27 PM PDT 24 13496714873 ps
T98 /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_intg_err.666450850 Apr 25 12:33:11 PM PDT 24 Apr 25 12:34:25 PM PDT 24 1204409980 ps
T399 /workspace/coverage/cover_reg_top/16.rom_ctrl_same_csr_outstanding.1701414549 Apr 25 12:33:28 PM PDT 24 Apr 25 12:33:34 PM PDT 24 86334183 ps
T400 /workspace/coverage/cover_reg_top/2.rom_ctrl_same_csr_outstanding.2609208243 Apr 25 12:33:12 PM PDT 24 Apr 25 12:33:25 PM PDT 24 1184002581 ps
T401 /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_walk.1808683904 Apr 25 12:33:05 PM PDT 24 Apr 25 12:33:12 PM PDT 24 333349779 ps
T402 /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_mem_rw_with_rand_reset.1861195814 Apr 25 12:33:34 PM PDT 24 Apr 25 12:33:42 PM PDT 24 459024736 ps
T104 /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_intg_err.181569769 Apr 25 12:33:24 PM PDT 24 Apr 25 12:34:01 PM PDT 24 2291979581 ps
T403 /workspace/coverage/cover_reg_top/3.rom_ctrl_same_csr_outstanding.1656751323 Apr 25 12:33:11 PM PDT 24 Apr 25 12:33:18 PM PDT 24 174616122 ps
T404 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_rw.3428354880 Apr 25 12:33:21 PM PDT 24 Apr 25 12:33:34 PM PDT 24 2538363245 ps
T100 /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_intg_err.3477959113 Apr 25 12:33:15 PM PDT 24 Apr 25 12:34:04 PM PDT 24 31787383223 ps
T405 /workspace/coverage/cover_reg_top/17.rom_ctrl_same_csr_outstanding.1376733307 Apr 25 12:33:25 PM PDT 24 Apr 25 12:33:34 PM PDT 24 2892862377 ps
T406 /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_errors.2072152592 Apr 25 12:33:22 PM PDT 24 Apr 25 12:33:41 PM PDT 24 1864045390 ps
T407 /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_walk.1157433167 Apr 25 12:33:10 PM PDT 24 Apr 25 12:33:19 PM PDT 24 832796725 ps
T408 /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_rw.2401012160 Apr 25 12:33:26 PM PDT 24 Apr 25 12:33:32 PM PDT 24 86248889 ps
T78 /workspace/coverage/cover_reg_top/15.rom_ctrl_passthru_mem_tl_intg_err.3188805254 Apr 25 12:33:28 PM PDT 24 Apr 25 12:33:49 PM PDT 24 382394809 ps
T409 /workspace/coverage/cover_reg_top/9.rom_ctrl_same_csr_outstanding.2697223324 Apr 25 12:33:21 PM PDT 24 Apr 25 12:33:32 PM PDT 24 2335972173 ps
T410 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_mem_rw_with_rand_reset.1007658404 Apr 25 12:33:18 PM PDT 24 Apr 25 12:33:27 PM PDT 24 1354666771 ps
T411 /workspace/coverage/cover_reg_top/14.rom_ctrl_same_csr_outstanding.2057060397 Apr 25 12:33:23 PM PDT 24 Apr 25 12:33:29 PM PDT 24 347171137 ps
T412 /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_partial_access.2622845962 Apr 25 12:33:11 PM PDT 24 Apr 25 12:33:26 PM PDT 24 3797383063 ps
T413 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_bit_bash.2487317626 Apr 25 12:33:20 PM PDT 24 Apr 25 12:33:26 PM PDT 24 923840477 ps
T74 /workspace/coverage/cover_reg_top/11.rom_ctrl_passthru_mem_tl_intg_err.1499696344 Apr 25 12:33:20 PM PDT 24 Apr 25 12:34:36 PM PDT 24 7789439575 ps
T414 /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_rw.3334339723 Apr 25 12:33:19 PM PDT 24 Apr 25 12:33:35 PM PDT 24 8003104241 ps
T415 /workspace/coverage/cover_reg_top/8.rom_ctrl_passthru_mem_tl_intg_err.1163994556 Apr 25 12:33:18 PM PDT 24 Apr 25 12:33:56 PM PDT 24 2771185556 ps
T416 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_bit_bash.2320096832 Apr 25 12:33:09 PM PDT 24 Apr 25 12:33:28 PM PDT 24 10190024398 ps
T417 /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_mem_rw_with_rand_reset.825791688 Apr 25 12:33:19 PM PDT 24 Apr 25 12:33:34 PM PDT 24 1690238899 ps
T418 /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_rw.1855454085 Apr 25 12:33:14 PM PDT 24 Apr 25 12:33:19 PM PDT 24 85401296 ps
T102 /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_intg_err.4287068966 Apr 25 12:33:35 PM PDT 24 Apr 25 12:34:59 PM PDT 24 8768309878 ps
T419 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_bit_bash.1620558662 Apr 25 12:33:10 PM PDT 24 Apr 25 12:33:18 PM PDT 24 4103111899 ps
T420 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_rw.2690314342 Apr 25 12:33:20 PM PDT 24 Apr 25 12:33:25 PM PDT 24 174962602 ps
T421 /workspace/coverage/cover_reg_top/7.rom_ctrl_same_csr_outstanding.862090443 Apr 25 12:33:18 PM PDT 24 Apr 25 12:33:35 PM PDT 24 7464020847 ps
T422 /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_walk.1659452125 Apr 25 12:33:16 PM PDT 24 Apr 25 12:33:31 PM PDT 24 1732689235 ps
T75 /workspace/coverage/cover_reg_top/14.rom_ctrl_passthru_mem_tl_intg_err.2397979420 Apr 25 12:33:22 PM PDT 24 Apr 25 12:34:07 PM PDT 24 92526709751 ps
T423 /workspace/coverage/cover_reg_top/9.rom_ctrl_passthru_mem_tl_intg_err.1645067943 Apr 25 12:33:54 PM PDT 24 Apr 25 12:35:03 PM PDT 24 7174358476 ps
T424 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_aliasing.2703927747 Apr 25 12:33:20 PM PDT 24 Apr 25 12:33:34 PM PDT 24 3002914193 ps
T99 /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_intg_err.3367736290 Apr 25 12:33:16 PM PDT 24 Apr 25 12:33:58 PM PDT 24 5074411662 ps
T425 /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_errors.694397357 Apr 25 12:33:29 PM PDT 24 Apr 25 12:33:52 PM PDT 24 29180783956 ps
T101 /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_intg_err.1797853535 Apr 25 12:33:27 PM PDT 24 Apr 25 12:34:05 PM PDT 24 543975322 ps
T426 /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_mem_rw_with_rand_reset.2848195981 Apr 25 12:33:24 PM PDT 24 Apr 25 12:33:31 PM PDT 24 302819864 ps
T427 /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_intg_err.4038094455 Apr 25 12:33:34 PM PDT 24 Apr 25 12:34:25 PM PDT 24 8456062708 ps
T428 /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_mem_rw_with_rand_reset.2854530972 Apr 25 12:33:19 PM PDT 24 Apr 25 12:33:36 PM PDT 24 1903225568 ps
T429 /workspace/coverage/cover_reg_top/0.rom_ctrl_same_csr_outstanding.1394866612 Apr 25 12:33:01 PM PDT 24 Apr 25 12:33:11 PM PDT 24 347707445 ps
T430 /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_errors.1481562793 Apr 25 12:33:10 PM PDT 24 Apr 25 12:33:29 PM PDT 24 1879228242 ps
T76 /workspace/coverage/cover_reg_top/5.rom_ctrl_passthru_mem_tl_intg_err.3790392877 Apr 25 12:33:20 PM PDT 24 Apr 25 12:34:15 PM PDT 24 23962205236 ps
T431 /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_intg_err.1614510724 Apr 25 12:33:05 PM PDT 24 Apr 25 12:34:22 PM PDT 24 1147773418 ps
T432 /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_errors.3662860062 Apr 25 12:33:16 PM PDT 24 Apr 25 12:33:26 PM PDT 24 2100798788 ps
T433 /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_rw.1070240757 Apr 25 12:33:31 PM PDT 24 Apr 25 12:33:46 PM PDT 24 1575346325 ps
T434 /workspace/coverage/cover_reg_top/12.rom_ctrl_same_csr_outstanding.153078338 Apr 25 12:33:23 PM PDT 24 Apr 25 12:33:40 PM PDT 24 1959971902 ps
T435 /workspace/coverage/cover_reg_top/12.rom_ctrl_passthru_mem_tl_intg_err.2146656414 Apr 25 12:33:23 PM PDT 24 Apr 25 12:34:25 PM PDT 24 55537410332 ps
T436 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_rw.3652178340 Apr 25 12:33:11 PM PDT 24 Apr 25 12:33:22 PM PDT 24 749165882 ps
T437 /workspace/coverage/cover_reg_top/16.rom_ctrl_passthru_mem_tl_intg_err.3223210370 Apr 25 12:33:24 PM PDT 24 Apr 25 12:34:21 PM PDT 24 6835261719 ps
T438 /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_errors.3533739141 Apr 25 12:33:15 PM PDT 24 Apr 25 12:33:27 PM PDT 24 1544744276 ps
T439 /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_rw.1229173653 Apr 25 12:33:22 PM PDT 24 Apr 25 12:33:39 PM PDT 24 1881648172 ps
T440 /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_mem_rw_with_rand_reset.1323319388 Apr 25 12:33:28 PM PDT 24 Apr 25 12:33:35 PM PDT 24 228594780 ps
T441 /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_errors.2734059386 Apr 25 12:33:32 PM PDT 24 Apr 25 12:33:51 PM PDT 24 3599864993 ps
T442 /workspace/coverage/cover_reg_top/10.rom_ctrl_same_csr_outstanding.1880642188 Apr 25 12:33:18 PM PDT 24 Apr 25 12:33:38 PM PDT 24 15900852879 ps
T443 /workspace/coverage/cover_reg_top/4.rom_ctrl_passthru_mem_tl_intg_err.1331056472 Apr 25 12:33:11 PM PDT 24 Apr 25 12:34:50 PM PDT 24 50375212538 ps
T444 /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_errors.1970810613 Apr 25 12:33:18 PM PDT 24 Apr 25 12:33:34 PM PDT 24 1513509948 ps
T445 /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_partial_access.1430487152 Apr 25 12:33:08 PM PDT 24 Apr 25 12:33:16 PM PDT 24 389356429 ps
T446 /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_errors.4144870001 Apr 25 12:33:07 PM PDT 24 Apr 25 12:33:18 PM PDT 24 331531689 ps
T447 /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_rw.336985039 Apr 25 12:33:14 PM PDT 24 Apr 25 12:33:31 PM PDT 24 2011665163 ps
T448 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_mem_rw_with_rand_reset.573337861 Apr 25 12:33:11 PM PDT 24 Apr 25 12:33:21 PM PDT 24 3124030515 ps
T449 /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_errors.220808399 Apr 25 12:33:23 PM PDT 24 Apr 25 12:33:38 PM PDT 24 1153817188 ps
T450 /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_rw.1763034256 Apr 25 12:33:34 PM PDT 24 Apr 25 12:33:42 PM PDT 24 194768487 ps
T451 /workspace/coverage/cover_reg_top/19.rom_ctrl_passthru_mem_tl_intg_err.412575164 Apr 25 12:33:33 PM PDT 24 Apr 25 12:33:55 PM PDT 24 1730052830 ps
T452 /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_mem_rw_with_rand_reset.3774080427 Apr 25 12:33:23 PM PDT 24 Apr 25 12:33:30 PM PDT 24 531510944 ps
T453 /workspace/coverage/cover_reg_top/17.rom_ctrl_passthru_mem_tl_intg_err.3900103510 Apr 25 12:33:23 PM PDT 24 Apr 25 12:33:51 PM PDT 24 4415454703 ps
T454 /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_errors.1505105783 Apr 25 12:33:09 PM PDT 24 Apr 25 12:33:28 PM PDT 24 6501814455 ps
T455 /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_intg_err.1975362267 Apr 25 12:33:11 PM PDT 24 Apr 25 12:34:27 PM PDT 24 4200220220 ps
T456 /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_errors.720152768 Apr 25 12:33:19 PM PDT 24 Apr 25 12:33:28 PM PDT 24 171956118 ps
T457 /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_partial_access.3222611648 Apr 25 12:33:05 PM PDT 24 Apr 25 12:33:12 PM PDT 24 347146587 ps
T103 /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_intg_err.3255161020 Apr 25 12:33:19 PM PDT 24 Apr 25 12:34:08 PM PDT 24 10119000809 ps
T458 /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_rw.1950742682 Apr 25 12:33:14 PM PDT 24 Apr 25 12:33:19 PM PDT 24 178786318 ps
T459 /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_errors.2302188745 Apr 25 12:33:17 PM PDT 24 Apr 25 12:33:38 PM PDT 24 9654235126 ps
T460 /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_walk.507832791 Apr 25 12:33:12 PM PDT 24 Apr 25 12:33:22 PM PDT 24 654981839 ps
T461 /workspace/coverage/cover_reg_top/13.rom_ctrl_same_csr_outstanding.2126356320 Apr 25 12:33:24 PM PDT 24 Apr 25 12:33:29 PM PDT 24 1379217813 ps

Test location /workspace/coverage/default/48.rom_ctrl_stress_all_with_rand_reset.2250228734
Short name T6
Test name
Test status
Simulation time 272619935468 ps
CPU time 2465.46 seconds
Started Apr 25 12:37:31 PM PDT 24
Finished Apr 25 01:18:37 PM PDT 24
Peak memory 244356 kb
Host smart-4966aeae-6f62-4132-ad1d-a61698447667
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2250228734 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_stress_all_with_rand_reset.2250228734
Directory /workspace/48.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.rom_ctrl_corrupt_sig_fatal_chk.1163944097
Short name T8
Test name
Test status
Simulation time 12164681704 ps
CPU time 86.18 seconds
Started Apr 25 12:37:19 PM PDT 24
Finished Apr 25 12:38:48 PM PDT 24
Peak memory 219508 kb
Host smart-098eceab-a68e-4534-9203-49f6756eb470
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1163944097 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_
corrupt_sig_fatal_chk.1163944097
Directory /workspace/35.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/18.rom_ctrl_stress_all.154619864
Short name T19
Test name
Test status
Simulation time 1031027572 ps
CPU time 12.84 seconds
Started Apr 25 12:37:16 PM PDT 24
Finished Apr 25 12:37:32 PM PDT 24
Peak memory 211984 kb
Host smart-3fdd89ae-1bf6-4446-92d7-0ddf20accbf7
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=154619864 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 18.rom_ctrl_stress_all.154619864
Directory /workspace/18.rom_ctrl_stress_all/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_intg_err.3760722476
Short name T93
Test name
Test status
Simulation time 658972976 ps
CPU time 70.75 seconds
Started Apr 25 12:33:15 PM PDT 24
Finished Apr 25 12:34:27 PM PDT 24
Peak memory 212564 kb
Host smart-ca1f47e3-2f9b-48c1-8960-8c872998960d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3760722476 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_tl_in
tg_err.3760722476
Directory /workspace/6.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/40.rom_ctrl_corrupt_sig_fatal_chk.1876890800
Short name T27
Test name
Test status
Simulation time 47472773067 ps
CPU time 192.68 seconds
Started Apr 25 12:37:24 PM PDT 24
Finished Apr 25 12:40:39 PM PDT 24
Peak memory 236952 kb
Host smart-7868583a-e246-4530-af7a-a639f4c8bfe5
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1876890800 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_
corrupt_sig_fatal_chk.1876890800
Directory /workspace/40.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/2.rom_ctrl_sec_cm.2175385704
Short name T4
Test name
Test status
Simulation time 1533213389 ps
CPU time 106.79 seconds
Started Apr 25 12:36:59 PM PDT 24
Finished Apr 25 12:38:47 PM PDT 24
Peak memory 236960 kb
Host smart-a204254e-2863-41b7-ac77-87aef1b5f0e7
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2175385704 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_sec_cm.2175385704
Directory /workspace/2.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_passthru_mem_tl_intg_err.3888538813
Short name T54
Test name
Test status
Simulation time 6543499816 ps
CPU time 38.22 seconds
Started Apr 25 12:33:21 PM PDT 24
Finished Apr 25 12:34:01 PM PDT 24
Peak memory 210536 kb
Host smart-470edb86-3df3-489e-81a0-d9870642f739
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3888538813 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_p
assthru_mem_tl_intg_err.3888538813
Directory /workspace/13.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_intg_err.666450850
Short name T98
Test name
Test status
Simulation time 1204409980 ps
CPU time 72.33 seconds
Started Apr 25 12:33:11 PM PDT 24
Finished Apr 25 12:34:25 PM PDT 24
Peak memory 210376 kb
Host smart-6bbb7297-f6f4-4b5e-9844-b8c86991e99b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=666450850 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_tl_int
g_err.666450850
Directory /workspace/3.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/42.rom_ctrl_stress_all_with_rand_reset.1852274183
Short name T31
Test name
Test status
Simulation time 36396951762 ps
CPU time 1336.74 seconds
Started Apr 25 12:37:22 PM PDT 24
Finished Apr 25 12:59:41 PM PDT 24
Peak memory 232256 kb
Host smart-08b1d3e3-aa6d-4e18-ab97-f2646c70aac9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1852274183 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_stress_all_with_rand_reset.1852274183
Directory /workspace/42.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/19.rom_ctrl_alert_test.171011062
Short name T150
Test name
Test status
Simulation time 2903865912 ps
CPU time 12.47 seconds
Started Apr 25 12:37:05 PM PDT 24
Finished Apr 25 12:37:19 PM PDT 24
Peak memory 211424 kb
Host smart-2d731c82-a7cd-45d5-b222-6d4958025030
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=171011062 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_alert_test.171011062
Directory /workspace/19.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/19.rom_ctrl_kmac_err_chk.1735297090
Short name T22
Test name
Test status
Simulation time 30152784909 ps
CPU time 28.26 seconds
Started Apr 25 12:37:06 PM PDT 24
Finished Apr 25 12:37:37 PM PDT 24
Peak memory 212308 kb
Host smart-09e5d152-049e-48de-bc5e-5e932f35424a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1735297090 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_kmac_err_chk.1735297090
Directory /workspace/19.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/11.rom_ctrl_kmac_err_chk.1368675393
Short name T206
Test name
Test status
Simulation time 792271852 ps
CPU time 9.55 seconds
Started Apr 25 12:36:58 PM PDT 24
Finished Apr 25 12:37:09 PM PDT 24
Peak memory 211928 kb
Host smart-be2c5f9a-bf9f-4c30-910d-177c526c1b47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1368675393 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_kmac_err_chk.1368675393
Directory /workspace/11.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_intg_err.3255161020
Short name T103
Test name
Test status
Simulation time 10119000809 ps
CPU time 47.3 seconds
Started Apr 25 12:33:19 PM PDT 24
Finished Apr 25 12:34:08 PM PDT 24
Peak memory 211324 kb
Host smart-ddb06992-00b9-4cea-98d9-ac10684e88c8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3255161020 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_tl_in
tg_err.3255161020
Directory /workspace/7.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_passthru_mem_tl_intg_err.1922772456
Short name T88
Test name
Test status
Simulation time 43207361473 ps
CPU time 85.83 seconds
Started Apr 25 12:33:05 PM PDT 24
Finished Apr 25 12:34:34 PM PDT 24
Peak memory 210440 kb
Host smart-c76ddd28-11d1-4158-8ceb-08db3a998c1c
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1922772456 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_pa
ssthru_mem_tl_intg_err.1922772456
Directory /workspace/0.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/default/21.rom_ctrl_stress_all_with_rand_reset.2234696603
Short name T30
Test name
Test status
Simulation time 88276900413 ps
CPU time 2662.01 seconds
Started Apr 25 12:37:13 PM PDT 24
Finished Apr 25 01:21:38 PM PDT 24
Peak memory 236048 kb
Host smart-20a91636-503e-4cd2-9d64-216b5671cf24
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2234696603 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_stress_all_with_rand_reset.2234696603
Directory /workspace/21.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.rom_ctrl_stress_all.1289160117
Short name T220
Test name
Test status
Simulation time 225188607 ps
CPU time 11.08 seconds
Started Apr 25 12:37:03 PM PDT 24
Finished Apr 25 12:37:16 PM PDT 24
Peak memory 214520 kb
Host smart-55e0e798-bd0b-4c6b-8cca-40ef782ca62b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1289160117 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 6.rom_ctrl_stress_all.1289160117
Directory /workspace/6.rom_ctrl_stress_all/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_aliasing.1921554686
Short name T89
Test name
Test status
Simulation time 1984768794 ps
CPU time 15.21 seconds
Started Apr 25 12:33:10 PM PDT 24
Finished Apr 25 12:33:27 PM PDT 24
Peak memory 210336 kb
Host smart-51b382a9-59f8-4307-b5e5-4e1ef015847a
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1921554686 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_alia
sing.1921554686
Directory /workspace/0.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_bit_bash.1620558662
Short name T419
Test name
Test status
Simulation time 4103111899 ps
CPU time 6.03 seconds
Started Apr 25 12:33:10 PM PDT 24
Finished Apr 25 12:33:18 PM PDT 24
Peak memory 210480 kb
Host smart-798c45da-8819-4e91-b72a-a6def7d0c4b4
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1620558662 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_bit_
bash.1620558662
Directory /workspace/0.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_hw_reset.1020378352
Short name T397
Test name
Test status
Simulation time 3094632544 ps
CPU time 10.13 seconds
Started Apr 25 12:33:12 PM PDT 24
Finished Apr 25 12:33:24 PM PDT 24
Peak memory 210220 kb
Host smart-08ec9509-1576-4715-a4d0-242a2acc21a0
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1020378352 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_hw_r
eset.1020378352
Directory /workspace/0.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_mem_rw_with_rand_reset.3204413496
Short name T367
Test name
Test status
Simulation time 2955337082 ps
CPU time 9.97 seconds
Started Apr 25 12:33:10 PM PDT 24
Finished Apr 25 12:33:21 PM PDT 24
Peak memory 212616 kb
Host smart-cf795b25-a13f-4e35-80a4-2dd8f8834876
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3204413496 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 0.rom_ctrl_csr_mem_rw_with_rand_reset.3204413496
Directory /workspace/0.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_rw.2088296585
Short name T61
Test name
Test status
Simulation time 270695944 ps
CPU time 4.78 seconds
Started Apr 25 12:33:10 PM PDT 24
Finished Apr 25 12:33:17 PM PDT 24
Peak memory 210372 kb
Host smart-d287c9c7-40a2-4dd6-af0f-fe7426a9cb27
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2088296585 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_rw.2088296585
Directory /workspace/0.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_partial_access.3222611648
Short name T457
Test name
Test status
Simulation time 347146587 ps
CPU time 4.01 seconds
Started Apr 25 12:33:05 PM PDT 24
Finished Apr 25 12:33:12 PM PDT 24
Peak memory 210336 kb
Host smart-c18e2d85-9b0c-46bf-a60d-6381381e393e
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3222611648 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctr
l_mem_partial_access.3222611648
Directory /workspace/0.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_walk.1808683904
Short name T401
Test name
Test status
Simulation time 333349779 ps
CPU time 4.1 seconds
Started Apr 25 12:33:05 PM PDT 24
Finished Apr 25 12:33:12 PM PDT 24
Peak memory 210388 kb
Host smart-c22c6206-9beb-4b52-8490-bb9d314b758b
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1808683904 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_mem_walk
.1808683904
Directory /workspace/0.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_same_csr_outstanding.1394866612
Short name T429
Test name
Test status
Simulation time 347707445 ps
CPU time 6.5 seconds
Started Apr 25 12:33:01 PM PDT 24
Finished Apr 25 12:33:11 PM PDT 24
Peak memory 210396 kb
Host smart-873f06e2-b814-48e3-b283-792336233ea6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1394866612 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_c
trl_same_csr_outstanding.1394866612
Directory /workspace/0.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_errors.3271386297
Short name T376
Test name
Test status
Simulation time 416492571 ps
CPU time 9.58 seconds
Started Apr 25 12:33:10 PM PDT 24
Finished Apr 25 12:33:21 PM PDT 24
Peak memory 218692 kb
Host smart-3840cb70-bb73-456f-a9c8-defcd9c45607
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3271386297 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_tl_errors.3271386297
Directory /workspace/0.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_intg_err.1238611135
Short name T389
Test name
Test status
Simulation time 5765914976 ps
CPU time 37.43 seconds
Started Apr 25 12:33:02 PM PDT 24
Finished Apr 25 12:33:43 PM PDT 24
Peak memory 210568 kb
Host smart-45b6f156-79d5-4333-b6af-bfbeb22ee63a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1238611135 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_tl_in
tg_err.1238611135
Directory /workspace/0.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_aliasing.2453100906
Short name T69
Test name
Test status
Simulation time 3537577395 ps
CPU time 8.98 seconds
Started Apr 25 12:33:12 PM PDT 24
Finished Apr 25 12:33:22 PM PDT 24
Peak memory 210440 kb
Host smart-3e77ec65-2e1d-4a3c-9056-00cbdab1328b
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2453100906 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_alia
sing.2453100906
Directory /workspace/1.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_bit_bash.3582066964
Short name T381
Test name
Test status
Simulation time 825741096 ps
CPU time 5.99 seconds
Started Apr 25 12:33:10 PM PDT 24
Finished Apr 25 12:33:17 PM PDT 24
Peak memory 210376 kb
Host smart-d73291b2-5502-4d21-8073-b941645f801d
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3582066964 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_bit_
bash.3582066964
Directory /workspace/1.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_hw_reset.3777938433
Short name T382
Test name
Test status
Simulation time 404381300 ps
CPU time 7.29 seconds
Started Apr 25 12:33:11 PM PDT 24
Finished Apr 25 12:33:20 PM PDT 24
Peak memory 210368 kb
Host smart-7d65adc1-86f6-4cbf-a77d-f2c8672714c9
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3777938433 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_hw_r
eset.3777938433
Directory /workspace/1.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_mem_rw_with_rand_reset.2037665537
Short name T369
Test name
Test status
Simulation time 125822856 ps
CPU time 4.42 seconds
Started Apr 25 12:33:10 PM PDT 24
Finished Apr 25 12:33:17 PM PDT 24
Peak memory 218648 kb
Host smart-f74ba708-94e5-4d28-a999-e245fc66f076
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2037665537 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 1.rom_ctrl_csr_mem_rw_with_rand_reset.2037665537
Directory /workspace/1.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_rw.3428354880
Short name T404
Test name
Test status
Simulation time 2538363245 ps
CPU time 12.23 seconds
Started Apr 25 12:33:21 PM PDT 24
Finished Apr 25 12:33:34 PM PDT 24
Peak memory 210480 kb
Host smart-5fa1f546-cd2c-4ce7-8990-6105d0de4134
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3428354880 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_rw.3428354880
Directory /workspace/1.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_partial_access.314221623
Short name T398
Test name
Test status
Simulation time 13496714873 ps
CPU time 15.49 seconds
Started Apr 25 12:33:10 PM PDT 24
Finished Apr 25 12:33:27 PM PDT 24
Peak memory 210448 kb
Host smart-00e2362c-8210-47ac-9aec-0fd624e70b72
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=314221623 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl
_mem_partial_access.314221623
Directory /workspace/1.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_walk.1157433167
Short name T407
Test name
Test status
Simulation time 832796725 ps
CPU time 6.91 seconds
Started Apr 25 12:33:10 PM PDT 24
Finished Apr 25 12:33:19 PM PDT 24
Peak memory 210364 kb
Host smart-f69aa3b1-93f5-4069-acf7-70f390e38908
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1157433167 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_mem_walk
.1157433167
Directory /workspace/1.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_passthru_mem_tl_intg_err.3797843725
Short name T60
Test name
Test status
Simulation time 11117835508 ps
CPU time 87.91 seconds
Started Apr 25 12:33:05 PM PDT 24
Finished Apr 25 12:34:36 PM PDT 24
Peak memory 210584 kb
Host smart-75ea78e5-2b92-4795-878c-7ddee365d825
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3797843725 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_pa
ssthru_mem_tl_intg_err.3797843725
Directory /workspace/1.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_same_csr_outstanding.649821714
Short name T86
Test name
Test status
Simulation time 7782511560 ps
CPU time 13.69 seconds
Started Apr 25 12:33:09 PM PDT 24
Finished Apr 25 12:33:24 PM PDT 24
Peak memory 210524 kb
Host smart-4b734ad9-7283-4bae-b8c2-3ad5f42249ae
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=649821714 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ct
rl_same_csr_outstanding.649821714
Directory /workspace/1.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_errors.1481562793
Short name T430
Test name
Test status
Simulation time 1879228242 ps
CPU time 17.23 seconds
Started Apr 25 12:33:10 PM PDT 24
Finished Apr 25 12:33:29 PM PDT 24
Peak memory 218716 kb
Host smart-f1adf0de-93ef-49c7-943c-19fbdc55847b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1481562793 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_tl_errors.1481562793
Directory /workspace/1.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_intg_err.1614510724
Short name T431
Test name
Test status
Simulation time 1147773418 ps
CPU time 73.38 seconds
Started Apr 25 12:33:05 PM PDT 24
Finished Apr 25 12:34:22 PM PDT 24
Peak memory 210456 kb
Host smart-0c9679ca-c880-41aa-a650-08f317176340
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1614510724 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_tl_in
tg_err.1614510724
Directory /workspace/1.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_mem_rw_with_rand_reset.825791688
Short name T417
Test name
Test status
Simulation time 1690238899 ps
CPU time 13.69 seconds
Started Apr 25 12:33:19 PM PDT 24
Finished Apr 25 12:33:34 PM PDT 24
Peak memory 218652 kb
Host smart-7fbd7acc-824e-4a11-ab2c-491a384dcc3c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=825791688 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 10.rom_ctrl_csr_mem_rw_with_rand_reset.825791688
Directory /workspace/10.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_rw.1855454085
Short name T418
Test name
Test status
Simulation time 85401296 ps
CPU time 4.45 seconds
Started Apr 25 12:33:14 PM PDT 24
Finished Apr 25 12:33:19 PM PDT 24
Peak memory 210108 kb
Host smart-73f325d4-7421-4bcb-b9ab-1e5538a06bde
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1855454085 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_csr_rw.1855454085
Directory /workspace/10.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_passthru_mem_tl_intg_err.1250971221
Short name T57
Test name
Test status
Simulation time 19229650460 ps
CPU time 40.24 seconds
Started Apr 25 12:33:21 PM PDT 24
Finished Apr 25 12:34:03 PM PDT 24
Peak memory 210628 kb
Host smart-f5014196-27d0-4a6d-bd9c-21783c0b7096
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1250971221 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_p
assthru_mem_tl_intg_err.1250971221
Directory /workspace/10.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_same_csr_outstanding.1880642188
Short name T442
Test name
Test status
Simulation time 15900852879 ps
CPU time 18.53 seconds
Started Apr 25 12:33:18 PM PDT 24
Finished Apr 25 12:33:38 PM PDT 24
Peak memory 210512 kb
Host smart-ebfd0813-513b-456a-9507-4ba355275142
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1880642188 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_
ctrl_same_csr_outstanding.1880642188
Directory /workspace/10.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_errors.720152768
Short name T456
Test name
Test status
Simulation time 171956118 ps
CPU time 6.72 seconds
Started Apr 25 12:33:19 PM PDT 24
Finished Apr 25 12:33:28 PM PDT 24
Peak memory 218600 kb
Host smart-d97aeeb8-e9bf-4428-b598-ce7cb03a6f18
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=720152768 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_tl_errors.720152768
Directory /workspace/10.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_intg_err.232310545
Short name T46
Test name
Test status
Simulation time 944194794 ps
CPU time 38.4 seconds
Started Apr 25 12:33:16 PM PDT 24
Finished Apr 25 12:33:55 PM PDT 24
Peak memory 211212 kb
Host smart-df3f030b-4564-4f83-9781-9e8c12a8b380
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=232310545 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_tl_in
tg_err.232310545
Directory /workspace/10.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_mem_rw_with_rand_reset.3774080427
Short name T452
Test name
Test status
Simulation time 531510944 ps
CPU time 5.32 seconds
Started Apr 25 12:33:23 PM PDT 24
Finished Apr 25 12:33:30 PM PDT 24
Peak memory 218708 kb
Host smart-612f6d14-2a81-45fa-9a2c-ae9875143cd0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3774080427 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 11.rom_ctrl_csr_mem_rw_with_rand_reset.3774080427
Directory /workspace/11.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_rw.4180941854
Short name T90
Test name
Test status
Simulation time 1190446650 ps
CPU time 11.09 seconds
Started Apr 25 12:33:27 PM PDT 24
Finished Apr 25 12:33:39 PM PDT 24
Peak memory 210332 kb
Host smart-30b31b2d-1ed0-4053-aee2-16f1173cb2b7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4180941854 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_csr_rw.4180941854
Directory /workspace/11.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_passthru_mem_tl_intg_err.1499696344
Short name T74
Test name
Test status
Simulation time 7789439575 ps
CPU time 74.19 seconds
Started Apr 25 12:33:20 PM PDT 24
Finished Apr 25 12:34:36 PM PDT 24
Peak memory 210532 kb
Host smart-1ce08529-3db9-4219-8cbc-5b4ce5acece5
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1499696344 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_p
assthru_mem_tl_intg_err.1499696344
Directory /workspace/11.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_same_csr_outstanding.185069492
Short name T80
Test name
Test status
Simulation time 3734146314 ps
CPU time 14.75 seconds
Started Apr 25 12:33:23 PM PDT 24
Finished Apr 25 12:33:39 PM PDT 24
Peak memory 210500 kb
Host smart-7e0008cb-b95f-487e-ac77-3ebd316e628a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=185069492 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_c
trl_same_csr_outstanding.185069492
Directory /workspace/11.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_errors.3778770387
Short name T368
Test name
Test status
Simulation time 1145834114 ps
CPU time 12.9 seconds
Started Apr 25 12:33:18 PM PDT 24
Finished Apr 25 12:33:32 PM PDT 24
Peak memory 218660 kb
Host smart-a5800b34-ee7d-4710-b0f1-7d85f249ae33
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3778770387 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_tl_errors.3778770387
Directory /workspace/11.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_intg_err.2530182352
Short name T97
Test name
Test status
Simulation time 15701219919 ps
CPU time 47.57 seconds
Started Apr 25 12:33:23 PM PDT 24
Finished Apr 25 12:34:12 PM PDT 24
Peak memory 211272 kb
Host smart-b57c2f03-c46e-43cc-92c0-eacb6da15b15
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2530182352 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_tl_i
ntg_err.2530182352
Directory /workspace/11.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_mem_rw_with_rand_reset.2848195981
Short name T426
Test name
Test status
Simulation time 302819864 ps
CPU time 6.39 seconds
Started Apr 25 12:33:24 PM PDT 24
Finished Apr 25 12:33:31 PM PDT 24
Peak memory 212592 kb
Host smart-2d7bb435-49c2-43f4-88a4-b605308a5224
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2848195981 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 12.rom_ctrl_csr_mem_rw_with_rand_reset.2848195981
Directory /workspace/12.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_rw.2706937549
Short name T375
Test name
Test status
Simulation time 6002388258 ps
CPU time 13.12 seconds
Started Apr 25 12:33:25 PM PDT 24
Finished Apr 25 12:33:40 PM PDT 24
Peak memory 210516 kb
Host smart-ebc51e96-353f-4448-b3a2-3d2b89abed5a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2706937549 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_csr_rw.2706937549
Directory /workspace/12.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_passthru_mem_tl_intg_err.2146656414
Short name T435
Test name
Test status
Simulation time 55537410332 ps
CPU time 60.01 seconds
Started Apr 25 12:33:23 PM PDT 24
Finished Apr 25 12:34:25 PM PDT 24
Peak memory 210540 kb
Host smart-bbb04cc0-f3f8-4e29-bb50-30ec62a797ed
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2146656414 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_p
assthru_mem_tl_intg_err.2146656414
Directory /workspace/12.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_same_csr_outstanding.153078338
Short name T434
Test name
Test status
Simulation time 1959971902 ps
CPU time 15.57 seconds
Started Apr 25 12:33:23 PM PDT 24
Finished Apr 25 12:33:40 PM PDT 24
Peak memory 210428 kb
Host smart-13401cfd-3dc3-4a8f-ab39-20030863b55a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=153078338 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_c
trl_same_csr_outstanding.153078338
Directory /workspace/12.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_errors.2075236433
Short name T384
Test name
Test status
Simulation time 2349410363 ps
CPU time 16.1 seconds
Started Apr 25 12:33:23 PM PDT 24
Finished Apr 25 12:33:41 PM PDT 24
Peak memory 218712 kb
Host smart-68744733-9d94-466b-8d00-2093051186bc
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2075236433 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_tl_errors.2075236433
Directory /workspace/12.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_intg_err.4203190735
Short name T96
Test name
Test status
Simulation time 3500432193 ps
CPU time 74.55 seconds
Started Apr 25 12:33:32 PM PDT 24
Finished Apr 25 12:34:50 PM PDT 24
Peak memory 212264 kb
Host smart-b77a9678-ad9a-4a42-ba87-0f9c7087c615
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4203190735 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_tl_i
ntg_err.4203190735
Directory /workspace/12.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_mem_rw_with_rand_reset.1919152543
Short name T374
Test name
Test status
Simulation time 1477135562 ps
CPU time 13.07 seconds
Started Apr 25 12:33:21 PM PDT 24
Finished Apr 25 12:33:36 PM PDT 24
Peak memory 218580 kb
Host smart-346471f8-bcdd-49ad-9fd1-9fc2973519ed
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1919152543 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 13.rom_ctrl_csr_mem_rw_with_rand_reset.1919152543
Directory /workspace/13.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_rw.3043901290
Short name T55
Test name
Test status
Simulation time 750606186 ps
CPU time 5.36 seconds
Started Apr 25 12:33:27 PM PDT 24
Finished Apr 25 12:33:34 PM PDT 24
Peak memory 210300 kb
Host smart-68969800-4344-48e3-a4bc-8d0baebedd5b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3043901290 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_csr_rw.3043901290
Directory /workspace/13.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_same_csr_outstanding.2126356320
Short name T461
Test name
Test status
Simulation time 1379217813 ps
CPU time 4.16 seconds
Started Apr 25 12:33:24 PM PDT 24
Finished Apr 25 12:33:29 PM PDT 24
Peak memory 210388 kb
Host smart-19c0eef8-712a-4d37-ae2f-268257a60a61
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2126356320 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_
ctrl_same_csr_outstanding.2126356320
Directory /workspace/13.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_errors.3890222547
Short name T388
Test name
Test status
Simulation time 1948467568 ps
CPU time 17.01 seconds
Started Apr 25 12:33:44 PM PDT 24
Finished Apr 25 12:34:04 PM PDT 24
Peak memory 213396 kb
Host smart-3efcc262-e8bb-4397-af28-2d036fc4ed8b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3890222547 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_tl_errors.3890222547
Directory /workspace/13.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_intg_err.708516008
Short name T95
Test name
Test status
Simulation time 1756686282 ps
CPU time 37.68 seconds
Started Apr 25 12:33:27 PM PDT 24
Finished Apr 25 12:34:06 PM PDT 24
Peak memory 212216 kb
Host smart-15ed6158-4c5b-4a85-a1d5-5d810c7fae03
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=708516008 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_tl_in
tg_err.708516008
Directory /workspace/13.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_mem_rw_with_rand_reset.4184074353
Short name T370
Test name
Test status
Simulation time 14155093036 ps
CPU time 11.75 seconds
Started Apr 25 12:33:25 PM PDT 24
Finished Apr 25 12:33:39 PM PDT 24
Peak memory 218756 kb
Host smart-2af2afb0-a50e-46c8-a5da-07f576989713
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4184074353 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 14.rom_ctrl_csr_mem_rw_with_rand_reset.4184074353
Directory /workspace/14.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_rw.2401012160
Short name T408
Test name
Test status
Simulation time 86248889 ps
CPU time 4.09 seconds
Started Apr 25 12:33:26 PM PDT 24
Finished Apr 25 12:33:32 PM PDT 24
Peak memory 210396 kb
Host smart-a451a7fe-5584-453c-ba0d-ae989b1135ed
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2401012160 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_csr_rw.2401012160
Directory /workspace/14.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_passthru_mem_tl_intg_err.2397979420
Short name T75
Test name
Test status
Simulation time 92526709751 ps
CPU time 44.28 seconds
Started Apr 25 12:33:22 PM PDT 24
Finished Apr 25 12:34:07 PM PDT 24
Peak memory 210516 kb
Host smart-bcc5933a-5483-48b3-b0ee-b7308d7506d2
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2397979420 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_p
assthru_mem_tl_intg_err.2397979420
Directory /workspace/14.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_same_csr_outstanding.2057060397
Short name T411
Test name
Test status
Simulation time 347171137 ps
CPU time 4.15 seconds
Started Apr 25 12:33:23 PM PDT 24
Finished Apr 25 12:33:29 PM PDT 24
Peak memory 210408 kb
Host smart-7a115bec-831a-4e14-b9f3-7051f88523ab
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2057060397 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_
ctrl_same_csr_outstanding.2057060397
Directory /workspace/14.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_errors.220808399
Short name T449
Test name
Test status
Simulation time 1153817188 ps
CPU time 13.15 seconds
Started Apr 25 12:33:23 PM PDT 24
Finished Apr 25 12:33:38 PM PDT 24
Peak memory 218560 kb
Host smart-11f28d50-8b39-4c4f-b532-3ff99560dbb1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=220808399 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_tl_errors.220808399
Directory /workspace/14.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_intg_err.4113027662
Short name T44
Test name
Test status
Simulation time 1866734252 ps
CPU time 77.53 seconds
Started Apr 25 12:33:28 PM PDT 24
Finished Apr 25 12:34:47 PM PDT 24
Peak memory 211188 kb
Host smart-21aa0f4c-f576-44a4-bde3-3139edb181ab
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4113027662 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_tl_i
ntg_err.4113027662
Directory /workspace/14.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_mem_rw_with_rand_reset.3541670774
Short name T371
Test name
Test status
Simulation time 2194586904 ps
CPU time 17.2 seconds
Started Apr 25 12:33:27 PM PDT 24
Finished Apr 25 12:33:46 PM PDT 24
Peak memory 218676 kb
Host smart-1c20c2b1-a1b1-4783-b172-36bb2c0eb4d6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3541670774 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 15.rom_ctrl_csr_mem_rw_with_rand_reset.3541670774
Directory /workspace/15.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_rw.662308535
Short name T394
Test name
Test status
Simulation time 346808572 ps
CPU time 4.41 seconds
Started Apr 25 12:33:23 PM PDT 24
Finished Apr 25 12:33:29 PM PDT 24
Peak memory 210368 kb
Host smart-f231c09a-a37c-4592-be32-3e7b2f3f9268
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=662308535 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_csr_rw.662308535
Directory /workspace/15.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_passthru_mem_tl_intg_err.3188805254
Short name T78
Test name
Test status
Simulation time 382394809 ps
CPU time 19.03 seconds
Started Apr 25 12:33:28 PM PDT 24
Finished Apr 25 12:33:49 PM PDT 24
Peak memory 210440 kb
Host smart-b84e6f7c-006c-4c48-b977-97ce0664c90f
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3188805254 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_p
assthru_mem_tl_intg_err.3188805254
Directory /workspace/15.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_same_csr_outstanding.1445715475
Short name T81
Test name
Test status
Simulation time 813617567 ps
CPU time 5.96 seconds
Started Apr 25 12:33:28 PM PDT 24
Finished Apr 25 12:33:35 PM PDT 24
Peak memory 210320 kb
Host smart-6c85a9c9-e2bf-4ced-89ca-777aae6bede3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1445715475 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_
ctrl_same_csr_outstanding.1445715475
Directory /workspace/15.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_errors.2004125589
Short name T390
Test name
Test status
Simulation time 1451889553 ps
CPU time 14.93 seconds
Started Apr 25 12:33:26 PM PDT 24
Finished Apr 25 12:33:42 PM PDT 24
Peak memory 218652 kb
Host smart-7cfb2b5b-a8ce-48e0-955c-331e0ba66f44
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2004125589 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_tl_errors.2004125589
Directory /workspace/15.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_intg_err.3158814100
Short name T94
Test name
Test status
Simulation time 1319758071 ps
CPU time 72.87 seconds
Started Apr 25 12:33:23 PM PDT 24
Finished Apr 25 12:34:38 PM PDT 24
Peak memory 218580 kb
Host smart-b74b3ef8-f9c0-4d44-b41c-1d71162f0bd2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3158814100 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_tl_i
ntg_err.3158814100
Directory /workspace/15.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_mem_rw_with_rand_reset.1864342057
Short name T378
Test name
Test status
Simulation time 2596565746 ps
CPU time 13.24 seconds
Started Apr 25 12:33:26 PM PDT 24
Finished Apr 25 12:33:41 PM PDT 24
Peak memory 218696 kb
Host smart-df9f24fe-e84e-46cd-adfd-04b36d9bedaf
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1864342057 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 16.rom_ctrl_csr_mem_rw_with_rand_reset.1864342057
Directory /workspace/16.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_rw.4215891288
Short name T59
Test name
Test status
Simulation time 332729401 ps
CPU time 4.14 seconds
Started Apr 25 12:33:22 PM PDT 24
Finished Apr 25 12:33:27 PM PDT 24
Peak memory 210328 kb
Host smart-5106e5b6-5051-4ddb-afb1-8666348a0262
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4215891288 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_csr_rw.4215891288
Directory /workspace/16.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_passthru_mem_tl_intg_err.3223210370
Short name T437
Test name
Test status
Simulation time 6835261719 ps
CPU time 55.36 seconds
Started Apr 25 12:33:24 PM PDT 24
Finished Apr 25 12:34:21 PM PDT 24
Peak memory 210500 kb
Host smart-f7490949-0f97-4de3-b493-925c8cc1abb3
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3223210370 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_p
assthru_mem_tl_intg_err.3223210370
Directory /workspace/16.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_same_csr_outstanding.1701414549
Short name T399
Test name
Test status
Simulation time 86334183 ps
CPU time 4.61 seconds
Started Apr 25 12:33:28 PM PDT 24
Finished Apr 25 12:33:34 PM PDT 24
Peak memory 210288 kb
Host smart-75022967-2284-44e4-a9d0-f81d62f1c814
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1701414549 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_
ctrl_same_csr_outstanding.1701414549
Directory /workspace/16.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_errors.1477755344
Short name T386
Test name
Test status
Simulation time 2089629201 ps
CPU time 19.93 seconds
Started Apr 25 12:33:23 PM PDT 24
Finished Apr 25 12:33:44 PM PDT 24
Peak memory 218628 kb
Host smart-2ed108f8-88df-49b9-8c22-804004f30b00
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1477755344 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_tl_errors.1477755344
Directory /workspace/16.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_intg_err.181569769
Short name T104
Test name
Test status
Simulation time 2291979581 ps
CPU time 36.16 seconds
Started Apr 25 12:33:24 PM PDT 24
Finished Apr 25 12:34:01 PM PDT 24
Peak memory 210476 kb
Host smart-7f2d726a-ccd7-4e2c-a581-61029223bd71
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=181569769 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_tl_in
tg_err.181569769
Directory /workspace/16.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_mem_rw_with_rand_reset.1323319388
Short name T440
Test name
Test status
Simulation time 228594780 ps
CPU time 4.7 seconds
Started Apr 25 12:33:28 PM PDT 24
Finished Apr 25 12:33:35 PM PDT 24
Peak memory 218636 kb
Host smart-1cf0c2ea-85de-4968-ac52-b6b8843024e5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1323319388 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 17.rom_ctrl_csr_mem_rw_with_rand_reset.1323319388
Directory /workspace/17.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_rw.1229173653
Short name T439
Test name
Test status
Simulation time 1881648172 ps
CPU time 15.07 seconds
Started Apr 25 12:33:22 PM PDT 24
Finished Apr 25 12:33:39 PM PDT 24
Peak memory 210396 kb
Host smart-86b05ebb-7f8f-4f3c-adc6-ce34b3811d08
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1229173653 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_csr_rw.1229173653
Directory /workspace/17.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_passthru_mem_tl_intg_err.3900103510
Short name T453
Test name
Test status
Simulation time 4415454703 ps
CPU time 27.16 seconds
Started Apr 25 12:33:23 PM PDT 24
Finished Apr 25 12:33:51 PM PDT 24
Peak memory 211576 kb
Host smart-249fccfe-ec27-40bb-a473-dd4573af5002
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3900103510 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_p
assthru_mem_tl_intg_err.3900103510
Directory /workspace/17.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_same_csr_outstanding.1376733307
Short name T405
Test name
Test status
Simulation time 2892862377 ps
CPU time 8.67 seconds
Started Apr 25 12:33:25 PM PDT 24
Finished Apr 25 12:33:34 PM PDT 24
Peak memory 210480 kb
Host smart-9078e0da-3bbb-4b15-97b7-ba62535ddf33
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1376733307 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_
ctrl_same_csr_outstanding.1376733307
Directory /workspace/17.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_errors.3741944160
Short name T372
Test name
Test status
Simulation time 3927755637 ps
CPU time 13.71 seconds
Started Apr 25 12:33:26 PM PDT 24
Finished Apr 25 12:33:41 PM PDT 24
Peak memory 218712 kb
Host smart-f12185a9-ad0c-47f6-85e9-f7c0627ebd78
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3741944160 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_tl_errors.3741944160
Directory /workspace/17.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_intg_err.1797853535
Short name T101
Test name
Test status
Simulation time 543975322 ps
CPU time 36.65 seconds
Started Apr 25 12:33:27 PM PDT 24
Finished Apr 25 12:34:05 PM PDT 24
Peak memory 211072 kb
Host smart-0d1d07bf-0808-4ce7-9db9-15eb7a4d9e8c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1797853535 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_tl_i
ntg_err.1797853535
Directory /workspace/17.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_mem_rw_with_rand_reset.1861195814
Short name T402
Test name
Test status
Simulation time 459024736 ps
CPU time 4.54 seconds
Started Apr 25 12:33:34 PM PDT 24
Finished Apr 25 12:33:42 PM PDT 24
Peak memory 212732 kb
Host smart-b11f39d1-6485-4382-8bd2-b28fefde3e7b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1861195814 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 18.rom_ctrl_csr_mem_rw_with_rand_reset.1861195814
Directory /workspace/18.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_rw.2575510232
Short name T70
Test name
Test status
Simulation time 5261067776 ps
CPU time 12.36 seconds
Started Apr 25 12:33:31 PM PDT 24
Finished Apr 25 12:33:46 PM PDT 24
Peak memory 210504 kb
Host smart-5d0cf023-03cb-41de-babd-094a931fecb0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2575510232 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_csr_rw.2575510232
Directory /workspace/18.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_passthru_mem_tl_intg_err.2492864201
Short name T395
Test name
Test status
Simulation time 1342978594 ps
CPU time 27.4 seconds
Started Apr 25 12:33:23 PM PDT 24
Finished Apr 25 12:33:52 PM PDT 24
Peak memory 210444 kb
Host smart-fd8a520d-64c9-4efe-98bd-3db84dc2e62f
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2492864201 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_p
assthru_mem_tl_intg_err.2492864201
Directory /workspace/18.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_same_csr_outstanding.1837290155
Short name T83
Test name
Test status
Simulation time 3600898726 ps
CPU time 15.21 seconds
Started Apr 25 12:33:30 PM PDT 24
Finished Apr 25 12:33:47 PM PDT 24
Peak memory 210456 kb
Host smart-7bd05a33-eaf0-4f23-bc31-4464ae74fe11
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1837290155 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_
ctrl_same_csr_outstanding.1837290155
Directory /workspace/18.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_errors.2734059386
Short name T441
Test name
Test status
Simulation time 3599864993 ps
CPU time 16.2 seconds
Started Apr 25 12:33:32 PM PDT 24
Finished Apr 25 12:33:51 PM PDT 24
Peak memory 218616 kb
Host smart-20f062e7-3524-4d6e-9ce5-621842fedbb3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2734059386 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_tl_errors.2734059386
Directory /workspace/18.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_intg_err.4038094455
Short name T427
Test name
Test status
Simulation time 8456062708 ps
CPU time 47.61 seconds
Started Apr 25 12:33:34 PM PDT 24
Finished Apr 25 12:34:25 PM PDT 24
Peak memory 211440 kb
Host smart-799f7604-dec2-40dc-8936-79a6979c3454
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4038094455 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_tl_i
ntg_err.4038094455
Directory /workspace/18.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_mem_rw_with_rand_reset.2618153591
Short name T392
Test name
Test status
Simulation time 264367050 ps
CPU time 7.19 seconds
Started Apr 25 12:33:36 PM PDT 24
Finished Apr 25 12:33:48 PM PDT 24
Peak memory 218688 kb
Host smart-0b88d9da-e13a-492b-a140-946057ddb36a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2618153591 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 19.rom_ctrl_csr_mem_rw_with_rand_reset.2618153591
Directory /workspace/19.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_rw.1070240757
Short name T433
Test name
Test status
Simulation time 1575346325 ps
CPU time 12.76 seconds
Started Apr 25 12:33:31 PM PDT 24
Finished Apr 25 12:33:46 PM PDT 24
Peak memory 210396 kb
Host smart-0f26b4ff-c902-4990-91ce-adee6d35949b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1070240757 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_csr_rw.1070240757
Directory /workspace/19.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_passthru_mem_tl_intg_err.412575164
Short name T451
Test name
Test status
Simulation time 1730052830 ps
CPU time 18.7 seconds
Started Apr 25 12:33:33 PM PDT 24
Finished Apr 25 12:33:55 PM PDT 24
Peak memory 210480 kb
Host smart-3c84b351-b274-4563-b1df-5d4addf5be71
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=412575164 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_pa
ssthru_mem_tl_intg_err.412575164
Directory /workspace/19.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_same_csr_outstanding.2900852501
Short name T84
Test name
Test status
Simulation time 6430156248 ps
CPU time 16.07 seconds
Started Apr 25 12:33:32 PM PDT 24
Finished Apr 25 12:33:51 PM PDT 24
Peak memory 210528 kb
Host smart-31bebde9-ce59-497e-a03a-a3f10248fb39
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2900852501 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_
ctrl_same_csr_outstanding.2900852501
Directory /workspace/19.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_errors.694397357
Short name T425
Test name
Test status
Simulation time 29180783956 ps
CPU time 21.16 seconds
Started Apr 25 12:33:29 PM PDT 24
Finished Apr 25 12:33:52 PM PDT 24
Peak memory 218736 kb
Host smart-c2ec9d57-d795-40dc-9091-9f2448c2a5de
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=694397357 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_tl_errors.694397357
Directory /workspace/19.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_intg_err.4287068966
Short name T102
Test name
Test status
Simulation time 8768309878 ps
CPU time 78.38 seconds
Started Apr 25 12:33:35 PM PDT 24
Finished Apr 25 12:34:59 PM PDT 24
Peak memory 218684 kb
Host smart-5436ab76-c5b9-4bd5-a2be-013dab96d458
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4287068966 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_tl_i
ntg_err.4287068966
Directory /workspace/19.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_aliasing.1577412676
Short name T58
Test name
Test status
Simulation time 4617251648 ps
CPU time 10.75 seconds
Started Apr 25 12:33:22 PM PDT 24
Finished Apr 25 12:33:34 PM PDT 24
Peak memory 210540 kb
Host smart-f8c77c33-ccfe-4d2b-bf94-c9173e99b30d
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1577412676 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_alia
sing.1577412676
Directory /workspace/2.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_bit_bash.2320096832
Short name T416
Test name
Test status
Simulation time 10190024398 ps
CPU time 16.59 seconds
Started Apr 25 12:33:09 PM PDT 24
Finished Apr 25 12:33:28 PM PDT 24
Peak memory 210508 kb
Host smart-7b43d8bf-788e-48c3-a1ed-ea89a0c49698
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2320096832 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_bit_
bash.2320096832
Directory /workspace/2.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_hw_reset.1558170698
Short name T391
Test name
Test status
Simulation time 10034301039 ps
CPU time 17.13 seconds
Started Apr 25 12:33:13 PM PDT 24
Finished Apr 25 12:33:31 PM PDT 24
Peak memory 210472 kb
Host smart-3f77cec8-cce2-4cfd-8d44-6691d3783cad
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1558170698 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_hw_r
eset.1558170698
Directory /workspace/2.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_mem_rw_with_rand_reset.573337861
Short name T448
Test name
Test status
Simulation time 3124030515 ps
CPU time 8.83 seconds
Started Apr 25 12:33:11 PM PDT 24
Finished Apr 25 12:33:21 PM PDT 24
Peak memory 212468 kb
Host smart-79cbf119-7927-4905-b147-81fb21aa697c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=573337861 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 2.rom_ctrl_csr_mem_rw_with_rand_reset.573337861
Directory /workspace/2.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_rw.3652178340
Short name T436
Test name
Test status
Simulation time 749165882 ps
CPU time 8.72 seconds
Started Apr 25 12:33:11 PM PDT 24
Finished Apr 25 12:33:22 PM PDT 24
Peak memory 210416 kb
Host smart-4f656065-4ef3-4eba-84d0-e2771286e867
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3652178340 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_rw.3652178340
Directory /workspace/2.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_partial_access.1430487152
Short name T445
Test name
Test status
Simulation time 389356429 ps
CPU time 6.53 seconds
Started Apr 25 12:33:08 PM PDT 24
Finished Apr 25 12:33:16 PM PDT 24
Peak memory 210140 kb
Host smart-3e95a980-bf1a-4958-bf3f-754d23ecf2be
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1430487152 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctr
l_mem_partial_access.1430487152
Directory /workspace/2.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_walk.775063614
Short name T365
Test name
Test status
Simulation time 1792245723 ps
CPU time 14.38 seconds
Started Apr 25 12:33:08 PM PDT 24
Finished Apr 25 12:33:24 PM PDT 24
Peak memory 210320 kb
Host smart-178d2c2f-f50a-45fb-8155-59ec94f02732
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=775063614 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_mem_walk.
775063614
Directory /workspace/2.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_passthru_mem_tl_intg_err.1751390584
Short name T56
Test name
Test status
Simulation time 7197779749 ps
CPU time 70.28 seconds
Started Apr 25 12:33:09 PM PDT 24
Finished Apr 25 12:34:21 PM PDT 24
Peak memory 210604 kb
Host smart-dfce31b6-749c-4162-b097-80ff8241f520
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1751390584 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_pa
ssthru_mem_tl_intg_err.1751390584
Directory /workspace/2.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_same_csr_outstanding.2609208243
Short name T400
Test name
Test status
Simulation time 1184002581 ps
CPU time 10.72 seconds
Started Apr 25 12:33:12 PM PDT 24
Finished Apr 25 12:33:25 PM PDT 24
Peak memory 210240 kb
Host smart-d1a673d2-2133-44dd-96ce-5c5438b4a15a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2609208243 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_c
trl_same_csr_outstanding.2609208243
Directory /workspace/2.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_errors.4144870001
Short name T446
Test name
Test status
Simulation time 331531689 ps
CPU time 8.66 seconds
Started Apr 25 12:33:07 PM PDT 24
Finished Apr 25 12:33:18 PM PDT 24
Peak memory 218708 kb
Host smart-82d81f48-2f6b-41e7-a942-508f4e14f060
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4144870001 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_tl_errors.4144870001
Directory /workspace/2.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_intg_err.2638921167
Short name T45
Test name
Test status
Simulation time 2080817906 ps
CPU time 46.3 seconds
Started Apr 25 12:33:11 PM PDT 24
Finished Apr 25 12:33:59 PM PDT 24
Peak memory 210384 kb
Host smart-09eeac18-f02f-4935-aace-137c76bc6a71
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2638921167 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_tl_in
tg_err.2638921167
Directory /workspace/2.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_aliasing.1713912
Short name T47
Test name
Test status
Simulation time 233171678 ps
CPU time 4.25 seconds
Started Apr 25 12:33:12 PM PDT 24
Finished Apr 25 12:33:18 PM PDT 24
Peak memory 210320 kb
Host smart-c1c0f7ba-696a-43f6-882e-8792ac2ddbc3
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1713912 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_aliasin
g.1713912
Directory /workspace/3.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_bit_bash.1106761963
Short name T366
Test name
Test status
Simulation time 10425577498 ps
CPU time 15.36 seconds
Started Apr 25 12:33:09 PM PDT 24
Finished Apr 25 12:33:26 PM PDT 24
Peak memory 210532 kb
Host smart-a4ebc6d0-fa34-45d9-a3a2-a36980671905
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1106761963 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_bit_
bash.1106761963
Directory /workspace/3.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_hw_reset.925000910
Short name T71
Test name
Test status
Simulation time 525748646 ps
CPU time 10.27 seconds
Started Apr 25 12:33:10 PM PDT 24
Finished Apr 25 12:33:22 PM PDT 24
Peak memory 210388 kb
Host smart-50574f9c-20ca-4769-8853-dac0470cbc7a
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=925000910 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_hw_re
set.925000910
Directory /workspace/3.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_mem_rw_with_rand_reset.4239669984
Short name T380
Test name
Test status
Simulation time 522375649 ps
CPU time 6.11 seconds
Started Apr 25 12:33:11 PM PDT 24
Finished Apr 25 12:33:19 PM PDT 24
Peak memory 212860 kb
Host smart-61487ef3-73a0-4b6b-9729-e469b65900dd
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4239669984 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 3.rom_ctrl_csr_mem_rw_with_rand_reset.4239669984
Directory /workspace/3.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_rw.2762155969
Short name T48
Test name
Test status
Simulation time 9497971360 ps
CPU time 15.43 seconds
Started Apr 25 12:33:11 PM PDT 24
Finished Apr 25 12:33:28 PM PDT 24
Peak memory 210512 kb
Host smart-2a2fbd88-77cf-4294-81d7-d78e6fd0d482
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2762155969 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_rw.2762155969
Directory /workspace/3.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_partial_access.2622845962
Short name T412
Test name
Test status
Simulation time 3797383063 ps
CPU time 12.9 seconds
Started Apr 25 12:33:11 PM PDT 24
Finished Apr 25 12:33:26 PM PDT 24
Peak memory 210308 kb
Host smart-49615f44-6e7e-4d79-8b90-1e5ac29249ea
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2622845962 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctr
l_mem_partial_access.2622845962
Directory /workspace/3.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_walk.507832791
Short name T460
Test name
Test status
Simulation time 654981839 ps
CPU time 8.3 seconds
Started Apr 25 12:33:12 PM PDT 24
Finished Apr 25 12:33:22 PM PDT 24
Peak memory 210300 kb
Host smart-10f70a5a-710e-4acc-8bca-3bb1eb3041f1
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=507832791 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_mem_walk.
507832791
Directory /workspace/3.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_passthru_mem_tl_intg_err.3997488550
Short name T92
Test name
Test status
Simulation time 1591744905 ps
CPU time 28.92 seconds
Started Apr 25 12:33:11 PM PDT 24
Finished Apr 25 12:33:42 PM PDT 24
Peak memory 210304 kb
Host smart-62faef53-c3f5-40b9-8ebf-51ca128d6b74
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3997488550 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_pa
ssthru_mem_tl_intg_err.3997488550
Directory /workspace/3.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_same_csr_outstanding.1656751323
Short name T403
Test name
Test status
Simulation time 174616122 ps
CPU time 4.26 seconds
Started Apr 25 12:33:11 PM PDT 24
Finished Apr 25 12:33:18 PM PDT 24
Peak memory 210368 kb
Host smart-fda2d6ca-4a46-442d-ae99-773778ad1dc3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1656751323 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_c
trl_same_csr_outstanding.1656751323
Directory /workspace/3.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_errors.4105802339
Short name T379
Test name
Test status
Simulation time 7340188281 ps
CPU time 17 seconds
Started Apr 25 12:33:09 PM PDT 24
Finished Apr 25 12:33:28 PM PDT 24
Peak memory 218740 kb
Host smart-8bd7dba0-d2b3-4dc6-813f-61910de5602e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4105802339 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_tl_errors.4105802339
Directory /workspace/3.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_aliasing.2703927747
Short name T424
Test name
Test status
Simulation time 3002914193 ps
CPU time 13.02 seconds
Started Apr 25 12:33:20 PM PDT 24
Finished Apr 25 12:33:34 PM PDT 24
Peak memory 210464 kb
Host smart-02994ee2-a83b-41aa-9c8e-b8708b7e1717
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2703927747 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_alia
sing.2703927747
Directory /workspace/4.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_bit_bash.2487317626
Short name T413
Test name
Test status
Simulation time 923840477 ps
CPU time 4.44 seconds
Started Apr 25 12:33:20 PM PDT 24
Finished Apr 25 12:33:26 PM PDT 24
Peak memory 210288 kb
Host smart-9ba1168a-ebc0-4863-932c-9f0407311053
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2487317626 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_bit_
bash.2487317626
Directory /workspace/4.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_hw_reset.4066974707
Short name T72
Test name
Test status
Simulation time 2865522356 ps
CPU time 14.22 seconds
Started Apr 25 12:33:21 PM PDT 24
Finished Apr 25 12:33:37 PM PDT 24
Peak memory 210480 kb
Host smart-c2767c72-f318-429f-b4d8-fbe64afa8e6a
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4066974707 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_hw_r
eset.4066974707
Directory /workspace/4.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_mem_rw_with_rand_reset.1007658404
Short name T410
Test name
Test status
Simulation time 1354666771 ps
CPU time 7.31 seconds
Started Apr 25 12:33:18 PM PDT 24
Finished Apr 25 12:33:27 PM PDT 24
Peak memory 218612 kb
Host smart-2e3f9e4e-94bd-471a-ae02-b9c4cf75cfa9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1007658404 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 4.rom_ctrl_csr_mem_rw_with_rand_reset.1007658404
Directory /workspace/4.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_rw.2690314342
Short name T420
Test name
Test status
Simulation time 174962602 ps
CPU time 4.27 seconds
Started Apr 25 12:33:20 PM PDT 24
Finished Apr 25 12:33:25 PM PDT 24
Peak memory 210380 kb
Host smart-6e1c7648-ec1f-40de-8725-b9606f37a896
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2690314342 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_rw.2690314342
Directory /workspace/4.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_partial_access.2171339437
Short name T383
Test name
Test status
Simulation time 894417438 ps
CPU time 9.15 seconds
Started Apr 25 12:33:17 PM PDT 24
Finished Apr 25 12:33:27 PM PDT 24
Peak memory 210164 kb
Host smart-dfe7e9cc-e1d7-43a2-9f8b-2773d0a54bd8
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2171339437 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctr
l_mem_partial_access.2171339437
Directory /workspace/4.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_walk.1659452125
Short name T422
Test name
Test status
Simulation time 1732689235 ps
CPU time 14.33 seconds
Started Apr 25 12:33:16 PM PDT 24
Finished Apr 25 12:33:31 PM PDT 24
Peak memory 210324 kb
Host smart-7c241e8c-a13e-488b-96fc-0bba5827eb9e
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1659452125 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_mem_walk
.1659452125
Directory /workspace/4.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_passthru_mem_tl_intg_err.1331056472
Short name T443
Test name
Test status
Simulation time 50375212538 ps
CPU time 96.51 seconds
Started Apr 25 12:33:11 PM PDT 24
Finished Apr 25 12:34:50 PM PDT 24
Peak memory 210552 kb
Host smart-973709de-7565-4344-b23a-60a7719f177b
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1331056472 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_pa
ssthru_mem_tl_intg_err.1331056472
Directory /workspace/4.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_same_csr_outstanding.942252291
Short name T87
Test name
Test status
Simulation time 1857010097 ps
CPU time 11.6 seconds
Started Apr 25 12:33:16 PM PDT 24
Finished Apr 25 12:33:28 PM PDT 24
Peak memory 210368 kb
Host smart-4f2ffb78-9cc2-4c76-bfdc-df41cd998b94
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=942252291 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ct
rl_same_csr_outstanding.942252291
Directory /workspace/4.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_errors.1505105783
Short name T454
Test name
Test status
Simulation time 6501814455 ps
CPU time 17.08 seconds
Started Apr 25 12:33:09 PM PDT 24
Finished Apr 25 12:33:28 PM PDT 24
Peak memory 218760 kb
Host smart-e756fdf4-e87e-4c13-b7cf-26c92cd2384c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1505105783 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_tl_errors.1505105783
Directory /workspace/4.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_intg_err.1975362267
Short name T455
Test name
Test status
Simulation time 4200220220 ps
CPU time 74.39 seconds
Started Apr 25 12:33:11 PM PDT 24
Finished Apr 25 12:34:27 PM PDT 24
Peak memory 210424 kb
Host smart-93d71146-295c-47a5-b048-824d4edd5a96
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1975362267 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_tl_in
tg_err.1975362267
Directory /workspace/4.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_mem_rw_with_rand_reset.1828423923
Short name T387
Test name
Test status
Simulation time 3620626293 ps
CPU time 14.81 seconds
Started Apr 25 12:33:21 PM PDT 24
Finished Apr 25 12:33:37 PM PDT 24
Peak memory 218776 kb
Host smart-70f083a2-848e-4fc5-97cd-3ab09009e87b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1828423923 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 5.rom_ctrl_csr_mem_rw_with_rand_reset.1828423923
Directory /workspace/5.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_rw.3334339723
Short name T414
Test name
Test status
Simulation time 8003104241 ps
CPU time 14.52 seconds
Started Apr 25 12:33:19 PM PDT 24
Finished Apr 25 12:33:35 PM PDT 24
Peak memory 210540 kb
Host smart-e05a595b-8f14-4fe0-a862-c40c821bfb52
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3334339723 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_csr_rw.3334339723
Directory /workspace/5.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_passthru_mem_tl_intg_err.3790392877
Short name T76
Test name
Test status
Simulation time 23962205236 ps
CPU time 52.9 seconds
Started Apr 25 12:33:20 PM PDT 24
Finished Apr 25 12:34:15 PM PDT 24
Peak memory 210568 kb
Host smart-9ddcb0f6-6b78-4cf4-a61f-07959b19c79b
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3790392877 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_pa
ssthru_mem_tl_intg_err.3790392877
Directory /workspace/5.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_same_csr_outstanding.4046545426
Short name T85
Test name
Test status
Simulation time 16558739860 ps
CPU time 9.64 seconds
Started Apr 25 12:33:19 PM PDT 24
Finished Apr 25 12:33:31 PM PDT 24
Peak memory 210524 kb
Host smart-8f47082e-986e-42e0-9b09-88802dab902d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4046545426 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_c
trl_same_csr_outstanding.4046545426
Directory /workspace/5.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_errors.3533739141
Short name T438
Test name
Test status
Simulation time 1544744276 ps
CPU time 11.29 seconds
Started Apr 25 12:33:15 PM PDT 24
Finished Apr 25 12:33:27 PM PDT 24
Peak memory 218656 kb
Host smart-8c6a05ea-3d99-46d3-95e3-81ea9827f04b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3533739141 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_tl_errors.3533739141
Directory /workspace/5.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_intg_err.3477959113
Short name T100
Test name
Test status
Simulation time 31787383223 ps
CPU time 47.73 seconds
Started Apr 25 12:33:15 PM PDT 24
Finished Apr 25 12:34:04 PM PDT 24
Peak memory 211620 kb
Host smart-77df88cb-52d8-4b9b-94a1-2aadfe70733a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3477959113 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_tl_in
tg_err.3477959113
Directory /workspace/5.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_mem_rw_with_rand_reset.2669952831
Short name T385
Test name
Test status
Simulation time 2837572882 ps
CPU time 9.25 seconds
Started Apr 25 12:33:18 PM PDT 24
Finished Apr 25 12:33:29 PM PDT 24
Peak memory 218716 kb
Host smart-b2b34730-35c1-4b77-b9d1-9cb1911ba62a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2669952831 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 6.rom_ctrl_csr_mem_rw_with_rand_reset.2669952831
Directory /workspace/6.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_rw.2135872016
Short name T73
Test name
Test status
Simulation time 9783785403 ps
CPU time 13.65 seconds
Started Apr 25 12:33:19 PM PDT 24
Finished Apr 25 12:33:35 PM PDT 24
Peak memory 210500 kb
Host smart-f9c1cfc1-a480-491a-9eb4-c8370967e6f7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2135872016 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_csr_rw.2135872016
Directory /workspace/6.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_passthru_mem_tl_intg_err.2447018161
Short name T373
Test name
Test status
Simulation time 6198323819 ps
CPU time 51.38 seconds
Started Apr 25 12:33:55 PM PDT 24
Finished Apr 25 12:34:48 PM PDT 24
Peak memory 210540 kb
Host smart-8a223ace-e219-42f5-ad21-da375e8da393
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2447018161 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_pa
ssthru_mem_tl_intg_err.2447018161
Directory /workspace/6.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_same_csr_outstanding.3933728976
Short name T82
Test name
Test status
Simulation time 1655535368 ps
CPU time 4.36 seconds
Started Apr 25 12:33:21 PM PDT 24
Finished Apr 25 12:33:27 PM PDT 24
Peak memory 210392 kb
Host smart-804a3e1c-e598-402b-b0c2-8a4b6906ce6f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3933728976 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_c
trl_same_csr_outstanding.3933728976
Directory /workspace/6.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_errors.2302188745
Short name T459
Test name
Test status
Simulation time 9654235126 ps
CPU time 20.71 seconds
Started Apr 25 12:33:17 PM PDT 24
Finished Apr 25 12:33:38 PM PDT 24
Peak memory 216312 kb
Host smart-f7da540e-63ae-45dd-98ef-01298b8b2dca
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2302188745 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_tl_errors.2302188745
Directory /workspace/6.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_mem_rw_with_rand_reset.758404501
Short name T377
Test name
Test status
Simulation time 3303782214 ps
CPU time 14.66 seconds
Started Apr 25 12:33:21 PM PDT 24
Finished Apr 25 12:33:37 PM PDT 24
Peak memory 218640 kb
Host smart-b0e69a16-2348-4367-ba67-f55444b4459e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=758404501 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 7.rom_ctrl_csr_mem_rw_with_rand_reset.758404501
Directory /workspace/7.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_rw.1763034256
Short name T450
Test name
Test status
Simulation time 194768487 ps
CPU time 4.22 seconds
Started Apr 25 12:33:34 PM PDT 24
Finished Apr 25 12:33:42 PM PDT 24
Peak memory 210344 kb
Host smart-d164bde8-db2c-414e-b7d0-120ea6dd6d01
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1763034256 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_csr_rw.1763034256
Directory /workspace/7.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_passthru_mem_tl_intg_err.547141892
Short name T77
Test name
Test status
Simulation time 8934490804 ps
CPU time 28.1 seconds
Started Apr 25 12:33:17 PM PDT 24
Finished Apr 25 12:33:46 PM PDT 24
Peak memory 210540 kb
Host smart-1725ff72-bdaf-4799-8e67-6527d2681d82
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=547141892 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_pas
sthru_mem_tl_intg_err.547141892
Directory /workspace/7.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_same_csr_outstanding.862090443
Short name T421
Test name
Test status
Simulation time 7464020847 ps
CPU time 15.02 seconds
Started Apr 25 12:33:18 PM PDT 24
Finished Apr 25 12:33:35 PM PDT 24
Peak memory 210500 kb
Host smart-f940d3f4-4be3-4120-a51e-3c58adf07009
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=862090443 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ct
rl_same_csr_outstanding.862090443
Directory /workspace/7.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_errors.2072152592
Short name T406
Test name
Test status
Simulation time 1864045390 ps
CPU time 17.2 seconds
Started Apr 25 12:33:22 PM PDT 24
Finished Apr 25 12:33:41 PM PDT 24
Peak memory 218584 kb
Host smart-6ade3525-59b9-4302-8f68-cb68075bf2cd
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2072152592 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_tl_errors.2072152592
Directory /workspace/7.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_mem_rw_with_rand_reset.2854530972
Short name T428
Test name
Test status
Simulation time 1903225568 ps
CPU time 15.13 seconds
Started Apr 25 12:33:19 PM PDT 24
Finished Apr 25 12:33:36 PM PDT 24
Peak memory 218608 kb
Host smart-b964b8e0-7694-4280-930f-2d8648df3268
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2854530972 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 8.rom_ctrl_csr_mem_rw_with_rand_reset.2854530972
Directory /workspace/8.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_rw.336985039
Short name T447
Test name
Test status
Simulation time 2011665163 ps
CPU time 15.38 seconds
Started Apr 25 12:33:14 PM PDT 24
Finished Apr 25 12:33:31 PM PDT 24
Peak memory 210384 kb
Host smart-e0c7d0b3-f37a-4259-ae6c-941277a3843c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=336985039 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_csr_rw.336985039
Directory /workspace/8.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_passthru_mem_tl_intg_err.1163994556
Short name T415
Test name
Test status
Simulation time 2771185556 ps
CPU time 35.75 seconds
Started Apr 25 12:33:18 PM PDT 24
Finished Apr 25 12:33:56 PM PDT 24
Peak memory 210480 kb
Host smart-8af1ace9-15fa-4dab-8e78-6fe445c35657
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1163994556 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_pa
ssthru_mem_tl_intg_err.1163994556
Directory /workspace/8.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_same_csr_outstanding.3289452495
Short name T79
Test name
Test status
Simulation time 4050758027 ps
CPU time 15.55 seconds
Started Apr 25 12:33:19 PM PDT 24
Finished Apr 25 12:33:36 PM PDT 24
Peak memory 210488 kb
Host smart-5e47e5f3-9c2b-4682-aa5e-07264f592e3d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3289452495 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_c
trl_same_csr_outstanding.3289452495
Directory /workspace/8.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_errors.3662860062
Short name T432
Test name
Test status
Simulation time 2100798788 ps
CPU time 9.35 seconds
Started Apr 25 12:33:16 PM PDT 24
Finished Apr 25 12:33:26 PM PDT 24
Peak memory 218708 kb
Host smart-dd4bed9c-69d5-4da4-bcea-8b3c97663637
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3662860062 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_tl_errors.3662860062
Directory /workspace/8.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_intg_err.3367736290
Short name T99
Test name
Test status
Simulation time 5074411662 ps
CPU time 41.06 seconds
Started Apr 25 12:33:16 PM PDT 24
Finished Apr 25 12:33:58 PM PDT 24
Peak memory 218620 kb
Host smart-31a209d9-92f8-495a-bfa5-e358351240d9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3367736290 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_tl_in
tg_err.3367736290
Directory /workspace/8.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_mem_rw_with_rand_reset.1544206953
Short name T393
Test name
Test status
Simulation time 934702761 ps
CPU time 7.66 seconds
Started Apr 25 12:33:21 PM PDT 24
Finished Apr 25 12:33:30 PM PDT 24
Peak memory 218624 kb
Host smart-df31a55a-7b8f-479c-9ce3-68f3fc0ffd49
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1544206953 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 9.rom_ctrl_csr_mem_rw_with_rand_reset.1544206953
Directory /workspace/9.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_rw.1950742682
Short name T458
Test name
Test status
Simulation time 178786318 ps
CPU time 4.04 seconds
Started Apr 25 12:33:14 PM PDT 24
Finished Apr 25 12:33:19 PM PDT 24
Peak memory 210316 kb
Host smart-ba2e25ca-ce6f-4ef7-b80d-33d98dc08e93
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1950742682 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_csr_rw.1950742682
Directory /workspace/9.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_passthru_mem_tl_intg_err.1645067943
Short name T423
Test name
Test status
Simulation time 7174358476 ps
CPU time 68.16 seconds
Started Apr 25 12:33:54 PM PDT 24
Finished Apr 25 12:35:03 PM PDT 24
Peak memory 210532 kb
Host smart-fc027e70-6fba-43f8-8515-aaa0477206de
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1645067943 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_pa
ssthru_mem_tl_intg_err.1645067943
Directory /workspace/9.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_same_csr_outstanding.2697223324
Short name T409
Test name
Test status
Simulation time 2335972173 ps
CPU time 9.61 seconds
Started Apr 25 12:33:21 PM PDT 24
Finished Apr 25 12:33:32 PM PDT 24
Peak memory 210368 kb
Host smart-dfac458c-35d2-45c3-9cb9-8c6075d2ff4f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2697223324 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_c
trl_same_csr_outstanding.2697223324
Directory /workspace/9.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_errors.1970810613
Short name T444
Test name
Test status
Simulation time 1513509948 ps
CPU time 14.01 seconds
Started Apr 25 12:33:18 PM PDT 24
Finished Apr 25 12:33:34 PM PDT 24
Peak memory 218652 kb
Host smart-72d161c6-97a3-4c3f-a816-6f9c252f519d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1970810613 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_tl_errors.1970810613
Directory /workspace/9.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_intg_err.2383450554
Short name T396
Test name
Test status
Simulation time 2664120233 ps
CPU time 39.43 seconds
Started Apr 25 12:33:19 PM PDT 24
Finished Apr 25 12:34:00 PM PDT 24
Peak memory 212208 kb
Host smart-a3198c1c-4ca4-4d08-9f1c-f87a7814b1a3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2383450554 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_tl_in
tg_err.2383450554
Directory /workspace/9.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/0.rom_ctrl_alert_test.1408609691
Short name T5
Test name
Test status
Simulation time 6166738761 ps
CPU time 12.63 seconds
Started Apr 25 12:36:56 PM PDT 24
Finished Apr 25 12:37:09 PM PDT 24
Peak memory 211436 kb
Host smart-e21e1b8f-5d50-4b5e-a498-82e0c07fafcc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1408609691 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_alert_test.1408609691
Directory /workspace/0.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/0.rom_ctrl_corrupt_sig_fatal_chk.2127106069
Short name T277
Test name
Test status
Simulation time 17790394936 ps
CPU time 173.77 seconds
Started Apr 25 12:36:48 PM PDT 24
Finished Apr 25 12:39:43 PM PDT 24
Peak memory 231252 kb
Host smart-77bf0a14-eafd-44b6-a58d-192a12fafe5b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2127106069 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_c
orrupt_sig_fatal_chk.2127106069
Directory /workspace/0.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/0.rom_ctrl_kmac_err_chk.4115333270
Short name T264
Test name
Test status
Simulation time 54077261650 ps
CPU time 25.45 seconds
Started Apr 25 12:36:50 PM PDT 24
Finished Apr 25 12:37:17 PM PDT 24
Peak memory 212372 kb
Host smart-8bf98faf-39ef-4de7-beb7-86b563729776
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4115333270 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_kmac_err_chk.4115333270
Directory /workspace/0.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/0.rom_ctrl_max_throughput_chk.2104386616
Short name T116
Test name
Test status
Simulation time 1159647031 ps
CPU time 6.81 seconds
Started Apr 25 12:36:58 PM PDT 24
Finished Apr 25 12:37:07 PM PDT 24
Peak memory 211340 kb
Host smart-b9335840-4404-49cf-8e56-1ffcab61ca15
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2104386616 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_max_throughput_chk.2104386616
Directory /workspace/0.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/0.rom_ctrl_sec_cm.2805471904
Short name T36
Test name
Test status
Simulation time 4031922552 ps
CPU time 63.46 seconds
Started Apr 25 12:36:57 PM PDT 24
Finished Apr 25 12:38:02 PM PDT 24
Peak memory 236456 kb
Host smart-cb5ea9a5-9118-4899-a157-5bf4a2bcb340
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2805471904 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_sec_cm.2805471904
Directory /workspace/0.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/0.rom_ctrl_smoke.3178293600
Short name T280
Test name
Test status
Simulation time 2225701544 ps
CPU time 23.14 seconds
Started Apr 25 12:36:51 PM PDT 24
Finished Apr 25 12:37:16 PM PDT 24
Peak memory 213540 kb
Host smart-543d45bb-d946-4c22-84ec-98962011e6b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3178293600 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_smoke.3178293600
Directory /workspace/0.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/0.rom_ctrl_stress_all.4077445315
Short name T167
Test name
Test status
Simulation time 1611441625 ps
CPU time 20.5 seconds
Started Apr 25 12:36:50 PM PDT 24
Finished Apr 25 12:37:12 PM PDT 24
Peak memory 215268 kb
Host smart-fa5a0ede-0a74-41c0-a87d-4ffcb93be365
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4077445315 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 0.rom_ctrl_stress_all.4077445315
Directory /workspace/0.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/0.rom_ctrl_stress_all_with_rand_reset.1403124458
Short name T29
Test name
Test status
Simulation time 110851354065 ps
CPU time 2343.88 seconds
Started Apr 25 12:36:45 PM PDT 24
Finished Apr 25 01:15:51 PM PDT 24
Peak memory 252420 kb
Host smart-b008f80d-722e-4f39-a1ad-919bd3e56d5a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1403124458 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_stress_all_with_rand_reset.1403124458
Directory /workspace/0.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.rom_ctrl_alert_test.1750630326
Short name T156
Test name
Test status
Simulation time 1131728434 ps
CPU time 11.27 seconds
Started Apr 25 12:36:53 PM PDT 24
Finished Apr 25 12:37:05 PM PDT 24
Peak memory 211400 kb
Host smart-b00a596c-fa12-4125-bdc8-dc268db5d294
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1750630326 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_alert_test.1750630326
Directory /workspace/1.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/1.rom_ctrl_corrupt_sig_fatal_chk.2481685480
Short name T226
Test name
Test status
Simulation time 14540923188 ps
CPU time 141.79 seconds
Started Apr 25 12:36:35 PM PDT 24
Finished Apr 25 12:38:57 PM PDT 24
Peak memory 237384 kb
Host smart-ebaec24c-fc71-4476-9ce5-2266f0ad707d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2481685480 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_c
orrupt_sig_fatal_chk.2481685480
Directory /workspace/1.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/1.rom_ctrl_kmac_err_chk.2997951297
Short name T193
Test name
Test status
Simulation time 1974681475 ps
CPU time 21.84 seconds
Started Apr 25 12:36:51 PM PDT 24
Finished Apr 25 12:37:14 PM PDT 24
Peak memory 212128 kb
Host smart-6f22906f-8609-477a-b176-1c6d78fbe36c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2997951297 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_kmac_err_chk.2997951297
Directory /workspace/1.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/1.rom_ctrl_max_throughput_chk.517445206
Short name T222
Test name
Test status
Simulation time 258569963 ps
CPU time 7.17 seconds
Started Apr 25 12:36:52 PM PDT 24
Finished Apr 25 12:37:00 PM PDT 24
Peak memory 211288 kb
Host smart-815d7b1e-b994-457c-8f17-987cbb2a6360
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=517445206 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_max_throughput_chk.517445206
Directory /workspace/1.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/1.rom_ctrl_sec_cm.3948687493
Short name T32
Test name
Test status
Simulation time 1480758594 ps
CPU time 57.87 seconds
Started Apr 25 12:36:45 PM PDT 24
Finished Apr 25 12:37:45 PM PDT 24
Peak memory 233444 kb
Host smart-6b3efa3a-13a9-4feb-913c-9be4d812d415
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3948687493 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_sec_cm.3948687493
Directory /workspace/1.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/1.rom_ctrl_smoke.842943223
Short name T127
Test name
Test status
Simulation time 10570727578 ps
CPU time 32.79 seconds
Started Apr 25 12:36:44 PM PDT 24
Finished Apr 25 12:37:18 PM PDT 24
Peak memory 213688 kb
Host smart-5e2a813a-0e70-4ac9-9167-01b709db089e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=842943223 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_smoke.842943223
Directory /workspace/1.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/1.rom_ctrl_stress_all.2733781588
Short name T107
Test name
Test status
Simulation time 35572760368 ps
CPU time 58.57 seconds
Started Apr 25 12:36:52 PM PDT 24
Finished Apr 25 12:37:52 PM PDT 24
Peak memory 219656 kb
Host smart-d73ce627-0057-4842-851d-e7c5e8c2c311
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2733781588 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 1.rom_ctrl_stress_all.2733781588
Directory /workspace/1.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/10.rom_ctrl_alert_test.2160098871
Short name T151
Test name
Test status
Simulation time 1131881816 ps
CPU time 10.61 seconds
Started Apr 25 12:36:57 PM PDT 24
Finished Apr 25 12:37:10 PM PDT 24
Peak memory 211372 kb
Host smart-fd10d60c-8c8f-4d15-8f79-b090006d00a6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2160098871 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_alert_test.2160098871
Directory /workspace/10.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/10.rom_ctrl_corrupt_sig_fatal_chk.2564155725
Short name T171
Test name
Test status
Simulation time 1944127131 ps
CPU time 105.27 seconds
Started Apr 25 12:37:07 PM PDT 24
Finished Apr 25 12:38:56 PM PDT 24
Peak memory 228316 kb
Host smart-a2d7f84c-46e0-4382-955a-475bde4ee16d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2564155725 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_
corrupt_sig_fatal_chk.2564155725
Directory /workspace/10.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/10.rom_ctrl_kmac_err_chk.2765127965
Short name T323
Test name
Test status
Simulation time 1369424622 ps
CPU time 18.05 seconds
Started Apr 25 12:37:08 PM PDT 24
Finished Apr 25 12:37:29 PM PDT 24
Peak memory 211424 kb
Host smart-56957490-47c2-422b-8303-14d899c841cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2765127965 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_kmac_err_chk.2765127965
Directory /workspace/10.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/10.rom_ctrl_max_throughput_chk.3569026661
Short name T335
Test name
Test status
Simulation time 1082352011 ps
CPU time 7.18 seconds
Started Apr 25 12:36:59 PM PDT 24
Finished Apr 25 12:37:08 PM PDT 24
Peak memory 211312 kb
Host smart-4156af51-3978-43e1-8647-479cd0f45d8d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3569026661 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_max_throughput_chk.3569026661
Directory /workspace/10.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/10.rom_ctrl_smoke.3408618229
Short name T159
Test name
Test status
Simulation time 1578811972 ps
CPU time 15.08 seconds
Started Apr 25 12:36:59 PM PDT 24
Finished Apr 25 12:37:16 PM PDT 24
Peak memory 213208 kb
Host smart-6b7ae50b-56fd-45d6-938b-2a407c8654f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3408618229 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_smoke.3408618229
Directory /workspace/10.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/10.rom_ctrl_stress_all.2354291442
Short name T272
Test name
Test status
Simulation time 13076158986 ps
CPU time 58.04 seconds
Started Apr 25 12:37:03 PM PDT 24
Finished Apr 25 12:38:03 PM PDT 24
Peak memory 219552 kb
Host smart-37943150-d57b-45d0-ab04-64e3d1cf951e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2354291442 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 10.rom_ctrl_stress_all.2354291442
Directory /workspace/10.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/11.rom_ctrl_alert_test.4203894301
Short name T286
Test name
Test status
Simulation time 320389539 ps
CPU time 4.27 seconds
Started Apr 25 12:36:56 PM PDT 24
Finished Apr 25 12:37:02 PM PDT 24
Peak memory 211300 kb
Host smart-e9f24dbb-1143-4518-b98a-b6cbc6dd1046
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4203894301 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_alert_test.4203894301
Directory /workspace/11.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/11.rom_ctrl_corrupt_sig_fatal_chk.2648060864
Short name T26
Test name
Test status
Simulation time 8161598904 ps
CPU time 121.78 seconds
Started Apr 25 12:37:03 PM PDT 24
Finished Apr 25 12:39:07 PM PDT 24
Peak memory 212204 kb
Host smart-45b941ec-1d44-40f7-9900-b6a37de527d2
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2648060864 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_
corrupt_sig_fatal_chk.2648060864
Directory /workspace/11.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/11.rom_ctrl_max_throughput_chk.2446299723
Short name T302
Test name
Test status
Simulation time 7627627558 ps
CPU time 15.95 seconds
Started Apr 25 12:37:02 PM PDT 24
Finished Apr 25 12:37:20 PM PDT 24
Peak memory 211376 kb
Host smart-2ab61cd1-7947-4e65-ac37-c32ef8617a50
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2446299723 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_max_throughput_chk.2446299723
Directory /workspace/11.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/11.rom_ctrl_smoke.1797228508
Short name T250
Test name
Test status
Simulation time 3056112753 ps
CPU time 28.28 seconds
Started Apr 25 12:36:57 PM PDT 24
Finished Apr 25 12:37:28 PM PDT 24
Peak memory 213184 kb
Host smart-d66ac14d-6c58-421a-9105-c6343975464d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1797228508 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_smoke.1797228508
Directory /workspace/11.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/11.rom_ctrl_stress_all.1148069702
Short name T148
Test name
Test status
Simulation time 3659756001 ps
CPU time 40.31 seconds
Started Apr 25 12:37:06 PM PDT 24
Finished Apr 25 12:37:48 PM PDT 24
Peak memory 219556 kb
Host smart-632d0ad5-916a-4c69-941c-2b86da9fcf92
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1148069702 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 11.rom_ctrl_stress_all.1148069702
Directory /workspace/11.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/12.rom_ctrl_alert_test.99120189
Short name T152
Test name
Test status
Simulation time 5016739268 ps
CPU time 8.72 seconds
Started Apr 25 12:37:05 PM PDT 24
Finished Apr 25 12:37:15 PM PDT 24
Peak memory 211448 kb
Host smart-61893b9c-abf5-4f29-86be-f8aab6b703cc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99120189 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_alert_test.99120189
Directory /workspace/12.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/12.rom_ctrl_corrupt_sig_fatal_chk.2540987915
Short name T21
Test name
Test status
Simulation time 30875444738 ps
CPU time 301.74 seconds
Started Apr 25 12:37:09 PM PDT 24
Finished Apr 25 12:42:13 PM PDT 24
Peak memory 218712 kb
Host smart-19a329b1-83d5-4c7c-9a7d-0f5faff063fd
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2540987915 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_
corrupt_sig_fatal_chk.2540987915
Directory /workspace/12.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/12.rom_ctrl_kmac_err_chk.2629898316
Short name T287
Test name
Test status
Simulation time 9362936816 ps
CPU time 24.22 seconds
Started Apr 25 12:37:08 PM PDT 24
Finished Apr 25 12:37:35 PM PDT 24
Peak memory 212396 kb
Host smart-26c98c74-c76e-42e4-ab45-0d1df9f53582
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2629898316 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_kmac_err_chk.2629898316
Directory /workspace/12.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/12.rom_ctrl_max_throughput_chk.3721788952
Short name T303
Test name
Test status
Simulation time 1069197922 ps
CPU time 7.36 seconds
Started Apr 25 12:37:12 PM PDT 24
Finished Apr 25 12:37:23 PM PDT 24
Peak memory 211304 kb
Host smart-17644d51-52cc-4950-9faa-1903bd96a3bb
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3721788952 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_max_throughput_chk.3721788952
Directory /workspace/12.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/12.rom_ctrl_smoke.1058314869
Short name T328
Test name
Test status
Simulation time 1331769323 ps
CPU time 18.35 seconds
Started Apr 25 12:36:58 PM PDT 24
Finished Apr 25 12:37:18 PM PDT 24
Peak memory 219536 kb
Host smart-afcab414-c6c9-43b8-a8c1-87bdb2a9f5ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1058314869 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_smoke.1058314869
Directory /workspace/12.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/12.rom_ctrl_stress_all.4121610669
Short name T9
Test name
Test status
Simulation time 2173741175 ps
CPU time 15.99 seconds
Started Apr 25 12:37:00 PM PDT 24
Finished Apr 25 12:37:17 PM PDT 24
Peak memory 211292 kb
Host smart-91558cf0-604a-452c-abfa-75db15b6073c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4121610669 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 12.rom_ctrl_stress_all.4121610669
Directory /workspace/12.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/13.rom_ctrl_alert_test.4128098186
Short name T362
Test name
Test status
Simulation time 2550897326 ps
CPU time 9.63 seconds
Started Apr 25 12:36:55 PM PDT 24
Finished Apr 25 12:37:06 PM PDT 24
Peak memory 211460 kb
Host smart-e216fcec-a991-4123-9f30-c9dac6030ad9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4128098186 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_alert_test.4128098186
Directory /workspace/13.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/13.rom_ctrl_corrupt_sig_fatal_chk.422034378
Short name T145
Test name
Test status
Simulation time 1684785831 ps
CPU time 109.04 seconds
Started Apr 25 12:37:08 PM PDT 24
Finished Apr 25 12:39:00 PM PDT 24
Peak memory 229820 kb
Host smart-6d36e841-1146-4009-b116-78096f33bdb9
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=422034378 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_c
orrupt_sig_fatal_chk.422034378
Directory /workspace/13.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/13.rom_ctrl_kmac_err_chk.3534603459
Short name T321
Test name
Test status
Simulation time 11385698899 ps
CPU time 26.94 seconds
Started Apr 25 12:37:09 PM PDT 24
Finished Apr 25 12:37:39 PM PDT 24
Peak memory 212228 kb
Host smart-dfd8107e-3551-4264-97f9-074c22c00f21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3534603459 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_kmac_err_chk.3534603459
Directory /workspace/13.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/13.rom_ctrl_max_throughput_chk.3938903042
Short name T2
Test name
Test status
Simulation time 429445600 ps
CPU time 5.95 seconds
Started Apr 25 12:37:08 PM PDT 24
Finished Apr 25 12:37:17 PM PDT 24
Peak memory 211276 kb
Host smart-3cdc5661-5452-47b6-8171-094cba303532
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3938903042 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_max_throughput_chk.3938903042
Directory /workspace/13.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/13.rom_ctrl_smoke.3871052857
Short name T135
Test name
Test status
Simulation time 599720052 ps
CPU time 10.05 seconds
Started Apr 25 12:37:08 PM PDT 24
Finished Apr 25 12:37:21 PM PDT 24
Peak memory 212032 kb
Host smart-08e83e21-e549-478c-9ad1-4e3b416e7564
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3871052857 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_smoke.3871052857
Directory /workspace/13.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/13.rom_ctrl_stress_all.2036798615
Short name T284
Test name
Test status
Simulation time 3510449314 ps
CPU time 19.22 seconds
Started Apr 25 12:37:08 PM PDT 24
Finished Apr 25 12:37:30 PM PDT 24
Peak memory 215584 kb
Host smart-1504dff1-3db9-4110-b615-27f25d472ad8
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2036798615 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 13.rom_ctrl_stress_all.2036798615
Directory /workspace/13.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/13.rom_ctrl_stress_all_with_rand_reset.4282615312
Short name T41
Test name
Test status
Simulation time 27765875795 ps
CPU time 3373.36 seconds
Started Apr 25 12:37:09 PM PDT 24
Finished Apr 25 01:33:26 PM PDT 24
Peak memory 235856 kb
Host smart-7171f046-ee60-408f-89ab-208bcee92954
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4282615312 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_stress_all_with_rand_reset.4282615312
Directory /workspace/13.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/14.rom_ctrl_alert_test.1811112989
Short name T288
Test name
Test status
Simulation time 1266061606 ps
CPU time 11.86 seconds
Started Apr 25 12:37:14 PM PDT 24
Finished Apr 25 12:37:29 PM PDT 24
Peak memory 211336 kb
Host smart-84456c34-5b82-4295-aa1d-b3e399363201
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1811112989 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_alert_test.1811112989
Directory /workspace/14.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/14.rom_ctrl_corrupt_sig_fatal_chk.4049561801
Short name T289
Test name
Test status
Simulation time 6387226662 ps
CPU time 91.83 seconds
Started Apr 25 12:37:02 PM PDT 24
Finished Apr 25 12:38:35 PM PDT 24
Peak memory 237012 kb
Host smart-7b536518-f519-4a53-b46f-a456bbff98f6
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4049561801 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_
corrupt_sig_fatal_chk.4049561801
Directory /workspace/14.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/14.rom_ctrl_kmac_err_chk.2189553761
Short name T18
Test name
Test status
Simulation time 663950319 ps
CPU time 9.37 seconds
Started Apr 25 12:37:00 PM PDT 24
Finished Apr 25 12:37:10 PM PDT 24
Peak memory 211888 kb
Host smart-d77210be-a6ea-4836-b8d1-9c740946aa67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2189553761 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_kmac_err_chk.2189553761
Directory /workspace/14.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/14.rom_ctrl_max_throughput_chk.3816716663
Short name T338
Test name
Test status
Simulation time 861231543 ps
CPU time 10.49 seconds
Started Apr 25 12:37:09 PM PDT 24
Finished Apr 25 12:37:22 PM PDT 24
Peak memory 211304 kb
Host smart-e9f80f9e-07b0-4ab0-9322-96799cb4bbbe
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3816716663 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_max_throughput_chk.3816716663
Directory /workspace/14.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/14.rom_ctrl_smoke.1205902738
Short name T64
Test name
Test status
Simulation time 4209542992 ps
CPU time 38.14 seconds
Started Apr 25 12:36:56 PM PDT 24
Finished Apr 25 12:37:36 PM PDT 24
Peak memory 212820 kb
Host smart-4604dd8c-3ffb-4f72-907e-a65379bdcc00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1205902738 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_smoke.1205902738
Directory /workspace/14.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/14.rom_ctrl_stress_all.4262012548
Short name T200
Test name
Test status
Simulation time 2060117308 ps
CPU time 9.48 seconds
Started Apr 25 12:37:10 PM PDT 24
Finished Apr 25 12:37:22 PM PDT 24
Peak memory 211360 kb
Host smart-ad2c2e69-e577-4c85-865b-b79a9240afbc
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4262012548 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 14.rom_ctrl_stress_all.4262012548
Directory /workspace/14.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/15.rom_ctrl_alert_test.3075365517
Short name T351
Test name
Test status
Simulation time 2418743547 ps
CPU time 9.08 seconds
Started Apr 25 12:37:01 PM PDT 24
Finished Apr 25 12:37:12 PM PDT 24
Peak memory 211456 kb
Host smart-d672d72b-e8ef-4851-8202-eec8a2ffebfb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3075365517 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_alert_test.3075365517
Directory /workspace/15.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/15.rom_ctrl_corrupt_sig_fatal_chk.1530381951
Short name T112
Test name
Test status
Simulation time 4633528598 ps
CPU time 78.56 seconds
Started Apr 25 12:37:08 PM PDT 24
Finished Apr 25 12:38:30 PM PDT 24
Peak memory 232860 kb
Host smart-debd2ec4-5314-42fc-9e0c-d84b468efde7
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1530381951 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_
corrupt_sig_fatal_chk.1530381951
Directory /workspace/15.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/15.rom_ctrl_kmac_err_chk.4211706433
Short name T149
Test name
Test status
Simulation time 347747594 ps
CPU time 9.16 seconds
Started Apr 25 12:37:05 PM PDT 24
Finished Apr 25 12:37:16 PM PDT 24
Peak memory 212112 kb
Host smart-fb4bc6c7-2160-4d7a-977f-4ccc75c37d0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4211706433 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_kmac_err_chk.4211706433
Directory /workspace/15.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/15.rom_ctrl_max_throughput_chk.2259759026
Short name T13
Test name
Test status
Simulation time 359488980 ps
CPU time 5.7 seconds
Started Apr 25 12:37:08 PM PDT 24
Finished Apr 25 12:37:17 PM PDT 24
Peak memory 211268 kb
Host smart-af5e63eb-2e03-4f90-8332-a6e6f7a7de66
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2259759026 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_max_throughput_chk.2259759026
Directory /workspace/15.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/15.rom_ctrl_smoke.3706100150
Short name T63
Test name
Test status
Simulation time 185620286 ps
CPU time 10.19 seconds
Started Apr 25 12:37:10 PM PDT 24
Finished Apr 25 12:37:23 PM PDT 24
Peak memory 219568 kb
Host smart-1257d3eb-0ccb-42dd-9766-e946a24925f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3706100150 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_smoke.3706100150
Directory /workspace/15.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/15.rom_ctrl_stress_all.3536951640
Short name T317
Test name
Test status
Simulation time 9212812165 ps
CPU time 35.13 seconds
Started Apr 25 12:37:08 PM PDT 24
Finished Apr 25 12:37:46 PM PDT 24
Peak memory 212132 kb
Host smart-5842c7d8-2dd9-49dd-b818-b3d9880879b0
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3536951640 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 15.rom_ctrl_stress_all.3536951640
Directory /workspace/15.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/16.rom_ctrl_alert_test.49388055
Short name T199
Test name
Test status
Simulation time 5417915156 ps
CPU time 12.67 seconds
Started Apr 25 12:37:16 PM PDT 24
Finished Apr 25 12:37:31 PM PDT 24
Peak memory 211396 kb
Host smart-7da85de2-a278-43d0-a2e1-b05bf6847476
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49388055 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_alert_test.49388055
Directory /workspace/16.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/16.rom_ctrl_corrupt_sig_fatal_chk.3689957924
Short name T37
Test name
Test status
Simulation time 1914294675 ps
CPU time 123.54 seconds
Started Apr 25 12:37:01 PM PDT 24
Finished Apr 25 12:39:06 PM PDT 24
Peak memory 237880 kb
Host smart-5e1e68a0-78aa-4fb5-a8f9-59389b0bff5d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3689957924 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_
corrupt_sig_fatal_chk.3689957924
Directory /workspace/16.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/16.rom_ctrl_kmac_err_chk.3281420996
Short name T364
Test name
Test status
Simulation time 2647041707 ps
CPU time 25.15 seconds
Started Apr 25 12:37:12 PM PDT 24
Finished Apr 25 12:37:40 PM PDT 24
Peak memory 212188 kb
Host smart-7adf6ab7-aae1-48c3-b284-6e08fdef452e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3281420996 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_kmac_err_chk.3281420996
Directory /workspace/16.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/16.rom_ctrl_max_throughput_chk.3141955764
Short name T334
Test name
Test status
Simulation time 616698465 ps
CPU time 5.58 seconds
Started Apr 25 12:37:02 PM PDT 24
Finished Apr 25 12:37:09 PM PDT 24
Peak memory 211316 kb
Host smart-06a88dcc-06ca-4122-907d-13355d187710
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3141955764 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_max_throughput_chk.3141955764
Directory /workspace/16.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/16.rom_ctrl_smoke.4127892083
Short name T241
Test name
Test status
Simulation time 1178508771 ps
CPU time 17.91 seconds
Started Apr 25 12:37:18 PM PDT 24
Finished Apr 25 12:37:39 PM PDT 24
Peak memory 219512 kb
Host smart-91a480dd-7097-4b80-b124-9b52e25944d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4127892083 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_smoke.4127892083
Directory /workspace/16.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/16.rom_ctrl_stress_all.3162032114
Short name T348
Test name
Test status
Simulation time 11040996947 ps
CPU time 54.94 seconds
Started Apr 25 12:37:04 PM PDT 24
Finished Apr 25 12:38:06 PM PDT 24
Peak memory 219512 kb
Host smart-f7b9af8c-8041-428a-8d5a-362becc4ecf8
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3162032114 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 16.rom_ctrl_stress_all.3162032114
Directory /workspace/16.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/17.rom_ctrl_alert_test.1758292508
Short name T155
Test name
Test status
Simulation time 4490648586 ps
CPU time 9.75 seconds
Started Apr 25 12:37:11 PM PDT 24
Finished Apr 25 12:37:24 PM PDT 24
Peak memory 211404 kb
Host smart-63cf1520-d76c-4b5d-a070-d0a539cd3ca3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1758292508 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_alert_test.1758292508
Directory /workspace/17.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/17.rom_ctrl_corrupt_sig_fatal_chk.1416606812
Short name T246
Test name
Test status
Simulation time 153702504279 ps
CPU time 298.37 seconds
Started Apr 25 12:37:04 PM PDT 24
Finished Apr 25 12:42:04 PM PDT 24
Peak memory 237304 kb
Host smart-78ea287d-8826-406f-9b63-ece01a3c796e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1416606812 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_
corrupt_sig_fatal_chk.1416606812
Directory /workspace/17.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/17.rom_ctrl_kmac_err_chk.1255438435
Short name T168
Test name
Test status
Simulation time 1568694845 ps
CPU time 18.69 seconds
Started Apr 25 12:37:12 PM PDT 24
Finished Apr 25 12:37:34 PM PDT 24
Peak memory 212060 kb
Host smart-177751c2-d651-4a87-bd07-3d4d20eac91d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1255438435 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_kmac_err_chk.1255438435
Directory /workspace/17.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/17.rom_ctrl_max_throughput_chk.1672809289
Short name T336
Test name
Test status
Simulation time 2627065882 ps
CPU time 9.14 seconds
Started Apr 25 12:37:18 PM PDT 24
Finished Apr 25 12:37:30 PM PDT 24
Peak memory 211380 kb
Host smart-6e6b635e-d7d7-48fd-a72e-ce5d202e6d09
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1672809289 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_max_throughput_chk.1672809289
Directory /workspace/17.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/17.rom_ctrl_smoke.2917686841
Short name T347
Test name
Test status
Simulation time 4205166568 ps
CPU time 34.68 seconds
Started Apr 25 12:37:12 PM PDT 24
Finished Apr 25 12:37:50 PM PDT 24
Peak memory 213268 kb
Host smart-0eb9f6d8-cea2-4ae9-b82a-84083509faad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2917686841 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_smoke.2917686841
Directory /workspace/17.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/17.rom_ctrl_stress_all.3320137440
Short name T240
Test name
Test status
Simulation time 4694975952 ps
CPU time 56.3 seconds
Started Apr 25 12:37:15 PM PDT 24
Finished Apr 25 12:38:14 PM PDT 24
Peak memory 216584 kb
Host smart-baf0ef42-935b-4de5-8190-d3120ed7830f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3320137440 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 17.rom_ctrl_stress_all.3320137440
Directory /workspace/17.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/18.rom_ctrl_alert_test.2231790852
Short name T49
Test name
Test status
Simulation time 168750233 ps
CPU time 4.23 seconds
Started Apr 25 12:37:05 PM PDT 24
Finished Apr 25 12:37:11 PM PDT 24
Peak memory 211400 kb
Host smart-0eb48b65-3d05-4a48-a52b-446cb827697a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2231790852 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_alert_test.2231790852
Directory /workspace/18.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/18.rom_ctrl_corrupt_sig_fatal_chk.474915616
Short name T230
Test name
Test status
Simulation time 26145012536 ps
CPU time 186.05 seconds
Started Apr 25 12:37:12 PM PDT 24
Finished Apr 25 12:40:22 PM PDT 24
Peak memory 225348 kb
Host smart-a6126044-0f07-4f0c-80df-1099c71c84bc
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=474915616 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_c
orrupt_sig_fatal_chk.474915616
Directory /workspace/18.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/18.rom_ctrl_kmac_err_chk.2307795631
Short name T251
Test name
Test status
Simulation time 11777235506 ps
CPU time 26.07 seconds
Started Apr 25 12:37:09 PM PDT 24
Finished Apr 25 12:37:38 PM PDT 24
Peak memory 211464 kb
Host smart-9a04f11d-32ea-4bea-9bd3-ba162fa0ef8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2307795631 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_kmac_err_chk.2307795631
Directory /workspace/18.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/18.rom_ctrl_max_throughput_chk.3899761310
Short name T144
Test name
Test status
Simulation time 1997030643 ps
CPU time 11.2 seconds
Started Apr 25 12:36:53 PM PDT 24
Finished Apr 25 12:37:06 PM PDT 24
Peak memory 211292 kb
Host smart-04c470b8-69ed-4107-be02-23d8a8f8760e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3899761310 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_max_throughput_chk.3899761310
Directory /workspace/18.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/18.rom_ctrl_smoke.1012990185
Short name T211
Test name
Test status
Simulation time 12486473654 ps
CPU time 29.91 seconds
Started Apr 25 12:36:58 PM PDT 24
Finished Apr 25 12:37:30 PM PDT 24
Peak memory 219632 kb
Host smart-6a189bc7-74e8-4ac7-879e-bf528d6eb150
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1012990185 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_smoke.1012990185
Directory /workspace/18.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/19.rom_ctrl_corrupt_sig_fatal_chk.1446089352
Short name T332
Test name
Test status
Simulation time 238963279633 ps
CPU time 568.83 seconds
Started Apr 25 12:37:25 PM PDT 24
Finished Apr 25 12:46:57 PM PDT 24
Peak memory 224684 kb
Host smart-81d8b0af-d9d3-4b3a-a9f6-55221b55b302
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1446089352 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_
corrupt_sig_fatal_chk.1446089352
Directory /workspace/19.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/19.rom_ctrl_max_throughput_chk.220285870
Short name T115
Test name
Test status
Simulation time 265417339 ps
CPU time 7.29 seconds
Started Apr 25 12:37:13 PM PDT 24
Finished Apr 25 12:37:23 PM PDT 24
Peak memory 211280 kb
Host smart-197eae77-2954-4cc3-8ff2-9f60ff2bda94
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=220285870 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_max_throughput_chk.220285870
Directory /workspace/19.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/19.rom_ctrl_smoke.170647022
Short name T91
Test name
Test status
Simulation time 1784287721 ps
CPU time 12.88 seconds
Started Apr 25 12:37:04 PM PDT 24
Finished Apr 25 12:37:19 PM PDT 24
Peak memory 219528 kb
Host smart-162c57e8-0a24-4053-a2f6-2a5b12ae6871
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=170647022 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_smoke.170647022
Directory /workspace/19.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/19.rom_ctrl_stress_all.129424195
Short name T356
Test name
Test status
Simulation time 9761254576 ps
CPU time 52.63 seconds
Started Apr 25 12:37:07 PM PDT 24
Finished Apr 25 12:38:02 PM PDT 24
Peak memory 214748 kb
Host smart-8363876a-11c0-4e76-803d-876fa5181480
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=129424195 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 19.rom_ctrl_stress_all.129424195
Directory /workspace/19.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/19.rom_ctrl_stress_all_with_rand_reset.208693590
Short name T43
Test name
Test status
Simulation time 15481846011 ps
CPU time 1196.95 seconds
Started Apr 25 12:37:16 PM PDT 24
Finished Apr 25 12:57:16 PM PDT 24
Peak memory 228392 kb
Host smart-187426f4-53e0-49da-bf0e-83982ad9adf6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=208693590 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_stress_all_with_rand_reset.208693590
Directory /workspace/19.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.rom_ctrl_alert_test.4045042771
Short name T187
Test name
Test status
Simulation time 219813606 ps
CPU time 4.21 seconds
Started Apr 25 12:36:51 PM PDT 24
Finished Apr 25 12:36:57 PM PDT 24
Peak memory 211400 kb
Host smart-1d4d7358-c0c2-4bd8-93bf-b84fd46a4756
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4045042771 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_alert_test.4045042771
Directory /workspace/2.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/2.rom_ctrl_corrupt_sig_fatal_chk.4208991030
Short name T331
Test name
Test status
Simulation time 104714760780 ps
CPU time 246.94 seconds
Started Apr 25 12:36:52 PM PDT 24
Finished Apr 25 12:41:01 PM PDT 24
Peak memory 221492 kb
Host smart-7e68ccae-d0c0-48f6-9e6d-a0405fb314d5
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4208991030 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_c
orrupt_sig_fatal_chk.4208991030
Directory /workspace/2.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/2.rom_ctrl_kmac_err_chk.2320887708
Short name T181
Test name
Test status
Simulation time 1430865045 ps
CPU time 11.49 seconds
Started Apr 25 12:36:44 PM PDT 24
Finished Apr 25 12:36:56 PM PDT 24
Peak memory 211452 kb
Host smart-6a9f5d51-5d3d-43a0-a4bb-3fdbefff8581
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2320887708 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_kmac_err_chk.2320887708
Directory /workspace/2.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/2.rom_ctrl_max_throughput_chk.3543591783
Short name T265
Test name
Test status
Simulation time 99704463 ps
CPU time 5.87 seconds
Started Apr 25 12:36:56 PM PDT 24
Finished Apr 25 12:37:04 PM PDT 24
Peak memory 211308 kb
Host smart-ac0fbe58-7e4e-4e02-a697-9aca5f65be4a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3543591783 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_max_throughput_chk.3543591783
Directory /workspace/2.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/2.rom_ctrl_smoke.3850949231
Short name T300
Test name
Test status
Simulation time 8336853542 ps
CPU time 37.75 seconds
Started Apr 25 12:36:39 PM PDT 24
Finished Apr 25 12:37:17 PM PDT 24
Peak memory 213896 kb
Host smart-8c3e39ea-883a-430f-872f-3ff8ad01ce53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3850949231 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_smoke.3850949231
Directory /workspace/2.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/2.rom_ctrl_stress_all.88411868
Short name T258
Test name
Test status
Simulation time 15329730501 ps
CPU time 50.42 seconds
Started Apr 25 12:36:42 PM PDT 24
Finished Apr 25 12:37:33 PM PDT 24
Peak memory 219496 kb
Host smart-163794e1-17ea-46bb-a5bd-a4d7ce03f001
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=88411868 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +U
VM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n
ame 2.rom_ctrl_stress_all.88411868
Directory /workspace/2.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/20.rom_ctrl_alert_test.1139707531
Short name T33
Test name
Test status
Simulation time 3022296263 ps
CPU time 12.3 seconds
Started Apr 25 12:37:11 PM PDT 24
Finished Apr 25 12:37:26 PM PDT 24
Peak memory 211424 kb
Host smart-42744311-7a1a-4feb-a7b0-065698d3420e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1139707531 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_alert_test.1139707531
Directory /workspace/20.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/20.rom_ctrl_corrupt_sig_fatal_chk.2570801034
Short name T349
Test name
Test status
Simulation time 144770265222 ps
CPU time 383.29 seconds
Started Apr 25 12:37:10 PM PDT 24
Finished Apr 25 12:43:36 PM PDT 24
Peak memory 237984 kb
Host smart-d15cd65e-fdde-47d3-a13a-d232e77fdcba
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2570801034 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_
corrupt_sig_fatal_chk.2570801034
Directory /workspace/20.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/20.rom_ctrl_kmac_err_chk.3111497164
Short name T117
Test name
Test status
Simulation time 437706209 ps
CPU time 12.43 seconds
Started Apr 25 12:37:08 PM PDT 24
Finished Apr 25 12:37:24 PM PDT 24
Peak memory 212056 kb
Host smart-654979a7-9402-4bda-ab75-4c5bd2f63b28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3111497164 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_kmac_err_chk.3111497164
Directory /workspace/20.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/20.rom_ctrl_max_throughput_chk.3583745189
Short name T146
Test name
Test status
Simulation time 8658004388 ps
CPU time 15.45 seconds
Started Apr 25 12:37:11 PM PDT 24
Finished Apr 25 12:37:30 PM PDT 24
Peak memory 211336 kb
Host smart-2fe6cd6a-b369-478e-a0c5-1419192e309b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3583745189 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_max_throughput_chk.3583745189
Directory /workspace/20.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/20.rom_ctrl_smoke.1950218320
Short name T320
Test name
Test status
Simulation time 23984822410 ps
CPU time 35.95 seconds
Started Apr 25 12:37:07 PM PDT 24
Finished Apr 25 12:37:46 PM PDT 24
Peak memory 214068 kb
Host smart-f540af5f-56bb-4778-afee-8a96bb1f1649
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1950218320 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_smoke.1950218320
Directory /workspace/20.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/20.rom_ctrl_stress_all.1138073581
Short name T224
Test name
Test status
Simulation time 5907099271 ps
CPU time 44.42 seconds
Started Apr 25 12:36:56 PM PDT 24
Finished Apr 25 12:37:42 PM PDT 24
Peak memory 219548 kb
Host smart-4fd20e64-75c1-4f78-9ce3-44b6e66989b1
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1138073581 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 20.rom_ctrl_stress_all.1138073581
Directory /workspace/20.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/21.rom_ctrl_alert_test.3065023106
Short name T51
Test name
Test status
Simulation time 2621533181 ps
CPU time 8.24 seconds
Started Apr 25 12:37:13 PM PDT 24
Finished Apr 25 12:37:24 PM PDT 24
Peak memory 211392 kb
Host smart-e2ce3551-f23c-474e-86e0-13ee7b45b119
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3065023106 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_alert_test.3065023106
Directory /workspace/21.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/21.rom_ctrl_corrupt_sig_fatal_chk.1113829075
Short name T283
Test name
Test status
Simulation time 4732221726 ps
CPU time 167.09 seconds
Started Apr 25 12:37:18 PM PDT 24
Finished Apr 25 12:40:08 PM PDT 24
Peak memory 228532 kb
Host smart-b80abe53-9d44-4fd4-9260-a221de3a3fe6
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1113829075 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_
corrupt_sig_fatal_chk.1113829075
Directory /workspace/21.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/21.rom_ctrl_kmac_err_chk.1040594771
Short name T154
Test name
Test status
Simulation time 2415545562 ps
CPU time 23.42 seconds
Started Apr 25 12:37:11 PM PDT 24
Finished Apr 25 12:37:37 PM PDT 24
Peak memory 212076 kb
Host smart-8e18cfe8-7d80-47f1-a62b-786f94be54b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1040594771 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_kmac_err_chk.1040594771
Directory /workspace/21.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/21.rom_ctrl_max_throughput_chk.1255306324
Short name T182
Test name
Test status
Simulation time 31867148277 ps
CPU time 15.74 seconds
Started Apr 25 12:37:01 PM PDT 24
Finished Apr 25 12:37:18 PM PDT 24
Peak memory 211340 kb
Host smart-cf0a50ad-7295-4592-bee8-6aea8214b7f1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1255306324 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_max_throughput_chk.1255306324
Directory /workspace/21.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/21.rom_ctrl_smoke.3312364365
Short name T306
Test name
Test status
Simulation time 4021987248 ps
CPU time 38.01 seconds
Started Apr 25 12:37:16 PM PDT 24
Finished Apr 25 12:37:58 PM PDT 24
Peak memory 213236 kb
Host smart-f29f1c34-35a3-4f96-bb75-07bf3fc39f66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3312364365 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_smoke.3312364365
Directory /workspace/21.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/21.rom_ctrl_stress_all.2894559193
Short name T68
Test name
Test status
Simulation time 8059608355 ps
CPU time 14.16 seconds
Started Apr 25 12:37:12 PM PDT 24
Finished Apr 25 12:37:34 PM PDT 24
Peak memory 212508 kb
Host smart-706cb7f6-3afd-4a26-b800-75e8be23ce47
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2894559193 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 21.rom_ctrl_stress_all.2894559193
Directory /workspace/21.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/22.rom_ctrl_alert_test.704493514
Short name T165
Test name
Test status
Simulation time 4504654691 ps
CPU time 15.78 seconds
Started Apr 25 12:37:25 PM PDT 24
Finished Apr 25 12:37:43 PM PDT 24
Peak memory 211408 kb
Host smart-31c141b3-ffdb-48ef-9431-9bc2ea855b78
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=704493514 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_alert_test.704493514
Directory /workspace/22.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/22.rom_ctrl_corrupt_sig_fatal_chk.322844315
Short name T128
Test name
Test status
Simulation time 4354722235 ps
CPU time 66.15 seconds
Started Apr 25 12:37:19 PM PDT 24
Finished Apr 25 12:38:28 PM PDT 24
Peak memory 237364 kb
Host smart-e417455b-c99f-4160-a12b-ba9e6fd838de
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=322844315 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_c
orrupt_sig_fatal_chk.322844315
Directory /workspace/22.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/22.rom_ctrl_kmac_err_chk.1960887075
Short name T231
Test name
Test status
Simulation time 15587263308 ps
CPU time 32.47 seconds
Started Apr 25 12:37:00 PM PDT 24
Finished Apr 25 12:37:34 PM PDT 24
Peak memory 212372 kb
Host smart-3bcfa9df-5ec5-41cf-b046-a7099ae72fec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1960887075 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_kmac_err_chk.1960887075
Directory /workspace/22.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/22.rom_ctrl_max_throughput_chk.1820648898
Short name T216
Test name
Test status
Simulation time 6933994403 ps
CPU time 16.11 seconds
Started Apr 25 12:37:16 PM PDT 24
Finished Apr 25 12:37:35 PM PDT 24
Peak memory 211392 kb
Host smart-5ac3d991-4765-4c4b-96f2-7e2b55b117c7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1820648898 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_max_throughput_chk.1820648898
Directory /workspace/22.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/22.rom_ctrl_smoke.2291418618
Short name T212
Test name
Test status
Simulation time 2481807988 ps
CPU time 23.95 seconds
Started Apr 25 12:37:15 PM PDT 24
Finished Apr 25 12:37:42 PM PDT 24
Peak memory 219572 kb
Host smart-bf05b288-33e9-481a-806b-4f0fe40f8051
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2291418618 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_smoke.2291418618
Directory /workspace/22.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/22.rom_ctrl_stress_all.3807167463
Short name T67
Test name
Test status
Simulation time 12634092362 ps
CPU time 41.61 seconds
Started Apr 25 12:37:11 PM PDT 24
Finished Apr 25 12:37:56 PM PDT 24
Peak memory 219548 kb
Host smart-a7974c51-f993-48af-8dd7-6d5b6ea3e843
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3807167463 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 22.rom_ctrl_stress_all.3807167463
Directory /workspace/22.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/23.rom_ctrl_alert_test.1592707967
Short name T301
Test name
Test status
Simulation time 7701253128 ps
CPU time 15.76 seconds
Started Apr 25 12:37:19 PM PDT 24
Finished Apr 25 12:37:39 PM PDT 24
Peak memory 211432 kb
Host smart-8439e7d8-e077-42a6-b53d-4cab5d197445
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1592707967 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_alert_test.1592707967
Directory /workspace/23.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/23.rom_ctrl_corrupt_sig_fatal_chk.33560536
Short name T20
Test name
Test status
Simulation time 189878887102 ps
CPU time 446.25 seconds
Started Apr 25 12:37:14 PM PDT 24
Finished Apr 25 12:44:43 PM PDT 24
Peak memory 237008 kb
Host smart-1d7a0078-add8-45a2-96fa-9198538e9581
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33560536 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_
sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_co
rrupt_sig_fatal_chk.33560536
Directory /workspace/23.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/23.rom_ctrl_kmac_err_chk.261499737
Short name T237
Test name
Test status
Simulation time 321842095 ps
CPU time 9.36 seconds
Started Apr 25 12:37:17 PM PDT 24
Finished Apr 25 12:37:29 PM PDT 24
Peak memory 212144 kb
Host smart-30ab157d-70b0-484c-8c5b-a301f06a4ae9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=261499737 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_kmac_err_chk.261499737
Directory /workspace/23.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/23.rom_ctrl_max_throughput_chk.817443924
Short name T298
Test name
Test status
Simulation time 1470776181 ps
CPU time 13.37 seconds
Started Apr 25 12:37:25 PM PDT 24
Finished Apr 25 12:37:40 PM PDT 24
Peak memory 211324 kb
Host smart-573c404a-347e-4f7c-9212-cfa9e528e152
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=817443924 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_max_throughput_chk.817443924
Directory /workspace/23.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/23.rom_ctrl_smoke.4024980991
Short name T166
Test name
Test status
Simulation time 787161431 ps
CPU time 14.94 seconds
Started Apr 25 12:37:23 PM PDT 24
Finished Apr 25 12:37:40 PM PDT 24
Peak memory 219560 kb
Host smart-28520862-8a21-45ee-9fe1-14cd25e6460f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4024980991 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_smoke.4024980991
Directory /workspace/23.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/23.rom_ctrl_stress_all.2419727543
Short name T326
Test name
Test status
Simulation time 148574275 ps
CPU time 11.16 seconds
Started Apr 25 12:37:18 PM PDT 24
Finished Apr 25 12:37:32 PM PDT 24
Peak memory 211248 kb
Host smart-4854d5b0-528f-4c16-acd6-5c699cc59d8f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2419727543 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 23.rom_ctrl_stress_all.2419727543
Directory /workspace/23.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/24.rom_ctrl_alert_test.2860672135
Short name T244
Test name
Test status
Simulation time 4075552921 ps
CPU time 10.18 seconds
Started Apr 25 12:37:10 PM PDT 24
Finished Apr 25 12:37:24 PM PDT 24
Peak memory 211440 kb
Host smart-e685f98d-6344-446f-8c86-5a5c6ce5c501
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2860672135 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_alert_test.2860672135
Directory /workspace/24.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/24.rom_ctrl_corrupt_sig_fatal_chk.3310876514
Short name T14
Test name
Test status
Simulation time 20955386424 ps
CPU time 281.82 seconds
Started Apr 25 12:37:18 PM PDT 24
Finished Apr 25 12:42:04 PM PDT 24
Peak memory 211472 kb
Host smart-043a3f79-1c82-4864-af28-f7b9de6b8317
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3310876514 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_
corrupt_sig_fatal_chk.3310876514
Directory /workspace/24.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/24.rom_ctrl_kmac_err_chk.2375150255
Short name T292
Test name
Test status
Simulation time 2547402067 ps
CPU time 23.69 seconds
Started Apr 25 12:37:21 PM PDT 24
Finished Apr 25 12:37:48 PM PDT 24
Peak memory 211496 kb
Host smart-bfad8a60-0a78-4b26-9b5e-dcf832336c3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2375150255 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_kmac_err_chk.2375150255
Directory /workspace/24.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/24.rom_ctrl_max_throughput_chk.47807434
Short name T257
Test name
Test status
Simulation time 4359657646 ps
CPU time 13.54 seconds
Started Apr 25 12:37:14 PM PDT 24
Finished Apr 25 12:37:30 PM PDT 24
Peak memory 211364 kb
Host smart-59d760f5-e453-47fa-b4fb-2e25b514e1ad
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=47807434 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_max_throughput_chk.47807434
Directory /workspace/24.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/24.rom_ctrl_smoke.1471065111
Short name T305
Test name
Test status
Simulation time 3798523536 ps
CPU time 22.17 seconds
Started Apr 25 12:37:12 PM PDT 24
Finished Apr 25 12:37:37 PM PDT 24
Peak memory 219636 kb
Host smart-f34e2ac8-ad26-4cbf-a5fe-ee8e3f23d6bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1471065111 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_smoke.1471065111
Directory /workspace/24.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/24.rom_ctrl_stress_all.2185336031
Short name T333
Test name
Test status
Simulation time 245054501 ps
CPU time 7.15 seconds
Started Apr 25 12:37:14 PM PDT 24
Finished Apr 25 12:37:24 PM PDT 24
Peak memory 211328 kb
Host smart-d5cc838b-51cb-4dd8-a395-91d33839276b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2185336031 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 24.rom_ctrl_stress_all.2185336031
Directory /workspace/24.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/25.rom_ctrl_alert_test.3377822989
Short name T52
Test name
Test status
Simulation time 886718011 ps
CPU time 9.56 seconds
Started Apr 25 12:37:11 PM PDT 24
Finished Apr 25 12:37:23 PM PDT 24
Peak memory 211384 kb
Host smart-4d18dd62-0c9b-4e49-920b-91feaa7b2b14
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3377822989 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_alert_test.3377822989
Directory /workspace/25.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/25.rom_ctrl_corrupt_sig_fatal_chk.554045560
Short name T201
Test name
Test status
Simulation time 2167868010 ps
CPU time 125.47 seconds
Started Apr 25 12:37:18 PM PDT 24
Finished Apr 25 12:39:27 PM PDT 24
Peak memory 237992 kb
Host smart-11d9b658-22bd-4e44-ba60-147030f4ef77
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=554045560 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_c
orrupt_sig_fatal_chk.554045560
Directory /workspace/25.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/25.rom_ctrl_kmac_err_chk.615023363
Short name T126
Test name
Test status
Simulation time 13820840539 ps
CPU time 27.12 seconds
Started Apr 25 12:37:11 PM PDT 24
Finished Apr 25 12:37:41 PM PDT 24
Peak memory 213824 kb
Host smart-5778c667-4875-415f-bea7-7906bc1ff6bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=615023363 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_kmac_err_chk.615023363
Directory /workspace/25.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/25.rom_ctrl_max_throughput_chk.1741490937
Short name T105
Test name
Test status
Simulation time 390613978 ps
CPU time 5.74 seconds
Started Apr 25 12:37:07 PM PDT 24
Finished Apr 25 12:37:16 PM PDT 24
Peak memory 210692 kb
Host smart-b862bfbd-8a70-4239-8cbd-7eef5fe28dbc
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1741490937 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_max_throughput_chk.1741490937
Directory /workspace/25.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/25.rom_ctrl_smoke.418206083
Short name T142
Test name
Test status
Simulation time 374200493 ps
CPU time 10.46 seconds
Started Apr 25 12:37:19 PM PDT 24
Finished Apr 25 12:37:33 PM PDT 24
Peak memory 219544 kb
Host smart-2840953f-bef8-44ae-a8da-e776dcdd9cde
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=418206083 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_smoke.418206083
Directory /workspace/25.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/25.rom_ctrl_stress_all.1357196055
Short name T339
Test name
Test status
Simulation time 5029241858 ps
CPU time 14.81 seconds
Started Apr 25 12:37:16 PM PDT 24
Finished Apr 25 12:37:33 PM PDT 24
Peak memory 212388 kb
Host smart-9e81563b-e56f-4a7d-a99e-3fe475d574c9
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1357196055 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 25.rom_ctrl_stress_all.1357196055
Directory /workspace/25.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/26.rom_ctrl_alert_test.2566252943
Short name T337
Test name
Test status
Simulation time 940586945 ps
CPU time 7.38 seconds
Started Apr 25 12:37:06 PM PDT 24
Finished Apr 25 12:37:16 PM PDT 24
Peak memory 211344 kb
Host smart-7e8fe222-3253-4f58-8e15-52da43317efd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2566252943 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_alert_test.2566252943
Directory /workspace/26.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/26.rom_ctrl_corrupt_sig_fatal_chk.1308006742
Short name T138
Test name
Test status
Simulation time 147384086480 ps
CPU time 337.55 seconds
Started Apr 25 12:37:07 PM PDT 24
Finished Apr 25 12:42:48 PM PDT 24
Peak memory 212716 kb
Host smart-a3ae5f6e-440d-438f-851b-dc8b3cef1fc5
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1308006742 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_
corrupt_sig_fatal_chk.1308006742
Directory /workspace/26.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/26.rom_ctrl_kmac_err_chk.4026365020
Short name T353
Test name
Test status
Simulation time 15619638457 ps
CPU time 32.29 seconds
Started Apr 25 12:37:07 PM PDT 24
Finished Apr 25 12:37:42 PM PDT 24
Peak memory 212292 kb
Host smart-c42e5c1f-2143-4f8c-abe4-0c2e787b1e93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4026365020 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_kmac_err_chk.4026365020
Directory /workspace/26.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/26.rom_ctrl_max_throughput_chk.2134428974
Short name T352
Test name
Test status
Simulation time 340401665 ps
CPU time 7.89 seconds
Started Apr 25 12:37:12 PM PDT 24
Finished Apr 25 12:37:23 PM PDT 24
Peak memory 211236 kb
Host smart-12bf8dfc-4a47-45d1-9193-049375849acd
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2134428974 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_max_throughput_chk.2134428974
Directory /workspace/26.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/26.rom_ctrl_smoke.1622579042
Short name T163
Test name
Test status
Simulation time 16989756053 ps
CPU time 38.22 seconds
Started Apr 25 12:37:12 PM PDT 24
Finished Apr 25 12:37:53 PM PDT 24
Peak memory 219572 kb
Host smart-5a66983b-6aa3-4295-97fa-536790e943fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1622579042 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_smoke.1622579042
Directory /workspace/26.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/26.rom_ctrl_stress_all.3068585742
Short name T160
Test name
Test status
Simulation time 1126329236 ps
CPU time 8.17 seconds
Started Apr 25 12:37:20 PM PDT 24
Finished Apr 25 12:37:31 PM PDT 24
Peak memory 212204 kb
Host smart-babc6444-52bc-4dc3-97fa-e7c4b61151f3
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3068585742 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 26.rom_ctrl_stress_all.3068585742
Directory /workspace/26.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/27.rom_ctrl_alert_test.4175767168
Short name T136
Test name
Test status
Simulation time 378047389 ps
CPU time 4.28 seconds
Started Apr 25 12:37:09 PM PDT 24
Finished Apr 25 12:37:16 PM PDT 24
Peak memory 211372 kb
Host smart-6234d9a7-b9d9-4f8f-95da-dffee75d3435
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4175767168 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_alert_test.4175767168
Directory /workspace/27.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/27.rom_ctrl_corrupt_sig_fatal_chk.3448842996
Short name T223
Test name
Test status
Simulation time 41771282311 ps
CPU time 275.91 seconds
Started Apr 25 12:37:18 PM PDT 24
Finished Apr 25 12:41:57 PM PDT 24
Peak memory 236852 kb
Host smart-d5e1d679-33b3-4488-80cb-384ebc2b6b8d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3448842996 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_
corrupt_sig_fatal_chk.3448842996
Directory /workspace/27.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/27.rom_ctrl_kmac_err_chk.944415705
Short name T294
Test name
Test status
Simulation time 341258820 ps
CPU time 9.35 seconds
Started Apr 25 12:37:17 PM PDT 24
Finished Apr 25 12:37:30 PM PDT 24
Peak memory 212192 kb
Host smart-ed223664-ff69-44c4-baf7-f1b486f3a926
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=944415705 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_kmac_err_chk.944415705
Directory /workspace/27.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/27.rom_ctrl_max_throughput_chk.846443279
Short name T361
Test name
Test status
Simulation time 8235039955 ps
CPU time 17.03 seconds
Started Apr 25 12:37:04 PM PDT 24
Finished Apr 25 12:37:23 PM PDT 24
Peak memory 211400 kb
Host smart-8cd7dcd1-2518-426d-beb3-b61d77ad7b80
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=846443279 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_max_throughput_chk.846443279
Directory /workspace/27.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/27.rom_ctrl_smoke.2731383647
Short name T62
Test name
Test status
Simulation time 12030100295 ps
CPU time 30.82 seconds
Started Apr 25 12:37:09 PM PDT 24
Finished Apr 25 12:37:43 PM PDT 24
Peak memory 219532 kb
Host smart-a38c717f-2769-40e0-9e66-85650f926e28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2731383647 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_smoke.2731383647
Directory /workspace/27.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/27.rom_ctrl_stress_all.2017647831
Short name T234
Test name
Test status
Simulation time 5880024016 ps
CPU time 47.44 seconds
Started Apr 25 12:37:15 PM PDT 24
Finished Apr 25 12:38:05 PM PDT 24
Peak memory 219568 kb
Host smart-98ad9119-b1f3-43ac-80be-24019ec10b12
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2017647831 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 27.rom_ctrl_stress_all.2017647831
Directory /workspace/27.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/28.rom_ctrl_alert_test.266446286
Short name T245
Test name
Test status
Simulation time 2193208073 ps
CPU time 16.84 seconds
Started Apr 25 12:37:19 PM PDT 24
Finished Apr 25 12:37:40 PM PDT 24
Peak memory 211460 kb
Host smart-ef98b16e-2b50-40f0-82d1-d678ead5431a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=266446286 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_alert_test.266446286
Directory /workspace/28.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/28.rom_ctrl_corrupt_sig_fatal_chk.407867050
Short name T120
Test name
Test status
Simulation time 3572205308 ps
CPU time 109.05 seconds
Started Apr 25 12:37:06 PM PDT 24
Finished Apr 25 12:38:58 PM PDT 24
Peak memory 238056 kb
Host smart-0598e160-9811-402f-97e2-a03e89d66acc
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=407867050 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_c
orrupt_sig_fatal_chk.407867050
Directory /workspace/28.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/28.rom_ctrl_kmac_err_chk.1617248977
Short name T123
Test name
Test status
Simulation time 768739828 ps
CPU time 14.39 seconds
Started Apr 25 12:37:10 PM PDT 24
Finished Apr 25 12:37:27 PM PDT 24
Peak memory 211940 kb
Host smart-1641ae58-62fc-409f-894f-ae050fdd5703
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1617248977 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_kmac_err_chk.1617248977
Directory /workspace/28.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/28.rom_ctrl_max_throughput_chk.2823601977
Short name T316
Test name
Test status
Simulation time 372217368 ps
CPU time 5.43 seconds
Started Apr 25 12:37:27 PM PDT 24
Finished Apr 25 12:37:35 PM PDT 24
Peak memory 211320 kb
Host smart-472a46bf-36d7-4087-a583-bdae3dd43e00
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2823601977 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_max_throughput_chk.2823601977
Directory /workspace/28.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/28.rom_ctrl_smoke.450197062
Short name T344
Test name
Test status
Simulation time 3029541853 ps
CPU time 19.75 seconds
Started Apr 25 12:37:07 PM PDT 24
Finished Apr 25 12:37:30 PM PDT 24
Peak memory 213364 kb
Host smart-59d8c525-8461-4301-a818-01e25ae00920
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=450197062 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_smoke.450197062
Directory /workspace/28.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/28.rom_ctrl_stress_all.4238431808
Short name T345
Test name
Test status
Simulation time 307388743 ps
CPU time 17.83 seconds
Started Apr 25 12:37:16 PM PDT 24
Finished Apr 25 12:37:37 PM PDT 24
Peak memory 219524 kb
Host smart-15c65b7c-608e-4bf5-800b-f73121ee496b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4238431808 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 28.rom_ctrl_stress_all.4238431808
Directory /workspace/28.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/29.rom_ctrl_alert_test.2250600447
Short name T242
Test name
Test status
Simulation time 3934215492 ps
CPU time 15.16 seconds
Started Apr 25 12:37:22 PM PDT 24
Finished Apr 25 12:37:40 PM PDT 24
Peak memory 211404 kb
Host smart-8f95fc7a-d795-4e5a-92ed-39b22774915c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2250600447 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_alert_test.2250600447
Directory /workspace/29.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/29.rom_ctrl_corrupt_sig_fatal_chk.1705219938
Short name T157
Test name
Test status
Simulation time 4717670690 ps
CPU time 72.59 seconds
Started Apr 25 12:37:18 PM PDT 24
Finished Apr 25 12:38:34 PM PDT 24
Peak memory 237352 kb
Host smart-976c99af-0189-489f-9dab-1bdb50c18fbc
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1705219938 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_
corrupt_sig_fatal_chk.1705219938
Directory /workspace/29.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/29.rom_ctrl_kmac_err_chk.2385865854
Short name T129
Test name
Test status
Simulation time 8801562940 ps
CPU time 23.52 seconds
Started Apr 25 12:37:20 PM PDT 24
Finished Apr 25 12:37:47 PM PDT 24
Peak memory 212248 kb
Host smart-fccd0a8d-4176-45e8-b671-2aeff31065a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2385865854 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_kmac_err_chk.2385865854
Directory /workspace/29.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/29.rom_ctrl_max_throughput_chk.905786379
Short name T3
Test name
Test status
Simulation time 999623623 ps
CPU time 11.24 seconds
Started Apr 25 12:37:19 PM PDT 24
Finished Apr 25 12:37:34 PM PDT 24
Peak memory 211304 kb
Host smart-8c3b545d-a207-42b2-b53f-203688a7e1e4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=905786379 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_max_throughput_chk.905786379
Directory /workspace/29.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/29.rom_ctrl_smoke.1753340446
Short name T363
Test name
Test status
Simulation time 17084258347 ps
CPU time 30.88 seconds
Started Apr 25 12:37:13 PM PDT 24
Finished Apr 25 12:37:46 PM PDT 24
Peak memory 219612 kb
Host smart-d5f85b9c-3894-49a2-b933-fba779f34652
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1753340446 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_smoke.1753340446
Directory /workspace/29.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/29.rom_ctrl_stress_all.2555658995
Short name T209
Test name
Test status
Simulation time 10368439581 ps
CPU time 26.76 seconds
Started Apr 25 12:37:23 PM PDT 24
Finished Apr 25 12:37:51 PM PDT 24
Peak memory 219552 kb
Host smart-63d41df0-6173-45e2-b9f5-dde3b987fd70
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2555658995 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 29.rom_ctrl_stress_all.2555658995
Directory /workspace/29.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/3.rom_ctrl_alert_test.283135466
Short name T273
Test name
Test status
Simulation time 152789115 ps
CPU time 4.21 seconds
Started Apr 25 12:36:58 PM PDT 24
Finished Apr 25 12:37:04 PM PDT 24
Peak memory 211400 kb
Host smart-aeb70228-e6fe-41c5-921e-78dceb2f21a8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=283135466 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_alert_test.283135466
Directory /workspace/3.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/3.rom_ctrl_corrupt_sig_fatal_chk.2885521909
Short name T141
Test name
Test status
Simulation time 8584765934 ps
CPU time 203.26 seconds
Started Apr 25 12:37:05 PM PDT 24
Finished Apr 25 12:40:29 PM PDT 24
Peak memory 228836 kb
Host smart-821780bb-8b8e-4025-a78b-b4e34559a540
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2885521909 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_c
orrupt_sig_fatal_chk.2885521909
Directory /workspace/3.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/3.rom_ctrl_kmac_err_chk.1110616015
Short name T204
Test name
Test status
Simulation time 1602362719 ps
CPU time 19.48 seconds
Started Apr 25 12:36:53 PM PDT 24
Finished Apr 25 12:37:14 PM PDT 24
Peak memory 211432 kb
Host smart-402cf14f-2c36-47bd-8ea5-e1cf72ecf856
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1110616015 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_kmac_err_chk.1110616015
Directory /workspace/3.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/3.rom_ctrl_max_throughput_chk.3776585763
Short name T270
Test name
Test status
Simulation time 392847720 ps
CPU time 5.67 seconds
Started Apr 25 12:36:47 PM PDT 24
Finished Apr 25 12:36:54 PM PDT 24
Peak memory 211320 kb
Host smart-2b0adcdf-24ba-4515-ac9d-07d5e1a6c355
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3776585763 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_max_throughput_chk.3776585763
Directory /workspace/3.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/3.rom_ctrl_sec_cm.1579750146
Short name T35
Test name
Test status
Simulation time 3826940358 ps
CPU time 105.56 seconds
Started Apr 25 12:36:56 PM PDT 24
Finished Apr 25 12:38:42 PM PDT 24
Peak memory 231484 kb
Host smart-41b40b9d-bba7-4fe5-a3d9-80f0a24e72e4
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1579750146 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_sec_cm.1579750146
Directory /workspace/3.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/3.rom_ctrl_smoke.2857596974
Short name T291
Test name
Test status
Simulation time 8036801380 ps
CPU time 40.12 seconds
Started Apr 25 12:36:55 PM PDT 24
Finished Apr 25 12:37:36 PM PDT 24
Peak memory 215008 kb
Host smart-d1f2de1a-d27c-476e-ab3a-99e0aa66d127
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2857596974 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_smoke.2857596974
Directory /workspace/3.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/3.rom_ctrl_stress_all.942252021
Short name T10
Test name
Test status
Simulation time 86415233761 ps
CPU time 48.59 seconds
Started Apr 25 12:36:41 PM PDT 24
Finished Apr 25 12:37:30 PM PDT 24
Peak memory 213556 kb
Host smart-08be7f85-f07c-486f-8c36-64c302d14b39
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=942252021 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 3.rom_ctrl_stress_all.942252021
Directory /workspace/3.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/30.rom_ctrl_alert_test.3589928667
Short name T282
Test name
Test status
Simulation time 556465323 ps
CPU time 6.69 seconds
Started Apr 25 12:37:18 PM PDT 24
Finished Apr 25 12:37:29 PM PDT 24
Peak memory 211400 kb
Host smart-5e3e0ca6-fd2d-44d6-b171-6925cbe42415
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3589928667 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_alert_test.3589928667
Directory /workspace/30.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/30.rom_ctrl_corrupt_sig_fatal_chk.2766387688
Short name T111
Test name
Test status
Simulation time 40107363068 ps
CPU time 95.33 seconds
Started Apr 25 12:37:18 PM PDT 24
Finished Apr 25 12:38:57 PM PDT 24
Peak memory 227392 kb
Host smart-e2b34050-625f-417a-87c3-5210026ab6b0
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2766387688 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_
corrupt_sig_fatal_chk.2766387688
Directory /workspace/30.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/30.rom_ctrl_kmac_err_chk.186431910
Short name T125
Test name
Test status
Simulation time 7683725467 ps
CPU time 25.59 seconds
Started Apr 25 12:37:13 PM PDT 24
Finished Apr 25 12:37:41 PM PDT 24
Peak memory 212532 kb
Host smart-02b46b3c-1516-4694-9dfd-e9510efecd7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=186431910 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_kmac_err_chk.186431910
Directory /workspace/30.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/30.rom_ctrl_max_throughput_chk.2216995545
Short name T274
Test name
Test status
Simulation time 1992777683 ps
CPU time 16.4 seconds
Started Apr 25 12:37:18 PM PDT 24
Finished Apr 25 12:37:38 PM PDT 24
Peak memory 211284 kb
Host smart-35a76f3f-e263-4d02-9938-5ef83daf39b3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2216995545 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_max_throughput_chk.2216995545
Directory /workspace/30.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/30.rom_ctrl_smoke.3014150314
Short name T219
Test name
Test status
Simulation time 3134300558 ps
CPU time 15.55 seconds
Started Apr 25 12:37:16 PM PDT 24
Finished Apr 25 12:37:35 PM PDT 24
Peak memory 214096 kb
Host smart-8c00a75e-c187-4369-ad06-2e5a0aded3a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3014150314 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_smoke.3014150314
Directory /workspace/30.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/30.rom_ctrl_stress_all.2868117741
Short name T318
Test name
Test status
Simulation time 1865956443 ps
CPU time 13.95 seconds
Started Apr 25 12:37:18 PM PDT 24
Finished Apr 25 12:37:36 PM PDT 24
Peak memory 212144 kb
Host smart-9d9c611f-fcb9-49a4-b330-d755569808de
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2868117741 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 30.rom_ctrl_stress_all.2868117741
Directory /workspace/30.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/31.rom_ctrl_alert_test.4131242178
Short name T236
Test name
Test status
Simulation time 2309746342 ps
CPU time 8.2 seconds
Started Apr 25 12:37:10 PM PDT 24
Finished Apr 25 12:37:21 PM PDT 24
Peak memory 211340 kb
Host smart-589d1443-1ec9-4cea-a6db-7d753e32428a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4131242178 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_alert_test.4131242178
Directory /workspace/31.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/31.rom_ctrl_corrupt_sig_fatal_chk.2894606895
Short name T113
Test name
Test status
Simulation time 88190789042 ps
CPU time 209.01 seconds
Started Apr 25 12:37:19 PM PDT 24
Finished Apr 25 12:40:51 PM PDT 24
Peak memory 228820 kb
Host smart-6abf4585-ba5a-4b0c-bcc4-e37d17c51493
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2894606895 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_
corrupt_sig_fatal_chk.2894606895
Directory /workspace/31.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/31.rom_ctrl_kmac_err_chk.142775417
Short name T255
Test name
Test status
Simulation time 1368688979 ps
CPU time 14.07 seconds
Started Apr 25 12:37:16 PM PDT 24
Finished Apr 25 12:37:34 PM PDT 24
Peak memory 212060 kb
Host smart-c476a125-fd26-45c4-a400-04e93b97507d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=142775417 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_kmac_err_chk.142775417
Directory /workspace/31.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/31.rom_ctrl_max_throughput_chk.135029823
Short name T295
Test name
Test status
Simulation time 5503083409 ps
CPU time 14.18 seconds
Started Apr 25 12:37:06 PM PDT 24
Finished Apr 25 12:37:23 PM PDT 24
Peak memory 211368 kb
Host smart-acafe033-e27d-4776-b0eb-3ee50756ae28
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=135029823 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_max_throughput_chk.135029823
Directory /workspace/31.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/31.rom_ctrl_smoke.1523205059
Short name T307
Test name
Test status
Simulation time 347986937 ps
CPU time 12.69 seconds
Started Apr 25 12:37:18 PM PDT 24
Finished Apr 25 12:37:34 PM PDT 24
Peak memory 219432 kb
Host smart-7240eb7f-5921-4ab8-805e-9dbdfc25ac32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1523205059 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_smoke.1523205059
Directory /workspace/31.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/31.rom_ctrl_stress_all.1957649563
Short name T11
Test name
Test status
Simulation time 10821167423 ps
CPU time 44.58 seconds
Started Apr 25 12:37:18 PM PDT 24
Finished Apr 25 12:38:05 PM PDT 24
Peak memory 219520 kb
Host smart-dc2af858-a1a8-4fbe-8fbb-19fc0502352f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1957649563 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 31.rom_ctrl_stress_all.1957649563
Directory /workspace/31.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/31.rom_ctrl_stress_all_with_rand_reset.3233754965
Short name T39
Test name
Test status
Simulation time 310462688717 ps
CPU time 7681.03 seconds
Started Apr 25 12:37:14 PM PDT 24
Finished Apr 25 02:45:18 PM PDT 24
Peak memory 244280 kb
Host smart-d750c549-f12d-4d72-acde-812d9f81fed7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3233754965 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_stress_all_with_rand_reset.3233754965
Directory /workspace/31.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.rom_ctrl_alert_test.590817553
Short name T34
Test name
Test status
Simulation time 1744535833 ps
CPU time 14.3 seconds
Started Apr 25 12:37:18 PM PDT 24
Finished Apr 25 12:37:36 PM PDT 24
Peak memory 211352 kb
Host smart-3d29df0d-c3a0-4557-9f62-7f402499356d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=590817553 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_alert_test.590817553
Directory /workspace/32.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/32.rom_ctrl_corrupt_sig_fatal_chk.2457320784
Short name T357
Test name
Test status
Simulation time 3695949988 ps
CPU time 136.48 seconds
Started Apr 25 12:37:16 PM PDT 24
Finished Apr 25 12:39:35 PM PDT 24
Peak memory 238336 kb
Host smart-37039fcd-b1f3-45f9-af7f-88b123a39e89
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2457320784 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_
corrupt_sig_fatal_chk.2457320784
Directory /workspace/32.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/32.rom_ctrl_kmac_err_chk.730354526
Short name T124
Test name
Test status
Simulation time 9190101838 ps
CPU time 31.19 seconds
Started Apr 25 12:37:20 PM PDT 24
Finished Apr 25 12:37:55 PM PDT 24
Peak memory 211620 kb
Host smart-1d790c39-e4a3-4b83-a5ab-b51e90872d88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=730354526 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_kmac_err_chk.730354526
Directory /workspace/32.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/32.rom_ctrl_max_throughput_chk.3563514226
Short name T53
Test name
Test status
Simulation time 375109253 ps
CPU time 5.37 seconds
Started Apr 25 12:37:36 PM PDT 24
Finished Apr 25 12:37:43 PM PDT 24
Peak memory 211340 kb
Host smart-4b657ca4-979c-4d9c-acdf-e6768063125b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3563514226 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_max_throughput_chk.3563514226
Directory /workspace/32.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/32.rom_ctrl_smoke.2521160103
Short name T186
Test name
Test status
Simulation time 1414565365 ps
CPU time 17.41 seconds
Started Apr 25 12:37:21 PM PDT 24
Finished Apr 25 12:37:41 PM PDT 24
Peak memory 219560 kb
Host smart-275a186c-c062-4360-815a-3c1e98fae4d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2521160103 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_smoke.2521160103
Directory /workspace/32.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/32.rom_ctrl_stress_all.3993783001
Short name T268
Test name
Test status
Simulation time 1144351853 ps
CPU time 20.9 seconds
Started Apr 25 12:37:25 PM PDT 24
Finished Apr 25 12:37:49 PM PDT 24
Peak memory 216444 kb
Host smart-6ec3c2e9-94e1-4b76-bd5c-eca8e7c1d8ed
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3993783001 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 32.rom_ctrl_stress_all.3993783001
Directory /workspace/32.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/32.rom_ctrl_stress_all_with_rand_reset.2561614436
Short name T346
Test name
Test status
Simulation time 70452739338 ps
CPU time 1243.08 seconds
Started Apr 25 12:37:28 PM PDT 24
Finished Apr 25 12:58:13 PM PDT 24
Peak memory 232000 kb
Host smart-46f23ee9-bfe8-420f-96fe-39b11fea745a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2561614436 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_stress_all_with_rand_reset.2561614436
Directory /workspace/32.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.rom_ctrl_alert_test.1373441250
Short name T218
Test name
Test status
Simulation time 3943939935 ps
CPU time 11.18 seconds
Started Apr 25 12:37:20 PM PDT 24
Finished Apr 25 12:37:35 PM PDT 24
Peak memory 211516 kb
Host smart-f812c867-c159-40a0-9286-aa60946e4c73
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1373441250 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_alert_test.1373441250
Directory /workspace/33.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/33.rom_ctrl_corrupt_sig_fatal_chk.3823760828
Short name T38
Test name
Test status
Simulation time 4644037422 ps
CPU time 71.35 seconds
Started Apr 25 12:37:18 PM PDT 24
Finished Apr 25 12:38:33 PM PDT 24
Peak memory 236840 kb
Host smart-e72a044b-331e-4ec4-8c15-72c43d5b7719
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3823760828 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_
corrupt_sig_fatal_chk.3823760828
Directory /workspace/33.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/33.rom_ctrl_kmac_err_chk.3076994174
Short name T16
Test name
Test status
Simulation time 334305830 ps
CPU time 9.42 seconds
Started Apr 25 12:37:07 PM PDT 24
Finished Apr 25 12:37:20 PM PDT 24
Peak memory 211924 kb
Host smart-ff348295-21ae-4853-a4ff-348ef423936e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3076994174 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_kmac_err_chk.3076994174
Directory /workspace/33.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/33.rom_ctrl_max_throughput_chk.4003090129
Short name T190
Test name
Test status
Simulation time 1978954441 ps
CPU time 16.57 seconds
Started Apr 25 12:37:12 PM PDT 24
Finished Apr 25 12:37:32 PM PDT 24
Peak memory 211332 kb
Host smart-9ff7776d-5832-4fb9-aab9-28bbdf5af127
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4003090129 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_max_throughput_chk.4003090129
Directory /workspace/33.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/33.rom_ctrl_smoke.622842855
Short name T239
Test name
Test status
Simulation time 22120644775 ps
CPU time 34.56 seconds
Started Apr 25 12:37:26 PM PDT 24
Finished Apr 25 12:38:03 PM PDT 24
Peak memory 219556 kb
Host smart-527a6623-6c04-4073-8e99-5ec44fc7baba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=622842855 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_smoke.622842855
Directory /workspace/33.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/33.rom_ctrl_stress_all.1152719953
Short name T140
Test name
Test status
Simulation time 14672072447 ps
CPU time 50.86 seconds
Started Apr 25 12:37:14 PM PDT 24
Finished Apr 25 12:38:07 PM PDT 24
Peak memory 219560 kb
Host smart-9a431212-fa02-429f-a111-1fd30762dcaa
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1152719953 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 33.rom_ctrl_stress_all.1152719953
Directory /workspace/33.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/34.rom_ctrl_alert_test.3996708792
Short name T322
Test name
Test status
Simulation time 1292687134 ps
CPU time 8.49 seconds
Started Apr 25 12:37:18 PM PDT 24
Finished Apr 25 12:37:30 PM PDT 24
Peak memory 211340 kb
Host smart-8f97548e-b173-439f-b257-2a4a72692812
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3996708792 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_alert_test.3996708792
Directory /workspace/34.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/34.rom_ctrl_corrupt_sig_fatal_chk.2240521953
Short name T25
Test name
Test status
Simulation time 12248948603 ps
CPU time 116.04 seconds
Started Apr 25 12:37:19 PM PDT 24
Finished Apr 25 12:39:18 PM PDT 24
Peak memory 227888 kb
Host smart-d8c18e49-252f-4db2-8aae-5c44f07da8a1
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2240521953 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_
corrupt_sig_fatal_chk.2240521953
Directory /workspace/34.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/34.rom_ctrl_kmac_err_chk.2243135952
Short name T161
Test name
Test status
Simulation time 695680375 ps
CPU time 9.55 seconds
Started Apr 25 12:37:20 PM PDT 24
Finished Apr 25 12:37:33 PM PDT 24
Peak memory 212512 kb
Host smart-44edc909-18bc-4c79-8977-67457b89346d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2243135952 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_kmac_err_chk.2243135952
Directory /workspace/34.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/34.rom_ctrl_max_throughput_chk.2082481317
Short name T175
Test name
Test status
Simulation time 100703009 ps
CPU time 5.49 seconds
Started Apr 25 12:37:07 PM PDT 24
Finished Apr 25 12:37:15 PM PDT 24
Peak memory 211276 kb
Host smart-2c656a2f-7e1f-4ee3-9c7f-26326fd16605
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2082481317 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_max_throughput_chk.2082481317
Directory /workspace/34.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/34.rom_ctrl_smoke.2411174865
Short name T330
Test name
Test status
Simulation time 1726857893 ps
CPU time 20.95 seconds
Started Apr 25 12:37:14 PM PDT 24
Finished Apr 25 12:37:38 PM PDT 24
Peak memory 219592 kb
Host smart-bb3a2606-047f-4595-ae2b-b15c3c91a86f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2411174865 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_smoke.2411174865
Directory /workspace/34.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/34.rom_ctrl_stress_all.3255440817
Short name T278
Test name
Test status
Simulation time 5336046760 ps
CPU time 45.8 seconds
Started Apr 25 12:37:22 PM PDT 24
Finished Apr 25 12:38:10 PM PDT 24
Peak memory 213668 kb
Host smart-97fe092f-f5d3-4370-b3f3-7756df856267
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3255440817 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 34.rom_ctrl_stress_all.3255440817
Directory /workspace/34.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/35.rom_ctrl_alert_test.465075509
Short name T360
Test name
Test status
Simulation time 334110583 ps
CPU time 6.56 seconds
Started Apr 25 12:37:18 PM PDT 24
Finished Apr 25 12:37:27 PM PDT 24
Peak memory 211324 kb
Host smart-a803e69c-454a-44fa-825f-acd45ffe5ec8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=465075509 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_alert_test.465075509
Directory /workspace/35.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/35.rom_ctrl_kmac_err_chk.1624750515
Short name T137
Test name
Test status
Simulation time 348405745 ps
CPU time 11.61 seconds
Started Apr 25 12:37:16 PM PDT 24
Finished Apr 25 12:37:31 PM PDT 24
Peak memory 212192 kb
Host smart-405a5662-22b6-46f9-a46b-bea87a8e0442
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1624750515 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_kmac_err_chk.1624750515
Directory /workspace/35.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/35.rom_ctrl_max_throughput_chk.3228956331
Short name T174
Test name
Test status
Simulation time 4613646025 ps
CPU time 12.27 seconds
Started Apr 25 12:37:08 PM PDT 24
Finished Apr 25 12:37:23 PM PDT 24
Peak memory 211376 kb
Host smart-5755bb93-fd07-43b2-b2bf-13826291726b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3228956331 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_max_throughput_chk.3228956331
Directory /workspace/35.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/35.rom_ctrl_smoke.4285250636
Short name T179
Test name
Test status
Simulation time 2166041586 ps
CPU time 22.54 seconds
Started Apr 25 12:37:11 PM PDT 24
Finished Apr 25 12:37:36 PM PDT 24
Peak memory 219640 kb
Host smart-3fafa88f-da9d-4030-9e74-f3e5fae1e868
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4285250636 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_smoke.4285250636
Directory /workspace/35.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/35.rom_ctrl_stress_all.3551226608
Short name T281
Test name
Test status
Simulation time 203472276 ps
CPU time 7.53 seconds
Started Apr 25 12:37:19 PM PDT 24
Finished Apr 25 12:37:30 PM PDT 24
Peak memory 212068 kb
Host smart-50ee18b5-9ee2-4dbd-9a47-1d5177d7d615
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3551226608 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 35.rom_ctrl_stress_all.3551226608
Directory /workspace/35.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/36.rom_ctrl_alert_test.594522077
Short name T172
Test name
Test status
Simulation time 1535392795 ps
CPU time 13.08 seconds
Started Apr 25 12:37:16 PM PDT 24
Finished Apr 25 12:37:33 PM PDT 24
Peak memory 211360 kb
Host smart-f43cfccc-aecb-4c42-90b4-a5d17acccb4d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=594522077 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_alert_test.594522077
Directory /workspace/36.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/36.rom_ctrl_corrupt_sig_fatal_chk.2525056428
Short name T119
Test name
Test status
Simulation time 34994612675 ps
CPU time 302.07 seconds
Started Apr 25 12:37:11 PM PDT 24
Finished Apr 25 12:42:16 PM PDT 24
Peak memory 231196 kb
Host smart-a9324ef2-6efb-4d20-a0c4-c491233db82d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2525056428 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_
corrupt_sig_fatal_chk.2525056428
Directory /workspace/36.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/36.rom_ctrl_kmac_err_chk.1372833161
Short name T169
Test name
Test status
Simulation time 768804968 ps
CPU time 14.26 seconds
Started Apr 25 12:37:06 PM PDT 24
Finished Apr 25 12:37:21 PM PDT 24
Peak memory 212056 kb
Host smart-a42cafac-9edb-492f-80b5-4b72f72af565
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1372833161 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_kmac_err_chk.1372833161
Directory /workspace/36.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/36.rom_ctrl_max_throughput_chk.832941746
Short name T205
Test name
Test status
Simulation time 94385289 ps
CPU time 5.62 seconds
Started Apr 25 12:37:24 PM PDT 24
Finished Apr 25 12:37:32 PM PDT 24
Peak memory 211280 kb
Host smart-c2a50896-3493-4624-98d1-6eb91dfa6519
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=832941746 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_max_throughput_chk.832941746
Directory /workspace/36.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/36.rom_ctrl_smoke.3421733326
Short name T203
Test name
Test status
Simulation time 1555952022 ps
CPU time 19.58 seconds
Started Apr 25 12:37:18 PM PDT 24
Finished Apr 25 12:37:41 PM PDT 24
Peak memory 213036 kb
Host smart-c8549ef7-3f14-4bd2-949d-16708c0f3793
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3421733326 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_smoke.3421733326
Directory /workspace/36.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/36.rom_ctrl_stress_all.3469813585
Short name T158
Test name
Test status
Simulation time 35107244576 ps
CPU time 72.64 seconds
Started Apr 25 12:37:16 PM PDT 24
Finished Apr 25 12:38:31 PM PDT 24
Peak memory 219560 kb
Host smart-0db42af4-8f0d-49fd-a984-5e63d22e99d4
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3469813585 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 36.rom_ctrl_stress_all.3469813585
Directory /workspace/36.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/37.rom_ctrl_alert_test.695030855
Short name T329
Test name
Test status
Simulation time 1714576470 ps
CPU time 14.49 seconds
Started Apr 25 12:37:18 PM PDT 24
Finished Apr 25 12:37:35 PM PDT 24
Peak memory 211364 kb
Host smart-0fb98e9a-e953-4ead-8d81-c0a6a4e33cf5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=695030855 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_alert_test.695030855
Directory /workspace/37.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/37.rom_ctrl_corrupt_sig_fatal_chk.1888133559
Short name T229
Test name
Test status
Simulation time 36616797228 ps
CPU time 115.8 seconds
Started Apr 25 12:37:24 PM PDT 24
Finished Apr 25 12:39:23 PM PDT 24
Peak memory 232848 kb
Host smart-c18da8bb-13f6-4fa4-8c20-99dd2858cd66
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1888133559 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_
corrupt_sig_fatal_chk.1888133559
Directory /workspace/37.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/37.rom_ctrl_kmac_err_chk.261553724
Short name T170
Test name
Test status
Simulation time 16023719418 ps
CPU time 28.22 seconds
Started Apr 25 12:37:16 PM PDT 24
Finished Apr 25 12:37:48 PM PDT 24
Peak memory 212260 kb
Host smart-ce8cb1fe-40ee-4b74-a3a3-5cdf480d8de3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=261553724 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_kmac_err_chk.261553724
Directory /workspace/37.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/37.rom_ctrl_max_throughput_chk.1372171764
Short name T275
Test name
Test status
Simulation time 4147156975 ps
CPU time 11.18 seconds
Started Apr 25 12:37:12 PM PDT 24
Finished Apr 25 12:37:26 PM PDT 24
Peak memory 211396 kb
Host smart-34619815-55fb-4f19-8559-97844a9ee121
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1372171764 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_max_throughput_chk.1372171764
Directory /workspace/37.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/37.rom_ctrl_smoke.3692797315
Short name T343
Test name
Test status
Simulation time 7242473500 ps
CPU time 20.49 seconds
Started Apr 25 12:37:14 PM PDT 24
Finished Apr 25 12:37:37 PM PDT 24
Peak memory 214056 kb
Host smart-2b77c9a0-682f-4f94-a290-f0880db25fae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3692797315 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_smoke.3692797315
Directory /workspace/37.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/37.rom_ctrl_stress_all.3058122285
Short name T173
Test name
Test status
Simulation time 10310765720 ps
CPU time 49.74 seconds
Started Apr 25 12:37:36 PM PDT 24
Finished Apr 25 12:38:27 PM PDT 24
Peak memory 219568 kb
Host smart-b542072e-a20f-47bb-988d-2e8cb0684ee9
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3058122285 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 37.rom_ctrl_stress_all.3058122285
Directory /workspace/37.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/38.rom_ctrl_alert_test.2700023336
Short name T215
Test name
Test status
Simulation time 1281135215 ps
CPU time 7.11 seconds
Started Apr 25 12:37:20 PM PDT 24
Finished Apr 25 12:37:30 PM PDT 24
Peak memory 211380 kb
Host smart-45cdb11d-e70d-4d45-ba38-d7f975e91d7e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2700023336 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_alert_test.2700023336
Directory /workspace/38.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/38.rom_ctrl_corrupt_sig_fatal_chk.2765272191
Short name T217
Test name
Test status
Simulation time 16004507999 ps
CPU time 188.98 seconds
Started Apr 25 12:37:26 PM PDT 24
Finished Apr 25 12:40:38 PM PDT 24
Peak memory 240124 kb
Host smart-87a82306-d6cc-4865-ba6f-021bb5357f64
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2765272191 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_
corrupt_sig_fatal_chk.2765272191
Directory /workspace/38.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/38.rom_ctrl_kmac_err_chk.3065514112
Short name T202
Test name
Test status
Simulation time 10977559289 ps
CPU time 13.35 seconds
Started Apr 25 12:37:32 PM PDT 24
Finished Apr 25 12:37:46 PM PDT 24
Peak memory 212260 kb
Host smart-5aacc652-3b87-45ff-871b-4944c26386dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3065514112 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_kmac_err_chk.3065514112
Directory /workspace/38.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/38.rom_ctrl_max_throughput_chk.1651499425
Short name T235
Test name
Test status
Simulation time 373223136 ps
CPU time 5.6 seconds
Started Apr 25 12:37:37 PM PDT 24
Finished Apr 25 12:37:44 PM PDT 24
Peak memory 211304 kb
Host smart-e8a3ff1c-7217-4b51-bb06-6382b8b1a27a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1651499425 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_max_throughput_chk.1651499425
Directory /workspace/38.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/38.rom_ctrl_smoke.764116472
Short name T12
Test name
Test status
Simulation time 2908835029 ps
CPU time 29.77 seconds
Started Apr 25 12:37:19 PM PDT 24
Finished Apr 25 12:37:53 PM PDT 24
Peak memory 219624 kb
Host smart-3d17539b-24a1-4cea-880b-e762d156dcd3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=764116472 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_smoke.764116472
Directory /workspace/38.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/38.rom_ctrl_stress_all.203609772
Short name T314
Test name
Test status
Simulation time 14792119371 ps
CPU time 66.72 seconds
Started Apr 25 12:37:39 PM PDT 24
Finished Apr 25 12:38:47 PM PDT 24
Peak memory 219604 kb
Host smart-780c3387-a6df-4e84-ad9b-89dfc3c9ad94
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=203609772 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 38.rom_ctrl_stress_all.203609772
Directory /workspace/38.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/39.rom_ctrl_alert_test.2041163687
Short name T263
Test name
Test status
Simulation time 987300102 ps
CPU time 6.24 seconds
Started Apr 25 12:37:32 PM PDT 24
Finished Apr 25 12:37:39 PM PDT 24
Peak memory 211380 kb
Host smart-016697dd-6d6d-49f9-b72e-dac24b5676fe
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2041163687 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_alert_test.2041163687
Directory /workspace/39.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/39.rom_ctrl_corrupt_sig_fatal_chk.2044926702
Short name T293
Test name
Test status
Simulation time 9313122753 ps
CPU time 156.12 seconds
Started Apr 25 12:37:24 PM PDT 24
Finished Apr 25 12:40:01 PM PDT 24
Peak memory 230964 kb
Host smart-33e68e2e-c49c-4b53-9cb0-7c76c7c83886
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2044926702 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_
corrupt_sig_fatal_chk.2044926702
Directory /workspace/39.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/39.rom_ctrl_kmac_err_chk.1259262403
Short name T131
Test name
Test status
Simulation time 14770339737 ps
CPU time 23.23 seconds
Started Apr 25 12:37:16 PM PDT 24
Finished Apr 25 12:37:43 PM PDT 24
Peak memory 212344 kb
Host smart-cefc58ea-cae1-47a8-97d9-a34dd54ca49a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1259262403 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_kmac_err_chk.1259262403
Directory /workspace/39.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/39.rom_ctrl_max_throughput_chk.2703829348
Short name T319
Test name
Test status
Simulation time 1976786802 ps
CPU time 16.43 seconds
Started Apr 25 12:37:21 PM PDT 24
Finished Apr 25 12:37:40 PM PDT 24
Peak memory 211320 kb
Host smart-eb26f38c-12f4-410a-92e1-21076152f4c5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2703829348 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_max_throughput_chk.2703829348
Directory /workspace/39.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/39.rom_ctrl_smoke.647894380
Short name T310
Test name
Test status
Simulation time 7699894606 ps
CPU time 29.47 seconds
Started Apr 25 12:37:25 PM PDT 24
Finished Apr 25 12:37:58 PM PDT 24
Peak memory 214688 kb
Host smart-85a3fca4-d1f3-4d22-b186-3e5d7a1edcf6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=647894380 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_smoke.647894380
Directory /workspace/39.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/39.rom_ctrl_stress_all.2130000086
Short name T271
Test name
Test status
Simulation time 606724960 ps
CPU time 5.84 seconds
Started Apr 25 12:37:12 PM PDT 24
Finished Apr 25 12:37:21 PM PDT 24
Peak memory 211360 kb
Host smart-bdb89754-7047-4dfc-8890-13b37501dedc
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2130000086 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 39.rom_ctrl_stress_all.2130000086
Directory /workspace/39.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/4.rom_ctrl_alert_test.1632825062
Short name T232
Test name
Test status
Simulation time 4269657767 ps
CPU time 10.31 seconds
Started Apr 25 12:36:58 PM PDT 24
Finished Apr 25 12:37:11 PM PDT 24
Peak memory 211428 kb
Host smart-98093ae4-71cd-4103-9ade-1eea9fed5224
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1632825062 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_alert_test.1632825062
Directory /workspace/4.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/4.rom_ctrl_corrupt_sig_fatal_chk.852780191
Short name T15
Test name
Test status
Simulation time 3096793750 ps
CPU time 142.7 seconds
Started Apr 25 12:36:55 PM PDT 24
Finished Apr 25 12:39:19 PM PDT 24
Peak memory 231028 kb
Host smart-5ba755db-cb59-41f6-95df-816e732ebbd7
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=852780191 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_co
rrupt_sig_fatal_chk.852780191
Directory /workspace/4.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/4.rom_ctrl_kmac_err_chk.2348613667
Short name T296
Test name
Test status
Simulation time 340126331 ps
CPU time 9.55 seconds
Started Apr 25 12:37:05 PM PDT 24
Finished Apr 25 12:37:17 PM PDT 24
Peak memory 212164 kb
Host smart-d8bcbfd4-39f6-4f5f-9df2-3a581a708bb1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2348613667 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_kmac_err_chk.2348613667
Directory /workspace/4.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/4.rom_ctrl_max_throughput_chk.3785211958
Short name T309
Test name
Test status
Simulation time 640894486 ps
CPU time 9.49 seconds
Started Apr 25 12:37:03 PM PDT 24
Finished Apr 25 12:37:14 PM PDT 24
Peak memory 211276 kb
Host smart-88cd055b-a12c-4d5a-9e0e-e91278f2fe2c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3785211958 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_max_throughput_chk.3785211958
Directory /workspace/4.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/4.rom_ctrl_sec_cm.2592865015
Short name T7
Test name
Test status
Simulation time 4628977085 ps
CPU time 119.54 seconds
Started Apr 25 12:36:45 PM PDT 24
Finished Apr 25 12:38:46 PM PDT 24
Peak memory 246732 kb
Host smart-9ad77db1-0c05-437a-867e-de41e17d3380
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2592865015 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_sec_cm.2592865015
Directory /workspace/4.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/4.rom_ctrl_smoke.636783038
Short name T197
Test name
Test status
Simulation time 5164663597 ps
CPU time 20.44 seconds
Started Apr 25 12:36:51 PM PDT 24
Finished Apr 25 12:37:13 PM PDT 24
Peak memory 213532 kb
Host smart-c5b52305-9562-44a8-b9f3-05ee4d6a5be6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=636783038 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_smoke.636783038
Directory /workspace/4.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/4.rom_ctrl_stress_all.3176926855
Short name T121
Test name
Test status
Simulation time 1327781276 ps
CPU time 16.26 seconds
Started Apr 25 12:36:59 PM PDT 24
Finished Apr 25 12:37:17 PM PDT 24
Peak memory 211172 kb
Host smart-e1726694-2892-4592-b9db-f2c99bd921b3
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3176926855 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 4.rom_ctrl_stress_all.3176926855
Directory /workspace/4.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/40.rom_ctrl_alert_test.349982464
Short name T325
Test name
Test status
Simulation time 1491591385 ps
CPU time 12.42 seconds
Started Apr 25 12:37:18 PM PDT 24
Finished Apr 25 12:37:34 PM PDT 24
Peak memory 211344 kb
Host smart-edbd4f2d-e953-4d35-961d-cd750a5f2d69
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=349982464 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_alert_test.349982464
Directory /workspace/40.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/40.rom_ctrl_kmac_err_chk.461461774
Short name T260
Test name
Test status
Simulation time 17091756868 ps
CPU time 32.28 seconds
Started Apr 25 12:37:37 PM PDT 24
Finished Apr 25 12:38:11 PM PDT 24
Peak memory 219648 kb
Host smart-a28a5332-2bd4-4c79-a404-68a46b4fe494
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=461461774 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_kmac_err_chk.461461774
Directory /workspace/40.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/40.rom_ctrl_max_throughput_chk.1249884382
Short name T178
Test name
Test status
Simulation time 8188021347 ps
CPU time 11.35 seconds
Started Apr 25 12:37:19 PM PDT 24
Finished Apr 25 12:37:34 PM PDT 24
Peak memory 211372 kb
Host smart-163d4c6f-0252-49cd-8f80-d343b846976d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1249884382 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_max_throughput_chk.1249884382
Directory /workspace/40.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/40.rom_ctrl_smoke.2093628617
Short name T342
Test name
Test status
Simulation time 2146593736 ps
CPU time 25.34 seconds
Started Apr 25 12:37:40 PM PDT 24
Finished Apr 25 12:38:06 PM PDT 24
Peak memory 219620 kb
Host smart-ef69538c-3548-42a7-aed3-f3e157a5c9b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2093628617 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_smoke.2093628617
Directory /workspace/40.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/40.rom_ctrl_stress_all.3220812988
Short name T106
Test name
Test status
Simulation time 15853372905 ps
CPU time 34.8 seconds
Started Apr 25 12:37:18 PM PDT 24
Finished Apr 25 12:37:56 PM PDT 24
Peak memory 219524 kb
Host smart-1cb5394d-f8f4-490f-a1a0-04f316b8fed4
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3220812988 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 40.rom_ctrl_stress_all.3220812988
Directory /workspace/40.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/40.rom_ctrl_stress_all_with_rand_reset.845998260
Short name T40
Test name
Test status
Simulation time 87572830797 ps
CPU time 8750.18 seconds
Started Apr 25 12:37:25 PM PDT 24
Finished Apr 25 03:03:18 PM PDT 24
Peak memory 236016 kb
Host smart-385c0880-fbd7-4e1f-8d92-071be5e91b90
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=845998260 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_stress_all_with_rand_reset.845998260
Directory /workspace/40.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.rom_ctrl_alert_test.3890270878
Short name T208
Test name
Test status
Simulation time 346707718 ps
CPU time 4.2 seconds
Started Apr 25 12:37:27 PM PDT 24
Finished Apr 25 12:37:34 PM PDT 24
Peak memory 211368 kb
Host smart-cd56d7cf-6dcf-4cac-accc-2dfd97a7ecd8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3890270878 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_alert_test.3890270878
Directory /workspace/41.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/41.rom_ctrl_corrupt_sig_fatal_chk.2282945788
Short name T134
Test name
Test status
Simulation time 37838147856 ps
CPU time 130.03 seconds
Started Apr 25 12:37:26 PM PDT 24
Finished Apr 25 12:39:39 PM PDT 24
Peak memory 228504 kb
Host smart-b19e7879-5a78-41a5-9d17-0e7293f8d358
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2282945788 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_
corrupt_sig_fatal_chk.2282945788
Directory /workspace/41.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/41.rom_ctrl_kmac_err_chk.1666300565
Short name T24
Test name
Test status
Simulation time 1966162690 ps
CPU time 20.22 seconds
Started Apr 25 12:37:31 PM PDT 24
Finished Apr 25 12:37:52 PM PDT 24
Peak memory 211952 kb
Host smart-4b03cce7-07f8-4d1f-a515-f86e0a462cb8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1666300565 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_kmac_err_chk.1666300565
Directory /workspace/41.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/41.rom_ctrl_max_throughput_chk.373416431
Short name T238
Test name
Test status
Simulation time 9036825063 ps
CPU time 15.32 seconds
Started Apr 25 12:37:25 PM PDT 24
Finished Apr 25 12:37:43 PM PDT 24
Peak memory 211368 kb
Host smart-eb58e389-fdd5-4a7c-854c-bc276565e593
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=373416431 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_max_throughput_chk.373416431
Directory /workspace/41.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/41.rom_ctrl_smoke.1944434213
Short name T192
Test name
Test status
Simulation time 11623654969 ps
CPU time 26.63 seconds
Started Apr 25 12:37:27 PM PDT 24
Finished Apr 25 12:37:56 PM PDT 24
Peak memory 214020 kb
Host smart-2599d4b2-2f1f-4202-8631-be384ee45edb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1944434213 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_smoke.1944434213
Directory /workspace/41.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/41.rom_ctrl_stress_all.2331787579
Short name T341
Test name
Test status
Simulation time 4992728683 ps
CPU time 20.45 seconds
Started Apr 25 12:37:36 PM PDT 24
Finished Apr 25 12:37:58 PM PDT 24
Peak memory 213840 kb
Host smart-ce08d1fd-d8c7-4266-ac54-83c3e276e6ca
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2331787579 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 41.rom_ctrl_stress_all.2331787579
Directory /workspace/41.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/41.rom_ctrl_stress_all_with_rand_reset.2286072561
Short name T28
Test name
Test status
Simulation time 104554906811 ps
CPU time 1993.01 seconds
Started Apr 25 12:37:32 PM PDT 24
Finished Apr 25 01:10:47 PM PDT 24
Peak memory 232552 kb
Host smart-005c767a-21bc-433f-a40f-07e00d813512
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2286072561 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_stress_all_with_rand_reset.2286072561
Directory /workspace/41.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.rom_ctrl_alert_test.1193089297
Short name T177
Test name
Test status
Simulation time 870960461 ps
CPU time 9.9 seconds
Started Apr 25 12:37:14 PM PDT 24
Finished Apr 25 12:37:26 PM PDT 24
Peak memory 211352 kb
Host smart-f3df1d29-69a9-4131-9387-4c0b11c72266
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1193089297 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_alert_test.1193089297
Directory /workspace/42.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/42.rom_ctrl_corrupt_sig_fatal_chk.4158817949
Short name T233
Test name
Test status
Simulation time 1750854351 ps
CPU time 99.88 seconds
Started Apr 25 12:37:26 PM PDT 24
Finished Apr 25 12:39:09 PM PDT 24
Peak memory 212580 kb
Host smart-8d737de0-582c-46e4-afbb-f69848f4a25e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4158817949 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_
corrupt_sig_fatal_chk.4158817949
Directory /workspace/42.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/42.rom_ctrl_kmac_err_chk.855450440
Short name T249
Test name
Test status
Simulation time 348829733 ps
CPU time 9.08 seconds
Started Apr 25 12:37:20 PM PDT 24
Finished Apr 25 12:37:32 PM PDT 24
Peak memory 211852 kb
Host smart-9d21b5d1-3ec0-47aa-980e-0c675bd40aff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=855450440 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_kmac_err_chk.855450440
Directory /workspace/42.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/42.rom_ctrl_max_throughput_chk.4047454714
Short name T210
Test name
Test status
Simulation time 687540783 ps
CPU time 9.86 seconds
Started Apr 25 12:37:14 PM PDT 24
Finished Apr 25 12:37:26 PM PDT 24
Peak memory 211332 kb
Host smart-ff994b41-c488-4ab3-88b1-cab9043421ef
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4047454714 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_max_throughput_chk.4047454714
Directory /workspace/42.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/42.rom_ctrl_smoke.2459618139
Short name T162
Test name
Test status
Simulation time 1492484218 ps
CPU time 18.98 seconds
Started Apr 25 12:37:26 PM PDT 24
Finished Apr 25 12:37:48 PM PDT 24
Peak memory 213464 kb
Host smart-98505415-7756-4314-90d6-49109d57f1b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2459618139 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_smoke.2459618139
Directory /workspace/42.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/42.rom_ctrl_stress_all.1693934273
Short name T299
Test name
Test status
Simulation time 6811373828 ps
CPU time 79.84 seconds
Started Apr 25 12:37:17 PM PDT 24
Finished Apr 25 12:38:40 PM PDT 24
Peak memory 219560 kb
Host smart-438bb622-c582-4968-9ba6-5950421d5ac2
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1693934273 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 42.rom_ctrl_stress_all.1693934273
Directory /workspace/42.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/43.rom_ctrl_alert_test.3397398788
Short name T285
Test name
Test status
Simulation time 4775213115 ps
CPU time 10.95 seconds
Started Apr 25 12:37:18 PM PDT 24
Finished Apr 25 12:37:32 PM PDT 24
Peak memory 211404 kb
Host smart-69dd24c5-b88b-4bba-b89f-db558652669b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3397398788 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_alert_test.3397398788
Directory /workspace/43.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/43.rom_ctrl_corrupt_sig_fatal_chk.2250167642
Short name T132
Test name
Test status
Simulation time 2261310878 ps
CPU time 87.48 seconds
Started Apr 25 12:37:38 PM PDT 24
Finished Apr 25 12:39:07 PM PDT 24
Peak memory 211620 kb
Host smart-637ae6d7-3ca6-4c02-b37c-d95b851a48bb
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2250167642 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_
corrupt_sig_fatal_chk.2250167642
Directory /workspace/43.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/43.rom_ctrl_kmac_err_chk.76942281
Short name T23
Test name
Test status
Simulation time 13861365497 ps
CPU time 28.57 seconds
Started Apr 25 12:37:33 PM PDT 24
Finished Apr 25 12:38:03 PM PDT 24
Peak memory 212456 kb
Host smart-582c5330-e349-4cfc-8d03-0c250a98032a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=76942281 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_kmac_err_chk.76942281
Directory /workspace/43.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/43.rom_ctrl_max_throughput_chk.3143715249
Short name T279
Test name
Test status
Simulation time 447289919 ps
CPU time 7 seconds
Started Apr 25 12:37:34 PM PDT 24
Finished Apr 25 12:37:42 PM PDT 24
Peak memory 211208 kb
Host smart-00bc9996-5177-4309-99eb-b18668eef2eb
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3143715249 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_max_throughput_chk.3143715249
Directory /workspace/43.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/43.rom_ctrl_smoke.1596899426
Short name T188
Test name
Test status
Simulation time 2655541947 ps
CPU time 23.72 seconds
Started Apr 25 12:37:39 PM PDT 24
Finished Apr 25 12:38:04 PM PDT 24
Peak memory 213712 kb
Host smart-5da569fe-ec9c-4504-8151-d2700327286a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1596899426 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_smoke.1596899426
Directory /workspace/43.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/43.rom_ctrl_stress_all.1428508613
Short name T253
Test name
Test status
Simulation time 4534821419 ps
CPU time 20.84 seconds
Started Apr 25 12:38:02 PM PDT 24
Finished Apr 25 12:38:24 PM PDT 24
Peak memory 211232 kb
Host smart-de4a7f48-d30a-40b9-95e6-36e645c1c7dd
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1428508613 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 43.rom_ctrl_stress_all.1428508613
Directory /workspace/43.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/44.rom_ctrl_alert_test.549496997
Short name T243
Test name
Test status
Simulation time 1298499843 ps
CPU time 11.98 seconds
Started Apr 25 12:37:26 PM PDT 24
Finished Apr 25 12:37:45 PM PDT 24
Peak memory 211388 kb
Host smart-c3cb1b1c-d1b5-4081-bcab-db2cdbaf1ae8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=549496997 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_alert_test.549496997
Directory /workspace/44.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/44.rom_ctrl_corrupt_sig_fatal_chk.14669443
Short name T350
Test name
Test status
Simulation time 693237363481 ps
CPU time 465.41 seconds
Started Apr 25 12:37:32 PM PDT 24
Finished Apr 25 12:45:19 PM PDT 24
Peak memory 239232 kb
Host smart-6f921b4e-0e77-4e38-a2c8-07f226ce8a4e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14669443 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_
sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_co
rrupt_sig_fatal_chk.14669443
Directory /workspace/44.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/44.rom_ctrl_kmac_err_chk.3208179569
Short name T122
Test name
Test status
Simulation time 3682840080 ps
CPU time 31.93 seconds
Started Apr 25 12:37:25 PM PDT 24
Finished Apr 25 12:38:00 PM PDT 24
Peak memory 212024 kb
Host smart-86e63fb8-a312-47bd-8594-be12f311690e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3208179569 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_kmac_err_chk.3208179569
Directory /workspace/44.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/44.rom_ctrl_max_throughput_chk.759119453
Short name T269
Test name
Test status
Simulation time 384995252 ps
CPU time 5.36 seconds
Started Apr 25 12:37:24 PM PDT 24
Finished Apr 25 12:37:32 PM PDT 24
Peak memory 211332 kb
Host smart-eba4b7a4-293b-42c1-a01e-6f3e92d7cd7f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=759119453 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_max_throughput_chk.759119453
Directory /workspace/44.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/44.rom_ctrl_smoke.4065465288
Short name T195
Test name
Test status
Simulation time 7039165888 ps
CPU time 29.53 seconds
Started Apr 25 12:37:37 PM PDT 24
Finished Apr 25 12:38:08 PM PDT 24
Peak memory 214428 kb
Host smart-47cdb64a-fba3-4db9-b7ad-f180398c0efd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4065465288 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_smoke.4065465288
Directory /workspace/44.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/44.rom_ctrl_stress_all.2606322166
Short name T118
Test name
Test status
Simulation time 1795560659 ps
CPU time 18.08 seconds
Started Apr 25 12:37:42 PM PDT 24
Finished Apr 25 12:38:03 PM PDT 24
Peak memory 211268 kb
Host smart-8e63dc74-19a6-4d8a-a899-e19fda789960
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2606322166 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 44.rom_ctrl_stress_all.2606322166
Directory /workspace/44.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/45.rom_ctrl_alert_test.3617120915
Short name T50
Test name
Test status
Simulation time 3444416704 ps
CPU time 13.92 seconds
Started Apr 25 12:37:25 PM PDT 24
Finished Apr 25 12:37:42 PM PDT 24
Peak memory 211452 kb
Host smart-ba43ca8a-3106-413a-b03d-abc7b08d4362
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3617120915 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_alert_test.3617120915
Directory /workspace/45.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/45.rom_ctrl_corrupt_sig_fatal_chk.4176034410
Short name T327
Test name
Test status
Simulation time 182371435438 ps
CPU time 460.78 seconds
Started Apr 25 12:37:31 PM PDT 24
Finished Apr 25 12:45:13 PM PDT 24
Peak memory 235004 kb
Host smart-05d638cd-aac5-4012-b04a-0eb0c59e039b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4176034410 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_
corrupt_sig_fatal_chk.4176034410
Directory /workspace/45.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/45.rom_ctrl_kmac_err_chk.2636433414
Short name T267
Test name
Test status
Simulation time 7466872108 ps
CPU time 33.98 seconds
Started Apr 25 12:37:18 PM PDT 24
Finished Apr 25 12:37:55 PM PDT 24
Peak memory 212148 kb
Host smart-f6506ab3-df3b-474a-8ba0-a1aea01e96b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2636433414 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_kmac_err_chk.2636433414
Directory /workspace/45.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/45.rom_ctrl_max_throughput_chk.2453983555
Short name T261
Test name
Test status
Simulation time 2947046714 ps
CPU time 9.63 seconds
Started Apr 25 12:37:43 PM PDT 24
Finished Apr 25 12:37:56 PM PDT 24
Peak memory 211396 kb
Host smart-9adb1fe3-a33b-442b-bc95-3880f248cb39
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2453983555 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_max_throughput_chk.2453983555
Directory /workspace/45.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/45.rom_ctrl_smoke.1300287170
Short name T315
Test name
Test status
Simulation time 3805514764 ps
CPU time 23.19 seconds
Started Apr 25 12:37:37 PM PDT 24
Finished Apr 25 12:38:02 PM PDT 24
Peak memory 219652 kb
Host smart-eeebe11f-7152-49eb-8252-b6bcb7409b48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1300287170 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_smoke.1300287170
Directory /workspace/45.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/45.rom_ctrl_stress_all.3149489740
Short name T184
Test name
Test status
Simulation time 3930218558 ps
CPU time 15.92 seconds
Started Apr 25 12:37:28 PM PDT 24
Finished Apr 25 12:37:46 PM PDT 24
Peak memory 216464 kb
Host smart-2afe6a0b-8ecc-4018-b28e-e41111f130cb
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3149489740 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 45.rom_ctrl_stress_all.3149489740
Directory /workspace/45.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/46.rom_ctrl_alert_test.3122512492
Short name T139
Test name
Test status
Simulation time 880844567 ps
CPU time 9.67 seconds
Started Apr 25 12:37:27 PM PDT 24
Finished Apr 25 12:37:39 PM PDT 24
Peak memory 211472 kb
Host smart-d04116e6-61e0-4c62-a430-525ec7201867
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3122512492 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_alert_test.3122512492
Directory /workspace/46.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/46.rom_ctrl_corrupt_sig_fatal_chk.4252474348
Short name T185
Test name
Test status
Simulation time 29771644368 ps
CPU time 226.27 seconds
Started Apr 25 12:37:42 PM PDT 24
Finished Apr 25 12:41:32 PM PDT 24
Peak memory 228712 kb
Host smart-efe63f73-cfad-4a54-8644-f1ffd6cead36
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4252474348 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_
corrupt_sig_fatal_chk.4252474348
Directory /workspace/46.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/46.rom_ctrl_kmac_err_chk.1231762530
Short name T276
Test name
Test status
Simulation time 4671425171 ps
CPU time 25.75 seconds
Started Apr 25 12:37:32 PM PDT 24
Finished Apr 25 12:37:59 PM PDT 24
Peak memory 212648 kb
Host smart-9bbe0c76-6987-44ca-80fe-71e56ada7181
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1231762530 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_kmac_err_chk.1231762530
Directory /workspace/46.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/46.rom_ctrl_max_throughput_chk.900904672
Short name T248
Test name
Test status
Simulation time 1249627256 ps
CPU time 7.07 seconds
Started Apr 25 12:37:32 PM PDT 24
Finished Apr 25 12:37:41 PM PDT 24
Peak memory 211308 kb
Host smart-5405cc4f-72ac-43e7-8bd7-d41553ea1482
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=900904672 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_max_throughput_chk.900904672
Directory /workspace/46.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/46.rom_ctrl_smoke.4273998622
Short name T228
Test name
Test status
Simulation time 3523592988 ps
CPU time 29 seconds
Started Apr 25 12:37:13 PM PDT 24
Finished Apr 25 12:37:44 PM PDT 24
Peak memory 213960 kb
Host smart-0fd16d72-c28e-4f2a-82dc-e8947244aecf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4273998622 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_smoke.4273998622
Directory /workspace/46.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/46.rom_ctrl_stress_all.2867777021
Short name T191
Test name
Test status
Simulation time 1652802322 ps
CPU time 25.3 seconds
Started Apr 25 12:37:32 PM PDT 24
Finished Apr 25 12:37:58 PM PDT 24
Peak memory 215136 kb
Host smart-f9028464-c62c-4ce9-93b3-2f697fef5a0f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2867777021 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 46.rom_ctrl_stress_all.2867777021
Directory /workspace/46.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/47.rom_ctrl_alert_test.1177381438
Short name T164
Test name
Test status
Simulation time 1074599410 ps
CPU time 7.25 seconds
Started Apr 25 12:37:32 PM PDT 24
Finished Apr 25 12:37:40 PM PDT 24
Peak memory 211368 kb
Host smart-bd8edf64-7693-4eb3-9521-b60442aef7a5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1177381438 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_alert_test.1177381438
Directory /workspace/47.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/47.rom_ctrl_corrupt_sig_fatal_chk.353643684
Short name T358
Test name
Test status
Simulation time 77642099067 ps
CPU time 191.03 seconds
Started Apr 25 12:37:25 PM PDT 24
Finished Apr 25 12:40:38 PM PDT 24
Peak memory 225200 kb
Host smart-9dd6656e-cb10-4ca0-982e-df1f42cf077f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=353643684 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_c
orrupt_sig_fatal_chk.353643684
Directory /workspace/47.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/47.rom_ctrl_kmac_err_chk.4005574923
Short name T147
Test name
Test status
Simulation time 3689309088 ps
CPU time 29.35 seconds
Started Apr 25 12:37:21 PM PDT 24
Finished Apr 25 12:37:53 PM PDT 24
Peak memory 212104 kb
Host smart-032bdbdd-c8f2-46b5-b45d-58b56120297c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4005574923 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_kmac_err_chk.4005574923
Directory /workspace/47.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/47.rom_ctrl_max_throughput_chk.2558828749
Short name T108
Test name
Test status
Simulation time 1041481233 ps
CPU time 11.59 seconds
Started Apr 25 12:37:20 PM PDT 24
Finished Apr 25 12:37:35 PM PDT 24
Peak memory 211232 kb
Host smart-7bdaf9f9-e509-457e-8a2d-fce41f8dd0b0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2558828749 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_max_throughput_chk.2558828749
Directory /workspace/47.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/47.rom_ctrl_smoke.2917634093
Short name T355
Test name
Test status
Simulation time 708372610 ps
CPU time 15.28 seconds
Started Apr 25 12:37:28 PM PDT 24
Finished Apr 25 12:37:45 PM PDT 24
Peak memory 213676 kb
Host smart-a2af7a25-93c4-447a-8c71-8fe33d099a3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2917634093 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_smoke.2917634093
Directory /workspace/47.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/47.rom_ctrl_stress_all.524564055
Short name T259
Test name
Test status
Simulation time 8645786730 ps
CPU time 21.34 seconds
Started Apr 25 12:37:34 PM PDT 24
Finished Apr 25 12:37:56 PM PDT 24
Peak memory 219528 kb
Host smart-acda1a93-5df4-4f17-992c-58559041e0a8
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=524564055 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 47.rom_ctrl_stress_all.524564055
Directory /workspace/47.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/48.rom_ctrl_alert_test.108886869
Short name T256
Test name
Test status
Simulation time 1148984671 ps
CPU time 11.11 seconds
Started Apr 25 12:37:29 PM PDT 24
Finished Apr 25 12:37:42 PM PDT 24
Peak memory 211388 kb
Host smart-42679de7-20f5-42d2-a169-42be33a25e34
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=108886869 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_alert_test.108886869
Directory /workspace/48.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/48.rom_ctrl_corrupt_sig_fatal_chk.1372283308
Short name T311
Test name
Test status
Simulation time 7756660922 ps
CPU time 84.35 seconds
Started Apr 25 12:37:17 PM PDT 24
Finished Apr 25 12:38:44 PM PDT 24
Peak memory 228728 kb
Host smart-9c376918-ab4d-43b0-b10a-592eeeb9806e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1372283308 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_
corrupt_sig_fatal_chk.1372283308
Directory /workspace/48.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/48.rom_ctrl_kmac_err_chk.4167454351
Short name T359
Test name
Test status
Simulation time 451286030 ps
CPU time 9.43 seconds
Started Apr 25 12:37:24 PM PDT 24
Finished Apr 25 12:37:35 PM PDT 24
Peak memory 211900 kb
Host smart-3c443a5d-228c-4640-9b7e-23a2228f644c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4167454351 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_kmac_err_chk.4167454351
Directory /workspace/48.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/48.rom_ctrl_max_throughput_chk.2294173068
Short name T354
Test name
Test status
Simulation time 8740396704 ps
CPU time 16.55 seconds
Started Apr 25 12:38:28 PM PDT 24
Finished Apr 25 12:38:47 PM PDT 24
Peak memory 210504 kb
Host smart-2ffc7a68-ee2f-4602-8438-d4cef8bacf30
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2294173068 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_max_throughput_chk.2294173068
Directory /workspace/48.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/48.rom_ctrl_smoke.895260909
Short name T324
Test name
Test status
Simulation time 8580868349 ps
CPU time 28.91 seconds
Started Apr 25 12:37:19 PM PDT 24
Finished Apr 25 12:37:51 PM PDT 24
Peak memory 219576 kb
Host smart-b8cb4700-7d2d-4271-b0d5-4690bff29dcb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=895260909 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_smoke.895260909
Directory /workspace/48.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/48.rom_ctrl_stress_all.978625782
Short name T313
Test name
Test status
Simulation time 3502106722 ps
CPU time 32.85 seconds
Started Apr 25 12:37:32 PM PDT 24
Finished Apr 25 12:38:06 PM PDT 24
Peak memory 214480 kb
Host smart-1b66e806-663d-4d5d-b1d8-4607ad725f9d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=978625782 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 48.rom_ctrl_stress_all.978625782
Directory /workspace/48.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/49.rom_ctrl_alert_test.922310209
Short name T189
Test name
Test status
Simulation time 5315923666 ps
CPU time 11.89 seconds
Started Apr 25 12:37:20 PM PDT 24
Finished Apr 25 12:37:35 PM PDT 24
Peak memory 211416 kb
Host smart-c2304a75-d684-4a37-9b50-681b971aee82
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=922310209 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_alert_test.922310209
Directory /workspace/49.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/49.rom_ctrl_corrupt_sig_fatal_chk.3619297746
Short name T340
Test name
Test status
Simulation time 28133090772 ps
CPU time 290.26 seconds
Started Apr 25 12:37:24 PM PDT 24
Finished Apr 25 12:42:16 PM PDT 24
Peak memory 211628 kb
Host smart-2f62c036-c923-412b-a806-2bc8d1de8c41
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3619297746 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_
corrupt_sig_fatal_chk.3619297746
Directory /workspace/49.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/49.rom_ctrl_kmac_err_chk.1453893837
Short name T17
Test name
Test status
Simulation time 639358535 ps
CPU time 9.29 seconds
Started Apr 25 12:37:34 PM PDT 24
Finished Apr 25 12:37:44 PM PDT 24
Peak memory 211812 kb
Host smart-b24474a0-460a-4d75-8c2a-9c497d073e84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1453893837 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_kmac_err_chk.1453893837
Directory /workspace/49.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/49.rom_ctrl_max_throughput_chk.512096900
Short name T214
Test name
Test status
Simulation time 423568992 ps
CPU time 5.42 seconds
Started Apr 25 12:37:29 PM PDT 24
Finished Apr 25 12:37:36 PM PDT 24
Peak memory 211312 kb
Host smart-27cdbc4b-597d-4d9e-bff2-f545fb0fd4f7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=512096900 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_max_throughput_chk.512096900
Directory /workspace/49.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/49.rom_ctrl_smoke.1528464820
Short name T65
Test name
Test status
Simulation time 677875811 ps
CPU time 15.13 seconds
Started Apr 25 12:37:37 PM PDT 24
Finished Apr 25 12:37:54 PM PDT 24
Peak memory 219492 kb
Host smart-e37936df-38a3-4800-ac7f-d2e2ed11797c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1528464820 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_smoke.1528464820
Directory /workspace/49.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/49.rom_ctrl_stress_all.225252289
Short name T183
Test name
Test status
Simulation time 941409717 ps
CPU time 10.78 seconds
Started Apr 25 12:37:31 PM PDT 24
Finished Apr 25 12:37:43 PM PDT 24
Peak memory 211216 kb
Host smart-c65b7d38-3f49-47e3-993d-fd35e06a6998
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=225252289 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 49.rom_ctrl_stress_all.225252289
Directory /workspace/49.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/5.rom_ctrl_alert_test.814597513
Short name T176
Test name
Test status
Simulation time 3633822543 ps
CPU time 15.22 seconds
Started Apr 25 12:36:53 PM PDT 24
Finished Apr 25 12:37:10 PM PDT 24
Peak memory 211464 kb
Host smart-93e2b61f-ea76-4795-bcbc-19192e50b19e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=814597513 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_alert_test.814597513
Directory /workspace/5.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/5.rom_ctrl_corrupt_sig_fatal_chk.2014970256
Short name T213
Test name
Test status
Simulation time 14655129765 ps
CPU time 158.5 seconds
Started Apr 25 12:36:51 PM PDT 24
Finished Apr 25 12:39:30 PM PDT 24
Peak memory 237776 kb
Host smart-51fc1b24-090e-410c-b994-0615ebef687f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2014970256 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_c
orrupt_sig_fatal_chk.2014970256
Directory /workspace/5.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/5.rom_ctrl_kmac_err_chk.1625574738
Short name T133
Test name
Test status
Simulation time 17326020840 ps
CPU time 26.91 seconds
Started Apr 25 12:36:57 PM PDT 24
Finished Apr 25 12:37:26 PM PDT 24
Peak memory 212252 kb
Host smart-6baf2f58-f4c8-4dfb-87c9-91198e0fb9b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1625574738 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_kmac_err_chk.1625574738
Directory /workspace/5.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/5.rom_ctrl_max_throughput_chk.34693876
Short name T297
Test name
Test status
Simulation time 2418201986 ps
CPU time 14.85 seconds
Started Apr 25 12:37:12 PM PDT 24
Finished Apr 25 12:37:30 PM PDT 24
Peak memory 211400 kb
Host smart-9f68d75b-5aef-4699-9b5a-4f230757e28c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=34693876 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_max_throughput_chk.34693876
Directory /workspace/5.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/5.rom_ctrl_smoke.1649835843
Short name T308
Test name
Test status
Simulation time 17062477585 ps
CPU time 23.46 seconds
Started Apr 25 12:37:02 PM PDT 24
Finished Apr 25 12:37:27 PM PDT 24
Peak memory 214116 kb
Host smart-906a6667-e692-462a-a218-e33c61d70b90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1649835843 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_smoke.1649835843
Directory /workspace/5.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/5.rom_ctrl_stress_all.1942380815
Short name T254
Test name
Test status
Simulation time 945852817 ps
CPU time 17.48 seconds
Started Apr 25 12:37:08 PM PDT 24
Finished Apr 25 12:37:29 PM PDT 24
Peak memory 219432 kb
Host smart-e52e0a6b-0c72-484a-a099-1418ab2d3e3f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1942380815 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 5.rom_ctrl_stress_all.1942380815
Directory /workspace/5.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/6.rom_ctrl_alert_test.855626646
Short name T196
Test name
Test status
Simulation time 5547550791 ps
CPU time 11.71 seconds
Started Apr 25 12:36:52 PM PDT 24
Finished Apr 25 12:37:06 PM PDT 24
Peak memory 211404 kb
Host smart-1d234ce0-a6de-4ff6-b6d7-5ad42884cf9e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=855626646 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_alert_test.855626646
Directory /workspace/6.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/6.rom_ctrl_corrupt_sig_fatal_chk.1815605659
Short name T153
Test name
Test status
Simulation time 3964046001 ps
CPU time 158.6 seconds
Started Apr 25 12:37:06 PM PDT 24
Finished Apr 25 12:39:46 PM PDT 24
Peak memory 228728 kb
Host smart-81e3ab89-90b7-45d0-8d89-6dec56f302da
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1815605659 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_c
orrupt_sig_fatal_chk.1815605659
Directory /workspace/6.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/6.rom_ctrl_kmac_err_chk.604036147
Short name T252
Test name
Test status
Simulation time 328242998 ps
CPU time 9.36 seconds
Started Apr 25 12:36:54 PM PDT 24
Finished Apr 25 12:37:04 PM PDT 24
Peak memory 212248 kb
Host smart-0c3d995a-955a-4781-9382-77c74285f5e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=604036147 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_kmac_err_chk.604036147
Directory /workspace/6.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/6.rom_ctrl_max_throughput_chk.1887567694
Short name T198
Test name
Test status
Simulation time 887368793 ps
CPU time 6.77 seconds
Started Apr 25 12:37:05 PM PDT 24
Finished Apr 25 12:37:13 PM PDT 24
Peak memory 211272 kb
Host smart-16768e61-f961-4250-a3fa-8359e710216c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1887567694 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_max_throughput_chk.1887567694
Directory /workspace/6.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/6.rom_ctrl_smoke.1102461754
Short name T109
Test name
Test status
Simulation time 17130951412 ps
CPU time 33.51 seconds
Started Apr 25 12:36:58 PM PDT 24
Finished Apr 25 12:37:33 PM PDT 24
Peak memory 213932 kb
Host smart-161c5edc-d26f-4e87-bc47-60c2c68ef1ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1102461754 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_smoke.1102461754
Directory /workspace/6.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/7.rom_ctrl_alert_test.541395429
Short name T221
Test name
Test status
Simulation time 6291880854 ps
CPU time 9.5 seconds
Started Apr 25 12:36:57 PM PDT 24
Finished Apr 25 12:37:08 PM PDT 24
Peak memory 211432 kb
Host smart-253dc2ed-01fe-4a50-855f-669e336a432c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=541395429 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_alert_test.541395429
Directory /workspace/7.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/7.rom_ctrl_corrupt_sig_fatal_chk.3115825107
Short name T207
Test name
Test status
Simulation time 36444126778 ps
CPU time 93.18 seconds
Started Apr 25 12:36:55 PM PDT 24
Finished Apr 25 12:38:29 PM PDT 24
Peak memory 212648 kb
Host smart-ff588be3-3ef6-41bb-a16a-14944230e1a8
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3115825107 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_c
orrupt_sig_fatal_chk.3115825107
Directory /workspace/7.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/7.rom_ctrl_kmac_err_chk.308878512
Short name T227
Test name
Test status
Simulation time 4283471014 ps
CPU time 22.83 seconds
Started Apr 25 12:37:08 PM PDT 24
Finished Apr 25 12:37:34 PM PDT 24
Peak memory 212012 kb
Host smart-8070c589-d3f9-4692-9e9e-2eabe47bceca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=308878512 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_kmac_err_chk.308878512
Directory /workspace/7.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/7.rom_ctrl_max_throughput_chk.1382746356
Short name T1
Test name
Test status
Simulation time 98717471 ps
CPU time 5.37 seconds
Started Apr 25 12:37:10 PM PDT 24
Finished Apr 25 12:37:18 PM PDT 24
Peak memory 211304 kb
Host smart-53f3b046-8f7e-466c-a0e4-b2a8bef49839
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1382746356 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_max_throughput_chk.1382746356
Directory /workspace/7.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/7.rom_ctrl_smoke.1533202273
Short name T130
Test name
Test status
Simulation time 4161576890 ps
CPU time 40.88 seconds
Started Apr 25 12:37:07 PM PDT 24
Finished Apr 25 12:37:51 PM PDT 24
Peak memory 213532 kb
Host smart-1f7f09f0-0e29-4d6c-8dd3-b694b9ae71ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1533202273 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_smoke.1533202273
Directory /workspace/7.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/7.rom_ctrl_stress_all.4254883927
Short name T110
Test name
Test status
Simulation time 1586878650 ps
CPU time 16.15 seconds
Started Apr 25 12:36:50 PM PDT 24
Finished Apr 25 12:37:08 PM PDT 24
Peak memory 212116 kb
Host smart-dc81c6de-6f8e-43e1-9959-82ed00f68d6e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4254883927 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 7.rom_ctrl_stress_all.4254883927
Directory /workspace/7.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/8.rom_ctrl_alert_test.4257698977
Short name T225
Test name
Test status
Simulation time 2413204416 ps
CPU time 11.32 seconds
Started Apr 25 12:36:56 PM PDT 24
Finished Apr 25 12:37:08 PM PDT 24
Peak memory 211384 kb
Host smart-01ca95c9-4613-422b-850c-03413400abba
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4257698977 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_alert_test.4257698977
Directory /workspace/8.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/8.rom_ctrl_corrupt_sig_fatal_chk.2858356080
Short name T266
Test name
Test status
Simulation time 67042865390 ps
CPU time 358.24 seconds
Started Apr 25 12:37:00 PM PDT 24
Finished Apr 25 12:42:59 PM PDT 24
Peak memory 229372 kb
Host smart-96cc8598-846f-4c94-a0ff-3e434c04323e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2858356080 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_c
orrupt_sig_fatal_chk.2858356080
Directory /workspace/8.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/8.rom_ctrl_kmac_err_chk.722071329
Short name T290
Test name
Test status
Simulation time 3105174252 ps
CPU time 27.25 seconds
Started Apr 25 12:36:57 PM PDT 24
Finished Apr 25 12:37:26 PM PDT 24
Peak memory 212052 kb
Host smart-7a387093-de1b-4dfd-a897-b6ab92370227
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=722071329 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_kmac_err_chk.722071329
Directory /workspace/8.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/8.rom_ctrl_max_throughput_chk.2448773027
Short name T312
Test name
Test status
Simulation time 358257501 ps
CPU time 5.68 seconds
Started Apr 25 12:36:42 PM PDT 24
Finished Apr 25 12:36:48 PM PDT 24
Peak memory 211312 kb
Host smart-a1a52e07-54df-4ad5-95f8-cb052b127997
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2448773027 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_max_throughput_chk.2448773027
Directory /workspace/8.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/8.rom_ctrl_smoke.1553242646
Short name T262
Test name
Test status
Simulation time 192073475 ps
CPU time 10.12 seconds
Started Apr 25 12:36:51 PM PDT 24
Finished Apr 25 12:37:03 PM PDT 24
Peak memory 219504 kb
Host smart-7756d358-0707-4385-afbb-013f54f6e601
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1553242646 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_smoke.1553242646
Directory /workspace/8.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/8.rom_ctrl_stress_all.2960037277
Short name T66
Test name
Test status
Simulation time 7958911420 ps
CPU time 87.21 seconds
Started Apr 25 12:36:52 PM PDT 24
Finished Apr 25 12:38:20 PM PDT 24
Peak memory 216944 kb
Host smart-8d0a9b10-4d14-4158-ab7d-5ba6e0b64024
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2960037277 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 8.rom_ctrl_stress_all.2960037277
Directory /workspace/8.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/8.rom_ctrl_stress_all_with_rand_reset.794234392
Short name T42
Test name
Test status
Simulation time 576838389953 ps
CPU time 1782.68 seconds
Started Apr 25 12:36:45 PM PDT 24
Finished Apr 25 01:06:30 PM PDT 24
Peak memory 236056 kb
Host smart-b3250034-55b3-4477-9e8a-5262b4a1dd70
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=794234392 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_stress_all_with_rand_reset.794234392
Directory /workspace/8.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.rom_ctrl_alert_test.1478794818
Short name T247
Test name
Test status
Simulation time 1812812556 ps
CPU time 14.32 seconds
Started Apr 25 12:36:57 PM PDT 24
Finished Apr 25 12:37:14 PM PDT 24
Peak memory 211368 kb
Host smart-43b49bb3-18a1-4924-bfae-328ca0a51020
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1478794818 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_alert_test.1478794818
Directory /workspace/9.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/9.rom_ctrl_corrupt_sig_fatal_chk.3997527914
Short name T180
Test name
Test status
Simulation time 11063473703 ps
CPU time 119.25 seconds
Started Apr 25 12:36:56 PM PDT 24
Finished Apr 25 12:38:56 PM PDT 24
Peak memory 236836 kb
Host smart-58be32a0-98a9-49aa-956c-aeca9bd6e163
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3997527914 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_c
orrupt_sig_fatal_chk.3997527914
Directory /workspace/9.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/9.rom_ctrl_kmac_err_chk.1522586121
Short name T194
Test name
Test status
Simulation time 1012592325 ps
CPU time 12.92 seconds
Started Apr 25 12:37:20 PM PDT 24
Finished Apr 25 12:37:36 PM PDT 24
Peak memory 212204 kb
Host smart-03f3c83d-c75e-4ffd-a0d4-149ae9761fc3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1522586121 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_kmac_err_chk.1522586121
Directory /workspace/9.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/9.rom_ctrl_max_throughput_chk.1713218885
Short name T114
Test name
Test status
Simulation time 2479725527 ps
CPU time 11.87 seconds
Started Apr 25 12:37:03 PM PDT 24
Finished Apr 25 12:37:17 PM PDT 24
Peak memory 211372 kb
Host smart-8d279bb9-3103-4f88-9e43-5f28a8bc2c94
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1713218885 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_max_throughput_chk.1713218885
Directory /workspace/9.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/9.rom_ctrl_smoke.1340603107
Short name T304
Test name
Test status
Simulation time 747613207 ps
CPU time 10.02 seconds
Started Apr 25 12:36:58 PM PDT 24
Finished Apr 25 12:37:10 PM PDT 24
Peak memory 219480 kb
Host smart-915e26dd-5a9c-411f-abb1-4fcc305ccc7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1340603107 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_smoke.1340603107
Directory /workspace/9.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/9.rom_ctrl_stress_all.2002962585
Short name T143
Test name
Test status
Simulation time 17456479297 ps
CPU time 75.4 seconds
Started Apr 25 12:36:55 PM PDT 24
Finished Apr 25 12:38:11 PM PDT 24
Peak memory 219576 kb
Host smart-054d337e-2b12-447c-9c9d-04a13cdb6eb4
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2002962585 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 9.rom_ctrl_stress_all.2002962585
Directory /workspace/9.rom_ctrl_stress_all/latest
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