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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
97.62 96.97 93.01 97.88 100.00 98.37 98.03 99.07


Total test records in report: 469
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html
T299 /workspace/coverage/default/43.rom_ctrl_corrupt_sig_fatal_chk.1860293225 Apr 28 12:41:25 PM PDT 24 Apr 28 12:45:50 PM PDT 24 91488076441 ps
T300 /workspace/coverage/default/8.rom_ctrl_alert_test.2619189025 Apr 28 12:40:52 PM PDT 24 Apr 28 12:41:04 PM PDT 24 4953755063 ps
T301 /workspace/coverage/default/47.rom_ctrl_stress_all.500293120 Apr 28 12:41:26 PM PDT 24 Apr 28 12:42:07 PM PDT 24 10558635964 ps
T302 /workspace/coverage/default/46.rom_ctrl_alert_test.2997766783 Apr 28 12:41:21 PM PDT 24 Apr 28 12:41:36 PM PDT 24 1579894540 ps
T303 /workspace/coverage/default/24.rom_ctrl_max_throughput_chk.939971459 Apr 28 12:41:07 PM PDT 24 Apr 28 12:41:22 PM PDT 24 2495277202 ps
T304 /workspace/coverage/default/42.rom_ctrl_alert_test.2805259040 Apr 28 12:41:27 PM PDT 24 Apr 28 12:41:41 PM PDT 24 1317929600 ps
T305 /workspace/coverage/default/33.rom_ctrl_max_throughput_chk.605484268 Apr 28 12:41:18 PM PDT 24 Apr 28 12:41:32 PM PDT 24 1201486015 ps
T306 /workspace/coverage/default/49.rom_ctrl_alert_test.1399068433 Apr 28 12:41:27 PM PDT 24 Apr 28 12:41:33 PM PDT 24 174860268 ps
T35 /workspace/coverage/default/2.rom_ctrl_sec_cm.1704476340 Apr 28 12:40:48 PM PDT 24 Apr 28 12:41:46 PM PDT 24 3930624770 ps
T307 /workspace/coverage/default/8.rom_ctrl_kmac_err_chk.40175844 Apr 28 12:40:57 PM PDT 24 Apr 28 12:41:08 PM PDT 24 2070801726 ps
T308 /workspace/coverage/default/3.rom_ctrl_alert_test.3726845974 Apr 28 12:40:59 PM PDT 24 Apr 28 12:41:14 PM PDT 24 1531198142 ps
T309 /workspace/coverage/default/39.rom_ctrl_kmac_err_chk.1959875341 Apr 28 12:41:48 PM PDT 24 Apr 28 12:42:16 PM PDT 24 27872741433 ps
T310 /workspace/coverage/default/12.rom_ctrl_stress_all.149345817 Apr 28 12:40:42 PM PDT 24 Apr 28 12:41:13 PM PDT 24 2948889700 ps
T311 /workspace/coverage/default/22.rom_ctrl_max_throughput_chk.1479519075 Apr 28 12:41:06 PM PDT 24 Apr 28 12:41:19 PM PDT 24 917134892 ps
T312 /workspace/coverage/default/13.rom_ctrl_corrupt_sig_fatal_chk.3976031764 Apr 28 12:40:52 PM PDT 24 Apr 28 12:42:04 PM PDT 24 5229381179 ps
T313 /workspace/coverage/default/18.rom_ctrl_stress_all.1072146203 Apr 28 12:41:03 PM PDT 24 Apr 28 12:41:11 PM PDT 24 220686336 ps
T314 /workspace/coverage/default/7.rom_ctrl_kmac_err_chk.2436532634 Apr 28 12:41:06 PM PDT 24 Apr 28 12:41:31 PM PDT 24 4903712401 ps
T315 /workspace/coverage/default/24.rom_ctrl_smoke.4028522419 Apr 28 12:41:08 PM PDT 24 Apr 28 12:41:30 PM PDT 24 5270250364 ps
T316 /workspace/coverage/default/18.rom_ctrl_kmac_err_chk.3250990914 Apr 28 12:41:12 PM PDT 24 Apr 28 12:41:46 PM PDT 24 4016125479 ps
T317 /workspace/coverage/default/17.rom_ctrl_alert_test.3372570847 Apr 28 12:41:03 PM PDT 24 Apr 28 12:41:12 PM PDT 24 673637977 ps
T318 /workspace/coverage/default/25.rom_ctrl_kmac_err_chk.3672347896 Apr 28 12:41:22 PM PDT 24 Apr 28 12:41:52 PM PDT 24 10840180148 ps
T319 /workspace/coverage/default/33.rom_ctrl_corrupt_sig_fatal_chk.3024467174 Apr 28 12:41:18 PM PDT 24 Apr 28 12:46:31 PM PDT 24 129020184785 ps
T320 /workspace/coverage/default/6.rom_ctrl_alert_test.1603344737 Apr 28 12:40:55 PM PDT 24 Apr 28 12:41:02 PM PDT 24 343666029 ps
T321 /workspace/coverage/default/30.rom_ctrl_max_throughput_chk.1709366910 Apr 28 12:41:24 PM PDT 24 Apr 28 12:41:42 PM PDT 24 11705428378 ps
T322 /workspace/coverage/default/25.rom_ctrl_max_throughput_chk.2492736245 Apr 28 12:41:21 PM PDT 24 Apr 28 12:41:35 PM PDT 24 4486541425 ps
T323 /workspace/coverage/default/48.rom_ctrl_stress_all.2347308734 Apr 28 12:41:50 PM PDT 24 Apr 28 12:43:11 PM PDT 24 52143583152 ps
T324 /workspace/coverage/default/8.rom_ctrl_max_throughput_chk.676263781 Apr 28 12:41:08 PM PDT 24 Apr 28 12:41:21 PM PDT 24 3763392179 ps
T325 /workspace/coverage/default/1.rom_ctrl_stress_all.4110097413 Apr 28 12:40:40 PM PDT 24 Apr 28 12:41:21 PM PDT 24 6208190783 ps
T326 /workspace/coverage/default/13.rom_ctrl_stress_all.22751595 Apr 28 12:41:01 PM PDT 24 Apr 28 12:41:34 PM PDT 24 16421587262 ps
T327 /workspace/coverage/default/30.rom_ctrl_corrupt_sig_fatal_chk.1724528767 Apr 28 12:41:35 PM PDT 24 Apr 28 12:45:10 PM PDT 24 84704264921 ps
T328 /workspace/coverage/default/14.rom_ctrl_corrupt_sig_fatal_chk.862411363 Apr 28 12:40:52 PM PDT 24 Apr 28 12:45:12 PM PDT 24 112164279037 ps
T329 /workspace/coverage/default/6.rom_ctrl_corrupt_sig_fatal_chk.1028453907 Apr 28 12:41:10 PM PDT 24 Apr 28 12:45:12 PM PDT 24 277203181879 ps
T330 /workspace/coverage/default/14.rom_ctrl_max_throughput_chk.3688387367 Apr 28 12:41:12 PM PDT 24 Apr 28 12:41:24 PM PDT 24 3585031641 ps
T331 /workspace/coverage/default/4.rom_ctrl_smoke.2427360381 Apr 28 12:41:01 PM PDT 24 Apr 28 12:41:13 PM PDT 24 370446235 ps
T332 /workspace/coverage/default/12.rom_ctrl_max_throughput_chk.2659539943 Apr 28 12:41:15 PM PDT 24 Apr 28 12:41:26 PM PDT 24 2088169886 ps
T333 /workspace/coverage/default/25.rom_ctrl_corrupt_sig_fatal_chk.2545945361 Apr 28 12:41:09 PM PDT 24 Apr 28 12:43:19 PM PDT 24 5318475923 ps
T21 /workspace/coverage/default/14.rom_ctrl_stress_all_with_rand_reset.1181845553 Apr 28 12:41:08 PM PDT 24 Apr 28 03:33:59 PM PDT 24 86065525729 ps
T334 /workspace/coverage/default/38.rom_ctrl_stress_all.1405958821 Apr 28 12:41:30 PM PDT 24 Apr 28 12:41:57 PM PDT 24 9891299123 ps
T335 /workspace/coverage/default/37.rom_ctrl_alert_test.1076802267 Apr 28 12:41:18 PM PDT 24 Apr 28 12:41:26 PM PDT 24 1946291219 ps
T336 /workspace/coverage/default/7.rom_ctrl_stress_all.3851502382 Apr 28 12:40:55 PM PDT 24 Apr 28 12:41:39 PM PDT 24 13001665163 ps
T337 /workspace/coverage/default/6.rom_ctrl_smoke.930249522 Apr 28 12:40:55 PM PDT 24 Apr 28 12:41:24 PM PDT 24 10822936642 ps
T338 /workspace/coverage/default/43.rom_ctrl_alert_test.4158139216 Apr 28 12:41:20 PM PDT 24 Apr 28 12:41:29 PM PDT 24 6566349394 ps
T339 /workspace/coverage/default/39.rom_ctrl_alert_test.1656115748 Apr 28 12:41:24 PM PDT 24 Apr 28 12:41:42 PM PDT 24 7121076576 ps
T340 /workspace/coverage/default/18.rom_ctrl_corrupt_sig_fatal_chk.416668352 Apr 28 12:41:13 PM PDT 24 Apr 28 12:43:35 PM PDT 24 28512142542 ps
T341 /workspace/coverage/default/36.rom_ctrl_corrupt_sig_fatal_chk.465223747 Apr 28 12:41:10 PM PDT 24 Apr 28 12:45:30 PM PDT 24 56812005457 ps
T342 /workspace/coverage/default/0.rom_ctrl_alert_test.1911685501 Apr 28 12:40:44 PM PDT 24 Apr 28 12:40:58 PM PDT 24 1480626820 ps
T343 /workspace/coverage/default/7.rom_ctrl_max_throughput_chk.1032221404 Apr 28 12:41:02 PM PDT 24 Apr 28 12:41:16 PM PDT 24 1117801006 ps
T344 /workspace/coverage/default/14.rom_ctrl_kmac_err_chk.3830119407 Apr 28 12:41:10 PM PDT 24 Apr 28 12:41:25 PM PDT 24 752794946 ps
T345 /workspace/coverage/default/16.rom_ctrl_max_throughput_chk.2352692190 Apr 28 12:41:15 PM PDT 24 Apr 28 12:41:24 PM PDT 24 558462241 ps
T346 /workspace/coverage/default/45.rom_ctrl_stress_all_with_rand_reset.460741897 Apr 28 12:41:20 PM PDT 24 Apr 28 01:59:13 PM PDT 24 178953608331 ps
T347 /workspace/coverage/default/21.rom_ctrl_kmac_err_chk.544909267 Apr 28 12:41:28 PM PDT 24 Apr 28 12:41:48 PM PDT 24 2517684744 ps
T348 /workspace/coverage/default/4.rom_ctrl_stress_all.1226937679 Apr 28 12:41:11 PM PDT 24 Apr 28 12:41:45 PM PDT 24 11865377965 ps
T349 /workspace/coverage/default/19.rom_ctrl_stress_all_with_rand_reset.3459861648 Apr 28 12:41:11 PM PDT 24 Apr 28 01:20:45 PM PDT 24 64326189509 ps
T350 /workspace/coverage/default/0.rom_ctrl_corrupt_sig_fatal_chk.2949320815 Apr 28 12:40:47 PM PDT 24 Apr 28 12:42:27 PM PDT 24 6321144240 ps
T351 /workspace/coverage/default/32.rom_ctrl_alert_test.1339345404 Apr 28 12:41:17 PM PDT 24 Apr 28 12:41:35 PM PDT 24 5720549455 ps
T352 /workspace/coverage/default/45.rom_ctrl_stress_all.2786396458 Apr 28 12:41:41 PM PDT 24 Apr 28 12:42:09 PM PDT 24 472246021 ps
T353 /workspace/coverage/default/35.rom_ctrl_kmac_err_chk.496102371 Apr 28 12:41:25 PM PDT 24 Apr 28 12:41:57 PM PDT 24 7999378138 ps
T354 /workspace/coverage/default/16.rom_ctrl_corrupt_sig_fatal_chk.1224917609 Apr 28 12:40:53 PM PDT 24 Apr 28 12:42:36 PM PDT 24 7754068330 ps
T355 /workspace/coverage/default/26.rom_ctrl_smoke.1746367708 Apr 28 12:41:21 PM PDT 24 Apr 28 12:41:33 PM PDT 24 748039983 ps
T356 /workspace/coverage/default/43.rom_ctrl_stress_all.3208776240 Apr 28 12:41:41 PM PDT 24 Apr 28 12:42:49 PM PDT 24 8445832645 ps
T357 /workspace/coverage/default/36.rom_ctrl_stress_all.930770686 Apr 28 12:41:29 PM PDT 24 Apr 28 12:41:37 PM PDT 24 627555620 ps
T358 /workspace/coverage/default/45.rom_ctrl_corrupt_sig_fatal_chk.3256066369 Apr 28 12:41:24 PM PDT 24 Apr 28 12:44:28 PM PDT 24 11976297548 ps
T359 /workspace/coverage/default/10.rom_ctrl_stress_all.1027954570 Apr 28 12:41:08 PM PDT 24 Apr 28 12:42:12 PM PDT 24 12852496684 ps
T360 /workspace/coverage/default/41.rom_ctrl_kmac_err_chk.3655734909 Apr 28 12:41:25 PM PDT 24 Apr 28 12:41:38 PM PDT 24 279870024 ps
T36 /workspace/coverage/default/3.rom_ctrl_sec_cm.298566080 Apr 28 12:41:05 PM PDT 24 Apr 28 12:42:00 PM PDT 24 2174418562 ps
T361 /workspace/coverage/default/49.rom_ctrl_max_throughput_chk.1567795298 Apr 28 12:41:54 PM PDT 24 Apr 28 12:42:06 PM PDT 24 2501179768 ps
T362 /workspace/coverage/default/47.rom_ctrl_stress_all_with_rand_reset.1765189992 Apr 28 12:41:26 PM PDT 24 Apr 28 03:33:24 PM PDT 24 102503600829 ps
T363 /workspace/coverage/default/37.rom_ctrl_smoke.2106698140 Apr 28 12:41:24 PM PDT 24 Apr 28 12:41:49 PM PDT 24 7889205022 ps
T364 /workspace/coverage/default/22.rom_ctrl_stress_all.1176682717 Apr 28 12:41:29 PM PDT 24 Apr 28 12:41:42 PM PDT 24 887979184 ps
T365 /workspace/coverage/default/27.rom_ctrl_stress_all.3989168820 Apr 28 12:41:21 PM PDT 24 Apr 28 12:41:33 PM PDT 24 1720328222 ps
T366 /workspace/coverage/default/5.rom_ctrl_kmac_err_chk.2695750945 Apr 28 12:41:06 PM PDT 24 Apr 28 12:41:37 PM PDT 24 12033635270 ps
T367 /workspace/coverage/default/35.rom_ctrl_smoke.2219913415 Apr 28 12:41:32 PM PDT 24 Apr 28 12:41:43 PM PDT 24 365975139 ps
T368 /workspace/coverage/default/1.rom_ctrl_alert_test.4218444645 Apr 28 12:41:08 PM PDT 24 Apr 28 12:41:25 PM PDT 24 22654790108 ps
T369 /workspace/coverage/default/27.rom_ctrl_corrupt_sig_fatal_chk.2887813512 Apr 28 12:41:16 PM PDT 24 Apr 28 12:46:29 PM PDT 24 36834574051 ps
T61 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_hw_reset.1009065211 Apr 28 12:40:34 PM PDT 24 Apr 28 12:40:45 PM PDT 24 321682291 ps
T62 /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_rw.726766195 Apr 28 12:40:56 PM PDT 24 Apr 28 12:41:10 PM PDT 24 1745318130 ps
T63 /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_mem_rw_with_rand_reset.3296742399 Apr 28 12:40:57 PM PDT 24 Apr 28 12:41:11 PM PDT 24 2346460548 ps
T370 /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_errors.3207523918 Apr 28 12:40:48 PM PDT 24 Apr 28 12:40:59 PM PDT 24 141862467 ps
T113 /workspace/coverage/cover_reg_top/4.rom_ctrl_passthru_mem_tl_intg_err.1600144460 Apr 28 12:40:28 PM PDT 24 Apr 28 12:41:20 PM PDT 24 14367949155 ps
T371 /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_walk.145185423 Apr 28 12:40:51 PM PDT 24 Apr 28 12:40:55 PM PDT 24 333121264 ps
T372 /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_mem_rw_with_rand_reset.1909051225 Apr 28 12:41:07 PM PDT 24 Apr 28 12:41:14 PM PDT 24 101777428 ps
T67 /workspace/coverage/cover_reg_top/0.rom_ctrl_passthru_mem_tl_intg_err.1585099039 Apr 28 12:40:34 PM PDT 24 Apr 28 12:40:54 PM PDT 24 1444410409 ps
T68 /workspace/coverage/cover_reg_top/19.rom_ctrl_passthru_mem_tl_intg_err.2600204914 Apr 28 12:40:45 PM PDT 24 Apr 28 12:41:35 PM PDT 24 23494308370 ps
T58 /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_intg_err.419983939 Apr 28 12:40:59 PM PDT 24 Apr 28 12:42:11 PM PDT 24 923248538 ps
T69 /workspace/coverage/cover_reg_top/18.rom_ctrl_same_csr_outstanding.4201683044 Apr 28 12:41:01 PM PDT 24 Apr 28 12:41:14 PM PDT 24 2105539271 ps
T114 /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_rw.2098879964 Apr 28 12:40:40 PM PDT 24 Apr 28 12:40:45 PM PDT 24 87152419 ps
T373 /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_errors.2280618262 Apr 28 12:40:40 PM PDT 24 Apr 28 12:40:48 PM PDT 24 737957074 ps
T115 /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_rw.3084098298 Apr 28 12:40:43 PM PDT 24 Apr 28 12:40:57 PM PDT 24 1655621275 ps
T70 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_aliasing.2147223992 Apr 28 12:40:45 PM PDT 24 Apr 28 12:40:51 PM PDT 24 128907407 ps
T374 /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_errors.2607402188 Apr 28 12:41:16 PM PDT 24 Apr 28 12:41:32 PM PDT 24 5861264952 ps
T116 /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_rw.1579956218 Apr 28 12:40:46 PM PDT 24 Apr 28 12:40:53 PM PDT 24 295743470 ps
T375 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_hw_reset.509123812 Apr 28 12:40:32 PM PDT 24 Apr 28 12:40:50 PM PDT 24 3097693036 ps
T71 /workspace/coverage/cover_reg_top/6.rom_ctrl_passthru_mem_tl_intg_err.1559349024 Apr 28 12:40:43 PM PDT 24 Apr 28 12:42:00 PM PDT 24 7975456221 ps
T72 /workspace/coverage/cover_reg_top/11.rom_ctrl_passthru_mem_tl_intg_err.3750032819 Apr 28 12:40:56 PM PDT 24 Apr 28 12:41:32 PM PDT 24 41493865852 ps
T59 /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_intg_err.2834147574 Apr 28 12:40:56 PM PDT 24 Apr 28 12:41:34 PM PDT 24 574671754 ps
T376 /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_errors.4178740146 Apr 28 12:41:11 PM PDT 24 Apr 28 12:41:28 PM PDT 24 1192067325 ps
T60 /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_intg_err.2045538324 Apr 28 12:40:35 PM PDT 24 Apr 28 12:41:50 PM PDT 24 8529710333 ps
T123 /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_intg_err.2469874753 Apr 28 12:40:29 PM PDT 24 Apr 28 12:41:14 PM PDT 24 1532803954 ps
T73 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_rw.2675435366 Apr 28 12:40:46 PM PDT 24 Apr 28 12:40:54 PM PDT 24 1229879491 ps
T130 /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_intg_err.1817835163 Apr 28 12:41:07 PM PDT 24 Apr 28 12:41:45 PM PDT 24 155851280 ps
T74 /workspace/coverage/cover_reg_top/7.rom_ctrl_passthru_mem_tl_intg_err.3656026673 Apr 28 12:40:35 PM PDT 24 Apr 28 12:42:00 PM PDT 24 9790302640 ps
T377 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_hw_reset.2839373168 Apr 28 12:40:31 PM PDT 24 Apr 28 12:40:50 PM PDT 24 2188208827 ps
T378 /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_errors.100292945 Apr 28 12:40:31 PM PDT 24 Apr 28 12:40:51 PM PDT 24 4210594074 ps
T75 /workspace/coverage/cover_reg_top/6.rom_ctrl_same_csr_outstanding.2784597391 Apr 28 12:40:49 PM PDT 24 Apr 28 12:41:06 PM PDT 24 10448116237 ps
T379 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_mem_rw_with_rand_reset.3494166054 Apr 28 12:40:57 PM PDT 24 Apr 28 12:41:11 PM PDT 24 2565729535 ps
T102 /workspace/coverage/cover_reg_top/10.rom_ctrl_same_csr_outstanding.1663452877 Apr 28 12:40:39 PM PDT 24 Apr 28 12:40:46 PM PDT 24 508087637 ps
T124 /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_intg_err.3790841007 Apr 28 12:40:42 PM PDT 24 Apr 28 12:41:56 PM PDT 24 941847486 ps
T380 /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_mem_rw_with_rand_reset.1773331866 Apr 28 12:40:51 PM PDT 24 Apr 28 12:41:02 PM PDT 24 3673119389 ps
T103 /workspace/coverage/cover_reg_top/15.rom_ctrl_same_csr_outstanding.1019649644 Apr 28 12:41:06 PM PDT 24 Apr 28 12:41:25 PM PDT 24 1894454875 ps
T104 /workspace/coverage/cover_reg_top/9.rom_ctrl_same_csr_outstanding.3478891023 Apr 28 12:40:37 PM PDT 24 Apr 28 12:40:47 PM PDT 24 903292382 ps
T381 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_bit_bash.2713221638 Apr 28 12:40:37 PM PDT 24 Apr 28 12:40:48 PM PDT 24 3949854733 ps
T382 /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_rw.658496170 Apr 28 12:40:51 PM PDT 24 Apr 28 12:41:00 PM PDT 24 664881051 ps
T128 /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_intg_err.2153510372 Apr 28 12:40:39 PM PDT 24 Apr 28 12:41:58 PM PDT 24 3542462427 ps
T383 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_mem_rw_with_rand_reset.415506181 Apr 28 12:40:29 PM PDT 24 Apr 28 12:40:37 PM PDT 24 298202969 ps
T127 /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_intg_err.568079780 Apr 28 12:40:40 PM PDT 24 Apr 28 12:41:24 PM PDT 24 5351277945 ps
T384 /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_partial_access.2974695351 Apr 28 12:40:34 PM PDT 24 Apr 28 12:40:50 PM PDT 24 3748870607 ps
T82 /workspace/coverage/cover_reg_top/12.rom_ctrl_passthru_mem_tl_intg_err.2255520484 Apr 28 12:41:06 PM PDT 24 Apr 28 12:42:05 PM PDT 24 89457472592 ps
T385 /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_intg_err.2176791394 Apr 28 12:41:08 PM PDT 24 Apr 28 12:41:55 PM PDT 24 1676897787 ps
T129 /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_intg_err.1834755537 Apr 28 12:40:46 PM PDT 24 Apr 28 12:41:57 PM PDT 24 1673081914 ps
T386 /workspace/coverage/cover_reg_top/8.rom_ctrl_same_csr_outstanding.3880638235 Apr 28 12:40:32 PM PDT 24 Apr 28 12:40:45 PM PDT 24 143565165 ps
T387 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_mem_rw_with_rand_reset.2908108406 Apr 28 12:40:38 PM PDT 24 Apr 28 12:40:44 PM PDT 24 189611246 ps
T388 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_bit_bash.2586831031 Apr 28 12:40:39 PM PDT 24 Apr 28 12:40:50 PM PDT 24 1765148068 ps
T83 /workspace/coverage/cover_reg_top/2.rom_ctrl_passthru_mem_tl_intg_err.3643329445 Apr 28 12:40:46 PM PDT 24 Apr 28 12:41:14 PM PDT 24 2449392271 ps
T84 /workspace/coverage/cover_reg_top/18.rom_ctrl_passthru_mem_tl_intg_err.3416794155 Apr 28 12:41:00 PM PDT 24 Apr 28 12:41:32 PM PDT 24 8370874276 ps
T389 /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_walk.3528739837 Apr 28 12:40:38 PM PDT 24 Apr 28 12:40:43 PM PDT 24 87147875 ps
T390 /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_partial_access.3744548591 Apr 28 12:40:36 PM PDT 24 Apr 28 12:40:52 PM PDT 24 8035623647 ps
T391 /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_errors.3078295355 Apr 28 12:40:50 PM PDT 24 Apr 28 12:41:09 PM PDT 24 1666556350 ps
T392 /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_errors.116931731 Apr 28 12:40:31 PM PDT 24 Apr 28 12:40:44 PM PDT 24 2540260093 ps
T125 /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_intg_err.105586878 Apr 28 12:40:50 PM PDT 24 Apr 28 12:42:02 PM PDT 24 336237439 ps
T393 /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_intg_err.3429329681 Apr 28 12:40:38 PM PDT 24 Apr 28 12:41:20 PM PDT 24 1938758503 ps
T394 /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_partial_access.1600332769 Apr 28 12:40:43 PM PDT 24 Apr 28 12:40:48 PM PDT 24 334100394 ps
T395 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_aliasing.1424439913 Apr 28 12:40:57 PM PDT 24 Apr 28 12:41:10 PM PDT 24 18260074340 ps
T396 /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_errors.2704852882 Apr 28 12:40:40 PM PDT 24 Apr 28 12:40:57 PM PDT 24 1740746430 ps
T397 /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_errors.3547896097 Apr 28 12:40:58 PM PDT 24 Apr 28 12:41:10 PM PDT 24 858954829 ps
T398 /workspace/coverage/cover_reg_top/17.rom_ctrl_same_csr_outstanding.1487920084 Apr 28 12:40:56 PM PDT 24 Apr 28 12:41:13 PM PDT 24 9323055410 ps
T399 /workspace/coverage/cover_reg_top/13.rom_ctrl_passthru_mem_tl_intg_err.3428466008 Apr 28 12:40:50 PM PDT 24 Apr 28 12:41:28 PM PDT 24 5108237581 ps
T131 /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_intg_err.4255395401 Apr 28 12:40:53 PM PDT 24 Apr 28 12:41:37 PM PDT 24 5718878234 ps
T400 /workspace/coverage/cover_reg_top/16.rom_ctrl_same_csr_outstanding.1791500675 Apr 28 12:40:50 PM PDT 24 Apr 28 12:41:05 PM PDT 24 1787793492 ps
T401 /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_mem_rw_with_rand_reset.2566530075 Apr 28 12:40:33 PM PDT 24 Apr 28 12:40:45 PM PDT 24 1632353669 ps
T402 /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_errors.1292243243 Apr 28 12:40:39 PM PDT 24 Apr 28 12:40:59 PM PDT 24 8116198273 ps
T403 /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_rw.2727355270 Apr 28 12:40:57 PM PDT 24 Apr 28 12:41:11 PM PDT 24 5352749100 ps
T404 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_mem_rw_with_rand_reset.2045393037 Apr 28 12:40:46 PM PDT 24 Apr 28 12:40:58 PM PDT 24 1140874817 ps
T405 /workspace/coverage/cover_reg_top/1.rom_ctrl_same_csr_outstanding.419924526 Apr 28 12:40:41 PM PDT 24 Apr 28 12:40:56 PM PDT 24 1550416089 ps
T406 /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_rw.331959687 Apr 28 12:40:54 PM PDT 24 Apr 28 12:41:09 PM PDT 24 1797663494 ps
T407 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_bit_bash.4254288150 Apr 28 12:40:30 PM PDT 24 Apr 28 12:40:48 PM PDT 24 3937399328 ps
T408 /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_mem_rw_with_rand_reset.1024872961 Apr 28 12:40:33 PM PDT 24 Apr 28 12:40:44 PM PDT 24 1905752845 ps
T409 /workspace/coverage/cover_reg_top/14.rom_ctrl_passthru_mem_tl_intg_err.2179541157 Apr 28 12:40:42 PM PDT 24 Apr 28 12:42:07 PM PDT 24 50683101721 ps
T410 /workspace/coverage/cover_reg_top/2.rom_ctrl_same_csr_outstanding.3522708071 Apr 28 12:40:49 PM PDT 24 Apr 28 12:40:57 PM PDT 24 522851860 ps
T411 /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_mem_rw_with_rand_reset.719147947 Apr 28 12:41:02 PM PDT 24 Apr 28 12:41:12 PM PDT 24 1560082175 ps
T412 /workspace/coverage/cover_reg_top/12.rom_ctrl_same_csr_outstanding.3963607817 Apr 28 12:40:41 PM PDT 24 Apr 28 12:40:51 PM PDT 24 1606376882 ps
T413 /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_errors.684518477 Apr 28 12:40:44 PM PDT 24 Apr 28 12:40:57 PM PDT 24 1390680899 ps
T85 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_aliasing.1330110255 Apr 28 12:40:41 PM PDT 24 Apr 28 12:40:58 PM PDT 24 2147553319 ps
T414 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_bit_bash.2788371127 Apr 28 12:40:42 PM PDT 24 Apr 28 12:40:51 PM PDT 24 477268157 ps
T86 /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_rw.2127554945 Apr 28 12:40:55 PM PDT 24 Apr 28 12:41:02 PM PDT 24 373454244 ps
T89 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_rw.3408648746 Apr 28 12:40:39 PM PDT 24 Apr 28 12:40:53 PM PDT 24 4429507455 ps
T415 /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_errors.2740718135 Apr 28 12:41:24 PM PDT 24 Apr 28 12:41:34 PM PDT 24 920717492 ps
T87 /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_rw.1367317551 Apr 28 12:40:51 PM PDT 24 Apr 28 12:40:56 PM PDT 24 346301475 ps
T416 /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_mem_rw_with_rand_reset.3239193488 Apr 28 12:41:06 PM PDT 24 Apr 28 12:41:21 PM PDT 24 6423344884 ps
T417 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_bit_bash.79062190 Apr 28 12:41:07 PM PDT 24 Apr 28 12:41:17 PM PDT 24 4116258541 ps
T90 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_aliasing.739302050 Apr 28 12:40:32 PM PDT 24 Apr 28 12:40:38 PM PDT 24 91173723 ps
T126 /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_intg_err.2367870444 Apr 28 12:40:58 PM PDT 24 Apr 28 12:42:11 PM PDT 24 4320263942 ps
T418 /workspace/coverage/cover_reg_top/15.rom_ctrl_passthru_mem_tl_intg_err.3662704034 Apr 28 12:40:52 PM PDT 24 Apr 28 12:42:27 PM PDT 24 75784521653 ps
T419 /workspace/coverage/cover_reg_top/7.rom_ctrl_same_csr_outstanding.3220046847 Apr 28 12:40:28 PM PDT 24 Apr 28 12:40:41 PM PDT 24 2283880790 ps
T420 /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_rw.660604995 Apr 28 12:41:08 PM PDT 24 Apr 28 12:41:25 PM PDT 24 3928095487 ps
T121 /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_intg_err.3222572772 Apr 28 12:40:33 PM PDT 24 Apr 28 12:41:47 PM PDT 24 4455621247 ps
T421 /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_mem_rw_with_rand_reset.2263950027 Apr 28 12:40:55 PM PDT 24 Apr 28 12:41:00 PM PDT 24 94380947 ps
T422 /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_mem_rw_with_rand_reset.1524844420 Apr 28 12:40:47 PM PDT 24 Apr 28 12:40:57 PM PDT 24 630578587 ps
T423 /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_mem_rw_with_rand_reset.2637085889 Apr 28 12:40:40 PM PDT 24 Apr 28 12:40:45 PM PDT 24 177650331 ps
T424 /workspace/coverage/cover_reg_top/3.rom_ctrl_passthru_mem_tl_intg_err.2753121686 Apr 28 12:40:36 PM PDT 24 Apr 28 12:41:05 PM PDT 24 2150146132 ps
T91 /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_rw.3250487159 Apr 28 12:40:48 PM PDT 24 Apr 28 12:41:04 PM PDT 24 3996345801 ps
T425 /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_mem_rw_with_rand_reset.3674038205 Apr 28 12:40:43 PM PDT 24 Apr 28 12:40:52 PM PDT 24 2128507301 ps
T426 /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_errors.1488515557 Apr 28 12:40:44 PM PDT 24 Apr 28 12:40:59 PM PDT 24 665167524 ps
T427 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_rw.1391325143 Apr 28 12:40:30 PM PDT 24 Apr 28 12:40:41 PM PDT 24 4904213521 ps
T428 /workspace/coverage/cover_reg_top/1.rom_ctrl_passthru_mem_tl_intg_err.3393527680 Apr 28 12:40:43 PM PDT 24 Apr 28 12:41:05 PM PDT 24 1087338398 ps
T429 /workspace/coverage/cover_reg_top/10.rom_ctrl_passthru_mem_tl_intg_err.2062779519 Apr 28 12:40:45 PM PDT 24 Apr 28 12:41:12 PM PDT 24 1537650915 ps
T430 /workspace/coverage/cover_reg_top/0.rom_ctrl_same_csr_outstanding.355223047 Apr 28 12:40:39 PM PDT 24 Apr 28 12:40:54 PM PDT 24 1711736989 ps
T431 /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_intg_err.2619933582 Apr 28 12:40:44 PM PDT 24 Apr 28 12:42:00 PM PDT 24 6064016432 ps
T432 /workspace/coverage/cover_reg_top/9.rom_ctrl_passthru_mem_tl_intg_err.2912925800 Apr 28 12:41:06 PM PDT 24 Apr 28 12:41:56 PM PDT 24 5258382940 ps
T433 /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_partial_access.1179991014 Apr 28 12:40:26 PM PDT 24 Apr 28 12:40:43 PM PDT 24 8435275485 ps
T92 /workspace/coverage/cover_reg_top/16.rom_ctrl_passthru_mem_tl_intg_err.542890998 Apr 28 12:41:01 PM PDT 24 Apr 28 12:41:55 PM PDT 24 15930418263 ps
T434 /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_walk.2285119924 Apr 28 12:40:30 PM PDT 24 Apr 28 12:40:37 PM PDT 24 522794095 ps
T435 /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_intg_err.2444423719 Apr 28 12:40:58 PM PDT 24 Apr 28 12:42:15 PM PDT 24 2864230467 ps
T436 /workspace/coverage/cover_reg_top/14.rom_ctrl_same_csr_outstanding.2525364005 Apr 28 12:40:58 PM PDT 24 Apr 28 12:41:14 PM PDT 24 1608057201 ps
T437 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_aliasing.3323175358 Apr 28 12:40:43 PM PDT 24 Apr 28 12:40:57 PM PDT 24 2962669832 ps
T438 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_rw.24830799 Apr 28 12:40:39 PM PDT 24 Apr 28 12:40:54 PM PDT 24 14221688622 ps
T439 /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_intg_err.368830739 Apr 28 12:40:42 PM PDT 24 Apr 28 12:41:27 PM PDT 24 22609956781 ps
T440 /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_mem_rw_with_rand_reset.300139634 Apr 28 12:40:32 PM PDT 24 Apr 28 12:40:39 PM PDT 24 505128689 ps
T441 /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_rw.928535646 Apr 28 12:40:53 PM PDT 24 Apr 28 12:41:07 PM PDT 24 1566078508 ps
T442 /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_walk.1200620689 Apr 28 12:40:50 PM PDT 24 Apr 28 12:40:55 PM PDT 24 333248845 ps
T443 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_rw.383683923 Apr 28 12:40:45 PM PDT 24 Apr 28 12:40:58 PM PDT 24 1311685817 ps
T444 /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_errors.110576274 Apr 28 12:40:56 PM PDT 24 Apr 28 12:41:09 PM PDT 24 1575764421 ps
T445 /workspace/coverage/cover_reg_top/3.rom_ctrl_same_csr_outstanding.1815508032 Apr 28 12:40:34 PM PDT 24 Apr 28 12:40:49 PM PDT 24 6275711709 ps
T93 /workspace/coverage/cover_reg_top/5.rom_ctrl_passthru_mem_tl_intg_err.2151166180 Apr 28 12:40:40 PM PDT 24 Apr 28 12:41:00 PM PDT 24 1621463464 ps
T446 /workspace/coverage/cover_reg_top/11.rom_ctrl_same_csr_outstanding.181580584 Apr 28 12:41:14 PM PDT 24 Apr 28 12:41:29 PM PDT 24 5619037845 ps
T122 /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_intg_err.1006723429 Apr 28 12:40:54 PM PDT 24 Apr 28 12:41:37 PM PDT 24 1074470162 ps
T447 /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_rw.3518363906 Apr 28 12:40:48 PM PDT 24 Apr 28 12:40:54 PM PDT 24 346427860 ps
T448 /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_mem_rw_with_rand_reset.590049986 Apr 28 12:40:58 PM PDT 24 Apr 28 12:41:17 PM PDT 24 23910685953 ps
T449 /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_errors.819872373 Apr 28 12:40:47 PM PDT 24 Apr 28 12:41:05 PM PDT 24 5158196490 ps
T450 /workspace/coverage/cover_reg_top/5.rom_ctrl_same_csr_outstanding.4183817549 Apr 28 12:40:43 PM PDT 24 Apr 28 12:40:54 PM PDT 24 6872834149 ps
T451 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_hw_reset.2814828066 Apr 28 12:40:45 PM PDT 24 Apr 28 12:40:53 PM PDT 24 835579084 ps
T88 /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_rw.3662036550 Apr 28 12:41:04 PM PDT 24 Apr 28 12:41:13 PM PDT 24 865923888 ps
T452 /workspace/coverage/cover_reg_top/17.rom_ctrl_passthru_mem_tl_intg_err.2326168737 Apr 28 12:41:05 PM PDT 24 Apr 28 12:41:53 PM PDT 24 10355087087 ps
T453 /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_errors.520693976 Apr 28 12:40:56 PM PDT 24 Apr 28 12:41:09 PM PDT 24 1037144282 ps
T454 /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_errors.1793387093 Apr 28 12:40:56 PM PDT 24 Apr 28 12:41:06 PM PDT 24 412818557 ps
T455 /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_partial_access.3862094327 Apr 28 12:40:31 PM PDT 24 Apr 28 12:40:37 PM PDT 24 347545898 ps
T456 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_mem_rw_with_rand_reset.1981051093 Apr 28 12:40:39 PM PDT 24 Apr 28 12:40:52 PM PDT 24 1403800923 ps
T457 /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_intg_err.1121929158 Apr 28 12:41:00 PM PDT 24 Apr 28 12:42:11 PM PDT 24 2071710490 ps
T458 /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_errors.1889531294 Apr 28 12:41:00 PM PDT 24 Apr 28 12:41:13 PM PDT 24 412035218 ps
T459 /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_mem_rw_with_rand_reset.193290056 Apr 28 12:40:47 PM PDT 24 Apr 28 12:41:04 PM PDT 24 1994776620 ps
T460 /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_mem_rw_with_rand_reset.1783945308 Apr 28 12:40:43 PM PDT 24 Apr 28 12:40:54 PM PDT 24 897933093 ps
T461 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_hw_reset.1319674907 Apr 28 12:40:40 PM PDT 24 Apr 28 12:40:50 PM PDT 24 827792378 ps
T462 /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_walk.3482387224 Apr 28 12:40:45 PM PDT 24 Apr 28 12:40:50 PM PDT 24 333517399 ps
T463 /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_errors.903531927 Apr 28 12:40:29 PM PDT 24 Apr 28 12:40:42 PM PDT 24 1589589485 ps
T464 /workspace/coverage/cover_reg_top/4.rom_ctrl_same_csr_outstanding.3061937936 Apr 28 12:40:29 PM PDT 24 Apr 28 12:40:35 PM PDT 24 91061128 ps
T465 /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_rw.3381341179 Apr 28 12:41:00 PM PDT 24 Apr 28 12:41:09 PM PDT 24 2954699995 ps
T466 /workspace/coverage/cover_reg_top/13.rom_ctrl_same_csr_outstanding.3853206392 Apr 28 12:41:15 PM PDT 24 Apr 28 12:41:22 PM PDT 24 346688554 ps
T467 /workspace/coverage/cover_reg_top/19.rom_ctrl_same_csr_outstanding.3374451850 Apr 28 12:40:58 PM PDT 24 Apr 28 12:41:16 PM PDT 24 3790510554 ps
T468 /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_errors.3083533411 Apr 28 12:40:48 PM PDT 24 Apr 28 12:41:03 PM PDT 24 1949687331 ps
T469 /workspace/coverage/cover_reg_top/8.rom_ctrl_passthru_mem_tl_intg_err.762698678 Apr 28 12:40:46 PM PDT 24 Apr 28 12:41:15 PM PDT 24 8966587913 ps

Test location /workspace/coverage/default/22.rom_ctrl_corrupt_sig_fatal_chk.3566241460
Short name T1
Test name
Test status
Simulation time 16456443641 ps
CPU time 119.73 seconds
Started Apr 28 12:41:10 PM PDT 24
Finished Apr 28 12:43:11 PM PDT 24
Peak memory 225212 kb
Host smart-717924fc-2e58-4cd0-a0bc-648edefb8518
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3566241460 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_
corrupt_sig_fatal_chk.3566241460
Directory /workspace/22.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/18.rom_ctrl_stress_all_with_rand_reset.168420372
Short name T11
Test name
Test status
Simulation time 129136520137 ps
CPU time 2041.08 seconds
Started Apr 28 12:40:55 PM PDT 24
Finished Apr 28 01:14:57 PM PDT 24
Peak memory 236028 kb
Host smart-0e2a13f2-45d1-4fe8-bc64-d40e1660a716
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=168420372 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_stress_all_with_rand_reset.168420372
Directory /workspace/18.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/26.rom_ctrl_corrupt_sig_fatal_chk.2369672570
Short name T14
Test name
Test status
Simulation time 1480257124 ps
CPU time 87.57 seconds
Started Apr 28 12:41:23 PM PDT 24
Finished Apr 28 12:42:53 PM PDT 24
Peak memory 237824 kb
Host smart-6d777849-2412-498f-8f71-b45e6bd336bd
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2369672570 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_
corrupt_sig_fatal_chk.2369672570
Directory /workspace/26.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/29.rom_ctrl_corrupt_sig_fatal_chk.3382361288
Short name T4
Test name
Test status
Simulation time 15308417949 ps
CPU time 161.4 seconds
Started Apr 28 12:41:18 PM PDT 24
Finished Apr 28 12:44:01 PM PDT 24
Peak memory 212568 kb
Host smart-9a4e3c87-8ef2-448a-b597-bcb807d43bad
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3382361288 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_
corrupt_sig_fatal_chk.3382361288
Directory /workspace/29.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_intg_err.2045538324
Short name T60
Test name
Test status
Simulation time 8529710333 ps
CPU time 74.06 seconds
Started Apr 28 12:40:35 PM PDT 24
Finished Apr 28 12:41:50 PM PDT 24
Peak memory 211588 kb
Host smart-0a759491-0911-4168-8c82-04849e6bdb33
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2045538324 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_tl_in
tg_err.2045538324
Directory /workspace/2.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/4.rom_ctrl_sec_cm.1537859927
Short name T30
Test name
Test status
Simulation time 473089259 ps
CPU time 55.15 seconds
Started Apr 28 12:40:57 PM PDT 24
Finished Apr 28 12:41:53 PM PDT 24
Peak memory 230216 kb
Host smart-ffb63249-11dc-461a-8552-1873f40aa472
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1537859927 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_sec_cm.1537859927
Directory /workspace/4.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_passthru_mem_tl_intg_err.1585099039
Short name T67
Test name
Test status
Simulation time 1444410409 ps
CPU time 18.6 seconds
Started Apr 28 12:40:34 PM PDT 24
Finished Apr 28 12:40:54 PM PDT 24
Peak memory 210444 kb
Host smart-fb2278ab-9820-4739-8187-794dbc0c43a8
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1585099039 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_pa
ssthru_mem_tl_intg_err.1585099039
Directory /workspace/0.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/default/20.rom_ctrl_smoke.3305891999
Short name T12
Test name
Test status
Simulation time 18881010931 ps
CPU time 31.1 seconds
Started Apr 28 12:41:13 PM PDT 24
Finished Apr 28 12:41:47 PM PDT 24
Peak memory 214064 kb
Host smart-2e9c6fef-8687-47f7-a59b-ec754a3e8e71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3305891999 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_smoke.3305891999
Directory /workspace/20.rom_ctrl_smoke/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_intg_err.2367870444
Short name T126
Test name
Test status
Simulation time 4320263942 ps
CPU time 70.63 seconds
Started Apr 28 12:40:58 PM PDT 24
Finished Apr 28 12:42:11 PM PDT 24
Peak memory 211788 kb
Host smart-1a8a2add-b76d-44ca-8a9f-acca93815236
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2367870444 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_tl_i
ntg_err.2367870444
Directory /workspace/10.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/34.rom_ctrl_stress_all.3674069815
Short name T94
Test name
Test status
Simulation time 2296711838 ps
CPU time 19.58 seconds
Started Apr 28 12:41:17 PM PDT 24
Finished Apr 28 12:41:38 PM PDT 24
Peak memory 219576 kb
Host smart-793b2504-89b6-4f1a-a440-151a21e2eb19
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3674069815 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 34.rom_ctrl_stress_all.3674069815
Directory /workspace/34.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/28.rom_ctrl_alert_test.1208023175
Short name T64
Test name
Test status
Simulation time 1940238045 ps
CPU time 15.4 seconds
Started Apr 28 12:41:22 PM PDT 24
Finished Apr 28 12:41:41 PM PDT 24
Peak memory 211356 kb
Host smart-6cc6b913-91dd-4769-812a-0e1b7f3b217d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1208023175 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_alert_test.1208023175
Directory /workspace/28.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/0.rom_ctrl_kmac_err_chk.3370000568
Short name T22
Test name
Test status
Simulation time 3465857594 ps
CPU time 28.92 seconds
Started Apr 28 12:41:10 PM PDT 24
Finished Apr 28 12:41:41 PM PDT 24
Peak memory 212104 kb
Host smart-d146dc01-ea89-465d-b4f1-21b8bd003c14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3370000568 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_kmac_err_chk.3370000568
Directory /workspace/0.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/13.rom_ctrl_kmac_err_chk.3543386196
Short name T26
Test name
Test status
Simulation time 3836404896 ps
CPU time 18.56 seconds
Started Apr 28 12:41:04 PM PDT 24
Finished Apr 28 12:41:24 PM PDT 24
Peak memory 211912 kb
Host smart-9cae17fa-0162-4dd1-a5bf-fe52067faffd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3543386196 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_kmac_err_chk.3543386196
Directory /workspace/13.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_intg_err.105586878
Short name T125
Test name
Test status
Simulation time 336237439 ps
CPU time 70.63 seconds
Started Apr 28 12:40:50 PM PDT 24
Finished Apr 28 12:42:02 PM PDT 24
Peak memory 211452 kb
Host smart-5f8b5583-7728-45c1-8a12-3139b60a1ceb
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=105586878 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_tl_in
tg_err.105586878
Directory /workspace/17.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_passthru_mem_tl_intg_err.2255520484
Short name T82
Test name
Test status
Simulation time 89457472592 ps
CPU time 56.83 seconds
Started Apr 28 12:41:06 PM PDT 24
Finished Apr 28 12:42:05 PM PDT 24
Peak memory 210540 kb
Host smart-ce2ead18-5ae9-450d-8d88-0d463b6436b2
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2255520484 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_p
assthru_mem_tl_intg_err.2255520484
Directory /workspace/12.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/default/32.rom_ctrl_corrupt_sig_fatal_chk.3520327871
Short name T2
Test name
Test status
Simulation time 26439874843 ps
CPU time 189.39 seconds
Started Apr 28 12:41:14 PM PDT 24
Finished Apr 28 12:44:25 PM PDT 24
Peak memory 233284 kb
Host smart-def4d857-b228-4d68-ba7e-e3e3dcf3fd43
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3520327871 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_
corrupt_sig_fatal_chk.3520327871
Directory /workspace/32.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/13.rom_ctrl_max_throughput_chk.1594592601
Short name T140
Test name
Test status
Simulation time 2830253054 ps
CPU time 13.3 seconds
Started Apr 28 12:41:05 PM PDT 24
Finished Apr 28 12:41:20 PM PDT 24
Peak memory 211328 kb
Host smart-9d0e415b-fa27-45f2-8815-75c0d0791f0f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1594592601 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_max_throughput_chk.1594592601
Directory /workspace/13.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_aliasing.1330110255
Short name T85
Test name
Test status
Simulation time 2147553319 ps
CPU time 15.83 seconds
Started Apr 28 12:40:41 PM PDT 24
Finished Apr 28 12:40:58 PM PDT 24
Peak memory 210344 kb
Host smart-decf62b2-4737-4c12-b75d-af725c93fb42
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1330110255 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_alia
sing.1330110255
Directory /workspace/0.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_bit_bash.2586831031
Short name T388
Test name
Test status
Simulation time 1765148068 ps
CPU time 9.69 seconds
Started Apr 28 12:40:39 PM PDT 24
Finished Apr 28 12:40:50 PM PDT 24
Peak memory 210352 kb
Host smart-f4f5c125-b327-45ec-9ee6-dc64a3da150d
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2586831031 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_bit_
bash.2586831031
Directory /workspace/0.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_hw_reset.1009065211
Short name T61
Test name
Test status
Simulation time 321682291 ps
CPU time 9.41 seconds
Started Apr 28 12:40:34 PM PDT 24
Finished Apr 28 12:40:45 PM PDT 24
Peak memory 210404 kb
Host smart-2564110b-238c-4387-ba88-031a3b4c00eb
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1009065211 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_hw_r
eset.1009065211
Directory /workspace/0.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_mem_rw_with_rand_reset.2045393037
Short name T404
Test name
Test status
Simulation time 1140874817 ps
CPU time 11.29 seconds
Started Apr 28 12:40:46 PM PDT 24
Finished Apr 28 12:40:58 PM PDT 24
Peak memory 213228 kb
Host smart-de4ac610-d715-438c-960d-b6184deab995
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2045393037 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 0.rom_ctrl_csr_mem_rw_with_rand_reset.2045393037
Directory /workspace/0.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_rw.3408648746
Short name T89
Test name
Test status
Simulation time 4429507455 ps
CPU time 13.85 seconds
Started Apr 28 12:40:39 PM PDT 24
Finished Apr 28 12:40:53 PM PDT 24
Peak memory 210620 kb
Host smart-8db21b0a-846b-4d22-b183-faabdcde6719
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3408648746 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_rw.3408648746
Directory /workspace/0.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_partial_access.1179991014
Short name T433
Test name
Test status
Simulation time 8435275485 ps
CPU time 15.64 seconds
Started Apr 28 12:40:26 PM PDT 24
Finished Apr 28 12:40:43 PM PDT 24
Peak memory 210352 kb
Host smart-50d1317b-1067-4859-a3f4-bcc8ce8313c8
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1179991014 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctr
l_mem_partial_access.1179991014
Directory /workspace/0.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_walk.2285119924
Short name T434
Test name
Test status
Simulation time 522794095 ps
CPU time 5.01 seconds
Started Apr 28 12:40:30 PM PDT 24
Finished Apr 28 12:40:37 PM PDT 24
Peak memory 210284 kb
Host smart-df2629e3-b4d9-46de-89a5-414e5374c44e
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2285119924 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_mem_walk
.2285119924
Directory /workspace/0.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_same_csr_outstanding.355223047
Short name T430
Test name
Test status
Simulation time 1711736989 ps
CPU time 14.52 seconds
Started Apr 28 12:40:39 PM PDT 24
Finished Apr 28 12:40:54 PM PDT 24
Peak memory 210420 kb
Host smart-3fb18407-3c2b-49a4-bdd5-c657da4e90f7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=355223047 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ct
rl_same_csr_outstanding.355223047
Directory /workspace/0.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_errors.2704852882
Short name T396
Test name
Test status
Simulation time 1740746430 ps
CPU time 15.67 seconds
Started Apr 28 12:40:40 PM PDT 24
Finished Apr 28 12:40:57 PM PDT 24
Peak memory 218644 kb
Host smart-07de9f18-9fe6-4b4d-a231-be3de65e7b4b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2704852882 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_tl_errors.2704852882
Directory /workspace/0.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_intg_err.3790841007
Short name T124
Test name
Test status
Simulation time 941847486 ps
CPU time 72.33 seconds
Started Apr 28 12:40:42 PM PDT 24
Finished Apr 28 12:41:56 PM PDT 24
Peak memory 218564 kb
Host smart-76d97714-222c-45f8-a065-6575451d1e69
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3790841007 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_tl_in
tg_err.3790841007
Directory /workspace/0.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_aliasing.739302050
Short name T90
Test name
Test status
Simulation time 91173723 ps
CPU time 4.37 seconds
Started Apr 28 12:40:32 PM PDT 24
Finished Apr 28 12:40:38 PM PDT 24
Peak memory 210440 kb
Host smart-94d417fb-da1e-4fe1-aef7-9e8a5f9bcff0
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=739302050 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_alias
ing.739302050
Directory /workspace/1.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_bit_bash.2713221638
Short name T381
Test name
Test status
Simulation time 3949854733 ps
CPU time 10.22 seconds
Started Apr 28 12:40:37 PM PDT 24
Finished Apr 28 12:40:48 PM PDT 24
Peak memory 210496 kb
Host smart-e70f3ff9-175c-400f-9723-0097db42da3b
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2713221638 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_bit_
bash.2713221638
Directory /workspace/1.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_hw_reset.2839373168
Short name T377
Test name
Test status
Simulation time 2188208827 ps
CPU time 17.66 seconds
Started Apr 28 12:40:31 PM PDT 24
Finished Apr 28 12:40:50 PM PDT 24
Peak memory 210448 kb
Host smart-bafd4473-0b05-4a0f-81e4-074ff8db28f1
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2839373168 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_hw_r
eset.2839373168
Directory /workspace/1.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_mem_rw_with_rand_reset.2908108406
Short name T387
Test name
Test status
Simulation time 189611246 ps
CPU time 4.98 seconds
Started Apr 28 12:40:38 PM PDT 24
Finished Apr 28 12:40:44 PM PDT 24
Peak memory 218584 kb
Host smart-1247c09f-548e-48db-a411-f9473e769c8c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2908108406 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 1.rom_ctrl_csr_mem_rw_with_rand_reset.2908108406
Directory /workspace/1.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_rw.1391325143
Short name T427
Test name
Test status
Simulation time 4904213521 ps
CPU time 8.89 seconds
Started Apr 28 12:40:30 PM PDT 24
Finished Apr 28 12:40:41 PM PDT 24
Peak memory 210496 kb
Host smart-e0d7410a-2e42-4b9b-b3a7-212104a49036
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1391325143 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_rw.1391325143
Directory /workspace/1.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_partial_access.1600332769
Short name T394
Test name
Test status
Simulation time 334100394 ps
CPU time 4.1 seconds
Started Apr 28 12:40:43 PM PDT 24
Finished Apr 28 12:40:48 PM PDT 24
Peak memory 210304 kb
Host smart-a6bc05ab-24dc-40c9-ace5-2e4571f00785
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1600332769 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctr
l_mem_partial_access.1600332769
Directory /workspace/1.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_walk.3528739837
Short name T389
Test name
Test status
Simulation time 87147875 ps
CPU time 4.41 seconds
Started Apr 28 12:40:38 PM PDT 24
Finished Apr 28 12:40:43 PM PDT 24
Peak memory 210300 kb
Host smart-24e92aca-80cf-4441-acea-88051ed125d2
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3528739837 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_mem_walk
.3528739837
Directory /workspace/1.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_passthru_mem_tl_intg_err.3393527680
Short name T428
Test name
Test status
Simulation time 1087338398 ps
CPU time 21.32 seconds
Started Apr 28 12:40:43 PM PDT 24
Finished Apr 28 12:41:05 PM PDT 24
Peak memory 210440 kb
Host smart-68a257bc-7180-4684-9e0b-7adfed541857
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3393527680 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_pa
ssthru_mem_tl_intg_err.3393527680
Directory /workspace/1.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_same_csr_outstanding.419924526
Short name T405
Test name
Test status
Simulation time 1550416089 ps
CPU time 13.48 seconds
Started Apr 28 12:40:41 PM PDT 24
Finished Apr 28 12:40:56 PM PDT 24
Peak memory 210392 kb
Host smart-101a1795-5c20-4942-a1ea-95a00e6be84a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=419924526 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ct
rl_same_csr_outstanding.419924526
Directory /workspace/1.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_errors.116931731
Short name T392
Test name
Test status
Simulation time 2540260093 ps
CPU time 10.88 seconds
Started Apr 28 12:40:31 PM PDT 24
Finished Apr 28 12:40:44 PM PDT 24
Peak memory 218736 kb
Host smart-99cb251b-ae8f-40e3-b762-ce6d44eeb854
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=116931731 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_tl_errors.116931731
Directory /workspace/1.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_intg_err.2834147574
Short name T59
Test name
Test status
Simulation time 574671754 ps
CPU time 36.09 seconds
Started Apr 28 12:40:56 PM PDT 24
Finished Apr 28 12:41:34 PM PDT 24
Peak memory 210404 kb
Host smart-226e8b80-ad18-469d-b6ec-28ffba01de07
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2834147574 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_tl_in
tg_err.2834147574
Directory /workspace/1.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_mem_rw_with_rand_reset.1783945308
Short name T460
Test name
Test status
Simulation time 897933093 ps
CPU time 10.49 seconds
Started Apr 28 12:40:43 PM PDT 24
Finished Apr 28 12:40:54 PM PDT 24
Peak memory 212020 kb
Host smart-f12da023-f5c2-4162-98be-7e9ebf77714e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1783945308 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 10.rom_ctrl_csr_mem_rw_with_rand_reset.1783945308
Directory /workspace/10.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_rw.3084098298
Short name T115
Test name
Test status
Simulation time 1655621275 ps
CPU time 13.33 seconds
Started Apr 28 12:40:43 PM PDT 24
Finished Apr 28 12:40:57 PM PDT 24
Peak memory 210396 kb
Host smart-8f5d165b-be99-4db5-8cde-b552bee6abbd
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3084098298 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_csr_rw.3084098298
Directory /workspace/10.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_passthru_mem_tl_intg_err.2062779519
Short name T429
Test name
Test status
Simulation time 1537650915 ps
CPU time 26.53 seconds
Started Apr 28 12:40:45 PM PDT 24
Finished Apr 28 12:41:12 PM PDT 24
Peak memory 210420 kb
Host smart-60db90d8-df39-412f-8919-0a632744d4fd
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2062779519 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_p
assthru_mem_tl_intg_err.2062779519
Directory /workspace/10.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_same_csr_outstanding.1663452877
Short name T102
Test name
Test status
Simulation time 508087637 ps
CPU time 6 seconds
Started Apr 28 12:40:39 PM PDT 24
Finished Apr 28 12:40:46 PM PDT 24
Peak memory 210400 kb
Host smart-7abb6758-cbea-4259-a182-eecb7b316f38
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1663452877 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_
ctrl_same_csr_outstanding.1663452877
Directory /workspace/10.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_errors.520693976
Short name T453
Test name
Test status
Simulation time 1037144282 ps
CPU time 7.03 seconds
Started Apr 28 12:40:56 PM PDT 24
Finished Apr 28 12:41:09 PM PDT 24
Peak memory 218684 kb
Host smart-4a2f699e-e223-47d2-96cc-068cec86a01f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=520693976 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_tl_errors.520693976
Directory /workspace/10.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_mem_rw_with_rand_reset.719147947
Short name T411
Test name
Test status
Simulation time 1560082175 ps
CPU time 7.61 seconds
Started Apr 28 12:41:02 PM PDT 24
Finished Apr 28 12:41:12 PM PDT 24
Peak memory 218648 kb
Host smart-58503398-0c8e-458a-b1e3-08023fc53413
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=719147947 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 11.rom_ctrl_csr_mem_rw_with_rand_reset.719147947
Directory /workspace/11.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_rw.2727355270
Short name T403
Test name
Test status
Simulation time 5352749100 ps
CPU time 12.06 seconds
Started Apr 28 12:40:57 PM PDT 24
Finished Apr 28 12:41:11 PM PDT 24
Peak memory 210496 kb
Host smart-31935073-9349-4b4f-bf8f-45e851c54895
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2727355270 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_csr_rw.2727355270
Directory /workspace/11.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_passthru_mem_tl_intg_err.3750032819
Short name T72
Test name
Test status
Simulation time 41493865852 ps
CPU time 34.79 seconds
Started Apr 28 12:40:56 PM PDT 24
Finished Apr 28 12:41:32 PM PDT 24
Peak memory 210540 kb
Host smart-4b31814d-6d4a-489a-aea7-cc68d0a06ac5
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3750032819 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_p
assthru_mem_tl_intg_err.3750032819
Directory /workspace/11.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_same_csr_outstanding.181580584
Short name T446
Test name
Test status
Simulation time 5619037845 ps
CPU time 12.58 seconds
Started Apr 28 12:41:14 PM PDT 24
Finished Apr 28 12:41:29 PM PDT 24
Peak memory 210548 kb
Host smart-ab40235b-07cc-4267-9a29-f66e2c86e379
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=181580584 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_c
trl_same_csr_outstanding.181580584
Directory /workspace/11.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_errors.3547896097
Short name T397
Test name
Test status
Simulation time 858954829 ps
CPU time 10.03 seconds
Started Apr 28 12:40:58 PM PDT 24
Finished Apr 28 12:41:10 PM PDT 24
Peak memory 218620 kb
Host smart-18bd075c-27c5-4310-ad68-cec8ab898ed0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3547896097 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_tl_errors.3547896097
Directory /workspace/11.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_intg_err.368830739
Short name T439
Test name
Test status
Simulation time 22609956781 ps
CPU time 44.33 seconds
Started Apr 28 12:40:42 PM PDT 24
Finished Apr 28 12:41:27 PM PDT 24
Peak memory 218708 kb
Host smart-fdcf20d3-0d3e-4077-91db-5d42753188ad
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=368830739 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_tl_in
tg_err.368830739
Directory /workspace/11.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_mem_rw_with_rand_reset.193290056
Short name T459
Test name
Test status
Simulation time 1994776620 ps
CPU time 15.94 seconds
Started Apr 28 12:40:47 PM PDT 24
Finished Apr 28 12:41:04 PM PDT 24
Peak memory 214412 kb
Host smart-ed417640-71cb-48f7-9410-0b33321f94d6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=193290056 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 12.rom_ctrl_csr_mem_rw_with_rand_reset.193290056
Directory /workspace/12.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_rw.1579956218
Short name T116
Test name
Test status
Simulation time 295743470 ps
CPU time 6.08 seconds
Started Apr 28 12:40:46 PM PDT 24
Finished Apr 28 12:40:53 PM PDT 24
Peak memory 210368 kb
Host smart-28f76cb2-7c49-48aa-a0b1-2d37e010bf39
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1579956218 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_csr_rw.1579956218
Directory /workspace/12.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_same_csr_outstanding.3963607817
Short name T412
Test name
Test status
Simulation time 1606376882 ps
CPU time 9.6 seconds
Started Apr 28 12:40:41 PM PDT 24
Finished Apr 28 12:40:51 PM PDT 24
Peak memory 210432 kb
Host smart-b5264016-d0ad-4a57-8633-c455bce05c72
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3963607817 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_
ctrl_same_csr_outstanding.3963607817
Directory /workspace/12.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_errors.3083533411
Short name T468
Test name
Test status
Simulation time 1949687331 ps
CPU time 13.93 seconds
Started Apr 28 12:40:48 PM PDT 24
Finished Apr 28 12:41:03 PM PDT 24
Peak memory 218588 kb
Host smart-7fd83b45-0b53-400c-8a48-2a069368f420
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3083533411 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_tl_errors.3083533411
Directory /workspace/12.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_intg_err.1121929158
Short name T457
Test name
Test status
Simulation time 2071710490 ps
CPU time 69.24 seconds
Started Apr 28 12:41:00 PM PDT 24
Finished Apr 28 12:42:11 PM PDT 24
Peak memory 211372 kb
Host smart-76d868ad-a6c6-49b3-a6bc-fc3e76686dd2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1121929158 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_tl_i
ntg_err.1121929158
Directory /workspace/12.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_mem_rw_with_rand_reset.1909051225
Short name T372
Test name
Test status
Simulation time 101777428 ps
CPU time 4.79 seconds
Started Apr 28 12:41:07 PM PDT 24
Finished Apr 28 12:41:14 PM PDT 24
Peak memory 218600 kb
Host smart-123379a2-97da-4789-93cd-70eb49eb2f93
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1909051225 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 13.rom_ctrl_csr_mem_rw_with_rand_reset.1909051225
Directory /workspace/13.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_rw.1367317551
Short name T87
Test name
Test status
Simulation time 346301475 ps
CPU time 4.2 seconds
Started Apr 28 12:40:51 PM PDT 24
Finished Apr 28 12:40:56 PM PDT 24
Peak memory 210384 kb
Host smart-215c8dff-9e32-41fe-9423-cd23a845970c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1367317551 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_csr_rw.1367317551
Directory /workspace/13.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_passthru_mem_tl_intg_err.3428466008
Short name T399
Test name
Test status
Simulation time 5108237581 ps
CPU time 36.65 seconds
Started Apr 28 12:40:50 PM PDT 24
Finished Apr 28 12:41:28 PM PDT 24
Peak memory 210536 kb
Host smart-f575f276-3347-471c-b64c-8dd93b8b81d3
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3428466008 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_p
assthru_mem_tl_intg_err.3428466008
Directory /workspace/13.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_same_csr_outstanding.3853206392
Short name T466
Test name
Test status
Simulation time 346688554 ps
CPU time 5.37 seconds
Started Apr 28 12:41:15 PM PDT 24
Finished Apr 28 12:41:22 PM PDT 24
Peak memory 210360 kb
Host smart-89fe0256-b8b5-4106-aa2b-f03a8f0a4e33
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3853206392 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_
ctrl_same_csr_outstanding.3853206392
Directory /workspace/13.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_errors.3207523918
Short name T370
Test name
Test status
Simulation time 141862467 ps
CPU time 9.8 seconds
Started Apr 28 12:40:48 PM PDT 24
Finished Apr 28 12:40:59 PM PDT 24
Peak memory 213884 kb
Host smart-8c065fb2-7ac6-4921-8ee7-2b64984f465c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3207523918 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_tl_errors.3207523918
Directory /workspace/13.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_intg_err.3429329681
Short name T393
Test name
Test status
Simulation time 1938758503 ps
CPU time 41.37 seconds
Started Apr 28 12:40:38 PM PDT 24
Finished Apr 28 12:41:20 PM PDT 24
Peak memory 211272 kb
Host smart-64c57211-fa1a-42a7-8927-56fd9de58b29
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3429329681 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_tl_i
ntg_err.3429329681
Directory /workspace/13.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_mem_rw_with_rand_reset.2566530075
Short name T401
Test name
Test status
Simulation time 1632353669 ps
CPU time 9.79 seconds
Started Apr 28 12:40:33 PM PDT 24
Finished Apr 28 12:40:45 PM PDT 24
Peak memory 218668 kb
Host smart-7a6eea29-a6f1-453d-bf08-199e02bb8186
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2566530075 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 14.rom_ctrl_csr_mem_rw_with_rand_reset.2566530075
Directory /workspace/14.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_rw.658496170
Short name T382
Test name
Test status
Simulation time 664881051 ps
CPU time 8.34 seconds
Started Apr 28 12:40:51 PM PDT 24
Finished Apr 28 12:41:00 PM PDT 24
Peak memory 210392 kb
Host smart-a6465d5f-1604-4838-8c56-cf96ffc184a8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=658496170 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_csr_rw.658496170
Directory /workspace/14.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_passthru_mem_tl_intg_err.2179541157
Short name T409
Test name
Test status
Simulation time 50683101721 ps
CPU time 83.96 seconds
Started Apr 28 12:40:42 PM PDT 24
Finished Apr 28 12:42:07 PM PDT 24
Peak memory 210584 kb
Host smart-018eedd5-5ec8-4797-87bb-5600e43ce5fc
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2179541157 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_p
assthru_mem_tl_intg_err.2179541157
Directory /workspace/14.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_same_csr_outstanding.2525364005
Short name T436
Test name
Test status
Simulation time 1608057201 ps
CPU time 13.38 seconds
Started Apr 28 12:40:58 PM PDT 24
Finished Apr 28 12:41:14 PM PDT 24
Peak memory 210436 kb
Host smart-9850579d-6ea2-454d-8d2c-ea6bac445707
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2525364005 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_
ctrl_same_csr_outstanding.2525364005
Directory /workspace/14.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_errors.4178740146
Short name T376
Test name
Test status
Simulation time 1192067325 ps
CPU time 14.78 seconds
Started Apr 28 12:41:11 PM PDT 24
Finished Apr 28 12:41:28 PM PDT 24
Peak memory 218600 kb
Host smart-d6e6e250-6772-4149-83d4-4638348f1e35
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4178740146 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_tl_errors.4178740146
Directory /workspace/14.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_intg_err.1834755537
Short name T129
Test name
Test status
Simulation time 1673081914 ps
CPU time 69.54 seconds
Started Apr 28 12:40:46 PM PDT 24
Finished Apr 28 12:41:57 PM PDT 24
Peak memory 211452 kb
Host smart-7fa21c84-8991-4ba2-900f-71ff5d9db3ee
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1834755537 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_tl_i
ntg_err.1834755537
Directory /workspace/14.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_mem_rw_with_rand_reset.3239193488
Short name T416
Test name
Test status
Simulation time 6423344884 ps
CPU time 13.65 seconds
Started Apr 28 12:41:06 PM PDT 24
Finished Apr 28 12:41:21 PM PDT 24
Peak memory 213248 kb
Host smart-33dba07d-babd-48ae-b658-4c0df32106d8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3239193488 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 15.rom_ctrl_csr_mem_rw_with_rand_reset.3239193488
Directory /workspace/15.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_rw.660604995
Short name T420
Test name
Test status
Simulation time 3928095487 ps
CPU time 15.44 seconds
Started Apr 28 12:41:08 PM PDT 24
Finished Apr 28 12:41:25 PM PDT 24
Peak memory 210488 kb
Host smart-232c61c5-b427-4317-811c-ba1a2f461e0f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=660604995 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_csr_rw.660604995
Directory /workspace/15.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_passthru_mem_tl_intg_err.3662704034
Short name T418
Test name
Test status
Simulation time 75784521653 ps
CPU time 83.46 seconds
Started Apr 28 12:40:52 PM PDT 24
Finished Apr 28 12:42:27 PM PDT 24
Peak memory 210496 kb
Host smart-17a22f3a-2676-4fab-bd80-f43df9b5ed5a
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3662704034 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_p
assthru_mem_tl_intg_err.3662704034
Directory /workspace/15.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_same_csr_outstanding.1019649644
Short name T103
Test name
Test status
Simulation time 1894454875 ps
CPU time 16.35 seconds
Started Apr 28 12:41:06 PM PDT 24
Finished Apr 28 12:41:25 PM PDT 24
Peak memory 210432 kb
Host smart-803ef7ab-2639-46c9-8c06-f3c715560054
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1019649644 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_
ctrl_same_csr_outstanding.1019649644
Directory /workspace/15.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_errors.1488515557
Short name T426
Test name
Test status
Simulation time 665167524 ps
CPU time 13.53 seconds
Started Apr 28 12:40:44 PM PDT 24
Finished Apr 28 12:40:59 PM PDT 24
Peak memory 218640 kb
Host smart-f364dd80-fbd0-4202-82c2-3a4d5bae8559
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1488515557 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_tl_errors.1488515557
Directory /workspace/15.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_intg_err.1817835163
Short name T130
Test name
Test status
Simulation time 155851280 ps
CPU time 35.55 seconds
Started Apr 28 12:41:07 PM PDT 24
Finished Apr 28 12:41:45 PM PDT 24
Peak memory 210420 kb
Host smart-1fecc1b6-c4ce-404b-b874-2c39e285c323
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1817835163 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_tl_i
ntg_err.1817835163
Directory /workspace/15.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_mem_rw_with_rand_reset.3296742399
Short name T63
Test name
Test status
Simulation time 2346460548 ps
CPU time 11.8 seconds
Started Apr 28 12:40:57 PM PDT 24
Finished Apr 28 12:41:11 PM PDT 24
Peak memory 214432 kb
Host smart-fade56ab-7a86-4900-a6d5-c9612bbc9f65
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3296742399 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 16.rom_ctrl_csr_mem_rw_with_rand_reset.3296742399
Directory /workspace/16.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_rw.2127554945
Short name T86
Test name
Test status
Simulation time 373454244 ps
CPU time 6.82 seconds
Started Apr 28 12:40:55 PM PDT 24
Finished Apr 28 12:41:02 PM PDT 24
Peak memory 210468 kb
Host smart-704e7388-1640-452c-97f4-af2d9bc78a68
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2127554945 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_csr_rw.2127554945
Directory /workspace/16.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_passthru_mem_tl_intg_err.542890998
Short name T92
Test name
Test status
Simulation time 15930418263 ps
CPU time 52.53 seconds
Started Apr 28 12:41:01 PM PDT 24
Finished Apr 28 12:41:55 PM PDT 24
Peak memory 210576 kb
Host smart-857f5248-8a06-4b09-a263-220a6a1d290c
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=542890998 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_pa
ssthru_mem_tl_intg_err.542890998
Directory /workspace/16.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_same_csr_outstanding.1791500675
Short name T400
Test name
Test status
Simulation time 1787793492 ps
CPU time 14.25 seconds
Started Apr 28 12:40:50 PM PDT 24
Finished Apr 28 12:41:05 PM PDT 24
Peak memory 210416 kb
Host smart-9cc2bd6b-6e78-4754-ba8f-be19593ed81f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1791500675 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_
ctrl_same_csr_outstanding.1791500675
Directory /workspace/16.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_errors.2607402188
Short name T374
Test name
Test status
Simulation time 5861264952 ps
CPU time 14.62 seconds
Started Apr 28 12:41:16 PM PDT 24
Finished Apr 28 12:41:32 PM PDT 24
Peak memory 218744 kb
Host smart-f069483a-7bb2-4ef6-8b00-aa647f336484
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2607402188 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_tl_errors.2607402188
Directory /workspace/16.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_intg_err.1006723429
Short name T122
Test name
Test status
Simulation time 1074470162 ps
CPU time 42.23 seconds
Started Apr 28 12:40:54 PM PDT 24
Finished Apr 28 12:41:37 PM PDT 24
Peak memory 211104 kb
Host smart-837b4c83-4a0e-4c04-9e48-122ac7aa7002
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1006723429 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_tl_i
ntg_err.1006723429
Directory /workspace/16.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_mem_rw_with_rand_reset.1773331866
Short name T380
Test name
Test status
Simulation time 3673119389 ps
CPU time 10.13 seconds
Started Apr 28 12:40:51 PM PDT 24
Finished Apr 28 12:41:02 PM PDT 24
Peak memory 218708 kb
Host smart-2b7fb480-6d9a-4322-9510-b9571757e34a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1773331866 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 17.rom_ctrl_csr_mem_rw_with_rand_reset.1773331866
Directory /workspace/17.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_rw.3518363906
Short name T447
Test name
Test status
Simulation time 346427860 ps
CPU time 4.32 seconds
Started Apr 28 12:40:48 PM PDT 24
Finished Apr 28 12:40:54 PM PDT 24
Peak memory 210384 kb
Host smart-457d00a1-fe6d-4a52-84cb-275a1c208e54
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3518363906 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_csr_rw.3518363906
Directory /workspace/17.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_passthru_mem_tl_intg_err.2326168737
Short name T452
Test name
Test status
Simulation time 10355087087 ps
CPU time 46.41 seconds
Started Apr 28 12:41:05 PM PDT 24
Finished Apr 28 12:41:53 PM PDT 24
Peak memory 210520 kb
Host smart-f7a2779b-37c7-429d-b324-98d8667adc77
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2326168737 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_p
assthru_mem_tl_intg_err.2326168737
Directory /workspace/17.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_same_csr_outstanding.1487920084
Short name T398
Test name
Test status
Simulation time 9323055410 ps
CPU time 16.49 seconds
Started Apr 28 12:40:56 PM PDT 24
Finished Apr 28 12:41:13 PM PDT 24
Peak memory 210460 kb
Host smart-3d1a1773-4a89-462c-b356-a46f8595e41c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1487920084 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_
ctrl_same_csr_outstanding.1487920084
Directory /workspace/17.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_errors.3078295355
Short name T391
Test name
Test status
Simulation time 1666556350 ps
CPU time 17.63 seconds
Started Apr 28 12:40:50 PM PDT 24
Finished Apr 28 12:41:09 PM PDT 24
Peak memory 218676 kb
Host smart-a052d995-4b55-4b3b-bafc-3e1b79b564fe
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3078295355 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_tl_errors.3078295355
Directory /workspace/17.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_mem_rw_with_rand_reset.590049986
Short name T448
Test name
Test status
Simulation time 23910685953 ps
CPU time 16.42 seconds
Started Apr 28 12:40:58 PM PDT 24
Finished Apr 28 12:41:17 PM PDT 24
Peak memory 218724 kb
Host smart-93db0145-246f-46dd-ae54-18f1729592cc
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=590049986 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 18.rom_ctrl_csr_mem_rw_with_rand_reset.590049986
Directory /workspace/18.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_rw.2098879964
Short name T114
Test name
Test status
Simulation time 87152419 ps
CPU time 4.22 seconds
Started Apr 28 12:40:40 PM PDT 24
Finished Apr 28 12:40:45 PM PDT 24
Peak memory 210420 kb
Host smart-da4cbb48-2ae5-404d-a016-b61179691b52
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2098879964 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_csr_rw.2098879964
Directory /workspace/18.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_passthru_mem_tl_intg_err.3416794155
Short name T84
Test name
Test status
Simulation time 8370874276 ps
CPU time 29.94 seconds
Started Apr 28 12:41:00 PM PDT 24
Finished Apr 28 12:41:32 PM PDT 24
Peak memory 210564 kb
Host smart-d692a43e-d8ba-441a-a356-d1f96cc5e22e
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3416794155 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_p
assthru_mem_tl_intg_err.3416794155
Directory /workspace/18.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_same_csr_outstanding.4201683044
Short name T69
Test name
Test status
Simulation time 2105539271 ps
CPU time 10.71 seconds
Started Apr 28 12:41:01 PM PDT 24
Finished Apr 28 12:41:14 PM PDT 24
Peak memory 210412 kb
Host smart-fa31efdf-bead-4426-8d8f-08794bb55c44
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4201683044 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_
ctrl_same_csr_outstanding.4201683044
Directory /workspace/18.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_errors.1889531294
Short name T458
Test name
Test status
Simulation time 412035218 ps
CPU time 11.05 seconds
Started Apr 28 12:41:00 PM PDT 24
Finished Apr 28 12:41:13 PM PDT 24
Peak memory 218548 kb
Host smart-fb7231cb-60a6-4ad9-9b49-c71d130d4366
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1889531294 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_tl_errors.1889531294
Directory /workspace/18.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_intg_err.4255395401
Short name T131
Test name
Test status
Simulation time 5718878234 ps
CPU time 43.2 seconds
Started Apr 28 12:40:53 PM PDT 24
Finished Apr 28 12:41:37 PM PDT 24
Peak memory 211652 kb
Host smart-2589a464-7bb1-47a7-868a-eca5efa0433f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4255395401 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_tl_i
ntg_err.4255395401
Directory /workspace/18.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_mem_rw_with_rand_reset.3674038205
Short name T425
Test name
Test status
Simulation time 2128507301 ps
CPU time 8.11 seconds
Started Apr 28 12:40:43 PM PDT 24
Finished Apr 28 12:40:52 PM PDT 24
Peak memory 211556 kb
Host smart-204eb716-0950-497b-b3cb-070ec6f083e8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3674038205 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 19.rom_ctrl_csr_mem_rw_with_rand_reset.3674038205
Directory /workspace/19.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_rw.3662036550
Short name T88
Test name
Test status
Simulation time 865923888 ps
CPU time 7.08 seconds
Started Apr 28 12:41:04 PM PDT 24
Finished Apr 28 12:41:13 PM PDT 24
Peak memory 210368 kb
Host smart-23b33c99-7ee4-4f83-804e-411fb4f48330
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3662036550 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_csr_rw.3662036550
Directory /workspace/19.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_passthru_mem_tl_intg_err.2600204914
Short name T68
Test name
Test status
Simulation time 23494308370 ps
CPU time 49.08 seconds
Started Apr 28 12:40:45 PM PDT 24
Finished Apr 28 12:41:35 PM PDT 24
Peak memory 210536 kb
Host smart-0b55f9c1-a964-4478-a32b-0377feb48952
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2600204914 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_p
assthru_mem_tl_intg_err.2600204914
Directory /workspace/19.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_same_csr_outstanding.3374451850
Short name T467
Test name
Test status
Simulation time 3790510554 ps
CPU time 16.06 seconds
Started Apr 28 12:40:58 PM PDT 24
Finished Apr 28 12:41:16 PM PDT 24
Peak memory 210520 kb
Host smart-4a7864f6-c7d4-4454-ae66-4ebd424c74e6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3374451850 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_
ctrl_same_csr_outstanding.3374451850
Directory /workspace/19.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_errors.684518477
Short name T413
Test name
Test status
Simulation time 1390680899 ps
CPU time 12.58 seconds
Started Apr 28 12:40:44 PM PDT 24
Finished Apr 28 12:40:57 PM PDT 24
Peak memory 218628 kb
Host smart-f21d7fa9-04f0-40b7-8d65-6dc98d2327ea
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=684518477 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_tl_errors.684518477
Directory /workspace/19.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_intg_err.2176791394
Short name T385
Test name
Test status
Simulation time 1676897787 ps
CPU time 44.92 seconds
Started Apr 28 12:41:08 PM PDT 24
Finished Apr 28 12:41:55 PM PDT 24
Peak memory 211036 kb
Host smart-8f0bd4ed-3ba7-4743-a261-0c55195679a2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2176791394 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_tl_i
ntg_err.2176791394
Directory /workspace/19.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_aliasing.2147223992
Short name T70
Test name
Test status
Simulation time 128907407 ps
CPU time 5.17 seconds
Started Apr 28 12:40:45 PM PDT 24
Finished Apr 28 12:40:51 PM PDT 24
Peak memory 210352 kb
Host smart-85f4b5cc-dfff-4350-837b-f0e21ec93f51
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2147223992 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_alia
sing.2147223992
Directory /workspace/2.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_bit_bash.4254288150
Short name T407
Test name
Test status
Simulation time 3937399328 ps
CPU time 15.42 seconds
Started Apr 28 12:40:30 PM PDT 24
Finished Apr 28 12:40:48 PM PDT 24
Peak memory 210496 kb
Host smart-af0ce3e4-e419-41db-a6a1-6439fa810647
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4254288150 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_bit_
bash.4254288150
Directory /workspace/2.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_hw_reset.1319674907
Short name T461
Test name
Test status
Simulation time 827792378 ps
CPU time 8.55 seconds
Started Apr 28 12:40:40 PM PDT 24
Finished Apr 28 12:40:50 PM PDT 24
Peak memory 210396 kb
Host smart-0e9fb82a-6c24-4274-b08d-aa7e970bc2e8
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1319674907 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_hw_r
eset.1319674907
Directory /workspace/2.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_mem_rw_with_rand_reset.415506181
Short name T383
Test name
Test status
Simulation time 298202969 ps
CPU time 6.36 seconds
Started Apr 28 12:40:29 PM PDT 24
Finished Apr 28 12:40:37 PM PDT 24
Peak memory 210728 kb
Host smart-db7ab638-c585-4b1b-9778-619526ce5484
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=415506181 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 2.rom_ctrl_csr_mem_rw_with_rand_reset.415506181
Directory /workspace/2.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_rw.2675435366
Short name T73
Test name
Test status
Simulation time 1229879491 ps
CPU time 8.01 seconds
Started Apr 28 12:40:46 PM PDT 24
Finished Apr 28 12:40:54 PM PDT 24
Peak memory 210424 kb
Host smart-327c831b-70ed-4ff0-99a5-08bc0ea68e21
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2675435366 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_rw.2675435366
Directory /workspace/2.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_partial_access.2974695351
Short name T384
Test name
Test status
Simulation time 3748870607 ps
CPU time 14.71 seconds
Started Apr 28 12:40:34 PM PDT 24
Finished Apr 28 12:40:50 PM PDT 24
Peak memory 210336 kb
Host smart-18670e1e-ce97-4b3a-822d-b69ee3c0d1ad
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2974695351 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctr
l_mem_partial_access.2974695351
Directory /workspace/2.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_walk.1200620689
Short name T442
Test name
Test status
Simulation time 333248845 ps
CPU time 4.18 seconds
Started Apr 28 12:40:50 PM PDT 24
Finished Apr 28 12:40:55 PM PDT 24
Peak memory 210344 kb
Host smart-a303352e-409f-42bf-a194-7892cdf336f9
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1200620689 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_mem_walk
.1200620689
Directory /workspace/2.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_passthru_mem_tl_intg_err.3643329445
Short name T83
Test name
Test status
Simulation time 2449392271 ps
CPU time 27.57 seconds
Started Apr 28 12:40:46 PM PDT 24
Finished Apr 28 12:41:14 PM PDT 24
Peak memory 210476 kb
Host smart-ce921c68-a647-4d4f-a8c8-9795bf004144
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3643329445 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_pa
ssthru_mem_tl_intg_err.3643329445
Directory /workspace/2.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_same_csr_outstanding.3522708071
Short name T410
Test name
Test status
Simulation time 522851860 ps
CPU time 7.83 seconds
Started Apr 28 12:40:49 PM PDT 24
Finished Apr 28 12:40:57 PM PDT 24
Peak memory 210428 kb
Host smart-fb005e00-1942-473e-983b-8895ba67412d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3522708071 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_c
trl_same_csr_outstanding.3522708071
Directory /workspace/2.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_errors.819872373
Short name T449
Test name
Test status
Simulation time 5158196490 ps
CPU time 17.27 seconds
Started Apr 28 12:40:47 PM PDT 24
Finished Apr 28 12:41:05 PM PDT 24
Peak memory 218800 kb
Host smart-6cc4c536-6fd9-4f17-8af7-d4a791dcb2b5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=819872373 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_tl_errors.819872373
Directory /workspace/2.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_aliasing.3323175358
Short name T437
Test name
Test status
Simulation time 2962669832 ps
CPU time 12.77 seconds
Started Apr 28 12:40:43 PM PDT 24
Finished Apr 28 12:40:57 PM PDT 24
Peak memory 210472 kb
Host smart-f17dd225-e28f-4bbc-8188-fa772a3a343c
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3323175358 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_alia
sing.3323175358
Directory /workspace/3.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_bit_bash.2788371127
Short name T414
Test name
Test status
Simulation time 477268157 ps
CPU time 7.5 seconds
Started Apr 28 12:40:42 PM PDT 24
Finished Apr 28 12:40:51 PM PDT 24
Peak memory 210344 kb
Host smart-d898fe91-372a-4cb4-9b3f-e8d7920564f5
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2788371127 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_bit_
bash.2788371127
Directory /workspace/3.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_hw_reset.2814828066
Short name T451
Test name
Test status
Simulation time 835579084 ps
CPU time 7.21 seconds
Started Apr 28 12:40:45 PM PDT 24
Finished Apr 28 12:40:53 PM PDT 24
Peak memory 210352 kb
Host smart-99b5501d-60a6-4142-bfd9-df553f89d7f3
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2814828066 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_hw_r
eset.2814828066
Directory /workspace/3.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_mem_rw_with_rand_reset.3494166054
Short name T379
Test name
Test status
Simulation time 2565729535 ps
CPU time 12.28 seconds
Started Apr 28 12:40:57 PM PDT 24
Finished Apr 28 12:41:11 PM PDT 24
Peak memory 218748 kb
Host smart-330b6769-d50f-4666-88ce-bfd73d41d440
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3494166054 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 3.rom_ctrl_csr_mem_rw_with_rand_reset.3494166054
Directory /workspace/3.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_rw.383683923
Short name T443
Test name
Test status
Simulation time 1311685817 ps
CPU time 12.13 seconds
Started Apr 28 12:40:45 PM PDT 24
Finished Apr 28 12:40:58 PM PDT 24
Peak memory 210368 kb
Host smart-078475a4-1dc5-4355-b19a-90c1f0f38211
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=383683923 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_rw.383683923
Directory /workspace/3.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_partial_access.3744548591
Short name T390
Test name
Test status
Simulation time 8035623647 ps
CPU time 15.65 seconds
Started Apr 28 12:40:36 PM PDT 24
Finished Apr 28 12:40:52 PM PDT 24
Peak memory 210344 kb
Host smart-d2e050c4-1cda-49bf-9993-b87406fbc3a4
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3744548591 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctr
l_mem_partial_access.3744548591
Directory /workspace/3.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_walk.145185423
Short name T371
Test name
Test status
Simulation time 333121264 ps
CPU time 4.01 seconds
Started Apr 28 12:40:51 PM PDT 24
Finished Apr 28 12:40:55 PM PDT 24
Peak memory 210292 kb
Host smart-07230de4-c5ab-4792-99d1-75fb280428b7
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=145185423 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_mem_walk.
145185423
Directory /workspace/3.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_passthru_mem_tl_intg_err.2753121686
Short name T424
Test name
Test status
Simulation time 2150146132 ps
CPU time 27.76 seconds
Started Apr 28 12:40:36 PM PDT 24
Finished Apr 28 12:41:05 PM PDT 24
Peak memory 210500 kb
Host smart-d94c0f17-6a04-4514-89a8-7108d7de9f5e
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2753121686 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_pa
ssthru_mem_tl_intg_err.2753121686
Directory /workspace/3.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_same_csr_outstanding.1815508032
Short name T445
Test name
Test status
Simulation time 6275711709 ps
CPU time 13.42 seconds
Started Apr 28 12:40:34 PM PDT 24
Finished Apr 28 12:40:49 PM PDT 24
Peak memory 210560 kb
Host smart-9f579b22-f624-4f67-b870-220d73ac2c13
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1815508032 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_c
trl_same_csr_outstanding.1815508032
Directory /workspace/3.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_errors.2280618262
Short name T373
Test name
Test status
Simulation time 737957074 ps
CPU time 7.05 seconds
Started Apr 28 12:40:40 PM PDT 24
Finished Apr 28 12:40:48 PM PDT 24
Peak memory 218644 kb
Host smart-9286ff3f-f375-4bb6-b048-11af1e7ca66e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2280618262 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_tl_errors.2280618262
Directory /workspace/3.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_intg_err.568079780
Short name T127
Test name
Test status
Simulation time 5351277945 ps
CPU time 42.85 seconds
Started Apr 28 12:40:40 PM PDT 24
Finished Apr 28 12:41:24 PM PDT 24
Peak memory 211580 kb
Host smart-8b310b89-b040-4a8f-afe7-c948899b6ce8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=568079780 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_tl_int
g_err.568079780
Directory /workspace/3.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_aliasing.1424439913
Short name T395
Test name
Test status
Simulation time 18260074340 ps
CPU time 11.12 seconds
Started Apr 28 12:40:57 PM PDT 24
Finished Apr 28 12:41:10 PM PDT 24
Peak memory 210492 kb
Host smart-1f5d4cb2-0f57-452b-b4c4-66e067dc8343
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1424439913 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_alia
sing.1424439913
Directory /workspace/4.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_bit_bash.79062190
Short name T417
Test name
Test status
Simulation time 4116258541 ps
CPU time 7.43 seconds
Started Apr 28 12:41:07 PM PDT 24
Finished Apr 28 12:41:17 PM PDT 24
Peak memory 210456 kb
Host smart-05746272-2c48-4dbb-9433-5b5e708da9aa
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=79062190 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_bit_ba
sh.79062190
Directory /workspace/4.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_hw_reset.509123812
Short name T375
Test name
Test status
Simulation time 3097693036 ps
CPU time 16.11 seconds
Started Apr 28 12:40:32 PM PDT 24
Finished Apr 28 12:40:50 PM PDT 24
Peak memory 210496 kb
Host smart-9b76b67b-183b-4713-af2b-106f11857321
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=509123812 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_hw_re
set.509123812
Directory /workspace/4.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_mem_rw_with_rand_reset.1981051093
Short name T456
Test name
Test status
Simulation time 1403800923 ps
CPU time 12.13 seconds
Started Apr 28 12:40:39 PM PDT 24
Finished Apr 28 12:40:52 PM PDT 24
Peak memory 213076 kb
Host smart-dc48fa28-0f02-4f38-8f74-67d81990617e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1981051093 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 4.rom_ctrl_csr_mem_rw_with_rand_reset.1981051093
Directory /workspace/4.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_rw.24830799
Short name T438
Test name
Test status
Simulation time 14221688622 ps
CPU time 13.65 seconds
Started Apr 28 12:40:39 PM PDT 24
Finished Apr 28 12:40:54 PM PDT 24
Peak memory 210556 kb
Host smart-29b5c5af-f3db-43af-a3f9-80390e228987
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24830799 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_rw.24830799
Directory /workspace/4.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_partial_access.3862094327
Short name T455
Test name
Test status
Simulation time 347545898 ps
CPU time 4.05 seconds
Started Apr 28 12:40:31 PM PDT 24
Finished Apr 28 12:40:37 PM PDT 24
Peak memory 210276 kb
Host smart-c10c6f19-b22d-4735-9aa2-171be22c7235
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3862094327 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctr
l_mem_partial_access.3862094327
Directory /workspace/4.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_walk.3482387224
Short name T462
Test name
Test status
Simulation time 333517399 ps
CPU time 4.18 seconds
Started Apr 28 12:40:45 PM PDT 24
Finished Apr 28 12:40:50 PM PDT 24
Peak memory 210320 kb
Host smart-26a46538-52d8-4701-93b4-7f494391e5db
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3482387224 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_mem_walk
.3482387224
Directory /workspace/4.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_passthru_mem_tl_intg_err.1600144460
Short name T113
Test name
Test status
Simulation time 14367949155 ps
CPU time 50.95 seconds
Started Apr 28 12:40:28 PM PDT 24
Finished Apr 28 12:41:20 PM PDT 24
Peak memory 210584 kb
Host smart-6ab49fa2-ccf8-43a2-aca8-2f649540dc9c
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1600144460 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_pa
ssthru_mem_tl_intg_err.1600144460
Directory /workspace/4.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_same_csr_outstanding.3061937936
Short name T464
Test name
Test status
Simulation time 91061128 ps
CPU time 4.32 seconds
Started Apr 28 12:40:29 PM PDT 24
Finished Apr 28 12:40:35 PM PDT 24
Peak memory 210408 kb
Host smart-3f8172f2-c8e3-4f1e-bc5f-80042def2993
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3061937936 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_c
trl_same_csr_outstanding.3061937936
Directory /workspace/4.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_errors.110576274
Short name T444
Test name
Test status
Simulation time 1575764421 ps
CPU time 11.7 seconds
Started Apr 28 12:40:56 PM PDT 24
Finished Apr 28 12:41:09 PM PDT 24
Peak memory 218740 kb
Host smart-fbe8ec38-5654-4ce4-9037-fc18697dcc3a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=110576274 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_tl_errors.110576274
Directory /workspace/4.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_intg_err.2469874753
Short name T123
Test name
Test status
Simulation time 1532803954 ps
CPU time 43.7 seconds
Started Apr 28 12:40:29 PM PDT 24
Finished Apr 28 12:41:14 PM PDT 24
Peak memory 211208 kb
Host smart-39c37cdb-d0cc-49d0-8dd0-5f14786e21ba
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2469874753 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_tl_in
tg_err.2469874753
Directory /workspace/4.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_mem_rw_with_rand_reset.1024872961
Short name T408
Test name
Test status
Simulation time 1905752845 ps
CPU time 10.23 seconds
Started Apr 28 12:40:33 PM PDT 24
Finished Apr 28 12:40:44 PM PDT 24
Peak memory 218652 kb
Host smart-15f6626b-b097-4303-94e8-e4ec87d6cc63
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1024872961 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 5.rom_ctrl_csr_mem_rw_with_rand_reset.1024872961
Directory /workspace/5.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_rw.3250487159
Short name T91
Test name
Test status
Simulation time 3996345801 ps
CPU time 15.49 seconds
Started Apr 28 12:40:48 PM PDT 24
Finished Apr 28 12:41:04 PM PDT 24
Peak memory 210372 kb
Host smart-5d6143b8-baf0-4fb6-8c4c-e7deb6575c1b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3250487159 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_csr_rw.3250487159
Directory /workspace/5.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_passthru_mem_tl_intg_err.2151166180
Short name T93
Test name
Test status
Simulation time 1621463464 ps
CPU time 18.98 seconds
Started Apr 28 12:40:40 PM PDT 24
Finished Apr 28 12:41:00 PM PDT 24
Peak memory 210384 kb
Host smart-1ae28e07-642c-4f89-a9ca-a29e72ba530d
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2151166180 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_pa
ssthru_mem_tl_intg_err.2151166180
Directory /workspace/5.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_same_csr_outstanding.4183817549
Short name T450
Test name
Test status
Simulation time 6872834149 ps
CPU time 9.37 seconds
Started Apr 28 12:40:43 PM PDT 24
Finished Apr 28 12:40:54 PM PDT 24
Peak memory 210528 kb
Host smart-fab89304-827c-4294-808f-b54d122b8c85
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4183817549 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_c
trl_same_csr_outstanding.4183817549
Directory /workspace/5.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_errors.1793387093
Short name T454
Test name
Test status
Simulation time 412818557 ps
CPU time 7.82 seconds
Started Apr 28 12:40:56 PM PDT 24
Finished Apr 28 12:41:06 PM PDT 24
Peak memory 218664 kb
Host smart-7710b9ac-1412-4f11-b610-220d5665021f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1793387093 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_tl_errors.1793387093
Directory /workspace/5.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_intg_err.2619933582
Short name T431
Test name
Test status
Simulation time 6064016432 ps
CPU time 75.08 seconds
Started Apr 28 12:40:44 PM PDT 24
Finished Apr 28 12:42:00 PM PDT 24
Peak memory 218688 kb
Host smart-e3474190-fa0f-4508-bac6-24a594f1a532
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2619933582 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_tl_in
tg_err.2619933582
Directory /workspace/5.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_mem_rw_with_rand_reset.2637085889
Short name T423
Test name
Test status
Simulation time 177650331 ps
CPU time 4.32 seconds
Started Apr 28 12:40:40 PM PDT 24
Finished Apr 28 12:40:45 PM PDT 24
Peak memory 210904 kb
Host smart-ec563fd0-bce2-4b4f-b6f5-ffb3ccce52fd
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2637085889 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 6.rom_ctrl_csr_mem_rw_with_rand_reset.2637085889
Directory /workspace/6.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_rw.3381341179
Short name T465
Test name
Test status
Simulation time 2954699995 ps
CPU time 7.64 seconds
Started Apr 28 12:41:00 PM PDT 24
Finished Apr 28 12:41:09 PM PDT 24
Peak memory 210480 kb
Host smart-7ebf709a-84eb-4895-8510-39ab9c6d3526
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3381341179 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_csr_rw.3381341179
Directory /workspace/6.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_passthru_mem_tl_intg_err.1559349024
Short name T71
Test name
Test status
Simulation time 7975456221 ps
CPU time 70.65 seconds
Started Apr 28 12:40:43 PM PDT 24
Finished Apr 28 12:42:00 PM PDT 24
Peak memory 210584 kb
Host smart-3c690488-276a-44e0-ad43-bb79cf20c1c6
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1559349024 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_pa
ssthru_mem_tl_intg_err.1559349024
Directory /workspace/6.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_same_csr_outstanding.2784597391
Short name T75
Test name
Test status
Simulation time 10448116237 ps
CPU time 16.21 seconds
Started Apr 28 12:40:49 PM PDT 24
Finished Apr 28 12:41:06 PM PDT 24
Peak memory 210572 kb
Host smart-8a958955-4024-44a4-a8e4-8a6b9e111807
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2784597391 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_c
trl_same_csr_outstanding.2784597391
Directory /workspace/6.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_errors.1292243243
Short name T402
Test name
Test status
Simulation time 8116198273 ps
CPU time 19.9 seconds
Started Apr 28 12:40:39 PM PDT 24
Finished Apr 28 12:40:59 PM PDT 24
Peak memory 218860 kb
Host smart-c246e9a4-4d18-45a4-a088-b4dd2eae0d6a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1292243243 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_tl_errors.1292243243
Directory /workspace/6.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_intg_err.3222572772
Short name T121
Test name
Test status
Simulation time 4455621247 ps
CPU time 72.66 seconds
Started Apr 28 12:40:33 PM PDT 24
Finished Apr 28 12:41:47 PM PDT 24
Peak memory 218696 kb
Host smart-95d08a5e-639c-4452-bba8-645915b204eb
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3222572772 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_tl_in
tg_err.3222572772
Directory /workspace/6.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_mem_rw_with_rand_reset.1524844420
Short name T422
Test name
Test status
Simulation time 630578587 ps
CPU time 8.41 seconds
Started Apr 28 12:40:47 PM PDT 24
Finished Apr 28 12:40:57 PM PDT 24
Peak memory 211652 kb
Host smart-3be86888-ecf9-4cc7-bd80-d728e4f81d51
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1524844420 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 7.rom_ctrl_csr_mem_rw_with_rand_reset.1524844420
Directory /workspace/7.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_rw.726766195
Short name T62
Test name
Test status
Simulation time 1745318130 ps
CPU time 13.01 seconds
Started Apr 28 12:40:56 PM PDT 24
Finished Apr 28 12:41:10 PM PDT 24
Peak memory 210384 kb
Host smart-f111b561-a482-4caa-aa7d-9a53af5d20b8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=726766195 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_csr_rw.726766195
Directory /workspace/7.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_passthru_mem_tl_intg_err.3656026673
Short name T74
Test name
Test status
Simulation time 9790302640 ps
CPU time 84.14 seconds
Started Apr 28 12:40:35 PM PDT 24
Finished Apr 28 12:42:00 PM PDT 24
Peak memory 210580 kb
Host smart-25527eda-0660-4242-a4aa-6bb7284b59e9
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3656026673 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_pa
ssthru_mem_tl_intg_err.3656026673
Directory /workspace/7.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_same_csr_outstanding.3220046847
Short name T419
Test name
Test status
Simulation time 2283880790 ps
CPU time 11.36 seconds
Started Apr 28 12:40:28 PM PDT 24
Finished Apr 28 12:40:41 PM PDT 24
Peak memory 210520 kb
Host smart-016ac6c6-c1f2-46d8-b30a-7392e840e2d7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3220046847 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_c
trl_same_csr_outstanding.3220046847
Directory /workspace/7.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_errors.100292945
Short name T378
Test name
Test status
Simulation time 4210594074 ps
CPU time 18.85 seconds
Started Apr 28 12:40:31 PM PDT 24
Finished Apr 28 12:40:51 PM PDT 24
Peak memory 218708 kb
Host smart-93b20f2f-a4f1-4a48-9003-eef2ac55e723
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=100292945 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_tl_errors.100292945
Directory /workspace/7.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_intg_err.419983939
Short name T58
Test name
Test status
Simulation time 923248538 ps
CPU time 70.17 seconds
Started Apr 28 12:40:59 PM PDT 24
Finished Apr 28 12:42:11 PM PDT 24
Peak memory 211436 kb
Host smart-86cb80a3-5ff4-4e36-b550-5e38b7052835
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=419983939 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_tl_int
g_err.419983939
Directory /workspace/7.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_mem_rw_with_rand_reset.2263950027
Short name T421
Test name
Test status
Simulation time 94380947 ps
CPU time 4.58 seconds
Started Apr 28 12:40:55 PM PDT 24
Finished Apr 28 12:41:00 PM PDT 24
Peak memory 211844 kb
Host smart-6e6b2a01-16c7-4274-ba30-e3ce574e4f05
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2263950027 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 8.rom_ctrl_csr_mem_rw_with_rand_reset.2263950027
Directory /workspace/8.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_rw.331959687
Short name T406
Test name
Test status
Simulation time 1797663494 ps
CPU time 14.17 seconds
Started Apr 28 12:40:54 PM PDT 24
Finished Apr 28 12:41:09 PM PDT 24
Peak memory 210392 kb
Host smart-17f67f5f-762b-42ad-98f9-d68472f009fa
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=331959687 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_csr_rw.331959687
Directory /workspace/8.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_passthru_mem_tl_intg_err.762698678
Short name T469
Test name
Test status
Simulation time 8966587913 ps
CPU time 28.52 seconds
Started Apr 28 12:40:46 PM PDT 24
Finished Apr 28 12:41:15 PM PDT 24
Peak memory 210556 kb
Host smart-0c2f5090-4ef5-496d-9353-e4ca85f6a9e0
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=762698678 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_pas
sthru_mem_tl_intg_err.762698678
Directory /workspace/8.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_same_csr_outstanding.3880638235
Short name T386
Test name
Test status
Simulation time 143565165 ps
CPU time 7 seconds
Started Apr 28 12:40:32 PM PDT 24
Finished Apr 28 12:40:45 PM PDT 24
Peak memory 210440 kb
Host smart-74423622-83b0-44a9-853b-4bf4085e6f75
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3880638235 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_c
trl_same_csr_outstanding.3880638235
Directory /workspace/8.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_errors.903531927
Short name T463
Test name
Test status
Simulation time 1589589485 ps
CPU time 11.05 seconds
Started Apr 28 12:40:29 PM PDT 24
Finished Apr 28 12:40:42 PM PDT 24
Peak memory 218736 kb
Host smart-71507060-e511-4ddd-a57b-a61f78967cca
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=903531927 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_tl_errors.903531927
Directory /workspace/8.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_intg_err.2153510372
Short name T128
Test name
Test status
Simulation time 3542462427 ps
CPU time 78.25 seconds
Started Apr 28 12:40:39 PM PDT 24
Finished Apr 28 12:41:58 PM PDT 24
Peak memory 218660 kb
Host smart-2ffaf0c3-27a1-4a52-97bb-38acdfc8e3b7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2153510372 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_tl_in
tg_err.2153510372
Directory /workspace/8.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_mem_rw_with_rand_reset.300139634
Short name T440
Test name
Test status
Simulation time 505128689 ps
CPU time 4.62 seconds
Started Apr 28 12:40:32 PM PDT 24
Finished Apr 28 12:40:39 PM PDT 24
Peak memory 211988 kb
Host smart-1bb5e6bb-6194-48e2-8efb-6165f0842311
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=300139634 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 9.rom_ctrl_csr_mem_rw_with_rand_reset.300139634
Directory /workspace/9.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_rw.928535646
Short name T441
Test name
Test status
Simulation time 1566078508 ps
CPU time 13.32 seconds
Started Apr 28 12:40:53 PM PDT 24
Finished Apr 28 12:41:07 PM PDT 24
Peak memory 210304 kb
Host smart-08d02b0b-786f-47f9-90a1-5fd55026a2f8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=928535646 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_csr_rw.928535646
Directory /workspace/9.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_passthru_mem_tl_intg_err.2912925800
Short name T432
Test name
Test status
Simulation time 5258382940 ps
CPU time 49 seconds
Started Apr 28 12:41:06 PM PDT 24
Finished Apr 28 12:41:56 PM PDT 24
Peak memory 210552 kb
Host smart-56de0478-cbb1-46f3-9392-56b6bc251bd3
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2912925800 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_pa
ssthru_mem_tl_intg_err.2912925800
Directory /workspace/9.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_same_csr_outstanding.3478891023
Short name T104
Test name
Test status
Simulation time 903292382 ps
CPU time 9.49 seconds
Started Apr 28 12:40:37 PM PDT 24
Finished Apr 28 12:40:47 PM PDT 24
Peak memory 210424 kb
Host smart-07464977-320f-4ed5-96e6-3f975f056573
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3478891023 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_c
trl_same_csr_outstanding.3478891023
Directory /workspace/9.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_errors.2740718135
Short name T415
Test name
Test status
Simulation time 920717492 ps
CPU time 6.79 seconds
Started Apr 28 12:41:24 PM PDT 24
Finished Apr 28 12:41:34 PM PDT 24
Peak memory 218672 kb
Host smart-d17f4c3a-8bb6-43c9-90bc-8414991ef8e1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2740718135 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_tl_errors.2740718135
Directory /workspace/9.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_intg_err.2444423719
Short name T435
Test name
Test status
Simulation time 2864230467 ps
CPU time 74.35 seconds
Started Apr 28 12:40:58 PM PDT 24
Finished Apr 28 12:42:15 PM PDT 24
Peak memory 218592 kb
Host smart-fa6256ce-8dc5-44a4-ba20-432b6d0b91e1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2444423719 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_tl_in
tg_err.2444423719
Directory /workspace/9.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/0.rom_ctrl_alert_test.1911685501
Short name T342
Test name
Test status
Simulation time 1480626820 ps
CPU time 12.97 seconds
Started Apr 28 12:40:44 PM PDT 24
Finished Apr 28 12:40:58 PM PDT 24
Peak memory 211312 kb
Host smart-1caf906b-c9f1-44c1-b297-d01c54bd2c2b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1911685501 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_alert_test.1911685501
Directory /workspace/0.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/0.rom_ctrl_corrupt_sig_fatal_chk.2949320815
Short name T350
Test name
Test status
Simulation time 6321144240 ps
CPU time 99.13 seconds
Started Apr 28 12:40:47 PM PDT 24
Finished Apr 28 12:42:27 PM PDT 24
Peak memory 229256 kb
Host smart-b3ff4ae8-eca1-4a8d-9300-60a00c1a8eec
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2949320815 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_c
orrupt_sig_fatal_chk.2949320815
Directory /workspace/0.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/0.rom_ctrl_max_throughput_chk.943053870
Short name T280
Test name
Test status
Simulation time 2147820521 ps
CPU time 16.56 seconds
Started Apr 28 12:41:01 PM PDT 24
Finished Apr 28 12:41:19 PM PDT 24
Peak memory 211352 kb
Host smart-fd36d9ed-7306-4301-aa88-1f72f9b60253
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=943053870 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_max_throughput_chk.943053870
Directory /workspace/0.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/0.rom_ctrl_sec_cm.4135263387
Short name T31
Test name
Test status
Simulation time 1206191468 ps
CPU time 51.62 seconds
Started Apr 28 12:40:58 PM PDT 24
Finished Apr 28 12:41:52 PM PDT 24
Peak memory 230460 kb
Host smart-ef24695f-4d15-4cab-85fe-f1c9f41267f1
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4135263387 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_sec_cm.4135263387
Directory /workspace/0.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/0.rom_ctrl_smoke.4133080987
Short name T97
Test name
Test status
Simulation time 4813414427 ps
CPU time 22.91 seconds
Started Apr 28 12:40:56 PM PDT 24
Finished Apr 28 12:41:20 PM PDT 24
Peak memory 213808 kb
Host smart-c362fcfe-8969-4a7a-9b63-e49a0b0bb74c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4133080987 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_smoke.4133080987
Directory /workspace/0.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/0.rom_ctrl_stress_all.3373599571
Short name T180
Test name
Test status
Simulation time 224188502 ps
CPU time 15.55 seconds
Started Apr 28 12:41:00 PM PDT 24
Finished Apr 28 12:41:17 PM PDT 24
Peak memory 214616 kb
Host smart-4ee27bc2-8f64-4eec-adc2-05b56351782c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3373599571 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 0.rom_ctrl_stress_all.3373599571
Directory /workspace/0.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/1.rom_ctrl_alert_test.4218444645
Short name T368
Test name
Test status
Simulation time 22654790108 ps
CPU time 14.16 seconds
Started Apr 28 12:41:08 PM PDT 24
Finished Apr 28 12:41:25 PM PDT 24
Peak memory 211408 kb
Host smart-50b4a905-d970-4d94-85a0-0a8c6cbaf175
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4218444645 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_alert_test.4218444645
Directory /workspace/1.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/1.rom_ctrl_corrupt_sig_fatal_chk.1395506679
Short name T107
Test name
Test status
Simulation time 77898136331 ps
CPU time 230.06 seconds
Started Apr 28 12:40:57 PM PDT 24
Finished Apr 28 12:44:48 PM PDT 24
Peak memory 212260 kb
Host smart-d81a5749-7ca3-4ace-96b0-2938d0aa7023
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1395506679 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_c
orrupt_sig_fatal_chk.1395506679
Directory /workspace/1.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/1.rom_ctrl_kmac_err_chk.285461727
Short name T244
Test name
Test status
Simulation time 3096023369 ps
CPU time 25.37 seconds
Started Apr 28 12:41:15 PM PDT 24
Finished Apr 28 12:41:42 PM PDT 24
Peak memory 212084 kb
Host smart-95c5f244-ce0f-4749-8cfc-63270fe51a85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=285461727 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_kmac_err_chk.285461727
Directory /workspace/1.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/1.rom_ctrl_max_throughput_chk.483967307
Short name T201
Test name
Test status
Simulation time 2207814754 ps
CPU time 12.03 seconds
Started Apr 28 12:41:14 PM PDT 24
Finished Apr 28 12:41:28 PM PDT 24
Peak memory 211320 kb
Host smart-8de4b73f-c5a5-4c2f-a0ef-ab30175cd3c7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=483967307 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_max_throughput_chk.483967307
Directory /workspace/1.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/1.rom_ctrl_sec_cm.905025770
Short name T32
Test name
Test status
Simulation time 1113802398 ps
CPU time 103.5 seconds
Started Apr 28 12:41:08 PM PDT 24
Finished Apr 28 12:42:54 PM PDT 24
Peak memory 233712 kb
Host smart-5dff9ba9-fd4b-4d2d-bdcb-dc4463034ace
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=905025770 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_sec_cm.905025770
Directory /workspace/1.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/1.rom_ctrl_smoke.1264522237
Short name T218
Test name
Test status
Simulation time 6576389096 ps
CPU time 32.76 seconds
Started Apr 28 12:41:00 PM PDT 24
Finished Apr 28 12:41:35 PM PDT 24
Peak memory 219632 kb
Host smart-8dc80332-3147-4d5a-ac26-52f9ffec347a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1264522237 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_smoke.1264522237
Directory /workspace/1.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/1.rom_ctrl_stress_all.4110097413
Short name T325
Test name
Test status
Simulation time 6208190783 ps
CPU time 40.19 seconds
Started Apr 28 12:40:40 PM PDT 24
Finished Apr 28 12:41:21 PM PDT 24
Peak memory 216240 kb
Host smart-c0e852f4-be11-4aef-af5c-3b94efe344d4
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4110097413 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 1.rom_ctrl_stress_all.4110097413
Directory /workspace/1.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/10.rom_ctrl_alert_test.3445936286
Short name T272
Test name
Test status
Simulation time 1997056582 ps
CPU time 16.52 seconds
Started Apr 28 12:40:53 PM PDT 24
Finished Apr 28 12:41:10 PM PDT 24
Peak memory 211300 kb
Host smart-56acdc05-d895-4617-83fc-51b0ee5063f4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3445936286 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_alert_test.3445936286
Directory /workspace/10.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/10.rom_ctrl_corrupt_sig_fatal_chk.2567869282
Short name T285
Test name
Test status
Simulation time 2966847369 ps
CPU time 115.28 seconds
Started Apr 28 12:41:02 PM PDT 24
Finished Apr 28 12:42:59 PM PDT 24
Peak memory 233992 kb
Host smart-ac84643c-81f3-49b8-bf68-4e17ccab05e5
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2567869282 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_
corrupt_sig_fatal_chk.2567869282
Directory /workspace/10.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/10.rom_ctrl_kmac_err_chk.4222583911
Short name T110
Test name
Test status
Simulation time 1538320789 ps
CPU time 19.2 seconds
Started Apr 28 12:41:04 PM PDT 24
Finished Apr 28 12:41:25 PM PDT 24
Peak memory 211400 kb
Host smart-b3211fa4-0706-4712-88d2-89f621ed120c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4222583911 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_kmac_err_chk.4222583911
Directory /workspace/10.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/10.rom_ctrl_max_throughput_chk.2015657389
Short name T252
Test name
Test status
Simulation time 5252291878 ps
CPU time 13.32 seconds
Started Apr 28 12:40:57 PM PDT 24
Finished Apr 28 12:41:13 PM PDT 24
Peak memory 211340 kb
Host smart-8898206e-9c6c-41be-b6dc-f584a05a51bb
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2015657389 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_max_throughput_chk.2015657389
Directory /workspace/10.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/10.rom_ctrl_smoke.2139123571
Short name T297
Test name
Test status
Simulation time 2857164407 ps
CPU time 26.13 seconds
Started Apr 28 12:41:06 PM PDT 24
Finished Apr 28 12:41:34 PM PDT 24
Peak memory 213824 kb
Host smart-79ef91d6-3202-4cb2-8fc8-09144e5a3a2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2139123571 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_smoke.2139123571
Directory /workspace/10.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/10.rom_ctrl_stress_all.1027954570
Short name T359
Test name
Test status
Simulation time 12852496684 ps
CPU time 62.02 seconds
Started Apr 28 12:41:08 PM PDT 24
Finished Apr 28 12:42:12 PM PDT 24
Peak memory 213628 kb
Host smart-112a5ad7-bcc9-42a6-897f-aa92ccdec14f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1027954570 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 10.rom_ctrl_stress_all.1027954570
Directory /workspace/10.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/11.rom_ctrl_alert_test.556236013
Short name T17
Test name
Test status
Simulation time 3570665463 ps
CPU time 14.31 seconds
Started Apr 28 12:41:13 PM PDT 24
Finished Apr 28 12:41:29 PM PDT 24
Peak memory 211416 kb
Host smart-8f296e1e-96a1-4907-a362-0d4de45763ea
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=556236013 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_alert_test.556236013
Directory /workspace/11.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/11.rom_ctrl_corrupt_sig_fatal_chk.409010980
Short name T158
Test name
Test status
Simulation time 12156582875 ps
CPU time 143.57 seconds
Started Apr 28 12:40:50 PM PDT 24
Finished Apr 28 12:43:20 PM PDT 24
Peak memory 212628 kb
Host smart-d4d6ca13-2def-422d-b071-2c7d1f39f292
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=409010980 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_c
orrupt_sig_fatal_chk.409010980
Directory /workspace/11.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/11.rom_ctrl_kmac_err_chk.1240962146
Short name T210
Test name
Test status
Simulation time 4505636006 ps
CPU time 25.46 seconds
Started Apr 28 12:41:20 PM PDT 24
Finished Apr 28 12:41:47 PM PDT 24
Peak memory 212404 kb
Host smart-7026b582-de7b-490b-9da5-ca057a774041
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1240962146 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_kmac_err_chk.1240962146
Directory /workspace/11.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/11.rom_ctrl_max_throughput_chk.3573807678
Short name T193
Test name
Test status
Simulation time 2147745360 ps
CPU time 17.78 seconds
Started Apr 28 12:41:05 PM PDT 24
Finished Apr 28 12:41:24 PM PDT 24
Peak memory 211328 kb
Host smart-e6db7542-4f7f-4fba-969d-3c0e56bf100d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3573807678 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_max_throughput_chk.3573807678
Directory /workspace/11.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/11.rom_ctrl_smoke.3112632855
Short name T271
Test name
Test status
Simulation time 17758488994 ps
CPU time 32.88 seconds
Started Apr 28 12:40:49 PM PDT 24
Finished Apr 28 12:41:23 PM PDT 24
Peak memory 214336 kb
Host smart-bbdb16be-be1c-48bc-8e6c-5a1da6d3a165
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3112632855 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_smoke.3112632855
Directory /workspace/11.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/11.rom_ctrl_stress_all.977005069
Short name T220
Test name
Test status
Simulation time 459683795 ps
CPU time 8.93 seconds
Started Apr 28 12:40:51 PM PDT 24
Finished Apr 28 12:41:00 PM PDT 24
Peak memory 211324 kb
Host smart-5c3294dc-b8a9-4fe3-938f-faa713dfdcf1
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=977005069 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 11.rom_ctrl_stress_all.977005069
Directory /workspace/11.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/12.rom_ctrl_alert_test.1662639846
Short name T164
Test name
Test status
Simulation time 88960806 ps
CPU time 4.3 seconds
Started Apr 28 12:40:57 PM PDT 24
Finished Apr 28 12:41:03 PM PDT 24
Peak memory 211372 kb
Host smart-a3cf9451-1667-46d6-a54d-79689f514bc3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1662639846 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_alert_test.1662639846
Directory /workspace/12.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/12.rom_ctrl_corrupt_sig_fatal_chk.4221120281
Short name T258
Test name
Test status
Simulation time 52707161065 ps
CPU time 145.86 seconds
Started Apr 28 12:40:55 PM PDT 24
Finished Apr 28 12:43:22 PM PDT 24
Peak memory 233228 kb
Host smart-70cfb8a7-a044-47cf-9312-15f49165fd98
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4221120281 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_
corrupt_sig_fatal_chk.4221120281
Directory /workspace/12.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/12.rom_ctrl_kmac_err_chk.2471741616
Short name T178
Test name
Test status
Simulation time 171597374 ps
CPU time 9.58 seconds
Started Apr 28 12:41:12 PM PDT 24
Finished Apr 28 12:41:24 PM PDT 24
Peak memory 212100 kb
Host smart-a1bc03bd-69aa-436d-9fbf-3d6626220ae8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2471741616 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_kmac_err_chk.2471741616
Directory /workspace/12.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/12.rom_ctrl_max_throughput_chk.2659539943
Short name T332
Test name
Test status
Simulation time 2088169886 ps
CPU time 8.96 seconds
Started Apr 28 12:41:15 PM PDT 24
Finished Apr 28 12:41:26 PM PDT 24
Peak memory 211328 kb
Host smart-f8b9a2b3-8f5a-4e5b-8b3b-c10f881456e4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2659539943 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_max_throughput_chk.2659539943
Directory /workspace/12.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/12.rom_ctrl_smoke.2817300921
Short name T261
Test name
Test status
Simulation time 4366146934 ps
CPU time 15.99 seconds
Started Apr 28 12:40:57 PM PDT 24
Finished Apr 28 12:41:15 PM PDT 24
Peak memory 213744 kb
Host smart-b51fa053-908f-4b6a-b434-2e07512dec4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2817300921 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_smoke.2817300921
Directory /workspace/12.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/12.rom_ctrl_stress_all.149345817
Short name T310
Test name
Test status
Simulation time 2948889700 ps
CPU time 29.96 seconds
Started Apr 28 12:40:42 PM PDT 24
Finished Apr 28 12:41:13 PM PDT 24
Peak memory 214832 kb
Host smart-0198b5f3-3d1d-4bf4-8389-d25389e1367f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=149345817 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 12.rom_ctrl_stress_all.149345817
Directory /workspace/12.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/13.rom_ctrl_alert_test.102200488
Short name T177
Test name
Test status
Simulation time 87498430 ps
CPU time 4.4 seconds
Started Apr 28 12:40:58 PM PDT 24
Finished Apr 28 12:41:05 PM PDT 24
Peak memory 211316 kb
Host smart-00fed100-63d5-42d1-bb2f-ba43cee0878e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=102200488 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_alert_test.102200488
Directory /workspace/13.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/13.rom_ctrl_corrupt_sig_fatal_chk.3976031764
Short name T312
Test name
Test status
Simulation time 5229381179 ps
CPU time 66.28 seconds
Started Apr 28 12:40:52 PM PDT 24
Finished Apr 28 12:42:04 PM PDT 24
Peak memory 212616 kb
Host smart-c0b0f452-2ea1-4130-94af-3987f7cd82d4
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3976031764 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_
corrupt_sig_fatal_chk.3976031764
Directory /workspace/13.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/13.rom_ctrl_smoke.1603423888
Short name T80
Test name
Test status
Simulation time 2285854032 ps
CPU time 14.44 seconds
Started Apr 28 12:40:59 PM PDT 24
Finished Apr 28 12:41:15 PM PDT 24
Peak memory 211612 kb
Host smart-1da1c199-8fa5-43e2-af72-0f95fc45b4df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1603423888 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_smoke.1603423888
Directory /workspace/13.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/13.rom_ctrl_stress_all.22751595
Short name T326
Test name
Test status
Simulation time 16421587262 ps
CPU time 31.31 seconds
Started Apr 28 12:41:01 PM PDT 24
Finished Apr 28 12:41:34 PM PDT 24
Peak memory 219500 kb
Host smart-b776c70e-644c-4f51-a45d-775a1b2c9305
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22751595 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +U
VM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n
ame 13.rom_ctrl_stress_all.22751595
Directory /workspace/13.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/13.rom_ctrl_stress_all_with_rand_reset.2972292407
Short name T120
Test name
Test status
Simulation time 49934906309 ps
CPU time 1995.33 seconds
Started Apr 28 12:40:52 PM PDT 24
Finished Apr 28 01:14:08 PM PDT 24
Peak memory 238676 kb
Host smart-1f7b4733-b72f-4803-b6f5-c12a9178a7bb
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2972292407 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_stress_all_with_rand_reset.2972292407
Directory /workspace/13.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/14.rom_ctrl_alert_test.1518191971
Short name T34
Test name
Test status
Simulation time 5728594680 ps
CPU time 12.6 seconds
Started Apr 28 12:41:10 PM PDT 24
Finished Apr 28 12:41:25 PM PDT 24
Peak memory 211436 kb
Host smart-553acc84-d3e5-43f4-a694-9fddae3dcb7f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1518191971 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_alert_test.1518191971
Directory /workspace/14.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/14.rom_ctrl_corrupt_sig_fatal_chk.862411363
Short name T328
Test name
Test status
Simulation time 112164279037 ps
CPU time 258.68 seconds
Started Apr 28 12:40:52 PM PDT 24
Finished Apr 28 12:45:12 PM PDT 24
Peak memory 230972 kb
Host smart-759edd33-53a4-41ec-b945-b995dafa7c7b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=862411363 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_c
orrupt_sig_fatal_chk.862411363
Directory /workspace/14.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/14.rom_ctrl_kmac_err_chk.3830119407
Short name T344
Test name
Test status
Simulation time 752794946 ps
CPU time 12.13 seconds
Started Apr 28 12:41:10 PM PDT 24
Finished Apr 28 12:41:25 PM PDT 24
Peak memory 212100 kb
Host smart-fbef0213-dc70-41c2-92ff-7a265a148309
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3830119407 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_kmac_err_chk.3830119407
Directory /workspace/14.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/14.rom_ctrl_max_throughput_chk.3688387367
Short name T330
Test name
Test status
Simulation time 3585031641 ps
CPU time 10.92 seconds
Started Apr 28 12:41:12 PM PDT 24
Finished Apr 28 12:41:24 PM PDT 24
Peak memory 211328 kb
Host smart-e5528f82-88de-453d-aba9-bb1205e41719
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3688387367 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_max_throughput_chk.3688387367
Directory /workspace/14.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/14.rom_ctrl_smoke.2625729390
Short name T231
Test name
Test status
Simulation time 4968773298 ps
CPU time 17.5 seconds
Started Apr 28 12:41:08 PM PDT 24
Finished Apr 28 12:41:28 PM PDT 24
Peak memory 213332 kb
Host smart-51e82175-978b-4390-886e-9f8906be0cf6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2625729390 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_smoke.2625729390
Directory /workspace/14.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/14.rom_ctrl_stress_all.2184435483
Short name T160
Test name
Test status
Simulation time 2122667920 ps
CPU time 10.56 seconds
Started Apr 28 12:40:59 PM PDT 24
Finished Apr 28 12:41:11 PM PDT 24
Peak memory 211248 kb
Host smart-3b7ff5d3-b4c4-424f-af53-99930bc4ce1e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2184435483 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 14.rom_ctrl_stress_all.2184435483
Directory /workspace/14.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/14.rom_ctrl_stress_all_with_rand_reset.1181845553
Short name T21
Test name
Test status
Simulation time 86065525729 ps
CPU time 10368.2 seconds
Started Apr 28 12:41:08 PM PDT 24
Finished Apr 28 03:33:59 PM PDT 24
Peak memory 237980 kb
Host smart-31f9095e-3c79-4489-b15d-3d41293ba9b2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1181845553 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_stress_all_with_rand_reset.1181845553
Directory /workspace/14.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/15.rom_ctrl_alert_test.2039965324
Short name T166
Test name
Test status
Simulation time 3324896110 ps
CPU time 10.34 seconds
Started Apr 28 12:40:56 PM PDT 24
Finished Apr 28 12:41:08 PM PDT 24
Peak memory 211428 kb
Host smart-d9472365-9250-4d2d-85ea-589b6c37f8d7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2039965324 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_alert_test.2039965324
Directory /workspace/15.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/15.rom_ctrl_corrupt_sig_fatal_chk.4106703720
Short name T296
Test name
Test status
Simulation time 64399736948 ps
CPU time 222.34 seconds
Started Apr 28 12:41:23 PM PDT 24
Finished Apr 28 12:45:11 PM PDT 24
Peak memory 228292 kb
Host smart-1c40fb48-5c5b-4fec-bdac-c361edd35e5c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4106703720 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_
corrupt_sig_fatal_chk.4106703720
Directory /workspace/15.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/15.rom_ctrl_kmac_err_chk.4237305803
Short name T209
Test name
Test status
Simulation time 2380190880 ps
CPU time 23.43 seconds
Started Apr 28 12:41:12 PM PDT 24
Finished Apr 28 12:41:38 PM PDT 24
Peak memory 212460 kb
Host smart-b50a2db9-2108-4cea-9404-b3c8f20bd9b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4237305803 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_kmac_err_chk.4237305803
Directory /workspace/15.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/15.rom_ctrl_max_throughput_chk.2071882989
Short name T198
Test name
Test status
Simulation time 1010603272 ps
CPU time 11.78 seconds
Started Apr 28 12:41:02 PM PDT 24
Finished Apr 28 12:41:16 PM PDT 24
Peak memory 211312 kb
Host smart-682b4cbc-b444-4be6-aa6f-624ac5520d45
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2071882989 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_max_throughput_chk.2071882989
Directory /workspace/15.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/15.rom_ctrl_smoke.4042707149
Short name T6
Test name
Test status
Simulation time 2157463218 ps
CPU time 23.74 seconds
Started Apr 28 12:41:02 PM PDT 24
Finished Apr 28 12:41:28 PM PDT 24
Peak memory 219596 kb
Host smart-cb62ced8-90c0-4182-b39a-94b9d7038bdd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4042707149 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_smoke.4042707149
Directory /workspace/15.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/15.rom_ctrl_stress_all.1194561588
Short name T56
Test name
Test status
Simulation time 2575023314 ps
CPU time 34.95 seconds
Started Apr 28 12:41:22 PM PDT 24
Finished Apr 28 12:42:00 PM PDT 24
Peak memory 215972 kb
Host smart-60ce5db7-8059-455b-85ec-f9cc11b39171
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1194561588 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 15.rom_ctrl_stress_all.1194561588
Directory /workspace/15.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/16.rom_ctrl_alert_test.1328992311
Short name T274
Test name
Test status
Simulation time 1628182068 ps
CPU time 13.71 seconds
Started Apr 28 12:41:21 PM PDT 24
Finished Apr 28 12:41:37 PM PDT 24
Peak memory 211284 kb
Host smart-c6055be4-088c-4997-9861-6149204e7a12
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1328992311 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_alert_test.1328992311
Directory /workspace/16.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/16.rom_ctrl_corrupt_sig_fatal_chk.1224917609
Short name T354
Test name
Test status
Simulation time 7754068330 ps
CPU time 101.73 seconds
Started Apr 28 12:40:53 PM PDT 24
Finished Apr 28 12:42:36 PM PDT 24
Peak memory 211600 kb
Host smart-99962b64-f7b4-47f2-bfb9-9a41955ca8d8
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1224917609 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_
corrupt_sig_fatal_chk.1224917609
Directory /workspace/16.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/16.rom_ctrl_kmac_err_chk.759073449
Short name T172
Test name
Test status
Simulation time 4136083631 ps
CPU time 11.07 seconds
Started Apr 28 12:41:02 PM PDT 24
Finished Apr 28 12:41:15 PM PDT 24
Peak memory 211968 kb
Host smart-be9506ea-003c-46bd-88fd-5f7f8525ff22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=759073449 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_kmac_err_chk.759073449
Directory /workspace/16.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/16.rom_ctrl_max_throughput_chk.2352692190
Short name T345
Test name
Test status
Simulation time 558462241 ps
CPU time 7.85 seconds
Started Apr 28 12:41:15 PM PDT 24
Finished Apr 28 12:41:24 PM PDT 24
Peak memory 211340 kb
Host smart-a3623dc2-c27b-4f86-b4f9-1d0f071c8122
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2352692190 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_max_throughput_chk.2352692190
Directory /workspace/16.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/16.rom_ctrl_smoke.704672110
Short name T111
Test name
Test status
Simulation time 194077136 ps
CPU time 10.26 seconds
Started Apr 28 12:41:10 PM PDT 24
Finished Apr 28 12:41:23 PM PDT 24
Peak memory 219468 kb
Host smart-a93cc04f-4df2-459e-a3e4-f0db5cbe50c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=704672110 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_smoke.704672110
Directory /workspace/16.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/16.rom_ctrl_stress_all.706695603
Short name T211
Test name
Test status
Simulation time 7633276411 ps
CPU time 50.37 seconds
Started Apr 28 12:41:05 PM PDT 24
Finished Apr 28 12:41:56 PM PDT 24
Peak memory 216456 kb
Host smart-fa2866e1-ad81-422d-8dd0-646870e24226
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=706695603 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 16.rom_ctrl_stress_all.706695603
Directory /workspace/16.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/16.rom_ctrl_stress_all_with_rand_reset.450805983
Short name T55
Test name
Test status
Simulation time 213733622255 ps
CPU time 1958.13 seconds
Started Apr 28 12:41:10 PM PDT 24
Finished Apr 28 01:13:51 PM PDT 24
Peak memory 234576 kb
Host smart-e22b1b05-e8e7-4ea0-a32f-83c92b431521
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=450805983 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_stress_all_with_rand_reset.450805983
Directory /workspace/16.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/17.rom_ctrl_alert_test.3372570847
Short name T317
Test name
Test status
Simulation time 673637977 ps
CPU time 7.02 seconds
Started Apr 28 12:41:03 PM PDT 24
Finished Apr 28 12:41:12 PM PDT 24
Peak memory 211376 kb
Host smart-977bae84-d349-452d-92d9-7d3643ea621e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3372570847 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_alert_test.3372570847
Directory /workspace/17.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/17.rom_ctrl_corrupt_sig_fatal_chk.1298937149
Short name T49
Test name
Test status
Simulation time 37750649406 ps
CPU time 350.85 seconds
Started Apr 28 12:41:18 PM PDT 24
Finished Apr 28 12:47:10 PM PDT 24
Peak memory 238172 kb
Host smart-d48e1ce4-3f05-479b-aa2b-de004ddd0088
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1298937149 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_
corrupt_sig_fatal_chk.1298937149
Directory /workspace/17.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/17.rom_ctrl_kmac_err_chk.3368904310
Short name T173
Test name
Test status
Simulation time 3349055245 ps
CPU time 20.52 seconds
Started Apr 28 12:41:17 PM PDT 24
Finished Apr 28 12:41:39 PM PDT 24
Peak memory 211992 kb
Host smart-a73e658d-648c-4a81-aa59-dca677d083bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3368904310 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_kmac_err_chk.3368904310
Directory /workspace/17.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/17.rom_ctrl_max_throughput_chk.473663756
Short name T223
Test name
Test status
Simulation time 1902306020 ps
CPU time 15.71 seconds
Started Apr 28 12:41:12 PM PDT 24
Finished Apr 28 12:41:30 PM PDT 24
Peak memory 211244 kb
Host smart-1e049cf2-88e5-4016-b831-dddcb79275d3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=473663756 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_max_throughput_chk.473663756
Directory /workspace/17.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/17.rom_ctrl_smoke.1306615589
Short name T273
Test name
Test status
Simulation time 717393507 ps
CPU time 10.19 seconds
Started Apr 28 12:41:10 PM PDT 24
Finished Apr 28 12:41:23 PM PDT 24
Peak memory 213572 kb
Host smart-32cd07fa-21cc-4aaf-aae1-2c539d2e987b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1306615589 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_smoke.1306615589
Directory /workspace/17.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/17.rom_ctrl_stress_all.2338135643
Short name T154
Test name
Test status
Simulation time 9338546482 ps
CPU time 19.97 seconds
Started Apr 28 12:41:18 PM PDT 24
Finished Apr 28 12:41:49 PM PDT 24
Peak memory 212520 kb
Host smart-190b61ed-0c1e-465f-8727-731baa3545c3
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2338135643 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 17.rom_ctrl_stress_all.2338135643
Directory /workspace/17.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/18.rom_ctrl_alert_test.1274025473
Short name T162
Test name
Test status
Simulation time 1542084691 ps
CPU time 13.01 seconds
Started Apr 28 12:41:06 PM PDT 24
Finished Apr 28 12:41:21 PM PDT 24
Peak memory 211320 kb
Host smart-720e682c-5126-4d12-ba81-957e31bd154d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1274025473 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_alert_test.1274025473
Directory /workspace/18.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/18.rom_ctrl_corrupt_sig_fatal_chk.416668352
Short name T340
Test name
Test status
Simulation time 28512142542 ps
CPU time 139.35 seconds
Started Apr 28 12:41:13 PM PDT 24
Finished Apr 28 12:43:35 PM PDT 24
Peak memory 232028 kb
Host smart-91e7852d-5801-44b6-acd0-1c8c3d14f140
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=416668352 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_c
orrupt_sig_fatal_chk.416668352
Directory /workspace/18.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/18.rom_ctrl_kmac_err_chk.3250990914
Short name T316
Test name
Test status
Simulation time 4016125479 ps
CPU time 31.87 seconds
Started Apr 28 12:41:12 PM PDT 24
Finished Apr 28 12:41:46 PM PDT 24
Peak memory 212532 kb
Host smart-2ba3a9d0-4315-4a0b-903e-c5ce389e127a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3250990914 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_kmac_err_chk.3250990914
Directory /workspace/18.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/18.rom_ctrl_max_throughput_chk.2884900821
Short name T150
Test name
Test status
Simulation time 416961265 ps
CPU time 5.57 seconds
Started Apr 28 12:41:06 PM PDT 24
Finished Apr 28 12:41:13 PM PDT 24
Peak memory 211312 kb
Host smart-0a50f5ff-edbc-4b3c-a10f-0d40236dc378
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2884900821 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_max_throughput_chk.2884900821
Directory /workspace/18.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/18.rom_ctrl_smoke.2896780161
Short name T138
Test name
Test status
Simulation time 29083457307 ps
CPU time 31.43 seconds
Started Apr 28 12:40:59 PM PDT 24
Finished Apr 28 12:41:32 PM PDT 24
Peak memory 219556 kb
Host smart-68c8c869-c4da-4c75-af5b-702560de3b2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2896780161 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_smoke.2896780161
Directory /workspace/18.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/18.rom_ctrl_stress_all.1072146203
Short name T313
Test name
Test status
Simulation time 220686336 ps
CPU time 5.93 seconds
Started Apr 28 12:41:03 PM PDT 24
Finished Apr 28 12:41:11 PM PDT 24
Peak memory 211368 kb
Host smart-063b1a05-37f7-4a87-b9ca-75f58b3f07af
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1072146203 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 18.rom_ctrl_stress_all.1072146203
Directory /workspace/18.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/19.rom_ctrl_alert_test.3761376131
Short name T225
Test name
Test status
Simulation time 578199341 ps
CPU time 8.02 seconds
Started Apr 28 12:41:17 PM PDT 24
Finished Apr 28 12:41:26 PM PDT 24
Peak memory 211324 kb
Host smart-525f7ce9-cacb-4133-8889-1c5fc502b87a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3761376131 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_alert_test.3761376131
Directory /workspace/19.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/19.rom_ctrl_corrupt_sig_fatal_chk.609171909
Short name T214
Test name
Test status
Simulation time 49297976728 ps
CPU time 124.76 seconds
Started Apr 28 12:41:13 PM PDT 24
Finished Apr 28 12:43:20 PM PDT 24
Peak memory 220388 kb
Host smart-f1538115-85ec-41bc-b77e-0223a835bd85
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=609171909 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_c
orrupt_sig_fatal_chk.609171909
Directory /workspace/19.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/19.rom_ctrl_kmac_err_chk.3949012540
Short name T168
Test name
Test status
Simulation time 4372041001 ps
CPU time 34.41 seconds
Started Apr 28 12:41:17 PM PDT 24
Finished Apr 28 12:41:52 PM PDT 24
Peak memory 212412 kb
Host smart-20825610-0f59-44a9-bc79-fb00c6919ef2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3949012540 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_kmac_err_chk.3949012540
Directory /workspace/19.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/19.rom_ctrl_max_throughput_chk.1290979649
Short name T109
Test name
Test status
Simulation time 381979874 ps
CPU time 5.48 seconds
Started Apr 28 12:40:53 PM PDT 24
Finished Apr 28 12:41:00 PM PDT 24
Peak memory 211304 kb
Host smart-24228b6d-7796-4d9e-bf1b-5eaef1d5f066
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1290979649 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_max_throughput_chk.1290979649
Directory /workspace/19.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/19.rom_ctrl_smoke.337157705
Short name T57
Test name
Test status
Simulation time 4879184254 ps
CPU time 26.17 seconds
Started Apr 28 12:41:14 PM PDT 24
Finished Apr 28 12:41:42 PM PDT 24
Peak memory 219384 kb
Host smart-62672f3f-473c-4385-a1c3-0141ce53c2eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=337157705 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_smoke.337157705
Directory /workspace/19.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/19.rom_ctrl_stress_all.23186424
Short name T137
Test name
Test status
Simulation time 1450427760 ps
CPU time 26.12 seconds
Started Apr 28 12:41:04 PM PDT 24
Finished Apr 28 12:41:37 PM PDT 24
Peak memory 213308 kb
Host smart-9034a500-c560-4358-87a4-1b98d43050a7
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23186424 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +U
VM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n
ame 19.rom_ctrl_stress_all.23186424
Directory /workspace/19.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/19.rom_ctrl_stress_all_with_rand_reset.3459861648
Short name T349
Test name
Test status
Simulation time 64326189509 ps
CPU time 2371.35 seconds
Started Apr 28 12:41:11 PM PDT 24
Finished Apr 28 01:20:45 PM PDT 24
Peak memory 237516 kb
Host smart-0f1b7509-e39c-47a7-a551-38cd3b4a4515
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3459861648 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_stress_all_with_rand_reset.3459861648
Directory /workspace/19.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.rom_ctrl_alert_test.170786232
Short name T254
Test name
Test status
Simulation time 2107228327 ps
CPU time 16.57 seconds
Started Apr 28 12:40:59 PM PDT 24
Finished Apr 28 12:41:18 PM PDT 24
Peak memory 211368 kb
Host smart-c17c2f2b-fa32-42ca-91bf-d218731ff38b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=170786232 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_alert_test.170786232
Directory /workspace/2.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/2.rom_ctrl_corrupt_sig_fatal_chk.1357778204
Short name T247
Test name
Test status
Simulation time 36238836072 ps
CPU time 384.6 seconds
Started Apr 28 12:40:59 PM PDT 24
Finished Apr 28 12:47:26 PM PDT 24
Peak memory 225168 kb
Host smart-bfcc4b0b-78dc-4779-adf2-0edc67a38f69
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1357778204 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_c
orrupt_sig_fatal_chk.1357778204
Directory /workspace/2.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/2.rom_ctrl_kmac_err_chk.3834497752
Short name T235
Test name
Test status
Simulation time 995420922 ps
CPU time 11.03 seconds
Started Apr 28 12:40:52 PM PDT 24
Finished Apr 28 12:41:04 PM PDT 24
Peak memory 211836 kb
Host smart-b3d69ec2-218d-447a-9d3e-4bbd71edbf47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3834497752 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_kmac_err_chk.3834497752
Directory /workspace/2.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/2.rom_ctrl_max_throughput_chk.294337041
Short name T200
Test name
Test status
Simulation time 3101311612 ps
CPU time 14.39 seconds
Started Apr 28 12:40:58 PM PDT 24
Finished Apr 28 12:41:15 PM PDT 24
Peak memory 211348 kb
Host smart-b776d59b-edc7-4b40-8ae3-0b6b12015371
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=294337041 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_max_throughput_chk.294337041
Directory /workspace/2.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/2.rom_ctrl_sec_cm.1704476340
Short name T35
Test name
Test status
Simulation time 3930624770 ps
CPU time 57.7 seconds
Started Apr 28 12:40:48 PM PDT 24
Finished Apr 28 12:41:46 PM PDT 24
Peak memory 235504 kb
Host smart-56a138f5-a21f-4fe6-a03f-2b48e288dea8
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1704476340 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_sec_cm.1704476340
Directory /workspace/2.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/2.rom_ctrl_smoke.1154831424
Short name T95
Test name
Test status
Simulation time 2090314730 ps
CPU time 17.21 seconds
Started Apr 28 12:41:07 PM PDT 24
Finished Apr 28 12:41:26 PM PDT 24
Peak memory 213644 kb
Host smart-33f2cf1a-4ccb-455f-8492-6b204fe11610
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1154831424 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_smoke.1154831424
Directory /workspace/2.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/2.rom_ctrl_stress_all.3760127078
Short name T39
Test name
Test status
Simulation time 10446020344 ps
CPU time 43.03 seconds
Started Apr 28 12:41:15 PM PDT 24
Finished Apr 28 12:42:00 PM PDT 24
Peak memory 219528 kb
Host smart-206b63a9-3ab8-42ca-8d1a-9c6e6bd6c6e5
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3760127078 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 2.rom_ctrl_stress_all.3760127078
Directory /workspace/2.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/20.rom_ctrl_alert_test.2959438855
Short name T189
Test name
Test status
Simulation time 1195985889 ps
CPU time 11.1 seconds
Started Apr 28 12:41:21 PM PDT 24
Finished Apr 28 12:41:34 PM PDT 24
Peak memory 211336 kb
Host smart-79712834-197d-4c59-89bf-a2933d48f599
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2959438855 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_alert_test.2959438855
Directory /workspace/20.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/20.rom_ctrl_corrupt_sig_fatal_chk.3180715037
Short name T286
Test name
Test status
Simulation time 22216830441 ps
CPU time 142.35 seconds
Started Apr 28 12:41:12 PM PDT 24
Finished Apr 28 12:43:37 PM PDT 24
Peak memory 237492 kb
Host smart-4c1e6987-5c59-479c-9ef1-b88952f9be30
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3180715037 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_
corrupt_sig_fatal_chk.3180715037
Directory /workspace/20.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/20.rom_ctrl_kmac_err_chk.1881036487
Short name T236
Test name
Test status
Simulation time 3239861797 ps
CPU time 27.89 seconds
Started Apr 28 12:41:10 PM PDT 24
Finished Apr 28 12:41:40 PM PDT 24
Peak memory 211936 kb
Host smart-db7b1018-836d-40c6-a5da-74df63531ea7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1881036487 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_kmac_err_chk.1881036487
Directory /workspace/20.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/20.rom_ctrl_max_throughput_chk.2934767451
Short name T249
Test name
Test status
Simulation time 612903031 ps
CPU time 5.57 seconds
Started Apr 28 12:41:08 PM PDT 24
Finished Apr 28 12:41:16 PM PDT 24
Peak memory 211268 kb
Host smart-1543a1d6-b1e4-4c19-9e5a-49c1b26479f6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2934767451 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_max_throughput_chk.2934767451
Directory /workspace/20.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/20.rom_ctrl_stress_all.400619091
Short name T161
Test name
Test status
Simulation time 4345659297 ps
CPU time 39.36 seconds
Started Apr 28 12:41:15 PM PDT 24
Finished Apr 28 12:41:56 PM PDT 24
Peak memory 219576 kb
Host smart-e0c94e0b-b3be-41ad-a5d1-031e5f28d7a5
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=400619091 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 20.rom_ctrl_stress_all.400619091
Directory /workspace/20.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/21.rom_ctrl_alert_test.3903791317
Short name T65
Test name
Test status
Simulation time 1966097245 ps
CPU time 15.36 seconds
Started Apr 28 12:41:19 PM PDT 24
Finished Apr 28 12:41:35 PM PDT 24
Peak memory 211404 kb
Host smart-6802489e-2376-4ef5-bfce-8aca49c08478
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3903791317 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_alert_test.3903791317
Directory /workspace/21.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/21.rom_ctrl_corrupt_sig_fatal_chk.3477177614
Short name T25
Test name
Test status
Simulation time 56015071654 ps
CPU time 448.47 seconds
Started Apr 28 12:41:39 PM PDT 24
Finished Apr 28 12:49:08 PM PDT 24
Peak memory 237064 kb
Host smart-c3376599-e2d9-4cea-9c48-f2caa244c95b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3477177614 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_
corrupt_sig_fatal_chk.3477177614
Directory /workspace/21.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/21.rom_ctrl_kmac_err_chk.544909267
Short name T347
Test name
Test status
Simulation time 2517684744 ps
CPU time 18.42 seconds
Started Apr 28 12:41:28 PM PDT 24
Finished Apr 28 12:41:48 PM PDT 24
Peak memory 211948 kb
Host smart-44acf2d1-92a6-4412-8728-6471b3fc929c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=544909267 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_kmac_err_chk.544909267
Directory /workspace/21.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/21.rom_ctrl_max_throughput_chk.1683739529
Short name T175
Test name
Test status
Simulation time 190123573 ps
CPU time 5.47 seconds
Started Apr 28 12:41:15 PM PDT 24
Finished Apr 28 12:41:22 PM PDT 24
Peak memory 211304 kb
Host smart-21021164-ce75-42f6-9d3b-30c944ff2f2e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1683739529 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_max_throughput_chk.1683739529
Directory /workspace/21.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/21.rom_ctrl_smoke.3905927999
Short name T79
Test name
Test status
Simulation time 4153217064 ps
CPU time 15.81 seconds
Started Apr 28 12:41:18 PM PDT 24
Finished Apr 28 12:41:35 PM PDT 24
Peak memory 219612 kb
Host smart-715ddd4b-97d9-4140-b931-298d46413669
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3905927999 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_smoke.3905927999
Directory /workspace/21.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/21.rom_ctrl_stress_all.4080587627
Short name T228
Test name
Test status
Simulation time 11441663821 ps
CPU time 37.17 seconds
Started Apr 28 12:41:12 PM PDT 24
Finished Apr 28 12:41:51 PM PDT 24
Peak memory 219528 kb
Host smart-d6d18f27-8052-41f6-beea-01edbc056e1d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4080587627 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 21.rom_ctrl_stress_all.4080587627
Directory /workspace/21.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/21.rom_ctrl_stress_all_with_rand_reset.2868195331
Short name T234
Test name
Test status
Simulation time 35616222528 ps
CPU time 4434.38 seconds
Started Apr 28 12:41:04 PM PDT 24
Finished Apr 28 01:55:00 PM PDT 24
Peak memory 227836 kb
Host smart-f783a00f-29f0-40a0-8279-07137bc6dedf
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2868195331 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_stress_all_with_rand_reset.2868195331
Directory /workspace/21.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/22.rom_ctrl_alert_test.3804414031
Short name T196
Test name
Test status
Simulation time 1471147713 ps
CPU time 13.04 seconds
Started Apr 28 12:41:08 PM PDT 24
Finished Apr 28 12:41:23 PM PDT 24
Peak memory 211312 kb
Host smart-76d612bf-39cf-413f-9c8d-195351a4b23f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3804414031 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_alert_test.3804414031
Directory /workspace/22.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/22.rom_ctrl_kmac_err_chk.3145572229
Short name T147
Test name
Test status
Simulation time 171966812 ps
CPU time 9.42 seconds
Started Apr 28 12:41:27 PM PDT 24
Finished Apr 28 12:41:39 PM PDT 24
Peak memory 211936 kb
Host smart-36b43af6-cde7-4c1a-bf43-d0eae15866f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3145572229 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_kmac_err_chk.3145572229
Directory /workspace/22.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/22.rom_ctrl_max_throughput_chk.1479519075
Short name T311
Test name
Test status
Simulation time 917134892 ps
CPU time 10.94 seconds
Started Apr 28 12:41:06 PM PDT 24
Finished Apr 28 12:41:19 PM PDT 24
Peak memory 211236 kb
Host smart-8e618082-e26b-4fa1-9be0-7500045e3c2f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1479519075 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_max_throughput_chk.1479519075
Directory /workspace/22.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/22.rom_ctrl_smoke.101941528
Short name T233
Test name
Test status
Simulation time 872238100 ps
CPU time 15.11 seconds
Started Apr 28 12:41:13 PM PDT 24
Finished Apr 28 12:41:30 PM PDT 24
Peak memory 219552 kb
Host smart-89d7cdb5-5724-48b8-84d7-2b392d43da3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=101941528 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_smoke.101941528
Directory /workspace/22.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/22.rom_ctrl_stress_all.1176682717
Short name T364
Test name
Test status
Simulation time 887979184 ps
CPU time 12.5 seconds
Started Apr 28 12:41:29 PM PDT 24
Finished Apr 28 12:41:42 PM PDT 24
Peak memory 213584 kb
Host smart-c7549abb-9ce0-4ebe-a833-2b009e6b2b61
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1176682717 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 22.rom_ctrl_stress_all.1176682717
Directory /workspace/22.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/23.rom_ctrl_alert_test.2959204111
Short name T237
Test name
Test status
Simulation time 669866208 ps
CPU time 7.78 seconds
Started Apr 28 12:41:11 PM PDT 24
Finished Apr 28 12:41:21 PM PDT 24
Peak memory 211368 kb
Host smart-abde1e5e-761c-49c6-b3b3-5353586f72b5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2959204111 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_alert_test.2959204111
Directory /workspace/23.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/23.rom_ctrl_corrupt_sig_fatal_chk.1514202951
Short name T101
Test name
Test status
Simulation time 133201555029 ps
CPU time 293.58 seconds
Started Apr 28 12:41:13 PM PDT 24
Finished Apr 28 12:46:09 PM PDT 24
Peak memory 228896 kb
Host smart-53cea9da-5f93-483f-9b57-0a39a4047cd0
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1514202951 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_
corrupt_sig_fatal_chk.1514202951
Directory /workspace/23.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/23.rom_ctrl_kmac_err_chk.918464818
Short name T292
Test name
Test status
Simulation time 2390138383 ps
CPU time 23.82 seconds
Started Apr 28 12:41:06 PM PDT 24
Finished Apr 28 12:41:32 PM PDT 24
Peak memory 212048 kb
Host smart-31a6489a-e4f1-4179-983c-67a6db3770ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=918464818 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_kmac_err_chk.918464818
Directory /workspace/23.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/23.rom_ctrl_max_throughput_chk.3347240027
Short name T38
Test name
Test status
Simulation time 1849309917 ps
CPU time 15.49 seconds
Started Apr 28 12:41:14 PM PDT 24
Finished Apr 28 12:41:32 PM PDT 24
Peak memory 211252 kb
Host smart-eb4f6782-fb65-4f67-9697-c4197c2e0910
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3347240027 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_max_throughput_chk.3347240027
Directory /workspace/23.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/23.rom_ctrl_smoke.853228163
Short name T132
Test name
Test status
Simulation time 8850321370 ps
CPU time 32.09 seconds
Started Apr 28 12:41:19 PM PDT 24
Finished Apr 28 12:41:52 PM PDT 24
Peak memory 214024 kb
Host smart-746ee904-1cf3-45e9-9b8c-74a3d7206635
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=853228163 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_smoke.853228163
Directory /workspace/23.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/23.rom_ctrl_stress_all.552858967
Short name T267
Test name
Test status
Simulation time 469436579 ps
CPU time 15.82 seconds
Started Apr 28 12:40:59 PM PDT 24
Finished Apr 28 12:41:17 PM PDT 24
Peak memory 214792 kb
Host smart-b9044c63-76b6-4832-a845-05feb00a1ef3
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=552858967 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 23.rom_ctrl_stress_all.552858967
Directory /workspace/23.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/24.rom_ctrl_alert_test.2596917351
Short name T148
Test name
Test status
Simulation time 6832044339 ps
CPU time 15.12 seconds
Started Apr 28 12:41:12 PM PDT 24
Finished Apr 28 12:41:29 PM PDT 24
Peak memory 211480 kb
Host smart-59ebaaf1-0e2e-46e1-b3e6-14ffd75f70d8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2596917351 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_alert_test.2596917351
Directory /workspace/24.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/24.rom_ctrl_corrupt_sig_fatal_chk.2752246264
Short name T245
Test name
Test status
Simulation time 65525545227 ps
CPU time 177.73 seconds
Started Apr 28 12:41:15 PM PDT 24
Finished Apr 28 12:44:15 PM PDT 24
Peak memory 220604 kb
Host smart-356bfaad-2914-4dec-88e9-2098da46ed42
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2752246264 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_
corrupt_sig_fatal_chk.2752246264
Directory /workspace/24.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/24.rom_ctrl_kmac_err_chk.730073352
Short name T28
Test name
Test status
Simulation time 4270507918 ps
CPU time 15.86 seconds
Started Apr 28 12:41:16 PM PDT 24
Finished Apr 28 12:41:33 PM PDT 24
Peak memory 211968 kb
Host smart-272b52cd-4209-4808-bd23-e4ddf51708e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=730073352 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_kmac_err_chk.730073352
Directory /workspace/24.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/24.rom_ctrl_max_throughput_chk.939971459
Short name T303
Test name
Test status
Simulation time 2495277202 ps
CPU time 12.54 seconds
Started Apr 28 12:41:07 PM PDT 24
Finished Apr 28 12:41:22 PM PDT 24
Peak memory 211372 kb
Host smart-7893793d-20b3-471d-9152-4f022b41ac6a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=939971459 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_max_throughput_chk.939971459
Directory /workspace/24.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/24.rom_ctrl_smoke.4028522419
Short name T315
Test name
Test status
Simulation time 5270250364 ps
CPU time 19.73 seconds
Started Apr 28 12:41:08 PM PDT 24
Finished Apr 28 12:41:30 PM PDT 24
Peak memory 214260 kb
Host smart-137eb9bf-2114-4612-9878-f8fda4ef54ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4028522419 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_smoke.4028522419
Directory /workspace/24.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/24.rom_ctrl_stress_all.1183308727
Short name T100
Test name
Test status
Simulation time 889336477 ps
CPU time 12.43 seconds
Started Apr 28 12:41:11 PM PDT 24
Finished Apr 28 12:41:25 PM PDT 24
Peak memory 211248 kb
Host smart-aa6a53b1-7d87-4166-b6b8-7f7a5254bb07
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1183308727 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 24.rom_ctrl_stress_all.1183308727
Directory /workspace/24.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/25.rom_ctrl_alert_test.119944407
Short name T176
Test name
Test status
Simulation time 988405860 ps
CPU time 5.94 seconds
Started Apr 28 12:41:02 PM PDT 24
Finished Apr 28 12:41:09 PM PDT 24
Peak memory 211340 kb
Host smart-20617758-8571-47da-b39b-b7de576e4e4f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=119944407 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_alert_test.119944407
Directory /workspace/25.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/25.rom_ctrl_corrupt_sig_fatal_chk.2545945361
Short name T333
Test name
Test status
Simulation time 5318475923 ps
CPU time 128.02 seconds
Started Apr 28 12:41:09 PM PDT 24
Finished Apr 28 12:43:19 PM PDT 24
Peak memory 225068 kb
Host smart-390045da-d4d5-4ab5-bef5-a48b339d70f0
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2545945361 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_
corrupt_sig_fatal_chk.2545945361
Directory /workspace/25.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/25.rom_ctrl_kmac_err_chk.3672347896
Short name T318
Test name
Test status
Simulation time 10840180148 ps
CPU time 27 seconds
Started Apr 28 12:41:22 PM PDT 24
Finished Apr 28 12:41:52 PM PDT 24
Peak memory 212352 kb
Host smart-5aa40728-00fe-4b7f-970a-d9c8d23b9954
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3672347896 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_kmac_err_chk.3672347896
Directory /workspace/25.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/25.rom_ctrl_max_throughput_chk.2492736245
Short name T322
Test name
Test status
Simulation time 4486541425 ps
CPU time 11.61 seconds
Started Apr 28 12:41:21 PM PDT 24
Finished Apr 28 12:41:35 PM PDT 24
Peak memory 211420 kb
Host smart-ceef1bd9-7e31-40a5-82c6-dbac6d1f2d59
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2492736245 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_max_throughput_chk.2492736245
Directory /workspace/25.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/25.rom_ctrl_smoke.2902277273
Short name T257
Test name
Test status
Simulation time 3690869969 ps
CPU time 39.81 seconds
Started Apr 28 12:41:23 PM PDT 24
Finished Apr 28 12:42:08 PM PDT 24
Peak memory 214088 kb
Host smart-858b7eb5-0bd1-4557-8ad0-6a03d0109fa3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2902277273 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_smoke.2902277273
Directory /workspace/25.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/25.rom_ctrl_stress_all.776656616
Short name T213
Test name
Test status
Simulation time 1632409848 ps
CPU time 8.6 seconds
Started Apr 28 12:41:11 PM PDT 24
Finished Apr 28 12:41:22 PM PDT 24
Peak memory 211288 kb
Host smart-13b338e2-b996-4d24-b94d-36e2edd35326
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=776656616 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 25.rom_ctrl_stress_all.776656616
Directory /workspace/25.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/26.rom_ctrl_alert_test.3830718
Short name T243
Test name
Test status
Simulation time 168561439 ps
CPU time 4.26 seconds
Started Apr 28 12:41:20 PM PDT 24
Finished Apr 28 12:41:26 PM PDT 24
Peak memory 211320 kb
Host smart-e347251d-7542-4d91-8dc4-510b0ace05a7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3830718 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_alert_test.3830718
Directory /workspace/26.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/26.rom_ctrl_kmac_err_chk.3382775025
Short name T186
Test name
Test status
Simulation time 8431465402 ps
CPU time 24 seconds
Started Apr 28 12:41:11 PM PDT 24
Finished Apr 28 12:41:37 PM PDT 24
Peak memory 212600 kb
Host smart-23fe7f1e-5b95-439f-90a9-4faabd7f7acb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3382775025 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_kmac_err_chk.3382775025
Directory /workspace/26.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/26.rom_ctrl_max_throughput_chk.80587223
Short name T246
Test name
Test status
Simulation time 4259231492 ps
CPU time 17.28 seconds
Started Apr 28 12:41:32 PM PDT 24
Finished Apr 28 12:41:50 PM PDT 24
Peak memory 211412 kb
Host smart-3cf1f834-263b-4544-96a5-58bff5ca2089
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=80587223 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_max_throughput_chk.80587223
Directory /workspace/26.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/26.rom_ctrl_smoke.1746367708
Short name T355
Test name
Test status
Simulation time 748039983 ps
CPU time 10.28 seconds
Started Apr 28 12:41:21 PM PDT 24
Finished Apr 28 12:41:33 PM PDT 24
Peak memory 219488 kb
Host smart-925a983e-880b-4c7e-a969-a0ffd3752ec2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1746367708 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_smoke.1746367708
Directory /workspace/26.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/26.rom_ctrl_stress_all.1469964143
Short name T188
Test name
Test status
Simulation time 489493132 ps
CPU time 25.2 seconds
Started Apr 28 12:41:30 PM PDT 24
Finished Apr 28 12:41:56 PM PDT 24
Peak memory 215400 kb
Host smart-63fbee0e-b43e-4810-ad29-d8d959e27232
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1469964143 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 26.rom_ctrl_stress_all.1469964143
Directory /workspace/26.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/26.rom_ctrl_stress_all_with_rand_reset.4003560993
Short name T54
Test name
Test status
Simulation time 40679248417 ps
CPU time 2572.97 seconds
Started Apr 28 12:41:25 PM PDT 24
Finished Apr 28 01:24:21 PM PDT 24
Peak memory 236076 kb
Host smart-407ae562-a3bf-4691-a5e3-fd6bfe20f4c6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4003560993 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_stress_all_with_rand_reset.4003560993
Directory /workspace/26.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/27.rom_ctrl_alert_test.4249667035
Short name T227
Test name
Test status
Simulation time 6156718248 ps
CPU time 7.71 seconds
Started Apr 28 12:41:16 PM PDT 24
Finished Apr 28 12:41:25 PM PDT 24
Peak memory 211056 kb
Host smart-652a4b58-6421-489f-98b9-799499268828
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4249667035 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_alert_test.4249667035
Directory /workspace/27.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/27.rom_ctrl_corrupt_sig_fatal_chk.2887813512
Short name T369
Test name
Test status
Simulation time 36834574051 ps
CPU time 310.98 seconds
Started Apr 28 12:41:16 PM PDT 24
Finished Apr 28 12:46:29 PM PDT 24
Peak memory 218676 kb
Host smart-b5ceae20-afaa-4591-9c74-05c16b22e2a5
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2887813512 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_
corrupt_sig_fatal_chk.2887813512
Directory /workspace/27.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/27.rom_ctrl_kmac_err_chk.1882562382
Short name T281
Test name
Test status
Simulation time 3146555218 ps
CPU time 18.6 seconds
Started Apr 28 12:41:19 PM PDT 24
Finished Apr 28 12:41:39 PM PDT 24
Peak memory 211896 kb
Host smart-0ef570b8-3ee6-4249-9ced-f254eb1739be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1882562382 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_kmac_err_chk.1882562382
Directory /workspace/27.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/27.rom_ctrl_max_throughput_chk.712565664
Short name T141
Test name
Test status
Simulation time 2958504881 ps
CPU time 14.05 seconds
Started Apr 28 12:41:33 PM PDT 24
Finished Apr 28 12:41:48 PM PDT 24
Peak memory 211280 kb
Host smart-2d5db155-5643-4ea4-9e64-e2a39ef58d43
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=712565664 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_max_throughput_chk.712565664
Directory /workspace/27.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/27.rom_ctrl_smoke.3228624489
Short name T208
Test name
Test status
Simulation time 1635009547 ps
CPU time 21.06 seconds
Started Apr 28 12:41:02 PM PDT 24
Finished Apr 28 12:41:25 PM PDT 24
Peak memory 219544 kb
Host smart-767b6420-91a3-4ad8-8d45-7875be8ef0ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3228624489 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_smoke.3228624489
Directory /workspace/27.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/27.rom_ctrl_stress_all.3989168820
Short name T365
Test name
Test status
Simulation time 1720328222 ps
CPU time 9.23 seconds
Started Apr 28 12:41:21 PM PDT 24
Finished Apr 28 12:41:33 PM PDT 24
Peak memory 211204 kb
Host smart-1c15d5af-fc69-4815-a10c-7888fb3ce195
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3989168820 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 27.rom_ctrl_stress_all.3989168820
Directory /workspace/27.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/28.rom_ctrl_corrupt_sig_fatal_chk.1172372984
Short name T224
Test name
Test status
Simulation time 91705133620 ps
CPU time 234.8 seconds
Started Apr 28 12:41:21 PM PDT 24
Finished Apr 28 12:45:18 PM PDT 24
Peak memory 228684 kb
Host smart-cfc7f60a-d554-4221-9aa6-019888ea0583
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1172372984 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_
corrupt_sig_fatal_chk.1172372984
Directory /workspace/28.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/28.rom_ctrl_kmac_err_chk.2314401981
Short name T219
Test name
Test status
Simulation time 2468272187 ps
CPU time 16.86 seconds
Started Apr 28 12:41:21 PM PDT 24
Finished Apr 28 12:41:41 PM PDT 24
Peak memory 212676 kb
Host smart-25f0bb3a-8c21-45da-8cd9-935a650a8669
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2314401981 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_kmac_err_chk.2314401981
Directory /workspace/28.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/28.rom_ctrl_max_throughput_chk.1690593063
Short name T145
Test name
Test status
Simulation time 16593450377 ps
CPU time 11.02 seconds
Started Apr 28 12:41:09 PM PDT 24
Finished Apr 28 12:41:22 PM PDT 24
Peak memory 211344 kb
Host smart-6dfacd7d-de04-4113-a855-1fe6f2a7f970
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1690593063 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_max_throughput_chk.1690593063
Directory /workspace/28.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/28.rom_ctrl_smoke.2785375941
Short name T81
Test name
Test status
Simulation time 1402198681 ps
CPU time 15.05 seconds
Started Apr 28 12:41:18 PM PDT 24
Finished Apr 28 12:41:34 PM PDT 24
Peak memory 219540 kb
Host smart-b890b51f-8efc-4313-84fa-63125267177c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2785375941 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_smoke.2785375941
Directory /workspace/28.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/28.rom_ctrl_stress_all.2924695182
Short name T262
Test name
Test status
Simulation time 247815069 ps
CPU time 14.36 seconds
Started Apr 28 12:41:10 PM PDT 24
Finished Apr 28 12:41:26 PM PDT 24
Peak memory 213752 kb
Host smart-755c1978-188d-4e51-ac43-249e5ccbd849
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2924695182 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 28.rom_ctrl_stress_all.2924695182
Directory /workspace/28.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/29.rom_ctrl_alert_test.2993329443
Short name T288
Test name
Test status
Simulation time 584025044 ps
CPU time 7.97 seconds
Started Apr 28 12:41:33 PM PDT 24
Finished Apr 28 12:41:42 PM PDT 24
Peak memory 211376 kb
Host smart-729c071e-dc47-459f-8059-28e78879595c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2993329443 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_alert_test.2993329443
Directory /workspace/29.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/29.rom_ctrl_kmac_err_chk.2857969409
Short name T184
Test name
Test status
Simulation time 5989574439 ps
CPU time 31.32 seconds
Started Apr 28 12:41:18 PM PDT 24
Finished Apr 28 12:41:50 PM PDT 24
Peak memory 212456 kb
Host smart-56f281ee-5088-4508-8143-98b60ab51139
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2857969409 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_kmac_err_chk.2857969409
Directory /workspace/29.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/29.rom_ctrl_max_throughput_chk.4085306918
Short name T265
Test name
Test status
Simulation time 959157603 ps
CPU time 8.37 seconds
Started Apr 28 12:41:26 PM PDT 24
Finished Apr 28 12:41:37 PM PDT 24
Peak memory 211196 kb
Host smart-1a7d68b6-34fb-4e95-868e-0037dbef14b1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4085306918 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_max_throughput_chk.4085306918
Directory /workspace/29.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/29.rom_ctrl_smoke.2277500064
Short name T217
Test name
Test status
Simulation time 2420521804 ps
CPU time 23.77 seconds
Started Apr 28 12:41:13 PM PDT 24
Finished Apr 28 12:41:39 PM PDT 24
Peak memory 212200 kb
Host smart-a4d15306-7cbb-4893-9994-fcf274cbc06e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2277500064 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_smoke.2277500064
Directory /workspace/29.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/29.rom_ctrl_stress_all.2385414872
Short name T117
Test name
Test status
Simulation time 305316331 ps
CPU time 18.81 seconds
Started Apr 28 12:41:26 PM PDT 24
Finished Apr 28 12:41:47 PM PDT 24
Peak memory 219424 kb
Host smart-7916d62c-3e8a-4e1d-b59c-a4a759b1582a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2385414872 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 29.rom_ctrl_stress_all.2385414872
Directory /workspace/29.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/29.rom_ctrl_stress_all_with_rand_reset.3312046578
Short name T263
Test name
Test status
Simulation time 22627661036 ps
CPU time 744.92 seconds
Started Apr 28 12:41:34 PM PDT 24
Finished Apr 28 12:54:00 PM PDT 24
Peak memory 233004 kb
Host smart-a159737f-13c5-4c30-aad2-ec0bdb3a65fb
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3312046578 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_stress_all_with_rand_reset.3312046578
Directory /workspace/29.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.rom_ctrl_alert_test.3726845974
Short name T308
Test name
Test status
Simulation time 1531198142 ps
CPU time 13.25 seconds
Started Apr 28 12:40:59 PM PDT 24
Finished Apr 28 12:41:14 PM PDT 24
Peak memory 211300 kb
Host smart-f83e8d67-30fd-4be6-b897-d5057e5e0542
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3726845974 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_alert_test.3726845974
Directory /workspace/3.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/3.rom_ctrl_corrupt_sig_fatal_chk.4192667018
Short name T287
Test name
Test status
Simulation time 26335428741 ps
CPU time 118.1 seconds
Started Apr 28 12:40:47 PM PDT 24
Finished Apr 28 12:42:46 PM PDT 24
Peak memory 237964 kb
Host smart-09a8f40b-aeb5-4dce-93f4-79a192b8102a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4192667018 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_c
orrupt_sig_fatal_chk.4192667018
Directory /workspace/3.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/3.rom_ctrl_kmac_err_chk.2524922877
Short name T242
Test name
Test status
Simulation time 1607183052 ps
CPU time 18.76 seconds
Started Apr 28 12:40:42 PM PDT 24
Finished Apr 28 12:41:03 PM PDT 24
Peak memory 211836 kb
Host smart-f661a6b3-2eeb-401a-8571-5bfe7fd409c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2524922877 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_kmac_err_chk.2524922877
Directory /workspace/3.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/3.rom_ctrl_max_throughput_chk.4179752336
Short name T191
Test name
Test status
Simulation time 1683223916 ps
CPU time 10.48 seconds
Started Apr 28 12:41:01 PM PDT 24
Finished Apr 28 12:41:13 PM PDT 24
Peak memory 211264 kb
Host smart-1706530a-5508-4889-bb95-99caf6f4aaa4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4179752336 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_max_throughput_chk.4179752336
Directory /workspace/3.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/3.rom_ctrl_sec_cm.298566080
Short name T36
Test name
Test status
Simulation time 2174418562 ps
CPU time 54.05 seconds
Started Apr 28 12:41:05 PM PDT 24
Finished Apr 28 12:42:00 PM PDT 24
Peak memory 235492 kb
Host smart-61c64a69-2778-4a91-a62f-5c5cc38a77a1
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=298566080 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_sec_cm.298566080
Directory /workspace/3.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/3.rom_ctrl_smoke.3568688736
Short name T241
Test name
Test status
Simulation time 8884968436 ps
CPU time 25.02 seconds
Started Apr 28 12:41:06 PM PDT 24
Finished Apr 28 12:41:33 PM PDT 24
Peak memory 214532 kb
Host smart-988ec1bf-114a-4e66-9c86-20f5a28c4d27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3568688736 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_smoke.3568688736
Directory /workspace/3.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/3.rom_ctrl_stress_all.3646731639
Short name T284
Test name
Test status
Simulation time 302274687 ps
CPU time 17.52 seconds
Started Apr 28 12:40:58 PM PDT 24
Finished Apr 28 12:41:18 PM PDT 24
Peak memory 214704 kb
Host smart-6620ef13-5879-4d57-b9c2-ee3af584bcda
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3646731639 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 3.rom_ctrl_stress_all.3646731639
Directory /workspace/3.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/30.rom_ctrl_alert_test.524847050
Short name T169
Test name
Test status
Simulation time 300416217 ps
CPU time 5.88 seconds
Started Apr 28 12:41:24 PM PDT 24
Finished Apr 28 12:41:33 PM PDT 24
Peak memory 211340 kb
Host smart-4e6c42be-993f-439c-b858-7c478badc178
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=524847050 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_alert_test.524847050
Directory /workspace/30.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/30.rom_ctrl_corrupt_sig_fatal_chk.1724528767
Short name T327
Test name
Test status
Simulation time 84704264921 ps
CPU time 214.05 seconds
Started Apr 28 12:41:35 PM PDT 24
Finished Apr 28 12:45:10 PM PDT 24
Peak memory 236912 kb
Host smart-b7babfc6-f907-4616-a092-23335bf5d562
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1724528767 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_
corrupt_sig_fatal_chk.1724528767
Directory /workspace/30.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/30.rom_ctrl_kmac_err_chk.1081976589
Short name T269
Test name
Test status
Simulation time 14428639968 ps
CPU time 31 seconds
Started Apr 28 12:41:14 PM PDT 24
Finished Apr 28 12:41:47 PM PDT 24
Peak memory 212052 kb
Host smart-fa085974-4a9c-488e-9f06-090170da8b56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1081976589 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_kmac_err_chk.1081976589
Directory /workspace/30.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/30.rom_ctrl_max_throughput_chk.1709366910
Short name T321
Test name
Test status
Simulation time 11705428378 ps
CPU time 14.13 seconds
Started Apr 28 12:41:24 PM PDT 24
Finished Apr 28 12:41:42 PM PDT 24
Peak memory 211372 kb
Host smart-d5d7c8ac-edcd-4bb5-8390-37266b70fa9a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1709366910 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_max_throughput_chk.1709366910
Directory /workspace/30.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/30.rom_ctrl_smoke.1146179048
Short name T134
Test name
Test status
Simulation time 693614665 ps
CPU time 10.05 seconds
Started Apr 28 12:41:22 PM PDT 24
Finished Apr 28 12:41:35 PM PDT 24
Peak memory 213936 kb
Host smart-06f98da1-7a03-47d2-854d-cc3f1490067f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1146179048 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_smoke.1146179048
Directory /workspace/30.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/30.rom_ctrl_stress_all.2422549310
Short name T183
Test name
Test status
Simulation time 6909221585 ps
CPU time 13.67 seconds
Started Apr 28 12:41:24 PM PDT 24
Finished Apr 28 12:41:41 PM PDT 24
Peak memory 211224 kb
Host smart-3067c5b3-daa0-4e44-b98d-bbf58fc4ebc3
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2422549310 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 30.rom_ctrl_stress_all.2422549310
Directory /workspace/30.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/31.rom_ctrl_alert_test.1756888509
Short name T33
Test name
Test status
Simulation time 85522329 ps
CPU time 4.32 seconds
Started Apr 28 12:41:22 PM PDT 24
Finished Apr 28 12:41:30 PM PDT 24
Peak memory 211356 kb
Host smart-782ca897-739e-4664-a10f-92c83f349928
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1756888509 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_alert_test.1756888509
Directory /workspace/31.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/31.rom_ctrl_corrupt_sig_fatal_chk.225821457
Short name T216
Test name
Test status
Simulation time 57615364434 ps
CPU time 198.48 seconds
Started Apr 28 12:41:23 PM PDT 24
Finished Apr 28 12:44:45 PM PDT 24
Peak memory 218700 kb
Host smart-0973ed06-fcdd-4edb-b8b0-588be1cf5e06
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=225821457 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_c
orrupt_sig_fatal_chk.225821457
Directory /workspace/31.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/31.rom_ctrl_kmac_err_chk.1317817621
Short name T181
Test name
Test status
Simulation time 171646648 ps
CPU time 9.52 seconds
Started Apr 28 12:41:14 PM PDT 24
Finished Apr 28 12:41:25 PM PDT 24
Peak memory 212020 kb
Host smart-973b77cf-f1de-4211-b61d-0d2165348662
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1317817621 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_kmac_err_chk.1317817621
Directory /workspace/31.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/31.rom_ctrl_max_throughput_chk.306351108
Short name T239
Test name
Test status
Simulation time 875634381 ps
CPU time 10.4 seconds
Started Apr 28 12:41:16 PM PDT 24
Finished Apr 28 12:41:28 PM PDT 24
Peak memory 211272 kb
Host smart-9180b874-790f-4b5f-aee1-e75acb6e8c3c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=306351108 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_max_throughput_chk.306351108
Directory /workspace/31.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/31.rom_ctrl_smoke.48131521
Short name T13
Test name
Test status
Simulation time 1190882530 ps
CPU time 9.9 seconds
Started Apr 28 12:41:42 PM PDT 24
Finished Apr 28 12:41:54 PM PDT 24
Peak memory 213712 kb
Host smart-143b08f4-0125-4471-9a81-f2038207af3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=48131521 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_smoke.48131521
Directory /workspace/31.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/31.rom_ctrl_stress_all.1605510143
Short name T78
Test name
Test status
Simulation time 4509213156 ps
CPU time 54.09 seconds
Started Apr 28 12:41:28 PM PDT 24
Finished Apr 28 12:42:23 PM PDT 24
Peak memory 219536 kb
Host smart-cb20922c-6b1f-4ff0-9d98-4f82a594ac74
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1605510143 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 31.rom_ctrl_stress_all.1605510143
Directory /workspace/31.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/31.rom_ctrl_stress_all_with_rand_reset.493649636
Short name T19
Test name
Test status
Simulation time 88441004858 ps
CPU time 3156.35 seconds
Started Apr 28 12:41:17 PM PDT 24
Finished Apr 28 01:33:55 PM PDT 24
Peak memory 249828 kb
Host smart-5f4784e1-f60d-40b4-8a81-ca90103e5b13
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=493649636 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_stress_all_with_rand_reset.493649636
Directory /workspace/31.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.rom_ctrl_alert_test.1339345404
Short name T351
Test name
Test status
Simulation time 5720549455 ps
CPU time 17.02 seconds
Started Apr 28 12:41:17 PM PDT 24
Finished Apr 28 12:41:35 PM PDT 24
Peak memory 211392 kb
Host smart-372e88cc-d92a-497e-9485-918cffb3a0f9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1339345404 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_alert_test.1339345404
Directory /workspace/32.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/32.rom_ctrl_kmac_err_chk.372003320
Short name T194
Test name
Test status
Simulation time 9202298978 ps
CPU time 22.83 seconds
Started Apr 28 12:41:18 PM PDT 24
Finished Apr 28 12:41:42 PM PDT 24
Peak memory 212360 kb
Host smart-5b40040f-345a-4065-937b-cea9e7597bd6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=372003320 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_kmac_err_chk.372003320
Directory /workspace/32.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/32.rom_ctrl_max_throughput_chk.225908650
Short name T268
Test name
Test status
Simulation time 1553604539 ps
CPU time 14.14 seconds
Started Apr 28 12:41:22 PM PDT 24
Finished Apr 28 12:41:39 PM PDT 24
Peak memory 211296 kb
Host smart-e9ad7330-6146-4ca4-81ed-159ea6c607fd
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=225908650 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_max_throughput_chk.225908650
Directory /workspace/32.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/32.rom_ctrl_smoke.1523238752
Short name T260
Test name
Test status
Simulation time 3024392961 ps
CPU time 34.17 seconds
Started Apr 28 12:41:20 PM PDT 24
Finished Apr 28 12:41:56 PM PDT 24
Peak memory 213880 kb
Host smart-86449ca3-1261-4264-9c40-8521670b499c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1523238752 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_smoke.1523238752
Directory /workspace/32.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/32.rom_ctrl_stress_all.751002813
Short name T105
Test name
Test status
Simulation time 2155521487 ps
CPU time 23.95 seconds
Started Apr 28 12:41:22 PM PDT 24
Finished Apr 28 12:41:48 PM PDT 24
Peak memory 214072 kb
Host smart-65ebfbff-d804-43e4-b3f4-193d1759ddb9
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=751002813 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 32.rom_ctrl_stress_all.751002813
Directory /workspace/32.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/33.rom_ctrl_alert_test.2619059910
Short name T66
Test name
Test status
Simulation time 523261857 ps
CPU time 5.06 seconds
Started Apr 28 12:41:15 PM PDT 24
Finished Apr 28 12:41:22 PM PDT 24
Peak memory 211296 kb
Host smart-d14d27a9-d62a-42c1-b938-eebaef41171c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2619059910 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_alert_test.2619059910
Directory /workspace/33.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/33.rom_ctrl_corrupt_sig_fatal_chk.3024467174
Short name T319
Test name
Test status
Simulation time 129020184785 ps
CPU time 311.64 seconds
Started Apr 28 12:41:18 PM PDT 24
Finished Apr 28 12:46:31 PM PDT 24
Peak memory 218808 kb
Host smart-47de55cb-edb6-4200-bd39-840b2ee8f918
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3024467174 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_
corrupt_sig_fatal_chk.3024467174
Directory /workspace/33.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/33.rom_ctrl_kmac_err_chk.365111149
Short name T44
Test name
Test status
Simulation time 44099015272 ps
CPU time 31.5 seconds
Started Apr 28 12:41:36 PM PDT 24
Finished Apr 28 12:42:09 PM PDT 24
Peak memory 212324 kb
Host smart-be46539c-637f-45d1-873f-ac152d1f85ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=365111149 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_kmac_err_chk.365111149
Directory /workspace/33.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/33.rom_ctrl_max_throughput_chk.605484268
Short name T305
Test name
Test status
Simulation time 1201486015 ps
CPU time 12.37 seconds
Started Apr 28 12:41:18 PM PDT 24
Finished Apr 28 12:41:32 PM PDT 24
Peak memory 211244 kb
Host smart-1e8b1c28-8678-49e9-9424-7960b0b83783
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=605484268 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_max_throughput_chk.605484268
Directory /workspace/33.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/33.rom_ctrl_smoke.777934679
Short name T142
Test name
Test status
Simulation time 37882342265 ps
CPU time 23.13 seconds
Started Apr 28 12:41:19 PM PDT 24
Finished Apr 28 12:41:43 PM PDT 24
Peak memory 214640 kb
Host smart-11bf7070-5f5e-4911-a4b7-9e107e8df480
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=777934679 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_smoke.777934679
Directory /workspace/33.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/33.rom_ctrl_stress_all.1878162128
Short name T279
Test name
Test status
Simulation time 4067927879 ps
CPU time 17.75 seconds
Started Apr 28 12:41:20 PM PDT 24
Finished Apr 28 12:41:38 PM PDT 24
Peak memory 212232 kb
Host smart-b58f2bd1-1bb8-4be0-9ef4-8b09203efe1b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1878162128 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 33.rom_ctrl_stress_all.1878162128
Directory /workspace/33.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/34.rom_ctrl_alert_test.1954864343
Short name T153
Test name
Test status
Simulation time 361849340 ps
CPU time 4.19 seconds
Started Apr 28 12:41:19 PM PDT 24
Finished Apr 28 12:41:24 PM PDT 24
Peak memory 211424 kb
Host smart-7c94b22d-823c-4e53-9f1d-b6b72463e033
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1954864343 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_alert_test.1954864343
Directory /workspace/34.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/34.rom_ctrl_corrupt_sig_fatal_chk.531990807
Short name T259
Test name
Test status
Simulation time 4194118771 ps
CPU time 79.94 seconds
Started Apr 28 12:41:23 PM PDT 24
Finished Apr 28 12:42:46 PM PDT 24
Peak memory 233924 kb
Host smart-dff0e515-8844-48a4-ab1c-9158e87c6d1a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=531990807 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_c
orrupt_sig_fatal_chk.531990807
Directory /workspace/34.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/34.rom_ctrl_kmac_err_chk.984406873
Short name T159
Test name
Test status
Simulation time 3318373292 ps
CPU time 30.21 seconds
Started Apr 28 12:41:24 PM PDT 24
Finished Apr 28 12:41:57 PM PDT 24
Peak memory 212016 kb
Host smart-2266107e-5f47-49f8-9957-79ea420dbeb5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=984406873 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_kmac_err_chk.984406873
Directory /workspace/34.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/34.rom_ctrl_max_throughput_chk.2129331282
Short name T195
Test name
Test status
Simulation time 391632077 ps
CPU time 5.78 seconds
Started Apr 28 12:41:30 PM PDT 24
Finished Apr 28 12:41:39 PM PDT 24
Peak memory 211288 kb
Host smart-3e0a91b3-4502-439d-a3a4-a2d5a7e39348
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2129331282 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_max_throughput_chk.2129331282
Directory /workspace/34.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/34.rom_ctrl_smoke.624382635
Short name T230
Test name
Test status
Simulation time 2221595331 ps
CPU time 21.53 seconds
Started Apr 28 12:41:34 PM PDT 24
Finished Apr 28 12:41:56 PM PDT 24
Peak memory 213084 kb
Host smart-1b1389df-e29d-4c91-9c50-8d299566d787
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=624382635 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_smoke.624382635
Directory /workspace/34.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/35.rom_ctrl_alert_test.2628177605
Short name T204
Test name
Test status
Simulation time 2142776830 ps
CPU time 11.28 seconds
Started Apr 28 12:41:39 PM PDT 24
Finished Apr 28 12:41:51 PM PDT 24
Peak memory 211428 kb
Host smart-a78dbf0c-e5f8-4b93-b60e-e29f9e4d137f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2628177605 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_alert_test.2628177605
Directory /workspace/35.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/35.rom_ctrl_corrupt_sig_fatal_chk.139530787
Short name T136
Test name
Test status
Simulation time 12218907694 ps
CPU time 112.72 seconds
Started Apr 28 12:41:31 PM PDT 24
Finished Apr 28 12:43:24 PM PDT 24
Peak memory 211604 kb
Host smart-c261a5a2-0e4f-4437-9f03-76f3d7254a5a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=139530787 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_c
orrupt_sig_fatal_chk.139530787
Directory /workspace/35.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/35.rom_ctrl_kmac_err_chk.496102371
Short name T353
Test name
Test status
Simulation time 7999378138 ps
CPU time 28.59 seconds
Started Apr 28 12:41:25 PM PDT 24
Finished Apr 28 12:41:57 PM PDT 24
Peak memory 212392 kb
Host smart-8479111e-a10a-4872-9d0f-fdbc51f4840a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=496102371 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_kmac_err_chk.496102371
Directory /workspace/35.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/35.rom_ctrl_max_throughput_chk.2439288079
Short name T144
Test name
Test status
Simulation time 899425230 ps
CPU time 6.83 seconds
Started Apr 28 12:41:21 PM PDT 24
Finished Apr 28 12:41:30 PM PDT 24
Peak memory 211276 kb
Host smart-55c0870f-901f-40e6-9e15-b5be1590702d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2439288079 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_max_throughput_chk.2439288079
Directory /workspace/35.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/35.rom_ctrl_smoke.2219913415
Short name T367
Test name
Test status
Simulation time 365975139 ps
CPU time 10.11 seconds
Started Apr 28 12:41:32 PM PDT 24
Finished Apr 28 12:41:43 PM PDT 24
Peak memory 213172 kb
Host smart-a09a2d6d-8a0e-403c-889a-b1197899ed2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2219913415 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_smoke.2219913415
Directory /workspace/35.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/35.rom_ctrl_stress_all.1249167124
Short name T77
Test name
Test status
Simulation time 1605451154 ps
CPU time 15.45 seconds
Started Apr 28 12:41:22 PM PDT 24
Finished Apr 28 12:41:41 PM PDT 24
Peak memory 219460 kb
Host smart-ff94dac4-c678-449a-b349-b1de91a48eae
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1249167124 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 35.rom_ctrl_stress_all.1249167124
Directory /workspace/35.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/35.rom_ctrl_stress_all_with_rand_reset.745742242
Short name T18
Test name
Test status
Simulation time 47201931157 ps
CPU time 831.16 seconds
Started Apr 28 12:41:21 PM PDT 24
Finished Apr 28 12:55:15 PM PDT 24
Peak memory 228000 kb
Host smart-db39e2ef-fb29-4a94-965b-d1b891e2256f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=745742242 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_stress_all_with_rand_reset.745742242
Directory /workspace/35.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.rom_ctrl_alert_test.2545019004
Short name T192
Test name
Test status
Simulation time 2178959423 ps
CPU time 11.1 seconds
Started Apr 28 12:41:40 PM PDT 24
Finished Apr 28 12:41:52 PM PDT 24
Peak memory 211384 kb
Host smart-c8144be8-8d16-4462-80ca-b3582911e556
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2545019004 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_alert_test.2545019004
Directory /workspace/36.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/36.rom_ctrl_corrupt_sig_fatal_chk.465223747
Short name T341
Test name
Test status
Simulation time 56812005457 ps
CPU time 258.23 seconds
Started Apr 28 12:41:10 PM PDT 24
Finished Apr 28 12:45:30 PM PDT 24
Peak memory 211584 kb
Host smart-12eebe86-fbd3-4cee-b49f-8eab49817a16
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=465223747 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_c
orrupt_sig_fatal_chk.465223747
Directory /workspace/36.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/36.rom_ctrl_kmac_err_chk.4152081935
Short name T23
Test name
Test status
Simulation time 693156124 ps
CPU time 9.33 seconds
Started Apr 28 12:41:17 PM PDT 24
Finished Apr 28 12:41:28 PM PDT 24
Peak memory 211384 kb
Host smart-f43bd3ed-f9b9-4a48-938d-136840c0d71e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4152081935 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_kmac_err_chk.4152081935
Directory /workspace/36.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/36.rom_ctrl_max_throughput_chk.3734949137
Short name T41
Test name
Test status
Simulation time 405157201 ps
CPU time 8.2 seconds
Started Apr 28 12:41:23 PM PDT 24
Finished Apr 28 12:41:34 PM PDT 24
Peak memory 211276 kb
Host smart-3f0bb386-ef2d-402d-883d-8d85da19c81b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3734949137 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_max_throughput_chk.3734949137
Directory /workspace/36.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/36.rom_ctrl_smoke.2258126207
Short name T7
Test name
Test status
Simulation time 5885321115 ps
CPU time 19.26 seconds
Started Apr 28 12:41:15 PM PDT 24
Finished Apr 28 12:41:36 PM PDT 24
Peak memory 214580 kb
Host smart-5a79b13d-96d2-48a8-a737-69b774fcac4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2258126207 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_smoke.2258126207
Directory /workspace/36.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/36.rom_ctrl_stress_all.930770686
Short name T357
Test name
Test status
Simulation time 627555620 ps
CPU time 7.57 seconds
Started Apr 28 12:41:29 PM PDT 24
Finished Apr 28 12:41:37 PM PDT 24
Peak memory 211324 kb
Host smart-b1fcbde8-7e79-4242-9394-53a04d70ab34
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=930770686 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 36.rom_ctrl_stress_all.930770686
Directory /workspace/36.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/36.rom_ctrl_stress_all_with_rand_reset.760503741
Short name T20
Test name
Test status
Simulation time 18430829671 ps
CPU time 698.74 seconds
Started Apr 28 12:41:17 PM PDT 24
Finished Apr 28 12:52:57 PM PDT 24
Peak memory 233808 kb
Host smart-aa5ad94f-45cb-40e0-b244-a7a7ee93c2da
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=760503741 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_stress_all_with_rand_reset.760503741
Directory /workspace/36.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.rom_ctrl_alert_test.1076802267
Short name T335
Test name
Test status
Simulation time 1946291219 ps
CPU time 6.79 seconds
Started Apr 28 12:41:18 PM PDT 24
Finished Apr 28 12:41:26 PM PDT 24
Peak memory 211340 kb
Host smart-f0ad02f9-064a-4f1e-952c-252d9a3967e0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1076802267 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_alert_test.1076802267
Directory /workspace/37.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/37.rom_ctrl_corrupt_sig_fatal_chk.2912182809
Short name T48
Test name
Test status
Simulation time 7909200985 ps
CPU time 125.23 seconds
Started Apr 28 12:41:31 PM PDT 24
Finished Apr 28 12:43:37 PM PDT 24
Peak memory 235048 kb
Host smart-628c3c6a-26b6-433b-b391-524307d9d075
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2912182809 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_
corrupt_sig_fatal_chk.2912182809
Directory /workspace/37.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/37.rom_ctrl_kmac_err_chk.2946091812
Short name T185
Test name
Test status
Simulation time 2996201731 ps
CPU time 17.19 seconds
Started Apr 28 12:41:28 PM PDT 24
Finished Apr 28 12:41:47 PM PDT 24
Peak memory 211928 kb
Host smart-239db696-9a16-489a-aab1-af7c2b59a2b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2946091812 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_kmac_err_chk.2946091812
Directory /workspace/37.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/37.rom_ctrl_max_throughput_chk.4192466854
Short name T283
Test name
Test status
Simulation time 2137358852 ps
CPU time 12.11 seconds
Started Apr 28 12:41:23 PM PDT 24
Finished Apr 28 12:41:38 PM PDT 24
Peak memory 211252 kb
Host smart-ceeb83bd-541e-49bb-813a-29aff5f033d7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4192466854 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_max_throughput_chk.4192466854
Directory /workspace/37.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/37.rom_ctrl_smoke.2106698140
Short name T363
Test name
Test status
Simulation time 7889205022 ps
CPU time 22.11 seconds
Started Apr 28 12:41:24 PM PDT 24
Finished Apr 28 12:41:49 PM PDT 24
Peak memory 214968 kb
Host smart-9abb7ffe-aaa1-48c2-8ea3-dbea3c00e064
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2106698140 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_smoke.2106698140
Directory /workspace/37.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/37.rom_ctrl_stress_all.3282998871
Short name T171
Test name
Test status
Simulation time 5945775703 ps
CPU time 21.66 seconds
Started Apr 28 12:41:37 PM PDT 24
Finished Apr 28 12:42:00 PM PDT 24
Peak memory 215064 kb
Host smart-a3233f4d-a7cf-4dcf-9569-f50eeedd513f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3282998871 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 37.rom_ctrl_stress_all.3282998871
Directory /workspace/37.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/38.rom_ctrl_alert_test.930403538
Short name T278
Test name
Test status
Simulation time 1547428711 ps
CPU time 13.57 seconds
Started Apr 28 12:41:24 PM PDT 24
Finished Apr 28 12:41:40 PM PDT 24
Peak memory 211312 kb
Host smart-b0d1a39b-d7bc-4135-9704-c88507f6dae3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=930403538 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_alert_test.930403538
Directory /workspace/38.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/38.rom_ctrl_corrupt_sig_fatal_chk.3451998377
Short name T24
Test name
Test status
Simulation time 27719806126 ps
CPU time 268.56 seconds
Started Apr 28 12:41:21 PM PDT 24
Finished Apr 28 12:45:51 PM PDT 24
Peak memory 230264 kb
Host smart-b2c2f0a0-c11c-4c41-9289-679ce601c3f5
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3451998377 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_
corrupt_sig_fatal_chk.3451998377
Directory /workspace/38.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/38.rom_ctrl_kmac_err_chk.149812406
Short name T277
Test name
Test status
Simulation time 315448055 ps
CPU time 9.53 seconds
Started Apr 28 12:41:32 PM PDT 24
Finished Apr 28 12:41:43 PM PDT 24
Peak memory 212136 kb
Host smart-8c47cf08-a4b5-4d3d-8b0e-f1a0763a4db5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=149812406 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_kmac_err_chk.149812406
Directory /workspace/38.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/38.rom_ctrl_max_throughput_chk.2504537964
Short name T275
Test name
Test status
Simulation time 1752692831 ps
CPU time 13.94 seconds
Started Apr 28 12:41:28 PM PDT 24
Finished Apr 28 12:41:43 PM PDT 24
Peak memory 211196 kb
Host smart-329e34dd-1a66-4c40-b449-78cd44551ec6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2504537964 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_max_throughput_chk.2504537964
Directory /workspace/38.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/38.rom_ctrl_smoke.1195540687
Short name T139
Test name
Test status
Simulation time 218259813 ps
CPU time 10.61 seconds
Started Apr 28 12:41:17 PM PDT 24
Finished Apr 28 12:41:29 PM PDT 24
Peak memory 219524 kb
Host smart-38c9be4d-3027-4152-b712-3d74652f3a6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1195540687 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_smoke.1195540687
Directory /workspace/38.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/38.rom_ctrl_stress_all.1405958821
Short name T334
Test name
Test status
Simulation time 9891299123 ps
CPU time 26.39 seconds
Started Apr 28 12:41:30 PM PDT 24
Finished Apr 28 12:41:57 PM PDT 24
Peak memory 214472 kb
Host smart-86f29ed0-190e-472d-90b5-752a719543ec
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1405958821 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 38.rom_ctrl_stress_all.1405958821
Directory /workspace/38.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/38.rom_ctrl_stress_all_with_rand_reset.1941003920
Short name T119
Test name
Test status
Simulation time 197935850672 ps
CPU time 1665.17 seconds
Started Apr 28 12:41:22 PM PDT 24
Finished Apr 28 01:09:10 PM PDT 24
Peak memory 236436 kb
Host smart-7b41e3f5-9433-4b29-bb8d-06b9ec4ccbb3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1941003920 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_stress_all_with_rand_reset.1941003920
Directory /workspace/38.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.rom_ctrl_alert_test.1656115748
Short name T339
Test name
Test status
Simulation time 7121076576 ps
CPU time 14.95 seconds
Started Apr 28 12:41:24 PM PDT 24
Finished Apr 28 12:41:42 PM PDT 24
Peak memory 211376 kb
Host smart-8ee0edd9-5faa-4774-97de-b3b6dcfc0000
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1656115748 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_alert_test.1656115748
Directory /workspace/39.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/39.rom_ctrl_corrupt_sig_fatal_chk.2714016362
Short name T157
Test name
Test status
Simulation time 38266662291 ps
CPU time 138.38 seconds
Started Apr 28 12:41:23 PM PDT 24
Finished Apr 28 12:43:45 PM PDT 24
Peak memory 238100 kb
Host smart-5af220e5-a452-4594-b9c1-5fa899a33c84
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2714016362 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_
corrupt_sig_fatal_chk.2714016362
Directory /workspace/39.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/39.rom_ctrl_kmac_err_chk.1959875341
Short name T309
Test name
Test status
Simulation time 27872741433 ps
CPU time 26.34 seconds
Started Apr 28 12:41:48 PM PDT 24
Finished Apr 28 12:42:16 PM PDT 24
Peak memory 212308 kb
Host smart-925dd9a5-47b5-4f2b-a45a-60a6aa9e1de2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1959875341 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_kmac_err_chk.1959875341
Directory /workspace/39.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/39.rom_ctrl_max_throughput_chk.3392883677
Short name T298
Test name
Test status
Simulation time 1126439292 ps
CPU time 11.48 seconds
Started Apr 28 12:41:22 PM PDT 24
Finished Apr 28 12:41:36 PM PDT 24
Peak memory 211292 kb
Host smart-55df4e63-d474-4b8f-b25a-cb98b1376b22
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3392883677 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_max_throughput_chk.3392883677
Directory /workspace/39.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/39.rom_ctrl_smoke.965549010
Short name T5
Test name
Test status
Simulation time 700116938 ps
CPU time 10.02 seconds
Started Apr 28 12:41:22 PM PDT 24
Finished Apr 28 12:41:35 PM PDT 24
Peak memory 213232 kb
Host smart-7772062e-0166-400b-b33f-122176f947ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=965549010 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_smoke.965549010
Directory /workspace/39.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/39.rom_ctrl_stress_all.2400188947
Short name T167
Test name
Test status
Simulation time 41610880317 ps
CPU time 72.82 seconds
Started Apr 28 12:41:20 PM PDT 24
Finished Apr 28 12:42:34 PM PDT 24
Peak memory 217056 kb
Host smart-87fb3b01-ad16-4a74-a1e1-7f0fda30a48a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2400188947 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 39.rom_ctrl_stress_all.2400188947
Directory /workspace/39.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/39.rom_ctrl_stress_all_with_rand_reset.4278671391
Short name T52
Test name
Test status
Simulation time 177646834034 ps
CPU time 3339.52 seconds
Started Apr 28 12:41:22 PM PDT 24
Finished Apr 28 01:37:04 PM PDT 24
Peak memory 249344 kb
Host smart-648534f3-72e1-49cc-b615-5c378179cd97
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4278671391 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_stress_all_with_rand_reset.4278671391
Directory /workspace/39.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.rom_ctrl_alert_test.3857599749
Short name T99
Test name
Test status
Simulation time 89196162 ps
CPU time 4.25 seconds
Started Apr 28 12:40:55 PM PDT 24
Finished Apr 28 12:41:00 PM PDT 24
Peak memory 211348 kb
Host smart-585203c2-12fb-4cae-8fd2-cf43fafa9790
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3857599749 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_alert_test.3857599749
Directory /workspace/4.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/4.rom_ctrl_corrupt_sig_fatal_chk.2089570962
Short name T40
Test name
Test status
Simulation time 88426225440 ps
CPU time 155.97 seconds
Started Apr 28 12:41:11 PM PDT 24
Finished Apr 28 12:43:49 PM PDT 24
Peak memory 224792 kb
Host smart-1e6dbf3f-8874-415c-bce1-2f2618a68192
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2089570962 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_c
orrupt_sig_fatal_chk.2089570962
Directory /workspace/4.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/4.rom_ctrl_kmac_err_chk.3085502268
Short name T27
Test name
Test status
Simulation time 15962692133 ps
CPU time 33.67 seconds
Started Apr 28 12:40:53 PM PDT 24
Finished Apr 28 12:41:28 PM PDT 24
Peak memory 212104 kb
Host smart-f9ac39d9-8781-423f-b453-0571a6c6f369
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3085502268 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_kmac_err_chk.3085502268
Directory /workspace/4.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/4.rom_ctrl_max_throughput_chk.1663321864
Short name T238
Test name
Test status
Simulation time 1361509822 ps
CPU time 13.54 seconds
Started Apr 28 12:41:04 PM PDT 24
Finished Apr 28 12:41:19 PM PDT 24
Peak memory 211292 kb
Host smart-6d083682-610c-48c3-98b2-c92d99154aa4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1663321864 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_max_throughput_chk.1663321864
Directory /workspace/4.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/4.rom_ctrl_smoke.2427360381
Short name T331
Test name
Test status
Simulation time 370446235 ps
CPU time 10.12 seconds
Started Apr 28 12:41:01 PM PDT 24
Finished Apr 28 12:41:13 PM PDT 24
Peak memory 213252 kb
Host smart-651141af-63da-4b3d-bbc0-2024d340a5a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2427360381 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_smoke.2427360381
Directory /workspace/4.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/4.rom_ctrl_stress_all.1226937679
Short name T348
Test name
Test status
Simulation time 11865377965 ps
CPU time 31.89 seconds
Started Apr 28 12:41:11 PM PDT 24
Finished Apr 28 12:41:45 PM PDT 24
Peak memory 219548 kb
Host smart-2f527fe6-d21a-484b-a490-aeadb5b27202
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1226937679 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 4.rom_ctrl_stress_all.1226937679
Directory /workspace/4.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/4.rom_ctrl_stress_all_with_rand_reset.297287818
Short name T251
Test name
Test status
Simulation time 42082469360 ps
CPU time 3633.89 seconds
Started Apr 28 12:41:10 PM PDT 24
Finished Apr 28 01:41:46 PM PDT 24
Peak memory 236108 kb
Host smart-b3261fe4-f2cd-4eaa-90e5-c159ff52e0ca
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=297287818 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_stress_all_with_rand_reset.297287818
Directory /workspace/4.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.rom_ctrl_alert_test.2684559822
Short name T174
Test name
Test status
Simulation time 1862606988 ps
CPU time 15.26 seconds
Started Apr 28 12:41:23 PM PDT 24
Finished Apr 28 12:41:41 PM PDT 24
Peak memory 211356 kb
Host smart-b60c2c2c-3157-4499-b03e-85a1fb715663
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2684559822 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_alert_test.2684559822
Directory /workspace/40.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/40.rom_ctrl_corrupt_sig_fatal_chk.4043179217
Short name T143
Test name
Test status
Simulation time 18023762739 ps
CPU time 202.78 seconds
Started Apr 28 12:41:23 PM PDT 24
Finished Apr 28 12:44:48 PM PDT 24
Peak memory 230352 kb
Host smart-36d388dc-48d6-477f-baa0-4bb9ca5ff88a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4043179217 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_
corrupt_sig_fatal_chk.4043179217
Directory /workspace/40.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/40.rom_ctrl_kmac_err_chk.1056470488
Short name T248
Test name
Test status
Simulation time 10699639319 ps
CPU time 34.35 seconds
Started Apr 28 12:41:25 PM PDT 24
Finished Apr 28 12:42:03 PM PDT 24
Peak memory 211428 kb
Host smart-009bea2b-8b0b-4cdf-82ab-661429bc72c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1056470488 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_kmac_err_chk.1056470488
Directory /workspace/40.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/40.rom_ctrl_max_throughput_chk.2111053595
Short name T42
Test name
Test status
Simulation time 98052120 ps
CPU time 5.91 seconds
Started Apr 28 12:41:22 PM PDT 24
Finished Apr 28 12:41:33 PM PDT 24
Peak memory 211284 kb
Host smart-f69fbd98-bd6b-44a1-b182-673c229f2941
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2111053595 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_max_throughput_chk.2111053595
Directory /workspace/40.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/40.rom_ctrl_smoke.1136823251
Short name T294
Test name
Test status
Simulation time 21013176495 ps
CPU time 22 seconds
Started Apr 28 12:41:40 PM PDT 24
Finished Apr 28 12:42:04 PM PDT 24
Peak memory 214388 kb
Host smart-09d3e6de-c98e-44b3-ada8-f874d334e8ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1136823251 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_smoke.1136823251
Directory /workspace/40.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/40.rom_ctrl_stress_all.2916556279
Short name T155
Test name
Test status
Simulation time 8313334416 ps
CPU time 26.15 seconds
Started Apr 28 12:41:36 PM PDT 24
Finished Apr 28 12:42:04 PM PDT 24
Peak memory 219556 kb
Host smart-7f31f2c6-5631-43e5-92f4-6c49f5740b05
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2916556279 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 40.rom_ctrl_stress_all.2916556279
Directory /workspace/40.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/41.rom_ctrl_alert_test.1807489850
Short name T170
Test name
Test status
Simulation time 412116096 ps
CPU time 7.16 seconds
Started Apr 28 12:41:35 PM PDT 24
Finished Apr 28 12:41:43 PM PDT 24
Peak memory 211304 kb
Host smart-e0686465-2cc9-4b02-8a55-4d5c3f631eb1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1807489850 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_alert_test.1807489850
Directory /workspace/41.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/41.rom_ctrl_corrupt_sig_fatal_chk.2764569673
Short name T152
Test name
Test status
Simulation time 9102653548 ps
CPU time 95.21 seconds
Started Apr 28 12:41:24 PM PDT 24
Finished Apr 28 12:43:03 PM PDT 24
Peak memory 238920 kb
Host smart-356e5d1e-8557-442a-b84a-deca69a2f2b8
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2764569673 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_
corrupt_sig_fatal_chk.2764569673
Directory /workspace/41.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/41.rom_ctrl_kmac_err_chk.3655734909
Short name T360
Test name
Test status
Simulation time 279870024 ps
CPU time 9.47 seconds
Started Apr 28 12:41:25 PM PDT 24
Finished Apr 28 12:41:38 PM PDT 24
Peak memory 212028 kb
Host smart-22d85f39-f65f-430d-b3ac-7860974d95f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3655734909 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_kmac_err_chk.3655734909
Directory /workspace/41.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/41.rom_ctrl_max_throughput_chk.705057378
Short name T165
Test name
Test status
Simulation time 15830688458 ps
CPU time 16.3 seconds
Started Apr 28 12:41:41 PM PDT 24
Finished Apr 28 12:41:59 PM PDT 24
Peak memory 211404 kb
Host smart-a97eb340-bb8a-4920-9f96-cc69aede87d7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=705057378 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_max_throughput_chk.705057378
Directory /workspace/41.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/41.rom_ctrl_smoke.4273901945
Short name T229
Test name
Test status
Simulation time 1089876088 ps
CPU time 11.52 seconds
Started Apr 28 12:41:24 PM PDT 24
Finished Apr 28 12:41:38 PM PDT 24
Peak memory 219516 kb
Host smart-b7d52bc8-3219-4a56-8bec-d1b920fbc526
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4273901945 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_smoke.4273901945
Directory /workspace/41.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/41.rom_ctrl_stress_all.4197520440
Short name T203
Test name
Test status
Simulation time 12086181484 ps
CPU time 54.36 seconds
Started Apr 28 12:41:45 PM PDT 24
Finished Apr 28 12:42:41 PM PDT 24
Peak memory 216504 kb
Host smart-048ca526-ec9d-42f9-a31a-ab835b92e5e0
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4197520440 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 41.rom_ctrl_stress_all.4197520440
Directory /workspace/41.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/42.rom_ctrl_alert_test.2805259040
Short name T304
Test name
Test status
Simulation time 1317929600 ps
CPU time 12.2 seconds
Started Apr 28 12:41:27 PM PDT 24
Finished Apr 28 12:41:41 PM PDT 24
Peak memory 211448 kb
Host smart-f6593ab6-b09a-44d8-a96e-5a52e8300f1c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2805259040 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_alert_test.2805259040
Directory /workspace/42.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/42.rom_ctrl_corrupt_sig_fatal_chk.345492263
Short name T45
Test name
Test status
Simulation time 169664928206 ps
CPU time 382.15 seconds
Started Apr 28 12:41:18 PM PDT 24
Finished Apr 28 12:47:42 PM PDT 24
Peak memory 219796 kb
Host smart-26346e0f-414b-4057-9e86-2646569b95bd
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=345492263 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_c
orrupt_sig_fatal_chk.345492263
Directory /workspace/42.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/42.rom_ctrl_kmac_err_chk.2180280933
Short name T199
Test name
Test status
Simulation time 3356719661 ps
CPU time 30.05 seconds
Started Apr 28 12:41:41 PM PDT 24
Finished Apr 28 12:42:14 PM PDT 24
Peak memory 212056 kb
Host smart-31fa8552-ce58-4968-9221-90be0f4ffbe3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2180280933 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_kmac_err_chk.2180280933
Directory /workspace/42.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/42.rom_ctrl_max_throughput_chk.3758328371
Short name T212
Test name
Test status
Simulation time 5046236304 ps
CPU time 13.22 seconds
Started Apr 28 12:41:24 PM PDT 24
Finished Apr 28 12:41:41 PM PDT 24
Peak memory 211284 kb
Host smart-5c8a6888-fa9e-49cd-a0e9-ad0b1353b694
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3758328371 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_max_throughput_chk.3758328371
Directory /workspace/42.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/42.rom_ctrl_smoke.660511024
Short name T240
Test name
Test status
Simulation time 667867237 ps
CPU time 12.63 seconds
Started Apr 28 12:41:24 PM PDT 24
Finished Apr 28 12:41:40 PM PDT 24
Peak memory 213700 kb
Host smart-cb7dfe94-0798-4966-9a7b-568d63b15d00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=660511024 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_smoke.660511024
Directory /workspace/42.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/42.rom_ctrl_stress_all.1059181148
Short name T206
Test name
Test status
Simulation time 11988359461 ps
CPU time 39.77 seconds
Started Apr 28 12:41:21 PM PDT 24
Finished Apr 28 12:42:02 PM PDT 24
Peak memory 217224 kb
Host smart-6db92593-4930-4503-888d-cdabe395171a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1059181148 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 42.rom_ctrl_stress_all.1059181148
Directory /workspace/42.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/43.rom_ctrl_alert_test.4158139216
Short name T338
Test name
Test status
Simulation time 6566349394 ps
CPU time 8.4 seconds
Started Apr 28 12:41:20 PM PDT 24
Finished Apr 28 12:41:29 PM PDT 24
Peak memory 211420 kb
Host smart-0f365757-bccd-4866-bc76-431afb9557e0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4158139216 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_alert_test.4158139216
Directory /workspace/43.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/43.rom_ctrl_corrupt_sig_fatal_chk.1860293225
Short name T299
Test name
Test status
Simulation time 91488076441 ps
CPU time 261.41 seconds
Started Apr 28 12:41:25 PM PDT 24
Finished Apr 28 12:45:50 PM PDT 24
Peak memory 238008 kb
Host smart-853d778e-1e58-40d6-a8bb-61eabf050e7c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1860293225 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_
corrupt_sig_fatal_chk.1860293225
Directory /workspace/43.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/43.rom_ctrl_kmac_err_chk.2741565272
Short name T98
Test name
Test status
Simulation time 526243739 ps
CPU time 13.14 seconds
Started Apr 28 12:41:26 PM PDT 24
Finished Apr 28 12:41:41 PM PDT 24
Peak memory 212036 kb
Host smart-fbdaf738-f752-42a7-a671-a303dd1842be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2741565272 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_kmac_err_chk.2741565272
Directory /workspace/43.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/43.rom_ctrl_max_throughput_chk.298632596
Short name T282
Test name
Test status
Simulation time 187537048 ps
CPU time 5.44 seconds
Started Apr 28 12:41:30 PM PDT 24
Finished Apr 28 12:41:38 PM PDT 24
Peak memory 211300 kb
Host smart-4b258b77-e255-45c1-99d5-31be816d3a0c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=298632596 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_max_throughput_chk.298632596
Directory /workspace/43.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/43.rom_ctrl_smoke.3336897925
Short name T151
Test name
Test status
Simulation time 3171460432 ps
CPU time 18.82 seconds
Started Apr 28 12:41:45 PM PDT 24
Finished Apr 28 12:42:05 PM PDT 24
Peak memory 213064 kb
Host smart-f8f3a377-c858-4062-b255-8d2595715f09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3336897925 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_smoke.3336897925
Directory /workspace/43.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/43.rom_ctrl_stress_all.3208776240
Short name T356
Test name
Test status
Simulation time 8445832645 ps
CPU time 65.11 seconds
Started Apr 28 12:41:41 PM PDT 24
Finished Apr 28 12:42:49 PM PDT 24
Peak memory 215656 kb
Host smart-50674693-73d8-4218-898c-7208348cdec3
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3208776240 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 43.rom_ctrl_stress_all.3208776240
Directory /workspace/43.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/44.rom_ctrl_alert_test.1314598869
Short name T250
Test name
Test status
Simulation time 627304295 ps
CPU time 8.92 seconds
Started Apr 28 12:41:33 PM PDT 24
Finished Apr 28 12:41:43 PM PDT 24
Peak memory 211448 kb
Host smart-dcbcc446-386e-4c8f-a9a9-0c89d1e57285
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1314598869 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_alert_test.1314598869
Directory /workspace/44.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/44.rom_ctrl_corrupt_sig_fatal_chk.2644505590
Short name T256
Test name
Test status
Simulation time 6734081644 ps
CPU time 99.28 seconds
Started Apr 28 12:41:41 PM PDT 24
Finished Apr 28 12:43:22 PM PDT 24
Peak memory 220912 kb
Host smart-6be12ef3-50e0-4703-80de-2f67d9a39757
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2644505590 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_
corrupt_sig_fatal_chk.2644505590
Directory /workspace/44.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/44.rom_ctrl_kmac_err_chk.1841638079
Short name T255
Test name
Test status
Simulation time 3125714315 ps
CPU time 27.13 seconds
Started Apr 28 12:41:23 PM PDT 24
Finished Apr 28 12:41:53 PM PDT 24
Peak memory 212248 kb
Host smart-38871fee-0801-4a0e-b64c-5772bac5fdc4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1841638079 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_kmac_err_chk.1841638079
Directory /workspace/44.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/44.rom_ctrl_max_throughput_chk.1673755452
Short name T16
Test name
Test status
Simulation time 23926764807 ps
CPU time 14.1 seconds
Started Apr 28 12:41:31 PM PDT 24
Finished Apr 28 12:41:46 PM PDT 24
Peak memory 211384 kb
Host smart-05f08e08-db5b-414b-85bc-a2ba2d48f5d8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1673755452 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_max_throughput_chk.1673755452
Directory /workspace/44.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/44.rom_ctrl_smoke.2740044027
Short name T9
Test name
Test status
Simulation time 3946787047 ps
CPU time 30.19 seconds
Started Apr 28 12:41:27 PM PDT 24
Finished Apr 28 12:41:59 PM PDT 24
Peak memory 219584 kb
Host smart-91b4bb86-ce50-494f-b07b-1630637e0850
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2740044027 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_smoke.2740044027
Directory /workspace/44.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/44.rom_ctrl_stress_all.1611392750
Short name T221
Test name
Test status
Simulation time 1516876494 ps
CPU time 17.54 seconds
Started Apr 28 12:41:32 PM PDT 24
Finished Apr 28 12:41:51 PM PDT 24
Peak memory 211164 kb
Host smart-53c8a066-0138-45a2-ad79-29e36a06eca3
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1611392750 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 44.rom_ctrl_stress_all.1611392750
Directory /workspace/44.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/44.rom_ctrl_stress_all_with_rand_reset.2961760631
Short name T51
Test name
Test status
Simulation time 135366948261 ps
CPU time 2783.61 seconds
Started Apr 28 12:41:23 PM PDT 24
Finished Apr 28 01:27:50 PM PDT 24
Peak memory 236040 kb
Host smart-d4611820-ed35-4930-8bf2-b1d8871de105
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2961760631 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_stress_all_with_rand_reset.2961760631
Directory /workspace/44.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.rom_ctrl_alert_test.2341928238
Short name T108
Test name
Test status
Simulation time 4438917494 ps
CPU time 10.72 seconds
Started Apr 28 12:41:19 PM PDT 24
Finished Apr 28 12:41:31 PM PDT 24
Peak memory 211400 kb
Host smart-ae8dedc4-22ce-4a5e-b49b-2a207dc4302e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2341928238 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_alert_test.2341928238
Directory /workspace/45.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/45.rom_ctrl_corrupt_sig_fatal_chk.3256066369
Short name T358
Test name
Test status
Simulation time 11976297548 ps
CPU time 180.99 seconds
Started Apr 28 12:41:24 PM PDT 24
Finished Apr 28 12:44:28 PM PDT 24
Peak memory 228800 kb
Host smart-a7423398-5baa-477e-ba2c-3efb68ecbe11
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3256066369 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_
corrupt_sig_fatal_chk.3256066369
Directory /workspace/45.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/45.rom_ctrl_kmac_err_chk.1220964225
Short name T270
Test name
Test status
Simulation time 7654047096 ps
CPU time 30.96 seconds
Started Apr 28 12:41:23 PM PDT 24
Finished Apr 28 12:41:57 PM PDT 24
Peak memory 212216 kb
Host smart-1ed96348-3623-4df7-8513-f1ff2125a5f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1220964225 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_kmac_err_chk.1220964225
Directory /workspace/45.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/45.rom_ctrl_max_throughput_chk.1770669832
Short name T190
Test name
Test status
Simulation time 16583625909 ps
CPU time 15.65 seconds
Started Apr 28 12:41:41 PM PDT 24
Finished Apr 28 12:41:59 PM PDT 24
Peak memory 211364 kb
Host smart-f3431d11-3cfe-4c2b-bc1e-811cc55ed180
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1770669832 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_max_throughput_chk.1770669832
Directory /workspace/45.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/45.rom_ctrl_smoke.314668796
Short name T266
Test name
Test status
Simulation time 2523866142 ps
CPU time 24.86 seconds
Started Apr 28 12:41:35 PM PDT 24
Finished Apr 28 12:42:01 PM PDT 24
Peak memory 219576 kb
Host smart-ea48b928-77dc-45c9-a78a-95d98fc4b756
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=314668796 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_smoke.314668796
Directory /workspace/45.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/45.rom_ctrl_stress_all.2786396458
Short name T352
Test name
Test status
Simulation time 472246021 ps
CPU time 26.6 seconds
Started Apr 28 12:41:41 PM PDT 24
Finished Apr 28 12:42:09 PM PDT 24
Peak memory 216036 kb
Host smart-4f33d6b1-e627-4e0a-8775-213186dfc568
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2786396458 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 45.rom_ctrl_stress_all.2786396458
Directory /workspace/45.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/45.rom_ctrl_stress_all_with_rand_reset.460741897
Short name T346
Test name
Test status
Simulation time 178953608331 ps
CPU time 4671.15 seconds
Started Apr 28 12:41:20 PM PDT 24
Finished Apr 28 01:59:13 PM PDT 24
Peak memory 236040 kb
Host smart-6e70cafd-7469-49e4-8ce0-8a7b9b6a5842
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=460741897 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_stress_all_with_rand_reset.460741897
Directory /workspace/45.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.rom_ctrl_alert_test.2997766783
Short name T302
Test name
Test status
Simulation time 1579894540 ps
CPU time 13.38 seconds
Started Apr 28 12:41:21 PM PDT 24
Finished Apr 28 12:41:36 PM PDT 24
Peak memory 211320 kb
Host smart-bf94491b-59f7-4c91-b2d8-2ff26942db1a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2997766783 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_alert_test.2997766783
Directory /workspace/46.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/46.rom_ctrl_corrupt_sig_fatal_chk.1643428942
Short name T135
Test name
Test status
Simulation time 81041660374 ps
CPU time 219.69 seconds
Started Apr 28 12:41:23 PM PDT 24
Finished Apr 28 12:45:06 PM PDT 24
Peak memory 236892 kb
Host smart-f4b3d5d1-6a10-4248-a9b8-0adf1c4c319d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1643428942 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_
corrupt_sig_fatal_chk.1643428942
Directory /workspace/46.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/46.rom_ctrl_kmac_err_chk.21822970
Short name T207
Test name
Test status
Simulation time 1957738227 ps
CPU time 21.13 seconds
Started Apr 28 12:41:48 PM PDT 24
Finished Apr 28 12:42:11 PM PDT 24
Peak memory 214124 kb
Host smart-d33cedf9-ffb7-47ec-bae1-50e004cd1ad7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=21822970 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_kmac_err_chk.21822970
Directory /workspace/46.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/46.rom_ctrl_max_throughput_chk.2625992792
Short name T179
Test name
Test status
Simulation time 1474499266 ps
CPU time 6.37 seconds
Started Apr 28 12:41:21 PM PDT 24
Finished Apr 28 12:41:30 PM PDT 24
Peak memory 211252 kb
Host smart-30a376f7-6629-4404-9118-79bb25a65227
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2625992792 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_max_throughput_chk.2625992792
Directory /workspace/46.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/46.rom_ctrl_smoke.1363761522
Short name T187
Test name
Test status
Simulation time 184254089 ps
CPU time 10.28 seconds
Started Apr 28 12:41:24 PM PDT 24
Finished Apr 28 12:41:37 PM PDT 24
Peak memory 219568 kb
Host smart-2bd92307-01e3-43de-9369-b7c7693b67e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1363761522 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_smoke.1363761522
Directory /workspace/46.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/46.rom_ctrl_stress_all.1438077250
Short name T290
Test name
Test status
Simulation time 335991889 ps
CPU time 13.67 seconds
Started Apr 28 12:41:41 PM PDT 24
Finished Apr 28 12:41:56 PM PDT 24
Peak memory 212440 kb
Host smart-a6c39272-e53c-4fe2-96ea-4c8ef7aab9d3
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1438077250 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 46.rom_ctrl_stress_all.1438077250
Directory /workspace/46.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/47.rom_ctrl_alert_test.2072167461
Short name T293
Test name
Test status
Simulation time 1718257153 ps
CPU time 9.63 seconds
Started Apr 28 12:41:43 PM PDT 24
Finished Apr 28 12:41:54 PM PDT 24
Peak memory 211376 kb
Host smart-45a7e145-10ee-46a8-be47-ad5ed8a76114
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2072167461 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_alert_test.2072167461
Directory /workspace/47.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/47.rom_ctrl_corrupt_sig_fatal_chk.262546442
Short name T253
Test name
Test status
Simulation time 220675080943 ps
CPU time 357.58 seconds
Started Apr 28 12:41:36 PM PDT 24
Finished Apr 28 12:47:35 PM PDT 24
Peak memory 228488 kb
Host smart-2bb144f1-cf93-4ba2-8b27-30a448873069
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=262546442 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_c
orrupt_sig_fatal_chk.262546442
Directory /workspace/47.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/47.rom_ctrl_kmac_err_chk.2619612821
Short name T289
Test name
Test status
Simulation time 4471224440 ps
CPU time 22.57 seconds
Started Apr 28 12:41:47 PM PDT 24
Finished Apr 28 12:42:11 PM PDT 24
Peak memory 212200 kb
Host smart-a5719fce-f555-47b5-bcbf-39e17ea2b8cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2619612821 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_kmac_err_chk.2619612821
Directory /workspace/47.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/47.rom_ctrl_max_throughput_chk.251186119
Short name T3
Test name
Test status
Simulation time 3787573781 ps
CPU time 11.4 seconds
Started Apr 28 12:41:34 PM PDT 24
Finished Apr 28 12:41:46 PM PDT 24
Peak memory 211348 kb
Host smart-a584d22c-d47b-4d5c-987c-b5385519f8ce
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=251186119 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_max_throughput_chk.251186119
Directory /workspace/47.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/47.rom_ctrl_smoke.4220017636
Short name T291
Test name
Test status
Simulation time 1466213360 ps
CPU time 14.91 seconds
Started Apr 28 12:41:44 PM PDT 24
Finished Apr 28 12:42:01 PM PDT 24
Peak memory 219548 kb
Host smart-6e2a4abf-1f2d-4727-9409-dc8abbe36d78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4220017636 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_smoke.4220017636
Directory /workspace/47.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/47.rom_ctrl_stress_all.500293120
Short name T301
Test name
Test status
Simulation time 10558635964 ps
CPU time 38.47 seconds
Started Apr 28 12:41:26 PM PDT 24
Finished Apr 28 12:42:07 PM PDT 24
Peak memory 219524 kb
Host smart-386abfa7-5d57-4ed3-bf6d-e9c4442cadcc
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=500293120 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 47.rom_ctrl_stress_all.500293120
Directory /workspace/47.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/47.rom_ctrl_stress_all_with_rand_reset.1765189992
Short name T362
Test name
Test status
Simulation time 102503600829 ps
CPU time 10314.5 seconds
Started Apr 28 12:41:26 PM PDT 24
Finished Apr 28 03:33:24 PM PDT 24
Peak memory 227884 kb
Host smart-2560173a-f0f5-4e10-be67-9ee88043300b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1765189992 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_stress_all_with_rand_reset.1765189992
Directory /workspace/47.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.rom_ctrl_alert_test.4021172414
Short name T226
Test name
Test status
Simulation time 1205658874 ps
CPU time 11.62 seconds
Started Apr 28 12:41:21 PM PDT 24
Finished Apr 28 12:41:35 PM PDT 24
Peak memory 211408 kb
Host smart-2e6c96a5-37ed-4d35-a4b0-61c37cfd0ef2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4021172414 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_alert_test.4021172414
Directory /workspace/48.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/48.rom_ctrl_corrupt_sig_fatal_chk.1879737535
Short name T47
Test name
Test status
Simulation time 167822705602 ps
CPU time 464.11 seconds
Started Apr 28 12:41:55 PM PDT 24
Finished Apr 28 12:49:41 PM PDT 24
Peak memory 238012 kb
Host smart-50e4bfbe-f077-4810-bf6c-ded27bc3aef0
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1879737535 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_
corrupt_sig_fatal_chk.1879737535
Directory /workspace/48.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/48.rom_ctrl_kmac_err_chk.237278548
Short name T96
Test name
Test status
Simulation time 71926576018 ps
CPU time 32.52 seconds
Started Apr 28 12:41:25 PM PDT 24
Finished Apr 28 12:42:00 PM PDT 24
Peak memory 212272 kb
Host smart-544d9d6a-dac0-46e8-9f06-f81957c77dc4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=237278548 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_kmac_err_chk.237278548
Directory /workspace/48.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/48.rom_ctrl_max_throughput_chk.3450527627
Short name T202
Test name
Test status
Simulation time 7568252269 ps
CPU time 17.6 seconds
Started Apr 28 12:41:28 PM PDT 24
Finished Apr 28 12:41:47 PM PDT 24
Peak memory 211432 kb
Host smart-3dff1ea2-50b3-4691-8e3d-1e827dd5b298
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3450527627 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_max_throughput_chk.3450527627
Directory /workspace/48.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/48.rom_ctrl_smoke.1198720277
Short name T232
Test name
Test status
Simulation time 184423134 ps
CPU time 9.7 seconds
Started Apr 28 12:41:22 PM PDT 24
Finished Apr 28 12:41:34 PM PDT 24
Peak memory 213056 kb
Host smart-738ff031-fd9c-48af-8580-151cc1a12704
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1198720277 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_smoke.1198720277
Directory /workspace/48.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/48.rom_ctrl_stress_all.2347308734
Short name T323
Test name
Test status
Simulation time 52143583152 ps
CPU time 79.21 seconds
Started Apr 28 12:41:50 PM PDT 24
Finished Apr 28 12:43:11 PM PDT 24
Peak memory 217288 kb
Host smart-d4852136-0829-4c9d-911f-a8d64f95dbf8
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2347308734 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 48.rom_ctrl_stress_all.2347308734
Directory /workspace/48.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/49.rom_ctrl_alert_test.1399068433
Short name T306
Test name
Test status
Simulation time 174860268 ps
CPU time 4.17 seconds
Started Apr 28 12:41:27 PM PDT 24
Finished Apr 28 12:41:33 PM PDT 24
Peak memory 211356 kb
Host smart-76dacf9a-bced-4015-863c-f925251f6cc4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1399068433 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_alert_test.1399068433
Directory /workspace/49.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/49.rom_ctrl_corrupt_sig_fatal_chk.2396849883
Short name T8
Test name
Test status
Simulation time 3850396660 ps
CPU time 117.91 seconds
Started Apr 28 12:41:32 PM PDT 24
Finished Apr 28 12:43:31 PM PDT 24
Peak memory 219768 kb
Host smart-edd6e6a6-7fe2-4b2f-bb51-3c7097bbae95
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2396849883 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_
corrupt_sig_fatal_chk.2396849883
Directory /workspace/49.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/49.rom_ctrl_kmac_err_chk.755706929
Short name T37
Test name
Test status
Simulation time 5741566915 ps
CPU time 26.33 seconds
Started Apr 28 12:41:24 PM PDT 24
Finished Apr 28 12:41:54 PM PDT 24
Peak memory 212484 kb
Host smart-d79a70ad-a329-4e29-9ec4-cb0844bae52f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=755706929 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_kmac_err_chk.755706929
Directory /workspace/49.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/49.rom_ctrl_max_throughput_chk.1567795298
Short name T361
Test name
Test status
Simulation time 2501179768 ps
CPU time 9.93 seconds
Started Apr 28 12:41:54 PM PDT 24
Finished Apr 28 12:42:06 PM PDT 24
Peak memory 211304 kb
Host smart-bf80ccda-b68e-4c31-911a-4f752a287929
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1567795298 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_max_throughput_chk.1567795298
Directory /workspace/49.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/49.rom_ctrl_smoke.3545709348
Short name T146
Test name
Test status
Simulation time 2625976571 ps
CPU time 21.25 seconds
Started Apr 28 12:41:24 PM PDT 24
Finished Apr 28 12:41:48 PM PDT 24
Peak memory 213508 kb
Host smart-9b64176b-bf77-4a73-9147-d8b292b85b42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3545709348 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_smoke.3545709348
Directory /workspace/49.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/49.rom_ctrl_stress_all.1942242431
Short name T205
Test name
Test status
Simulation time 45592459813 ps
CPU time 83.01 seconds
Started Apr 28 12:41:42 PM PDT 24
Finished Apr 28 12:43:07 PM PDT 24
Peak memory 219576 kb
Host smart-a479416a-8e36-4643-aba4-948d4142fc46
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1942242431 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 49.rom_ctrl_stress_all.1942242431
Directory /workspace/49.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/49.rom_ctrl_stress_all_with_rand_reset.372200715
Short name T50
Test name
Test status
Simulation time 865222033708 ps
CPU time 4456.72 seconds
Started Apr 28 12:41:38 PM PDT 24
Finished Apr 28 01:55:56 PM PDT 24
Peak memory 252388 kb
Host smart-ce3e3f62-6939-4370-870f-776cdac7abcb
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=372200715 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_stress_all_with_rand_reset.372200715
Directory /workspace/49.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.rom_ctrl_alert_test.3681263766
Short name T163
Test name
Test status
Simulation time 2008970454 ps
CPU time 16.35 seconds
Started Apr 28 12:41:00 PM PDT 24
Finished Apr 28 12:41:18 PM PDT 24
Peak memory 211404 kb
Host smart-68dbc78d-e994-4083-83b9-d441d6cffa94
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3681263766 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_alert_test.3681263766
Directory /workspace/5.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/5.rom_ctrl_corrupt_sig_fatal_chk.853511317
Short name T156
Test name
Test status
Simulation time 31834875806 ps
CPU time 412.21 seconds
Started Apr 28 12:40:56 PM PDT 24
Finished Apr 28 12:47:49 PM PDT 24
Peak memory 235064 kb
Host smart-dea9c6c9-581f-4e25-805b-952057925a39
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=853511317 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_co
rrupt_sig_fatal_chk.853511317
Directory /workspace/5.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/5.rom_ctrl_kmac_err_chk.2695750945
Short name T366
Test name
Test status
Simulation time 12033635270 ps
CPU time 28 seconds
Started Apr 28 12:41:06 PM PDT 24
Finished Apr 28 12:41:37 PM PDT 24
Peak memory 212368 kb
Host smart-58f1dbb8-362e-4b89-b842-6a523ca2cad0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2695750945 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_kmac_err_chk.2695750945
Directory /workspace/5.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/5.rom_ctrl_max_throughput_chk.2133072631
Short name T197
Test name
Test status
Simulation time 1343164820 ps
CPU time 12.62 seconds
Started Apr 28 12:40:45 PM PDT 24
Finished Apr 28 12:40:59 PM PDT 24
Peak memory 211264 kb
Host smart-af4f6c41-c178-4b01-8430-db64a9873ce0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2133072631 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_max_throughput_chk.2133072631
Directory /workspace/5.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/5.rom_ctrl_smoke.51032547
Short name T295
Test name
Test status
Simulation time 261412743 ps
CPU time 12.2 seconds
Started Apr 28 12:40:58 PM PDT 24
Finished Apr 28 12:41:12 PM PDT 24
Peak memory 213764 kb
Host smart-f7fe8214-e520-43b7-a459-a8760cada933
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=51032547 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_smoke.51032547
Directory /workspace/5.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/5.rom_ctrl_stress_all.4125428565
Short name T106
Test name
Test status
Simulation time 3169931951 ps
CPU time 18.31 seconds
Started Apr 28 12:41:14 PM PDT 24
Finished Apr 28 12:41:34 PM PDT 24
Peak memory 211348 kb
Host smart-7c37e1a2-d170-45f6-a336-2596b12e04e3
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4125428565 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 5.rom_ctrl_stress_all.4125428565
Directory /workspace/5.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/6.rom_ctrl_alert_test.1603344737
Short name T320
Test name
Test status
Simulation time 343666029 ps
CPU time 6.03 seconds
Started Apr 28 12:40:55 PM PDT 24
Finished Apr 28 12:41:02 PM PDT 24
Peak memory 211348 kb
Host smart-13fe3dc7-a775-4a91-a44d-f18f9238a7f3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1603344737 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_alert_test.1603344737
Directory /workspace/6.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/6.rom_ctrl_corrupt_sig_fatal_chk.1028453907
Short name T329
Test name
Test status
Simulation time 277203181879 ps
CPU time 239.5 seconds
Started Apr 28 12:41:10 PM PDT 24
Finished Apr 28 12:45:12 PM PDT 24
Peak memory 225068 kb
Host smart-bd42c449-5e5e-4fc6-9566-9348dc0ae468
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1028453907 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_c
orrupt_sig_fatal_chk.1028453907
Directory /workspace/6.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/6.rom_ctrl_kmac_err_chk.2171945981
Short name T276
Test name
Test status
Simulation time 11113502228 ps
CPU time 26.23 seconds
Started Apr 28 12:40:55 PM PDT 24
Finished Apr 28 12:41:22 PM PDT 24
Peak memory 212348 kb
Host smart-2414142e-0b30-4b72-a6b5-45796464c28c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2171945981 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_kmac_err_chk.2171945981
Directory /workspace/6.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/6.rom_ctrl_max_throughput_chk.1121962670
Short name T10
Test name
Test status
Simulation time 1027991186 ps
CPU time 7.41 seconds
Started Apr 28 12:40:47 PM PDT 24
Finished Apr 28 12:40:56 PM PDT 24
Peak memory 211308 kb
Host smart-6df1aabb-10f0-47a6-9b3b-ebefcc32ef20
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1121962670 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_max_throughput_chk.1121962670
Directory /workspace/6.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/6.rom_ctrl_smoke.930249522
Short name T337
Test name
Test status
Simulation time 10822936642 ps
CPU time 28.31 seconds
Started Apr 28 12:40:55 PM PDT 24
Finished Apr 28 12:41:24 PM PDT 24
Peak memory 219540 kb
Host smart-df15b65b-d918-429e-a379-c0c139e78a33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=930249522 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_smoke.930249522
Directory /workspace/6.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/6.rom_ctrl_stress_all.924375720
Short name T118
Test name
Test status
Simulation time 822389346 ps
CPU time 13.84 seconds
Started Apr 28 12:41:03 PM PDT 24
Finished Apr 28 12:41:19 PM PDT 24
Peak memory 219420 kb
Host smart-3fc71c7a-eaf0-4f79-9ecf-8d2cba58b928
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=924375720 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 6.rom_ctrl_stress_all.924375720
Directory /workspace/6.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/6.rom_ctrl_stress_all_with_rand_reset.352066531
Short name T53
Test name
Test status
Simulation time 114627081857 ps
CPU time 947.64 seconds
Started Apr 28 12:40:57 PM PDT 24
Finished Apr 28 12:56:47 PM PDT 24
Peak memory 230068 kb
Host smart-2f09d40a-08c7-433f-b34b-18525647995b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=352066531 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_stress_all_with_rand_reset.352066531
Directory /workspace/6.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.rom_ctrl_alert_test.24920793
Short name T43
Test name
Test status
Simulation time 6675192630 ps
CPU time 14.58 seconds
Started Apr 28 12:40:52 PM PDT 24
Finished Apr 28 12:41:08 PM PDT 24
Peak memory 211420 kb
Host smart-70ed82c7-6601-4366-a4be-77f6e2e6b188
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24920793 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_alert_test.24920793
Directory /workspace/7.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/7.rom_ctrl_corrupt_sig_fatal_chk.2817318105
Short name T149
Test name
Test status
Simulation time 9603409437 ps
CPU time 126.12 seconds
Started Apr 28 12:40:49 PM PDT 24
Finished Apr 28 12:42:56 PM PDT 24
Peak memory 225068 kb
Host smart-811db7e4-c646-4e34-b180-308fb5705451
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2817318105 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_c
orrupt_sig_fatal_chk.2817318105
Directory /workspace/7.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/7.rom_ctrl_kmac_err_chk.2436532634
Short name T314
Test name
Test status
Simulation time 4903712401 ps
CPU time 23.81 seconds
Started Apr 28 12:41:06 PM PDT 24
Finished Apr 28 12:41:31 PM PDT 24
Peak memory 213112 kb
Host smart-693ab7c5-42ab-4188-baee-ab580190fbf9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2436532634 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_kmac_err_chk.2436532634
Directory /workspace/7.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/7.rom_ctrl_max_throughput_chk.1032221404
Short name T343
Test name
Test status
Simulation time 1117801006 ps
CPU time 12.31 seconds
Started Apr 28 12:41:02 PM PDT 24
Finished Apr 28 12:41:16 PM PDT 24
Peak memory 211288 kb
Host smart-606cd4e4-1524-471d-ae71-de1963e1c54f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1032221404 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_max_throughput_chk.1032221404
Directory /workspace/7.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/7.rom_ctrl_smoke.774516410
Short name T264
Test name
Test status
Simulation time 363156820 ps
CPU time 9.79 seconds
Started Apr 28 12:40:54 PM PDT 24
Finished Apr 28 12:41:05 PM PDT 24
Peak memory 213788 kb
Host smart-0a3b1ee7-b24f-46c7-97a5-5b8fdf2bca01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=774516410 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_smoke.774516410
Directory /workspace/7.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/7.rom_ctrl_stress_all.3851502382
Short name T336
Test name
Test status
Simulation time 13001665163 ps
CPU time 43.69 seconds
Started Apr 28 12:40:55 PM PDT 24
Finished Apr 28 12:41:39 PM PDT 24
Peak memory 219496 kb
Host smart-1f04b546-cf63-4f35-80b7-a8cd72ba3e6d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3851502382 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 7.rom_ctrl_stress_all.3851502382
Directory /workspace/7.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/8.rom_ctrl_alert_test.2619189025
Short name T300
Test name
Test status
Simulation time 4953755063 ps
CPU time 10.95 seconds
Started Apr 28 12:40:52 PM PDT 24
Finished Apr 28 12:41:04 PM PDT 24
Peak memory 211340 kb
Host smart-4186f625-3716-467e-99d4-ffc76e5cbb7e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2619189025 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_alert_test.2619189025
Directory /workspace/8.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/8.rom_ctrl_corrupt_sig_fatal_chk.2289354421
Short name T29
Test name
Test status
Simulation time 9445742364 ps
CPU time 148.7 seconds
Started Apr 28 12:40:57 PM PDT 24
Finished Apr 28 12:43:28 PM PDT 24
Peak memory 220896 kb
Host smart-75a3938e-fcf4-43a5-83fc-1e4eceeea961
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2289354421 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_c
orrupt_sig_fatal_chk.2289354421
Directory /workspace/8.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/8.rom_ctrl_kmac_err_chk.40175844
Short name T307
Test name
Test status
Simulation time 2070801726 ps
CPU time 9.29 seconds
Started Apr 28 12:40:57 PM PDT 24
Finished Apr 28 12:41:08 PM PDT 24
Peak memory 211900 kb
Host smart-69554b31-575c-40c8-b7bf-2a0f7660c27f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=40175844 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_kmac_err_chk.40175844
Directory /workspace/8.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/8.rom_ctrl_max_throughput_chk.676263781
Short name T324
Test name
Test status
Simulation time 3763392179 ps
CPU time 11.34 seconds
Started Apr 28 12:41:08 PM PDT 24
Finished Apr 28 12:41:21 PM PDT 24
Peak memory 211340 kb
Host smart-a9ae4136-72e5-43cf-b882-e88df187f19a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=676263781 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_max_throughput_chk.676263781
Directory /workspace/8.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/8.rom_ctrl_smoke.1433774258
Short name T112
Test name
Test status
Simulation time 1824155686 ps
CPU time 23.91 seconds
Started Apr 28 12:40:52 PM PDT 24
Finished Apr 28 12:41:17 PM PDT 24
Peak memory 213420 kb
Host smart-49d12ffd-e07a-4b86-900a-3ab23c05ba8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1433774258 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_smoke.1433774258
Directory /workspace/8.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/8.rom_ctrl_stress_all.2477854075
Short name T182
Test name
Test status
Simulation time 7725098765 ps
CPU time 22.29 seconds
Started Apr 28 12:41:03 PM PDT 24
Finished Apr 28 12:41:27 PM PDT 24
Peak memory 212564 kb
Host smart-32ff5bfa-3395-41c7-a584-eac2f5a6cf00
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2477854075 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 8.rom_ctrl_stress_all.2477854075
Directory /workspace/8.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/9.rom_ctrl_alert_test.3907294872
Short name T215
Test name
Test status
Simulation time 1696717361 ps
CPU time 14.38 seconds
Started Apr 28 12:41:08 PM PDT 24
Finished Apr 28 12:41:24 PM PDT 24
Peak memory 211372 kb
Host smart-01336b51-829f-402a-a51f-e86fe90cf2d7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3907294872 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_alert_test.3907294872
Directory /workspace/9.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/9.rom_ctrl_corrupt_sig_fatal_chk.2021489667
Short name T46
Test name
Test status
Simulation time 115170665534 ps
CPU time 299.51 seconds
Started Apr 28 12:41:02 PM PDT 24
Finished Apr 28 12:46:04 PM PDT 24
Peak memory 233864 kb
Host smart-238fa0bc-62c6-473c-81a0-22f6a5f47dc1
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2021489667 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_c
orrupt_sig_fatal_chk.2021489667
Directory /workspace/9.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/9.rom_ctrl_kmac_err_chk.2130595881
Short name T15
Test name
Test status
Simulation time 179275105 ps
CPU time 9.58 seconds
Started Apr 28 12:41:03 PM PDT 24
Finished Apr 28 12:41:14 PM PDT 24
Peak memory 212052 kb
Host smart-bff4308d-ec1c-4201-85fe-de59a056b735
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2130595881 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_kmac_err_chk.2130595881
Directory /workspace/9.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/9.rom_ctrl_max_throughput_chk.4126126791
Short name T133
Test name
Test status
Simulation time 1598193455 ps
CPU time 13.68 seconds
Started Apr 28 12:40:59 PM PDT 24
Finished Apr 28 12:41:14 PM PDT 24
Peak memory 211284 kb
Host smart-90bdcc36-b386-4f56-b6f4-27f1f216f650
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4126126791 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_max_throughput_chk.4126126791
Directory /workspace/9.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/9.rom_ctrl_smoke.2314151756
Short name T222
Test name
Test status
Simulation time 11960789590 ps
CPU time 26.86 seconds
Started Apr 28 12:41:03 PM PDT 24
Finished Apr 28 12:41:32 PM PDT 24
Peak memory 219584 kb
Host smart-96b18041-1c20-4d60-97ad-13a34bfb9560
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2314151756 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_smoke.2314151756
Directory /workspace/9.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/9.rom_ctrl_stress_all.1541511981
Short name T76
Test name
Test status
Simulation time 22542472154 ps
CPU time 60.76 seconds
Started Apr 28 12:41:09 PM PDT 24
Finished Apr 28 12:42:12 PM PDT 24
Peak memory 219456 kb
Host smart-b3cd10a7-1aa1-42f0-99eb-ca37820b7163
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1541511981 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 9.rom_ctrl_stress_all.1541511981
Directory /workspace/9.rom_ctrl_stress_all/latest
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