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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
97.55 96.97 93.15 97.88 100.00 98.69 98.03 98.14


Total test records in report: 463
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html
T301 /workspace/coverage/default/42.rom_ctrl_stress_all.2066475444 Apr 30 12:43:48 PM PDT 24 Apr 30 12:44:30 PM PDT 24 4178460392 ps
T302 /workspace/coverage/default/27.rom_ctrl_corrupt_sig_fatal_chk.1841008478 Apr 30 12:43:24 PM PDT 24 Apr 30 12:49:02 PM PDT 24 32175911193 ps
T19 /workspace/coverage/default/31.rom_ctrl_stress_all_with_rand_reset.2875145516 Apr 30 12:43:24 PM PDT 24 Apr 30 01:41:03 PM PDT 24 88454105354 ps
T303 /workspace/coverage/default/9.rom_ctrl_max_throughput_chk.3047129647 Apr 30 12:42:33 PM PDT 24 Apr 30 12:42:48 PM PDT 24 1713387219 ps
T304 /workspace/coverage/default/8.rom_ctrl_smoke.2069150811 Apr 30 12:42:31 PM PDT 24 Apr 30 12:42:58 PM PDT 24 12605005567 ps
T305 /workspace/coverage/default/29.rom_ctrl_smoke.307316154 Apr 30 12:43:16 PM PDT 24 Apr 30 12:43:53 PM PDT 24 13617265570 ps
T306 /workspace/coverage/default/30.rom_ctrl_corrupt_sig_fatal_chk.3919780085 Apr 30 12:43:17 PM PDT 24 Apr 30 12:49:23 PM PDT 24 63213647343 ps
T307 /workspace/coverage/default/8.rom_ctrl_stress_all.3815361800 Apr 30 12:42:30 PM PDT 24 Apr 30 12:43:12 PM PDT 24 59915217195 ps
T56 /workspace/coverage/default/6.rom_ctrl_stress_all_with_rand_reset.2801068376 Apr 30 12:42:23 PM PDT 24 Apr 30 01:22:52 PM PDT 24 266298612207 ps
T308 /workspace/coverage/default/43.rom_ctrl_stress_all_with_rand_reset.1261024096 Apr 30 12:43:55 PM PDT 24 Apr 30 02:10:39 PM PDT 24 79119239686 ps
T309 /workspace/coverage/default/49.rom_ctrl_alert_test.2883943641 Apr 30 12:44:07 PM PDT 24 Apr 30 12:44:18 PM PDT 24 3934310098 ps
T310 /workspace/coverage/default/15.rom_ctrl_stress_all_with_rand_reset.493569811 Apr 30 12:42:50 PM PDT 24 Apr 30 01:23:01 PM PDT 24 29500507857 ps
T311 /workspace/coverage/default/47.rom_ctrl_smoke.2977067287 Apr 30 12:43:56 PM PDT 24 Apr 30 12:44:26 PM PDT 24 11539985295 ps
T312 /workspace/coverage/default/9.rom_ctrl_kmac_err_chk.2031135896 Apr 30 12:42:29 PM PDT 24 Apr 30 12:42:39 PM PDT 24 303814915 ps
T313 /workspace/coverage/default/29.rom_ctrl_corrupt_sig_fatal_chk.3270557587 Apr 30 12:43:15 PM PDT 24 Apr 30 12:44:58 PM PDT 24 5298229398 ps
T314 /workspace/coverage/default/23.rom_ctrl_alert_test.1122180585 Apr 30 12:43:09 PM PDT 24 Apr 30 12:43:19 PM PDT 24 854754388 ps
T315 /workspace/coverage/default/49.rom_ctrl_stress_all.1305196967 Apr 30 12:44:02 PM PDT 24 Apr 30 12:44:37 PM PDT 24 5054620976 ps
T316 /workspace/coverage/default/46.rom_ctrl_corrupt_sig_fatal_chk.462736240 Apr 30 12:43:54 PM PDT 24 Apr 30 12:49:52 PM PDT 24 82392041536 ps
T317 /workspace/coverage/default/31.rom_ctrl_kmac_err_chk.2590192859 Apr 30 12:43:24 PM PDT 24 Apr 30 12:43:46 PM PDT 24 1850346659 ps
T33 /workspace/coverage/default/0.rom_ctrl_sec_cm.3277003719 Apr 30 12:42:08 PM PDT 24 Apr 30 12:43:06 PM PDT 24 1799514844 ps
T318 /workspace/coverage/default/31.rom_ctrl_corrupt_sig_fatal_chk.2973458977 Apr 30 12:43:25 PM PDT 24 Apr 30 12:46:37 PM PDT 24 19030337405 ps
T319 /workspace/coverage/default/8.rom_ctrl_max_throughput_chk.307512424 Apr 30 12:42:30 PM PDT 24 Apr 30 12:42:45 PM PDT 24 5966710090 ps
T320 /workspace/coverage/default/14.rom_ctrl_stress_all.589240348 Apr 30 12:42:37 PM PDT 24 Apr 30 12:42:49 PM PDT 24 3160820151 ps
T321 /workspace/coverage/default/38.rom_ctrl_stress_all.3608615230 Apr 30 12:43:36 PM PDT 24 Apr 30 12:44:15 PM PDT 24 1746079330 ps
T322 /workspace/coverage/default/35.rom_ctrl_stress_all.1137888503 Apr 30 12:43:25 PM PDT 24 Apr 30 12:43:46 PM PDT 24 7729408811 ps
T35 /workspace/coverage/default/2.rom_ctrl_sec_cm.3783486407 Apr 30 12:42:15 PM PDT 24 Apr 30 12:44:02 PM PDT 24 1307316452 ps
T323 /workspace/coverage/default/4.rom_ctrl_kmac_err_chk.427418495 Apr 30 12:42:20 PM PDT 24 Apr 30 12:42:30 PM PDT 24 692878724 ps
T324 /workspace/coverage/default/45.rom_ctrl_stress_all.3714142910 Apr 30 12:43:55 PM PDT 24 Apr 30 12:44:58 PM PDT 24 6928489107 ps
T325 /workspace/coverage/default/18.rom_ctrl_corrupt_sig_fatal_chk.611220978 Apr 30 12:42:57 PM PDT 24 Apr 30 12:45:48 PM PDT 24 12132908172 ps
T326 /workspace/coverage/default/19.rom_ctrl_corrupt_sig_fatal_chk.2944320145 Apr 30 12:42:57 PM PDT 24 Apr 30 12:46:32 PM PDT 24 91524393896 ps
T327 /workspace/coverage/default/21.rom_ctrl_kmac_err_chk.3318573679 Apr 30 12:43:06 PM PDT 24 Apr 30 12:43:37 PM PDT 24 6817682791 ps
T328 /workspace/coverage/default/11.rom_ctrl_smoke.440577315 Apr 30 12:42:38 PM PDT 24 Apr 30 12:43:00 PM PDT 24 1609718456 ps
T329 /workspace/coverage/default/29.rom_ctrl_max_throughput_chk.819110246 Apr 30 12:43:16 PM PDT 24 Apr 30 12:43:22 PM PDT 24 96974730 ps
T330 /workspace/coverage/default/20.rom_ctrl_max_throughput_chk.3403504875 Apr 30 12:42:54 PM PDT 24 Apr 30 12:43:09 PM PDT 24 1718102077 ps
T331 /workspace/coverage/default/41.rom_ctrl_stress_all.1836261620 Apr 30 12:43:45 PM PDT 24 Apr 30 12:43:52 PM PDT 24 489392482 ps
T332 /workspace/coverage/default/1.rom_ctrl_corrupt_sig_fatal_chk.3898602129 Apr 30 12:42:21 PM PDT 24 Apr 30 12:46:18 PM PDT 24 24093096855 ps
T333 /workspace/coverage/default/34.rom_ctrl_stress_all_with_rand_reset.1209386054 Apr 30 12:43:30 PM PDT 24 Apr 30 01:18:53 PM PDT 24 247694021187 ps
T36 /workspace/coverage/default/4.rom_ctrl_sec_cm.3355403567 Apr 30 12:42:20 PM PDT 24 Apr 30 12:44:05 PM PDT 24 2155749049 ps
T334 /workspace/coverage/default/23.rom_ctrl_max_throughput_chk.3904286275 Apr 30 12:43:08 PM PDT 24 Apr 30 12:43:25 PM PDT 24 2469240288 ps
T335 /workspace/coverage/default/46.rom_ctrl_stress_all_with_rand_reset.1373490045 Apr 30 12:43:55 PM PDT 24 Apr 30 02:18:10 PM PDT 24 16926597016 ps
T336 /workspace/coverage/default/20.rom_ctrl_stress_all.4134978156 Apr 30 12:42:56 PM PDT 24 Apr 30 12:43:36 PM PDT 24 9134151623 ps
T337 /workspace/coverage/default/7.rom_ctrl_alert_test.1376852672 Apr 30 12:42:31 PM PDT 24 Apr 30 12:42:36 PM PDT 24 347651833 ps
T338 /workspace/coverage/default/26.rom_ctrl_kmac_err_chk.1120658541 Apr 30 12:43:15 PM PDT 24 Apr 30 12:43:28 PM PDT 24 334245393 ps
T339 /workspace/coverage/default/48.rom_ctrl_stress_all.1636934290 Apr 30 12:44:09 PM PDT 24 Apr 30 12:45:36 PM PDT 24 8046633663 ps
T340 /workspace/coverage/default/41.rom_ctrl_corrupt_sig_fatal_chk.166532418 Apr 30 12:43:47 PM PDT 24 Apr 30 12:45:55 PM PDT 24 21188909189 ps
T341 /workspace/coverage/default/19.rom_ctrl_kmac_err_chk.1325010704 Apr 30 12:42:54 PM PDT 24 Apr 30 12:43:19 PM PDT 24 49154408963 ps
T342 /workspace/coverage/default/34.rom_ctrl_max_throughput_chk.2021675898 Apr 30 12:43:25 PM PDT 24 Apr 30 12:43:33 PM PDT 24 189462644 ps
T343 /workspace/coverage/default/48.rom_ctrl_corrupt_sig_fatal_chk.3162231705 Apr 30 12:44:08 PM PDT 24 Apr 30 12:46:56 PM PDT 24 37093070282 ps
T344 /workspace/coverage/default/23.rom_ctrl_kmac_err_chk.256412 Apr 30 12:43:08 PM PDT 24 Apr 30 12:43:38 PM PDT 24 19489390618 ps
T345 /workspace/coverage/default/12.rom_ctrl_max_throughput_chk.1334932141 Apr 30 12:42:38 PM PDT 24 Apr 30 12:42:56 PM PDT 24 2102902435 ps
T346 /workspace/coverage/default/7.rom_ctrl_kmac_err_chk.2825117102 Apr 30 12:42:22 PM PDT 24 Apr 30 12:42:45 PM PDT 24 7883219740 ps
T347 /workspace/coverage/default/42.rom_ctrl_corrupt_sig_fatal_chk.209218698 Apr 30 12:43:47 PM PDT 24 Apr 30 12:47:10 PM PDT 24 316850392656 ps
T348 /workspace/coverage/default/18.rom_ctrl_smoke.779746161 Apr 30 12:42:50 PM PDT 24 Apr 30 12:43:07 PM PDT 24 4459323937 ps
T349 /workspace/coverage/default/12.rom_ctrl_corrupt_sig_fatal_chk.3441130360 Apr 30 12:42:38 PM PDT 24 Apr 30 12:44:21 PM PDT 24 3136423544 ps
T350 /workspace/coverage/default/21.rom_ctrl_max_throughput_chk.1063199881 Apr 30 12:42:53 PM PDT 24 Apr 30 12:43:08 PM PDT 24 8213214275 ps
T351 /workspace/coverage/default/35.rom_ctrl_corrupt_sig_fatal_chk.1366132592 Apr 30 12:43:36 PM PDT 24 Apr 30 12:45:09 PM PDT 24 5267641053 ps
T352 /workspace/coverage/default/12.rom_ctrl_stress_all.3969447704 Apr 30 12:42:38 PM PDT 24 Apr 30 12:42:52 PM PDT 24 245292140 ps
T353 /workspace/coverage/default/49.rom_ctrl_corrupt_sig_fatal_chk.1580305452 Apr 30 12:44:03 PM PDT 24 Apr 30 12:45:33 PM PDT 24 6692007321 ps
T354 /workspace/coverage/default/43.rom_ctrl_max_throughput_chk.3292995886 Apr 30 12:44:00 PM PDT 24 Apr 30 12:44:06 PM PDT 24 189966657 ps
T355 /workspace/coverage/default/4.rom_ctrl_alert_test.3648385039 Apr 30 12:42:21 PM PDT 24 Apr 30 12:42:28 PM PDT 24 743204017 ps
T356 /workspace/coverage/default/35.rom_ctrl_kmac_err_chk.1861845141 Apr 30 12:43:38 PM PDT 24 Apr 30 12:44:02 PM PDT 24 2398253206 ps
T357 /workspace/coverage/default/19.rom_ctrl_max_throughput_chk.2602748939 Apr 30 12:42:55 PM PDT 24 Apr 30 12:43:04 PM PDT 24 360982335 ps
T358 /workspace/coverage/default/15.rom_ctrl_smoke.1377322772 Apr 30 12:42:43 PM PDT 24 Apr 30 12:43:17 PM PDT 24 71035495000 ps
T359 /workspace/coverage/default/34.rom_ctrl_corrupt_sig_fatal_chk.2551044254 Apr 30 12:43:25 PM PDT 24 Apr 30 12:46:41 PM PDT 24 66565406721 ps
T360 /workspace/coverage/default/35.rom_ctrl_max_throughput_chk.2972691837 Apr 30 12:43:38 PM PDT 24 Apr 30 12:43:53 PM PDT 24 25499358131 ps
T361 /workspace/coverage/default/22.rom_ctrl_stress_all.3767426215 Apr 30 12:43:06 PM PDT 24 Apr 30 12:45:09 PM PDT 24 96227074776 ps
T362 /workspace/coverage/default/43.rom_ctrl_stress_all.4095953924 Apr 30 12:43:48 PM PDT 24 Apr 30 12:44:10 PM PDT 24 2127712556 ps
T363 /workspace/coverage/default/17.rom_ctrl_smoke.3993560662 Apr 30 12:42:47 PM PDT 24 Apr 30 12:42:58 PM PDT 24 428984381 ps
T57 /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_intg_err.1607828105 Apr 30 12:41:44 PM PDT 24 Apr 30 12:42:31 PM PDT 24 2069208085 ps
T60 /workspace/coverage/cover_reg_top/1.rom_ctrl_same_csr_outstanding.3972013000 Apr 30 12:41:22 PM PDT 24 Apr 30 12:41:36 PM PDT 24 1661363727 ps
T61 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_mem_rw_with_rand_reset.836572262 Apr 30 12:41:22 PM PDT 24 Apr 30 12:41:28 PM PDT 24 98723597 ps
T99 /workspace/coverage/cover_reg_top/8.rom_ctrl_same_csr_outstanding.4233502973 Apr 30 12:41:45 PM PDT 24 Apr 30 12:41:53 PM PDT 24 518819387 ps
T364 /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_mem_rw_with_rand_reset.84990752 Apr 30 12:41:48 PM PDT 24 Apr 30 12:42:02 PM PDT 24 1645061135 ps
T58 /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_intg_err.2875080805 Apr 30 12:41:26 PM PDT 24 Apr 30 12:42:38 PM PDT 24 10861433387 ps
T365 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_mem_rw_with_rand_reset.3229419425 Apr 30 12:41:22 PM PDT 24 Apr 30 12:41:27 PM PDT 24 633581722 ps
T366 /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_mem_rw_with_rand_reset.1089742481 Apr 30 12:42:02 PM PDT 24 Apr 30 12:42:17 PM PDT 24 1789990827 ps
T104 /workspace/coverage/cover_reg_top/16.rom_ctrl_passthru_mem_tl_intg_err.1132524742 Apr 30 12:42:04 PM PDT 24 Apr 30 12:42:32 PM PDT 24 1514690680 ps
T367 /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_errors.838568832 Apr 30 12:42:01 PM PDT 24 Apr 30 12:42:22 PM PDT 24 6447248304 ps
T100 /workspace/coverage/cover_reg_top/17.rom_ctrl_same_csr_outstanding.3220480450 Apr 30 12:42:15 PM PDT 24 Apr 30 12:42:22 PM PDT 24 763337781 ps
T368 /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_errors.1183295654 Apr 30 12:41:53 PM PDT 24 Apr 30 12:42:04 PM PDT 24 893706270 ps
T68 /workspace/coverage/cover_reg_top/1.rom_ctrl_passthru_mem_tl_intg_err.249106272 Apr 30 12:41:22 PM PDT 24 Apr 30 12:42:47 PM PDT 24 72189074830 ps
T69 /workspace/coverage/cover_reg_top/7.rom_ctrl_passthru_mem_tl_intg_err.2491849718 Apr 30 12:41:37 PM PDT 24 Apr 30 12:42:38 PM PDT 24 7554645316 ps
T369 /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_walk.4058764163 Apr 30 12:41:22 PM PDT 24 Apr 30 12:41:33 PM PDT 24 3649265172 ps
T101 /workspace/coverage/cover_reg_top/18.rom_ctrl_passthru_mem_tl_intg_err.3976605516 Apr 30 12:42:06 PM PDT 24 Apr 30 12:42:50 PM PDT 24 9834642023 ps
T70 /workspace/coverage/cover_reg_top/11.rom_ctrl_same_csr_outstanding.2836011863 Apr 30 12:41:53 PM PDT 24 Apr 30 12:42:12 PM PDT 24 28775355155 ps
T71 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_aliasing.792724294 Apr 30 12:41:32 PM PDT 24 Apr 30 12:41:37 PM PDT 24 89979666 ps
T72 /workspace/coverage/cover_reg_top/3.rom_ctrl_passthru_mem_tl_intg_err.3650981975 Apr 30 12:41:36 PM PDT 24 Apr 30 12:42:05 PM PDT 24 2261351624 ps
T370 /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_errors.348614426 Apr 30 12:41:29 PM PDT 24 Apr 30 12:41:38 PM PDT 24 200628101 ps
T102 /workspace/coverage/cover_reg_top/17.rom_ctrl_passthru_mem_tl_intg_err.3236302840 Apr 30 12:42:00 PM PDT 24 Apr 30 12:42:57 PM PDT 24 25601200403 ps
T59 /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_intg_err.899263268 Apr 30 12:41:50 PM PDT 24 Apr 30 12:42:58 PM PDT 24 664652852 ps
T371 /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_errors.3347819216 Apr 30 12:41:51 PM PDT 24 Apr 30 12:42:03 PM PDT 24 4858396342 ps
T73 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_hw_reset.4161631823 Apr 30 12:41:30 PM PDT 24 Apr 30 12:41:41 PM PDT 24 2322593006 ps
T372 /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_mem_rw_with_rand_reset.2395939460 Apr 30 12:42:06 PM PDT 24 Apr 30 12:42:23 PM PDT 24 11935111157 ps
T373 /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_walk.522182919 Apr 30 12:41:32 PM PDT 24 Apr 30 12:41:44 PM PDT 24 1373547757 ps
T74 /workspace/coverage/cover_reg_top/10.rom_ctrl_same_csr_outstanding.3547547754 Apr 30 12:41:54 PM PDT 24 Apr 30 12:42:03 PM PDT 24 2652658349 ps
T75 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_aliasing.284745396 Apr 30 12:41:37 PM PDT 24 Apr 30 12:41:42 PM PDT 24 91022412 ps
T111 /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_intg_err.211204087 Apr 30 12:41:45 PM PDT 24 Apr 30 12:42:53 PM PDT 24 670546413 ps
T374 /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_mem_rw_with_rand_reset.4026371603 Apr 30 12:42:00 PM PDT 24 Apr 30 12:42:06 PM PDT 24 238752242 ps
T375 /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_mem_rw_with_rand_reset.1649748772 Apr 30 12:42:08 PM PDT 24 Apr 30 12:42:25 PM PDT 24 8239203881 ps
T76 /workspace/coverage/cover_reg_top/9.rom_ctrl_passthru_mem_tl_intg_err.1723635108 Apr 30 12:41:49 PM PDT 24 Apr 30 12:42:34 PM PDT 24 2761211916 ps
T376 /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_rw.2595418463 Apr 30 12:42:02 PM PDT 24 Apr 30 12:42:17 PM PDT 24 12405803915 ps
T77 /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_rw.294386724 Apr 30 12:41:44 PM PDT 24 Apr 30 12:41:55 PM PDT 24 1037468957 ps
T377 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_rw.1198431783 Apr 30 12:41:32 PM PDT 24 Apr 30 12:41:42 PM PDT 24 2816566946 ps
T378 /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_mem_rw_with_rand_reset.778228094 Apr 30 12:41:37 PM PDT 24 Apr 30 12:41:54 PM PDT 24 7926889791 ps
T379 /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_errors.4053891233 Apr 30 12:42:03 PM PDT 24 Apr 30 12:42:18 PM PDT 24 5917490022 ps
T380 /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_errors.1181663904 Apr 30 12:41:52 PM PDT 24 Apr 30 12:42:11 PM PDT 24 2989334598 ps
T381 /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_rw.3684646025 Apr 30 12:41:46 PM PDT 24 Apr 30 12:42:01 PM PDT 24 6968129873 ps
T83 /workspace/coverage/cover_reg_top/19.rom_ctrl_passthru_mem_tl_intg_err.3760954874 Apr 30 12:42:06 PM PDT 24 Apr 30 12:43:40 PM PDT 24 45436085142 ps
T382 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_bit_bash.1152026877 Apr 30 12:41:29 PM PDT 24 Apr 30 12:41:40 PM PDT 24 1107759959 ps
T383 /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_walk.3193785800 Apr 30 12:41:29 PM PDT 24 Apr 30 12:41:43 PM PDT 24 1969379660 ps
T384 /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_errors.4213036431 Apr 30 12:42:03 PM PDT 24 Apr 30 12:42:16 PM PDT 24 2380372688 ps
T385 /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_partial_access.1208673701 Apr 30 12:41:22 PM PDT 24 Apr 30 12:41:27 PM PDT 24 168552403 ps
T386 /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_errors.3923141334 Apr 30 12:41:22 PM PDT 24 Apr 30 12:41:40 PM PDT 24 7436025914 ps
T103 /workspace/coverage/cover_reg_top/2.rom_ctrl_same_csr_outstanding.3549505705 Apr 30 12:41:29 PM PDT 24 Apr 30 12:41:40 PM PDT 24 5129829037 ps
T387 /workspace/coverage/cover_reg_top/11.rom_ctrl_passthru_mem_tl_intg_err.29367506 Apr 30 12:41:53 PM PDT 24 Apr 30 12:42:12 PM PDT 24 475655485 ps
T84 /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_rw.1742045098 Apr 30 12:41:59 PM PDT 24 Apr 30 12:42:14 PM PDT 24 7310614319 ps
T388 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_bit_bash.3641549101 Apr 30 12:41:23 PM PDT 24 Apr 30 12:41:36 PM PDT 24 6131997902 ps
T389 /workspace/coverage/cover_reg_top/5.rom_ctrl_same_csr_outstanding.3099497703 Apr 30 12:41:37 PM PDT 24 Apr 30 12:41:53 PM PDT 24 1853859389 ps
T390 /workspace/coverage/cover_reg_top/14.rom_ctrl_passthru_mem_tl_intg_err.3441529030 Apr 30 12:42:01 PM PDT 24 Apr 30 12:42:30 PM PDT 24 1104053425 ps
T391 /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_mem_rw_with_rand_reset.2303034762 Apr 30 12:41:52 PM PDT 24 Apr 30 12:41:58 PM PDT 24 356295540 ps
T116 /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_intg_err.568308414 Apr 30 12:42:00 PM PDT 24 Apr 30 12:43:14 PM PDT 24 1608268307 ps
T392 /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_rw.4187205098 Apr 30 12:41:59 PM PDT 24 Apr 30 12:42:15 PM PDT 24 7765361636 ps
T393 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_mem_rw_with_rand_reset.2746367042 Apr 30 12:41:32 PM PDT 24 Apr 30 12:41:46 PM PDT 24 2006974501 ps
T394 /workspace/coverage/cover_reg_top/8.rom_ctrl_passthru_mem_tl_intg_err.2706787448 Apr 30 12:41:45 PM PDT 24 Apr 30 12:42:41 PM PDT 24 29045977833 ps
T395 /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_walk.1850280485 Apr 30 12:41:36 PM PDT 24 Apr 30 12:41:50 PM PDT 24 21120277001 ps
T119 /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_intg_err.878134676 Apr 30 12:41:54 PM PDT 24 Apr 30 12:42:34 PM PDT 24 2448587822 ps
T396 /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_mem_rw_with_rand_reset.3866023668 Apr 30 12:41:55 PM PDT 24 Apr 30 12:42:00 PM PDT 24 104539218 ps
T85 /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_rw.3114464753 Apr 30 12:41:53 PM PDT 24 Apr 30 12:42:10 PM PDT 24 4530979000 ps
T397 /workspace/coverage/cover_reg_top/9.rom_ctrl_same_csr_outstanding.1082818693 Apr 30 12:41:47 PM PDT 24 Apr 30 12:41:59 PM PDT 24 2505204979 ps
T86 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_aliasing.3303321998 Apr 30 12:41:23 PM PDT 24 Apr 30 12:41:38 PM PDT 24 1682565770 ps
T398 /workspace/coverage/cover_reg_top/4.rom_ctrl_passthru_mem_tl_intg_err.1226291442 Apr 30 12:41:30 PM PDT 24 Apr 30 12:42:39 PM PDT 24 44796914947 ps
T399 /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_partial_access.3907945415 Apr 30 12:41:22 PM PDT 24 Apr 30 12:41:32 PM PDT 24 900375927 ps
T120 /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_intg_err.3736976604 Apr 30 12:41:16 PM PDT 24 Apr 30 12:41:57 PM PDT 24 12603572754 ps
T400 /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_errors.2090895715 Apr 30 12:41:49 PM PDT 24 Apr 30 12:42:08 PM PDT 24 2157850834 ps
T118 /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_intg_err.565140910 Apr 30 12:41:36 PM PDT 24 Apr 30 12:42:23 PM PDT 24 4325765114 ps
T401 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_hw_reset.2877224497 Apr 30 12:41:24 PM PDT 24 Apr 30 12:41:43 PM PDT 24 7923042381 ps
T402 /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_mem_rw_with_rand_reset.1520147225 Apr 30 12:42:00 PM PDT 24 Apr 30 12:42:12 PM PDT 24 4953390339 ps
T117 /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_intg_err.3973416435 Apr 30 12:41:37 PM PDT 24 Apr 30 12:42:47 PM PDT 24 384152292 ps
T403 /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_walk.1223738841 Apr 30 12:41:21 PM PDT 24 Apr 30 12:41:32 PM PDT 24 3564298250 ps
T404 /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_rw.996581939 Apr 30 12:41:44 PM PDT 24 Apr 30 12:41:54 PM PDT 24 789465403 ps
T121 /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_intg_err.644596029 Apr 30 12:41:21 PM PDT 24 Apr 30 12:42:08 PM PDT 24 2665983215 ps
T405 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_bit_bash.1606604520 Apr 30 12:41:22 PM PDT 24 Apr 30 12:41:34 PM PDT 24 6183537743 ps
T406 /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_errors.1352620285 Apr 30 12:41:54 PM PDT 24 Apr 30 12:42:05 PM PDT 24 651033603 ps
T407 /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_intg_err.3650541566 Apr 30 12:41:53 PM PDT 24 Apr 30 12:43:09 PM PDT 24 1377202098 ps
T87 /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_rw.1435201306 Apr 30 12:41:42 PM PDT 24 Apr 30 12:41:59 PM PDT 24 2833008660 ps
T92 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_rw.4226940339 Apr 30 12:41:33 PM PDT 24 Apr 30 12:41:41 PM PDT 24 2377723362 ps
T93 /workspace/coverage/cover_reg_top/13.rom_ctrl_passthru_mem_tl_intg_err.843246335 Apr 30 12:41:53 PM PDT 24 Apr 30 12:42:17 PM PDT 24 728032137 ps
T408 /workspace/coverage/cover_reg_top/15.rom_ctrl_same_csr_outstanding.1398924056 Apr 30 12:42:02 PM PDT 24 Apr 30 12:42:09 PM PDT 24 1365467439 ps
T409 /workspace/coverage/cover_reg_top/16.rom_ctrl_same_csr_outstanding.790025792 Apr 30 12:42:01 PM PDT 24 Apr 30 12:42:12 PM PDT 24 4086450079 ps
T410 /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_errors.3083923 Apr 30 12:42:06 PM PDT 24 Apr 30 12:42:26 PM PDT 24 7422753798 ps
T88 /workspace/coverage/cover_reg_top/2.rom_ctrl_passthru_mem_tl_intg_err.3575208751 Apr 30 12:41:23 PM PDT 24 Apr 30 12:42:15 PM PDT 24 43193004756 ps
T89 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_aliasing.2745742097 Apr 30 12:41:22 PM PDT 24 Apr 30 12:41:27 PM PDT 24 378193745 ps
T112 /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_intg_err.3213425324 Apr 30 12:42:06 PM PDT 24 Apr 30 12:42:47 PM PDT 24 587320195 ps
T411 /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_mem_rw_with_rand_reset.1065559527 Apr 30 12:41:54 PM PDT 24 Apr 30 12:42:06 PM PDT 24 6487523363 ps
T412 /workspace/coverage/cover_reg_top/4.rom_ctrl_same_csr_outstanding.2517501145 Apr 30 12:41:41 PM PDT 24 Apr 30 12:41:59 PM PDT 24 8474838750 ps
T90 /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_rw.3882852196 Apr 30 12:42:07 PM PDT 24 Apr 30 12:42:23 PM PDT 24 1852904374 ps
T413 /workspace/coverage/cover_reg_top/6.rom_ctrl_passthru_mem_tl_intg_err.1376820403 Apr 30 12:41:41 PM PDT 24 Apr 30 12:42:17 PM PDT 24 29477867560 ps
T414 /workspace/coverage/cover_reg_top/3.rom_ctrl_same_csr_outstanding.1728467438 Apr 30 12:41:30 PM PDT 24 Apr 30 12:41:43 PM PDT 24 2980437264 ps
T415 /workspace/coverage/cover_reg_top/7.rom_ctrl_same_csr_outstanding.3495257805 Apr 30 12:41:45 PM PDT 24 Apr 30 12:42:00 PM PDT 24 2867977731 ps
T416 /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_rw.84672987 Apr 30 12:41:51 PM PDT 24 Apr 30 12:42:07 PM PDT 24 2028620584 ps
T417 /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_errors.1069226437 Apr 30 12:41:39 PM PDT 24 Apr 30 12:41:57 PM PDT 24 1386586286 ps
T418 /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_partial_access.558250733 Apr 30 12:41:36 PM PDT 24 Apr 30 12:41:51 PM PDT 24 1941359745 ps
T419 /workspace/coverage/cover_reg_top/18.rom_ctrl_same_csr_outstanding.3948750641 Apr 30 12:42:13 PM PDT 24 Apr 30 12:42:29 PM PDT 24 6960445065 ps
T420 /workspace/coverage/cover_reg_top/0.rom_ctrl_same_csr_outstanding.3781830861 Apr 30 12:41:22 PM PDT 24 Apr 30 12:41:37 PM PDT 24 2940878171 ps
T421 /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_partial_access.3609592994 Apr 30 12:41:30 PM PDT 24 Apr 30 12:41:44 PM PDT 24 3333116217 ps
T422 /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_errors.889055743 Apr 30 12:41:22 PM PDT 24 Apr 30 12:41:29 PM PDT 24 333201145 ps
T423 /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_intg_err.228564515 Apr 30 12:42:00 PM PDT 24 Apr 30 12:43:09 PM PDT 24 954489354 ps
T424 /workspace/coverage/cover_reg_top/14.rom_ctrl_same_csr_outstanding.292908993 Apr 30 12:42:01 PM PDT 24 Apr 30 12:42:13 PM PDT 24 1653183827 ps
T425 /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_intg_err.3417955892 Apr 30 12:41:59 PM PDT 24 Apr 30 12:42:39 PM PDT 24 3124154300 ps
T115 /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_intg_err.1834302056 Apr 30 12:41:59 PM PDT 24 Apr 30 12:43:07 PM PDT 24 512483372 ps
T426 /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_errors.1150515664 Apr 30 12:42:00 PM PDT 24 Apr 30 12:42:19 PM PDT 24 24028740545 ps
T427 /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_errors.4051077000 Apr 30 12:41:45 PM PDT 24 Apr 30 12:42:00 PM PDT 24 16344538763 ps
T91 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_hw_reset.3320656828 Apr 30 12:41:30 PM PDT 24 Apr 30 12:41:40 PM PDT 24 429217133 ps
T428 /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_rw.1660420803 Apr 30 12:42:02 PM PDT 24 Apr 30 12:42:09 PM PDT 24 346168400 ps
T429 /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_mem_rw_with_rand_reset.3514043169 Apr 30 12:41:44 PM PDT 24 Apr 30 12:41:51 PM PDT 24 302728453 ps
T94 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_rw.4108010307 Apr 30 12:41:30 PM PDT 24 Apr 30 12:41:42 PM PDT 24 3940103362 ps
T430 /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_partial_access.3388818404 Apr 30 12:41:31 PM PDT 24 Apr 30 12:41:46 PM PDT 24 7360117643 ps
T431 /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_rw.966307519 Apr 30 12:41:38 PM PDT 24 Apr 30 12:41:43 PM PDT 24 125959084 ps
T432 /workspace/coverage/cover_reg_top/6.rom_ctrl_same_csr_outstanding.328005187 Apr 30 12:41:39 PM PDT 24 Apr 30 12:41:50 PM PDT 24 1042697050 ps
T433 /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_errors.3644925413 Apr 30 12:41:40 PM PDT 24 Apr 30 12:41:49 PM PDT 24 254630064 ps
T434 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_mem_rw_with_rand_reset.1444557930 Apr 30 12:41:36 PM PDT 24 Apr 30 12:41:49 PM PDT 24 1177831456 ps
T435 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_rw.39975774 Apr 30 12:41:22 PM PDT 24 Apr 30 12:41:39 PM PDT 24 8901611542 ps
T436 /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_mem_rw_with_rand_reset.2381360444 Apr 30 12:42:06 PM PDT 24 Apr 30 12:42:19 PM PDT 24 2624766184 ps
T437 /workspace/coverage/cover_reg_top/12.rom_ctrl_same_csr_outstanding.3603042407 Apr 30 12:41:51 PM PDT 24 Apr 30 12:42:05 PM PDT 24 1593227452 ps
T438 /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_mem_rw_with_rand_reset.923166419 Apr 30 12:41:46 PM PDT 24 Apr 30 12:42:02 PM PDT 24 1987210460 ps
T439 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_hw_reset.3122764840 Apr 30 12:41:29 PM PDT 24 Apr 30 12:41:44 PM PDT 24 2162812435 ps
T95 /workspace/coverage/cover_reg_top/12.rom_ctrl_passthru_mem_tl_intg_err.1636450919 Apr 30 12:41:54 PM PDT 24 Apr 30 12:43:02 PM PDT 24 7172119144 ps
T440 /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_mem_rw_with_rand_reset.1343674099 Apr 30 12:41:37 PM PDT 24 Apr 30 12:41:49 PM PDT 24 1224980488 ps
T441 /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_errors.1059921297 Apr 30 12:41:37 PM PDT 24 Apr 30 12:41:57 PM PDT 24 8122066125 ps
T442 /workspace/coverage/cover_reg_top/10.rom_ctrl_passthru_mem_tl_intg_err.1854244974 Apr 30 12:41:49 PM PDT 24 Apr 30 12:42:39 PM PDT 24 3494232727 ps
T443 /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_rw.4241779306 Apr 30 12:42:02 PM PDT 24 Apr 30 12:42:12 PM PDT 24 917337233 ps
T444 /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_errors.4179837118 Apr 30 12:41:17 PM PDT 24 Apr 30 12:41:26 PM PDT 24 493141008 ps
T445 /workspace/coverage/cover_reg_top/19.rom_ctrl_same_csr_outstanding.3312415821 Apr 30 12:42:06 PM PDT 24 Apr 30 12:42:18 PM PDT 24 1815081112 ps
T113 /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_intg_err.2846906295 Apr 30 12:41:38 PM PDT 24 Apr 30 12:42:57 PM PDT 24 660892435 ps
T114 /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_intg_err.2949476899 Apr 30 12:41:37 PM PDT 24 Apr 30 12:42:46 PM PDT 24 489988207 ps
T446 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_mem_rw_with_rand_reset.3877753384 Apr 30 12:41:38 PM PDT 24 Apr 30 12:41:54 PM PDT 24 3908512134 ps
T447 /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_mem_rw_with_rand_reset.2359095332 Apr 30 12:42:03 PM PDT 24 Apr 30 12:42:15 PM PDT 24 2955729847 ps
T448 /workspace/coverage/cover_reg_top/0.rom_ctrl_passthru_mem_tl_intg_err.3569835339 Apr 30 12:41:17 PM PDT 24 Apr 30 12:42:11 PM PDT 24 31942562623 ps
T449 /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_intg_err.2549128200 Apr 30 12:42:07 PM PDT 24 Apr 30 12:42:45 PM PDT 24 764390416 ps
T450 /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_rw.51702990 Apr 30 12:42:08 PM PDT 24 Apr 30 12:42:17 PM PDT 24 1899387282 ps
T451 /workspace/coverage/cover_reg_top/5.rom_ctrl_passthru_mem_tl_intg_err.3078441221 Apr 30 12:41:38 PM PDT 24 Apr 30 12:42:34 PM PDT 24 28607815427 ps
T452 /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_errors.296773030 Apr 30 12:41:31 PM PDT 24 Apr 30 12:41:42 PM PDT 24 795816658 ps
T453 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_aliasing.1729559607 Apr 30 12:41:36 PM PDT 24 Apr 30 12:41:53 PM PDT 24 4378222669 ps
T454 /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_rw.2411799206 Apr 30 12:41:54 PM PDT 24 Apr 30 12:42:05 PM PDT 24 884774672 ps
T455 /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_intg_err.4027686342 Apr 30 12:41:30 PM PDT 24 Apr 30 12:42:07 PM PDT 24 730268892 ps
T456 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_bit_bash.2326861575 Apr 30 12:41:34 PM PDT 24 Apr 30 12:41:51 PM PDT 24 7875377075 ps
T457 /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_errors.3959454042 Apr 30 12:42:07 PM PDT 24 Apr 30 12:42:20 PM PDT 24 653425703 ps
T458 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_rw.1749464682 Apr 30 12:41:23 PM PDT 24 Apr 30 12:41:27 PM PDT 24 333213001 ps
T459 /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_intg_err.521418086 Apr 30 12:42:10 PM PDT 24 Apr 30 12:43:21 PM PDT 24 897816008 ps
T460 /workspace/coverage/cover_reg_top/13.rom_ctrl_same_csr_outstanding.3009779800 Apr 30 12:42:01 PM PDT 24 Apr 30 12:42:17 PM PDT 24 1758382079 ps
T461 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_bit_bash.3002216090 Apr 30 12:41:31 PM PDT 24 Apr 30 12:41:41 PM PDT 24 3932573390 ps
T462 /workspace/coverage/cover_reg_top/15.rom_ctrl_passthru_mem_tl_intg_err.993337763 Apr 30 12:42:04 PM PDT 24 Apr 30 12:42:45 PM PDT 24 3952160962 ps
T463 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_hw_reset.1773582643 Apr 30 12:41:22 PM PDT 24 Apr 30 12:41:39 PM PDT 24 1935556123 ps

Test location /workspace/coverage/default/16.rom_ctrl_stress_all_with_rand_reset.2452709077
Short name T1
Test name
Test status
Simulation time 58901014701 ps
CPU time 405.82 seconds
Started Apr 30 12:42:48 PM PDT 24
Finished Apr 30 12:49:34 PM PDT 24
Peak memory 227980 kb
Host smart-66398d5f-8588-470f-8715-31d1327d9d9b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2452709077 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_stress_all_with_rand_reset.2452709077
Directory /workspace/16.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.rom_ctrl_corrupt_sig_fatal_chk.494360177
Short name T8
Test name
Test status
Simulation time 5996430724 ps
CPU time 118.7 seconds
Started Apr 30 12:42:22 PM PDT 24
Finished Apr 30 12:44:22 PM PDT 24
Peak memory 237452 kb
Host smart-23d9fd60-59d6-414f-a467-2893c2d39f68
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=494360177 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_co
rrupt_sig_fatal_chk.494360177
Directory /workspace/6.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/17.rom_ctrl_corrupt_sig_fatal_chk.3215979960
Short name T25
Test name
Test status
Simulation time 66678494075 ps
CPU time 327.69 seconds
Started Apr 30 12:42:50 PM PDT 24
Finished Apr 30 12:48:18 PM PDT 24
Peak memory 228744 kb
Host smart-60da5586-398d-4b8f-9df4-5408a06d33c8
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3215979960 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_
corrupt_sig_fatal_chk.3215979960
Directory /workspace/17.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_intg_err.211204087
Short name T111
Test name
Test status
Simulation time 670546413 ps
CPU time 67.41 seconds
Started Apr 30 12:41:45 PM PDT 24
Finished Apr 30 12:42:53 PM PDT 24
Peak memory 210560 kb
Host smart-9781447a-752d-430b-96d2-5e4435589dd9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=211204087 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_tl_int
g_err.211204087
Directory /workspace/8.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/24.rom_ctrl_smoke.1407207605
Short name T2
Test name
Test status
Simulation time 15733899813 ps
CPU time 41.68 seconds
Started Apr 30 12:43:07 PM PDT 24
Finished Apr 30 12:43:49 PM PDT 24
Peak memory 213812 kb
Host smart-d2dcc5fb-57ee-4824-a3d5-c917ccb046df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1407207605 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_smoke.1407207605
Directory /workspace/24.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/1.rom_ctrl_sec_cm.747102177
Short name T31
Test name
Test status
Simulation time 1295422100 ps
CPU time 101.28 seconds
Started Apr 30 12:42:13 PM PDT 24
Finished Apr 30 12:43:55 PM PDT 24
Peak memory 230960 kb
Host smart-4aaebcc8-edf6-48db-9aa3-5b6ae653c01c
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=747102177 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_sec_cm.747102177
Directory /workspace/1.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_passthru_mem_tl_intg_err.249106272
Short name T68
Test name
Test status
Simulation time 72189074830 ps
CPU time 84.36 seconds
Started Apr 30 12:41:22 PM PDT 24
Finished Apr 30 12:42:47 PM PDT 24
Peak memory 210628 kb
Host smart-132d6281-abf8-41c5-96f1-2e12024760fe
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=249106272 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_pas
sthru_mem_tl_intg_err.249106272
Directory /workspace/1.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_intg_err.1834302056
Short name T115
Test name
Test status
Simulation time 512483372 ps
CPU time 67.65 seconds
Started Apr 30 12:41:59 PM PDT 24
Finished Apr 30 12:43:07 PM PDT 24
Peak memory 211300 kb
Host smart-62fff9b6-07b2-4bf5-b4c4-c2733b56fdb9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1834302056 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_tl_i
ntg_err.1834302056
Directory /workspace/13.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/21.rom_ctrl_corrupt_sig_fatal_chk.3714047943
Short name T122
Test name
Test status
Simulation time 91640414007 ps
CPU time 207.4 seconds
Started Apr 30 12:43:01 PM PDT 24
Finished Apr 30 12:46:28 PM PDT 24
Peak memory 236240 kb
Host smart-5f243eea-64cd-44f3-8d8b-b9e2ce4f5150
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3714047943 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_
corrupt_sig_fatal_chk.3714047943
Directory /workspace/21.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/20.rom_ctrl_alert_test.2042573482
Short name T20
Test name
Test status
Simulation time 2685953815 ps
CPU time 8.87 seconds
Started Apr 30 12:42:54 PM PDT 24
Finished Apr 30 12:43:04 PM PDT 24
Peak memory 211532 kb
Host smart-2a16ac44-b9ec-421d-9e1d-77ac59f92059
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2042573482 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_alert_test.2042573482
Directory /workspace/20.rom_ctrl_alert_test/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_intg_err.1607828105
Short name T57
Test name
Test status
Simulation time 2069208085 ps
CPU time 46.59 seconds
Started Apr 30 12:41:44 PM PDT 24
Finished Apr 30 12:42:31 PM PDT 24
Peak memory 211204 kb
Host smart-31f05f1a-bc92-4840-8143-38ae183dfa3b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1607828105 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_tl_in
tg_err.1607828105
Directory /workspace/9.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/1.rom_ctrl_kmac_err_chk.1805599282
Short name T27
Test name
Test status
Simulation time 44530164147 ps
CPU time 32.96 seconds
Started Apr 30 12:42:13 PM PDT 24
Finished Apr 30 12:42:47 PM PDT 24
Peak memory 212468 kb
Host smart-91fb1dbe-46de-49fc-9c64-dc5df0ad3f71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1805599282 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_kmac_err_chk.1805599282
Directory /workspace/1.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/10.rom_ctrl_kmac_err_chk.2111709367
Short name T22
Test name
Test status
Simulation time 175497981 ps
CPU time 9.3 seconds
Started Apr 30 12:42:28 PM PDT 24
Finished Apr 30 12:42:37 PM PDT 24
Peak memory 211948 kb
Host smart-5f80eddb-6c74-4c04-8421-7ba703315ee3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2111709367 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_kmac_err_chk.2111709367
Directory /workspace/10.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/13.rom_ctrl_kmac_err_chk.148960917
Short name T26
Test name
Test status
Simulation time 2762500049 ps
CPU time 22.22 seconds
Started Apr 30 12:42:38 PM PDT 24
Finished Apr 30 12:43:01 PM PDT 24
Peak memory 212336 kb
Host smart-d830fa06-1121-4161-a181-394c68308482
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=148960917 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_kmac_err_chk.148960917
Directory /workspace/13.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_passthru_mem_tl_intg_err.3760954874
Short name T83
Test name
Test status
Simulation time 45436085142 ps
CPU time 92.13 seconds
Started Apr 30 12:42:06 PM PDT 24
Finished Apr 30 12:43:40 PM PDT 24
Peak memory 210552 kb
Host smart-5df6f301-16aa-410f-add3-b367bc62c360
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3760954874 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_p
assthru_mem_tl_intg_err.3760954874
Directory /workspace/19.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/default/21.rom_ctrl_stress_all_with_rand_reset.3224184364
Short name T53
Test name
Test status
Simulation time 46149744558 ps
CPU time 6014.59 seconds
Started Apr 30 12:43:06 PM PDT 24
Finished Apr 30 02:23:22 PM PDT 24
Peak memory 233172 kb
Host smart-2abd51ac-9b28-41bf-94b5-313cbb32b277
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3224184364 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_stress_all_with_rand_reset.3224184364
Directory /workspace/21.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_intg_err.3213425324
Short name T112
Test name
Test status
Simulation time 587320195 ps
CPU time 39.49 seconds
Started Apr 30 12:42:06 PM PDT 24
Finished Apr 30 12:42:47 PM PDT 24
Peak memory 212440 kb
Host smart-fd2cf639-3a66-41c3-9736-069e62602c5d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3213425324 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_tl_i
ntg_err.3213425324
Directory /workspace/18.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_intg_err.565140910
Short name T118
Test name
Test status
Simulation time 4325765114 ps
CPU time 46.57 seconds
Started Apr 30 12:41:36 PM PDT 24
Finished Apr 30 12:42:23 PM PDT 24
Peak memory 218840 kb
Host smart-6612e171-3b6c-4978-8da3-196f93e8a2f6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=565140910 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_tl_int
g_err.565140910
Directory /workspace/4.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/10.rom_ctrl_max_throughput_chk.1989930288
Short name T108
Test name
Test status
Simulation time 98223974 ps
CPU time 5.77 seconds
Started Apr 30 12:42:29 PM PDT 24
Finished Apr 30 12:42:35 PM PDT 24
Peak memory 211408 kb
Host smart-1b3ebf44-fd50-4bcf-8834-3837773673eb
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1989930288 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_max_throughput_chk.1989930288
Directory /workspace/10.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/33.rom_ctrl_stress_all.1219599803
Short name T40
Test name
Test status
Simulation time 8800338889 ps
CPU time 53.24 seconds
Started Apr 30 12:43:25 PM PDT 24
Finished Apr 30 12:44:19 PM PDT 24
Peak memory 217152 kb
Host smart-eac32714-5642-4235-8a17-e24704654940
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1219599803 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 33.rom_ctrl_stress_all.1219599803
Directory /workspace/33.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/31.rom_ctrl_stress_all_with_rand_reset.2875145516
Short name T19
Test name
Test status
Simulation time 88454105354 ps
CPU time 3457.49 seconds
Started Apr 30 12:43:24 PM PDT 24
Finished Apr 30 01:41:03 PM PDT 24
Peak memory 244352 kb
Host smart-e54fbefe-5693-4772-9617-a3f75329c0ac
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2875145516 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_stress_all_with_rand_reset.2875145516
Directory /workspace/31.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_aliasing.3303321998
Short name T86
Test name
Test status
Simulation time 1682565770 ps
CPU time 13.82 seconds
Started Apr 30 12:41:23 PM PDT 24
Finished Apr 30 12:41:38 PM PDT 24
Peak memory 210520 kb
Host smart-897ea56f-3394-4322-96ee-3b5a9750a32f
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3303321998 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_alia
sing.3303321998
Directory /workspace/0.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_bit_bash.3641549101
Short name T388
Test name
Test status
Simulation time 6131997902 ps
CPU time 12.42 seconds
Started Apr 30 12:41:23 PM PDT 24
Finished Apr 30 12:41:36 PM PDT 24
Peak memory 210592 kb
Host smart-1e1ce700-11a9-4e12-960f-5d645e669518
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3641549101 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_bit_
bash.3641549101
Directory /workspace/0.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_hw_reset.1773582643
Short name T463
Test name
Test status
Simulation time 1935556123 ps
CPU time 16.11 seconds
Started Apr 30 12:41:22 PM PDT 24
Finished Apr 30 12:41:39 PM PDT 24
Peak memory 210492 kb
Host smart-50effbd6-04fd-4436-b46a-ef6b63c141ba
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1773582643 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_hw_r
eset.1773582643
Directory /workspace/0.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_mem_rw_with_rand_reset.836572262
Short name T61
Test name
Test status
Simulation time 98723597 ps
CPU time 4.87 seconds
Started Apr 30 12:41:22 PM PDT 24
Finished Apr 30 12:41:28 PM PDT 24
Peak memory 213704 kb
Host smart-5347f72e-2a15-45b9-b90e-3317cfbec535
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=836572262 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 0.rom_ctrl_csr_mem_rw_with_rand_reset.836572262
Directory /workspace/0.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_rw.39975774
Short name T435
Test name
Test status
Simulation time 8901611542 ps
CPU time 16.31 seconds
Started Apr 30 12:41:22 PM PDT 24
Finished Apr 30 12:41:39 PM PDT 24
Peak memory 210500 kb
Host smart-6ac5e817-6b27-4083-8e9f-7ba9eaa32b10
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39975774 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_rw.39975774
Directory /workspace/0.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_partial_access.1208673701
Short name T385
Test name
Test status
Simulation time 168552403 ps
CPU time 4.07 seconds
Started Apr 30 12:41:22 PM PDT 24
Finished Apr 30 12:41:27 PM PDT 24
Peak memory 210292 kb
Host smart-6a94d35b-95f0-4b13-9df2-e6121404eac7
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1208673701 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctr
l_mem_partial_access.1208673701
Directory /workspace/0.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_walk.4058764163
Short name T369
Test name
Test status
Simulation time 3649265172 ps
CPU time 9.89 seconds
Started Apr 30 12:41:22 PM PDT 24
Finished Apr 30 12:41:33 PM PDT 24
Peak memory 210448 kb
Host smart-e876c209-0aef-47e8-838d-ca918a56f7ed
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4058764163 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_mem_walk
.4058764163
Directory /workspace/0.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_passthru_mem_tl_intg_err.3569835339
Short name T448
Test name
Test status
Simulation time 31942562623 ps
CPU time 53.25 seconds
Started Apr 30 12:41:17 PM PDT 24
Finished Apr 30 12:42:11 PM PDT 24
Peak memory 210596 kb
Host smart-aeaed56d-a22d-47a0-9028-11e34786585b
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3569835339 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_pa
ssthru_mem_tl_intg_err.3569835339
Directory /workspace/0.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_same_csr_outstanding.3781830861
Short name T420
Test name
Test status
Simulation time 2940878171 ps
CPU time 14.19 seconds
Started Apr 30 12:41:22 PM PDT 24
Finished Apr 30 12:41:37 PM PDT 24
Peak memory 210508 kb
Host smart-2d0fa8ce-c929-4854-a0ce-cf7076ec7e74
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3781830861 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_c
trl_same_csr_outstanding.3781830861
Directory /workspace/0.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_errors.4179837118
Short name T444
Test name
Test status
Simulation time 493141008 ps
CPU time 8.72 seconds
Started Apr 30 12:41:17 PM PDT 24
Finished Apr 30 12:41:26 PM PDT 24
Peak memory 218700 kb
Host smart-fb07ac85-f60b-4862-899d-87624e452b82
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4179837118 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_tl_errors.4179837118
Directory /workspace/0.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_intg_err.3736976604
Short name T120
Test name
Test status
Simulation time 12603572754 ps
CPU time 40.15 seconds
Started Apr 30 12:41:16 PM PDT 24
Finished Apr 30 12:41:57 PM PDT 24
Peak memory 211588 kb
Host smart-f3e01344-13a9-411c-b82f-d6fcc0db5d8b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3736976604 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_tl_in
tg_err.3736976604
Directory /workspace/0.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_aliasing.2745742097
Short name T89
Test name
Test status
Simulation time 378193745 ps
CPU time 4.27 seconds
Started Apr 30 12:41:22 PM PDT 24
Finished Apr 30 12:41:27 PM PDT 24
Peak memory 210448 kb
Host smart-00f11310-f102-4048-9f26-23e4d814167a
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2745742097 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_alia
sing.2745742097
Directory /workspace/1.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_bit_bash.1606604520
Short name T405
Test name
Test status
Simulation time 6183537743 ps
CPU time 11.62 seconds
Started Apr 30 12:41:22 PM PDT 24
Finished Apr 30 12:41:34 PM PDT 24
Peak memory 210596 kb
Host smart-58e93200-56f5-4069-96b1-f8b0e16bbfaa
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1606604520 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_bit_
bash.1606604520
Directory /workspace/1.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_hw_reset.2877224497
Short name T401
Test name
Test status
Simulation time 7923042381 ps
CPU time 17.86 seconds
Started Apr 30 12:41:24 PM PDT 24
Finished Apr 30 12:41:43 PM PDT 24
Peak memory 210572 kb
Host smart-153a6cff-8a4e-4388-923c-d8c3650730f9
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2877224497 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_hw_r
eset.2877224497
Directory /workspace/1.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_mem_rw_with_rand_reset.3229419425
Short name T365
Test name
Test status
Simulation time 633581722 ps
CPU time 4.35 seconds
Started Apr 30 12:41:22 PM PDT 24
Finished Apr 30 12:41:27 PM PDT 24
Peak memory 212164 kb
Host smart-50b5895a-22bb-4284-ac0f-efb42c7001b6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3229419425 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 1.rom_ctrl_csr_mem_rw_with_rand_reset.3229419425
Directory /workspace/1.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_rw.1749464682
Short name T458
Test name
Test status
Simulation time 333213001 ps
CPU time 3.95 seconds
Started Apr 30 12:41:23 PM PDT 24
Finished Apr 30 12:41:27 PM PDT 24
Peak memory 210552 kb
Host smart-8e9199bc-767d-4dae-aa6e-5cd87a8358cb
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1749464682 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_rw.1749464682
Directory /workspace/1.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_partial_access.3907945415
Short name T399
Test name
Test status
Simulation time 900375927 ps
CPU time 9.35 seconds
Started Apr 30 12:41:22 PM PDT 24
Finished Apr 30 12:41:32 PM PDT 24
Peak memory 210344 kb
Host smart-b0cd41f5-1bfe-4dbc-ab3b-969c8336219a
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3907945415 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctr
l_mem_partial_access.3907945415
Directory /workspace/1.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_walk.1223738841
Short name T403
Test name
Test status
Simulation time 3564298250 ps
CPU time 9.61 seconds
Started Apr 30 12:41:21 PM PDT 24
Finished Apr 30 12:41:32 PM PDT 24
Peak memory 210460 kb
Host smart-603749a3-5ea8-4532-aa84-a295e9cca808
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1223738841 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_mem_walk
.1223738841
Directory /workspace/1.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_same_csr_outstanding.3972013000
Short name T60
Test name
Test status
Simulation time 1661363727 ps
CPU time 13.18 seconds
Started Apr 30 12:41:22 PM PDT 24
Finished Apr 30 12:41:36 PM PDT 24
Peak memory 210532 kb
Host smart-3dd8bcb7-03dd-4c57-8b36-4a3831ef7d82
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3972013000 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_c
trl_same_csr_outstanding.3972013000
Directory /workspace/1.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_errors.889055743
Short name T422
Test name
Test status
Simulation time 333201145 ps
CPU time 6.12 seconds
Started Apr 30 12:41:22 PM PDT 24
Finished Apr 30 12:41:29 PM PDT 24
Peak memory 218792 kb
Host smart-b5e210ef-2477-402e-b8ba-b94a7c58b1b6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=889055743 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_tl_errors.889055743
Directory /workspace/1.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_intg_err.644596029
Short name T121
Test name
Test status
Simulation time 2665983215 ps
CPU time 46.41 seconds
Started Apr 30 12:41:21 PM PDT 24
Finished Apr 30 12:42:08 PM PDT 24
Peak memory 212312 kb
Host smart-319e4608-58ec-4568-aa6a-f49e02267921
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=644596029 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_tl_int
g_err.644596029
Directory /workspace/1.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_mem_rw_with_rand_reset.3866023668
Short name T396
Test name
Test status
Simulation time 104539218 ps
CPU time 5.01 seconds
Started Apr 30 12:41:55 PM PDT 24
Finished Apr 30 12:42:00 PM PDT 24
Peak memory 218736 kb
Host smart-efaf4a14-aab4-4d6a-bb63-62ffb410096c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3866023668 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 10.rom_ctrl_csr_mem_rw_with_rand_reset.3866023668
Directory /workspace/10.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_rw.3114464753
Short name T85
Test name
Test status
Simulation time 4530979000 ps
CPU time 16.43 seconds
Started Apr 30 12:41:53 PM PDT 24
Finished Apr 30 12:42:10 PM PDT 24
Peak memory 210536 kb
Host smart-f84e706b-fd29-4580-8e41-9716939666f3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3114464753 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_csr_rw.3114464753
Directory /workspace/10.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_passthru_mem_tl_intg_err.1854244974
Short name T442
Test name
Test status
Simulation time 3494232727 ps
CPU time 49.2 seconds
Started Apr 30 12:41:49 PM PDT 24
Finished Apr 30 12:42:39 PM PDT 24
Peak memory 217756 kb
Host smart-fd4a16bb-b4f4-433b-811b-3d453cb756ab
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1854244974 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_p
assthru_mem_tl_intg_err.1854244974
Directory /workspace/10.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_same_csr_outstanding.3547547754
Short name T74
Test name
Test status
Simulation time 2652658349 ps
CPU time 8.64 seconds
Started Apr 30 12:41:54 PM PDT 24
Finished Apr 30 12:42:03 PM PDT 24
Peak memory 210604 kb
Host smart-cc8318a7-2747-40ac-ac29-df698dcf7af1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3547547754 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_
ctrl_same_csr_outstanding.3547547754
Directory /workspace/10.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_errors.2090895715
Short name T400
Test name
Test status
Simulation time 2157850834 ps
CPU time 18.43 seconds
Started Apr 30 12:41:49 PM PDT 24
Finished Apr 30 12:42:08 PM PDT 24
Peak memory 218788 kb
Host smart-92f55aeb-5d97-4226-9889-4e59385c135f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2090895715 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_tl_errors.2090895715
Directory /workspace/10.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_intg_err.899263268
Short name T59
Test name
Test status
Simulation time 664652852 ps
CPU time 67.96 seconds
Started Apr 30 12:41:50 PM PDT 24
Finished Apr 30 12:42:58 PM PDT 24
Peak memory 211508 kb
Host smart-9a362928-fa97-4ed3-9a24-76b807038f8e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=899263268 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_tl_in
tg_err.899263268
Directory /workspace/10.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_mem_rw_with_rand_reset.2303034762
Short name T391
Test name
Test status
Simulation time 356295540 ps
CPU time 5.79 seconds
Started Apr 30 12:41:52 PM PDT 24
Finished Apr 30 12:41:58 PM PDT 24
Peak memory 211600 kb
Host smart-95d5c268-3d33-4cdd-83d7-0948f5a21558
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2303034762 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 11.rom_ctrl_csr_mem_rw_with_rand_reset.2303034762
Directory /workspace/11.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_rw.84672987
Short name T416
Test name
Test status
Simulation time 2028620584 ps
CPU time 15.06 seconds
Started Apr 30 12:41:51 PM PDT 24
Finished Apr 30 12:42:07 PM PDT 24
Peak memory 210420 kb
Host smart-87d2761f-1e8c-4a0f-a16b-7aaee5407435
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=84672987 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_csr_rw.84672987
Directory /workspace/11.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_passthru_mem_tl_intg_err.29367506
Short name T387
Test name
Test status
Simulation time 475655485 ps
CPU time 18.14 seconds
Started Apr 30 12:41:53 PM PDT 24
Finished Apr 30 12:42:12 PM PDT 24
Peak memory 210500 kb
Host smart-ed79a4d3-1cfd-4c0d-a4dc-4027dc3b2836
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29367506 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_pas
sthru_mem_tl_intg_err.29367506
Directory /workspace/11.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_same_csr_outstanding.2836011863
Short name T70
Test name
Test status
Simulation time 28775355155 ps
CPU time 18.33 seconds
Started Apr 30 12:41:53 PM PDT 24
Finished Apr 30 12:42:12 PM PDT 24
Peak memory 210612 kb
Host smart-c625ee47-b7c5-4c40-8d91-c85d46f70ad9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2836011863 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_
ctrl_same_csr_outstanding.2836011863
Directory /workspace/11.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_errors.3347819216
Short name T371
Test name
Test status
Simulation time 4858396342 ps
CPU time 12.01 seconds
Started Apr 30 12:41:51 PM PDT 24
Finished Apr 30 12:42:03 PM PDT 24
Peak memory 218828 kb
Host smart-07cab2cc-c566-4f4f-97fb-3951802b8395
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3347819216 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_tl_errors.3347819216
Directory /workspace/11.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_intg_err.878134676
Short name T119
Test name
Test status
Simulation time 2448587822 ps
CPU time 39 seconds
Started Apr 30 12:41:54 PM PDT 24
Finished Apr 30 12:42:34 PM PDT 24
Peak memory 210524 kb
Host smart-7c5bb856-df37-4a76-8256-193355df1560
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=878134676 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_tl_in
tg_err.878134676
Directory /workspace/11.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_mem_rw_with_rand_reset.1065559527
Short name T411
Test name
Test status
Simulation time 6487523363 ps
CPU time 11.87 seconds
Started Apr 30 12:41:54 PM PDT 24
Finished Apr 30 12:42:06 PM PDT 24
Peak memory 218864 kb
Host smart-04a77240-4a95-4091-aa3e-6ac7a1ad18bb
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1065559527 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 12.rom_ctrl_csr_mem_rw_with_rand_reset.1065559527
Directory /workspace/12.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_rw.2411799206
Short name T454
Test name
Test status
Simulation time 884774672 ps
CPU time 9.62 seconds
Started Apr 30 12:41:54 PM PDT 24
Finished Apr 30 12:42:05 PM PDT 24
Peak memory 210472 kb
Host smart-793a5b7b-d339-4f9e-94c1-becfbaf5e52e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2411799206 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_csr_rw.2411799206
Directory /workspace/12.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_passthru_mem_tl_intg_err.1636450919
Short name T95
Test name
Test status
Simulation time 7172119144 ps
CPU time 66.94 seconds
Started Apr 30 12:41:54 PM PDT 24
Finished Apr 30 12:43:02 PM PDT 24
Peak memory 210600 kb
Host smart-6c67a066-7d73-47be-99de-1a1dcf075436
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1636450919 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_p
assthru_mem_tl_intg_err.1636450919
Directory /workspace/12.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_same_csr_outstanding.3603042407
Short name T437
Test name
Test status
Simulation time 1593227452 ps
CPU time 13.44 seconds
Started Apr 30 12:41:51 PM PDT 24
Finished Apr 30 12:42:05 PM PDT 24
Peak memory 210496 kb
Host smart-f3ffe583-0ffc-4812-8c00-a2d7b8958dae
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3603042407 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_
ctrl_same_csr_outstanding.3603042407
Directory /workspace/12.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_errors.1183295654
Short name T368
Test name
Test status
Simulation time 893706270 ps
CPU time 10.03 seconds
Started Apr 30 12:41:53 PM PDT 24
Finished Apr 30 12:42:04 PM PDT 24
Peak memory 218808 kb
Host smart-aef08775-d6bc-4545-b5b6-297ec8c09ea0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1183295654 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_tl_errors.1183295654
Directory /workspace/12.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_intg_err.3650541566
Short name T407
Test name
Test status
Simulation time 1377202098 ps
CPU time 75.02 seconds
Started Apr 30 12:41:53 PM PDT 24
Finished Apr 30 12:43:09 PM PDT 24
Peak memory 211336 kb
Host smart-3de0731a-9a35-49a2-be20-81fb29aa25a5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3650541566 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_tl_i
ntg_err.3650541566
Directory /workspace/12.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_mem_rw_with_rand_reset.1089742481
Short name T366
Test name
Test status
Simulation time 1789990827 ps
CPU time 14.21 seconds
Started Apr 30 12:42:02 PM PDT 24
Finished Apr 30 12:42:17 PM PDT 24
Peak memory 213204 kb
Host smart-d3877f00-4b28-4b80-8bed-197ebb902af3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1089742481 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 13.rom_ctrl_csr_mem_rw_with_rand_reset.1089742481
Directory /workspace/13.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_rw.2595418463
Short name T376
Test name
Test status
Simulation time 12405803915 ps
CPU time 15.24 seconds
Started Apr 30 12:42:02 PM PDT 24
Finished Apr 30 12:42:17 PM PDT 24
Peak memory 210616 kb
Host smart-1702f0c7-44f6-405a-8584-2cb289b90f5e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2595418463 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_csr_rw.2595418463
Directory /workspace/13.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_passthru_mem_tl_intg_err.843246335
Short name T93
Test name
Test status
Simulation time 728032137 ps
CPU time 23.83 seconds
Started Apr 30 12:41:53 PM PDT 24
Finished Apr 30 12:42:17 PM PDT 24
Peak memory 210476 kb
Host smart-2542a35a-278f-4aee-81e3-78d4566b2ab5
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=843246335 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_pa
ssthru_mem_tl_intg_err.843246335
Directory /workspace/13.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_same_csr_outstanding.3009779800
Short name T460
Test name
Test status
Simulation time 1758382079 ps
CPU time 14.75 seconds
Started Apr 30 12:42:01 PM PDT 24
Finished Apr 30 12:42:17 PM PDT 24
Peak memory 210560 kb
Host smart-baf65e9e-47b0-46e3-9ada-2715e22c9a05
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3009779800 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_
ctrl_same_csr_outstanding.3009779800
Directory /workspace/13.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_errors.1181663904
Short name T380
Test name
Test status
Simulation time 2989334598 ps
CPU time 17.66 seconds
Started Apr 30 12:41:52 PM PDT 24
Finished Apr 30 12:42:11 PM PDT 24
Peak memory 218788 kb
Host smart-349ed35e-3ab3-4e9f-afea-7c046cb15556
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1181663904 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_tl_errors.1181663904
Directory /workspace/13.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_mem_rw_with_rand_reset.1520147225
Short name T402
Test name
Test status
Simulation time 4953390339 ps
CPU time 11.64 seconds
Started Apr 30 12:42:00 PM PDT 24
Finished Apr 30 12:42:12 PM PDT 24
Peak memory 218776 kb
Host smart-f05e825b-70a5-4ac7-ab84-ee59d39108d6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1520147225 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 14.rom_ctrl_csr_mem_rw_with_rand_reset.1520147225
Directory /workspace/14.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_rw.4241779306
Short name T443
Test name
Test status
Simulation time 917337233 ps
CPU time 9.82 seconds
Started Apr 30 12:42:02 PM PDT 24
Finished Apr 30 12:42:12 PM PDT 24
Peak memory 210512 kb
Host smart-e375582c-38c7-45cf-8fe5-263f09818c49
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4241779306 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_csr_rw.4241779306
Directory /workspace/14.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_passthru_mem_tl_intg_err.3441529030
Short name T390
Test name
Test status
Simulation time 1104053425 ps
CPU time 27.81 seconds
Started Apr 30 12:42:01 PM PDT 24
Finished Apr 30 12:42:30 PM PDT 24
Peak memory 210484 kb
Host smart-a35aecb3-0587-4fe5-9c18-f547ee087389
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3441529030 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_p
assthru_mem_tl_intg_err.3441529030
Directory /workspace/14.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_same_csr_outstanding.292908993
Short name T424
Test name
Test status
Simulation time 1653183827 ps
CPU time 11.06 seconds
Started Apr 30 12:42:01 PM PDT 24
Finished Apr 30 12:42:13 PM PDT 24
Peak memory 210228 kb
Host smart-8a0ea8cb-3428-4858-9807-4feb5af3ef0e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=292908993 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_c
trl_same_csr_outstanding.292908993
Directory /workspace/14.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_errors.1150515664
Short name T426
Test name
Test status
Simulation time 24028740545 ps
CPU time 18.35 seconds
Started Apr 30 12:42:00 PM PDT 24
Finished Apr 30 12:42:19 PM PDT 24
Peak memory 218856 kb
Host smart-0fd9d4ec-fa82-4fc7-a363-e3979b55119b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1150515664 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_tl_errors.1150515664
Directory /workspace/14.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_intg_err.228564515
Short name T423
Test name
Test status
Simulation time 954489354 ps
CPU time 68.61 seconds
Started Apr 30 12:42:00 PM PDT 24
Finished Apr 30 12:43:09 PM PDT 24
Peak memory 210608 kb
Host smart-dc4ace94-acaf-4d88-b7df-6a2a4c11ce80
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=228564515 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_tl_in
tg_err.228564515
Directory /workspace/14.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_mem_rw_with_rand_reset.4026371603
Short name T374
Test name
Test status
Simulation time 238752242 ps
CPU time 5.81 seconds
Started Apr 30 12:42:00 PM PDT 24
Finished Apr 30 12:42:06 PM PDT 24
Peak memory 218732 kb
Host smart-de581c9f-9cde-4cb5-99c9-21b96bc0e92d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4026371603 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 15.rom_ctrl_csr_mem_rw_with_rand_reset.4026371603
Directory /workspace/15.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_rw.4187205098
Short name T392
Test name
Test status
Simulation time 7765361636 ps
CPU time 15.59 seconds
Started Apr 30 12:41:59 PM PDT 24
Finished Apr 30 12:42:15 PM PDT 24
Peak memory 210616 kb
Host smart-d635936b-4619-4179-8b47-8ee3b45560ad
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4187205098 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_csr_rw.4187205098
Directory /workspace/15.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_passthru_mem_tl_intg_err.993337763
Short name T462
Test name
Test status
Simulation time 3952160962 ps
CPU time 40.4 seconds
Started Apr 30 12:42:04 PM PDT 24
Finished Apr 30 12:42:45 PM PDT 24
Peak memory 210464 kb
Host smart-4b81eabb-9f22-477a-8b91-4fbc6bde6e70
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=993337763 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_pa
ssthru_mem_tl_intg_err.993337763
Directory /workspace/15.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_same_csr_outstanding.1398924056
Short name T408
Test name
Test status
Simulation time 1365467439 ps
CPU time 6.57 seconds
Started Apr 30 12:42:02 PM PDT 24
Finished Apr 30 12:42:09 PM PDT 24
Peak memory 210428 kb
Host smart-735ae0b0-6ec2-4f90-9b87-32b415cddb8d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1398924056 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_
ctrl_same_csr_outstanding.1398924056
Directory /workspace/15.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_errors.838568832
Short name T367
Test name
Test status
Simulation time 6447248304 ps
CPU time 20.28 seconds
Started Apr 30 12:42:01 PM PDT 24
Finished Apr 30 12:42:22 PM PDT 24
Peak memory 218792 kb
Host smart-8ebc7e70-3768-487d-8ad5-169bc681e240
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=838568832 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_tl_errors.838568832
Directory /workspace/15.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_intg_err.2549128200
Short name T449
Test name
Test status
Simulation time 764390416 ps
CPU time 36.89 seconds
Started Apr 30 12:42:07 PM PDT 24
Finished Apr 30 12:42:45 PM PDT 24
Peak memory 211416 kb
Host smart-7106ccaa-a82a-474e-8011-0a5711691744
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2549128200 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_tl_i
ntg_err.2549128200
Directory /workspace/15.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_mem_rw_with_rand_reset.2359095332
Short name T447
Test name
Test status
Simulation time 2955729847 ps
CPU time 11.18 seconds
Started Apr 30 12:42:03 PM PDT 24
Finished Apr 30 12:42:15 PM PDT 24
Peak memory 218716 kb
Host smart-5151f170-89af-43ce-8a1f-811fb466c7a0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2359095332 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 16.rom_ctrl_csr_mem_rw_with_rand_reset.2359095332
Directory /workspace/16.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_rw.1660420803
Short name T428
Test name
Test status
Simulation time 346168400 ps
CPU time 6.72 seconds
Started Apr 30 12:42:02 PM PDT 24
Finished Apr 30 12:42:09 PM PDT 24
Peak memory 210460 kb
Host smart-417fcf4d-6290-436d-847e-823bebe6f0e6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1660420803 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_csr_rw.1660420803
Directory /workspace/16.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_passthru_mem_tl_intg_err.1132524742
Short name T104
Test name
Test status
Simulation time 1514690680 ps
CPU time 28.27 seconds
Started Apr 30 12:42:04 PM PDT 24
Finished Apr 30 12:42:32 PM PDT 24
Peak memory 210324 kb
Host smart-3550b6a8-0c65-42b3-8ba8-9d3351def029
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1132524742 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_p
assthru_mem_tl_intg_err.1132524742
Directory /workspace/16.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_same_csr_outstanding.790025792
Short name T409
Test name
Test status
Simulation time 4086450079 ps
CPU time 10.23 seconds
Started Apr 30 12:42:01 PM PDT 24
Finished Apr 30 12:42:12 PM PDT 24
Peak memory 210572 kb
Host smart-0886a488-17d5-4a75-8768-7cb0d069b89f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=790025792 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_c
trl_same_csr_outstanding.790025792
Directory /workspace/16.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_errors.4053891233
Short name T379
Test name
Test status
Simulation time 5917490022 ps
CPU time 14.42 seconds
Started Apr 30 12:42:03 PM PDT 24
Finished Apr 30 12:42:18 PM PDT 24
Peak memory 218840 kb
Host smart-0f1f146e-b67d-4b2c-b6a6-0e5e5ae3eeb0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4053891233 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_tl_errors.4053891233
Directory /workspace/16.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_intg_err.3417955892
Short name T425
Test name
Test status
Simulation time 3124154300 ps
CPU time 39.03 seconds
Started Apr 30 12:41:59 PM PDT 24
Finished Apr 30 12:42:39 PM PDT 24
Peak memory 210488 kb
Host smart-0e71cb7f-c4e4-46ec-8a82-91d9b4c718a6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3417955892 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_tl_i
ntg_err.3417955892
Directory /workspace/16.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_mem_rw_with_rand_reset.2381360444
Short name T436
Test name
Test status
Simulation time 2624766184 ps
CPU time 11.76 seconds
Started Apr 30 12:42:06 PM PDT 24
Finished Apr 30 12:42:19 PM PDT 24
Peak memory 211860 kb
Host smart-a1f337e2-9d12-4fd0-be63-6c39f9ecb352
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2381360444 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 17.rom_ctrl_csr_mem_rw_with_rand_reset.2381360444
Directory /workspace/17.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_rw.1742045098
Short name T84
Test name
Test status
Simulation time 7310614319 ps
CPU time 14.48 seconds
Started Apr 30 12:41:59 PM PDT 24
Finished Apr 30 12:42:14 PM PDT 24
Peak memory 210528 kb
Host smart-30cf5374-b6c6-4330-a923-d7fff3aec9d3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1742045098 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_csr_rw.1742045098
Directory /workspace/17.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_passthru_mem_tl_intg_err.3236302840
Short name T102
Test name
Test status
Simulation time 25601200403 ps
CPU time 56.06 seconds
Started Apr 30 12:42:00 PM PDT 24
Finished Apr 30 12:42:57 PM PDT 24
Peak memory 210616 kb
Host smart-fa733105-9afe-4127-8eeb-b6314c00b825
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3236302840 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_p
assthru_mem_tl_intg_err.3236302840
Directory /workspace/17.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_same_csr_outstanding.3220480450
Short name T100
Test name
Test status
Simulation time 763337781 ps
CPU time 5.81 seconds
Started Apr 30 12:42:15 PM PDT 24
Finished Apr 30 12:42:22 PM PDT 24
Peak memory 210504 kb
Host smart-b6dce3dd-7da2-45f4-b205-1de3cb68eeea
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3220480450 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_
ctrl_same_csr_outstanding.3220480450
Directory /workspace/17.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_errors.4213036431
Short name T384
Test name
Test status
Simulation time 2380372688 ps
CPU time 13.13 seconds
Started Apr 30 12:42:03 PM PDT 24
Finished Apr 30 12:42:16 PM PDT 24
Peak memory 218740 kb
Host smart-06566b35-d5c8-4a77-9c72-f3d5ff4c8a52
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4213036431 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_tl_errors.4213036431
Directory /workspace/17.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_intg_err.568308414
Short name T116
Test name
Test status
Simulation time 1608268307 ps
CPU time 73.84 seconds
Started Apr 30 12:42:00 PM PDT 24
Finished Apr 30 12:43:14 PM PDT 24
Peak memory 210452 kb
Host smart-e6e8c7fd-6365-4536-b2b0-15574d274016
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=568308414 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_tl_in
tg_err.568308414
Directory /workspace/17.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_mem_rw_with_rand_reset.1649748772
Short name T375
Test name
Test status
Simulation time 8239203881 ps
CPU time 15.59 seconds
Started Apr 30 12:42:08 PM PDT 24
Finished Apr 30 12:42:25 PM PDT 24
Peak memory 218844 kb
Host smart-20d0c83a-3ce2-450b-b97f-7d784a7594fc
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1649748772 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 18.rom_ctrl_csr_mem_rw_with_rand_reset.1649748772
Directory /workspace/18.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_rw.3882852196
Short name T90
Test name
Test status
Simulation time 1852904374 ps
CPU time 15.05 seconds
Started Apr 30 12:42:07 PM PDT 24
Finished Apr 30 12:42:23 PM PDT 24
Peak memory 210508 kb
Host smart-9a2960a7-df4c-49c4-bc70-5500573cbd61
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3882852196 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_csr_rw.3882852196
Directory /workspace/18.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_passthru_mem_tl_intg_err.3976605516
Short name T101
Test name
Test status
Simulation time 9834642023 ps
CPU time 43.02 seconds
Started Apr 30 12:42:06 PM PDT 24
Finished Apr 30 12:42:50 PM PDT 24
Peak memory 210684 kb
Host smart-a6a3a84d-b2cc-4d8e-badd-f3d0c9ca40eb
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3976605516 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_p
assthru_mem_tl_intg_err.3976605516
Directory /workspace/18.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_same_csr_outstanding.3948750641
Short name T419
Test name
Test status
Simulation time 6960445065 ps
CPU time 14.81 seconds
Started Apr 30 12:42:13 PM PDT 24
Finished Apr 30 12:42:29 PM PDT 24
Peak memory 210552 kb
Host smart-67bb4435-9fa7-425e-aa38-ffd025531a45
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3948750641 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_
ctrl_same_csr_outstanding.3948750641
Directory /workspace/18.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_errors.3083923
Short name T410
Test name
Test status
Simulation time 7422753798 ps
CPU time 18.98 seconds
Started Apr 30 12:42:06 PM PDT 24
Finished Apr 30 12:42:26 PM PDT 24
Peak memory 218772 kb
Host smart-0f2f17e7-4353-4c7d-9b3e-f2c8cdbba465
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3083923 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_tl_errors.3083923
Directory /workspace/18.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_mem_rw_with_rand_reset.2395939460
Short name T372
Test name
Test status
Simulation time 11935111157 ps
CPU time 15.64 seconds
Started Apr 30 12:42:06 PM PDT 24
Finished Apr 30 12:42:23 PM PDT 24
Peak memory 212280 kb
Host smart-4f397b6a-23fe-40b4-8c0c-f88e61654997
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2395939460 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 19.rom_ctrl_csr_mem_rw_with_rand_reset.2395939460
Directory /workspace/19.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_rw.51702990
Short name T450
Test name
Test status
Simulation time 1899387282 ps
CPU time 7.36 seconds
Started Apr 30 12:42:08 PM PDT 24
Finished Apr 30 12:42:17 PM PDT 24
Peak memory 210428 kb
Host smart-01c7ef06-34af-4043-a5f8-eeec08fcef35
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51702990 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_csr_rw.51702990
Directory /workspace/19.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_same_csr_outstanding.3312415821
Short name T445
Test name
Test status
Simulation time 1815081112 ps
CPU time 10.91 seconds
Started Apr 30 12:42:06 PM PDT 24
Finished Apr 30 12:42:18 PM PDT 24
Peak memory 210460 kb
Host smart-41ef83ee-bbe7-49b2-a1fa-d8148b5a2425
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3312415821 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_
ctrl_same_csr_outstanding.3312415821
Directory /workspace/19.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_errors.3959454042
Short name T457
Test name
Test status
Simulation time 653425703 ps
CPU time 11.7 seconds
Started Apr 30 12:42:07 PM PDT 24
Finished Apr 30 12:42:20 PM PDT 24
Peak memory 218492 kb
Host smart-9d347eea-28cf-4ec1-a946-2d9ae31b5ef1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3959454042 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_tl_errors.3959454042
Directory /workspace/19.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_intg_err.521418086
Short name T459
Test name
Test status
Simulation time 897816008 ps
CPU time 70.5 seconds
Started Apr 30 12:42:10 PM PDT 24
Finished Apr 30 12:43:21 PM PDT 24
Peak memory 211404 kb
Host smart-8c173ea6-55b0-4dbf-b73e-0431447adf05
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=521418086 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_tl_in
tg_err.521418086
Directory /workspace/19.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_aliasing.1729559607
Short name T453
Test name
Test status
Simulation time 4378222669 ps
CPU time 16.04 seconds
Started Apr 30 12:41:36 PM PDT 24
Finished Apr 30 12:41:53 PM PDT 24
Peak memory 210672 kb
Host smart-a20291b2-3603-4d6b-8b10-729aa97517c0
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1729559607 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_alia
sing.1729559607
Directory /workspace/2.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_bit_bash.1152026877
Short name T382
Test name
Test status
Simulation time 1107759959 ps
CPU time 11.02 seconds
Started Apr 30 12:41:29 PM PDT 24
Finished Apr 30 12:41:40 PM PDT 24
Peak memory 210444 kb
Host smart-393f9a46-7e6e-4477-b7c3-a43eec2e596f
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1152026877 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_bit_
bash.1152026877
Directory /workspace/2.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_hw_reset.3122764840
Short name T439
Test name
Test status
Simulation time 2162812435 ps
CPU time 13.52 seconds
Started Apr 30 12:41:29 PM PDT 24
Finished Apr 30 12:41:44 PM PDT 24
Peak memory 210504 kb
Host smart-56cf8ba1-da22-4206-a144-26016dc0a183
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3122764840 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_hw_r
eset.3122764840
Directory /workspace/2.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_mem_rw_with_rand_reset.1444557930
Short name T434
Test name
Test status
Simulation time 1177831456 ps
CPU time 12.3 seconds
Started Apr 30 12:41:36 PM PDT 24
Finished Apr 30 12:41:49 PM PDT 24
Peak memory 218716 kb
Host smart-557565f7-f97e-4d4d-b625-9f422d6336dc
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1444557930 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 2.rom_ctrl_csr_mem_rw_with_rand_reset.1444557930
Directory /workspace/2.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_rw.1198431783
Short name T377
Test name
Test status
Simulation time 2816566946 ps
CPU time 8.72 seconds
Started Apr 30 12:41:32 PM PDT 24
Finished Apr 30 12:41:42 PM PDT 24
Peak memory 210536 kb
Host smart-7fa1c827-eb6b-4a86-badf-c29006ad635c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1198431783 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_rw.1198431783
Directory /workspace/2.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_partial_access.3609592994
Short name T421
Test name
Test status
Simulation time 3333116217 ps
CPU time 13.26 seconds
Started Apr 30 12:41:30 PM PDT 24
Finished Apr 30 12:41:44 PM PDT 24
Peak memory 210412 kb
Host smart-499185d9-b94e-42f1-b32e-f38acc992468
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3609592994 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctr
l_mem_partial_access.3609592994
Directory /workspace/2.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_walk.1850280485
Short name T395
Test name
Test status
Simulation time 21120277001 ps
CPU time 12.99 seconds
Started Apr 30 12:41:36 PM PDT 24
Finished Apr 30 12:41:50 PM PDT 24
Peak memory 210608 kb
Host smart-218abea3-0d6b-43b9-ad6a-b6791c0ebaa1
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1850280485 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_mem_walk
.1850280485
Directory /workspace/2.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_passthru_mem_tl_intg_err.3575208751
Short name T88
Test name
Test status
Simulation time 43193004756 ps
CPU time 51.36 seconds
Started Apr 30 12:41:23 PM PDT 24
Finished Apr 30 12:42:15 PM PDT 24
Peak memory 210564 kb
Host smart-975eef61-8b1e-436e-a8a7-328460c74bcc
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3575208751 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_pa
ssthru_mem_tl_intg_err.3575208751
Directory /workspace/2.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_same_csr_outstanding.3549505705
Short name T103
Test name
Test status
Simulation time 5129829037 ps
CPU time 11.48 seconds
Started Apr 30 12:41:29 PM PDT 24
Finished Apr 30 12:41:40 PM PDT 24
Peak memory 210632 kb
Host smart-b4069768-febb-436c-9ab5-913f591b4a58
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3549505705 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_c
trl_same_csr_outstanding.3549505705
Directory /workspace/2.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_errors.3923141334
Short name T386
Test name
Test status
Simulation time 7436025914 ps
CPU time 18 seconds
Started Apr 30 12:41:22 PM PDT 24
Finished Apr 30 12:41:40 PM PDT 24
Peak memory 218852 kb
Host smart-4ee19635-dfb1-45e0-8aed-211d7b8026bd
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3923141334 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_tl_errors.3923141334
Directory /workspace/2.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_intg_err.2875080805
Short name T58
Test name
Test status
Simulation time 10861433387 ps
CPU time 71.41 seconds
Started Apr 30 12:41:26 PM PDT 24
Finished Apr 30 12:42:38 PM PDT 24
Peak memory 218684 kb
Host smart-14fef325-74e2-4f4d-8f0c-1794cf4ed18d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2875080805 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_tl_in
tg_err.2875080805
Directory /workspace/2.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_aliasing.792724294
Short name T71
Test name
Test status
Simulation time 89979666 ps
CPU time 4.27 seconds
Started Apr 30 12:41:32 PM PDT 24
Finished Apr 30 12:41:37 PM PDT 24
Peak memory 210432 kb
Host smart-a5a57152-2a2e-44f1-a4f5-e51a84012c0e
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=792724294 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_alias
ing.792724294
Directory /workspace/3.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_bit_bash.2326861575
Short name T456
Test name
Test status
Simulation time 7875377075 ps
CPU time 16.15 seconds
Started Apr 30 12:41:34 PM PDT 24
Finished Apr 30 12:41:51 PM PDT 24
Peak memory 210516 kb
Host smart-b45f8a68-47ae-4041-bd68-ad108d87505f
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2326861575 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_bit_
bash.2326861575
Directory /workspace/3.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_hw_reset.3320656828
Short name T91
Test name
Test status
Simulation time 429217133 ps
CPU time 10.01 seconds
Started Apr 30 12:41:30 PM PDT 24
Finished Apr 30 12:41:40 PM PDT 24
Peak memory 210484 kb
Host smart-1abd82bf-4085-4c99-81a9-3e4fc7d70765
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3320656828 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_hw_r
eset.3320656828
Directory /workspace/3.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_mem_rw_with_rand_reset.2746367042
Short name T393
Test name
Test status
Simulation time 2006974501 ps
CPU time 13.71 seconds
Started Apr 30 12:41:32 PM PDT 24
Finished Apr 30 12:41:46 PM PDT 24
Peak memory 212292 kb
Host smart-26982064-2bdd-4698-9d32-305d71e26e10
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2746367042 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 3.rom_ctrl_csr_mem_rw_with_rand_reset.2746367042
Directory /workspace/3.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_rw.4226940339
Short name T92
Test name
Test status
Simulation time 2377723362 ps
CPU time 7.82 seconds
Started Apr 30 12:41:33 PM PDT 24
Finished Apr 30 12:41:41 PM PDT 24
Peak memory 210540 kb
Host smart-70259c77-3aa8-4437-a567-a1c9f162ecc0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4226940339 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_rw.4226940339
Directory /workspace/3.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_partial_access.3388818404
Short name T430
Test name
Test status
Simulation time 7360117643 ps
CPU time 14.32 seconds
Started Apr 30 12:41:31 PM PDT 24
Finished Apr 30 12:41:46 PM PDT 24
Peak memory 210448 kb
Host smart-ec4cde91-7fa6-422d-9acc-f49f608eda08
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3388818404 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctr
l_mem_partial_access.3388818404
Directory /workspace/3.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_walk.3193785800
Short name T383
Test name
Test status
Simulation time 1969379660 ps
CPU time 13.18 seconds
Started Apr 30 12:41:29 PM PDT 24
Finished Apr 30 12:41:43 PM PDT 24
Peak memory 210484 kb
Host smart-466e8fb3-ae03-41b3-baa5-e3f3506e704a
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3193785800 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_mem_walk
.3193785800
Directory /workspace/3.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_passthru_mem_tl_intg_err.3650981975
Short name T72
Test name
Test status
Simulation time 2261351624 ps
CPU time 28.34 seconds
Started Apr 30 12:41:36 PM PDT 24
Finished Apr 30 12:42:05 PM PDT 24
Peak memory 210592 kb
Host smart-0e358845-0d5a-40f8-b2a2-cf9d3b4a2172
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3650981975 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_pa
ssthru_mem_tl_intg_err.3650981975
Directory /workspace/3.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_same_csr_outstanding.1728467438
Short name T414
Test name
Test status
Simulation time 2980437264 ps
CPU time 12.69 seconds
Started Apr 30 12:41:30 PM PDT 24
Finished Apr 30 12:41:43 PM PDT 24
Peak memory 210552 kb
Host smart-70f41a97-6909-44f7-b3f8-07fc0e5e1c13
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1728467438 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_c
trl_same_csr_outstanding.1728467438
Directory /workspace/3.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_errors.296773030
Short name T452
Test name
Test status
Simulation time 795816658 ps
CPU time 9.89 seconds
Started Apr 30 12:41:31 PM PDT 24
Finished Apr 30 12:41:42 PM PDT 24
Peak memory 218976 kb
Host smart-0727ef60-f81a-40a4-9101-de8ff6d4dd20
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=296773030 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_tl_errors.296773030
Directory /workspace/3.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_intg_err.4027686342
Short name T455
Test name
Test status
Simulation time 730268892 ps
CPU time 36.66 seconds
Started Apr 30 12:41:30 PM PDT 24
Finished Apr 30 12:42:07 PM PDT 24
Peak memory 210484 kb
Host smart-82990650-fb4b-4aca-a3c7-653fe37a3280
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4027686342 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_tl_in
tg_err.4027686342
Directory /workspace/3.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_aliasing.284745396
Short name T75
Test name
Test status
Simulation time 91022412 ps
CPU time 4.2 seconds
Started Apr 30 12:41:37 PM PDT 24
Finished Apr 30 12:41:42 PM PDT 24
Peak memory 210544 kb
Host smart-dc661023-e1c3-410a-be95-7513c46b5751
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=284745396 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_alias
ing.284745396
Directory /workspace/4.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_bit_bash.3002216090
Short name T461
Test name
Test status
Simulation time 3932573390 ps
CPU time 9.8 seconds
Started Apr 30 12:41:31 PM PDT 24
Finished Apr 30 12:41:41 PM PDT 24
Peak memory 210508 kb
Host smart-638a3de3-612b-4494-aa37-9e0d3dcaf9a0
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3002216090 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_bit_
bash.3002216090
Directory /workspace/4.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_hw_reset.4161631823
Short name T73
Test name
Test status
Simulation time 2322593006 ps
CPU time 11.01 seconds
Started Apr 30 12:41:30 PM PDT 24
Finished Apr 30 12:41:41 PM PDT 24
Peak memory 210472 kb
Host smart-ad8f8644-fdcd-430a-9d15-164cf99908ea
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4161631823 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_hw_r
eset.4161631823
Directory /workspace/4.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_mem_rw_with_rand_reset.3877753384
Short name T446
Test name
Test status
Simulation time 3908512134 ps
CPU time 15.92 seconds
Started Apr 30 12:41:38 PM PDT 24
Finished Apr 30 12:41:54 PM PDT 24
Peak memory 218736 kb
Host smart-bad42425-deb8-4a61-848a-913f9615fade
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3877753384 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 4.rom_ctrl_csr_mem_rw_with_rand_reset.3877753384
Directory /workspace/4.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_rw.4108010307
Short name T94
Test name
Test status
Simulation time 3940103362 ps
CPU time 11.07 seconds
Started Apr 30 12:41:30 PM PDT 24
Finished Apr 30 12:41:42 PM PDT 24
Peak memory 210468 kb
Host smart-59ed6e0a-fffe-4d19-8677-31442f201a49
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4108010307 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_rw.4108010307
Directory /workspace/4.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_partial_access.558250733
Short name T418
Test name
Test status
Simulation time 1941359745 ps
CPU time 14.78 seconds
Started Apr 30 12:41:36 PM PDT 24
Finished Apr 30 12:41:51 PM PDT 24
Peak memory 210388 kb
Host smart-38d1ac5f-bb86-4a65-a93c-f71e72c914c5
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=558250733 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl
_mem_partial_access.558250733
Directory /workspace/4.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_walk.522182919
Short name T373
Test name
Test status
Simulation time 1373547757 ps
CPU time 11.8 seconds
Started Apr 30 12:41:32 PM PDT 24
Finished Apr 30 12:41:44 PM PDT 24
Peak memory 210380 kb
Host smart-29163c50-d8fe-4cbb-bf5a-d0ce83982d66
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=522182919 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_mem_walk.
522182919
Directory /workspace/4.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_passthru_mem_tl_intg_err.1226291442
Short name T398
Test name
Test status
Simulation time 44796914947 ps
CPU time 69.25 seconds
Started Apr 30 12:41:30 PM PDT 24
Finished Apr 30 12:42:39 PM PDT 24
Peak memory 210604 kb
Host smart-1b0422fd-80a3-47ad-ba6b-e4f1bc9ed430
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1226291442 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_pa
ssthru_mem_tl_intg_err.1226291442
Directory /workspace/4.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_same_csr_outstanding.2517501145
Short name T412
Test name
Test status
Simulation time 8474838750 ps
CPU time 17.2 seconds
Started Apr 30 12:41:41 PM PDT 24
Finished Apr 30 12:41:59 PM PDT 24
Peak memory 210584 kb
Host smart-1858f959-e3ee-40af-aa9f-de458a4a7e42
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2517501145 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_c
trl_same_csr_outstanding.2517501145
Directory /workspace/4.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_errors.348614426
Short name T370
Test name
Test status
Simulation time 200628101 ps
CPU time 8.73 seconds
Started Apr 30 12:41:29 PM PDT 24
Finished Apr 30 12:41:38 PM PDT 24
Peak memory 218724 kb
Host smart-34957ee3-3420-4396-b149-62a21211a0bd
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=348614426 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_tl_errors.348614426
Directory /workspace/4.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_mem_rw_with_rand_reset.778228094
Short name T378
Test name
Test status
Simulation time 7926889791 ps
CPU time 16.58 seconds
Started Apr 30 12:41:37 PM PDT 24
Finished Apr 30 12:41:54 PM PDT 24
Peak memory 218780 kb
Host smart-ec580d35-d52b-4986-aa39-a1e61026bcc3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=778228094 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 5.rom_ctrl_csr_mem_rw_with_rand_reset.778228094
Directory /workspace/5.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_rw.1435201306
Short name T87
Test name
Test status
Simulation time 2833008660 ps
CPU time 16.32 seconds
Started Apr 30 12:41:42 PM PDT 24
Finished Apr 30 12:41:59 PM PDT 24
Peak memory 210528 kb
Host smart-d8239bd3-92cb-4c34-9300-2aad410b3b1d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1435201306 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_csr_rw.1435201306
Directory /workspace/5.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_passthru_mem_tl_intg_err.3078441221
Short name T451
Test name
Test status
Simulation time 28607815427 ps
CPU time 54.5 seconds
Started Apr 30 12:41:38 PM PDT 24
Finished Apr 30 12:42:34 PM PDT 24
Peak memory 210628 kb
Host smart-1d4dd746-6750-486f-ae84-9fde37abbb6c
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3078441221 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_pa
ssthru_mem_tl_intg_err.3078441221
Directory /workspace/5.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_same_csr_outstanding.3099497703
Short name T389
Test name
Test status
Simulation time 1853859389 ps
CPU time 15.33 seconds
Started Apr 30 12:41:37 PM PDT 24
Finished Apr 30 12:41:53 PM PDT 24
Peak memory 210452 kb
Host smart-7a791a17-de16-44f5-8744-cf643302abe9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3099497703 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_c
trl_same_csr_outstanding.3099497703
Directory /workspace/5.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_errors.3644925413
Short name T433
Test name
Test status
Simulation time 254630064 ps
CPU time 8.54 seconds
Started Apr 30 12:41:40 PM PDT 24
Finished Apr 30 12:41:49 PM PDT 24
Peak memory 218684 kb
Host smart-aeb4bd28-552a-4a13-85ac-f9225182dd33
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3644925413 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_tl_errors.3644925413
Directory /workspace/5.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_intg_err.2949476899
Short name T114
Test name
Test status
Simulation time 489988207 ps
CPU time 68.56 seconds
Started Apr 30 12:41:37 PM PDT 24
Finished Apr 30 12:42:46 PM PDT 24
Peak memory 211544 kb
Host smart-a3d9843f-e62f-4d3e-953f-0dec301e4edb
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2949476899 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_tl_in
tg_err.2949476899
Directory /workspace/5.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_mem_rw_with_rand_reset.1343674099
Short name T440
Test name
Test status
Simulation time 1224980488 ps
CPU time 11.41 seconds
Started Apr 30 12:41:37 PM PDT 24
Finished Apr 30 12:41:49 PM PDT 24
Peak memory 218736 kb
Host smart-04fa7433-4093-4d74-9e33-16272ac050c5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1343674099 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 6.rom_ctrl_csr_mem_rw_with_rand_reset.1343674099
Directory /workspace/6.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_rw.966307519
Short name T431
Test name
Test status
Simulation time 125959084 ps
CPU time 4.34 seconds
Started Apr 30 12:41:38 PM PDT 24
Finished Apr 30 12:41:43 PM PDT 24
Peak memory 210508 kb
Host smart-db5f8f91-87c8-4286-ad27-eb79b45a22da
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=966307519 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_csr_rw.966307519
Directory /workspace/6.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_passthru_mem_tl_intg_err.1376820403
Short name T413
Test name
Test status
Simulation time 29477867560 ps
CPU time 34.86 seconds
Started Apr 30 12:41:41 PM PDT 24
Finished Apr 30 12:42:17 PM PDT 24
Peak memory 210808 kb
Host smart-9ca53966-934e-4e65-ae6a-6f6ea9c74686
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1376820403 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_pa
ssthru_mem_tl_intg_err.1376820403
Directory /workspace/6.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_same_csr_outstanding.328005187
Short name T432
Test name
Test status
Simulation time 1042697050 ps
CPU time 10.52 seconds
Started Apr 30 12:41:39 PM PDT 24
Finished Apr 30 12:41:50 PM PDT 24
Peak memory 210560 kb
Host smart-f2e44663-477a-4fae-9b0a-04f916d724b6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=328005187 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ct
rl_same_csr_outstanding.328005187
Directory /workspace/6.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_errors.1059921297
Short name T441
Test name
Test status
Simulation time 8122066125 ps
CPU time 19.14 seconds
Started Apr 30 12:41:37 PM PDT 24
Finished Apr 30 12:41:57 PM PDT 24
Peak memory 218748 kb
Host smart-37293054-2221-4d1c-89f6-92d22cb3545d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1059921297 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_tl_errors.1059921297
Directory /workspace/6.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_intg_err.3973416435
Short name T117
Test name
Test status
Simulation time 384152292 ps
CPU time 68.52 seconds
Started Apr 30 12:41:37 PM PDT 24
Finished Apr 30 12:42:47 PM PDT 24
Peak memory 211252 kb
Host smart-d4d9653c-fc97-4219-9e41-ad1698c6a37a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3973416435 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_tl_in
tg_err.3973416435
Directory /workspace/6.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_mem_rw_with_rand_reset.923166419
Short name T438
Test name
Test status
Simulation time 1987210460 ps
CPU time 15.06 seconds
Started Apr 30 12:41:46 PM PDT 24
Finished Apr 30 12:42:02 PM PDT 24
Peak memory 218760 kb
Host smart-196db6b4-62b8-4a46-bef4-ed4ef3dc7c6b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=923166419 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 7.rom_ctrl_csr_mem_rw_with_rand_reset.923166419
Directory /workspace/7.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_rw.996581939
Short name T404
Test name
Test status
Simulation time 789465403 ps
CPU time 8.93 seconds
Started Apr 30 12:41:44 PM PDT 24
Finished Apr 30 12:41:54 PM PDT 24
Peak memory 210484 kb
Host smart-7a8d569e-e1dd-4cd4-acb7-68431c068d0b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=996581939 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_csr_rw.996581939
Directory /workspace/7.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_passthru_mem_tl_intg_err.2491849718
Short name T69
Test name
Test status
Simulation time 7554645316 ps
CPU time 59.77 seconds
Started Apr 30 12:41:37 PM PDT 24
Finished Apr 30 12:42:38 PM PDT 24
Peak memory 210660 kb
Host smart-abf0be06-6418-494f-aa72-de495d61bea2
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2491849718 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_pa
ssthru_mem_tl_intg_err.2491849718
Directory /workspace/7.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_same_csr_outstanding.3495257805
Short name T415
Test name
Test status
Simulation time 2867977731 ps
CPU time 14.2 seconds
Started Apr 30 12:41:45 PM PDT 24
Finished Apr 30 12:42:00 PM PDT 24
Peak memory 210564 kb
Host smart-1358d561-7736-4998-bd13-5507e69c5892
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3495257805 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_c
trl_same_csr_outstanding.3495257805
Directory /workspace/7.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_errors.1069226437
Short name T417
Test name
Test status
Simulation time 1386586286 ps
CPU time 16.73 seconds
Started Apr 30 12:41:39 PM PDT 24
Finished Apr 30 12:41:57 PM PDT 24
Peak memory 218732 kb
Host smart-3a6d6253-6cdb-4473-9102-2937708a43ba
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1069226437 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_tl_errors.1069226437
Directory /workspace/7.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_intg_err.2846906295
Short name T113
Test name
Test status
Simulation time 660892435 ps
CPU time 78.22 seconds
Started Apr 30 12:41:38 PM PDT 24
Finished Apr 30 12:42:57 PM PDT 24
Peak memory 212580 kb
Host smart-73d80776-88aa-4d57-8531-5b930d014561
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2846906295 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_tl_in
tg_err.2846906295
Directory /workspace/7.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_mem_rw_with_rand_reset.84990752
Short name T364
Test name
Test status
Simulation time 1645061135 ps
CPU time 13.84 seconds
Started Apr 30 12:41:48 PM PDT 24
Finished Apr 30 12:42:02 PM PDT 24
Peak memory 218660 kb
Host smart-d3ef9122-aceb-4739-ae81-af021f267a7a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=84990752 -assert nopostproc +UVM_TESTNAME=r
om_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 8.rom_ctrl_csr_mem_rw_with_rand_reset.84990752
Directory /workspace/8.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_rw.3684646025
Short name T381
Test name
Test status
Simulation time 6968129873 ps
CPU time 14.15 seconds
Started Apr 30 12:41:46 PM PDT 24
Finished Apr 30 12:42:01 PM PDT 24
Peak memory 210828 kb
Host smart-4a2345fa-e870-4890-a655-d0273146cd1d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3684646025 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_csr_rw.3684646025
Directory /workspace/8.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_passthru_mem_tl_intg_err.2706787448
Short name T394
Test name
Test status
Simulation time 29045977833 ps
CPU time 55.18 seconds
Started Apr 30 12:41:45 PM PDT 24
Finished Apr 30 12:42:41 PM PDT 24
Peak memory 210596 kb
Host smart-c56a591f-b128-4793-8b8c-db237d10ad1d
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2706787448 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_pa
ssthru_mem_tl_intg_err.2706787448
Directory /workspace/8.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_same_csr_outstanding.4233502973
Short name T99
Test name
Test status
Simulation time 518819387 ps
CPU time 7.38 seconds
Started Apr 30 12:41:45 PM PDT 24
Finished Apr 30 12:41:53 PM PDT 24
Peak memory 210484 kb
Host smart-2f2ad0b4-5c76-41f5-bd3e-dd735b0139bf
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4233502973 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_c
trl_same_csr_outstanding.4233502973
Directory /workspace/8.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_errors.1352620285
Short name T406
Test name
Test status
Simulation time 651033603 ps
CPU time 9.93 seconds
Started Apr 30 12:41:54 PM PDT 24
Finished Apr 30 12:42:05 PM PDT 24
Peak memory 218732 kb
Host smart-209dc946-08af-48b4-84a6-257cd2434671
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1352620285 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_tl_errors.1352620285
Directory /workspace/8.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_mem_rw_with_rand_reset.3514043169
Short name T429
Test name
Test status
Simulation time 302728453 ps
CPU time 6.84 seconds
Started Apr 30 12:41:44 PM PDT 24
Finished Apr 30 12:41:51 PM PDT 24
Peak memory 218636 kb
Host smart-75aaba4c-ba35-4625-9e4e-814a33caac58
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3514043169 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 9.rom_ctrl_csr_mem_rw_with_rand_reset.3514043169
Directory /workspace/9.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_rw.294386724
Short name T77
Test name
Test status
Simulation time 1037468957 ps
CPU time 10.47 seconds
Started Apr 30 12:41:44 PM PDT 24
Finished Apr 30 12:41:55 PM PDT 24
Peak memory 210456 kb
Host smart-38e57905-323f-4b3a-8c11-aadfe5fd7ed6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=294386724 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_csr_rw.294386724
Directory /workspace/9.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_passthru_mem_tl_intg_err.1723635108
Short name T76
Test name
Test status
Simulation time 2761211916 ps
CPU time 44.05 seconds
Started Apr 30 12:41:49 PM PDT 24
Finished Apr 30 12:42:34 PM PDT 24
Peak memory 210604 kb
Host smart-339d09f1-53d7-4215-9567-a93a025f9199
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1723635108 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_pa
ssthru_mem_tl_intg_err.1723635108
Directory /workspace/9.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_same_csr_outstanding.1082818693
Short name T397
Test name
Test status
Simulation time 2505204979 ps
CPU time 11.68 seconds
Started Apr 30 12:41:47 PM PDT 24
Finished Apr 30 12:41:59 PM PDT 24
Peak memory 210540 kb
Host smart-54650407-6ffc-400c-999a-40d2d0818a79
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1082818693 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_c
trl_same_csr_outstanding.1082818693
Directory /workspace/9.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_errors.4051077000
Short name T427
Test name
Test status
Simulation time 16344538763 ps
CPU time 14.39 seconds
Started Apr 30 12:41:45 PM PDT 24
Finished Apr 30 12:42:00 PM PDT 24
Peak memory 215220 kb
Host smart-02923b86-8f40-4620-bcce-47b0c92f06ae
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4051077000 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_tl_errors.4051077000
Directory /workspace/9.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/default/0.rom_ctrl_alert_test.394538961
Short name T64
Test name
Test status
Simulation time 5794278330 ps
CPU time 12.47 seconds
Started Apr 30 12:42:08 PM PDT 24
Finished Apr 30 12:42:22 PM PDT 24
Peak memory 211452 kb
Host smart-b9811f36-f0f4-4da2-97ce-21ed1724d3d8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=394538961 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_alert_test.394538961
Directory /workspace/0.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/0.rom_ctrl_corrupt_sig_fatal_chk.874997144
Short name T41
Test name
Test status
Simulation time 195326366122 ps
CPU time 274.16 seconds
Started Apr 30 12:42:08 PM PDT 24
Finished Apr 30 12:46:43 PM PDT 24
Peak memory 237008 kb
Host smart-55cae8e1-6ea3-46b2-b058-b947c0935013
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=874997144 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_co
rrupt_sig_fatal_chk.874997144
Directory /workspace/0.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/0.rom_ctrl_kmac_err_chk.2784530700
Short name T245
Test name
Test status
Simulation time 2595386999 ps
CPU time 22.24 seconds
Started Apr 30 12:42:06 PM PDT 24
Finished Apr 30 12:42:30 PM PDT 24
Peak memory 212196 kb
Host smart-b5614c48-2929-4415-af1f-0c7e915a5c1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2784530700 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_kmac_err_chk.2784530700
Directory /workspace/0.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/0.rom_ctrl_max_throughput_chk.2173636067
Short name T167
Test name
Test status
Simulation time 1064733252 ps
CPU time 11.44 seconds
Started Apr 30 12:42:10 PM PDT 24
Finished Apr 30 12:42:22 PM PDT 24
Peak memory 211260 kb
Host smart-93764625-b823-4506-b2f6-6734d7fd20bc
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2173636067 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_max_throughput_chk.2173636067
Directory /workspace/0.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/0.rom_ctrl_sec_cm.3277003719
Short name T33
Test name
Test status
Simulation time 1799514844 ps
CPU time 57.56 seconds
Started Apr 30 12:42:08 PM PDT 24
Finished Apr 30 12:43:06 PM PDT 24
Peak memory 234624 kb
Host smart-11e9794b-84cf-4bb4-a27c-d0c0ec7b879a
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3277003719 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_sec_cm.3277003719
Directory /workspace/0.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/0.rom_ctrl_smoke.306715864
Short name T204
Test name
Test status
Simulation time 1945462939 ps
CPU time 13.4 seconds
Started Apr 30 12:42:09 PM PDT 24
Finished Apr 30 12:42:23 PM PDT 24
Peak memory 213164 kb
Host smart-d2d5c034-c388-482e-8cd7-62d496282862
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=306715864 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_smoke.306715864
Directory /workspace/0.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/0.rom_ctrl_stress_all.1140789139
Short name T270
Test name
Test status
Simulation time 7133246934 ps
CPU time 37.86 seconds
Started Apr 30 12:42:14 PM PDT 24
Finished Apr 30 12:42:53 PM PDT 24
Peak memory 214584 kb
Host smart-e8310c95-c67c-4af2-9b62-5432b0d7fa0a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1140789139 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 0.rom_ctrl_stress_all.1140789139
Directory /workspace/0.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/1.rom_ctrl_alert_test.2853561564
Short name T178
Test name
Test status
Simulation time 679152594 ps
CPU time 8.12 seconds
Started Apr 30 12:42:14 PM PDT 24
Finished Apr 30 12:42:23 PM PDT 24
Peak memory 211360 kb
Host smart-4f53d30e-23a6-4b95-a1d5-58d701b8237b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2853561564 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_alert_test.2853561564
Directory /workspace/1.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/1.rom_ctrl_corrupt_sig_fatal_chk.3898602129
Short name T332
Test name
Test status
Simulation time 24093096855 ps
CPU time 236.16 seconds
Started Apr 30 12:42:21 PM PDT 24
Finished Apr 30 12:46:18 PM PDT 24
Peak memory 225360 kb
Host smart-73056a35-963a-455e-a0d2-54b635ece5cb
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3898602129 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_c
orrupt_sig_fatal_chk.3898602129
Directory /workspace/1.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/1.rom_ctrl_max_throughput_chk.2003815993
Short name T235
Test name
Test status
Simulation time 969175404 ps
CPU time 8.48 seconds
Started Apr 30 12:42:12 PM PDT 24
Finished Apr 30 12:42:21 PM PDT 24
Peak memory 211344 kb
Host smart-af15baa0-d5ef-434b-8428-f88847b2138d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2003815993 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_max_throughput_chk.2003815993
Directory /workspace/1.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/1.rom_ctrl_smoke.2570206978
Short name T176
Test name
Test status
Simulation time 5098032245 ps
CPU time 35.12 seconds
Started Apr 30 12:42:06 PM PDT 24
Finished Apr 30 12:42:42 PM PDT 24
Peak memory 219564 kb
Host smart-127d1469-c23b-4094-beca-73ec4a627694
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2570206978 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_smoke.2570206978
Directory /workspace/1.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/1.rom_ctrl_stress_all.3719601039
Short name T138
Test name
Test status
Simulation time 2852004572 ps
CPU time 26.14 seconds
Started Apr 30 12:42:11 PM PDT 24
Finished Apr 30 12:42:38 PM PDT 24
Peak memory 215896 kb
Host smart-470dce68-cccb-45b2-876a-c62587ffa649
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3719601039 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 1.rom_ctrl_stress_all.3719601039
Directory /workspace/1.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/10.rom_ctrl_alert_test.1916756666
Short name T66
Test name
Test status
Simulation time 4100468634 ps
CPU time 15.53 seconds
Started Apr 30 12:42:35 PM PDT 24
Finished Apr 30 12:42:51 PM PDT 24
Peak memory 211492 kb
Host smart-2ba6df7f-c51f-425b-a881-0c8e1c7fabad
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1916756666 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_alert_test.1916756666
Directory /workspace/10.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/10.rom_ctrl_corrupt_sig_fatal_chk.80524170
Short name T272
Test name
Test status
Simulation time 30066324120 ps
CPU time 275.32 seconds
Started Apr 30 12:42:32 PM PDT 24
Finished Apr 30 12:47:07 PM PDT 24
Peak memory 225236 kb
Host smart-f9bcebc0-b635-4a3b-8d98-3685af83b6cd
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=80524170 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_
sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_co
rrupt_sig_fatal_chk.80524170
Directory /workspace/10.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/10.rom_ctrl_smoke.276307502
Short name T4
Test name
Test status
Simulation time 2216615249 ps
CPU time 17.13 seconds
Started Apr 30 12:42:31 PM PDT 24
Finished Apr 30 12:42:49 PM PDT 24
Peak memory 213684 kb
Host smart-0f31b26d-64ba-43b3-bf1c-1b0f50d1e806
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=276307502 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_smoke.276307502
Directory /workspace/10.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/10.rom_ctrl_stress_all.1690202096
Short name T11
Test name
Test status
Simulation time 1032653157 ps
CPU time 17.86 seconds
Started Apr 30 12:42:34 PM PDT 24
Finished Apr 30 12:42:53 PM PDT 24
Peak memory 219476 kb
Host smart-ea0a56d5-8c00-4623-8df7-3f9a61d67bfd
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1690202096 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 10.rom_ctrl_stress_all.1690202096
Directory /workspace/10.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/11.rom_ctrl_alert_test.2974487285
Short name T42
Test name
Test status
Simulation time 2801477366 ps
CPU time 13.2 seconds
Started Apr 30 12:42:40 PM PDT 24
Finished Apr 30 12:42:54 PM PDT 24
Peak memory 211436 kb
Host smart-d3d6f254-1429-4a65-800b-2122422d038e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2974487285 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_alert_test.2974487285
Directory /workspace/11.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/11.rom_ctrl_corrupt_sig_fatal_chk.1188290475
Short name T199
Test name
Test status
Simulation time 19757892931 ps
CPU time 154.52 seconds
Started Apr 30 12:42:38 PM PDT 24
Finished Apr 30 12:45:13 PM PDT 24
Peak memory 229412 kb
Host smart-07df119b-2c12-4e37-a8a2-60fd692fc1de
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1188290475 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_
corrupt_sig_fatal_chk.1188290475
Directory /workspace/11.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/11.rom_ctrl_kmac_err_chk.2216781128
Short name T160
Test name
Test status
Simulation time 168382414 ps
CPU time 9.44 seconds
Started Apr 30 12:42:39 PM PDT 24
Finished Apr 30 12:42:49 PM PDT 24
Peak memory 211464 kb
Host smart-7ba168b8-56d1-45e9-a8e4-2e46d5a343ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2216781128 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_kmac_err_chk.2216781128
Directory /workspace/11.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/11.rom_ctrl_max_throughput_chk.2505262029
Short name T277
Test name
Test status
Simulation time 7894207916 ps
CPU time 17.47 seconds
Started Apr 30 12:42:38 PM PDT 24
Finished Apr 30 12:42:56 PM PDT 24
Peak memory 211412 kb
Host smart-603d10e9-7878-47f8-8ffa-9cd125ebd8cb
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2505262029 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_max_throughput_chk.2505262029
Directory /workspace/11.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/11.rom_ctrl_smoke.440577315
Short name T328
Test name
Test status
Simulation time 1609718456 ps
CPU time 21.39 seconds
Started Apr 30 12:42:38 PM PDT 24
Finished Apr 30 12:43:00 PM PDT 24
Peak memory 219636 kb
Host smart-b412b66f-defb-4a5c-92fd-6a95a71c64c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=440577315 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_smoke.440577315
Directory /workspace/11.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/11.rom_ctrl_stress_all.760801155
Short name T269
Test name
Test status
Simulation time 3036898831 ps
CPU time 37.12 seconds
Started Apr 30 12:42:36 PM PDT 24
Finished Apr 30 12:43:14 PM PDT 24
Peak memory 213176 kb
Host smart-d9432576-33d9-42bb-8b66-6edac314073e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=760801155 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 11.rom_ctrl_stress_all.760801155
Directory /workspace/11.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/11.rom_ctrl_stress_all_with_rand_reset.2485916614
Short name T55
Test name
Test status
Simulation time 95827349213 ps
CPU time 921.47 seconds
Started Apr 30 12:42:37 PM PDT 24
Finished Apr 30 12:57:59 PM PDT 24
Peak memory 236052 kb
Host smart-222e5efe-7818-4cba-b109-7354d5af75a5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2485916614 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_stress_all_with_rand_reset.2485916614
Directory /workspace/11.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/12.rom_ctrl_alert_test.1518488553
Short name T136
Test name
Test status
Simulation time 168088564 ps
CPU time 5.43 seconds
Started Apr 30 12:42:36 PM PDT 24
Finished Apr 30 12:42:42 PM PDT 24
Peak memory 211332 kb
Host smart-fb56420d-825b-4ec4-aa8e-c410bbbbbca1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1518488553 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_alert_test.1518488553
Directory /workspace/12.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/12.rom_ctrl_corrupt_sig_fatal_chk.3441130360
Short name T349
Test name
Test status
Simulation time 3136423544 ps
CPU time 102.41 seconds
Started Apr 30 12:42:38 PM PDT 24
Finished Apr 30 12:44:21 PM PDT 24
Peak memory 233340 kb
Host smart-2500966b-a069-47de-9e72-a6e9b53c9ba9
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3441130360 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_
corrupt_sig_fatal_chk.3441130360
Directory /workspace/12.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/12.rom_ctrl_kmac_err_chk.1546953907
Short name T281
Test name
Test status
Simulation time 1037019560 ps
CPU time 9.19 seconds
Started Apr 30 12:42:41 PM PDT 24
Finished Apr 30 12:42:51 PM PDT 24
Peak memory 212064 kb
Host smart-d83957bb-346f-4268-8e20-45b7753fd38c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1546953907 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_kmac_err_chk.1546953907
Directory /workspace/12.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/12.rom_ctrl_max_throughput_chk.1334932141
Short name T345
Test name
Test status
Simulation time 2102902435 ps
CPU time 16.73 seconds
Started Apr 30 12:42:38 PM PDT 24
Finished Apr 30 12:42:56 PM PDT 24
Peak memory 211396 kb
Host smart-80ece33a-808a-4b84-b120-4bac51fa1d7e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1334932141 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_max_throughput_chk.1334932141
Directory /workspace/12.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/12.rom_ctrl_smoke.104034535
Short name T173
Test name
Test status
Simulation time 183619531 ps
CPU time 9.73 seconds
Started Apr 30 12:42:37 PM PDT 24
Finished Apr 30 12:42:47 PM PDT 24
Peak memory 219652 kb
Host smart-ac8ef045-cac8-416e-9e19-76c0ac7ed86c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=104034535 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_smoke.104034535
Directory /workspace/12.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/12.rom_ctrl_stress_all.3969447704
Short name T352
Test name
Test status
Simulation time 245292140 ps
CPU time 13.33 seconds
Started Apr 30 12:42:38 PM PDT 24
Finished Apr 30 12:42:52 PM PDT 24
Peak memory 212980 kb
Host smart-25bdd27e-5a68-44fb-94a7-9954936d2aa3
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3969447704 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 12.rom_ctrl_stress_all.3969447704
Directory /workspace/12.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/13.rom_ctrl_alert_test.427434602
Short name T197
Test name
Test status
Simulation time 6109004634 ps
CPU time 13.87 seconds
Started Apr 30 12:42:37 PM PDT 24
Finished Apr 30 12:42:51 PM PDT 24
Peak memory 211452 kb
Host smart-466decaf-90d7-40ee-9fc0-941a9398ba78
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=427434602 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_alert_test.427434602
Directory /workspace/13.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/13.rom_ctrl_corrupt_sig_fatal_chk.2546325257
Short name T232
Test name
Test status
Simulation time 75009554922 ps
CPU time 189.22 seconds
Started Apr 30 12:42:38 PM PDT 24
Finished Apr 30 12:45:48 PM PDT 24
Peak memory 230004 kb
Host smart-1fc9d393-a99e-4e82-a494-133e0a391c36
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2546325257 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_
corrupt_sig_fatal_chk.2546325257
Directory /workspace/13.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/13.rom_ctrl_max_throughput_chk.2526515974
Short name T267
Test name
Test status
Simulation time 100849812 ps
CPU time 5.42 seconds
Started Apr 30 12:42:36 PM PDT 24
Finished Apr 30 12:42:42 PM PDT 24
Peak memory 211376 kb
Host smart-2e7454f7-6036-4ea2-bf87-4239e7716a68
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2526515974 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_max_throughput_chk.2526515974
Directory /workspace/13.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/13.rom_ctrl_smoke.3946500641
Short name T216
Test name
Test status
Simulation time 712146538 ps
CPU time 9.88 seconds
Started Apr 30 12:42:39 PM PDT 24
Finished Apr 30 12:42:49 PM PDT 24
Peak memory 213856 kb
Host smart-16d93fc3-53b9-4c49-83cc-532248a4bf31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3946500641 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_smoke.3946500641
Directory /workspace/13.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/13.rom_ctrl_stress_all.3879791554
Short name T205
Test name
Test status
Simulation time 7491105568 ps
CPU time 41.42 seconds
Started Apr 30 12:42:36 PM PDT 24
Finished Apr 30 12:43:18 PM PDT 24
Peak memory 212788 kb
Host smart-f3a69061-ec9f-4b81-a1d7-3b0ad37bdb0f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3879791554 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 13.rom_ctrl_stress_all.3879791554
Directory /workspace/13.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/14.rom_ctrl_alert_test.568382359
Short name T37
Test name
Test status
Simulation time 1545656594 ps
CPU time 6.67 seconds
Started Apr 30 12:42:46 PM PDT 24
Finished Apr 30 12:42:53 PM PDT 24
Peak memory 211328 kb
Host smart-ad1aa76b-262c-472f-82af-2338de1e1258
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=568382359 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_alert_test.568382359
Directory /workspace/14.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/14.rom_ctrl_corrupt_sig_fatal_chk.179292129
Short name T48
Test name
Test status
Simulation time 111213693452 ps
CPU time 290.03 seconds
Started Apr 30 12:42:37 PM PDT 24
Finished Apr 30 12:47:28 PM PDT 24
Peak memory 231004 kb
Host smart-9836e736-0489-4370-8386-0d001b203123
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=179292129 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_c
orrupt_sig_fatal_chk.179292129
Directory /workspace/14.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/14.rom_ctrl_kmac_err_chk.3905647345
Short name T5
Test name
Test status
Simulation time 16182687038 ps
CPU time 33.21 seconds
Started Apr 30 12:42:42 PM PDT 24
Finished Apr 30 12:43:16 PM PDT 24
Peak memory 212200 kb
Host smart-1db1359a-6f5f-4dea-a540-597d1e658562
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3905647345 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_kmac_err_chk.3905647345
Directory /workspace/14.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/14.rom_ctrl_max_throughput_chk.1510779896
Short name T142
Test name
Test status
Simulation time 544949693 ps
CPU time 8.86 seconds
Started Apr 30 12:42:36 PM PDT 24
Finished Apr 30 12:42:45 PM PDT 24
Peak memory 211308 kb
Host smart-bd6ef6ee-b0f8-4ad7-82b7-3ba298d65259
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1510779896 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_max_throughput_chk.1510779896
Directory /workspace/14.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/14.rom_ctrl_smoke.587497773
Short name T231
Test name
Test status
Simulation time 368101748 ps
CPU time 9.7 seconds
Started Apr 30 12:42:41 PM PDT 24
Finished Apr 30 12:42:51 PM PDT 24
Peak memory 219536 kb
Host smart-541bfc93-3998-4e6c-8c79-57f856b9664f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=587497773 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_smoke.587497773
Directory /workspace/14.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/14.rom_ctrl_stress_all.589240348
Short name T320
Test name
Test status
Simulation time 3160820151 ps
CPU time 11.74 seconds
Started Apr 30 12:42:37 PM PDT 24
Finished Apr 30 12:42:49 PM PDT 24
Peak memory 212140 kb
Host smart-30fb02de-a3f0-45d3-8030-3f9b673a5e8a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=589240348 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 14.rom_ctrl_stress_all.589240348
Directory /workspace/14.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/15.rom_ctrl_alert_test.1244261747
Short name T63
Test name
Test status
Simulation time 2645333996 ps
CPU time 8.55 seconds
Started Apr 30 12:42:48 PM PDT 24
Finished Apr 30 12:42:57 PM PDT 24
Peak memory 211444 kb
Host smart-050d88fa-9acc-40ac-98ba-247d3637051a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1244261747 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_alert_test.1244261747
Directory /workspace/15.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/15.rom_ctrl_corrupt_sig_fatal_chk.3265397256
Short name T296
Test name
Test status
Simulation time 4973188131 ps
CPU time 119.69 seconds
Started Apr 30 12:42:55 PM PDT 24
Finished Apr 30 12:44:56 PM PDT 24
Peak memory 219692 kb
Host smart-079eb246-fa9d-49b7-96ec-f90f6333d480
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3265397256 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_
corrupt_sig_fatal_chk.3265397256
Directory /workspace/15.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/15.rom_ctrl_kmac_err_chk.2927338589
Short name T278
Test name
Test status
Simulation time 7161118184 ps
CPU time 20.11 seconds
Started Apr 30 12:42:50 PM PDT 24
Finished Apr 30 12:43:10 PM PDT 24
Peak memory 212688 kb
Host smart-bd2b45d6-15ba-4ab3-ba57-c3d80b3092f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2927338589 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_kmac_err_chk.2927338589
Directory /workspace/15.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/15.rom_ctrl_max_throughput_chk.3239626850
Short name T243
Test name
Test status
Simulation time 1397414841 ps
CPU time 7.28 seconds
Started Apr 30 12:42:47 PM PDT 24
Finished Apr 30 12:42:54 PM PDT 24
Peak memory 211332 kb
Host smart-db64337f-e6b4-48e5-a508-ace63633eb53
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3239626850 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_max_throughput_chk.3239626850
Directory /workspace/15.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/15.rom_ctrl_smoke.1377322772
Short name T358
Test name
Test status
Simulation time 71035495000 ps
CPU time 33.55 seconds
Started Apr 30 12:42:43 PM PDT 24
Finished Apr 30 12:43:17 PM PDT 24
Peak memory 214412 kb
Host smart-4d29c8a8-c64e-4f00-9c0c-d8a2d4edf080
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1377322772 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_smoke.1377322772
Directory /workspace/15.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/15.rom_ctrl_stress_all.3082496229
Short name T212
Test name
Test status
Simulation time 8261316093 ps
CPU time 36.27 seconds
Started Apr 30 12:43:00 PM PDT 24
Finished Apr 30 12:43:37 PM PDT 24
Peak memory 214408 kb
Host smart-3bc2182a-784b-48a3-8373-663ccb0e2356
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3082496229 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 15.rom_ctrl_stress_all.3082496229
Directory /workspace/15.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/15.rom_ctrl_stress_all_with_rand_reset.493569811
Short name T310
Test name
Test status
Simulation time 29500507857 ps
CPU time 2410.78 seconds
Started Apr 30 12:42:50 PM PDT 24
Finished Apr 30 01:23:01 PM PDT 24
Peak memory 236116 kb
Host smart-28488ec9-45e2-4b35-96dd-07c9f0dd682a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=493569811 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_stress_all_with_rand_reset.493569811
Directory /workspace/15.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/16.rom_ctrl_alert_test.1894290393
Short name T179
Test name
Test status
Simulation time 1558237504 ps
CPU time 12.72 seconds
Started Apr 30 12:42:46 PM PDT 24
Finished Apr 30 12:42:59 PM PDT 24
Peak memory 211360 kb
Host smart-3320a383-dd3b-4cd7-acd9-d6673744bae3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1894290393 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_alert_test.1894290393
Directory /workspace/16.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/16.rom_ctrl_corrupt_sig_fatal_chk.1927679277
Short name T279
Test name
Test status
Simulation time 79476409430 ps
CPU time 377.61 seconds
Started Apr 30 12:42:43 PM PDT 24
Finished Apr 30 12:49:01 PM PDT 24
Peak memory 225308 kb
Host smart-67a44aa2-25eb-4161-bd4e-4d233db62580
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1927679277 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_
corrupt_sig_fatal_chk.1927679277
Directory /workspace/16.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/16.rom_ctrl_kmac_err_chk.973105645
Short name T208
Test name
Test status
Simulation time 1535968874 ps
CPU time 18.31 seconds
Started Apr 30 12:42:54 PM PDT 24
Finished Apr 30 12:43:13 PM PDT 24
Peak memory 212096 kb
Host smart-80104ae6-be89-45cf-b6e0-2678a1112779
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=973105645 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_kmac_err_chk.973105645
Directory /workspace/16.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/16.rom_ctrl_max_throughput_chk.3022638018
Short name T155
Test name
Test status
Simulation time 2070120076 ps
CPU time 11.39 seconds
Started Apr 30 12:42:47 PM PDT 24
Finished Apr 30 12:42:59 PM PDT 24
Peak memory 211324 kb
Host smart-5f5bb177-b2d0-46d9-8c51-ab4fbbfcc808
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3022638018 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_max_throughput_chk.3022638018
Directory /workspace/16.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/16.rom_ctrl_smoke.1929861296
Short name T159
Test name
Test status
Simulation time 8269689375 ps
CPU time 21.88 seconds
Started Apr 30 12:42:51 PM PDT 24
Finished Apr 30 12:43:13 PM PDT 24
Peak memory 213932 kb
Host smart-40076eec-3f9c-42f9-94e2-d3b8a232c636
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1929861296 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_smoke.1929861296
Directory /workspace/16.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/16.rom_ctrl_stress_all.4123311065
Short name T132
Test name
Test status
Simulation time 3218541252 ps
CPU time 38.37 seconds
Started Apr 30 12:42:48 PM PDT 24
Finished Apr 30 12:43:27 PM PDT 24
Peak memory 219564 kb
Host smart-a47c30d4-29bd-422e-8761-107dee7e1555
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4123311065 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 16.rom_ctrl_stress_all.4123311065
Directory /workspace/16.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/17.rom_ctrl_alert_test.1668944545
Short name T135
Test name
Test status
Simulation time 6046296203 ps
CPU time 13.04 seconds
Started Apr 30 12:42:49 PM PDT 24
Finished Apr 30 12:43:02 PM PDT 24
Peak memory 211532 kb
Host smart-11ce5e3c-dbfd-4b27-ade1-1642b8cba13c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1668944545 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_alert_test.1668944545
Directory /workspace/17.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/17.rom_ctrl_kmac_err_chk.4177542701
Short name T276
Test name
Test status
Simulation time 498352934 ps
CPU time 11.04 seconds
Started Apr 30 12:42:47 PM PDT 24
Finished Apr 30 12:42:59 PM PDT 24
Peak memory 212000 kb
Host smart-b3d4938f-ee63-4cdf-a937-604002c9c44d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4177542701 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_kmac_err_chk.4177542701
Directory /workspace/17.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/17.rom_ctrl_max_throughput_chk.1871279118
Short name T171
Test name
Test status
Simulation time 539934622 ps
CPU time 5.61 seconds
Started Apr 30 12:42:44 PM PDT 24
Finished Apr 30 12:42:50 PM PDT 24
Peak memory 211340 kb
Host smart-293ca071-ecf4-4edd-ae49-1788e0eecc8f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1871279118 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_max_throughput_chk.1871279118
Directory /workspace/17.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/17.rom_ctrl_smoke.3993560662
Short name T363
Test name
Test status
Simulation time 428984381 ps
CPU time 9.92 seconds
Started Apr 30 12:42:47 PM PDT 24
Finished Apr 30 12:42:58 PM PDT 24
Peak memory 219604 kb
Host smart-c8f70341-e821-47ad-a50f-832c8b2b1a9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3993560662 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_smoke.3993560662
Directory /workspace/17.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/17.rom_ctrl_stress_all.1667630799
Short name T174
Test name
Test status
Simulation time 36151783396 ps
CPU time 50.22 seconds
Started Apr 30 12:42:44 PM PDT 24
Finished Apr 30 12:43:35 PM PDT 24
Peak memory 219576 kb
Host smart-fb5820ff-db39-4b82-85fa-7cdef304b7ed
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1667630799 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 17.rom_ctrl_stress_all.1667630799
Directory /workspace/17.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/18.rom_ctrl_alert_test.1400437734
Short name T194
Test name
Test status
Simulation time 765378636 ps
CPU time 5.61 seconds
Started Apr 30 12:43:01 PM PDT 24
Finished Apr 30 12:43:07 PM PDT 24
Peak memory 211340 kb
Host smart-5786ea65-7cad-414f-8934-33f5c22697af
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1400437734 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_alert_test.1400437734
Directory /workspace/18.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/18.rom_ctrl_corrupt_sig_fatal_chk.611220978
Short name T325
Test name
Test status
Simulation time 12132908172 ps
CPU time 170.46 seconds
Started Apr 30 12:42:57 PM PDT 24
Finished Apr 30 12:45:48 PM PDT 24
Peak memory 213676 kb
Host smart-048a8269-b55e-48bc-88da-8bdb9481cb80
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=611220978 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_c
orrupt_sig_fatal_chk.611220978
Directory /workspace/18.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/18.rom_ctrl_kmac_err_chk.1638803797
Short name T257
Test name
Test status
Simulation time 1726498713 ps
CPU time 19.2 seconds
Started Apr 30 12:42:54 PM PDT 24
Finished Apr 30 12:43:14 PM PDT 24
Peak memory 212084 kb
Host smart-98bdc1a8-27f2-49cd-ae1f-0bb8dff22529
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1638803797 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_kmac_err_chk.1638803797
Directory /workspace/18.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/18.rom_ctrl_max_throughput_chk.3675741001
Short name T200
Test name
Test status
Simulation time 755486358 ps
CPU time 10.15 seconds
Started Apr 30 12:42:48 PM PDT 24
Finished Apr 30 12:42:59 PM PDT 24
Peak memory 210728 kb
Host smart-67b19d19-d67c-4039-a246-880bbc1c0072
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3675741001 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_max_throughput_chk.3675741001
Directory /workspace/18.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/18.rom_ctrl_smoke.779746161
Short name T348
Test name
Test status
Simulation time 4459323937 ps
CPU time 16.32 seconds
Started Apr 30 12:42:50 PM PDT 24
Finished Apr 30 12:43:07 PM PDT 24
Peak memory 213684 kb
Host smart-c55e2841-7843-4cdb-8efa-4803df702ff2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=779746161 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_smoke.779746161
Directory /workspace/18.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/18.rom_ctrl_stress_all.382453243
Short name T184
Test name
Test status
Simulation time 1958562435 ps
CPU time 29.93 seconds
Started Apr 30 12:42:50 PM PDT 24
Finished Apr 30 12:43:21 PM PDT 24
Peak memory 219476 kb
Host smart-ffd3c6d1-749a-454a-86ec-d6c8f5b0a385
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=382453243 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 18.rom_ctrl_stress_all.382453243
Directory /workspace/18.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/19.rom_ctrl_alert_test.3011477922
Short name T206
Test name
Test status
Simulation time 3433060759 ps
CPU time 9.87 seconds
Started Apr 30 12:42:54 PM PDT 24
Finished Apr 30 12:43:04 PM PDT 24
Peak memory 211492 kb
Host smart-75cf9477-ddb0-4f92-b877-38b72124346e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3011477922 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_alert_test.3011477922
Directory /workspace/19.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/19.rom_ctrl_corrupt_sig_fatal_chk.2944320145
Short name T326
Test name
Test status
Simulation time 91524393896 ps
CPU time 214.42 seconds
Started Apr 30 12:42:57 PM PDT 24
Finished Apr 30 12:46:32 PM PDT 24
Peak memory 228332 kb
Host smart-6cd416fd-ef78-4291-a98f-2ff6da55cdfe
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2944320145 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_
corrupt_sig_fatal_chk.2944320145
Directory /workspace/19.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/19.rom_ctrl_kmac_err_chk.1325010704
Short name T341
Test name
Test status
Simulation time 49154408963 ps
CPU time 25.19 seconds
Started Apr 30 12:42:54 PM PDT 24
Finished Apr 30 12:43:19 PM PDT 24
Peak memory 212328 kb
Host smart-1cabd99f-3098-4dd3-ae71-54ec11bef428
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1325010704 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_kmac_err_chk.1325010704
Directory /workspace/19.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/19.rom_ctrl_max_throughput_chk.2602748939
Short name T357
Test name
Test status
Simulation time 360982335 ps
CPU time 7.89 seconds
Started Apr 30 12:42:55 PM PDT 24
Finished Apr 30 12:43:04 PM PDT 24
Peak memory 211388 kb
Host smart-f3be1c5d-a310-44f1-99a8-d71117deda5d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2602748939 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_max_throughput_chk.2602748939
Directory /workspace/19.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/19.rom_ctrl_smoke.4241637151
Short name T210
Test name
Test status
Simulation time 19711082185 ps
CPU time 37.08 seconds
Started Apr 30 12:42:54 PM PDT 24
Finished Apr 30 12:43:32 PM PDT 24
Peak memory 219644 kb
Host smart-830a0825-e378-4906-83c6-fcfe7b23d4f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4241637151 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_smoke.4241637151
Directory /workspace/19.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/19.rom_ctrl_stress_all.1695764452
Short name T78
Test name
Test status
Simulation time 4148715893 ps
CPU time 23.23 seconds
Started Apr 30 12:42:57 PM PDT 24
Finished Apr 30 12:43:20 PM PDT 24
Peak memory 212164 kb
Host smart-e98dd7ee-1ce6-4c25-8b2d-e6728421dde0
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1695764452 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 19.rom_ctrl_stress_all.1695764452
Directory /workspace/19.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/2.rom_ctrl_alert_test.650301908
Short name T151
Test name
Test status
Simulation time 3747131570 ps
CPU time 14.85 seconds
Started Apr 30 12:42:13 PM PDT 24
Finished Apr 30 12:42:29 PM PDT 24
Peak memory 211496 kb
Host smart-a1008ff6-3c2a-49b6-ad64-d3fb18fe894d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=650301908 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_alert_test.650301908
Directory /workspace/2.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/2.rom_ctrl_corrupt_sig_fatal_chk.4129635092
Short name T30
Test name
Test status
Simulation time 4778727132 ps
CPU time 149.68 seconds
Started Apr 30 12:42:13 PM PDT 24
Finished Apr 30 12:44:44 PM PDT 24
Peak memory 236988 kb
Host smart-cb7a53f1-d072-40ab-9001-4c9c2451eeb0
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4129635092 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_c
orrupt_sig_fatal_chk.4129635092
Directory /workspace/2.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/2.rom_ctrl_kmac_err_chk.2450526076
Short name T263
Test name
Test status
Simulation time 25613829918 ps
CPU time 32.44 seconds
Started Apr 30 12:42:17 PM PDT 24
Finished Apr 30 12:42:50 PM PDT 24
Peak memory 212196 kb
Host smart-d9bf3308-fb42-4a64-a98c-b20c44193073
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2450526076 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_kmac_err_chk.2450526076
Directory /workspace/2.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/2.rom_ctrl_max_throughput_chk.780072123
Short name T110
Test name
Test status
Simulation time 2154931134 ps
CPU time 8.9 seconds
Started Apr 30 12:42:13 PM PDT 24
Finished Apr 30 12:42:23 PM PDT 24
Peak memory 211392 kb
Host smart-7dcfe73f-832f-4d52-8330-6eeb709427c9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=780072123 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_max_throughput_chk.780072123
Directory /workspace/2.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/2.rom_ctrl_sec_cm.3783486407
Short name T35
Test name
Test status
Simulation time 1307316452 ps
CPU time 106.58 seconds
Started Apr 30 12:42:15 PM PDT 24
Finished Apr 30 12:44:02 PM PDT 24
Peak memory 230716 kb
Host smart-e294e85c-db00-4f18-8996-1f7c87db5fb6
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3783486407 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_sec_cm.3783486407
Directory /workspace/2.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/2.rom_ctrl_smoke.275266684
Short name T39
Test name
Test status
Simulation time 10826336698 ps
CPU time 26.81 seconds
Started Apr 30 12:42:13 PM PDT 24
Finished Apr 30 12:42:40 PM PDT 24
Peak memory 213976 kb
Host smart-de4bb76e-d3ad-4a7f-b579-339f041d324e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=275266684 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_smoke.275266684
Directory /workspace/2.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/2.rom_ctrl_stress_all.1582150245
Short name T240
Test name
Test status
Simulation time 16866303297 ps
CPU time 69.78 seconds
Started Apr 30 12:42:17 PM PDT 24
Finished Apr 30 12:43:27 PM PDT 24
Peak memory 219528 kb
Host smart-23da65f4-6d02-4b30-b712-e52d5560893b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1582150245 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 2.rom_ctrl_stress_all.1582150245
Directory /workspace/2.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/2.rom_ctrl_stress_all_with_rand_reset.1278548257
Short name T17
Test name
Test status
Simulation time 105662013817 ps
CPU time 2090.77 seconds
Started Apr 30 12:42:13 PM PDT 24
Finished Apr 30 01:17:05 PM PDT 24
Peak memory 237384 kb
Host smart-577902e0-3848-4b46-b452-1e8ec04f3e7d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1278548257 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_stress_all_with_rand_reset.1278548257
Directory /workspace/2.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.rom_ctrl_corrupt_sig_fatal_chk.3636770248
Short name T242
Test name
Test status
Simulation time 20659396086 ps
CPU time 144.89 seconds
Started Apr 30 12:42:55 PM PDT 24
Finished Apr 30 12:45:21 PM PDT 24
Peak memory 232944 kb
Host smart-30dc6b89-a67d-471c-949e-75774e075f5a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3636770248 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_
corrupt_sig_fatal_chk.3636770248
Directory /workspace/20.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/20.rom_ctrl_kmac_err_chk.3560555443
Short name T191
Test name
Test status
Simulation time 2741419404 ps
CPU time 13.29 seconds
Started Apr 30 12:42:55 PM PDT 24
Finished Apr 30 12:43:09 PM PDT 24
Peak memory 212356 kb
Host smart-9fddd9f6-8250-4a59-b66c-9597cdbf5c21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3560555443 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_kmac_err_chk.3560555443
Directory /workspace/20.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/20.rom_ctrl_max_throughput_chk.3403504875
Short name T330
Test name
Test status
Simulation time 1718102077 ps
CPU time 14.88 seconds
Started Apr 30 12:42:54 PM PDT 24
Finished Apr 30 12:43:09 PM PDT 24
Peak memory 211344 kb
Host smart-a7b9db21-bf95-412f-a8f1-4a4cb7746da8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3403504875 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_max_throughput_chk.3403504875
Directory /workspace/20.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/20.rom_ctrl_smoke.2537870494
Short name T189
Test name
Test status
Simulation time 356974532 ps
CPU time 10.2 seconds
Started Apr 30 12:42:56 PM PDT 24
Finished Apr 30 12:43:07 PM PDT 24
Peak memory 218944 kb
Host smart-d963356a-5634-4a25-b122-a968c972cbb2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2537870494 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_smoke.2537870494
Directory /workspace/20.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/20.rom_ctrl_stress_all.4134978156
Short name T336
Test name
Test status
Simulation time 9134151623 ps
CPU time 39.85 seconds
Started Apr 30 12:42:56 PM PDT 24
Finished Apr 30 12:43:36 PM PDT 24
Peak memory 216432 kb
Host smart-e1e95586-1f74-46df-b810-37372fc34705
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4134978156 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 20.rom_ctrl_stress_all.4134978156
Directory /workspace/20.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/21.rom_ctrl_alert_test.4222266151
Short name T65
Test name
Test status
Simulation time 489868841 ps
CPU time 4.2 seconds
Started Apr 30 12:43:10 PM PDT 24
Finished Apr 30 12:43:14 PM PDT 24
Peak memory 211364 kb
Host smart-e0927612-3172-4b60-9f62-d38d32e9e1e7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4222266151 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_alert_test.4222266151
Directory /workspace/21.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/21.rom_ctrl_kmac_err_chk.3318573679
Short name T327
Test name
Test status
Simulation time 6817682791 ps
CPU time 30.06 seconds
Started Apr 30 12:43:06 PM PDT 24
Finished Apr 30 12:43:37 PM PDT 24
Peak memory 212772 kb
Host smart-be71ec6a-ee37-459b-92f9-9ba4ddb0a8e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3318573679 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_kmac_err_chk.3318573679
Directory /workspace/21.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/21.rom_ctrl_max_throughput_chk.1063199881
Short name T350
Test name
Test status
Simulation time 8213214275 ps
CPU time 15.12 seconds
Started Apr 30 12:42:53 PM PDT 24
Finished Apr 30 12:43:08 PM PDT 24
Peak memory 211388 kb
Host smart-2229a3d6-d75c-48a6-ae45-d6d3c43629b9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1063199881 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_max_throughput_chk.1063199881
Directory /workspace/21.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/21.rom_ctrl_smoke.1352294356
Short name T300
Test name
Test status
Simulation time 633835376 ps
CPU time 14.55 seconds
Started Apr 30 12:43:00 PM PDT 24
Finished Apr 30 12:43:15 PM PDT 24
Peak memory 219564 kb
Host smart-3065cf1b-912e-4d8d-bd88-2e8b852538ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1352294356 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_smoke.1352294356
Directory /workspace/21.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/21.rom_ctrl_stress_all.4099788046
Short name T254
Test name
Test status
Simulation time 296270180 ps
CPU time 18.91 seconds
Started Apr 30 12:42:58 PM PDT 24
Finished Apr 30 12:43:18 PM PDT 24
Peak memory 212776 kb
Host smart-bdafe518-1705-452b-84e4-4ddbb5c8d4a1
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4099788046 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 21.rom_ctrl_stress_all.4099788046
Directory /workspace/21.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/22.rom_ctrl_alert_test.966173333
Short name T190
Test name
Test status
Simulation time 85456320 ps
CPU time 4.36 seconds
Started Apr 30 12:43:08 PM PDT 24
Finished Apr 30 12:43:13 PM PDT 24
Peak memory 211376 kb
Host smart-b1716de4-2d4f-45f6-9520-680e60d83d7a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=966173333 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_alert_test.966173333
Directory /workspace/22.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/22.rom_ctrl_corrupt_sig_fatal_chk.2880851363
Short name T24
Test name
Test status
Simulation time 282823736340 ps
CPU time 163.67 seconds
Started Apr 30 12:43:05 PM PDT 24
Finished Apr 30 12:45:49 PM PDT 24
Peak memory 228584 kb
Host smart-a2bb0657-fb32-422c-b2b6-a433c62bde6f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2880851363 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_
corrupt_sig_fatal_chk.2880851363
Directory /workspace/22.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/22.rom_ctrl_kmac_err_chk.841317987
Short name T23
Test name
Test status
Simulation time 3261125513 ps
CPU time 13.92 seconds
Started Apr 30 12:43:08 PM PDT 24
Finished Apr 30 12:43:22 PM PDT 24
Peak memory 212092 kb
Host smart-b441f846-ed46-478f-bc79-64888bd137cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=841317987 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_kmac_err_chk.841317987
Directory /workspace/22.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/22.rom_ctrl_max_throughput_chk.2505173928
Short name T139
Test name
Test status
Simulation time 388695223 ps
CPU time 5.78 seconds
Started Apr 30 12:43:08 PM PDT 24
Finished Apr 30 12:43:14 PM PDT 24
Peak memory 211364 kb
Host smart-6904c408-c74f-4f10-8ca9-ae6f9e2ce3b3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2505173928 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_max_throughput_chk.2505173928
Directory /workspace/22.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/22.rom_ctrl_smoke.2991070289
Short name T250
Test name
Test status
Simulation time 7203457052 ps
CPU time 22.96 seconds
Started Apr 30 12:43:07 PM PDT 24
Finished Apr 30 12:43:31 PM PDT 24
Peak memory 213932 kb
Host smart-d23af389-808c-4bce-b47c-ad872c6c03ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2991070289 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_smoke.2991070289
Directory /workspace/22.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/22.rom_ctrl_stress_all.3767426215
Short name T361
Test name
Test status
Simulation time 96227074776 ps
CPU time 122.5 seconds
Started Apr 30 12:43:06 PM PDT 24
Finished Apr 30 12:45:09 PM PDT 24
Peak memory 219576 kb
Host smart-8789e7ca-4823-4283-8550-44eb6d3a78ca
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3767426215 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 22.rom_ctrl_stress_all.3767426215
Directory /workspace/22.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/23.rom_ctrl_alert_test.1122180585
Short name T314
Test name
Test status
Simulation time 854754388 ps
CPU time 9.23 seconds
Started Apr 30 12:43:09 PM PDT 24
Finished Apr 30 12:43:19 PM PDT 24
Peak memory 211380 kb
Host smart-1b10d019-b80c-4414-a553-63a61022a2e6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1122180585 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_alert_test.1122180585
Directory /workspace/23.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/23.rom_ctrl_corrupt_sig_fatal_chk.312768971
Short name T123
Test name
Test status
Simulation time 23366909860 ps
CPU time 228.46 seconds
Started Apr 30 12:43:06 PM PDT 24
Finished Apr 30 12:46:55 PM PDT 24
Peak memory 231044 kb
Host smart-1692dfbc-ad81-45c0-83e4-133408f9f310
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=312768971 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_c
orrupt_sig_fatal_chk.312768971
Directory /workspace/23.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/23.rom_ctrl_kmac_err_chk.256412
Short name T344
Test name
Test status
Simulation time 19489390618 ps
CPU time 30.22 seconds
Started Apr 30 12:43:08 PM PDT 24
Finished Apr 30 12:43:38 PM PDT 24
Peak memory 212216 kb
Host smart-1f364c33-bcf6-4fe2-8092-2581af8d943b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=256412 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_kmac_err_chk.256412
Directory /workspace/23.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/23.rom_ctrl_max_throughput_chk.3904286275
Short name T334
Test name
Test status
Simulation time 2469240288 ps
CPU time 16.36 seconds
Started Apr 30 12:43:08 PM PDT 24
Finished Apr 30 12:43:25 PM PDT 24
Peak memory 211444 kb
Host smart-cd0744d1-e286-4649-81c3-c491261bbb83
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3904286275 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_max_throughput_chk.3904286275
Directory /workspace/23.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/23.rom_ctrl_smoke.1464498515
Short name T10
Test name
Test status
Simulation time 44120711353 ps
CPU time 39.05 seconds
Started Apr 30 12:43:06 PM PDT 24
Finished Apr 30 12:43:45 PM PDT 24
Peak memory 214612 kb
Host smart-ef45ac18-8148-4661-ad89-b851974fd8e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1464498515 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_smoke.1464498515
Directory /workspace/23.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/23.rom_ctrl_stress_all.461068466
Short name T214
Test name
Test status
Simulation time 18397547312 ps
CPU time 49.14 seconds
Started Apr 30 12:43:09 PM PDT 24
Finished Apr 30 12:43:59 PM PDT 24
Peak memory 219584 kb
Host smart-8ad7e1d3-947e-4ae0-bf50-0eec7410efe0
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=461068466 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 23.rom_ctrl_stress_all.461068466
Directory /workspace/23.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/23.rom_ctrl_stress_all_with_rand_reset.908568056
Short name T54
Test name
Test status
Simulation time 154681276679 ps
CPU time 7557.97 seconds
Started Apr 30 12:43:08 PM PDT 24
Finished Apr 30 02:49:08 PM PDT 24
Peak memory 234080 kb
Host smart-8748fb93-4069-41ad-aee1-f39cde8ca2b0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=908568056 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_stress_all_with_rand_reset.908568056
Directory /workspace/23.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/24.rom_ctrl_alert_test.3946241615
Short name T261
Test name
Test status
Simulation time 2064980836 ps
CPU time 16.38 seconds
Started Apr 30 12:43:09 PM PDT 24
Finished Apr 30 12:43:26 PM PDT 24
Peak memory 211444 kb
Host smart-94741c34-6386-4514-ad6a-d6d6d36631cc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3946241615 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_alert_test.3946241615
Directory /workspace/24.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/24.rom_ctrl_corrupt_sig_fatal_chk.1603579550
Short name T46
Test name
Test status
Simulation time 61421780000 ps
CPU time 160.24 seconds
Started Apr 30 12:43:07 PM PDT 24
Finished Apr 30 12:45:48 PM PDT 24
Peak memory 236856 kb
Host smart-7f06f524-419f-4f45-acfe-ebeae406d792
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1603579550 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_
corrupt_sig_fatal_chk.1603579550
Directory /workspace/24.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/24.rom_ctrl_kmac_err_chk.4101943961
Short name T21
Test name
Test status
Simulation time 173571267 ps
CPU time 9.22 seconds
Started Apr 30 12:43:06 PM PDT 24
Finished Apr 30 12:43:15 PM PDT 24
Peak memory 212168 kb
Host smart-f3d54118-7e7b-49dc-835f-879d42905c30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4101943961 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_kmac_err_chk.4101943961
Directory /workspace/24.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/24.rom_ctrl_max_throughput_chk.3647897141
Short name T157
Test name
Test status
Simulation time 358128712 ps
CPU time 7.57 seconds
Started Apr 30 12:43:07 PM PDT 24
Finished Apr 30 12:43:15 PM PDT 24
Peak memory 211388 kb
Host smart-5e5e26ba-30df-47ff-89fb-9ba957a07be9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3647897141 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_max_throughput_chk.3647897141
Directory /workspace/24.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/24.rom_ctrl_stress_all.3434546635
Short name T247
Test name
Test status
Simulation time 462508161 ps
CPU time 25.16 seconds
Started Apr 30 12:43:09 PM PDT 24
Finished Apr 30 12:43:34 PM PDT 24
Peak memory 215384 kb
Host smart-b879c5a4-5533-4599-b011-980732a0e73e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3434546635 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 24.rom_ctrl_stress_all.3434546635
Directory /workspace/24.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/25.rom_ctrl_alert_test.3397811689
Short name T295
Test name
Test status
Simulation time 1277902326 ps
CPU time 11.5 seconds
Started Apr 30 12:43:15 PM PDT 24
Finished Apr 30 12:43:27 PM PDT 24
Peak memory 211480 kb
Host smart-1219f315-e8cf-4fff-a5e2-128777cc42f4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3397811689 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_alert_test.3397811689
Directory /workspace/25.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/25.rom_ctrl_corrupt_sig_fatal_chk.1724238439
Short name T265
Test name
Test status
Simulation time 2559254280 ps
CPU time 121.88 seconds
Started Apr 30 12:43:07 PM PDT 24
Finished Apr 30 12:45:09 PM PDT 24
Peak memory 240736 kb
Host smart-b0ad9110-7eff-4be2-8b77-2f103aee22f7
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1724238439 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_
corrupt_sig_fatal_chk.1724238439
Directory /workspace/25.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/25.rom_ctrl_kmac_err_chk.4217461929
Short name T207
Test name
Test status
Simulation time 2833516860 ps
CPU time 26.53 seconds
Started Apr 30 12:43:07 PM PDT 24
Finished Apr 30 12:43:34 PM PDT 24
Peak memory 211992 kb
Host smart-22f184bd-6f9c-497c-a009-084f7d7e2453
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4217461929 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_kmac_err_chk.4217461929
Directory /workspace/25.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/25.rom_ctrl_max_throughput_chk.2663371277
Short name T238
Test name
Test status
Simulation time 2446864639 ps
CPU time 9.09 seconds
Started Apr 30 12:43:08 PM PDT 24
Finished Apr 30 12:43:18 PM PDT 24
Peak memory 211428 kb
Host smart-b4b3e9bb-5cc3-440b-9a75-0321e9980442
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2663371277 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_max_throughput_chk.2663371277
Directory /workspace/25.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/25.rom_ctrl_smoke.2513125495
Short name T164
Test name
Test status
Simulation time 6156862491 ps
CPU time 17.23 seconds
Started Apr 30 12:43:07 PM PDT 24
Finished Apr 30 12:43:25 PM PDT 24
Peak memory 214628 kb
Host smart-31f29310-cee2-44bc-8d77-c759f9f0fa88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2513125495 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_smoke.2513125495
Directory /workspace/25.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/25.rom_ctrl_stress_all.1404476391
Short name T80
Test name
Test status
Simulation time 19430604652 ps
CPU time 53.47 seconds
Started Apr 30 12:43:08 PM PDT 24
Finished Apr 30 12:44:02 PM PDT 24
Peak memory 216948 kb
Host smart-841e9439-76bc-41f4-b870-2895fcfa917b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1404476391 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 25.rom_ctrl_stress_all.1404476391
Directory /workspace/25.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/26.rom_ctrl_alert_test.3440932171
Short name T298
Test name
Test status
Simulation time 603692176 ps
CPU time 8.09 seconds
Started Apr 30 12:43:17 PM PDT 24
Finished Apr 30 12:43:26 PM PDT 24
Peak memory 211424 kb
Host smart-40030b01-6c46-4183-8f13-d2d8ab07bcc5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3440932171 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_alert_test.3440932171
Directory /workspace/26.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/26.rom_ctrl_corrupt_sig_fatal_chk.2083100853
Short name T288
Test name
Test status
Simulation time 725207746425 ps
CPU time 412.71 seconds
Started Apr 30 12:43:15 PM PDT 24
Finished Apr 30 12:50:09 PM PDT 24
Peak memory 239136 kb
Host smart-17d1c758-a659-4b93-a930-7230c7a31898
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2083100853 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_
corrupt_sig_fatal_chk.2083100853
Directory /workspace/26.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/26.rom_ctrl_kmac_err_chk.1120658541
Short name T338
Test name
Test status
Simulation time 334245393 ps
CPU time 11.6 seconds
Started Apr 30 12:43:15 PM PDT 24
Finished Apr 30 12:43:28 PM PDT 24
Peak memory 211940 kb
Host smart-09f98e9f-b708-4e35-bd81-72755a30eb85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1120658541 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_kmac_err_chk.1120658541
Directory /workspace/26.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/26.rom_ctrl_max_throughput_chk.898110655
Short name T230
Test name
Test status
Simulation time 954982669 ps
CPU time 7.27 seconds
Started Apr 30 12:43:24 PM PDT 24
Finished Apr 30 12:43:32 PM PDT 24
Peak memory 211308 kb
Host smart-029743e6-34ee-48f4-8122-cc24dcbe1eb3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=898110655 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_max_throughput_chk.898110655
Directory /workspace/26.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/26.rom_ctrl_smoke.1041989960
Short name T266
Test name
Test status
Simulation time 3517898614 ps
CPU time 31.52 seconds
Started Apr 30 12:43:24 PM PDT 24
Finished Apr 30 12:43:56 PM PDT 24
Peak memory 219604 kb
Host smart-a897a355-2f8d-454e-a0da-60dd699e73dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1041989960 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_smoke.1041989960
Directory /workspace/26.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/26.rom_ctrl_stress_all.4077637560
Short name T289
Test name
Test status
Simulation time 2075222059 ps
CPU time 23.63 seconds
Started Apr 30 12:43:15 PM PDT 24
Finished Apr 30 12:43:39 PM PDT 24
Peak memory 214204 kb
Host smart-ec4013f1-800e-461f-a0ce-0c059dba6470
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4077637560 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 26.rom_ctrl_stress_all.4077637560
Directory /workspace/26.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/27.rom_ctrl_alert_test.906225603
Short name T258
Test name
Test status
Simulation time 2450593999 ps
CPU time 14.36 seconds
Started Apr 30 12:43:21 PM PDT 24
Finished Apr 30 12:43:36 PM PDT 24
Peak memory 211460 kb
Host smart-198d15ea-b230-404b-a9f4-7040a62f4a86
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=906225603 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_alert_test.906225603
Directory /workspace/27.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/27.rom_ctrl_corrupt_sig_fatal_chk.1841008478
Short name T302
Test name
Test status
Simulation time 32175911193 ps
CPU time 336.72 seconds
Started Apr 30 12:43:24 PM PDT 24
Finished Apr 30 12:49:02 PM PDT 24
Peak memory 225876 kb
Host smart-3915725e-89b3-4ce0-92fe-7bc61d98643c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1841008478 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_
corrupt_sig_fatal_chk.1841008478
Directory /workspace/27.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/27.rom_ctrl_kmac_err_chk.1018338549
Short name T7
Test name
Test status
Simulation time 10682880993 ps
CPU time 24.12 seconds
Started Apr 30 12:43:15 PM PDT 24
Finished Apr 30 12:43:40 PM PDT 24
Peak memory 212404 kb
Host smart-5de09e1c-f8be-464b-96c0-601ae91575e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1018338549 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_kmac_err_chk.1018338549
Directory /workspace/27.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/27.rom_ctrl_max_throughput_chk.596917918
Short name T107
Test name
Test status
Simulation time 734460402 ps
CPU time 10 seconds
Started Apr 30 12:43:16 PM PDT 24
Finished Apr 30 12:43:27 PM PDT 24
Peak memory 211340 kb
Host smart-f098ff0d-bdd9-4d99-bed6-2b6e7d5010bd
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=596917918 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_max_throughput_chk.596917918
Directory /workspace/27.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/27.rom_ctrl_smoke.3148706230
Short name T233
Test name
Test status
Simulation time 2148373098 ps
CPU time 26.79 seconds
Started Apr 30 12:43:21 PM PDT 24
Finished Apr 30 12:43:48 PM PDT 24
Peak memory 213516 kb
Host smart-6abe8e7c-d0a8-4208-bb1a-6f9f30f0a714
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3148706230 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_smoke.3148706230
Directory /workspace/27.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/27.rom_ctrl_stress_all.1595165378
Short name T192
Test name
Test status
Simulation time 431356716 ps
CPU time 7.27 seconds
Started Apr 30 12:43:21 PM PDT 24
Finished Apr 30 12:43:29 PM PDT 24
Peak memory 211380 kb
Host smart-fb166ff9-6c69-48d2-8bc0-f7470e85747f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1595165378 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 27.rom_ctrl_stress_all.1595165378
Directory /workspace/27.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/27.rom_ctrl_stress_all_with_rand_reset.2188154386
Short name T52
Test name
Test status
Simulation time 9155522285 ps
CPU time 869.27 seconds
Started Apr 30 12:43:16 PM PDT 24
Finished Apr 30 12:57:46 PM PDT 24
Peak memory 223864 kb
Host smart-20058a4b-99f0-4573-92e3-6e6fd2e61bed
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2188154386 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_stress_all_with_rand_reset.2188154386
Directory /workspace/27.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/28.rom_ctrl_alert_test.3684051294
Short name T220
Test name
Test status
Simulation time 508696432 ps
CPU time 7.53 seconds
Started Apr 30 12:43:16 PM PDT 24
Finished Apr 30 12:43:24 PM PDT 24
Peak memory 211328 kb
Host smart-f34ac30d-2e62-46d0-b017-fa266ec1cadb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3684051294 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_alert_test.3684051294
Directory /workspace/28.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/28.rom_ctrl_corrupt_sig_fatal_chk.3687891399
Short name T256
Test name
Test status
Simulation time 2525188678 ps
CPU time 122.95 seconds
Started Apr 30 12:43:17 PM PDT 24
Finished Apr 30 12:45:20 PM PDT 24
Peak memory 228700 kb
Host smart-eaa21709-80b0-4dc9-abaf-d2ac92663def
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3687891399 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_
corrupt_sig_fatal_chk.3687891399
Directory /workspace/28.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/28.rom_ctrl_kmac_err_chk.530533223
Short name T215
Test name
Test status
Simulation time 2548139776 ps
CPU time 24.56 seconds
Started Apr 30 12:43:21 PM PDT 24
Finished Apr 30 12:43:46 PM PDT 24
Peak memory 212164 kb
Host smart-aa5d96b4-a933-49df-a64d-b82ce7361b33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=530533223 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_kmac_err_chk.530533223
Directory /workspace/28.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/28.rom_ctrl_max_throughput_chk.147658435
Short name T144
Test name
Test status
Simulation time 678394209 ps
CPU time 5.78 seconds
Started Apr 30 12:43:18 PM PDT 24
Finished Apr 30 12:43:25 PM PDT 24
Peak memory 211332 kb
Host smart-d36b83d8-502e-4133-abda-d1c33cade157
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=147658435 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_max_throughput_chk.147658435
Directory /workspace/28.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/28.rom_ctrl_smoke.2827242562
Short name T98
Test name
Test status
Simulation time 13235231725 ps
CPU time 28.52 seconds
Started Apr 30 12:43:20 PM PDT 24
Finished Apr 30 12:43:49 PM PDT 24
Peak memory 214540 kb
Host smart-a2cc4163-a2b4-4e38-9f84-d001ebe7aecb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2827242562 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_smoke.2827242562
Directory /workspace/28.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/28.rom_ctrl_stress_all.225362080
Short name T15
Test name
Test status
Simulation time 1943873732 ps
CPU time 16 seconds
Started Apr 30 12:43:21 PM PDT 24
Finished Apr 30 12:43:37 PM PDT 24
Peak memory 219548 kb
Host smart-c02be189-44d0-4e35-9bf8-c6fbccf8e08a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=225362080 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 28.rom_ctrl_stress_all.225362080
Directory /workspace/28.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/29.rom_ctrl_alert_test.1102392691
Short name T6
Test name
Test status
Simulation time 5223011116 ps
CPU time 9.37 seconds
Started Apr 30 12:43:16 PM PDT 24
Finished Apr 30 12:43:26 PM PDT 24
Peak memory 211492 kb
Host smart-4f4dfd51-8e4a-4c35-95e9-1c5c3377f87c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1102392691 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_alert_test.1102392691
Directory /workspace/29.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/29.rom_ctrl_corrupt_sig_fatal_chk.3270557587
Short name T313
Test name
Test status
Simulation time 5298229398 ps
CPU time 102.1 seconds
Started Apr 30 12:43:15 PM PDT 24
Finished Apr 30 12:44:58 PM PDT 24
Peak memory 213144 kb
Host smart-0eadaf66-44af-4a85-bd6f-bc7e67135eba
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3270557587 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_
corrupt_sig_fatal_chk.3270557587
Directory /workspace/29.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/29.rom_ctrl_kmac_err_chk.2803363499
Short name T203
Test name
Test status
Simulation time 2201504039 ps
CPU time 22.29 seconds
Started Apr 30 12:43:18 PM PDT 24
Finished Apr 30 12:43:41 PM PDT 24
Peak memory 212400 kb
Host smart-2f46d81e-bdb9-4551-8aa4-ff0bd14d9131
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2803363499 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_kmac_err_chk.2803363499
Directory /workspace/29.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/29.rom_ctrl_max_throughput_chk.819110246
Short name T329
Test name
Test status
Simulation time 96974730 ps
CPU time 5.51 seconds
Started Apr 30 12:43:16 PM PDT 24
Finished Apr 30 12:43:22 PM PDT 24
Peak memory 211344 kb
Host smart-6185a193-dc48-48f2-9268-135d74c57288
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=819110246 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_max_throughput_chk.819110246
Directory /workspace/29.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/29.rom_ctrl_smoke.307316154
Short name T305
Test name
Test status
Simulation time 13617265570 ps
CPU time 36.25 seconds
Started Apr 30 12:43:16 PM PDT 24
Finished Apr 30 12:43:53 PM PDT 24
Peak memory 214148 kb
Host smart-a37a10e0-938d-4c63-a419-ca5220bc321d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=307316154 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_smoke.307316154
Directory /workspace/29.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/29.rom_ctrl_stress_all.3886999725
Short name T282
Test name
Test status
Simulation time 2473200405 ps
CPU time 30.96 seconds
Started Apr 30 12:43:18 PM PDT 24
Finished Apr 30 12:43:50 PM PDT 24
Peak memory 219852 kb
Host smart-a756bd86-949d-489d-88d1-f6c3b1e71928
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3886999725 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 29.rom_ctrl_stress_all.3886999725
Directory /workspace/29.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/3.rom_ctrl_alert_test.4042151484
Short name T193
Test name
Test status
Simulation time 1358875765 ps
CPU time 12.51 seconds
Started Apr 30 12:42:22 PM PDT 24
Finished Apr 30 12:42:36 PM PDT 24
Peak memory 211348 kb
Host smart-560f5e27-c3d0-4c25-bb54-6e62ecaaab3c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4042151484 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_alert_test.4042151484
Directory /workspace/3.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/3.rom_ctrl_corrupt_sig_fatal_chk.630941949
Short name T271
Test name
Test status
Simulation time 107911344126 ps
CPU time 355.57 seconds
Started Apr 30 12:42:18 PM PDT 24
Finished Apr 30 12:48:14 PM PDT 24
Peak memory 218948 kb
Host smart-71805215-bcb4-4e41-bff0-c9ac84ca9181
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=630941949 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_co
rrupt_sig_fatal_chk.630941949
Directory /workspace/3.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/3.rom_ctrl_kmac_err_chk.2890733091
Short name T150
Test name
Test status
Simulation time 6962205477 ps
CPU time 30.28 seconds
Started Apr 30 12:42:12 PM PDT 24
Finished Apr 30 12:42:43 PM PDT 24
Peak memory 211460 kb
Host smart-e1717320-1112-4d2d-9983-2f3459d5558b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2890733091 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_kmac_err_chk.2890733091
Directory /workspace/3.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/3.rom_ctrl_max_throughput_chk.3455607378
Short name T198
Test name
Test status
Simulation time 922943380 ps
CPU time 6.76 seconds
Started Apr 30 12:42:19 PM PDT 24
Finished Apr 30 12:42:27 PM PDT 24
Peak memory 211352 kb
Host smart-29da2127-c281-4bab-a25c-8bf540b3e2c0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3455607378 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_max_throughput_chk.3455607378
Directory /workspace/3.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/3.rom_ctrl_sec_cm.3355742681
Short name T32
Test name
Test status
Simulation time 16289202063 ps
CPU time 62.72 seconds
Started Apr 30 12:42:20 PM PDT 24
Finished Apr 30 12:43:23 PM PDT 24
Peak memory 236572 kb
Host smart-a5c13f55-e586-4ccb-986a-eb0f1903f25f
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3355742681 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_sec_cm.3355742681
Directory /workspace/3.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/3.rom_ctrl_smoke.2406915279
Short name T213
Test name
Test status
Simulation time 9873299275 ps
CPU time 24.51 seconds
Started Apr 30 12:42:14 PM PDT 24
Finished Apr 30 12:42:40 PM PDT 24
Peak memory 219724 kb
Host smart-bd5f3e60-b13a-4eff-ad82-3fafc36477b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2406915279 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_smoke.2406915279
Directory /workspace/3.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/3.rom_ctrl_stress_all.1877260726
Short name T182
Test name
Test status
Simulation time 554345280 ps
CPU time 29.09 seconds
Started Apr 30 12:42:14 PM PDT 24
Finished Apr 30 12:42:44 PM PDT 24
Peak memory 219612 kb
Host smart-2adbbd9b-9db2-4647-a440-0ac66251b82e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1877260726 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 3.rom_ctrl_stress_all.1877260726
Directory /workspace/3.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/30.rom_ctrl_alert_test.3599001064
Short name T67
Test name
Test status
Simulation time 7350169936 ps
CPU time 14.89 seconds
Started Apr 30 12:43:24 PM PDT 24
Finished Apr 30 12:43:40 PM PDT 24
Peak memory 211476 kb
Host smart-a89ffea3-6a13-4bdf-90df-01bfef447da4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3599001064 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_alert_test.3599001064
Directory /workspace/30.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/30.rom_ctrl_corrupt_sig_fatal_chk.3919780085
Short name T306
Test name
Test status
Simulation time 63213647343 ps
CPU time 365.47 seconds
Started Apr 30 12:43:17 PM PDT 24
Finished Apr 30 12:49:23 PM PDT 24
Peak memory 236392 kb
Host smart-b9972cdf-f887-41cc-855d-6718c4ecad77
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3919780085 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_
corrupt_sig_fatal_chk.3919780085
Directory /workspace/30.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/30.rom_ctrl_kmac_err_chk.483427318
Short name T145
Test name
Test status
Simulation time 1874004740 ps
CPU time 12.47 seconds
Started Apr 30 12:43:16 PM PDT 24
Finished Apr 30 12:43:29 PM PDT 24
Peak memory 212116 kb
Host smart-a66b603d-7a6c-4114-9ad9-8d2f02c0b9b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=483427318 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_kmac_err_chk.483427318
Directory /workspace/30.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/30.rom_ctrl_max_throughput_chk.612270730
Short name T105
Test name
Test status
Simulation time 6094747020 ps
CPU time 13.79 seconds
Started Apr 30 12:43:16 PM PDT 24
Finished Apr 30 12:43:31 PM PDT 24
Peak memory 211344 kb
Host smart-abeb9fe0-fb34-4182-b265-0af9a302d67c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=612270730 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_max_throughput_chk.612270730
Directory /workspace/30.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/30.rom_ctrl_smoke.3404303045
Short name T251
Test name
Test status
Simulation time 2934219311 ps
CPU time 17.78 seconds
Started Apr 30 12:43:24 PM PDT 24
Finished Apr 30 12:43:43 PM PDT 24
Peak memory 213492 kb
Host smart-c32da04e-6dfb-4f9e-884e-b053a895763a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3404303045 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_smoke.3404303045
Directory /workspace/30.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/30.rom_ctrl_stress_all.1578871678
Short name T187
Test name
Test status
Simulation time 1612690280 ps
CPU time 17.26 seconds
Started Apr 30 12:43:18 PM PDT 24
Finished Apr 30 12:43:36 PM PDT 24
Peak memory 211216 kb
Host smart-cb50aafa-b648-4fbf-9a7e-126190f0919a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1578871678 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 30.rom_ctrl_stress_all.1578871678
Directory /workspace/30.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/31.rom_ctrl_alert_test.171058241
Short name T128
Test name
Test status
Simulation time 644824784 ps
CPU time 8.04 seconds
Started Apr 30 12:43:27 PM PDT 24
Finished Apr 30 12:43:36 PM PDT 24
Peak memory 211364 kb
Host smart-f11ca6e1-9098-402e-863b-3f7deab65fd0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=171058241 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_alert_test.171058241
Directory /workspace/31.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/31.rom_ctrl_corrupt_sig_fatal_chk.2973458977
Short name T318
Test name
Test status
Simulation time 19030337405 ps
CPU time 191.39 seconds
Started Apr 30 12:43:25 PM PDT 24
Finished Apr 30 12:46:37 PM PDT 24
Peak memory 225244 kb
Host smart-6692c1f4-3fa3-415c-bb1b-2a37eca23478
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2973458977 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_
corrupt_sig_fatal_chk.2973458977
Directory /workspace/31.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/31.rom_ctrl_kmac_err_chk.2590192859
Short name T317
Test name
Test status
Simulation time 1850346659 ps
CPU time 20.84 seconds
Started Apr 30 12:43:24 PM PDT 24
Finished Apr 30 12:43:46 PM PDT 24
Peak memory 211992 kb
Host smart-f0af0ad6-4761-432e-af57-bd402fab08c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2590192859 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_kmac_err_chk.2590192859
Directory /workspace/31.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/31.rom_ctrl_max_throughput_chk.1986425102
Short name T286
Test name
Test status
Simulation time 2085972501 ps
CPU time 16.96 seconds
Started Apr 30 12:43:25 PM PDT 24
Finished Apr 30 12:43:43 PM PDT 24
Peak memory 211376 kb
Host smart-5ede4094-484c-4437-93a4-37976ae017ae
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1986425102 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_max_throughput_chk.1986425102
Directory /workspace/31.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/31.rom_ctrl_smoke.1372418807
Short name T180
Test name
Test status
Simulation time 191980823 ps
CPU time 10.06 seconds
Started Apr 30 12:43:25 PM PDT 24
Finished Apr 30 12:43:35 PM PDT 24
Peak memory 219472 kb
Host smart-b873a3c7-a2a1-4139-82a8-db5cd12c1f75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1372418807 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_smoke.1372418807
Directory /workspace/31.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/31.rom_ctrl_stress_all.3418437084
Short name T125
Test name
Test status
Simulation time 430332998 ps
CPU time 15.07 seconds
Started Apr 30 12:43:24 PM PDT 24
Finished Apr 30 12:43:39 PM PDT 24
Peak memory 212560 kb
Host smart-6772be6e-963d-4d0d-9632-a5b1c2344ad4
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3418437084 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 31.rom_ctrl_stress_all.3418437084
Directory /workspace/31.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/32.rom_ctrl_alert_test.3992646051
Short name T177
Test name
Test status
Simulation time 168641810 ps
CPU time 4.15 seconds
Started Apr 30 12:43:24 PM PDT 24
Finished Apr 30 12:43:28 PM PDT 24
Peak memory 211368 kb
Host smart-838536ab-f042-4721-8223-bc2d8efd6224
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3992646051 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_alert_test.3992646051
Directory /workspace/32.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/32.rom_ctrl_corrupt_sig_fatal_chk.3249467087
Short name T196
Test name
Test status
Simulation time 15611099269 ps
CPU time 182.01 seconds
Started Apr 30 12:43:26 PM PDT 24
Finished Apr 30 12:46:28 PM PDT 24
Peak memory 235084 kb
Host smart-628042ab-7769-4437-99bd-9e47edc583c7
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3249467087 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_
corrupt_sig_fatal_chk.3249467087
Directory /workspace/32.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/32.rom_ctrl_kmac_err_chk.2962917559
Short name T186
Test name
Test status
Simulation time 5090351887 ps
CPU time 17.3 seconds
Started Apr 30 12:43:25 PM PDT 24
Finished Apr 30 12:43:43 PM PDT 24
Peak memory 212460 kb
Host smart-6ae5da6d-8989-49f6-87d8-ee9a6f8a310b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2962917559 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_kmac_err_chk.2962917559
Directory /workspace/32.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/32.rom_ctrl_max_throughput_chk.118575821
Short name T183
Test name
Test status
Simulation time 220162519 ps
CPU time 6.94 seconds
Started Apr 30 12:43:26 PM PDT 24
Finished Apr 30 12:43:33 PM PDT 24
Peak memory 211384 kb
Host smart-743c9fef-dc3b-4414-855d-da4ae4f66b44
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=118575821 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_max_throughput_chk.118575821
Directory /workspace/32.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/32.rom_ctrl_smoke.1921536017
Short name T79
Test name
Test status
Simulation time 514360455 ps
CPU time 14.15 seconds
Started Apr 30 12:43:25 PM PDT 24
Finished Apr 30 12:43:40 PM PDT 24
Peak memory 219504 kb
Host smart-0e695f5c-4ddf-469a-8e9d-69a25dadca0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1921536017 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_smoke.1921536017
Directory /workspace/32.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/32.rom_ctrl_stress_all.2581806640
Short name T293
Test name
Test status
Simulation time 1760042461 ps
CPU time 13.19 seconds
Started Apr 30 12:43:23 PM PDT 24
Finished Apr 30 12:43:37 PM PDT 24
Peak memory 212032 kb
Host smart-4aef3217-b20f-42e5-bef5-bde66764e03a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2581806640 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 32.rom_ctrl_stress_all.2581806640
Directory /workspace/32.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/33.rom_ctrl_alert_test.2540943451
Short name T143
Test name
Test status
Simulation time 1861410261 ps
CPU time 14.71 seconds
Started Apr 30 12:43:29 PM PDT 24
Finished Apr 30 12:43:44 PM PDT 24
Peak memory 211460 kb
Host smart-54975219-4e3c-46a1-aaac-600ef61a6190
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2540943451 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_alert_test.2540943451
Directory /workspace/33.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/33.rom_ctrl_corrupt_sig_fatal_chk.3325387027
Short name T262
Test name
Test status
Simulation time 17904310927 ps
CPU time 175.26 seconds
Started Apr 30 12:43:25 PM PDT 24
Finished Apr 30 12:46:21 PM PDT 24
Peak memory 228248 kb
Host smart-0599cf88-2a7c-4a37-8269-860f7f8ab863
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3325387027 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_
corrupt_sig_fatal_chk.3325387027
Directory /workspace/33.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/33.rom_ctrl_kmac_err_chk.228123559
Short name T225
Test name
Test status
Simulation time 2143919246 ps
CPU time 22.26 seconds
Started Apr 30 12:43:26 PM PDT 24
Finished Apr 30 12:43:49 PM PDT 24
Peak memory 211936 kb
Host smart-dc4285bb-145e-47c4-97c3-6bf84afb3f89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=228123559 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_kmac_err_chk.228123559
Directory /workspace/33.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/33.rom_ctrl_max_throughput_chk.1259773410
Short name T217
Test name
Test status
Simulation time 1276496506 ps
CPU time 7.58 seconds
Started Apr 30 12:43:25 PM PDT 24
Finished Apr 30 12:43:34 PM PDT 24
Peak memory 211396 kb
Host smart-e7f62279-4afd-4a29-bc14-63769e40bba7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1259773410 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_max_throughput_chk.1259773410
Directory /workspace/33.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/33.rom_ctrl_smoke.4016266513
Short name T275
Test name
Test status
Simulation time 17669466001 ps
CPU time 30.31 seconds
Started Apr 30 12:43:24 PM PDT 24
Finished Apr 30 12:43:55 PM PDT 24
Peak memory 219620 kb
Host smart-f54f69d3-5e3c-4df6-b2ae-05f953f7727c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4016266513 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_smoke.4016266513
Directory /workspace/33.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/34.rom_ctrl_alert_test.81648336
Short name T285
Test name
Test status
Simulation time 6248740565 ps
CPU time 14.09 seconds
Started Apr 30 12:43:25 PM PDT 24
Finished Apr 30 12:43:40 PM PDT 24
Peak memory 211420 kb
Host smart-71fcc071-e65b-4a26-9e54-7a16b476c009
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=81648336 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_alert_test.81648336
Directory /workspace/34.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/34.rom_ctrl_corrupt_sig_fatal_chk.2551044254
Short name T359
Test name
Test status
Simulation time 66565406721 ps
CPU time 194.86 seconds
Started Apr 30 12:43:25 PM PDT 24
Finished Apr 30 12:46:41 PM PDT 24
Peak memory 236956 kb
Host smart-08eba4b0-4bcb-45e4-b098-f468dc5b782f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2551044254 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_
corrupt_sig_fatal_chk.2551044254
Directory /workspace/34.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/34.rom_ctrl_kmac_err_chk.3868495013
Short name T181
Test name
Test status
Simulation time 6622173289 ps
CPU time 27.98 seconds
Started Apr 30 12:43:29 PM PDT 24
Finished Apr 30 12:43:57 PM PDT 24
Peak memory 219740 kb
Host smart-aeeae86c-2178-4ebc-b946-742c202eec10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3868495013 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_kmac_err_chk.3868495013
Directory /workspace/34.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/34.rom_ctrl_max_throughput_chk.2021675898
Short name T342
Test name
Test status
Simulation time 189462644 ps
CPU time 7.04 seconds
Started Apr 30 12:43:25 PM PDT 24
Finished Apr 30 12:43:33 PM PDT 24
Peak memory 211368 kb
Host smart-f1fed3de-5677-42d1-9d0b-a038dcdafe02
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2021675898 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_max_throughput_chk.2021675898
Directory /workspace/34.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/34.rom_ctrl_smoke.4122993093
Short name T218
Test name
Test status
Simulation time 3480295913 ps
CPU time 30.61 seconds
Started Apr 30 12:43:28 PM PDT 24
Finished Apr 30 12:43:59 PM PDT 24
Peak memory 219668 kb
Host smart-daf30dbf-45bd-4b40-9462-845441314fd6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4122993093 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_smoke.4122993093
Directory /workspace/34.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/34.rom_ctrl_stress_all.1096554918
Short name T294
Test name
Test status
Simulation time 1275234686 ps
CPU time 15.66 seconds
Started Apr 30 12:43:25 PM PDT 24
Finished Apr 30 12:43:42 PM PDT 24
Peak memory 213612 kb
Host smart-cf59c2eb-2411-4858-9583-f55af62d1fc3
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1096554918 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 34.rom_ctrl_stress_all.1096554918
Directory /workspace/34.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/34.rom_ctrl_stress_all_with_rand_reset.1209386054
Short name T333
Test name
Test status
Simulation time 247694021187 ps
CPU time 2123.06 seconds
Started Apr 30 12:43:30 PM PDT 24
Finished Apr 30 01:18:53 PM PDT 24
Peak memory 237924 kb
Host smart-2f3fdf36-82bc-4ce0-8fb2-71616ffad615
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1209386054 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_stress_all_with_rand_reset.1209386054
Directory /workspace/34.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.rom_ctrl_alert_test.3751103745
Short name T134
Test name
Test status
Simulation time 1163166518 ps
CPU time 10.95 seconds
Started Apr 30 12:43:37 PM PDT 24
Finished Apr 30 12:43:48 PM PDT 24
Peak memory 211332 kb
Host smart-ba58696c-661e-4894-90c4-92aea14b4c3a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3751103745 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_alert_test.3751103745
Directory /workspace/35.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/35.rom_ctrl_corrupt_sig_fatal_chk.1366132592
Short name T351
Test name
Test status
Simulation time 5267641053 ps
CPU time 92.87 seconds
Started Apr 30 12:43:36 PM PDT 24
Finished Apr 30 12:45:09 PM PDT 24
Peak memory 233368 kb
Host smart-423533b8-d645-42da-a432-1ed9f788b3db
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1366132592 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_
corrupt_sig_fatal_chk.1366132592
Directory /workspace/35.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/35.rom_ctrl_kmac_err_chk.1861845141
Short name T356
Test name
Test status
Simulation time 2398253206 ps
CPU time 23.58 seconds
Started Apr 30 12:43:38 PM PDT 24
Finished Apr 30 12:44:02 PM PDT 24
Peak memory 212148 kb
Host smart-11068dcc-10e2-41ce-9627-87bfc291198b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1861845141 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_kmac_err_chk.1861845141
Directory /workspace/35.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/35.rom_ctrl_max_throughput_chk.2972691837
Short name T360
Test name
Test status
Simulation time 25499358131 ps
CPU time 14.71 seconds
Started Apr 30 12:43:38 PM PDT 24
Finished Apr 30 12:43:53 PM PDT 24
Peak memory 211344 kb
Host smart-4be0898f-2ad3-4d6a-89bd-2df661672155
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2972691837 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_max_throughput_chk.2972691837
Directory /workspace/35.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/35.rom_ctrl_smoke.116963176
Short name T228
Test name
Test status
Simulation time 12133838985 ps
CPU time 27.96 seconds
Started Apr 30 12:43:29 PM PDT 24
Finished Apr 30 12:43:58 PM PDT 24
Peak memory 219692 kb
Host smart-f2029097-ea1a-4b41-a53e-11e940c9efe0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=116963176 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_smoke.116963176
Directory /workspace/35.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/35.rom_ctrl_stress_all.1137888503
Short name T322
Test name
Test status
Simulation time 7729408811 ps
CPU time 19.86 seconds
Started Apr 30 12:43:25 PM PDT 24
Finished Apr 30 12:43:46 PM PDT 24
Peak memory 211348 kb
Host smart-94f829b8-0cfc-4f69-8b3e-a828acb153f6
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1137888503 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 35.rom_ctrl_stress_all.1137888503
Directory /workspace/35.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/36.rom_ctrl_alert_test.1727333545
Short name T133
Test name
Test status
Simulation time 552572661 ps
CPU time 4.27 seconds
Started Apr 30 12:43:38 PM PDT 24
Finished Apr 30 12:43:43 PM PDT 24
Peak memory 211352 kb
Host smart-8d7e1846-309d-42e2-b8a0-2e0979887419
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1727333545 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_alert_test.1727333545
Directory /workspace/36.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/36.rom_ctrl_corrupt_sig_fatal_chk.1148841012
Short name T237
Test name
Test status
Simulation time 30254697061 ps
CPU time 305.14 seconds
Started Apr 30 12:43:42 PM PDT 24
Finished Apr 30 12:48:47 PM PDT 24
Peak memory 224796 kb
Host smart-50461f82-47e8-4a5a-96a9-2935b10b1441
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1148841012 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_
corrupt_sig_fatal_chk.1148841012
Directory /workspace/36.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/36.rom_ctrl_kmac_err_chk.1593311007
Short name T170
Test name
Test status
Simulation time 175436634 ps
CPU time 9.4 seconds
Started Apr 30 12:43:36 PM PDT 24
Finished Apr 30 12:43:46 PM PDT 24
Peak memory 211872 kb
Host smart-415446f0-8f23-464f-be22-1962458f9fa1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1593311007 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_kmac_err_chk.1593311007
Directory /workspace/36.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/36.rom_ctrl_max_throughput_chk.2884429155
Short name T259
Test name
Test status
Simulation time 97703700 ps
CPU time 5.27 seconds
Started Apr 30 12:43:36 PM PDT 24
Finished Apr 30 12:43:41 PM PDT 24
Peak memory 211264 kb
Host smart-343b71e2-d583-4b21-a8d4-1541fe421db9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2884429155 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_max_throughput_chk.2884429155
Directory /workspace/36.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/36.rom_ctrl_smoke.166932801
Short name T81
Test name
Test status
Simulation time 1695934885 ps
CPU time 17.04 seconds
Started Apr 30 12:43:38 PM PDT 24
Finished Apr 30 12:43:56 PM PDT 24
Peak memory 213624 kb
Host smart-fdf6cc44-bac9-4576-a944-00c8e7b1132b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=166932801 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_smoke.166932801
Directory /workspace/36.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/36.rom_ctrl_stress_all.3933676645
Short name T50
Test name
Test status
Simulation time 17441302620 ps
CPU time 78.15 seconds
Started Apr 30 12:43:34 PM PDT 24
Finished Apr 30 12:44:53 PM PDT 24
Peak memory 217864 kb
Host smart-ef303d2d-f588-471c-990a-d18a5704e157
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3933676645 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 36.rom_ctrl_stress_all.3933676645
Directory /workspace/36.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/37.rom_ctrl_alert_test.3534121994
Short name T236
Test name
Test status
Simulation time 332733330 ps
CPU time 4.09 seconds
Started Apr 30 12:43:41 PM PDT 24
Finished Apr 30 12:43:46 PM PDT 24
Peak memory 211372 kb
Host smart-819cfda1-115d-4fda-a334-4cdb7cc120bd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3534121994 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_alert_test.3534121994
Directory /workspace/37.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/37.rom_ctrl_corrupt_sig_fatal_chk.3785221276
Short name T14
Test name
Test status
Simulation time 55951675374 ps
CPU time 138.95 seconds
Started Apr 30 12:43:38 PM PDT 24
Finished Apr 30 12:45:58 PM PDT 24
Peak memory 238052 kb
Host smart-a69c36cb-cee9-4917-937b-dd417343456d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3785221276 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_
corrupt_sig_fatal_chk.3785221276
Directory /workspace/37.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/37.rom_ctrl_kmac_err_chk.1545659413
Short name T299
Test name
Test status
Simulation time 596750844 ps
CPU time 13.6 seconds
Started Apr 30 12:43:35 PM PDT 24
Finished Apr 30 12:43:49 PM PDT 24
Peak memory 212076 kb
Host smart-94beffe5-5169-4541-ba08-c53f23c4b968
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1545659413 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_kmac_err_chk.1545659413
Directory /workspace/37.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/37.rom_ctrl_max_throughput_chk.1508950809
Short name T16
Test name
Test status
Simulation time 431613412 ps
CPU time 8.2 seconds
Started Apr 30 12:43:41 PM PDT 24
Finished Apr 30 12:43:50 PM PDT 24
Peak memory 211324 kb
Host smart-5056daaa-bcb8-4308-a344-66b0a2779e2c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1508950809 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_max_throughput_chk.1508950809
Directory /workspace/37.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/37.rom_ctrl_smoke.2898408120
Short name T202
Test name
Test status
Simulation time 6274414580 ps
CPU time 34.25 seconds
Started Apr 30 12:43:34 PM PDT 24
Finished Apr 30 12:44:09 PM PDT 24
Peak memory 214412 kb
Host smart-f01f9997-0545-49b6-a5f1-03253d64d00b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2898408120 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_smoke.2898408120
Directory /workspace/37.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/37.rom_ctrl_stress_all.679031788
Short name T82
Test name
Test status
Simulation time 9149686267 ps
CPU time 92.03 seconds
Started Apr 30 12:43:42 PM PDT 24
Finished Apr 30 12:45:14 PM PDT 24
Peak memory 219572 kb
Host smart-04748206-dc71-4753-88f5-889704ce34ab
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=679031788 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 37.rom_ctrl_stress_all.679031788
Directory /workspace/37.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/38.rom_ctrl_alert_test.1309615144
Short name T148
Test name
Test status
Simulation time 343221647 ps
CPU time 6.57 seconds
Started Apr 30 12:43:33 PM PDT 24
Finished Apr 30 12:43:40 PM PDT 24
Peak memory 211392 kb
Host smart-c3a9d94d-4b5a-474f-b902-1b8e3aeaed6b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1309615144 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_alert_test.1309615144
Directory /workspace/38.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/38.rom_ctrl_corrupt_sig_fatal_chk.2400884553
Short name T47
Test name
Test status
Simulation time 140929390489 ps
CPU time 316.65 seconds
Started Apr 30 12:43:36 PM PDT 24
Finished Apr 30 12:48:53 PM PDT 24
Peak memory 234292 kb
Host smart-ddf96bde-aa74-4086-a64f-1178693fb134
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2400884553 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_
corrupt_sig_fatal_chk.2400884553
Directory /workspace/38.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/38.rom_ctrl_kmac_err_chk.1507536225
Short name T201
Test name
Test status
Simulation time 4194826084 ps
CPU time 33.81 seconds
Started Apr 30 12:43:35 PM PDT 24
Finished Apr 30 12:44:10 PM PDT 24
Peak memory 212032 kb
Host smart-1779262b-2e22-487a-bef1-f725bca55c27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1507536225 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_kmac_err_chk.1507536225
Directory /workspace/38.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/38.rom_ctrl_max_throughput_chk.1671767553
Short name T154
Test name
Test status
Simulation time 5028554531 ps
CPU time 13.44 seconds
Started Apr 30 12:43:36 PM PDT 24
Finished Apr 30 12:43:50 PM PDT 24
Peak memory 211348 kb
Host smart-c3d29603-1877-428c-b1bf-0e260567f3bc
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1671767553 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_max_throughput_chk.1671767553
Directory /workspace/38.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/38.rom_ctrl_smoke.7323389
Short name T209
Test name
Test status
Simulation time 387385689 ps
CPU time 9.93 seconds
Started Apr 30 12:43:37 PM PDT 24
Finished Apr 30 12:43:48 PM PDT 24
Peak memory 213020 kb
Host smart-c9127004-76e2-4152-ab32-3b37c0730ee0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=7323389 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_smoke.7323389
Directory /workspace/38.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/38.rom_ctrl_stress_all.3608615230
Short name T321
Test name
Test status
Simulation time 1746079330 ps
CPU time 38.58 seconds
Started Apr 30 12:43:36 PM PDT 24
Finished Apr 30 12:44:15 PM PDT 24
Peak memory 214536 kb
Host smart-9b5c8006-54e3-4121-beb1-142af5cd9a7b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3608615230 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 38.rom_ctrl_stress_all.3608615230
Directory /workspace/38.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/39.rom_ctrl_alert_test.2556289830
Short name T140
Test name
Test status
Simulation time 17318913244 ps
CPU time 16.09 seconds
Started Apr 30 12:43:46 PM PDT 24
Finished Apr 30 12:44:03 PM PDT 24
Peak memory 211480 kb
Host smart-397c207e-1a24-4e40-b05e-c45250f69737
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2556289830 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_alert_test.2556289830
Directory /workspace/39.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/39.rom_ctrl_corrupt_sig_fatal_chk.1865167868
Short name T273
Test name
Test status
Simulation time 97556382071 ps
CPU time 250.52 seconds
Started Apr 30 12:43:39 PM PDT 24
Finished Apr 30 12:47:50 PM PDT 24
Peak memory 234460 kb
Host smart-afae00ca-52b8-4bb3-b3bb-046c33175edb
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1865167868 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_
corrupt_sig_fatal_chk.1865167868
Directory /workspace/39.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/39.rom_ctrl_kmac_err_chk.4277106097
Short name T211
Test name
Test status
Simulation time 341228301 ps
CPU time 9.16 seconds
Started Apr 30 12:43:34 PM PDT 24
Finished Apr 30 12:43:43 PM PDT 24
Peak memory 211984 kb
Host smart-34a87f9b-282a-4e5a-962e-90ec2177e657
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4277106097 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_kmac_err_chk.4277106097
Directory /workspace/39.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/39.rom_ctrl_max_throughput_chk.1748615797
Short name T45
Test name
Test status
Simulation time 3492469567 ps
CPU time 10.43 seconds
Started Apr 30 12:43:34 PM PDT 24
Finished Apr 30 12:43:45 PM PDT 24
Peak memory 211400 kb
Host smart-8aa02adf-272e-420c-bce7-d4db306cb410
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1748615797 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_max_throughput_chk.1748615797
Directory /workspace/39.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/39.rom_ctrl_smoke.2391708440
Short name T241
Test name
Test status
Simulation time 4048073404 ps
CPU time 34.41 seconds
Started Apr 30 12:43:34 PM PDT 24
Finished Apr 30 12:44:09 PM PDT 24
Peak memory 219628 kb
Host smart-17d4b4e9-e260-4941-9197-0150f0be3ad3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2391708440 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_smoke.2391708440
Directory /workspace/39.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/39.rom_ctrl_stress_all.720776343
Short name T163
Test name
Test status
Simulation time 4724426056 ps
CPU time 46.64 seconds
Started Apr 30 12:43:37 PM PDT 24
Finished Apr 30 12:44:24 PM PDT 24
Peak memory 219596 kb
Host smart-0b4a823d-c0bf-47f3-9665-e3eb2ea1a050
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=720776343 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 39.rom_ctrl_stress_all.720776343
Directory /workspace/39.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/4.rom_ctrl_alert_test.3648385039
Short name T355
Test name
Test status
Simulation time 743204017 ps
CPU time 6.79 seconds
Started Apr 30 12:42:21 PM PDT 24
Finished Apr 30 12:42:28 PM PDT 24
Peak memory 211352 kb
Host smart-866192e3-34c7-4d08-a529-e14069ff37aa
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3648385039 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_alert_test.3648385039
Directory /workspace/4.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/4.rom_ctrl_corrupt_sig_fatal_chk.2612323146
Short name T12
Test name
Test status
Simulation time 83724290194 ps
CPU time 273.87 seconds
Started Apr 30 12:42:20 PM PDT 24
Finished Apr 30 12:46:54 PM PDT 24
Peak memory 237332 kb
Host smart-a6d977a6-e5d7-4ad0-b5a3-e899b16d4cb5
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2612323146 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_c
orrupt_sig_fatal_chk.2612323146
Directory /workspace/4.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/4.rom_ctrl_kmac_err_chk.427418495
Short name T323
Test name
Test status
Simulation time 692878724 ps
CPU time 9.36 seconds
Started Apr 30 12:42:20 PM PDT 24
Finished Apr 30 12:42:30 PM PDT 24
Peak memory 212320 kb
Host smart-7b06fc3f-e016-41d2-b8a8-0a10822d1429
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=427418495 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_kmac_err_chk.427418495
Directory /workspace/4.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/4.rom_ctrl_max_throughput_chk.2490196276
Short name T188
Test name
Test status
Simulation time 1300764006 ps
CPU time 12.83 seconds
Started Apr 30 12:42:25 PM PDT 24
Finished Apr 30 12:42:38 PM PDT 24
Peak memory 211360 kb
Host smart-90fdd407-6082-4d5f-8a38-15ecc0681884
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2490196276 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_max_throughput_chk.2490196276
Directory /workspace/4.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/4.rom_ctrl_sec_cm.3355403567
Short name T36
Test name
Test status
Simulation time 2155749049 ps
CPU time 104.14 seconds
Started Apr 30 12:42:20 PM PDT 24
Finished Apr 30 12:44:05 PM PDT 24
Peak memory 232284 kb
Host smart-1579b122-25ed-439d-9323-bdbe92f08c63
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3355403567 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_sec_cm.3355403567
Directory /workspace/4.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/4.rom_ctrl_smoke.1310634152
Short name T3
Test name
Test status
Simulation time 1299388705 ps
CPU time 21.07 seconds
Started Apr 30 12:42:22 PM PDT 24
Finished Apr 30 12:42:43 PM PDT 24
Peak memory 213524 kb
Host smart-7a6ab07b-e884-43b7-9810-b390df8d3565
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1310634152 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_smoke.1310634152
Directory /workspace/4.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/4.rom_ctrl_stress_all.908353658
Short name T96
Test name
Test status
Simulation time 2629366576 ps
CPU time 38.62 seconds
Started Apr 30 12:42:20 PM PDT 24
Finished Apr 30 12:42:59 PM PDT 24
Peak memory 213556 kb
Host smart-641d20c9-1156-4a3e-9690-ec9caf7c3fd0
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=908353658 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 4.rom_ctrl_stress_all.908353658
Directory /workspace/4.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/4.rom_ctrl_stress_all_with_rand_reset.1466778934
Short name T18
Test name
Test status
Simulation time 135207742014 ps
CPU time 1205.6 seconds
Started Apr 30 12:42:20 PM PDT 24
Finished Apr 30 01:02:26 PM PDT 24
Peak memory 232980 kb
Host smart-9d62db91-51a1-423b-a7c8-8c4b05bd72ae
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1466778934 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_stress_all_with_rand_reset.1466778934
Directory /workspace/4.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.rom_ctrl_alert_test.102789076
Short name T168
Test name
Test status
Simulation time 2131272782 ps
CPU time 7.66 seconds
Started Apr 30 12:43:44 PM PDT 24
Finished Apr 30 12:43:52 PM PDT 24
Peak memory 211444 kb
Host smart-7d8cf534-ca98-4e12-826d-0a5918d592fe
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=102789076 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_alert_test.102789076
Directory /workspace/40.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/40.rom_ctrl_corrupt_sig_fatal_chk.3809890880
Short name T246
Test name
Test status
Simulation time 47511249556 ps
CPU time 163.74 seconds
Started Apr 30 12:43:48 PM PDT 24
Finished Apr 30 12:46:32 PM PDT 24
Peak memory 225356 kb
Host smart-d34033e0-337e-4bb5-b6a1-a7c750135727
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3809890880 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_
corrupt_sig_fatal_chk.3809890880
Directory /workspace/40.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/40.rom_ctrl_kmac_err_chk.4224414461
Short name T9
Test name
Test status
Simulation time 687789657 ps
CPU time 12.05 seconds
Started Apr 30 12:43:44 PM PDT 24
Finished Apr 30 12:43:57 PM PDT 24
Peak memory 212072 kb
Host smart-512b745e-3d84-44a3-885a-02a30deca65a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4224414461 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_kmac_err_chk.4224414461
Directory /workspace/40.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/40.rom_ctrl_max_throughput_chk.3882299600
Short name T283
Test name
Test status
Simulation time 313635436 ps
CPU time 7.57 seconds
Started Apr 30 12:43:44 PM PDT 24
Finished Apr 30 12:43:52 PM PDT 24
Peak memory 211432 kb
Host smart-901ad1fc-be42-4fe3-81a0-ad05b4259794
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3882299600 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_max_throughput_chk.3882299600
Directory /workspace/40.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/40.rom_ctrl_smoke.483022531
Short name T287
Test name
Test status
Simulation time 4076564654 ps
CPU time 35.79 seconds
Started Apr 30 12:43:48 PM PDT 24
Finished Apr 30 12:44:24 PM PDT 24
Peak memory 219724 kb
Host smart-e29c5cbd-c48c-4fc9-8360-111ebda9ce28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=483022531 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_smoke.483022531
Directory /workspace/40.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/40.rom_ctrl_stress_all.4073212845
Short name T268
Test name
Test status
Simulation time 129066528896 ps
CPU time 84.21 seconds
Started Apr 30 12:43:44 PM PDT 24
Finished Apr 30 12:45:09 PM PDT 24
Peak memory 219672 kb
Host smart-0a3cd2c1-51ac-4d0e-b8fe-248b8114913d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4073212845 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 40.rom_ctrl_stress_all.4073212845
Directory /workspace/40.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/41.rom_ctrl_alert_test.520634664
Short name T290
Test name
Test status
Simulation time 2608517852 ps
CPU time 7.78 seconds
Started Apr 30 12:43:45 PM PDT 24
Finished Apr 30 12:43:53 PM PDT 24
Peak memory 211532 kb
Host smart-5533c01c-b94f-4253-bdf5-74324d2d491a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=520634664 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_alert_test.520634664
Directory /workspace/41.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/41.rom_ctrl_corrupt_sig_fatal_chk.166532418
Short name T340
Test name
Test status
Simulation time 21188909189 ps
CPU time 127.6 seconds
Started Apr 30 12:43:47 PM PDT 24
Finished Apr 30 12:45:55 PM PDT 24
Peak memory 227880 kb
Host smart-41863c0b-1d80-4d00-b623-d50f24927f5d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=166532418 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_c
orrupt_sig_fatal_chk.166532418
Directory /workspace/41.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/41.rom_ctrl_kmac_err_chk.1417173546
Short name T175
Test name
Test status
Simulation time 2832359472 ps
CPU time 26.63 seconds
Started Apr 30 12:43:45 PM PDT 24
Finished Apr 30 12:44:12 PM PDT 24
Peak memory 212024 kb
Host smart-3b295138-bf0e-4886-bd7a-299745b92da5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1417173546 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_kmac_err_chk.1417173546
Directory /workspace/41.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/41.rom_ctrl_max_throughput_chk.2809832674
Short name T109
Test name
Test status
Simulation time 313468941 ps
CPU time 5.37 seconds
Started Apr 30 12:43:45 PM PDT 24
Finished Apr 30 12:43:50 PM PDT 24
Peak memory 211344 kb
Host smart-0d7ef7be-5b16-4eaf-84c6-c7e6fb9fb968
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2809832674 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_max_throughput_chk.2809832674
Directory /workspace/41.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/41.rom_ctrl_smoke.356598412
Short name T185
Test name
Test status
Simulation time 2293749644 ps
CPU time 25.52 seconds
Started Apr 30 12:43:47 PM PDT 24
Finished Apr 30 12:44:12 PM PDT 24
Peak memory 212876 kb
Host smart-6dfdecaf-44f3-48b1-8be3-c13c62213194
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=356598412 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_smoke.356598412
Directory /workspace/41.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/41.rom_ctrl_stress_all.1836261620
Short name T331
Test name
Test status
Simulation time 489392482 ps
CPU time 6.05 seconds
Started Apr 30 12:43:45 PM PDT 24
Finished Apr 30 12:43:52 PM PDT 24
Peak memory 211364 kb
Host smart-ac631319-b8ea-4c4c-b975-fe70fa2d9ccf
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1836261620 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 41.rom_ctrl_stress_all.1836261620
Directory /workspace/41.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/42.rom_ctrl_alert_test.3134579334
Short name T195
Test name
Test status
Simulation time 1685499096 ps
CPU time 13.54 seconds
Started Apr 30 12:43:45 PM PDT 24
Finished Apr 30 12:43:59 PM PDT 24
Peak memory 211436 kb
Host smart-6f2c7aba-88b6-47f4-8365-ac9d58ee887e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3134579334 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_alert_test.3134579334
Directory /workspace/42.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/42.rom_ctrl_corrupt_sig_fatal_chk.209218698
Short name T347
Test name
Test status
Simulation time 316850392656 ps
CPU time 202.64 seconds
Started Apr 30 12:43:47 PM PDT 24
Finished Apr 30 12:47:10 PM PDT 24
Peak memory 231036 kb
Host smart-34ff4e91-2b22-43d6-bb99-702b7befdfbf
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=209218698 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_c
orrupt_sig_fatal_chk.209218698
Directory /workspace/42.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/42.rom_ctrl_kmac_err_chk.3399844513
Short name T44
Test name
Test status
Simulation time 3180370485 ps
CPU time 15.12 seconds
Started Apr 30 12:43:47 PM PDT 24
Finished Apr 30 12:44:02 PM PDT 24
Peak memory 212096 kb
Host smart-f39eb25b-b494-4dc3-b9a5-e8587cc8e6f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3399844513 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_kmac_err_chk.3399844513
Directory /workspace/42.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/42.rom_ctrl_max_throughput_chk.2491367036
Short name T147
Test name
Test status
Simulation time 1777588925 ps
CPU time 8.44 seconds
Started Apr 30 12:43:46 PM PDT 24
Finished Apr 30 12:43:55 PM PDT 24
Peak memory 211264 kb
Host smart-e77a0041-d062-4a58-af08-556af9d7e451
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2491367036 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_max_throughput_chk.2491367036
Directory /workspace/42.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/42.rom_ctrl_smoke.3357628849
Short name T227
Test name
Test status
Simulation time 3559631840 ps
CPU time 30.22 seconds
Started Apr 30 12:43:47 PM PDT 24
Finished Apr 30 12:44:18 PM PDT 24
Peak memory 213452 kb
Host smart-01d452b0-4cf7-4061-9a6e-0c921a076aa9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3357628849 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_smoke.3357628849
Directory /workspace/42.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/42.rom_ctrl_stress_all.2066475444
Short name T301
Test name
Test status
Simulation time 4178460392 ps
CPU time 41.06 seconds
Started Apr 30 12:43:48 PM PDT 24
Finished Apr 30 12:44:30 PM PDT 24
Peak memory 213320 kb
Host smart-1525021d-e814-4f33-a6a6-b8b76bf1220c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2066475444 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 42.rom_ctrl_stress_all.2066475444
Directory /workspace/42.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/43.rom_ctrl_alert_test.2909592522
Short name T137
Test name
Test status
Simulation time 416130799 ps
CPU time 4.29 seconds
Started Apr 30 12:43:57 PM PDT 24
Finished Apr 30 12:44:02 PM PDT 24
Peak memory 211376 kb
Host smart-312a7004-bf73-4983-8681-c6dd48e9e76e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2909592522 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_alert_test.2909592522
Directory /workspace/43.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/43.rom_ctrl_corrupt_sig_fatal_chk.3927156512
Short name T284
Test name
Test status
Simulation time 117752158281 ps
CPU time 306.6 seconds
Started Apr 30 12:43:55 PM PDT 24
Finished Apr 30 12:49:02 PM PDT 24
Peak memory 233160 kb
Host smart-93219bf2-926c-4eb8-b827-e11723512d2d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3927156512 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_
corrupt_sig_fatal_chk.3927156512
Directory /workspace/43.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/43.rom_ctrl_kmac_err_chk.2349805435
Short name T146
Test name
Test status
Simulation time 1664384114 ps
CPU time 19.19 seconds
Started Apr 30 12:43:55 PM PDT 24
Finished Apr 30 12:44:15 PM PDT 24
Peak memory 212056 kb
Host smart-0b637c65-3a13-4bb8-ac69-552b24e0df6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2349805435 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_kmac_err_chk.2349805435
Directory /workspace/43.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/43.rom_ctrl_max_throughput_chk.3292995886
Short name T354
Test name
Test status
Simulation time 189966657 ps
CPU time 5.57 seconds
Started Apr 30 12:44:00 PM PDT 24
Finished Apr 30 12:44:06 PM PDT 24
Peak memory 211292 kb
Host smart-acc33727-f78d-473a-88f7-6896de91a1a6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3292995886 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_max_throughput_chk.3292995886
Directory /workspace/43.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/43.rom_ctrl_smoke.3411096
Short name T97
Test name
Test status
Simulation time 368438801 ps
CPU time 10.41 seconds
Started Apr 30 12:43:46 PM PDT 24
Finished Apr 30 12:43:56 PM PDT 24
Peak memory 213584 kb
Host smart-10e3d7c0-8a88-460c-ad94-8c6bcaff6589
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3411096 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_smoke.3411096
Directory /workspace/43.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/43.rom_ctrl_stress_all.4095953924
Short name T362
Test name
Test status
Simulation time 2127712556 ps
CPU time 21.26 seconds
Started Apr 30 12:43:48 PM PDT 24
Finished Apr 30 12:44:10 PM PDT 24
Peak memory 216388 kb
Host smart-eaf27939-164e-41fa-8165-de7732e29e3c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4095953924 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 43.rom_ctrl_stress_all.4095953924
Directory /workspace/43.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/43.rom_ctrl_stress_all_with_rand_reset.1261024096
Short name T308
Test name
Test status
Simulation time 79119239686 ps
CPU time 5202.21 seconds
Started Apr 30 12:43:55 PM PDT 24
Finished Apr 30 02:10:39 PM PDT 24
Peak memory 228348 kb
Host smart-b51e984f-21c3-460a-8327-07666f78a330
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1261024096 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_stress_all_with_rand_reset.1261024096
Directory /workspace/43.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.rom_ctrl_alert_test.3264200146
Short name T141
Test name
Test status
Simulation time 8635467546 ps
CPU time 15.92 seconds
Started Apr 30 12:44:03 PM PDT 24
Finished Apr 30 12:44:19 PM PDT 24
Peak memory 211400 kb
Host smart-92e9c9b4-973e-4c59-8ca5-d03a7db7ac51
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3264200146 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_alert_test.3264200146
Directory /workspace/44.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/44.rom_ctrl_corrupt_sig_fatal_chk.1341375059
Short name T219
Test name
Test status
Simulation time 28168813698 ps
CPU time 180.4 seconds
Started Apr 30 12:43:54 PM PDT 24
Finished Apr 30 12:46:55 PM PDT 24
Peak memory 228692 kb
Host smart-d9f14e2d-183c-4cb2-9ae1-79ad1084684c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1341375059 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_
corrupt_sig_fatal_chk.1341375059
Directory /workspace/44.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/44.rom_ctrl_kmac_err_chk.2246092985
Short name T162
Test name
Test status
Simulation time 5582548197 ps
CPU time 18.25 seconds
Started Apr 30 12:44:02 PM PDT 24
Finished Apr 30 12:44:21 PM PDT 24
Peak memory 212380 kb
Host smart-11f7bfe4-7867-4ab5-9a60-85a0480e2e5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2246092985 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_kmac_err_chk.2246092985
Directory /workspace/44.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/44.rom_ctrl_max_throughput_chk.2467113077
Short name T229
Test name
Test status
Simulation time 360023950 ps
CPU time 6.76 seconds
Started Apr 30 12:44:01 PM PDT 24
Finished Apr 30 12:44:08 PM PDT 24
Peak memory 211292 kb
Host smart-666fae40-4774-4e17-8344-1d69e76135a2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2467113077 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_max_throughput_chk.2467113077
Directory /workspace/44.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/44.rom_ctrl_smoke.1243038842
Short name T156
Test name
Test status
Simulation time 370500651 ps
CPU time 10.01 seconds
Started Apr 30 12:43:55 PM PDT 24
Finished Apr 30 12:44:05 PM PDT 24
Peak memory 219568 kb
Host smart-af840e2c-cbef-433f-b8d9-9d1fb3752383
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1243038842 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_smoke.1243038842
Directory /workspace/44.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/44.rom_ctrl_stress_all.1984858534
Short name T224
Test name
Test status
Simulation time 206470214 ps
CPU time 10.1 seconds
Started Apr 30 12:43:55 PM PDT 24
Finished Apr 30 12:44:06 PM PDT 24
Peak memory 219504 kb
Host smart-8b0926fa-d763-49d1-aba7-8e0950bb473f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1984858534 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 44.rom_ctrl_stress_all.1984858534
Directory /workspace/44.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/45.rom_ctrl_alert_test.364190602
Short name T127
Test name
Test status
Simulation time 1905292332 ps
CPU time 10.05 seconds
Started Apr 30 12:43:56 PM PDT 24
Finished Apr 30 12:44:07 PM PDT 24
Peak memory 211376 kb
Host smart-bfc0ef9d-4362-4dc0-bfa7-23e4aaf09f38
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=364190602 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_alert_test.364190602
Directory /workspace/45.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/45.rom_ctrl_corrupt_sig_fatal_chk.516523174
Short name T28
Test name
Test status
Simulation time 8382993090 ps
CPU time 127.09 seconds
Started Apr 30 12:44:01 PM PDT 24
Finished Apr 30 12:46:09 PM PDT 24
Peak memory 235048 kb
Host smart-fc327988-d110-40a1-a9d8-c75cb7d79756
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=516523174 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_c
orrupt_sig_fatal_chk.516523174
Directory /workspace/45.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/45.rom_ctrl_kmac_err_chk.2633717708
Short name T239
Test name
Test status
Simulation time 10794681736 ps
CPU time 25.66 seconds
Started Apr 30 12:44:00 PM PDT 24
Finished Apr 30 12:44:26 PM PDT 24
Peak memory 212272 kb
Host smart-efb6553a-5336-41b1-ba6f-4df81f1d9a62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2633717708 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_kmac_err_chk.2633717708
Directory /workspace/45.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/45.rom_ctrl_max_throughput_chk.3461949471
Short name T152
Test name
Test status
Simulation time 349035037 ps
CPU time 5.45 seconds
Started Apr 30 12:43:56 PM PDT 24
Finished Apr 30 12:44:02 PM PDT 24
Peak memory 211400 kb
Host smart-20251ac1-a338-4b00-a5bc-1778e0317954
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3461949471 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_max_throughput_chk.3461949471
Directory /workspace/45.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/45.rom_ctrl_smoke.2720651383
Short name T124
Test name
Test status
Simulation time 477487918 ps
CPU time 9.95 seconds
Started Apr 30 12:43:56 PM PDT 24
Finished Apr 30 12:44:07 PM PDT 24
Peak memory 219600 kb
Host smart-23316efe-340e-48c9-97b1-2943e24a99a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2720651383 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_smoke.2720651383
Directory /workspace/45.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/45.rom_ctrl_stress_all.3714142910
Short name T324
Test name
Test status
Simulation time 6928489107 ps
CPU time 61.53 seconds
Started Apr 30 12:43:55 PM PDT 24
Finished Apr 30 12:44:58 PM PDT 24
Peak memory 219644 kb
Host smart-8a782084-b3eb-4bc0-80df-3e7ca8d45c55
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3714142910 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 45.rom_ctrl_stress_all.3714142910
Directory /workspace/45.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/46.rom_ctrl_alert_test.2103353944
Short name T165
Test name
Test status
Simulation time 174829001 ps
CPU time 4.24 seconds
Started Apr 30 12:43:55 PM PDT 24
Finished Apr 30 12:43:59 PM PDT 24
Peak memory 211352 kb
Host smart-4e2279da-ccf3-48b7-883a-43f5fe1eb222
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2103353944 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_alert_test.2103353944
Directory /workspace/46.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/46.rom_ctrl_corrupt_sig_fatal_chk.462736240
Short name T316
Test name
Test status
Simulation time 82392041536 ps
CPU time 356.84 seconds
Started Apr 30 12:43:54 PM PDT 24
Finished Apr 30 12:49:52 PM PDT 24
Peak memory 213424 kb
Host smart-01867c04-9cf1-444a-acc1-8522713592c0
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=462736240 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_c
orrupt_sig_fatal_chk.462736240
Directory /workspace/46.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/46.rom_ctrl_kmac_err_chk.3836038930
Short name T292
Test name
Test status
Simulation time 1776791740 ps
CPU time 15.69 seconds
Started Apr 30 12:43:56 PM PDT 24
Finished Apr 30 12:44:13 PM PDT 24
Peak memory 212032 kb
Host smart-25912324-5eac-4dc4-8d0c-49f904918436
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3836038930 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_kmac_err_chk.3836038930
Directory /workspace/46.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/46.rom_ctrl_max_throughput_chk.3590776115
Short name T297
Test name
Test status
Simulation time 716104519 ps
CPU time 9.76 seconds
Started Apr 30 12:43:54 PM PDT 24
Finished Apr 30 12:44:05 PM PDT 24
Peak memory 211320 kb
Host smart-69ab7aa9-15eb-4709-947c-76a5c3407d27
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3590776115 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_max_throughput_chk.3590776115
Directory /workspace/46.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/46.rom_ctrl_smoke.1806226528
Short name T222
Test name
Test status
Simulation time 6859037667 ps
CPU time 29.06 seconds
Started Apr 30 12:43:54 PM PDT 24
Finished Apr 30 12:44:23 PM PDT 24
Peak memory 214872 kb
Host smart-7003564c-b4e0-4d54-b927-bda48b1eb2b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1806226528 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_smoke.1806226528
Directory /workspace/46.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/46.rom_ctrl_stress_all.3055687803
Short name T38
Test name
Test status
Simulation time 8029480489 ps
CPU time 21.89 seconds
Started Apr 30 12:44:03 PM PDT 24
Finished Apr 30 12:44:26 PM PDT 24
Peak memory 219576 kb
Host smart-fe3ab107-7d52-4f75-b8e0-cec19506cf3d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3055687803 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 46.rom_ctrl_stress_all.3055687803
Directory /workspace/46.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/46.rom_ctrl_stress_all_with_rand_reset.1373490045
Short name T335
Test name
Test status
Simulation time 16926597016 ps
CPU time 5653.65 seconds
Started Apr 30 12:43:55 PM PDT 24
Finished Apr 30 02:18:10 PM PDT 24
Peak memory 236068 kb
Host smart-d90f96d5-e15e-4bd4-a243-bf5fc8571b82
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1373490045 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_stress_all_with_rand_reset.1373490045
Directory /workspace/46.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.rom_ctrl_alert_test.577155703
Short name T62
Test name
Test status
Simulation time 8680103352 ps
CPU time 14.5 seconds
Started Apr 30 12:44:05 PM PDT 24
Finished Apr 30 12:44:20 PM PDT 24
Peak memory 211388 kb
Host smart-c11b51cf-5f2a-4655-92e3-7056aac029d4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=577155703 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_alert_test.577155703
Directory /workspace/47.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/47.rom_ctrl_corrupt_sig_fatal_chk.3158030413
Short name T29
Test name
Test status
Simulation time 7793231063 ps
CPU time 119.13 seconds
Started Apr 30 12:44:09 PM PDT 24
Finished Apr 30 12:46:08 PM PDT 24
Peak memory 238064 kb
Host smart-09f4b5f8-3787-4fe6-b510-29e62b667507
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3158030413 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_
corrupt_sig_fatal_chk.3158030413
Directory /workspace/47.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/47.rom_ctrl_kmac_err_chk.2444565751
Short name T166
Test name
Test status
Simulation time 10651777311 ps
CPU time 23.88 seconds
Started Apr 30 12:44:06 PM PDT 24
Finished Apr 30 12:44:30 PM PDT 24
Peak memory 211464 kb
Host smart-e00be0b2-3719-43e6-acf8-fa1d8f2bda77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2444565751 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_kmac_err_chk.2444565751
Directory /workspace/47.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/47.rom_ctrl_max_throughput_chk.558024881
Short name T169
Test name
Test status
Simulation time 380246065 ps
CPU time 5.59 seconds
Started Apr 30 12:44:02 PM PDT 24
Finished Apr 30 12:44:08 PM PDT 24
Peak memory 211332 kb
Host smart-9f5bd87e-5999-4bbd-b768-d6662f9cb008
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=558024881 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_max_throughput_chk.558024881
Directory /workspace/47.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/47.rom_ctrl_smoke.2977067287
Short name T311
Test name
Test status
Simulation time 11539985295 ps
CPU time 29.86 seconds
Started Apr 30 12:43:56 PM PDT 24
Finished Apr 30 12:44:26 PM PDT 24
Peak memory 219596 kb
Host smart-85b59896-7962-4b92-9723-e212ebd958dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2977067287 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_smoke.2977067287
Directory /workspace/47.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/47.rom_ctrl_stress_all.1098032040
Short name T226
Test name
Test status
Simulation time 6706844175 ps
CPU time 56.81 seconds
Started Apr 30 12:43:55 PM PDT 24
Finished Apr 30 12:44:52 PM PDT 24
Peak memory 217572 kb
Host smart-86971965-de10-4ae2-9bdc-5f33aef48696
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1098032040 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 47.rom_ctrl_stress_all.1098032040
Directory /workspace/47.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/48.rom_ctrl_alert_test.2461141441
Short name T161
Test name
Test status
Simulation time 2663639201 ps
CPU time 11.87 seconds
Started Apr 30 12:44:02 PM PDT 24
Finished Apr 30 12:44:14 PM PDT 24
Peak memory 211484 kb
Host smart-f340ada5-3adc-41bb-b1ab-856bbb3087ac
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2461141441 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_alert_test.2461141441
Directory /workspace/48.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/48.rom_ctrl_corrupt_sig_fatal_chk.3162231705
Short name T343
Test name
Test status
Simulation time 37093070282 ps
CPU time 168.22 seconds
Started Apr 30 12:44:08 PM PDT 24
Finished Apr 30 12:46:56 PM PDT 24
Peak memory 230104 kb
Host smart-a9b22455-e607-401d-9074-bdfa8dbde934
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3162231705 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_
corrupt_sig_fatal_chk.3162231705
Directory /workspace/48.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/48.rom_ctrl_kmac_err_chk.3982281533
Short name T158
Test name
Test status
Simulation time 4209388586 ps
CPU time 33.24 seconds
Started Apr 30 12:44:11 PM PDT 24
Finished Apr 30 12:44:45 PM PDT 24
Peak memory 212116 kb
Host smart-c79347af-6e7b-416b-bd51-9cef230fcafc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3982281533 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_kmac_err_chk.3982281533
Directory /workspace/48.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/48.rom_ctrl_max_throughput_chk.1214823323
Short name T221
Test name
Test status
Simulation time 1139353601 ps
CPU time 9.17 seconds
Started Apr 30 12:44:04 PM PDT 24
Finished Apr 30 12:44:13 PM PDT 24
Peak memory 211332 kb
Host smart-f994c777-869a-43a7-aacd-e61e2d4bcadb
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1214823323 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_max_throughput_chk.1214823323
Directory /workspace/48.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/48.rom_ctrl_smoke.2070150029
Short name T131
Test name
Test status
Simulation time 352799371 ps
CPU time 12.65 seconds
Started Apr 30 12:44:03 PM PDT 24
Finished Apr 30 12:44:16 PM PDT 24
Peak memory 213536 kb
Host smart-03106c45-2551-4f7d-b41d-d1a3c058f3e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2070150029 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_smoke.2070150029
Directory /workspace/48.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/48.rom_ctrl_stress_all.1636934290
Short name T339
Test name
Test status
Simulation time 8046633663 ps
CPU time 86.78 seconds
Started Apr 30 12:44:09 PM PDT 24
Finished Apr 30 12:45:36 PM PDT 24
Peak memory 217212 kb
Host smart-c17d940f-b4f9-474f-9ad1-095ecdf565d9
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1636934290 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 48.rom_ctrl_stress_all.1636934290
Directory /workspace/48.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/49.rom_ctrl_alert_test.2883943641
Short name T309
Test name
Test status
Simulation time 3934310098 ps
CPU time 10.31 seconds
Started Apr 30 12:44:07 PM PDT 24
Finished Apr 30 12:44:18 PM PDT 24
Peak memory 211428 kb
Host smart-f6260740-5065-4865-bfe4-e96f5a8dc275
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2883943641 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_alert_test.2883943641
Directory /workspace/49.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/49.rom_ctrl_corrupt_sig_fatal_chk.1580305452
Short name T353
Test name
Test status
Simulation time 6692007321 ps
CPU time 89.72 seconds
Started Apr 30 12:44:03 PM PDT 24
Finished Apr 30 12:45:33 PM PDT 24
Peak memory 212752 kb
Host smart-0299a67f-8aaf-42b0-8ae8-4d4dace0d7c0
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1580305452 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_
corrupt_sig_fatal_chk.1580305452
Directory /workspace/49.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/49.rom_ctrl_kmac_err_chk.175689213
Short name T249
Test name
Test status
Simulation time 1186748728 ps
CPU time 9.33 seconds
Started Apr 30 12:44:04 PM PDT 24
Finished Apr 30 12:44:13 PM PDT 24
Peak memory 212120 kb
Host smart-60f58e89-7cd2-4857-ae45-e029b31d5cf2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=175689213 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_kmac_err_chk.175689213
Directory /workspace/49.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/49.rom_ctrl_max_throughput_chk.827662891
Short name T149
Test name
Test status
Simulation time 394313541 ps
CPU time 5.47 seconds
Started Apr 30 12:44:03 PM PDT 24
Finished Apr 30 12:44:09 PM PDT 24
Peak memory 211344 kb
Host smart-e098815b-9aaa-444f-a7ae-7670a4e43af4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=827662891 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_max_throughput_chk.827662891
Directory /workspace/49.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/49.rom_ctrl_smoke.3708435332
Short name T244
Test name
Test status
Simulation time 6950784209 ps
CPU time 24.15 seconds
Started Apr 30 12:44:07 PM PDT 24
Finished Apr 30 12:44:32 PM PDT 24
Peak memory 214332 kb
Host smart-2b4865cd-55af-4500-9b23-f346e754b100
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3708435332 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_smoke.3708435332
Directory /workspace/49.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/49.rom_ctrl_stress_all.1305196967
Short name T315
Test name
Test status
Simulation time 5054620976 ps
CPU time 34.33 seconds
Started Apr 30 12:44:02 PM PDT 24
Finished Apr 30 12:44:37 PM PDT 24
Peak memory 219532 kb
Host smart-e9c22c21-351b-4482-85ae-2c5da093bff4
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1305196967 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 49.rom_ctrl_stress_all.1305196967
Directory /workspace/49.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/5.rom_ctrl_alert_test.2514928143
Short name T264
Test name
Test status
Simulation time 1759975298 ps
CPU time 14.23 seconds
Started Apr 30 12:42:20 PM PDT 24
Finished Apr 30 12:42:35 PM PDT 24
Peak memory 211444 kb
Host smart-0e3d1011-807a-4ba6-84b9-bfa6a2c5699c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2514928143 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_alert_test.2514928143
Directory /workspace/5.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/5.rom_ctrl_corrupt_sig_fatal_chk.2259255574
Short name T274
Test name
Test status
Simulation time 15703245294 ps
CPU time 116.75 seconds
Started Apr 30 12:42:20 PM PDT 24
Finished Apr 30 12:44:18 PM PDT 24
Peak memory 237368 kb
Host smart-a1923f3b-8d54-404e-8f97-0b895e0cb41c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2259255574 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_c
orrupt_sig_fatal_chk.2259255574
Directory /workspace/5.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/5.rom_ctrl_kmac_err_chk.1028479143
Short name T260
Test name
Test status
Simulation time 3208530823 ps
CPU time 27.53 seconds
Started Apr 30 12:42:20 PM PDT 24
Finished Apr 30 12:42:48 PM PDT 24
Peak memory 212116 kb
Host smart-5bd2f8bc-22fc-42cb-bf92-f8e759efb9d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1028479143 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_kmac_err_chk.1028479143
Directory /workspace/5.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/5.rom_ctrl_max_throughput_chk.1904675942
Short name T43
Test name
Test status
Simulation time 562688443 ps
CPU time 9.01 seconds
Started Apr 30 12:42:23 PM PDT 24
Finished Apr 30 12:42:32 PM PDT 24
Peak memory 211352 kb
Host smart-57198f3e-eae3-4051-8b5c-b4ef36ca73be
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1904675942 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_max_throughput_chk.1904675942
Directory /workspace/5.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/5.rom_ctrl_smoke.1776395312
Short name T172
Test name
Test status
Simulation time 2157363372 ps
CPU time 12.11 seconds
Started Apr 30 12:42:20 PM PDT 24
Finished Apr 30 12:42:33 PM PDT 24
Peak memory 219596 kb
Host smart-b126ddbd-0cc1-4dbf-a83c-e1f0daba6590
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1776395312 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_smoke.1776395312
Directory /workspace/5.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/5.rom_ctrl_stress_all.2743288045
Short name T255
Test name
Test status
Simulation time 1467913235 ps
CPU time 19.13 seconds
Started Apr 30 12:42:20 PM PDT 24
Finished Apr 30 12:42:40 PM PDT 24
Peak memory 219472 kb
Host smart-da139b2c-76ce-4b22-9813-929ab74f957d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2743288045 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 5.rom_ctrl_stress_all.2743288045
Directory /workspace/5.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/5.rom_ctrl_stress_all_with_rand_reset.2506641830
Short name T51
Test name
Test status
Simulation time 105602749031 ps
CPU time 486.23 seconds
Started Apr 30 12:42:21 PM PDT 24
Finished Apr 30 12:50:28 PM PDT 24
Peak memory 236136 kb
Host smart-11d9d27f-6d34-4c61-8cc3-7fbc3ed96d49
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2506641830 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_stress_all_with_rand_reset.2506641830
Directory /workspace/5.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.rom_ctrl_alert_test.1790560539
Short name T253
Test name
Test status
Simulation time 1063207155 ps
CPU time 11 seconds
Started Apr 30 12:42:19 PM PDT 24
Finished Apr 30 12:42:31 PM PDT 24
Peak memory 211364 kb
Host smart-35d7c0e2-8eac-4b7c-b5db-4c9e1f19a2ec
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1790560539 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_alert_test.1790560539
Directory /workspace/6.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/6.rom_ctrl_kmac_err_chk.4051625968
Short name T291
Test name
Test status
Simulation time 914678947 ps
CPU time 15.71 seconds
Started Apr 30 12:42:21 PM PDT 24
Finished Apr 30 12:42:38 PM PDT 24
Peak memory 211884 kb
Host smart-3b87474b-aae3-482e-8db2-4223bcf61406
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4051625968 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_kmac_err_chk.4051625968
Directory /workspace/6.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/6.rom_ctrl_max_throughput_chk.1532984511
Short name T13
Test name
Test status
Simulation time 910894381 ps
CPU time 10.89 seconds
Started Apr 30 12:42:21 PM PDT 24
Finished Apr 30 12:42:33 PM PDT 24
Peak memory 211388 kb
Host smart-24a1a15a-356e-4ff9-8962-847ea4badeb3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1532984511 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_max_throughput_chk.1532984511
Directory /workspace/6.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/6.rom_ctrl_smoke.2019093693
Short name T126
Test name
Test status
Simulation time 3169598333 ps
CPU time 19.56 seconds
Started Apr 30 12:42:21 PM PDT 24
Finished Apr 30 12:42:41 PM PDT 24
Peak memory 219700 kb
Host smart-fb293091-6b47-452b-bc03-025e2f507f51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2019093693 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_smoke.2019093693
Directory /workspace/6.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/6.rom_ctrl_stress_all.452073368
Short name T248
Test name
Test status
Simulation time 6597674748 ps
CPU time 35.94 seconds
Started Apr 30 12:42:29 PM PDT 24
Finished Apr 30 12:43:05 PM PDT 24
Peak memory 216996 kb
Host smart-143fcb23-cf1e-49ee-b358-48aea585bd99
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=452073368 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 6.rom_ctrl_stress_all.452073368
Directory /workspace/6.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/6.rom_ctrl_stress_all_with_rand_reset.2801068376
Short name T56
Test name
Test status
Simulation time 266298612207 ps
CPU time 2428 seconds
Started Apr 30 12:42:23 PM PDT 24
Finished Apr 30 01:22:52 PM PDT 24
Peak memory 239532 kb
Host smart-39b58a2e-68dd-43de-97c4-3e4ebb204da3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2801068376 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_stress_all_with_rand_reset.2801068376
Directory /workspace/6.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.rom_ctrl_alert_test.1376852672
Short name T337
Test name
Test status
Simulation time 347651833 ps
CPU time 4.06 seconds
Started Apr 30 12:42:31 PM PDT 24
Finished Apr 30 12:42:36 PM PDT 24
Peak memory 211400 kb
Host smart-44e40cbc-a127-4d72-b348-11e3fb44e417
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1376852672 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_alert_test.1376852672
Directory /workspace/7.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/7.rom_ctrl_corrupt_sig_fatal_chk.1498098253
Short name T252
Test name
Test status
Simulation time 6323234775 ps
CPU time 95.78 seconds
Started Apr 30 12:42:22 PM PDT 24
Finished Apr 30 12:43:58 PM PDT 24
Peak memory 228700 kb
Host smart-85375cde-061d-497a-b556-0c295d506261
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1498098253 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_c
orrupt_sig_fatal_chk.1498098253
Directory /workspace/7.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/7.rom_ctrl_kmac_err_chk.2825117102
Short name T346
Test name
Test status
Simulation time 7883219740 ps
CPU time 21.7 seconds
Started Apr 30 12:42:22 PM PDT 24
Finished Apr 30 12:42:45 PM PDT 24
Peak memory 212616 kb
Host smart-ea8af608-4cd3-4d99-b015-566f6c376f08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2825117102 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_kmac_err_chk.2825117102
Directory /workspace/7.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/7.rom_ctrl_max_throughput_chk.3316586624
Short name T106
Test name
Test status
Simulation time 2109354091 ps
CPU time 16.64 seconds
Started Apr 30 12:42:20 PM PDT 24
Finished Apr 30 12:42:37 PM PDT 24
Peak memory 211264 kb
Host smart-2fdcdf34-b31b-4f1b-bf97-344b75675a41
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3316586624 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_max_throughput_chk.3316586624
Directory /workspace/7.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/7.rom_ctrl_smoke.913876086
Short name T234
Test name
Test status
Simulation time 4976219835 ps
CPU time 17.22 seconds
Started Apr 30 12:42:25 PM PDT 24
Finished Apr 30 12:42:43 PM PDT 24
Peak memory 213908 kb
Host smart-82bd982d-c9bf-4ef0-9d68-9ae98f173bf0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=913876086 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_smoke.913876086
Directory /workspace/7.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/8.rom_ctrl_alert_test.2527885484
Short name T223
Test name
Test status
Simulation time 1710005383 ps
CPU time 14.37 seconds
Started Apr 30 12:42:31 PM PDT 24
Finished Apr 30 12:42:46 PM PDT 24
Peak memory 211360 kb
Host smart-d80f0fdb-266b-443f-982b-b1a108b293fc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2527885484 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_alert_test.2527885484
Directory /workspace/8.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/8.rom_ctrl_corrupt_sig_fatal_chk.3608939900
Short name T280
Test name
Test status
Simulation time 114485643381 ps
CPU time 296.83 seconds
Started Apr 30 12:42:29 PM PDT 24
Finished Apr 30 12:47:26 PM PDT 24
Peak memory 238188 kb
Host smart-56a1849f-0f72-407e-849d-3ee6b20d0963
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3608939900 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_c
orrupt_sig_fatal_chk.3608939900
Directory /workspace/8.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/8.rom_ctrl_kmac_err_chk.3032426279
Short name T129
Test name
Test status
Simulation time 1044251831 ps
CPU time 15.78 seconds
Started Apr 30 12:42:31 PM PDT 24
Finished Apr 30 12:42:48 PM PDT 24
Peak memory 212060 kb
Host smart-f5f6ab94-b375-4ca7-8445-631034a60e66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3032426279 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_kmac_err_chk.3032426279
Directory /workspace/8.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/8.rom_ctrl_max_throughput_chk.307512424
Short name T319
Test name
Test status
Simulation time 5966710090 ps
CPU time 14.95 seconds
Started Apr 30 12:42:30 PM PDT 24
Finished Apr 30 12:42:45 PM PDT 24
Peak memory 211368 kb
Host smart-59e190e8-5da6-4f60-9e06-9a0f57c63005
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=307512424 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_max_throughput_chk.307512424
Directory /workspace/8.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/8.rom_ctrl_smoke.2069150811
Short name T304
Test name
Test status
Simulation time 12605005567 ps
CPU time 26.56 seconds
Started Apr 30 12:42:31 PM PDT 24
Finished Apr 30 12:42:58 PM PDT 24
Peak memory 214640 kb
Host smart-aca45f3f-edf2-44c1-86c1-c6be40de9fa6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2069150811 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_smoke.2069150811
Directory /workspace/8.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/8.rom_ctrl_stress_all.3815361800
Short name T307
Test name
Test status
Simulation time 59915217195 ps
CPU time 41.94 seconds
Started Apr 30 12:42:30 PM PDT 24
Finished Apr 30 12:43:12 PM PDT 24
Peak memory 219564 kb
Host smart-8d576b22-284e-49f3-ba73-bf9a0818b997
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3815361800 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 8.rom_ctrl_stress_all.3815361800
Directory /workspace/8.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/9.rom_ctrl_alert_test.3801987326
Short name T34
Test name
Test status
Simulation time 110029619 ps
CPU time 4.12 seconds
Started Apr 30 12:42:33 PM PDT 24
Finished Apr 30 12:42:38 PM PDT 24
Peak memory 211444 kb
Host smart-5c8e9761-a45d-4da6-b3cf-1cf991f11ebc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3801987326 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_alert_test.3801987326
Directory /workspace/9.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/9.rom_ctrl_corrupt_sig_fatal_chk.3646297967
Short name T49
Test name
Test status
Simulation time 373129690365 ps
CPU time 435.41 seconds
Started Apr 30 12:42:29 PM PDT 24
Finished Apr 30 12:49:45 PM PDT 24
Peak memory 235148 kb
Host smart-89238b7f-83a2-459b-9a1b-51c1a6cfda79
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3646297967 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_c
orrupt_sig_fatal_chk.3646297967
Directory /workspace/9.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/9.rom_ctrl_kmac_err_chk.2031135896
Short name T312
Test name
Test status
Simulation time 303814915 ps
CPU time 9.44 seconds
Started Apr 30 12:42:29 PM PDT 24
Finished Apr 30 12:42:39 PM PDT 24
Peak memory 212172 kb
Host smart-baedee30-a598-49cb-ba45-c7de5b092e64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2031135896 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_kmac_err_chk.2031135896
Directory /workspace/9.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/9.rom_ctrl_max_throughput_chk.3047129647
Short name T303
Test name
Test status
Simulation time 1713387219 ps
CPU time 14.6 seconds
Started Apr 30 12:42:33 PM PDT 24
Finished Apr 30 12:42:48 PM PDT 24
Peak memory 211356 kb
Host smart-8c41a26a-ba1f-4681-ab60-fc883a104890
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3047129647 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_max_throughput_chk.3047129647
Directory /workspace/9.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/9.rom_ctrl_smoke.3152200564
Short name T130
Test name
Test status
Simulation time 3767050473 ps
CPU time 34.21 seconds
Started Apr 30 12:42:30 PM PDT 24
Finished Apr 30 12:43:04 PM PDT 24
Peak memory 219644 kb
Host smart-72091f05-494d-4109-98ad-bc04afd0338e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3152200564 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_smoke.3152200564
Directory /workspace/9.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/9.rom_ctrl_stress_all.4286760471
Short name T153
Test name
Test status
Simulation time 2166037725 ps
CPU time 18.49 seconds
Started Apr 30 12:42:33 PM PDT 24
Finished Apr 30 12:42:52 PM PDT 24
Peak memory 211988 kb
Host smart-a2788511-955c-405e-a8a0-440dd6b42c0b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4286760471 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 9.rom_ctrl_stress_all.4286760471
Directory /workspace/9.rom_ctrl_stress_all/latest
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