| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
| 97.62 | 96.97 | 93.01 | 97.88 | 100.00 | 98.37 | 98.03 | 99.07 |
| T301 | /workspace/coverage/default/19.rom_ctrl_corrupt_sig_fatal_chk.203979152 | May 05 12:46:20 PM PDT 24 | May 05 12:48:11 PM PDT 24 | 34000401044 ps | ||
| T302 | /workspace/coverage/default/15.rom_ctrl_max_throughput_chk.1748651379 | May 05 12:46:20 PM PDT 24 | May 05 12:46:35 PM PDT 24 | 13472220553 ps | ||
| T303 | /workspace/coverage/default/34.rom_ctrl_corrupt_sig_fatal_chk.1485411096 | May 05 12:46:48 PM PDT 24 | May 05 12:48:14 PM PDT 24 | 4510470673 ps | ||
| T304 | /workspace/coverage/default/22.rom_ctrl_max_throughput_chk.1103957015 | May 05 12:46:27 PM PDT 24 | May 05 12:46:33 PM PDT 24 | 386663301 ps | ||
| T305 | /workspace/coverage/default/10.rom_ctrl_corrupt_sig_fatal_chk.2018022233 | May 05 12:46:09 PM PDT 24 | May 05 12:51:38 PM PDT 24 | 103891145821 ps | ||
| T306 | /workspace/coverage/default/7.rom_ctrl_stress_all.2726460838 | May 05 12:46:06 PM PDT 24 | May 05 12:46:19 PM PDT 24 | 202678782 ps | ||
| T307 | /workspace/coverage/default/7.rom_ctrl_alert_test.1304537661 | May 05 12:46:06 PM PDT 24 | May 05 12:46:22 PM PDT 24 | 3919938600 ps | ||
| T308 | /workspace/coverage/default/12.rom_ctrl_stress_all.3271922609 | May 05 12:46:14 PM PDT 24 | May 05 12:48:33 PM PDT 24 | 60629122708 ps | ||
| T309 | /workspace/coverage/default/2.rom_ctrl_max_throughput_chk.1292186790 | May 05 12:46:13 PM PDT 24 | May 05 12:46:19 PM PDT 24 | 96659133 ps | ||
| T310 | /workspace/coverage/default/5.rom_ctrl_smoke.2590500405 | May 05 12:46:14 PM PDT 24 | May 05 12:46:37 PM PDT 24 | 1160865917 ps | ||
| T311 | /workspace/coverage/default/48.rom_ctrl_stress_all.1677623956 | May 05 12:47:16 PM PDT 24 | May 05 12:47:35 PM PDT 24 | 11581678973 ps | ||
| T312 | /workspace/coverage/default/43.rom_ctrl_max_throughput_chk.1844123744 | May 05 12:47:10 PM PDT 24 | May 05 12:47:23 PM PDT 24 | 1210546420 ps | ||
| T313 | /workspace/coverage/default/0.rom_ctrl_corrupt_sig_fatal_chk.2124508860 | May 05 12:46:11 PM PDT 24 | May 05 12:47:15 PM PDT 24 | 4248499896 ps | ||
| T314 | /workspace/coverage/default/42.rom_ctrl_stress_all.1468048184 | May 05 12:47:05 PM PDT 24 | May 05 12:47:24 PM PDT 24 | 3722592945 ps | ||
| T315 | /workspace/coverage/default/34.rom_ctrl_stress_all.286912306 | May 05 12:46:56 PM PDT 24 | May 05 12:47:11 PM PDT 24 | 3148377337 ps | ||
| T316 | /workspace/coverage/default/30.rom_ctrl_stress_all.495882393 | May 05 12:46:47 PM PDT 24 | May 05 12:47:32 PM PDT 24 | 5468770103 ps | ||
| T317 | /workspace/coverage/default/33.rom_ctrl_smoke.3165666976 | May 05 12:46:48 PM PDT 24 | May 05 12:47:12 PM PDT 24 | 4244355006 ps | ||
| T26 | /workspace/coverage/default/48.rom_ctrl_kmac_err_chk.1470995415 | May 05 12:47:12 PM PDT 24 | May 05 12:47:49 PM PDT 24 | 4249207359 ps | ||
| T318 | /workspace/coverage/default/48.rom_ctrl_max_throughput_chk.989428384 | May 05 12:47:10 PM PDT 24 | May 05 12:47:26 PM PDT 24 | 1716241520 ps | ||
| T319 | /workspace/coverage/default/24.rom_ctrl_stress_all.3814772253 | May 05 12:46:33 PM PDT 24 | May 05 12:46:52 PM PDT 24 | 4194369580 ps | ||
| T320 | /workspace/coverage/default/3.rom_ctrl_smoke.1134835244 | May 05 12:46:08 PM PDT 24 | May 05 12:46:19 PM PDT 24 | 747080937 ps | ||
| T321 | /workspace/coverage/default/45.rom_ctrl_stress_all.3398715195 | May 05 12:47:10 PM PDT 24 | May 05 12:47:56 PM PDT 24 | 4375200720 ps | ||
| T322 | /workspace/coverage/default/22.rom_ctrl_stress_all_with_rand_reset.1698601948 | May 05 12:46:37 PM PDT 24 | May 05 01:24:24 PM PDT 24 | 232686898108 ps | ||
| T323 | /workspace/coverage/default/28.rom_ctrl_kmac_err_chk.3306532516 | May 05 12:46:39 PM PDT 24 | May 05 12:47:11 PM PDT 24 | 7800239480 ps | ||
| T324 | /workspace/coverage/default/23.rom_ctrl_alert_test.2432118308 | May 05 12:46:34 PM PDT 24 | May 05 12:46:45 PM PDT 24 | 4613209154 ps | ||
| T325 | /workspace/coverage/default/44.rom_ctrl_stress_all.952106001 | May 05 12:47:06 PM PDT 24 | May 05 12:47:29 PM PDT 24 | 808890741 ps | ||
| T326 | /workspace/coverage/default/43.rom_ctrl_corrupt_sig_fatal_chk.3776598879 | May 05 12:47:07 PM PDT 24 | May 05 12:54:06 PM PDT 24 | 156677589039 ps | ||
| T327 | /workspace/coverage/default/38.rom_ctrl_max_throughput_chk.673049664 | May 05 12:46:58 PM PDT 24 | May 05 12:47:05 PM PDT 24 | 173077683 ps | ||
| T328 | /workspace/coverage/default/21.rom_ctrl_stress_all.3879833983 | May 05 12:46:28 PM PDT 24 | May 05 12:46:53 PM PDT 24 | 2409178828 ps | ||
| T329 | /workspace/coverage/default/10.rom_ctrl_smoke.1627804638 | May 05 12:46:07 PM PDT 24 | May 05 12:46:44 PM PDT 24 | 6171510017 ps | ||
| T330 | /workspace/coverage/default/20.rom_ctrl_kmac_err_chk.2061336180 | May 05 12:46:28 PM PDT 24 | May 05 12:46:38 PM PDT 24 | 274429783 ps | ||
| T331 | /workspace/coverage/default/1.rom_ctrl_corrupt_sig_fatal_chk.3731916907 | May 05 12:46:11 PM PDT 24 | May 05 12:49:01 PM PDT 24 | 64037462445 ps | ||
| T332 | /workspace/coverage/default/45.rom_ctrl_stress_all_with_rand_reset.3629686583 | May 05 12:47:11 PM PDT 24 | May 05 01:20:31 PM PDT 24 | 144137831480 ps | ||
| T333 | /workspace/coverage/default/30.rom_ctrl_alert_test.4188768625 | May 05 12:46:41 PM PDT 24 | May 05 12:46:47 PM PDT 24 | 1549587354 ps | ||
| T334 | /workspace/coverage/default/39.rom_ctrl_corrupt_sig_fatal_chk.1964375284 | May 05 12:46:59 PM PDT 24 | May 05 12:48:03 PM PDT 24 | 3691222866 ps | ||
| T335 | /workspace/coverage/default/23.rom_ctrl_stress_all_with_rand_reset.3992826286 | May 05 12:46:35 PM PDT 24 | May 05 01:21:35 PM PDT 24 | 54010882065 ps | ||
| T36 | /workspace/coverage/default/4.rom_ctrl_sec_cm.2475496685 | May 05 12:46:06 PM PDT 24 | May 05 12:47:49 PM PDT 24 | 2998508581 ps | ||
| T336 | /workspace/coverage/default/2.rom_ctrl_corrupt_sig_fatal_chk.2625385719 | May 05 12:46:07 PM PDT 24 | May 05 12:50:04 PM PDT 24 | 21592293725 ps | ||
| T337 | /workspace/coverage/default/15.rom_ctrl_corrupt_sig_fatal_chk.2824647690 | May 05 12:46:15 PM PDT 24 | May 05 12:50:43 PM PDT 24 | 72487613136 ps | ||
| T338 | /workspace/coverage/default/49.rom_ctrl_corrupt_sig_fatal_chk.1487280887 | May 05 12:47:16 PM PDT 24 | May 05 12:52:16 PM PDT 24 | 30023910831 ps | ||
| T339 | /workspace/coverage/default/47.rom_ctrl_corrupt_sig_fatal_chk.636320132 | May 05 12:47:13 PM PDT 24 | May 05 12:49:45 PM PDT 24 | 2440373964 ps | ||
| T340 | /workspace/coverage/default/13.rom_ctrl_corrupt_sig_fatal_chk.1791207649 | May 05 12:46:09 PM PDT 24 | May 05 12:48:37 PM PDT 24 | 2003807298 ps | ||
| T341 | /workspace/coverage/default/41.rom_ctrl_max_throughput_chk.1778387041 | May 05 12:47:10 PM PDT 24 | May 05 12:47:20 PM PDT 24 | 4132732537 ps | ||
| T342 | /workspace/coverage/default/7.rom_ctrl_kmac_err_chk.1255263726 | May 05 12:46:07 PM PDT 24 | May 05 12:46:29 PM PDT 24 | 3109285375 ps | ||
| T343 | /workspace/coverage/default/49.rom_ctrl_alert_test.3540648259 | May 05 12:47:15 PM PDT 24 | May 05 12:47:26 PM PDT 24 | 3500112425 ps | ||
| T344 | /workspace/coverage/default/44.rom_ctrl_kmac_err_chk.3586124581 | May 05 12:47:07 PM PDT 24 | May 05 12:47:37 PM PDT 24 | 3401135061 ps | ||
| T345 | /workspace/coverage/default/42.rom_ctrl_max_throughput_chk.1433856624 | May 05 12:47:08 PM PDT 24 | May 05 12:47:17 PM PDT 24 | 1752242822 ps | ||
| T346 | /workspace/coverage/default/27.rom_ctrl_alert_test.1524989254 | May 05 12:46:47 PM PDT 24 | May 05 12:46:54 PM PDT 24 | 344269788 ps | ||
| T347 | /workspace/coverage/default/23.rom_ctrl_max_throughput_chk.1352928240 | May 05 12:46:33 PM PDT 24 | May 05 12:46:41 PM PDT 24 | 343902626 ps | ||
| T348 | /workspace/coverage/default/15.rom_ctrl_stress_all.1694295404 | May 05 12:46:14 PM PDT 24 | May 05 12:46:45 PM PDT 24 | 6836373569 ps | ||
| T23 | /workspace/coverage/default/28.rom_ctrl_stress_all_with_rand_reset.3252667403 | May 05 12:46:40 PM PDT 24 | May 05 01:18:20 PM PDT 24 | 49861107253 ps | ||
| T349 | /workspace/coverage/default/26.rom_ctrl_alert_test.3470560151 | May 05 12:46:38 PM PDT 24 | May 05 12:46:46 PM PDT 24 | 1709868030 ps | ||
| T350 | /workspace/coverage/default/46.rom_ctrl_smoke.964509923 | May 05 12:47:12 PM PDT 24 | May 05 12:47:24 PM PDT 24 | 1046577947 ps | ||
| T351 | /workspace/coverage/default/14.rom_ctrl_stress_all.2839970866 | May 05 12:46:09 PM PDT 24 | May 05 12:46:25 PM PDT 24 | 1919166301 ps | ||
| T352 | /workspace/coverage/default/14.rom_ctrl_kmac_err_chk.2611909608 | May 05 12:46:20 PM PDT 24 | May 05 12:46:56 PM PDT 24 | 4412505982 ps | ||
| T353 | /workspace/coverage/default/37.rom_ctrl_max_throughput_chk.3964976507 | May 05 12:46:59 PM PDT 24 | May 05 12:47:10 PM PDT 24 | 880389715 ps | ||
| T354 | /workspace/coverage/default/11.rom_ctrl_kmac_err_chk.252081602 | May 05 12:46:14 PM PDT 24 | May 05 12:46:34 PM PDT 24 | 1542377229 ps | ||
| T355 | /workspace/coverage/default/9.rom_ctrl_corrupt_sig_fatal_chk.28765653 | May 05 12:46:13 PM PDT 24 | May 05 12:50:24 PM PDT 24 | 45526167990 ps | ||
| T356 | /workspace/coverage/default/11.rom_ctrl_stress_all.554077063 | May 05 12:46:13 PM PDT 24 | May 05 12:46:30 PM PDT 24 | 1908881544 ps | ||
| T357 | /workspace/coverage/default/48.rom_ctrl_smoke.636045133 | May 05 12:47:15 PM PDT 24 | May 05 12:47:45 PM PDT 24 | 15098514547 ps | ||
| T358 | /workspace/coverage/default/49.rom_ctrl_stress_all.1403636862 | May 05 12:47:10 PM PDT 24 | May 05 12:47:33 PM PDT 24 | 429317078 ps | ||
| T359 | /workspace/coverage/default/29.rom_ctrl_corrupt_sig_fatal_chk.3238054854 | May 05 12:46:42 PM PDT 24 | May 05 12:51:59 PM PDT 24 | 60420113239 ps | ||
| T360 | /workspace/coverage/default/47.rom_ctrl_smoke.2591973093 | May 05 12:47:10 PM PDT 24 | May 05 12:47:29 PM PDT 24 | 4133034566 ps | ||
| T361 | /workspace/coverage/default/4.rom_ctrl_kmac_err_chk.3884904743 | May 05 12:46:14 PM PDT 24 | May 05 12:46:41 PM PDT 24 | 11589770138 ps | ||
| T362 | /workspace/coverage/default/5.rom_ctrl_max_throughput_chk.1756642815 | May 05 12:46:09 PM PDT 24 | May 05 12:46:22 PM PDT 24 | 2766919785 ps | ||
| T363 | /workspace/coverage/default/49.rom_ctrl_max_throughput_chk.2231538998 | May 05 12:47:09 PM PDT 24 | May 05 12:47:25 PM PDT 24 | 1924274805 ps | ||
| T364 | /workspace/coverage/default/8.rom_ctrl_alert_test.3411975569 | May 05 12:46:14 PM PDT 24 | May 05 12:46:29 PM PDT 24 | 1634695098 ps | ||
| T365 | /workspace/coverage/default/16.rom_ctrl_corrupt_sig_fatal_chk.2638312114 | May 05 12:46:27 PM PDT 24 | May 05 12:55:08 PM PDT 24 | 52837624013 ps | ||
| T366 | /workspace/coverage/default/26.rom_ctrl_corrupt_sig_fatal_chk.710614188 | May 05 12:46:39 PM PDT 24 | May 05 12:50:09 PM PDT 24 | 24968034492 ps | ||
| T367 | /workspace/coverage/default/31.rom_ctrl_smoke.2588897084 | May 05 12:46:47 PM PDT 24 | May 05 12:47:14 PM PDT 24 | 11259067784 ps | ||
| T368 | /workspace/coverage/default/31.rom_ctrl_max_throughput_chk.2216834115 | May 05 12:46:46 PM PDT 24 | May 05 12:46:59 PM PDT 24 | 4665112807 ps | ||
| T369 | /workspace/coverage/default/49.rom_ctrl_smoke.2968086310 | May 05 12:47:10 PM PDT 24 | May 05 12:47:39 PM PDT 24 | 9951455633 ps | ||
| T370 | /workspace/coverage/default/4.rom_ctrl_alert_test.3842422283 | May 05 12:46:14 PM PDT 24 | May 05 12:46:31 PM PDT 24 | 4209090444 ps | ||
| T371 | /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_errors.912408421 | May 05 12:45:21 PM PDT 24 | May 05 12:45:36 PM PDT 24 | 786441894 ps | ||
| T49 | /workspace/coverage/cover_reg_top/8.rom_ctrl_passthru_mem_tl_intg_err.836804094 | May 05 12:46:03 PM PDT 24 | May 05 12:46:58 PM PDT 24 | 9629991672 ps | ||
| T50 | /workspace/coverage/cover_reg_top/1.rom_ctrl_same_csr_outstanding.1748167583 | May 05 12:45:29 PM PDT 24 | May 05 12:45:38 PM PDT 24 | 769925740 ps | ||
| T51 | /workspace/coverage/cover_reg_top/11.rom_ctrl_same_csr_outstanding.1701609286 | May 05 12:46:04 PM PDT 24 | May 05 12:46:14 PM PDT 24 | 536954187 ps | ||
| T46 | /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_intg_err.1265382842 | May 05 12:45:47 PM PDT 24 | May 05 12:46:24 PM PDT 24 | 399615415 ps | ||
| T372 | /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_mem_rw_with_rand_reset.1879133898 | May 05 12:45:49 PM PDT 24 | May 05 12:46:04 PM PDT 24 | 1893144425 ps | ||
| T59 | /workspace/coverage/cover_reg_top/3.rom_ctrl_same_csr_outstanding.1569116159 | May 05 12:45:51 PM PDT 24 | May 05 12:46:07 PM PDT 24 | 3522447218 ps | ||
| T373 | /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_errors.2560807752 | May 05 12:45:37 PM PDT 24 | May 05 12:45:57 PM PDT 24 | 9392151304 ps | ||
| T374 | /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_errors.4116745696 | May 05 12:46:06 PM PDT 24 | May 05 12:46:14 PM PDT 24 | 566011679 ps | ||
| T101 | /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_rw.3420757085 | May 05 12:45:42 PM PDT 24 | May 05 12:45:51 PM PDT 24 | 6327372555 ps | ||
| T102 | /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_rw.2528796342 | May 05 12:46:04 PM PDT 24 | May 05 12:46:09 PM PDT 24 | 347076175 ps | ||
| T103 | /workspace/coverage/cover_reg_top/3.rom_ctrl_passthru_mem_tl_intg_err.3102946919 | May 05 12:45:28 PM PDT 24 | May 05 12:46:34 PM PDT 24 | 21904206612 ps | ||
| T60 | /workspace/coverage/cover_reg_top/15.rom_ctrl_same_csr_outstanding.3162230377 | May 05 12:45:52 PM PDT 24 | May 05 12:46:06 PM PDT 24 | 12997412369 ps | ||
| T375 | /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_errors.344886690 | May 05 12:46:16 PM PDT 24 | May 05 12:46:26 PM PDT 24 | 515270496 ps | ||
| T376 | /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_mem_rw_with_rand_reset.579041675 | May 05 12:45:49 PM PDT 24 | May 05 12:46:02 PM PDT 24 | 16219931650 ps | ||
| T377 | /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_partial_access.3007659984 | May 05 12:45:22 PM PDT 24 | May 05 12:45:30 PM PDT 24 | 4152653846 ps | ||
| T104 | /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_aliasing.3032591970 | May 05 12:45:29 PM PDT 24 | May 05 12:45:44 PM PDT 24 | 7384483018 ps | ||
| T47 | /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_intg_err.3908028700 | May 05 12:46:00 PM PDT 24 | May 05 12:46:41 PM PDT 24 | 571942471 ps | ||
| T378 | /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_errors.1636598955 | May 05 12:45:44 PM PDT 24 | May 05 12:46:03 PM PDT 24 | 9454643378 ps | ||
| T105 | /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_rw.2242214572 | May 05 12:45:44 PM PDT 24 | May 05 12:45:56 PM PDT 24 | 2502016003 ps | ||
| T61 | /workspace/coverage/cover_reg_top/8.rom_ctrl_same_csr_outstanding.187895515 | May 05 12:45:37 PM PDT 24 | May 05 12:45:55 PM PDT 24 | 4374005767 ps | ||
| T379 | /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_errors.525778898 | May 05 12:45:51 PM PDT 24 | May 05 12:46:00 PM PDT 24 | 131569348 ps | ||
| T98 | /workspace/coverage/cover_reg_top/6.rom_ctrl_passthru_mem_tl_intg_err.576173358 | May 05 12:45:31 PM PDT 24 | May 05 12:45:59 PM PDT 24 | 5148245382 ps | ||
| T48 | /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_intg_err.2022386519 | May 05 12:45:43 PM PDT 24 | May 05 12:47:02 PM PDT 24 | 8968066579 ps | ||
| T62 | /workspace/coverage/cover_reg_top/10.rom_ctrl_passthru_mem_tl_intg_err.498245911 | May 05 12:46:04 PM PDT 24 | May 05 12:46:53 PM PDT 24 | 5076130653 ps | ||
| T63 | /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_rw.2809237914 | May 05 12:45:44 PM PDT 24 | May 05 12:45:49 PM PDT 24 | 379450194 ps | ||
| T64 | /workspace/coverage/cover_reg_top/5.rom_ctrl_passthru_mem_tl_intg_err.4054675070 | May 05 12:45:58 PM PDT 24 | May 05 12:46:37 PM PDT 24 | 3477285602 ps | ||
| T65 | /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_rw.117537837 | May 05 12:45:54 PM PDT 24 | May 05 12:46:09 PM PDT 24 | 1705425455 ps | ||
| T380 | /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_bit_bash.3993778265 | May 05 12:45:33 PM PDT 24 | May 05 12:45:48 PM PDT 24 | 3584779026 ps | ||
| T381 | /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_mem_rw_with_rand_reset.498525896 | May 05 12:45:47 PM PDT 24 | May 05 12:45:58 PM PDT 24 | 876680066 ps | ||
| T382 | /workspace/coverage/cover_reg_top/19.rom_ctrl_passthru_mem_tl_intg_err.3678162807 | May 05 12:45:51 PM PDT 24 | May 05 12:46:22 PM PDT 24 | 3484810201 ps | ||
| T383 | /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_mem_rw_with_rand_reset.4010856386 | May 05 12:45:49 PM PDT 24 | May 05 12:45:57 PM PDT 24 | 4731739877 ps | ||
| T384 | /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_mem_rw_with_rand_reset.2342851906 | May 05 12:45:58 PM PDT 24 | May 05 12:46:07 PM PDT 24 | 3086406456 ps | ||
| T66 | /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_rw.3163236833 | May 05 12:45:35 PM PDT 24 | May 05 12:45:44 PM PDT 24 | 8694827466 ps | ||
| T385 | /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_walk.1609763901 | May 05 12:45:22 PM PDT 24 | May 05 12:45:37 PM PDT 24 | 7266291796 ps | ||
| T386 | /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_errors.2131851932 | May 05 12:45:31 PM PDT 24 | May 05 12:45:40 PM PDT 24 | 478691835 ps | ||
| T387 | /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_partial_access.562730018 | May 05 12:45:34 PM PDT 24 | May 05 12:45:38 PM PDT 24 | 128281991 ps | ||
| T99 | /workspace/coverage/cover_reg_top/0.rom_ctrl_same_csr_outstanding.2290227722 | May 05 12:45:22 PM PDT 24 | May 05 12:45:40 PM PDT 24 | 8829939500 ps | ||
| T100 | /workspace/coverage/cover_reg_top/12.rom_ctrl_same_csr_outstanding.3341961628 | May 05 12:45:42 PM PDT 24 | May 05 12:45:50 PM PDT 24 | 464562321 ps | ||
| T112 | /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_intg_err.1531106929 | May 05 12:45:54 PM PDT 24 | May 05 12:46:33 PM PDT 24 | 8719121434 ps | ||
| T388 | /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_errors.3130895250 | May 05 12:46:00 PM PDT 24 | May 05 12:46:16 PM PDT 24 | 5026567345 ps | ||
| T74 | /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_rw.2239318738 | May 05 12:46:15 PM PDT 24 | May 05 12:46:31 PM PDT 24 | 1926985443 ps | ||
| T75 | /workspace/coverage/cover_reg_top/4.rom_ctrl_passthru_mem_tl_intg_err.4165447402 | May 05 12:45:30 PM PDT 24 | May 05 12:46:43 PM PDT 24 | 67390772370 ps | ||
| T389 | /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_mem_rw_with_rand_reset.882058298 | May 05 12:45:52 PM PDT 24 | May 05 12:45:58 PM PDT 24 | 354076381 ps | ||
| T76 | /workspace/coverage/cover_reg_top/17.rom_ctrl_passthru_mem_tl_intg_err.4076533810 | May 05 12:46:02 PM PDT 24 | May 05 12:46:44 PM PDT 24 | 9004334256 ps | ||
| T390 | /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_bit_bash.2424751581 | May 05 12:45:20 PM PDT 24 | May 05 12:45:26 PM PDT 24 | 346604260 ps | ||
| T391 | /workspace/coverage/cover_reg_top/14.rom_ctrl_passthru_mem_tl_intg_err.1158020813 | May 05 12:45:58 PM PDT 24 | May 05 12:46:40 PM PDT 24 | 2134346403 ps | ||
| T392 | /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_mem_rw_with_rand_reset.559182732 | May 05 12:45:32 PM PDT 24 | May 05 12:45:39 PM PDT 24 | 1166020075 ps | ||
| T393 | /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_aliasing.60808556 | May 05 12:45:27 PM PDT 24 | May 05 12:45:38 PM PDT 24 | 3909424502 ps | ||
| T394 | /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_errors.1996394610 | May 05 12:45:42 PM PDT 24 | May 05 12:45:55 PM PDT 24 | 8259309157 ps | ||
| T395 | /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_mem_rw_with_rand_reset.2695983770 | May 05 12:45:31 PM PDT 24 | May 05 12:45:45 PM PDT 24 | 26658242394 ps | ||
| T396 | /workspace/coverage/cover_reg_top/7.rom_ctrl_same_csr_outstanding.522749658 | May 05 12:46:01 PM PDT 24 | May 05 12:46:17 PM PDT 24 | 1977667447 ps | ||
| T397 | /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_hw_reset.617478510 | May 05 12:45:54 PM PDT 24 | May 05 12:46:01 PM PDT 24 | 88045436 ps | ||
| T111 | /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_intg_err.2459968478 | May 05 12:45:41 PM PDT 24 | May 05 12:46:49 PM PDT 24 | 427903677 ps | ||
| T77 | /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_rw.2274455494 | May 05 12:46:08 PM PDT 24 | May 05 12:46:20 PM PDT 24 | 2378340208 ps | ||
| T113 | /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_intg_err.1346503121 | May 05 12:45:53 PM PDT 24 | May 05 12:46:32 PM PDT 24 | 569679114 ps | ||
| T78 | /workspace/coverage/cover_reg_top/15.rom_ctrl_passthru_mem_tl_intg_err.102932645 | May 05 12:46:08 PM PDT 24 | May 05 12:47:12 PM PDT 24 | 33523629664 ps | ||
| T398 | /workspace/coverage/cover_reg_top/13.rom_ctrl_same_csr_outstanding.600024007 | May 05 12:46:05 PM PDT 24 | May 05 12:46:10 PM PDT 24 | 320172875 ps | ||
| T399 | /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_rw.2702763862 | May 05 12:45:34 PM PDT 24 | May 05 12:45:47 PM PDT 24 | 3078883545 ps | ||
| T400 | /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_bit_bash.3149200806 | May 05 12:45:27 PM PDT 24 | May 05 12:45:39 PM PDT 24 | 4859237133 ps | ||
| T401 | /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_errors.3622005677 | May 05 12:45:51 PM PDT 24 | May 05 12:46:01 PM PDT 24 | 136739227 ps | ||
| T402 | /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_rw.38108176 | May 05 12:45:47 PM PDT 24 | May 05 12:45:58 PM PDT 24 | 1005480192 ps | ||
| T403 | /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_errors.4002587464 | May 05 12:45:57 PM PDT 24 | May 05 12:46:06 PM PDT 24 | 132400129 ps | ||
| T404 | /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_rw.2517831947 | May 05 12:45:31 PM PDT 24 | May 05 12:45:40 PM PDT 24 | 1348223730 ps | ||
| T405 | /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_partial_access.1343536487 | May 05 12:45:30 PM PDT 24 | May 05 12:45:35 PM PDT 24 | 86393460 ps | ||
| T406 | /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_errors.265772508 | May 05 12:45:58 PM PDT 24 | May 05 12:46:16 PM PDT 24 | 3698570884 ps | ||
| T407 | /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_mem_rw_with_rand_reset.1378788963 | May 05 12:46:13 PM PDT 24 | May 05 12:46:24 PM PDT 24 | 2284492237 ps | ||
| T79 | /workspace/coverage/cover_reg_top/11.rom_ctrl_passthru_mem_tl_intg_err.2471969392 | May 05 12:45:42 PM PDT 24 | May 05 12:47:00 PM PDT 24 | 33595829337 ps | ||
| T408 | /workspace/coverage/cover_reg_top/9.rom_ctrl_passthru_mem_tl_intg_err.776621221 | May 05 12:45:36 PM PDT 24 | May 05 12:46:34 PM PDT 24 | 28743436642 ps | ||
| T116 | /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_intg_err.4115029253 | May 05 12:45:31 PM PDT 24 | May 05 12:46:15 PM PDT 24 | 1440748239 ps | ||
| T409 | /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_walk.3600163248 | May 05 12:45:31 PM PDT 24 | May 05 12:45:42 PM PDT 24 | 4274654627 ps | ||
| T410 | /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_mem_rw_with_rand_reset.445472263 | May 05 12:45:21 PM PDT 24 | May 05 12:45:34 PM PDT 24 | 4723397524 ps | ||
| T80 | /workspace/coverage/cover_reg_top/16.rom_ctrl_passthru_mem_tl_intg_err.877932744 | May 05 12:45:51 PM PDT 24 | May 05 12:46:54 PM PDT 24 | 13529885151 ps | ||
| T411 | /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_errors.4185638261 | May 05 12:45:35 PM PDT 24 | May 05 12:45:46 PM PDT 24 | 5860269114 ps | ||
| T114 | /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_intg_err.1464697795 | May 05 12:45:33 PM PDT 24 | May 05 12:46:47 PM PDT 24 | 2884461995 ps | ||
| T412 | /workspace/coverage/cover_reg_top/10.rom_ctrl_same_csr_outstanding.2721358029 | May 05 12:45:54 PM PDT 24 | May 05 12:46:11 PM PDT 24 | 4023620396 ps | ||
| T81 | /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_hw_reset.2781479177 | May 05 12:45:36 PM PDT 24 | May 05 12:45:52 PM PDT 24 | 719687021 ps | ||
| T413 | /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_mem_rw_with_rand_reset.3627594589 | May 05 12:46:02 PM PDT 24 | May 05 12:46:10 PM PDT 24 | 1737674537 ps | ||
| T82 | /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_rw.341776518 | May 05 12:45:58 PM PDT 24 | May 05 12:46:06 PM PDT 24 | 2850408893 ps | ||
| T414 | /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_rw.380033090 | May 05 12:45:37 PM PDT 24 | May 05 12:45:48 PM PDT 24 | 3613861860 ps | ||
| T415 | /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_partial_access.4001641631 | May 05 12:45:29 PM PDT 24 | May 05 12:45:42 PM PDT 24 | 1430847467 ps | ||
| T416 | /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_mem_rw_with_rand_reset.3934177305 | May 05 12:45:41 PM PDT 24 | May 05 12:45:55 PM PDT 24 | 3013343000 ps | ||
| T417 | /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_rw.1928225071 | May 05 12:45:37 PM PDT 24 | May 05 12:45:43 PM PDT 24 | 420716893 ps | ||
| T418 | /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_rw.4145059521 | May 05 12:45:52 PM PDT 24 | May 05 12:46:08 PM PDT 24 | 8776827361 ps | ||
| T419 | /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_intg_err.1975751638 | May 05 12:45:48 PM PDT 24 | May 05 12:46:25 PM PDT 24 | 588753418 ps | ||
| T420 | /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_aliasing.1086691700 | May 05 12:45:49 PM PDT 24 | May 05 12:46:04 PM PDT 24 | 1687760683 ps | ||
| T421 | /workspace/coverage/cover_reg_top/17.rom_ctrl_same_csr_outstanding.1225316007 | May 05 12:45:48 PM PDT 24 | May 05 12:45:54 PM PDT 24 | 297183219 ps | ||
| T117 | /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_intg_err.3060679256 | May 05 12:45:52 PM PDT 24 | May 05 12:47:07 PM PDT 24 | 1077445946 ps | ||
| T422 | /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_walk.2501838413 | May 05 12:45:26 PM PDT 24 | May 05 12:45:31 PM PDT 24 | 347265389 ps | ||
| T423 | /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_mem_rw_with_rand_reset.881082797 | May 05 12:45:48 PM PDT 24 | May 05 12:45:54 PM PDT 24 | 408837224 ps | ||
| T424 | /workspace/coverage/cover_reg_top/12.rom_ctrl_passthru_mem_tl_intg_err.2219166664 | May 05 12:45:57 PM PDT 24 | May 05 12:47:00 PM PDT 24 | 12144857359 ps | ||
| T425 | /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_mem_rw_with_rand_reset.4190020653 | May 05 12:45:51 PM PDT 24 | May 05 12:46:07 PM PDT 24 | 12076884960 ps | ||
| T426 | /workspace/coverage/cover_reg_top/19.rom_ctrl_same_csr_outstanding.1115610371 | May 05 12:45:58 PM PDT 24 | May 05 12:46:03 PM PDT 24 | 87991794 ps | ||
| T427 | /workspace/coverage/cover_reg_top/16.rom_ctrl_same_csr_outstanding.3900576677 | May 05 12:45:50 PM PDT 24 | May 05 12:46:06 PM PDT 24 | 6822604347 ps | ||
| T428 | /workspace/coverage/cover_reg_top/7.rom_ctrl_passthru_mem_tl_intg_err.2889229562 | May 05 12:45:31 PM PDT 24 | May 05 12:46:30 PM PDT 24 | 7341421486 ps | ||
| T429 | /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_errors.2556886996 | May 05 12:45:25 PM PDT 24 | May 05 12:45:41 PM PDT 24 | 1314636209 ps | ||
| T430 | /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_hw_reset.1919007583 | May 05 12:45:31 PM PDT 24 | May 05 12:45:48 PM PDT 24 | 7898428344 ps | ||
| T431 | /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_rw.3434342832 | May 05 12:45:29 PM PDT 24 | May 05 12:45:44 PM PDT 24 | 3505168937 ps | ||
| T432 | /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_rw.252008304 | May 05 12:46:14 PM PDT 24 | May 05 12:46:19 PM PDT 24 | 162152113 ps | ||
| T433 | /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_rw.1769763672 | May 05 12:46:03 PM PDT 24 | May 05 12:46:15 PM PDT 24 | 2363806839 ps | ||
| T434 | /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_errors.771281652 | May 05 12:45:56 PM PDT 24 | May 05 12:46:13 PM PDT 24 | 1669730856 ps | ||
| T435 | /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_mem_rw_with_rand_reset.1808503011 | May 05 12:45:32 PM PDT 24 | May 05 12:45:37 PM PDT 24 | 190443445 ps | ||
| T436 | /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_hw_reset.3804252564 | May 05 12:45:26 PM PDT 24 | May 05 12:45:35 PM PDT 24 | 89674509 ps | ||
| T83 | /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_aliasing.1408002665 | May 05 12:45:21 PM PDT 24 | May 05 12:45:38 PM PDT 24 | 6981765515 ps | ||
| T84 | /workspace/coverage/cover_reg_top/0.rom_ctrl_passthru_mem_tl_intg_err.3978031101 | May 05 12:45:20 PM PDT 24 | May 05 12:45:49 PM PDT 24 | 3014626291 ps | ||
| T119 | /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_intg_err.713469792 | May 05 12:45:54 PM PDT 24 | May 05 12:46:33 PM PDT 24 | 1778609485 ps | ||
| T437 | /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_errors.855132280 | May 05 12:45:20 PM PDT 24 | May 05 12:45:30 PM PDT 24 | 139884788 ps | ||
| T438 | /workspace/coverage/cover_reg_top/2.rom_ctrl_same_csr_outstanding.3844011242 | May 05 12:45:44 PM PDT 24 | May 05 12:45:56 PM PDT 24 | 1023446004 ps | ||
| T439 | /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_mem_rw_with_rand_reset.1284292580 | May 05 12:45:57 PM PDT 24 | May 05 12:46:06 PM PDT 24 | 1749736193 ps | ||
| T115 | /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_intg_err.2032183936 | May 05 12:45:29 PM PDT 24 | May 05 12:46:47 PM PDT 24 | 7717569060 ps | ||
| T440 | /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_errors.76310050 | May 05 12:45:48 PM PDT 24 | May 05 12:46:06 PM PDT 24 | 5932984185 ps | ||
| T441 | /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_hw_reset.1382914209 | May 05 12:45:21 PM PDT 24 | May 05 12:45:37 PM PDT 24 | 2331493506 ps | ||
| T121 | /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_intg_err.3806711427 | May 05 12:45:48 PM PDT 24 | May 05 12:46:58 PM PDT 24 | 1013455811 ps | ||
| T442 | /workspace/coverage/cover_reg_top/9.rom_ctrl_same_csr_outstanding.665614487 | May 05 12:45:46 PM PDT 24 | May 05 12:45:53 PM PDT 24 | 1483299549 ps | ||
| T85 | /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_rw.1865725916 | May 05 12:45:57 PM PDT 24 | May 05 12:46:12 PM PDT 24 | 1651153180 ps | ||
| T443 | /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_partial_access.2111635599 | May 05 12:45:25 PM PDT 24 | May 05 12:45:34 PM PDT 24 | 1212021259 ps | ||
| T86 | /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_aliasing.2740388456 | May 05 12:45:27 PM PDT 24 | May 05 12:45:38 PM PDT 24 | 2047375087 ps | ||
| T120 | /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_intg_err.3245996716 | May 05 12:45:26 PM PDT 24 | May 05 12:46:15 PM PDT 24 | 2133417298 ps | ||
| T118 | /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_intg_err.3369520408 | May 05 12:45:37 PM PDT 24 | May 05 12:46:14 PM PDT 24 | 557141638 ps | ||
| T444 | /workspace/coverage/cover_reg_top/4.rom_ctrl_same_csr_outstanding.3489444228 | May 05 12:45:31 PM PDT 24 | May 05 12:45:36 PM PDT 24 | 168657201 ps | ||
| T445 | /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_mem_rw_with_rand_reset.3969844757 | May 05 12:45:45 PM PDT 24 | May 05 12:45:53 PM PDT 24 | 432283928 ps | ||
| T446 | /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_mem_rw_with_rand_reset.2128079969 | May 05 12:45:48 PM PDT 24 | May 05 12:46:01 PM PDT 24 | 1199481128 ps | ||
| T447 | /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_intg_err.2340314391 | May 05 12:46:04 PM PDT 24 | May 05 12:47:16 PM PDT 24 | 998679304 ps | ||
| T448 | /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_intg_err.3702689287 | May 05 12:45:52 PM PDT 24 | May 05 12:47:10 PM PDT 24 | 2234413324 ps | ||
| T449 | /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_errors.2681080987 | May 05 12:45:37 PM PDT 24 | May 05 12:45:58 PM PDT 24 | 1910907400 ps | ||
| T450 | /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_mem_rw_with_rand_reset.1015049504 | May 05 12:45:48 PM PDT 24 | May 05 12:45:55 PM PDT 24 | 205551187 ps | ||
| T451 | /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_walk.3661056923 | May 05 12:45:55 PM PDT 24 | May 05 12:46:05 PM PDT 24 | 827217976 ps | ||
| T87 | /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_rw.3237194480 | May 05 12:45:26 PM PDT 24 | May 05 12:45:39 PM PDT 24 | 1499247542 ps | ||
| T452 | /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_intg_err.4141530532 | May 05 12:45:36 PM PDT 24 | May 05 12:46:24 PM PDT 24 | 2267475140 ps | ||
| T453 | /workspace/coverage/cover_reg_top/18.rom_ctrl_passthru_mem_tl_intg_err.2305341917 | May 05 12:46:11 PM PDT 24 | May 05 12:47:03 PM PDT 24 | 24915057079 ps | ||
| T454 | /workspace/coverage/cover_reg_top/1.rom_ctrl_passthru_mem_tl_intg_err.1398412368 | May 05 12:45:26 PM PDT 24 | May 05 12:46:10 PM PDT 24 | 2617479781 ps | ||
| T455 | /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_errors.569924708 | May 05 12:45:55 PM PDT 24 | May 05 12:46:13 PM PDT 24 | 6612658700 ps | ||
| T456 | /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_bit_bash.189183430 | May 05 12:45:28 PM PDT 24 | May 05 12:45:44 PM PDT 24 | 2018051709 ps | ||
| T457 | /workspace/coverage/cover_reg_top/18.rom_ctrl_same_csr_outstanding.1345534917 | May 05 12:45:52 PM PDT 24 | May 05 12:45:57 PM PDT 24 | 97123731 ps | ||
| T458 | /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_errors.1211691518 | May 05 12:45:36 PM PDT 24 | May 05 12:45:53 PM PDT 24 | 1283308890 ps | ||
| T459 | /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_walk.740926455 | May 05 12:45:30 PM PDT 24 | May 05 12:45:45 PM PDT 24 | 1764686890 ps | ||
| T460 | /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_bit_bash.3632474425 | May 05 12:45:30 PM PDT 24 | May 05 12:45:39 PM PDT 24 | 1246682626 ps | ||
| T461 | /workspace/coverage/cover_reg_top/5.rom_ctrl_same_csr_outstanding.248010282 | May 05 12:45:32 PM PDT 24 | May 05 12:45:45 PM PDT 24 | 4654869990 ps | ||
| T462 | /workspace/coverage/cover_reg_top/2.rom_ctrl_passthru_mem_tl_intg_err.2222485941 | May 05 12:45:44 PM PDT 24 | May 05 12:46:50 PM PDT 24 | 24637294839 ps | ||
| T463 | /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_mem_rw_with_rand_reset.1706348189 | May 05 12:45:43 PM PDT 24 | May 05 12:45:49 PM PDT 24 | 379129468 ps | ||
| T464 | /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_intg_err.3184386597 | May 05 12:46:01 PM PDT 24 | May 05 12:47:10 PM PDT 24 | 264463066 ps | ||
| T465 | /workspace/coverage/cover_reg_top/14.rom_ctrl_same_csr_outstanding.1676252827 | May 05 12:45:40 PM PDT 24 | May 05 12:45:55 PM PDT 24 | 3643877761 ps | ||
| T466 | /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_intg_err.1733526218 | May 05 12:45:55 PM PDT 24 | May 05 12:46:42 PM PDT 24 | 1864017873 ps | ||
| T467 | /workspace/coverage/cover_reg_top/13.rom_ctrl_passthru_mem_tl_intg_err.975053793 | May 05 12:45:43 PM PDT 24 | May 05 12:46:43 PM PDT 24 | 13878247183 ps | ||
| T468 | /workspace/coverage/cover_reg_top/6.rom_ctrl_same_csr_outstanding.3770424716 | May 05 12:45:48 PM PDT 24 | May 05 12:45:54 PM PDT 24 | 498165214 ps |
| Test location | /workspace/coverage/default/21.rom_ctrl_stress_all_with_rand_reset.2536570964 |
| Short name | T4 |
| Test name | |
| Test status | |
| Simulation time | 133818806960 ps |
| CPU time | 5294.76 seconds |
| Started | May 05 12:46:29 PM PDT 24 |
| Finished | May 05 02:14:45 PM PDT 24 |
| Peak memory | 235256 kb |
| Host | smart-a84c241e-0003-46d9-9f5e-7e9207bf225f |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2536570964 -assert nop ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_stress_all_with_rand_reset.2536570964 |
| Directory | /workspace/21.rom_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/38.rom_ctrl_corrupt_sig_fatal_chk.3274053760 |
| Short name | T14 |
| Test name | |
| Test status | |
| Simulation time | 221871141470 ps |
| CPU time | 238.02 seconds |
| Started | May 05 12:46:59 PM PDT 24 |
| Finished | May 05 12:50:58 PM PDT 24 |
| Peak memory | 231188 kb |
| Host | smart-2ccbea5d-08c0-4139-a06b-24afbc65d8d3 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3274053760 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_ corrupt_sig_fatal_chk.3274053760 |
| Directory | /workspace/38.rom_ctrl_corrupt_sig_fatal_chk/latest |
| Test location | /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_intg_err.2459968478 |
| Short name | T111 |
| Test name | |
| Test status | |
| Simulation time | 427903677 ps |
| CPU time | 67.5 seconds |
| Started | May 05 12:45:41 PM PDT 24 |
| Finished | May 05 12:46:49 PM PDT 24 |
| Peak memory | 210600 kb |
| Host | smart-40d24ab5-57d4-41c1-acd3-ebbb020605ef |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2459968478 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_tl_i ntg_err.2459968478 |
| Directory | /workspace/14.rom_ctrl_tl_intg_err/latest |
| Test location | /workspace/coverage/default/11.rom_ctrl_corrupt_sig_fatal_chk.2088112159 |
| Short name | T28 |
| Test name | |
| Test status | |
| Simulation time | 23148746292 ps |
| CPU time | 237.74 seconds |
| Started | May 05 12:46:18 PM PDT 24 |
| Finished | May 05 12:50:16 PM PDT 24 |
| Peak memory | 212928 kb |
| Host | smart-33953782-608f-4ff3-9de1-c82885a7a702 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2088112159 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_ corrupt_sig_fatal_chk.2088112159 |
| Directory | /workspace/11.rom_ctrl_corrupt_sig_fatal_chk/latest |
| Test location | /workspace/coverage/default/46.rom_ctrl_corrupt_sig_fatal_chk.2197896181 |
| Short name | T15 |
| Test name | |
| Test status | |
| Simulation time | 7319830000 ps |
| CPU time | 139.19 seconds |
| Started | May 05 12:47:10 PM PDT 24 |
| Finished | May 05 12:49:30 PM PDT 24 |
| Peak memory | 238268 kb |
| Host | smart-fbe86f83-eb40-4edb-a539-227d905cb1dc |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2197896181 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_ corrupt_sig_fatal_chk.2197896181 |
| Directory | /workspace/46.rom_ctrl_corrupt_sig_fatal_chk/latest |
| Test location | /workspace/coverage/default/42.rom_ctrl_stress_all_with_rand_reset.4055380213 |
| Short name | T40 |
| Test name | |
| Test status | |
| Simulation time | 5997750503 ps |
| CPU time | 739.09 seconds |
| Started | May 05 12:47:05 PM PDT 24 |
| Finished | May 05 12:59:25 PM PDT 24 |
| Peak memory | 220196 kb |
| Host | smart-244eeaeb-d880-47cc-b5bb-39e564410b23 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4055380213 -assert nop ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_stress_all_with_rand_reset.4055380213 |
| Directory | /workspace/42.rom_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/3.rom_ctrl_sec_cm.2538646099 |
| Short name | T34 |
| Test name | |
| Test status | |
| Simulation time | 225221749 ps |
| CPU time | 53.87 seconds |
| Started | May 05 12:46:06 PM PDT 24 |
| Finished | May 05 12:47:01 PM PDT 24 |
| Peak memory | 236748 kb |
| Host | smart-efa897b4-a433-4db7-bf95-d4978934380a |
| User | root |
| Command | /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2538646099 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_sec_cm.2538646099 |
| Directory | /workspace/3.rom_ctrl_sec_cm/latest |
| Test location | /workspace/coverage/cover_reg_top/10.rom_ctrl_passthru_mem_tl_intg_err.498245911 |
| Short name | T62 |
| Test name | |
| Test status | |
| Simulation time | 5076130653 ps |
| CPU time | 48.46 seconds |
| Started | May 05 12:46:04 PM PDT 24 |
| Finished | May 05 12:46:53 PM PDT 24 |
| Peak memory | 210588 kb |
| Host | smart-2db5a1df-8848-4734-9417-58e5bb8e85ea |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=498245911 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl _common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_pa ssthru_mem_tl_intg_err.498245911 |
| Directory | /workspace/10.rom_ctrl_passthru_mem_tl_intg_err/latest |
| Test location | /workspace/coverage/default/19.rom_ctrl_alert_test.2404080478 |
| Short name | T52 |
| Test name | |
| Test status | |
| Simulation time | 1788761349 ps |
| CPU time | 15.3 seconds |
| Started | May 05 12:46:26 PM PDT 24 |
| Finished | May 05 12:46:42 PM PDT 24 |
| Peak memory | 211556 kb |
| Host | smart-bc3cc9a1-c063-445e-8568-17bbded3e121 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2404080478 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_alert_test.2404080478 |
| Directory | /workspace/19.rom_ctrl_alert_test/latest |
| Test location | /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_intg_err.2032183936 |
| Short name | T115 |
| Test name | |
| Test status | |
| Simulation time | 7717569060 ps |
| CPU time | 77.94 seconds |
| Started | May 05 12:45:29 PM PDT 24 |
| Finished | May 05 12:46:47 PM PDT 24 |
| Peak memory | 211612 kb |
| Host | smart-3d2f8601-215b-4e8e-a84c-85fdbae1bfbe |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2032183936 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_tl_in tg_err.2032183936 |
| Directory | /workspace/0.rom_ctrl_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_intg_err.1464697795 |
| Short name | T114 |
| Test name | |
| Test status | |
| Simulation time | 2884461995 ps |
| CPU time | 72.95 seconds |
| Started | May 05 12:45:33 PM PDT 24 |
| Finished | May 05 12:46:47 PM PDT 24 |
| Peak memory | 211176 kb |
| Host | smart-e2dd2ade-a4cf-4661-aecf-9d480b393150 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1464697795 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_tl_in tg_err.1464697795 |
| Directory | /workspace/2.rom_ctrl_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/3.rom_ctrl_passthru_mem_tl_intg_err.3102946919 |
| Short name | T103 |
| Test name | |
| Test status | |
| Simulation time | 21904206612 ps |
| CPU time | 65.79 seconds |
| Started | May 05 12:45:28 PM PDT 24 |
| Finished | May 05 12:46:34 PM PDT 24 |
| Peak memory | 210476 kb |
| Host | smart-fd3cc3db-209f-4dc4-9974-41e2c9be8eb7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3102946919 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_pa ssthru_mem_tl_intg_err.3102946919 |
| Directory | /workspace/3.rom_ctrl_passthru_mem_tl_intg_err/latest |
| Test location | /workspace/coverage/default/12.rom_ctrl_kmac_err_chk.1153853736 |
| Short name | T3 |
| Test name | |
| Test status | |
| Simulation time | 15401909026 ps |
| CPU time | 31.11 seconds |
| Started | May 05 12:46:21 PM PDT 24 |
| Finished | May 05 12:46:53 PM PDT 24 |
| Peak memory | 212572 kb |
| Host | smart-541baff3-a670-4eff-98eb-ba3129bdc6d7 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1153853736 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_kmac_err_chk.1153853736 |
| Directory | /workspace/12.rom_ctrl_kmac_err_chk/latest |
| Test location | /workspace/coverage/default/20.rom_ctrl_kmac_err_chk.2061336180 |
| Short name | T330 |
| Test name | |
| Test status | |
| Simulation time | 274429783 ps |
| CPU time | 9.23 seconds |
| Started | May 05 12:46:28 PM PDT 24 |
| Finished | May 05 12:46:38 PM PDT 24 |
| Peak memory | 212260 kb |
| Host | smart-e55874b0-00b0-4cc1-864b-b9e1a5890ba4 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2061336180 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_kmac_err_chk.2061336180 |
| Directory | /workspace/20.rom_ctrl_kmac_err_chk/latest |
| Test location | /workspace/coverage/default/18.rom_ctrl_stress_all_with_rand_reset.2161888391 |
| Short name | T110 |
| Test name | |
| Test status | |
| Simulation time | 221211531605 ps |
| CPU time | 5397.34 seconds |
| Started | May 05 12:46:22 PM PDT 24 |
| Finished | May 05 02:16:20 PM PDT 24 |
| Peak memory | 269172 kb |
| Host | smart-f0b8aebc-0aba-411b-947d-4aa8ff0cbe85 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2161888391 -assert nop ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_stress_all_with_rand_reset.2161888391 |
| Directory | /workspace/18.rom_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/16.rom_ctrl_max_throughput_chk.422492684 |
| Short name | T58 |
| Test name | |
| Test status | |
| Simulation time | 725666925 ps |
| CPU time | 6.54 seconds |
| Started | May 05 12:46:14 PM PDT 24 |
| Finished | May 05 12:46:21 PM PDT 24 |
| Peak memory | 211556 kb |
| Host | smart-5b000870-b880-4a42-91ea-1a6a54eeba25 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=422492684 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_max_throughput_chk.422492684 |
| Directory | /workspace/16.rom_ctrl_max_throughput_chk/latest |
| Test location | /workspace/coverage/default/28.rom_ctrl_corrupt_sig_fatal_chk.3905378884 |
| Short name | T139 |
| Test name | |
| Test status | |
| Simulation time | 1759828329 ps |
| CPU time | 88.69 seconds |
| Started | May 05 12:46:40 PM PDT 24 |
| Finished | May 05 12:48:10 PM PDT 24 |
| Peak memory | 238136 kb |
| Host | smart-43b1d4d5-30a6-490a-9743-562761c84b7e |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3905378884 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_ corrupt_sig_fatal_chk.3905378884 |
| Directory | /workspace/28.rom_ctrl_corrupt_sig_fatal_chk/latest |
| Test location | /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_intg_err.3184386597 |
| Short name | T464 |
| Test name | |
| Test status | |
| Simulation time | 264463066 ps |
| CPU time | 68.72 seconds |
| Started | May 05 12:46:01 PM PDT 24 |
| Finished | May 05 12:47:10 PM PDT 24 |
| Peak memory | 211644 kb |
| Host | smart-f090a4c7-b964-4323-8808-78d2eca95d35 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3184386597 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_tl_i ntg_err.3184386597 |
| Directory | /workspace/10.rom_ctrl_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_intg_err.713469792 |
| Short name | T119 |
| Test name | |
| Test status | |
| Simulation time | 1778609485 ps |
| CPU time | 38.15 seconds |
| Started | May 05 12:45:54 PM PDT 24 |
| Finished | May 05 12:46:33 PM PDT 24 |
| Peak memory | 210412 kb |
| Host | smart-d3fc4ce4-d4a8-47db-8cac-7189d7e453e4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=713469792 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_tl_in tg_err.713469792 |
| Directory | /workspace/19.rom_ctrl_tl_intg_err/latest |
| Test location | /workspace/coverage/default/16.rom_ctrl_smoke.1537532126 |
| Short name | T69 |
| Test name | |
| Test status | |
| Simulation time | 14769021483 ps |
| CPU time | 35.16 seconds |
| Started | May 05 12:46:17 PM PDT 24 |
| Finished | May 05 12:46:53 PM PDT 24 |
| Peak memory | 219860 kb |
| Host | smart-9ecfde99-de43-4d80-80d1-fd287954ae67 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1537532126 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_smoke.1537532126 |
| Directory | /workspace/16.rom_ctrl_smoke/latest |
| Test location | /workspace/coverage/default/31.rom_ctrl_stress_all.1509684083 |
| Short name | T88 |
| Test name | |
| Test status | |
| Simulation time | 3775170039 ps |
| CPU time | 33.22 seconds |
| Started | May 05 12:46:46 PM PDT 24 |
| Finished | May 05 12:47:19 PM PDT 24 |
| Peak memory | 219988 kb |
| Host | smart-63019dba-e840-4ffb-9858-1fa3f7cb19da |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1509684083 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm _name 31.rom_ctrl_stress_all.1509684083 |
| Directory | /workspace/31.rom_ctrl_stress_all/latest |
| Test location | /workspace/coverage/default/10.rom_ctrl_stress_all_with_rand_reset.1075503816 |
| Short name | T22 |
| Test name | |
| Test status | |
| Simulation time | 92994122440 ps |
| CPU time | 3467.62 seconds |
| Started | May 05 12:46:15 PM PDT 24 |
| Finished | May 05 01:44:05 PM PDT 24 |
| Peak memory | 245628 kb |
| Host | smart-ada51226-8553-40c0-9b52-1687f9f427d6 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1075503816 -assert nop ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_stress_all_with_rand_reset.1075503816 |
| Directory | /workspace/10.rom_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/13.rom_ctrl_smoke.3727771438 |
| Short name | T254 |
| Test name | |
| Test status | |
| Simulation time | 4200943072 ps |
| CPU time | 32.95 seconds |
| Started | May 05 12:46:09 PM PDT 24 |
| Finished | May 05 12:46:43 PM PDT 24 |
| Peak memory | 213484 kb |
| Host | smart-4f3dcb96-a68a-42a8-8424-c50a8957d467 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3727771438 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_smoke.3727771438 |
| Directory | /workspace/13.rom_ctrl_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_aliasing.1408002665 |
| Short name | T83 |
| Test name | |
| Test status | |
| Simulation time | 6981765515 ps |
| CPU time | 15.08 seconds |
| Started | May 05 12:45:21 PM PDT 24 |
| Finished | May 05 12:45:38 PM PDT 24 |
| Peak memory | 210488 kb |
| Host | smart-f4a46dac-9e64-4679-895f-7a0e291e50c6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1408002665 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_alia sing.1408002665 |
| Directory | /workspace/0.rom_ctrl_csr_aliasing/latest |
| Test location | /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_bit_bash.2424751581 |
| Short name | T390 |
| Test name | |
| Test status | |
| Simulation time | 346604260 ps |
| CPU time | 4.65 seconds |
| Started | May 05 12:45:20 PM PDT 24 |
| Finished | May 05 12:45:26 PM PDT 24 |
| Peak memory | 210440 kb |
| Host | smart-7a6929d3-de71-4e76-a7be-61dc3fceda00 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2424751581 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_bit_ bash.2424751581 |
| Directory | /workspace/0.rom_ctrl_csr_bit_bash/latest |
| Test location | /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_hw_reset.1382914209 |
| Short name | T441 |
| Test name | |
| Test status | |
| Simulation time | 2331493506 ps |
| CPU time | 14.54 seconds |
| Started | May 05 12:45:21 PM PDT 24 |
| Finished | May 05 12:45:37 PM PDT 24 |
| Peak memory | 210500 kb |
| Host | smart-886a85db-fc4a-4d15-9b95-41b4db2028e1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1382914209 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_hw_r eset.1382914209 |
| Directory | /workspace/0.rom_ctrl_csr_hw_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_mem_rw_with_rand_reset.445472263 |
| Short name | T410 |
| Test name | |
| Test status | |
| Simulation time | 4723397524 ps |
| CPU time | 11.1 seconds |
| Started | May 05 12:45:21 PM PDT 24 |
| Finished | May 05 12:45:34 PM PDT 24 |
| Peak memory | 218716 kb |
| Host | smart-fbc8d726-d516-45b1-a409-361366623c33 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=445472263 -assert nopostproc +UVM_TESTNAME= rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_mem_rw_with_rand_reset.445472263 |
| Directory | /workspace/0.rom_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_rw.3237194480 |
| Short name | T87 |
| Test name | |
| Test status | |
| Simulation time | 1499247542 ps |
| CPU time | 12.43 seconds |
| Started | May 05 12:45:26 PM PDT 24 |
| Finished | May 05 12:45:39 PM PDT 24 |
| Peak memory | 210360 kb |
| Host | smart-f7a66dfd-fae5-48db-bb07-7a41619d53fa |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3237194480 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_rw.3237194480 |
| Directory | /workspace/0.rom_ctrl_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_partial_access.3007659984 |
| Short name | T377 |
| Test name | |
| Test status | |
| Simulation time | 4152653846 ps |
| CPU time | 6.82 seconds |
| Started | May 05 12:45:22 PM PDT 24 |
| Finished | May 05 12:45:30 PM PDT 24 |
| Peak memory | 210340 kb |
| Host | smart-f4379888-05f9-47bb-80e7-fcf62e367bf9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3007659984 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom _ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctr l_mem_partial_access.3007659984 |
| Directory | /workspace/0.rom_ctrl_mem_partial_access/latest |
| Test location | /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_walk.1609763901 |
| Short name | T385 |
| Test name | |
| Test status | |
| Simulation time | 7266291796 ps |
| CPU time | 14.03 seconds |
| Started | May 05 12:45:22 PM PDT 24 |
| Finished | May 05 12:45:37 PM PDT 24 |
| Peak memory | 210372 kb |
| Host | smart-4fc0e03b-e8f5-4c10-9a87-3b5b6ec98cf4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1609763901 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_mem_walk .1609763901 |
| Directory | /workspace/0.rom_ctrl_mem_walk/latest |
| Test location | /workspace/coverage/cover_reg_top/0.rom_ctrl_passthru_mem_tl_intg_err.3978031101 |
| Short name | T84 |
| Test name | |
| Test status | |
| Simulation time | 3014626291 ps |
| CPU time | 28.39 seconds |
| Started | May 05 12:45:20 PM PDT 24 |
| Finished | May 05 12:45:49 PM PDT 24 |
| Peak memory | 210464 kb |
| Host | smart-fe78523d-c40b-41af-a4fe-5e9e9fa60122 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3978031101 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_pa ssthru_mem_tl_intg_err.3978031101 |
| Directory | /workspace/0.rom_ctrl_passthru_mem_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/0.rom_ctrl_same_csr_outstanding.2290227722 |
| Short name | T99 |
| Test name | |
| Test status | |
| Simulation time | 8829939500 ps |
| CPU time | 16.65 seconds |
| Started | May 05 12:45:22 PM PDT 24 |
| Finished | May 05 12:45:40 PM PDT 24 |
| Peak memory | 210544 kb |
| Host | smart-8025f0c4-0165-45e7-956a-d1e87892f2b0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2290227722 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_c trl_same_csr_outstanding.2290227722 |
| Directory | /workspace/0.rom_ctrl_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_errors.912408421 |
| Short name | T371 |
| Test name | |
| Test status | |
| Simulation time | 786441894 ps |
| CPU time | 13.35 seconds |
| Started | May 05 12:45:21 PM PDT 24 |
| Finished | May 05 12:45:36 PM PDT 24 |
| Peak memory | 218684 kb |
| Host | smart-68d762f9-e991-4c6c-9535-319bbf52ef49 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=912408421 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_tl_errors.912408421 |
| Directory | /workspace/0.rom_ctrl_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_aliasing.2740388456 |
| Short name | T86 |
| Test name | |
| Test status | |
| Simulation time | 2047375087 ps |
| CPU time | 10.16 seconds |
| Started | May 05 12:45:27 PM PDT 24 |
| Finished | May 05 12:45:38 PM PDT 24 |
| Peak memory | 210408 kb |
| Host | smart-1a16df87-a97d-4c64-b887-715999abea0a |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2740388456 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_alia sing.2740388456 |
| Directory | /workspace/1.rom_ctrl_csr_aliasing/latest |
| Test location | /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_bit_bash.3993778265 |
| Short name | T380 |
| Test name | |
| Test status | |
| Simulation time | 3584779026 ps |
| CPU time | 14.23 seconds |
| Started | May 05 12:45:33 PM PDT 24 |
| Finished | May 05 12:45:48 PM PDT 24 |
| Peak memory | 210464 kb |
| Host | smart-44ba7663-e700-4465-9295-97fa5e1950c2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3993778265 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_bit_ bash.3993778265 |
| Directory | /workspace/1.rom_ctrl_csr_bit_bash/latest |
| Test location | /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_hw_reset.2781479177 |
| Short name | T81 |
| Test name | |
| Test status | |
| Simulation time | 719687021 ps |
| CPU time | 10.25 seconds |
| Started | May 05 12:45:36 PM PDT 24 |
| Finished | May 05 12:45:52 PM PDT 24 |
| Peak memory | 210356 kb |
| Host | smart-86388ac7-0e61-4dfd-876b-8be8ffbeba6e |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2781479177 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_hw_r eset.2781479177 |
| Directory | /workspace/1.rom_ctrl_csr_hw_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_mem_rw_with_rand_reset.1879133898 |
| Short name | T372 |
| Test name | |
| Test status | |
| Simulation time | 1893144425 ps |
| CPU time | 14.01 seconds |
| Started | May 05 12:45:49 PM PDT 24 |
| Finished | May 05 12:46:04 PM PDT 24 |
| Peak memory | 218720 kb |
| Host | smart-d585bb98-6bea-4c98-883d-1aa05041bd98 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1879133898 -assert nopostproc +UVM_TESTNAME =rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_mem_rw_with_rand_reset.1879133898 |
| Directory | /workspace/1.rom_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_rw.38108176 |
| Short name | T402 |
| Test name | |
| Test status | |
| Simulation time | 1005480192 ps |
| CPU time | 10.18 seconds |
| Started | May 05 12:45:47 PM PDT 24 |
| Finished | May 05 12:45:58 PM PDT 24 |
| Peak memory | 210492 kb |
| Host | smart-7bcb6494-9cc3-4378-bff2-4b8c1c1ef31e |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38108176 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_rw.38108176 |
| Directory | /workspace/1.rom_ctrl_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_partial_access.2111635599 |
| Short name | T443 |
| Test name | |
| Test status | |
| Simulation time | 1212021259 ps |
| CPU time | 7.65 seconds |
| Started | May 05 12:45:25 PM PDT 24 |
| Finished | May 05 12:45:34 PM PDT 24 |
| Peak memory | 210328 kb |
| Host | smart-8688eef1-9ef2-4a69-8a23-a4d72f860b8b |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2111635599 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom _ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctr l_mem_partial_access.2111635599 |
| Directory | /workspace/1.rom_ctrl_mem_partial_access/latest |
| Test location | /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_walk.3661056923 |
| Short name | T451 |
| Test name | |
| Test status | |
| Simulation time | 827217976 ps |
| CPU time | 9 seconds |
| Started | May 05 12:45:55 PM PDT 24 |
| Finished | May 05 12:46:05 PM PDT 24 |
| Peak memory | 210320 kb |
| Host | smart-becf5b9c-815c-49d1-a94b-82c97225ebba |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3661056923 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_mem_walk .3661056923 |
| Directory | /workspace/1.rom_ctrl_mem_walk/latest |
| Test location | /workspace/coverage/cover_reg_top/1.rom_ctrl_passthru_mem_tl_intg_err.1398412368 |
| Short name | T454 |
| Test name | |
| Test status | |
| Simulation time | 2617479781 ps |
| CPU time | 42.84 seconds |
| Started | May 05 12:45:26 PM PDT 24 |
| Finished | May 05 12:46:10 PM PDT 24 |
| Peak memory | 210500 kb |
| Host | smart-a60c7ae7-b648-4150-9923-60d27c00440a |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1398412368 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_pa ssthru_mem_tl_intg_err.1398412368 |
| Directory | /workspace/1.rom_ctrl_passthru_mem_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/1.rom_ctrl_same_csr_outstanding.1748167583 |
| Short name | T50 |
| Test name | |
| Test status | |
| Simulation time | 769925740 ps |
| CPU time | 8.96 seconds |
| Started | May 05 12:45:29 PM PDT 24 |
| Finished | May 05 12:45:38 PM PDT 24 |
| Peak memory | 210444 kb |
| Host | smart-05fb7648-7090-42cb-bb2b-91d2d946939c |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1748167583 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_c trl_same_csr_outstanding.1748167583 |
| Directory | /workspace/1.rom_ctrl_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_errors.855132280 |
| Short name | T437 |
| Test name | |
| Test status | |
| Simulation time | 139884788 ps |
| CPU time | 9.1 seconds |
| Started | May 05 12:45:20 PM PDT 24 |
| Finished | May 05 12:45:30 PM PDT 24 |
| Peak memory | 218744 kb |
| Host | smart-a9be290b-4576-40fd-ac9d-745516ab2dae |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=855132280 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_tl_errors.855132280 |
| Directory | /workspace/1.rom_ctrl_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_intg_err.3245996716 |
| Short name | T120 |
| Test name | |
| Test status | |
| Simulation time | 2133417298 ps |
| CPU time | 48.07 seconds |
| Started | May 05 12:45:26 PM PDT 24 |
| Finished | May 05 12:46:15 PM PDT 24 |
| Peak memory | 212380 kb |
| Host | smart-e2f6b2fb-1d5c-4e14-80b1-466b0c3ab3e1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3245996716 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_tl_in tg_err.3245996716 |
| Directory | /workspace/1.rom_ctrl_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_mem_rw_with_rand_reset.3627594589 |
| Short name | T413 |
| Test name | |
| Test status | |
| Simulation time | 1737674537 ps |
| CPU time | 7.8 seconds |
| Started | May 05 12:46:02 PM PDT 24 |
| Finished | May 05 12:46:10 PM PDT 24 |
| Peak memory | 213580 kb |
| Host | smart-827fdc21-6791-47fd-8399-47ca4566fefc |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3627594589 -assert nopostproc +UVM_TESTNAME =rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_csr_mem_rw_with_rand_reset.3627594589 |
| Directory | /workspace/10.rom_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_rw.2242214572 |
| Short name | T105 |
| Test name | |
| Test status | |
| Simulation time | 2502016003 ps |
| CPU time | 11.45 seconds |
| Started | May 05 12:45:44 PM PDT 24 |
| Finished | May 05 12:45:56 PM PDT 24 |
| Peak memory | 210464 kb |
| Host | smart-0bf00ce2-a786-489b-aadd-226d52b1dfb5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2242214572 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_csr_rw.2242214572 |
| Directory | /workspace/10.rom_ctrl_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/10.rom_ctrl_same_csr_outstanding.2721358029 |
| Short name | T412 |
| Test name | |
| Test status | |
| Simulation time | 4023620396 ps |
| CPU time | 15.34 seconds |
| Started | May 05 12:45:54 PM PDT 24 |
| Finished | May 05 12:46:11 PM PDT 24 |
| Peak memory | 210540 kb |
| Host | smart-a765fe59-4931-4f62-ba2e-d3a408b041f6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2721358029 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ ctrl_same_csr_outstanding.2721358029 |
| Directory | /workspace/10.rom_ctrl_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_errors.265772508 |
| Short name | T406 |
| Test name | |
| Test status | |
| Simulation time | 3698570884 ps |
| CPU time | 16.95 seconds |
| Started | May 05 12:45:58 PM PDT 24 |
| Finished | May 05 12:46:16 PM PDT 24 |
| Peak memory | 218748 kb |
| Host | smart-9ccf6e42-4e35-42e5-9f03-862ddf811a4b |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=265772508 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_tl_errors.265772508 |
| Directory | /workspace/10.rom_ctrl_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_mem_rw_with_rand_reset.1706348189 |
| Short name | T463 |
| Test name | |
| Test status | |
| Simulation time | 379129468 ps |
| CPU time | 4.63 seconds |
| Started | May 05 12:45:43 PM PDT 24 |
| Finished | May 05 12:45:49 PM PDT 24 |
| Peak memory | 213240 kb |
| Host | smart-acb3e5f7-b343-45bb-bf65-f7aae0a34f43 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1706348189 -assert nopostproc +UVM_TESTNAME =rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_csr_mem_rw_with_rand_reset.1706348189 |
| Directory | /workspace/11.rom_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_rw.117537837 |
| Short name | T65 |
| Test name | |
| Test status | |
| Simulation time | 1705425455 ps |
| CPU time | 14.26 seconds |
| Started | May 05 12:45:54 PM PDT 24 |
| Finished | May 05 12:46:09 PM PDT 24 |
| Peak memory | 210440 kb |
| Host | smart-7ceaa3b0-1da1-4759-9aca-6dde720c823b |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=117537837 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_csr_rw.117537837 |
| Directory | /workspace/11.rom_ctrl_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/11.rom_ctrl_passthru_mem_tl_intg_err.2471969392 |
| Short name | T79 |
| Test name | |
| Test status | |
| Simulation time | 33595829337 ps |
| CPU time | 76.79 seconds |
| Started | May 05 12:45:42 PM PDT 24 |
| Finished | May 05 12:47:00 PM PDT 24 |
| Peak memory | 210480 kb |
| Host | smart-08d90476-f9e8-4a18-af18-df6b1e43e79c |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2471969392 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_p assthru_mem_tl_intg_err.2471969392 |
| Directory | /workspace/11.rom_ctrl_passthru_mem_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/11.rom_ctrl_same_csr_outstanding.1701609286 |
| Short name | T51 |
| Test name | |
| Test status | |
| Simulation time | 536954187 ps |
| CPU time | 9.52 seconds |
| Started | May 05 12:46:04 PM PDT 24 |
| Finished | May 05 12:46:14 PM PDT 24 |
| Peak memory | 210396 kb |
| Host | smart-e8177d92-3280-4a9f-8097-d21f51d4c74b |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1701609286 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ ctrl_same_csr_outstanding.1701609286 |
| Directory | /workspace/11.rom_ctrl_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_errors.4116745696 |
| Short name | T374 |
| Test name | |
| Test status | |
| Simulation time | 566011679 ps |
| CPU time | 7.1 seconds |
| Started | May 05 12:46:06 PM PDT 24 |
| Finished | May 05 12:46:14 PM PDT 24 |
| Peak memory | 218720 kb |
| Host | smart-6943c4e9-3766-4115-a245-3ed8cd85dacb |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4116745696 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_tl_errors.4116745696 |
| Directory | /workspace/11.rom_ctrl_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_intg_err.3702689287 |
| Short name | T448 |
| Test name | |
| Test status | |
| Simulation time | 2234413324 ps |
| CPU time | 77.21 seconds |
| Started | May 05 12:45:52 PM PDT 24 |
| Finished | May 05 12:47:10 PM PDT 24 |
| Peak memory | 211516 kb |
| Host | smart-5ddb5048-3a92-45b2-8efc-5b018a21ca78 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3702689287 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_tl_i ntg_err.3702689287 |
| Directory | /workspace/11.rom_ctrl_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_mem_rw_with_rand_reset.4190020653 |
| Short name | T425 |
| Test name | |
| Test status | |
| Simulation time | 12076884960 ps |
| CPU time | 14.75 seconds |
| Started | May 05 12:45:51 PM PDT 24 |
| Finished | May 05 12:46:07 PM PDT 24 |
| Peak memory | 212488 kb |
| Host | smart-6b744185-5e38-464d-844c-5760af6fb84c |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4190020653 -assert nopostproc +UVM_TESTNAME =rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_csr_mem_rw_with_rand_reset.4190020653 |
| Directory | /workspace/12.rom_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_rw.2274455494 |
| Short name | T77 |
| Test name | |
| Test status | |
| Simulation time | 2378340208 ps |
| CPU time | 11.71 seconds |
| Started | May 05 12:46:08 PM PDT 24 |
| Finished | May 05 12:46:20 PM PDT 24 |
| Peak memory | 210608 kb |
| Host | smart-71ed4e9e-15cd-47c0-82bd-7886a7d1a5fd |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2274455494 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_csr_rw.2274455494 |
| Directory | /workspace/12.rom_ctrl_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/12.rom_ctrl_passthru_mem_tl_intg_err.2219166664 |
| Short name | T424 |
| Test name | |
| Test status | |
| Simulation time | 12144857359 ps |
| CPU time | 62.25 seconds |
| Started | May 05 12:45:57 PM PDT 24 |
| Finished | May 05 12:47:00 PM PDT 24 |
| Peak memory | 210556 kb |
| Host | smart-bce36284-026c-4cc8-ab2a-f5e240c923d5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2219166664 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_p assthru_mem_tl_intg_err.2219166664 |
| Directory | /workspace/12.rom_ctrl_passthru_mem_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/12.rom_ctrl_same_csr_outstanding.3341961628 |
| Short name | T100 |
| Test name | |
| Test status | |
| Simulation time | 464562321 ps |
| CPU time | 7.26 seconds |
| Started | May 05 12:45:42 PM PDT 24 |
| Finished | May 05 12:45:50 PM PDT 24 |
| Peak memory | 210444 kb |
| Host | smart-2255b3fc-087e-4e72-aa69-3e1af14565b5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3341961628 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ ctrl_same_csr_outstanding.3341961628 |
| Directory | /workspace/12.rom_ctrl_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_errors.771281652 |
| Short name | T434 |
| Test name | |
| Test status | |
| Simulation time | 1669730856 ps |
| CPU time | 15.92 seconds |
| Started | May 05 12:45:56 PM PDT 24 |
| Finished | May 05 12:46:13 PM PDT 24 |
| Peak memory | 218760 kb |
| Host | smart-7fa4b907-5746-4476-9c75-e80b4613945b |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=771281652 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_tl_errors.771281652 |
| Directory | /workspace/12.rom_ctrl_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_intg_err.2340314391 |
| Short name | T447 |
| Test name | |
| Test status | |
| Simulation time | 998679304 ps |
| CPU time | 72.08 seconds |
| Started | May 05 12:46:04 PM PDT 24 |
| Finished | May 05 12:47:16 PM PDT 24 |
| Peak memory | 218720 kb |
| Host | smart-3d73f566-1c47-4d28-bd1e-eda212e980b4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2340314391 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_tl_i ntg_err.2340314391 |
| Directory | /workspace/12.rom_ctrl_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_mem_rw_with_rand_reset.1284292580 |
| Short name | T439 |
| Test name | |
| Test status | |
| Simulation time | 1749736193 ps |
| CPU time | 7.77 seconds |
| Started | May 05 12:45:57 PM PDT 24 |
| Finished | May 05 12:46:06 PM PDT 24 |
| Peak memory | 218708 kb |
| Host | smart-ee391f64-07cb-45cb-8748-d700fa97c34c |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1284292580 -assert nopostproc +UVM_TESTNAME =rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_csr_mem_rw_with_rand_reset.1284292580 |
| Directory | /workspace/13.rom_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_rw.3420757085 |
| Short name | T101 |
| Test name | |
| Test status | |
| Simulation time | 6327372555 ps |
| CPU time | 8.52 seconds |
| Started | May 05 12:45:42 PM PDT 24 |
| Finished | May 05 12:45:51 PM PDT 24 |
| Peak memory | 210492 kb |
| Host | smart-18cc5b40-3e1a-4d4e-821f-7a8d15a0e3fe |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3420757085 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_csr_rw.3420757085 |
| Directory | /workspace/13.rom_ctrl_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/13.rom_ctrl_passthru_mem_tl_intg_err.975053793 |
| Short name | T467 |
| Test name | |
| Test status | |
| Simulation time | 13878247183 ps |
| CPU time | 58.43 seconds |
| Started | May 05 12:45:43 PM PDT 24 |
| Finished | May 05 12:46:43 PM PDT 24 |
| Peak memory | 210604 kb |
| Host | smart-32feaad0-7dc6-4399-bd4f-b4e6c70d1eb7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=975053793 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl _common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_pa ssthru_mem_tl_intg_err.975053793 |
| Directory | /workspace/13.rom_ctrl_passthru_mem_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/13.rom_ctrl_same_csr_outstanding.600024007 |
| Short name | T398 |
| Test name | |
| Test status | |
| Simulation time | 320172875 ps |
| CPU time | 4.35 seconds |
| Started | May 05 12:46:05 PM PDT 24 |
| Finished | May 05 12:46:10 PM PDT 24 |
| Peak memory | 210464 kb |
| Host | smart-a8795913-3da3-4095-8c07-86902252e671 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=600024007 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_c trl_same_csr_outstanding.600024007 |
| Directory | /workspace/13.rom_ctrl_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_errors.1636598955 |
| Short name | T378 |
| Test name | |
| Test status | |
| Simulation time | 9454643378 ps |
| CPU time | 17.95 seconds |
| Started | May 05 12:45:44 PM PDT 24 |
| Finished | May 05 12:46:03 PM PDT 24 |
| Peak memory | 218724 kb |
| Host | smart-eea97157-496e-4f63-b63a-ca5884af9c1d |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1636598955 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_tl_errors.1636598955 |
| Directory | /workspace/13.rom_ctrl_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_intg_err.3908028700 |
| Short name | T47 |
| Test name | |
| Test status | |
| Simulation time | 571942471 ps |
| CPU time | 39.93 seconds |
| Started | May 05 12:46:00 PM PDT 24 |
| Finished | May 05 12:46:41 PM PDT 24 |
| Peak memory | 210456 kb |
| Host | smart-95baf989-3b4c-45e0-8bb9-733ae4c31e7b |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3908028700 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_tl_i ntg_err.3908028700 |
| Directory | /workspace/13.rom_ctrl_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_mem_rw_with_rand_reset.2128079969 |
| Short name | T446 |
| Test name | |
| Test status | |
| Simulation time | 1199481128 ps |
| CPU time | 11.98 seconds |
| Started | May 05 12:45:48 PM PDT 24 |
| Finished | May 05 12:46:01 PM PDT 24 |
| Peak memory | 218664 kb |
| Host | smart-b4e6ba38-4c54-4614-836d-a9d00048db95 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2128079969 -assert nopostproc +UVM_TESTNAME =rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_csr_mem_rw_with_rand_reset.2128079969 |
| Directory | /workspace/14.rom_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_rw.341776518 |
| Short name | T82 |
| Test name | |
| Test status | |
| Simulation time | 2850408893 ps |
| CPU time | 8.17 seconds |
| Started | May 05 12:45:58 PM PDT 24 |
| Finished | May 05 12:46:06 PM PDT 24 |
| Peak memory | 210532 kb |
| Host | smart-a08a30fb-ce13-40f1-9b22-6c0cac2bf10d |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=341776518 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_csr_rw.341776518 |
| Directory | /workspace/14.rom_ctrl_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/14.rom_ctrl_passthru_mem_tl_intg_err.1158020813 |
| Short name | T391 |
| Test name | |
| Test status | |
| Simulation time | 2134346403 ps |
| CPU time | 40.94 seconds |
| Started | May 05 12:45:58 PM PDT 24 |
| Finished | May 05 12:46:40 PM PDT 24 |
| Peak memory | 210532 kb |
| Host | smart-c85d450d-f814-4bda-88ee-fa019f0eb62e |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1158020813 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_p assthru_mem_tl_intg_err.1158020813 |
| Directory | /workspace/14.rom_ctrl_passthru_mem_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/14.rom_ctrl_same_csr_outstanding.1676252827 |
| Short name | T465 |
| Test name | |
| Test status | |
| Simulation time | 3643877761 ps |
| CPU time | 14.14 seconds |
| Started | May 05 12:45:40 PM PDT 24 |
| Finished | May 05 12:45:55 PM PDT 24 |
| Peak memory | 210544 kb |
| Host | smart-f3853498-cb31-4842-ab1a-4fafe3af6073 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1676252827 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ ctrl_same_csr_outstanding.1676252827 |
| Directory | /workspace/14.rom_ctrl_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_errors.4002587464 |
| Short name | T403 |
| Test name | |
| Test status | |
| Simulation time | 132400129 ps |
| CPU time | 9.01 seconds |
| Started | May 05 12:45:57 PM PDT 24 |
| Finished | May 05 12:46:06 PM PDT 24 |
| Peak memory | 218792 kb |
| Host | smart-e6f7a3f7-6160-4c34-8473-2e79f089803b |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4002587464 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_tl_errors.4002587464 |
| Directory | /workspace/14.rom_ctrl_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_mem_rw_with_rand_reset.498525896 |
| Short name | T381 |
| Test name | |
| Test status | |
| Simulation time | 876680066 ps |
| CPU time | 9.75 seconds |
| Started | May 05 12:45:47 PM PDT 24 |
| Finished | May 05 12:45:58 PM PDT 24 |
| Peak memory | 210760 kb |
| Host | smart-41319f3e-0ddc-4358-8868-2ae216bf0df4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=498525896 -assert nopostproc +UVM_TESTNAME= rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_csr_mem_rw_with_rand_reset.498525896 |
| Directory | /workspace/15.rom_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_rw.1769763672 |
| Short name | T433 |
| Test name | |
| Test status | |
| Simulation time | 2363806839 ps |
| CPU time | 11.12 seconds |
| Started | May 05 12:46:03 PM PDT 24 |
| Finished | May 05 12:46:15 PM PDT 24 |
| Peak memory | 210540 kb |
| Host | smart-cdb38aff-f1e3-4cf7-b74c-2d1ccebd1e82 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1769763672 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_csr_rw.1769763672 |
| Directory | /workspace/15.rom_ctrl_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/15.rom_ctrl_passthru_mem_tl_intg_err.102932645 |
| Short name | T78 |
| Test name | |
| Test status | |
| Simulation time | 33523629664 ps |
| CPU time | 62.23 seconds |
| Started | May 05 12:46:08 PM PDT 24 |
| Finished | May 05 12:47:12 PM PDT 24 |
| Peak memory | 210556 kb |
| Host | smart-046113ff-305a-405a-9eef-b87484d6c8be |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=102932645 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl _common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_pa ssthru_mem_tl_intg_err.102932645 |
| Directory | /workspace/15.rom_ctrl_passthru_mem_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/15.rom_ctrl_same_csr_outstanding.3162230377 |
| Short name | T60 |
| Test name | |
| Test status | |
| Simulation time | 12997412369 ps |
| CPU time | 13.28 seconds |
| Started | May 05 12:45:52 PM PDT 24 |
| Finished | May 05 12:46:06 PM PDT 24 |
| Peak memory | 210516 kb |
| Host | smart-14a7cdb4-7b83-4917-97c3-b15b30a26051 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3162230377 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ ctrl_same_csr_outstanding.3162230377 |
| Directory | /workspace/15.rom_ctrl_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_errors.3622005677 |
| Short name | T401 |
| Test name | |
| Test status | |
| Simulation time | 136739227 ps |
| CPU time | 9.85 seconds |
| Started | May 05 12:45:51 PM PDT 24 |
| Finished | May 05 12:46:01 PM PDT 24 |
| Peak memory | 218688 kb |
| Host | smart-e4873c9b-4072-4749-94f0-da096f463c68 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3622005677 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_tl_errors.3622005677 |
| Directory | /workspace/15.rom_ctrl_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_intg_err.1265382842 |
| Short name | T46 |
| Test name | |
| Test status | |
| Simulation time | 399615415 ps |
| CPU time | 35.32 seconds |
| Started | May 05 12:45:47 PM PDT 24 |
| Finished | May 05 12:46:24 PM PDT 24 |
| Peak memory | 210488 kb |
| Host | smart-06d27f79-c971-4e0b-8c2a-b22f8014c80d |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1265382842 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_tl_i ntg_err.1265382842 |
| Directory | /workspace/15.rom_ctrl_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_mem_rw_with_rand_reset.579041675 |
| Short name | T376 |
| Test name | |
| Test status | |
| Simulation time | 16219931650 ps |
| CPU time | 12.69 seconds |
| Started | May 05 12:45:49 PM PDT 24 |
| Finished | May 05 12:46:02 PM PDT 24 |
| Peak memory | 218804 kb |
| Host | smart-ad97bfda-3b98-47f5-b9e7-c4e571d32fdd |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=579041675 -assert nopostproc +UVM_TESTNAME= rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_csr_mem_rw_with_rand_reset.579041675 |
| Directory | /workspace/16.rom_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_rw.2239318738 |
| Short name | T74 |
| Test name | |
| Test status | |
| Simulation time | 1926985443 ps |
| CPU time | 14.9 seconds |
| Started | May 05 12:46:15 PM PDT 24 |
| Finished | May 05 12:46:31 PM PDT 24 |
| Peak memory | 210360 kb |
| Host | smart-f094a3af-d998-4276-acf1-81c6faef8173 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2239318738 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_csr_rw.2239318738 |
| Directory | /workspace/16.rom_ctrl_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/16.rom_ctrl_passthru_mem_tl_intg_err.877932744 |
| Short name | T80 |
| Test name | |
| Test status | |
| Simulation time | 13529885151 ps |
| CPU time | 62.24 seconds |
| Started | May 05 12:45:51 PM PDT 24 |
| Finished | May 05 12:46:54 PM PDT 24 |
| Peak memory | 210604 kb |
| Host | smart-528b0c22-565f-4aa8-8ae8-a021a24ca8a3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=877932744 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl _common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_pa ssthru_mem_tl_intg_err.877932744 |
| Directory | /workspace/16.rom_ctrl_passthru_mem_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/16.rom_ctrl_same_csr_outstanding.3900576677 |
| Short name | T427 |
| Test name | |
| Test status | |
| Simulation time | 6822604347 ps |
| CPU time | 14.66 seconds |
| Started | May 05 12:45:50 PM PDT 24 |
| Finished | May 05 12:46:06 PM PDT 24 |
| Peak memory | 210552 kb |
| Host | smart-ef94c160-d2d1-4ec1-8faa-e05c67682fe8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3900576677 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ ctrl_same_csr_outstanding.3900576677 |
| Directory | /workspace/16.rom_ctrl_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_errors.76310050 |
| Short name | T440 |
| Test name | |
| Test status | |
| Simulation time | 5932984185 ps |
| CPU time | 16.98 seconds |
| Started | May 05 12:45:48 PM PDT 24 |
| Finished | May 05 12:46:06 PM PDT 24 |
| Peak memory | 218732 kb |
| Host | smart-f762c982-bade-4a37-a936-b7a309698c62 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76310050 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_tl_errors.76310050 |
| Directory | /workspace/16.rom_ctrl_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_intg_err.1733526218 |
| Short name | T466 |
| Test name | |
| Test status | |
| Simulation time | 1864017873 ps |
| CPU time | 46.51 seconds |
| Started | May 05 12:45:55 PM PDT 24 |
| Finished | May 05 12:46:42 PM PDT 24 |
| Peak memory | 211268 kb |
| Host | smart-519d5ba6-386d-4acc-bf4b-d823a6e22964 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1733526218 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_tl_i ntg_err.1733526218 |
| Directory | /workspace/16.rom_ctrl_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_mem_rw_with_rand_reset.1015049504 |
| Short name | T450 |
| Test name | |
| Test status | |
| Simulation time | 205551187 ps |
| CPU time | 5.22 seconds |
| Started | May 05 12:45:48 PM PDT 24 |
| Finished | May 05 12:45:55 PM PDT 24 |
| Peak memory | 218672 kb |
| Host | smart-185c7cc6-84fc-4f2e-ae1d-cb1b3707b1e3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1015049504 -assert nopostproc +UVM_TESTNAME =rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_csr_mem_rw_with_rand_reset.1015049504 |
| Directory | /workspace/17.rom_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_rw.2528796342 |
| Short name | T102 |
| Test name | |
| Test status | |
| Simulation time | 347076175 ps |
| CPU time | 4.15 seconds |
| Started | May 05 12:46:04 PM PDT 24 |
| Finished | May 05 12:46:09 PM PDT 24 |
| Peak memory | 210448 kb |
| Host | smart-4e123b3d-d5c6-4b3d-aa1e-737e2adde0d3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2528796342 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_csr_rw.2528796342 |
| Directory | /workspace/17.rom_ctrl_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/17.rom_ctrl_passthru_mem_tl_intg_err.4076533810 |
| Short name | T76 |
| Test name | |
| Test status | |
| Simulation time | 9004334256 ps |
| CPU time | 42.03 seconds |
| Started | May 05 12:46:02 PM PDT 24 |
| Finished | May 05 12:46:44 PM PDT 24 |
| Peak memory | 217664 kb |
| Host | smart-4ac8fd9c-f1c5-4103-8f65-b4a64a9e69d8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4076533810 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_p assthru_mem_tl_intg_err.4076533810 |
| Directory | /workspace/17.rom_ctrl_passthru_mem_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/17.rom_ctrl_same_csr_outstanding.1225316007 |
| Short name | T421 |
| Test name | |
| Test status | |
| Simulation time | 297183219 ps |
| CPU time | 4.26 seconds |
| Started | May 05 12:45:48 PM PDT 24 |
| Finished | May 05 12:45:54 PM PDT 24 |
| Peak memory | 210436 kb |
| Host | smart-54c4f273-5b44-4ab7-b358-fe10a99a072e |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1225316007 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ ctrl_same_csr_outstanding.1225316007 |
| Directory | /workspace/17.rom_ctrl_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_errors.525778898 |
| Short name | T379 |
| Test name | |
| Test status | |
| Simulation time | 131569348 ps |
| CPU time | 8.92 seconds |
| Started | May 05 12:45:51 PM PDT 24 |
| Finished | May 05 12:46:00 PM PDT 24 |
| Peak memory | 218688 kb |
| Host | smart-e2d090d2-ef2a-4133-830e-926783257861 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=525778898 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_tl_errors.525778898 |
| Directory | /workspace/17.rom_ctrl_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_intg_err.1975751638 |
| Short name | T419 |
| Test name | |
| Test status | |
| Simulation time | 588753418 ps |
| CPU time | 36 seconds |
| Started | May 05 12:45:48 PM PDT 24 |
| Finished | May 05 12:46:25 PM PDT 24 |
| Peak memory | 211052 kb |
| Host | smart-dec2942a-d324-4eb1-95f2-5573aa3f621d |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1975751638 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_tl_i ntg_err.1975751638 |
| Directory | /workspace/17.rom_ctrl_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_mem_rw_with_rand_reset.1378788963 |
| Short name | T407 |
| Test name | |
| Test status | |
| Simulation time | 2284492237 ps |
| CPU time | 10.01 seconds |
| Started | May 05 12:46:13 PM PDT 24 |
| Finished | May 05 12:46:24 PM PDT 24 |
| Peak memory | 218664 kb |
| Host | smart-b960eb57-87fa-49c5-b929-ae4a8f04d94d |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1378788963 -assert nopostproc +UVM_TESTNAME =rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_csr_mem_rw_with_rand_reset.1378788963 |
| Directory | /workspace/18.rom_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_rw.4145059521 |
| Short name | T418 |
| Test name | |
| Test status | |
| Simulation time | 8776827361 ps |
| CPU time | 14.95 seconds |
| Started | May 05 12:45:52 PM PDT 24 |
| Finished | May 05 12:46:08 PM PDT 24 |
| Peak memory | 210504 kb |
| Host | smart-b37593a0-1264-4693-ae64-9eecf0c69084 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4145059521 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_csr_rw.4145059521 |
| Directory | /workspace/18.rom_ctrl_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/18.rom_ctrl_passthru_mem_tl_intg_err.2305341917 |
| Short name | T453 |
| Test name | |
| Test status | |
| Simulation time | 24915057079 ps |
| CPU time | 50.98 seconds |
| Started | May 05 12:46:11 PM PDT 24 |
| Finished | May 05 12:47:03 PM PDT 24 |
| Peak memory | 210600 kb |
| Host | smart-8133d896-0594-49d9-92a1-81a290ff9101 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2305341917 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_p assthru_mem_tl_intg_err.2305341917 |
| Directory | /workspace/18.rom_ctrl_passthru_mem_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/18.rom_ctrl_same_csr_outstanding.1345534917 |
| Short name | T457 |
| Test name | |
| Test status | |
| Simulation time | 97123731 ps |
| CPU time | 4.45 seconds |
| Started | May 05 12:45:52 PM PDT 24 |
| Finished | May 05 12:45:57 PM PDT 24 |
| Peak memory | 210444 kb |
| Host | smart-aa5cbaa2-4646-4314-987f-64ba73f22e80 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1345534917 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ ctrl_same_csr_outstanding.1345534917 |
| Directory | /workspace/18.rom_ctrl_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_errors.344886690 |
| Short name | T375 |
| Test name | |
| Test status | |
| Simulation time | 515270496 ps |
| CPU time | 8.85 seconds |
| Started | May 05 12:46:16 PM PDT 24 |
| Finished | May 05 12:46:26 PM PDT 24 |
| Peak memory | 218704 kb |
| Host | smart-f3e4786f-3418-4e04-aee1-04ace5adcf6e |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=344886690 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_tl_errors.344886690 |
| Directory | /workspace/18.rom_ctrl_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_intg_err.3060679256 |
| Short name | T117 |
| Test name | |
| Test status | |
| Simulation time | 1077445946 ps |
| CPU time | 73.56 seconds |
| Started | May 05 12:45:52 PM PDT 24 |
| Finished | May 05 12:47:07 PM PDT 24 |
| Peak memory | 210428 kb |
| Host | smart-c6af43f0-71ab-4233-abd1-356312e25f69 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3060679256 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_tl_i ntg_err.3060679256 |
| Directory | /workspace/18.rom_ctrl_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_mem_rw_with_rand_reset.2342851906 |
| Short name | T384 |
| Test name | |
| Test status | |
| Simulation time | 3086406456 ps |
| CPU time | 7.3 seconds |
| Started | May 05 12:45:58 PM PDT 24 |
| Finished | May 05 12:46:07 PM PDT 24 |
| Peak memory | 218764 kb |
| Host | smart-eb4ff3bc-5523-47e4-9ccd-9c635d74d7f7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2342851906 -assert nopostproc +UVM_TESTNAME =rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_csr_mem_rw_with_rand_reset.2342851906 |
| Directory | /workspace/19.rom_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_rw.252008304 |
| Short name | T432 |
| Test name | |
| Test status | |
| Simulation time | 162152113 ps |
| CPU time | 4.18 seconds |
| Started | May 05 12:46:14 PM PDT 24 |
| Finished | May 05 12:46:19 PM PDT 24 |
| Peak memory | 210324 kb |
| Host | smart-28417daf-fc73-4f45-bb67-2814e5a0c41c |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=252008304 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_csr_rw.252008304 |
| Directory | /workspace/19.rom_ctrl_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/19.rom_ctrl_passthru_mem_tl_intg_err.3678162807 |
| Short name | T382 |
| Test name | |
| Test status | |
| Simulation time | 3484810201 ps |
| CPU time | 29.3 seconds |
| Started | May 05 12:45:51 PM PDT 24 |
| Finished | May 05 12:46:22 PM PDT 24 |
| Peak memory | 210516 kb |
| Host | smart-a6d87ec0-6130-4390-b314-5031d20d9527 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3678162807 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_p assthru_mem_tl_intg_err.3678162807 |
| Directory | /workspace/19.rom_ctrl_passthru_mem_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/19.rom_ctrl_same_csr_outstanding.1115610371 |
| Short name | T426 |
| Test name | |
| Test status | |
| Simulation time | 87991794 ps |
| CPU time | 4.3 seconds |
| Started | May 05 12:45:58 PM PDT 24 |
| Finished | May 05 12:46:03 PM PDT 24 |
| Peak memory | 210468 kb |
| Host | smart-2fd6a649-133b-40a8-8d5d-bce7de127a8f |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1115610371 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ ctrl_same_csr_outstanding.1115610371 |
| Directory | /workspace/19.rom_ctrl_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_errors.569924708 |
| Short name | T455 |
| Test name | |
| Test status | |
| Simulation time | 6612658700 ps |
| CPU time | 17.65 seconds |
| Started | May 05 12:45:55 PM PDT 24 |
| Finished | May 05 12:46:13 PM PDT 24 |
| Peak memory | 218728 kb |
| Host | smart-ca33a10b-80e5-4acb-b325-f7c402ff8604 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=569924708 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_tl_errors.569924708 |
| Directory | /workspace/19.rom_ctrl_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_aliasing.3032591970 |
| Short name | T104 |
| Test name | |
| Test status | |
| Simulation time | 7384483018 ps |
| CPU time | 14.66 seconds |
| Started | May 05 12:45:29 PM PDT 24 |
| Finished | May 05 12:45:44 PM PDT 24 |
| Peak memory | 210544 kb |
| Host | smart-3299b1a1-c3b4-4842-8e5a-c9d3bb9c853b |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3032591970 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_alia sing.3032591970 |
| Directory | /workspace/2.rom_ctrl_csr_aliasing/latest |
| Test location | /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_bit_bash.3149200806 |
| Short name | T400 |
| Test name | |
| Test status | |
| Simulation time | 4859237133 ps |
| CPU time | 10.73 seconds |
| Started | May 05 12:45:27 PM PDT 24 |
| Finished | May 05 12:45:39 PM PDT 24 |
| Peak memory | 210564 kb |
| Host | smart-a9ab6a69-7e55-4ca2-8959-88f65b95fb77 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3149200806 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_bit_ bash.3149200806 |
| Directory | /workspace/2.rom_ctrl_csr_bit_bash/latest |
| Test location | /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_hw_reset.3804252564 |
| Short name | T436 |
| Test name | |
| Test status | |
| Simulation time | 89674509 ps |
| CPU time | 7.33 seconds |
| Started | May 05 12:45:26 PM PDT 24 |
| Finished | May 05 12:45:35 PM PDT 24 |
| Peak memory | 210384 kb |
| Host | smart-0668cf1c-d976-4c7d-b152-0ba6c880827e |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3804252564 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_hw_r eset.3804252564 |
| Directory | /workspace/2.rom_ctrl_csr_hw_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_mem_rw_with_rand_reset.3934177305 |
| Short name | T416 |
| Test name | |
| Test status | |
| Simulation time | 3013343000 ps |
| CPU time | 13.5 seconds |
| Started | May 05 12:45:41 PM PDT 24 |
| Finished | May 05 12:45:55 PM PDT 24 |
| Peak memory | 211792 kb |
| Host | smart-c3c5bada-5247-4344-85d3-6b4eb3f37c2b |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3934177305 -assert nopostproc +UVM_TESTNAME =rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_mem_rw_with_rand_reset.3934177305 |
| Directory | /workspace/2.rom_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_rw.3434342832 |
| Short name | T431 |
| Test name | |
| Test status | |
| Simulation time | 3505168937 ps |
| CPU time | 14.36 seconds |
| Started | May 05 12:45:29 PM PDT 24 |
| Finished | May 05 12:45:44 PM PDT 24 |
| Peak memory | 210496 kb |
| Host | smart-3143fed2-37d4-4207-8d41-0ee200926a70 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3434342832 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_rw.3434342832 |
| Directory | /workspace/2.rom_ctrl_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_partial_access.4001641631 |
| Short name | T415 |
| Test name | |
| Test status | |
| Simulation time | 1430847467 ps |
| CPU time | 11.79 seconds |
| Started | May 05 12:45:29 PM PDT 24 |
| Finished | May 05 12:45:42 PM PDT 24 |
| Peak memory | 210352 kb |
| Host | smart-8dd65e26-f52f-4172-b76b-b768a78b8a23 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4001641631 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom _ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctr l_mem_partial_access.4001641631 |
| Directory | /workspace/2.rom_ctrl_mem_partial_access/latest |
| Test location | /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_walk.3600163248 |
| Short name | T409 |
| Test name | |
| Test status | |
| Simulation time | 4274654627 ps |
| CPU time | 9.93 seconds |
| Started | May 05 12:45:31 PM PDT 24 |
| Finished | May 05 12:45:42 PM PDT 24 |
| Peak memory | 210480 kb |
| Host | smart-70bf846f-2e28-47a6-9dd2-37e6869f0eba |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3600163248 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_mem_walk .3600163248 |
| Directory | /workspace/2.rom_ctrl_mem_walk/latest |
| Test location | /workspace/coverage/cover_reg_top/2.rom_ctrl_passthru_mem_tl_intg_err.2222485941 |
| Short name | T462 |
| Test name | |
| Test status | |
| Simulation time | 24637294839 ps |
| CPU time | 64.87 seconds |
| Started | May 05 12:45:44 PM PDT 24 |
| Finished | May 05 12:46:50 PM PDT 24 |
| Peak memory | 210588 kb |
| Host | smart-6a45a1f7-ca1b-4870-8147-b1c38abd75e8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2222485941 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_pa ssthru_mem_tl_intg_err.2222485941 |
| Directory | /workspace/2.rom_ctrl_passthru_mem_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/2.rom_ctrl_same_csr_outstanding.3844011242 |
| Short name | T438 |
| Test name | |
| Test status | |
| Simulation time | 1023446004 ps |
| CPU time | 10.63 seconds |
| Started | May 05 12:45:44 PM PDT 24 |
| Finished | May 05 12:45:56 PM PDT 24 |
| Peak memory | 210436 kb |
| Host | smart-d18a1b71-9840-47fb-ada7-6141769fdcd6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3844011242 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_c trl_same_csr_outstanding.3844011242 |
| Directory | /workspace/2.rom_ctrl_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_errors.2556886996 |
| Short name | T429 |
| Test name | |
| Test status | |
| Simulation time | 1314636209 ps |
| CPU time | 15.24 seconds |
| Started | May 05 12:45:25 PM PDT 24 |
| Finished | May 05 12:45:41 PM PDT 24 |
| Peak memory | 218644 kb |
| Host | smart-37560bf3-af21-4610-87fe-7b1ae02ae013 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2556886996 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_tl_errors.2556886996 |
| Directory | /workspace/2.rom_ctrl_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_aliasing.60808556 |
| Short name | T393 |
| Test name | |
| Test status | |
| Simulation time | 3909424502 ps |
| CPU time | 9.87 seconds |
| Started | May 05 12:45:27 PM PDT 24 |
| Finished | May 05 12:45:38 PM PDT 24 |
| Peak memory | 210488 kb |
| Host | smart-4f599797-0ee0-41ed-8473-773b30062c80 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=60808556 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_aliasi ng.60808556 |
| Directory | /workspace/3.rom_ctrl_csr_aliasing/latest |
| Test location | /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_bit_bash.189183430 |
| Short name | T456 |
| Test name | |
| Test status | |
| Simulation time | 2018051709 ps |
| CPU time | 16.05 seconds |
| Started | May 05 12:45:28 PM PDT 24 |
| Finished | May 05 12:45:44 PM PDT 24 |
| Peak memory | 210480 kb |
| Host | smart-45b6d86c-a1fd-4983-a204-b4ace9a764ec |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=189183430 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_bit_b ash.189183430 |
| Directory | /workspace/3.rom_ctrl_csr_bit_bash/latest |
| Test location | /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_hw_reset.617478510 |
| Short name | T397 |
| Test name | |
| Test status | |
| Simulation time | 88045436 ps |
| CPU time | 5.76 seconds |
| Started | May 05 12:45:54 PM PDT 24 |
| Finished | May 05 12:46:01 PM PDT 24 |
| Peak memory | 210500 kb |
| Host | smart-5ce0e985-a823-4354-967a-952059986713 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=617478510 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_hw_re set.617478510 |
| Directory | /workspace/3.rom_ctrl_csr_hw_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_mem_rw_with_rand_reset.1808503011 |
| Short name | T435 |
| Test name | |
| Test status | |
| Simulation time | 190443445 ps |
| CPU time | 4.61 seconds |
| Started | May 05 12:45:32 PM PDT 24 |
| Finished | May 05 12:45:37 PM PDT 24 |
| Peak memory | 212444 kb |
| Host | smart-d5b0eddd-f512-4768-8959-1ec8fb1eac44 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1808503011 -assert nopostproc +UVM_TESTNAME =rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_mem_rw_with_rand_reset.1808503011 |
| Directory | /workspace/3.rom_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_rw.2702763862 |
| Short name | T399 |
| Test name | |
| Test status | |
| Simulation time | 3078883545 ps |
| CPU time | 12.78 seconds |
| Started | May 05 12:45:34 PM PDT 24 |
| Finished | May 05 12:45:47 PM PDT 24 |
| Peak memory | 210540 kb |
| Host | smart-5a1a5085-5a91-4e71-88b2-bafe174aaf3b |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2702763862 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_rw.2702763862 |
| Directory | /workspace/3.rom_ctrl_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_partial_access.562730018 |
| Short name | T387 |
| Test name | |
| Test status | |
| Simulation time | 128281991 ps |
| CPU time | 4.06 seconds |
| Started | May 05 12:45:34 PM PDT 24 |
| Finished | May 05 12:45:38 PM PDT 24 |
| Peak memory | 210256 kb |
| Host | smart-ffd236ba-0f87-4a18-81fa-67e3dc817693 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=562730018 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl _mem_partial_access.562730018 |
| Directory | /workspace/3.rom_ctrl_mem_partial_access/latest |
| Test location | /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_walk.2501838413 |
| Short name | T422 |
| Test name | |
| Test status | |
| Simulation time | 347265389 ps |
| CPU time | 4.12 seconds |
| Started | May 05 12:45:26 PM PDT 24 |
| Finished | May 05 12:45:31 PM PDT 24 |
| Peak memory | 210424 kb |
| Host | smart-0c57db04-a227-4c30-b82a-58cc247dcac9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2501838413 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_mem_walk .2501838413 |
| Directory | /workspace/3.rom_ctrl_mem_walk/latest |
| Test location | /workspace/coverage/cover_reg_top/3.rom_ctrl_same_csr_outstanding.1569116159 |
| Short name | T59 |
| Test name | |
| Test status | |
| Simulation time | 3522447218 ps |
| CPU time | 15.94 seconds |
| Started | May 05 12:45:51 PM PDT 24 |
| Finished | May 05 12:46:07 PM PDT 24 |
| Peak memory | 210440 kb |
| Host | smart-2aa7d4fd-e102-4673-86d4-39619131490c |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1569116159 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_c trl_same_csr_outstanding.1569116159 |
| Directory | /workspace/3.rom_ctrl_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_errors.2131851932 |
| Short name | T386 |
| Test name | |
| Test status | |
| Simulation time | 478691835 ps |
| CPU time | 8.35 seconds |
| Started | May 05 12:45:31 PM PDT 24 |
| Finished | May 05 12:45:40 PM PDT 24 |
| Peak memory | 213660 kb |
| Host | smart-6ab29a05-c865-4a50-9ffa-48d72666dfc2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2131851932 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_tl_errors.2131851932 |
| Directory | /workspace/3.rom_ctrl_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_intg_err.4115029253 |
| Short name | T116 |
| Test name | |
| Test status | |
| Simulation time | 1440748239 ps |
| CPU time | 43.31 seconds |
| Started | May 05 12:45:31 PM PDT 24 |
| Finished | May 05 12:46:15 PM PDT 24 |
| Peak memory | 211252 kb |
| Host | smart-c9c30ca0-9a48-41f9-984d-bd333700a348 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4115029253 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_tl_in tg_err.4115029253 |
| Directory | /workspace/3.rom_ctrl_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_aliasing.1086691700 |
| Short name | T420 |
| Test name | |
| Test status | |
| Simulation time | 1687760683 ps |
| CPU time | 14.46 seconds |
| Started | May 05 12:45:49 PM PDT 24 |
| Finished | May 05 12:46:04 PM PDT 24 |
| Peak memory | 210456 kb |
| Host | smart-f95589d0-0787-4d92-b50f-5b20fba129b9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1086691700 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_alia sing.1086691700 |
| Directory | /workspace/4.rom_ctrl_csr_aliasing/latest |
| Test location | /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_bit_bash.3632474425 |
| Short name | T460 |
| Test name | |
| Test status | |
| Simulation time | 1246682626 ps |
| CPU time | 8.21 seconds |
| Started | May 05 12:45:30 PM PDT 24 |
| Finished | May 05 12:45:39 PM PDT 24 |
| Peak memory | 210384 kb |
| Host | smart-2bda1ce7-6b10-4237-94ee-56eae4648ba0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3632474425 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_bit_ bash.3632474425 |
| Directory | /workspace/4.rom_ctrl_csr_bit_bash/latest |
| Test location | /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_hw_reset.1919007583 |
| Short name | T430 |
| Test name | |
| Test status | |
| Simulation time | 7898428344 ps |
| CPU time | 16.82 seconds |
| Started | May 05 12:45:31 PM PDT 24 |
| Finished | May 05 12:45:48 PM PDT 24 |
| Peak memory | 210452 kb |
| Host | smart-9209466e-2d0e-47ba-820a-1abd22201162 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1919007583 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_hw_r eset.1919007583 |
| Directory | /workspace/4.rom_ctrl_csr_hw_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_mem_rw_with_rand_reset.2695983770 |
| Short name | T395 |
| Test name | |
| Test status | |
| Simulation time | 26658242394 ps |
| CPU time | 13.54 seconds |
| Started | May 05 12:45:31 PM PDT 24 |
| Finished | May 05 12:45:45 PM PDT 24 |
| Peak memory | 218776 kb |
| Host | smart-94513adc-23fa-4f2a-ab9d-cb5955f9588d |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2695983770 -assert nopostproc +UVM_TESTNAME =rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_mem_rw_with_rand_reset.2695983770 |
| Directory | /workspace/4.rom_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_rw.2517831947 |
| Short name | T404 |
| Test name | |
| Test status | |
| Simulation time | 1348223730 ps |
| CPU time | 8.11 seconds |
| Started | May 05 12:45:31 PM PDT 24 |
| Finished | May 05 12:45:40 PM PDT 24 |
| Peak memory | 210420 kb |
| Host | smart-cf8f4c4e-fe27-42da-8cff-0a04b8e9d4b1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2517831947 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_rw.2517831947 |
| Directory | /workspace/4.rom_ctrl_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_partial_access.1343536487 |
| Short name | T405 |
| Test name | |
| Test status | |
| Simulation time | 86393460 ps |
| CPU time | 4.14 seconds |
| Started | May 05 12:45:30 PM PDT 24 |
| Finished | May 05 12:45:35 PM PDT 24 |
| Peak memory | 210304 kb |
| Host | smart-612eb128-3367-4f38-a528-840f3a17a0e7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1343536487 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom _ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctr l_mem_partial_access.1343536487 |
| Directory | /workspace/4.rom_ctrl_mem_partial_access/latest |
| Test location | /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_walk.740926455 |
| Short name | T459 |
| Test name | |
| Test status | |
| Simulation time | 1764686890 ps |
| CPU time | 13.65 seconds |
| Started | May 05 12:45:30 PM PDT 24 |
| Finished | May 05 12:45:45 PM PDT 24 |
| Peak memory | 210356 kb |
| Host | smart-491cdafc-43c9-482b-aefd-2ba935fadbe7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=740926455 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_mem_walk. 740926455 |
| Directory | /workspace/4.rom_ctrl_mem_walk/latest |
| Test location | /workspace/coverage/cover_reg_top/4.rom_ctrl_passthru_mem_tl_intg_err.4165447402 |
| Short name | T75 |
| Test name | |
| Test status | |
| Simulation time | 67390772370 ps |
| CPU time | 72.56 seconds |
| Started | May 05 12:45:30 PM PDT 24 |
| Finished | May 05 12:46:43 PM PDT 24 |
| Peak memory | 210548 kb |
| Host | smart-d7bd493c-411e-4352-b63c-4d5570f32134 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4165447402 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_pa ssthru_mem_tl_intg_err.4165447402 |
| Directory | /workspace/4.rom_ctrl_passthru_mem_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/4.rom_ctrl_same_csr_outstanding.3489444228 |
| Short name | T444 |
| Test name | |
| Test status | |
| Simulation time | 168657201 ps |
| CPU time | 4.37 seconds |
| Started | May 05 12:45:31 PM PDT 24 |
| Finished | May 05 12:45:36 PM PDT 24 |
| Peak memory | 210488 kb |
| Host | smart-e680b5dc-0eb2-48da-b8ec-3c90fadaf4a1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3489444228 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_c trl_same_csr_outstanding.3489444228 |
| Directory | /workspace/4.rom_ctrl_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_errors.1211691518 |
| Short name | T458 |
| Test name | |
| Test status | |
| Simulation time | 1283308890 ps |
| CPU time | 16.03 seconds |
| Started | May 05 12:45:36 PM PDT 24 |
| Finished | May 05 12:45:53 PM PDT 24 |
| Peak memory | 218628 kb |
| Host | smart-bbd86fcc-495d-4ec6-bb09-d72d39b4b8a8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1211691518 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_tl_errors.1211691518 |
| Directory | /workspace/4.rom_ctrl_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_intg_err.4141530532 |
| Short name | T452 |
| Test name | |
| Test status | |
| Simulation time | 2267475140 ps |
| CPU time | 47.53 seconds |
| Started | May 05 12:45:36 PM PDT 24 |
| Finished | May 05 12:46:24 PM PDT 24 |
| Peak memory | 211116 kb |
| Host | smart-ea43f702-038a-4293-b25e-26fd7be0c8b5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4141530532 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_tl_in tg_err.4141530532 |
| Directory | /workspace/4.rom_ctrl_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_mem_rw_with_rand_reset.559182732 |
| Short name | T392 |
| Test name | |
| Test status | |
| Simulation time | 1166020075 ps |
| CPU time | 6.25 seconds |
| Started | May 05 12:45:32 PM PDT 24 |
| Finished | May 05 12:45:39 PM PDT 24 |
| Peak memory | 211344 kb |
| Host | smart-bddc58c5-8201-4f72-9b84-0060bdf40a1b |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=559182732 -assert nopostproc +UVM_TESTNAME= rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_csr_mem_rw_with_rand_reset.559182732 |
| Directory | /workspace/5.rom_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_rw.3163236833 |
| Short name | T66 |
| Test name | |
| Test status | |
| Simulation time | 8694827466 ps |
| CPU time | 8.52 seconds |
| Started | May 05 12:45:35 PM PDT 24 |
| Finished | May 05 12:45:44 PM PDT 24 |
| Peak memory | 210532 kb |
| Host | smart-a6310f9d-e1c9-4eb1-887b-e7be1d0a1db8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3163236833 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_csr_rw.3163236833 |
| Directory | /workspace/5.rom_ctrl_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/5.rom_ctrl_passthru_mem_tl_intg_err.4054675070 |
| Short name | T64 |
| Test name | |
| Test status | |
| Simulation time | 3477285602 ps |
| CPU time | 37.89 seconds |
| Started | May 05 12:45:58 PM PDT 24 |
| Finished | May 05 12:46:37 PM PDT 24 |
| Peak memory | 217548 kb |
| Host | smart-c50234c1-0451-49b4-89cf-f1d17fe0bec3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4054675070 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_pa ssthru_mem_tl_intg_err.4054675070 |
| Directory | /workspace/5.rom_ctrl_passthru_mem_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/5.rom_ctrl_same_csr_outstanding.248010282 |
| Short name | T461 |
| Test name | |
| Test status | |
| Simulation time | 4654869990 ps |
| CPU time | 12.77 seconds |
| Started | May 05 12:45:32 PM PDT 24 |
| Finished | May 05 12:45:45 PM PDT 24 |
| Peak memory | 210588 kb |
| Host | smart-13fcf40e-3ba7-4378-8e40-34c087b37ccf |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=248010282 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ct rl_same_csr_outstanding.248010282 |
| Directory | /workspace/5.rom_ctrl_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_errors.1996394610 |
| Short name | T394 |
| Test name | |
| Test status | |
| Simulation time | 8259309157 ps |
| CPU time | 12.42 seconds |
| Started | May 05 12:45:42 PM PDT 24 |
| Finished | May 05 12:45:55 PM PDT 24 |
| Peak memory | 218808 kb |
| Host | smart-2dcbfadf-4960-4e47-a51a-cdce9def8bd6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1996394610 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_tl_errors.1996394610 |
| Directory | /workspace/5.rom_ctrl_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_intg_err.1531106929 |
| Short name | T112 |
| Test name | |
| Test status | |
| Simulation time | 8719121434 ps |
| CPU time | 37.66 seconds |
| Started | May 05 12:45:54 PM PDT 24 |
| Finished | May 05 12:46:33 PM PDT 24 |
| Peak memory | 210536 kb |
| Host | smart-cab685aa-4b61-4903-9d16-f04a4ecfde5d |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1531106929 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_tl_in tg_err.1531106929 |
| Directory | /workspace/5.rom_ctrl_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_mem_rw_with_rand_reset.3969844757 |
| Short name | T445 |
| Test name | |
| Test status | |
| Simulation time | 432283928 ps |
| CPU time | 7.67 seconds |
| Started | May 05 12:45:45 PM PDT 24 |
| Finished | May 05 12:45:53 PM PDT 24 |
| Peak memory | 218676 kb |
| Host | smart-30595447-6d44-44ba-aaa2-a191149b741c |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3969844757 -assert nopostproc +UVM_TESTNAME =rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_csr_mem_rw_with_rand_reset.3969844757 |
| Directory | /workspace/6.rom_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_rw.2809237914 |
| Short name | T63 |
| Test name | |
| Test status | |
| Simulation time | 379450194 ps |
| CPU time | 4.26 seconds |
| Started | May 05 12:45:44 PM PDT 24 |
| Finished | May 05 12:45:49 PM PDT 24 |
| Peak memory | 210436 kb |
| Host | smart-21bdd540-e5a9-4e64-b366-979c8e502b54 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2809237914 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_csr_rw.2809237914 |
| Directory | /workspace/6.rom_ctrl_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/6.rom_ctrl_passthru_mem_tl_intg_err.576173358 |
| Short name | T98 |
| Test name | |
| Test status | |
| Simulation time | 5148245382 ps |
| CPU time | 27.18 seconds |
| Started | May 05 12:45:31 PM PDT 24 |
| Finished | May 05 12:45:59 PM PDT 24 |
| Peak memory | 210560 kb |
| Host | smart-fb1f68b0-0660-474e-9616-ba6e68df0910 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=576173358 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl _common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_pas sthru_mem_tl_intg_err.576173358 |
| Directory | /workspace/6.rom_ctrl_passthru_mem_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/6.rom_ctrl_same_csr_outstanding.3770424716 |
| Short name | T468 |
| Test name | |
| Test status | |
| Simulation time | 498165214 ps |
| CPU time | 5.98 seconds |
| Started | May 05 12:45:48 PM PDT 24 |
| Finished | May 05 12:45:54 PM PDT 24 |
| Peak memory | 210468 kb |
| Host | smart-5217730b-7860-4076-bcfb-2160190694ac |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3770424716 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_c trl_same_csr_outstanding.3770424716 |
| Directory | /workspace/6.rom_ctrl_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_errors.4185638261 |
| Short name | T411 |
| Test name | |
| Test status | |
| Simulation time | 5860269114 ps |
| CPU time | 10.07 seconds |
| Started | May 05 12:45:35 PM PDT 24 |
| Finished | May 05 12:45:46 PM PDT 24 |
| Peak memory | 218784 kb |
| Host | smart-ed21ba3f-f956-421d-ab99-aefcd1362e75 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4185638261 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_tl_errors.4185638261 |
| Directory | /workspace/6.rom_ctrl_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_intg_err.2022386519 |
| Short name | T48 |
| Test name | |
| Test status | |
| Simulation time | 8968066579 ps |
| CPU time | 77.19 seconds |
| Started | May 05 12:45:43 PM PDT 24 |
| Finished | May 05 12:47:02 PM PDT 24 |
| Peak memory | 218652 kb |
| Host | smart-2da3c443-c6a2-4616-bc88-24c730e7842b |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2022386519 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_tl_in tg_err.2022386519 |
| Directory | /workspace/6.rom_ctrl_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_mem_rw_with_rand_reset.4010856386 |
| Short name | T383 |
| Test name | |
| Test status | |
| Simulation time | 4731739877 ps |
| CPU time | 7.02 seconds |
| Started | May 05 12:45:49 PM PDT 24 |
| Finished | May 05 12:45:57 PM PDT 24 |
| Peak memory | 218716 kb |
| Host | smart-8508c148-815a-4790-bc16-9f9175596d30 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4010856386 -assert nopostproc +UVM_TESTNAME =rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_csr_mem_rw_with_rand_reset.4010856386 |
| Directory | /workspace/7.rom_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_rw.1865725916 |
| Short name | T85 |
| Test name | |
| Test status | |
| Simulation time | 1651153180 ps |
| CPU time | 13.59 seconds |
| Started | May 05 12:45:57 PM PDT 24 |
| Finished | May 05 12:46:12 PM PDT 24 |
| Peak memory | 210468 kb |
| Host | smart-baacc01f-ee8b-4294-b167-06da25d1d89e |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1865725916 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_csr_rw.1865725916 |
| Directory | /workspace/7.rom_ctrl_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/7.rom_ctrl_passthru_mem_tl_intg_err.2889229562 |
| Short name | T428 |
| Test name | |
| Test status | |
| Simulation time | 7341421486 ps |
| CPU time | 58.45 seconds |
| Started | May 05 12:45:31 PM PDT 24 |
| Finished | May 05 12:46:30 PM PDT 24 |
| Peak memory | 210564 kb |
| Host | smart-b7fcc20f-6950-4cec-8300-14bfc96c9dde |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2889229562 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_pa ssthru_mem_tl_intg_err.2889229562 |
| Directory | /workspace/7.rom_ctrl_passthru_mem_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/7.rom_ctrl_same_csr_outstanding.522749658 |
| Short name | T396 |
| Test name | |
| Test status | |
| Simulation time | 1977667447 ps |
| CPU time | 16.09 seconds |
| Started | May 05 12:46:01 PM PDT 24 |
| Finished | May 05 12:46:17 PM PDT 24 |
| Peak memory | 210488 kb |
| Host | smart-33df7384-ef25-4601-b43e-5d42e06a65dc |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=522749658 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ct rl_same_csr_outstanding.522749658 |
| Directory | /workspace/7.rom_ctrl_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_errors.2560807752 |
| Short name | T373 |
| Test name | |
| Test status | |
| Simulation time | 9392151304 ps |
| CPU time | 19.14 seconds |
| Started | May 05 12:45:37 PM PDT 24 |
| Finished | May 05 12:45:57 PM PDT 24 |
| Peak memory | 218780 kb |
| Host | smart-532a985f-2b97-42f4-a1f4-4ae466958339 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2560807752 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_tl_errors.2560807752 |
| Directory | /workspace/7.rom_ctrl_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_intg_err.3806711427 |
| Short name | T121 |
| Test name | |
| Test status | |
| Simulation time | 1013455811 ps |
| CPU time | 69.09 seconds |
| Started | May 05 12:45:48 PM PDT 24 |
| Finished | May 05 12:46:58 PM PDT 24 |
| Peak memory | 218644 kb |
| Host | smart-0d344a9c-0e33-45b7-958c-77cbcb04bea4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3806711427 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_tl_in tg_err.3806711427 |
| Directory | /workspace/7.rom_ctrl_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_mem_rw_with_rand_reset.881082797 |
| Short name | T423 |
| Test name | |
| Test status | |
| Simulation time | 408837224 ps |
| CPU time | 4.8 seconds |
| Started | May 05 12:45:48 PM PDT 24 |
| Finished | May 05 12:45:54 PM PDT 24 |
| Peak memory | 218728 kb |
| Host | smart-2e26acd6-4024-43bb-9598-1d7e7b39301b |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=881082797 -assert nopostproc +UVM_TESTNAME= rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_csr_mem_rw_with_rand_reset.881082797 |
| Directory | /workspace/8.rom_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_rw.1928225071 |
| Short name | T417 |
| Test name | |
| Test status | |
| Simulation time | 420716893 ps |
| CPU time | 6.1 seconds |
| Started | May 05 12:45:37 PM PDT 24 |
| Finished | May 05 12:45:43 PM PDT 24 |
| Peak memory | 210388 kb |
| Host | smart-05d3ce35-41d2-4c3c-8942-42129e26a576 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1928225071 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_csr_rw.1928225071 |
| Directory | /workspace/8.rom_ctrl_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/8.rom_ctrl_passthru_mem_tl_intg_err.836804094 |
| Short name | T49 |
| Test name | |
| Test status | |
| Simulation time | 9629991672 ps |
| CPU time | 55.31 seconds |
| Started | May 05 12:46:03 PM PDT 24 |
| Finished | May 05 12:46:58 PM PDT 24 |
| Peak memory | 210596 kb |
| Host | smart-8a44612d-76dd-4045-ae6f-aa0c15b48851 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=836804094 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl _common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_pas sthru_mem_tl_intg_err.836804094 |
| Directory | /workspace/8.rom_ctrl_passthru_mem_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/8.rom_ctrl_same_csr_outstanding.187895515 |
| Short name | T61 |
| Test name | |
| Test status | |
| Simulation time | 4374005767 ps |
| CPU time | 17.22 seconds |
| Started | May 05 12:45:37 PM PDT 24 |
| Finished | May 05 12:45:55 PM PDT 24 |
| Peak memory | 210464 kb |
| Host | smart-8602ec52-d705-4d6b-ae65-fc2f6be14166 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=187895515 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ct rl_same_csr_outstanding.187895515 |
| Directory | /workspace/8.rom_ctrl_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_errors.3130895250 |
| Short name | T388 |
| Test name | |
| Test status | |
| Simulation time | 5026567345 ps |
| CPU time | 15.62 seconds |
| Started | May 05 12:46:00 PM PDT 24 |
| Finished | May 05 12:46:16 PM PDT 24 |
| Peak memory | 218716 kb |
| Host | smart-3e281d16-f4bd-4a25-8073-82ce034cfcff |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3130895250 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_tl_errors.3130895250 |
| Directory | /workspace/8.rom_ctrl_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_intg_err.3369520408 |
| Short name | T118 |
| Test name | |
| Test status | |
| Simulation time | 557141638 ps |
| CPU time | 36.65 seconds |
| Started | May 05 12:45:37 PM PDT 24 |
| Finished | May 05 12:46:14 PM PDT 24 |
| Peak memory | 211500 kb |
| Host | smart-803c76c7-d8ed-4cb7-b72a-88971d1f94f3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3369520408 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_tl_in tg_err.3369520408 |
| Directory | /workspace/8.rom_ctrl_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_mem_rw_with_rand_reset.882058298 |
| Short name | T389 |
| Test name | |
| Test status | |
| Simulation time | 354076381 ps |
| CPU time | 4.52 seconds |
| Started | May 05 12:45:52 PM PDT 24 |
| Finished | May 05 12:45:58 PM PDT 24 |
| Peak memory | 212416 kb |
| Host | smart-85981d3b-d6a2-4cf5-8f5e-4adeff047723 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=882058298 -assert nopostproc +UVM_TESTNAME= rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_csr_mem_rw_with_rand_reset.882058298 |
| Directory | /workspace/9.rom_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_rw.380033090 |
| Short name | T414 |
| Test name | |
| Test status | |
| Simulation time | 3613861860 ps |
| CPU time | 9.67 seconds |
| Started | May 05 12:45:37 PM PDT 24 |
| Finished | May 05 12:45:48 PM PDT 24 |
| Peak memory | 210548 kb |
| Host | smart-88b3e384-2930-4d71-817e-f8aa7f00b2b1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=380033090 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_csr_rw.380033090 |
| Directory | /workspace/9.rom_ctrl_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/9.rom_ctrl_passthru_mem_tl_intg_err.776621221 |
| Short name | T408 |
| Test name | |
| Test status | |
| Simulation time | 28743436642 ps |
| CPU time | 57.1 seconds |
| Started | May 05 12:45:36 PM PDT 24 |
| Finished | May 05 12:46:34 PM PDT 24 |
| Peak memory | 210564 kb |
| Host | smart-df4982be-b3fa-4046-b9b5-98de114d84cd |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=776621221 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl _common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_pas sthru_mem_tl_intg_err.776621221 |
| Directory | /workspace/9.rom_ctrl_passthru_mem_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/9.rom_ctrl_same_csr_outstanding.665614487 |
| Short name | T442 |
| Test name | |
| Test status | |
| Simulation time | 1483299549 ps |
| CPU time | 6.7 seconds |
| Started | May 05 12:45:46 PM PDT 24 |
| Finished | May 05 12:45:53 PM PDT 24 |
| Peak memory | 210496 kb |
| Host | smart-0205b000-36e6-492e-96a0-8408deaff576 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=665614487 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ct rl_same_csr_outstanding.665614487 |
| Directory | /workspace/9.rom_ctrl_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_errors.2681080987 |
| Short name | T449 |
| Test name | |
| Test status | |
| Simulation time | 1910907400 ps |
| CPU time | 19.59 seconds |
| Started | May 05 12:45:37 PM PDT 24 |
| Finished | May 05 12:45:58 PM PDT 24 |
| Peak memory | 218660 kb |
| Host | smart-a5f22e16-522e-4289-b3ca-f0cb89812101 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2681080987 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_tl_errors.2681080987 |
| Directory | /workspace/9.rom_ctrl_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_intg_err.1346503121 |
| Short name | T113 |
| Test name | |
| Test status | |
| Simulation time | 569679114 ps |
| CPU time | 38.03 seconds |
| Started | May 05 12:45:53 PM PDT 24 |
| Finished | May 05 12:46:32 PM PDT 24 |
| Peak memory | 212056 kb |
| Host | smart-75e0806f-39fc-414a-a3df-917c3ed77475 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1346503121 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_tl_in tg_err.1346503121 |
| Directory | /workspace/9.rom_ctrl_tl_intg_err/latest |
| Test location | /workspace/coverage/default/0.rom_ctrl_alert_test.1123880007 |
| Short name | T168 |
| Test name | |
| Test status | |
| Simulation time | 1739989083 ps |
| CPU time | 14.24 seconds |
| Started | May 05 12:46:08 PM PDT 24 |
| Finished | May 05 12:46:23 PM PDT 24 |
| Peak memory | 211668 kb |
| Host | smart-6e22200a-6e22-425e-9423-3c2d6d94a86c |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1123880007 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_alert_test.1123880007 |
| Directory | /workspace/0.rom_ctrl_alert_test/latest |
| Test location | /workspace/coverage/default/0.rom_ctrl_corrupt_sig_fatal_chk.2124508860 |
| Short name | T313 |
| Test name | |
| Test status | |
| Simulation time | 4248499896 ps |
| CPU time | 62.8 seconds |
| Started | May 05 12:46:11 PM PDT 24 |
| Finished | May 05 12:47:15 PM PDT 24 |
| Peak memory | 220212 kb |
| Host | smart-f3b334f8-85b7-47a2-ae05-89b74b843790 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2124508860 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_c orrupt_sig_fatal_chk.2124508860 |
| Directory | /workspace/0.rom_ctrl_corrupt_sig_fatal_chk/latest |
| Test location | /workspace/coverage/default/0.rom_ctrl_kmac_err_chk.3545420755 |
| Short name | T252 |
| Test name | |
| Test status | |
| Simulation time | 4096798881 ps |
| CPU time | 14.87 seconds |
| Started | May 05 12:46:14 PM PDT 24 |
| Finished | May 05 12:46:30 PM PDT 24 |
| Peak memory | 212688 kb |
| Host | smart-e270ccf1-9137-4ad6-b827-1ee7d7ab0aac |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3545420755 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_kmac_err_chk.3545420755 |
| Directory | /workspace/0.rom_ctrl_kmac_err_chk/latest |
| Test location | /workspace/coverage/default/0.rom_ctrl_max_throughput_chk.2367671582 |
| Short name | T289 |
| Test name | |
| Test status | |
| Simulation time | 3482807909 ps |
| CPU time | 15.13 seconds |
| Started | May 05 12:46:03 PM PDT 24 |
| Finished | May 05 12:46:19 PM PDT 24 |
| Peak memory | 211636 kb |
| Host | smart-16297379-2f5c-4ac4-984c-a0ebd32de7c0 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2367671582 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_max_throughput_chk.2367671582 |
| Directory | /workspace/0.rom_ctrl_max_throughput_chk/latest |
| Test location | /workspace/coverage/default/0.rom_ctrl_sec_cm.3168003470 |
| Short name | T33 |
| Test name | |
| Test status | |
| Simulation time | 1307368989 ps |
| CPU time | 56.34 seconds |
| Started | May 05 12:45:58 PM PDT 24 |
| Finished | May 05 12:46:55 PM PDT 24 |
| Peak memory | 231124 kb |
| Host | smart-dbae4e27-931f-40c7-95c5-3b7d1b2b6ef9 |
| User | root |
| Command | /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3168003470 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_sec_cm.3168003470 |
| Directory | /workspace/0.rom_ctrl_sec_cm/latest |
| Test location | /workspace/coverage/default/0.rom_ctrl_smoke.3120809497 |
| Short name | T141 |
| Test name | |
| Test status | |
| Simulation time | 2343356314 ps |
| CPU time | 24.24 seconds |
| Started | May 05 12:45:53 PM PDT 24 |
| Finished | May 05 12:46:18 PM PDT 24 |
| Peak memory | 219960 kb |
| Host | smart-81b0ed4b-0f68-4316-9744-ee05de591f63 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3120809497 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_smoke.3120809497 |
| Directory | /workspace/0.rom_ctrl_smoke/latest |
| Test location | /workspace/coverage/default/0.rom_ctrl_stress_all.2226424169 |
| Short name | T152 |
| Test name | |
| Test status | |
| Simulation time | 2425433053 ps |
| CPU time | 13.66 seconds |
| Started | May 05 12:46:12 PM PDT 24 |
| Finished | May 05 12:46:26 PM PDT 24 |
| Peak memory | 212592 kb |
| Host | smart-31e5c4a5-45f9-4220-afc7-310db88908e3 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2226424169 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm _name 0.rom_ctrl_stress_all.2226424169 |
| Directory | /workspace/0.rom_ctrl_stress_all/latest |
| Test location | /workspace/coverage/default/1.rom_ctrl_alert_test.1048923966 |
| Short name | T172 |
| Test name | |
| Test status | |
| Simulation time | 7605831595 ps |
| CPU time | 16.6 seconds |
| Started | May 05 12:45:53 PM PDT 24 |
| Finished | May 05 12:46:11 PM PDT 24 |
| Peak memory | 211788 kb |
| Host | smart-cde04b88-8191-4326-9d21-c939a7846c45 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1048923966 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_alert_test.1048923966 |
| Directory | /workspace/1.rom_ctrl_alert_test/latest |
| Test location | /workspace/coverage/default/1.rom_ctrl_corrupt_sig_fatal_chk.3731916907 |
| Short name | T331 |
| Test name | |
| Test status | |
| Simulation time | 64037462445 ps |
| CPU time | 169.5 seconds |
| Started | May 05 12:46:11 PM PDT 24 |
| Finished | May 05 12:49:01 PM PDT 24 |
| Peak memory | 220700 kb |
| Host | smart-412c9320-b7c7-49f9-99e1-cd2a9f25e16c |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3731916907 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_c orrupt_sig_fatal_chk.3731916907 |
| Directory | /workspace/1.rom_ctrl_corrupt_sig_fatal_chk/latest |
| Test location | /workspace/coverage/default/1.rom_ctrl_kmac_err_chk.3340779921 |
| Short name | T180 |
| Test name | |
| Test status | |
| Simulation time | 9134701642 ps |
| CPU time | 23.56 seconds |
| Started | May 05 12:46:03 PM PDT 24 |
| Finished | May 05 12:46:27 PM PDT 24 |
| Peak memory | 212872 kb |
| Host | smart-8e6a64ac-74ab-4b5e-a22c-b5acbcef7341 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3340779921 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_kmac_err_chk.3340779921 |
| Directory | /workspace/1.rom_ctrl_kmac_err_chk/latest |
| Test location | /workspace/coverage/default/1.rom_ctrl_max_throughput_chk.744287463 |
| Short name | T222 |
| Test name | |
| Test status | |
| Simulation time | 1269284816 ps |
| CPU time | 7.78 seconds |
| Started | May 05 12:46:07 PM PDT 24 |
| Finished | May 05 12:46:15 PM PDT 24 |
| Peak memory | 211604 kb |
| Host | smart-fcd21f26-f061-4ae2-bab2-3d77b100a2d9 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=744287463 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_max_throughput_chk.744287463 |
| Directory | /workspace/1.rom_ctrl_max_throughput_chk/latest |
| Test location | /workspace/coverage/default/1.rom_ctrl_sec_cm.2459521922 |
| Short name | T35 |
| Test name | |
| Test status | |
| Simulation time | 1534682615 ps |
| CPU time | 112.67 seconds |
| Started | May 05 12:46:13 PM PDT 24 |
| Finished | May 05 12:48:06 PM PDT 24 |
| Peak memory | 241228 kb |
| Host | smart-35f8c082-7883-4173-a2cd-924123049c8d |
| User | root |
| Command | /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2459521922 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_sec_cm.2459521922 |
| Directory | /workspace/1.rom_ctrl_sec_cm/latest |
| Test location | /workspace/coverage/default/1.rom_ctrl_smoke.4271087446 |
| Short name | T18 |
| Test name | |
| Test status | |
| Simulation time | 2808186297 ps |
| CPU time | 27.11 seconds |
| Started | May 05 12:46:12 PM PDT 24 |
| Finished | May 05 12:46:40 PM PDT 24 |
| Peak memory | 214484 kb |
| Host | smart-9d437271-4067-4d41-97d3-c8f8d251fcaa |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4271087446 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_smoke.4271087446 |
| Directory | /workspace/1.rom_ctrl_smoke/latest |
| Test location | /workspace/coverage/default/1.rom_ctrl_stress_all.2275387644 |
| Short name | T277 |
| Test name | |
| Test status | |
| Simulation time | 8650278848 ps |
| CPU time | 42.33 seconds |
| Started | May 05 12:45:58 PM PDT 24 |
| Finished | May 05 12:46:41 PM PDT 24 |
| Peak memory | 215372 kb |
| Host | smart-88c4ee39-29e7-4145-85cc-c21fab741632 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2275387644 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm _name 1.rom_ctrl_stress_all.2275387644 |
| Directory | /workspace/1.rom_ctrl_stress_all/latest |
| Test location | /workspace/coverage/default/10.rom_ctrl_alert_test.110316155 |
| Short name | T156 |
| Test name | |
| Test status | |
| Simulation time | 6728672027 ps |
| CPU time | 13.93 seconds |
| Started | May 05 12:46:20 PM PDT 24 |
| Finished | May 05 12:46:34 PM PDT 24 |
| Peak memory | 211764 kb |
| Host | smart-04fb3b53-7c58-491c-b5d8-4f41eb819e8e |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=110316155 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_alert_test.110316155 |
| Directory | /workspace/10.rom_ctrl_alert_test/latest |
| Test location | /workspace/coverage/default/10.rom_ctrl_corrupt_sig_fatal_chk.2018022233 |
| Short name | T305 |
| Test name | |
| Test status | |
| Simulation time | 103891145821 ps |
| CPU time | 328.07 seconds |
| Started | May 05 12:46:09 PM PDT 24 |
| Finished | May 05 12:51:38 PM PDT 24 |
| Peak memory | 237492 kb |
| Host | smart-2e810007-9fc8-4e2c-80b3-da1f4a4debf0 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2018022233 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_ corrupt_sig_fatal_chk.2018022233 |
| Directory | /workspace/10.rom_ctrl_corrupt_sig_fatal_chk/latest |
| Test location | /workspace/coverage/default/10.rom_ctrl_kmac_err_chk.1235593276 |
| Short name | T164 |
| Test name | |
| Test status | |
| Simulation time | 1145627535 ps |
| CPU time | 16.59 seconds |
| Started | May 05 12:46:07 PM PDT 24 |
| Finished | May 05 12:46:24 PM PDT 24 |
| Peak memory | 212276 kb |
| Host | smart-26443f21-6ce9-4cfb-86ab-8a5f034502e5 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1235593276 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_kmac_err_chk.1235593276 |
| Directory | /workspace/10.rom_ctrl_kmac_err_chk/latest |
| Test location | /workspace/coverage/default/10.rom_ctrl_max_throughput_chk.139307553 |
| Short name | T286 |
| Test name | |
| Test status | |
| Simulation time | 2144738246 ps |
| CPU time | 11.73 seconds |
| Started | May 05 12:46:15 PM PDT 24 |
| Finished | May 05 12:46:28 PM PDT 24 |
| Peak memory | 211800 kb |
| Host | smart-b90adfe8-15d8-4be5-88ba-f1c8255badba |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=139307553 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_max_throughput_chk.139307553 |
| Directory | /workspace/10.rom_ctrl_max_throughput_chk/latest |
| Test location | /workspace/coverage/default/10.rom_ctrl_smoke.1627804638 |
| Short name | T329 |
| Test name | |
| Test status | |
| Simulation time | 6171510017 ps |
| CPU time | 36.35 seconds |
| Started | May 05 12:46:07 PM PDT 24 |
| Finished | May 05 12:46:44 PM PDT 24 |
| Peak memory | 214724 kb |
| Host | smart-29126e80-4f3f-4326-b2df-a086865ea1d6 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1627804638 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_smoke.1627804638 |
| Directory | /workspace/10.rom_ctrl_smoke/latest |
| Test location | /workspace/coverage/default/10.rom_ctrl_stress_all.1968851771 |
| Short name | T298 |
| Test name | |
| Test status | |
| Simulation time | 1772871847 ps |
| CPU time | 21.54 seconds |
| Started | May 05 12:46:14 PM PDT 24 |
| Finished | May 05 12:46:37 PM PDT 24 |
| Peak memory | 214792 kb |
| Host | smart-feffb8e0-9f00-4364-a22e-b62bee1b142f |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1968851771 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm _name 10.rom_ctrl_stress_all.1968851771 |
| Directory | /workspace/10.rom_ctrl_stress_all/latest |
| Test location | /workspace/coverage/default/11.rom_ctrl_alert_test.144694477 |
| Short name | T268 |
| Test name | |
| Test status | |
| Simulation time | 6070238877 ps |
| CPU time | 13.31 seconds |
| Started | May 05 12:46:14 PM PDT 24 |
| Finished | May 05 12:46:29 PM PDT 24 |
| Peak memory | 211744 kb |
| Host | smart-72674beb-755c-4931-9333-75b76dc5d8a5 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=144694477 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_alert_test.144694477 |
| Directory | /workspace/11.rom_ctrl_alert_test/latest |
| Test location | /workspace/coverage/default/11.rom_ctrl_kmac_err_chk.252081602 |
| Short name | T354 |
| Test name | |
| Test status | |
| Simulation time | 1542377229 ps |
| CPU time | 18.73 seconds |
| Started | May 05 12:46:14 PM PDT 24 |
| Finished | May 05 12:46:34 PM PDT 24 |
| Peak memory | 212380 kb |
| Host | smart-daeacdcf-0b20-492b-aa3e-a89fda771f7b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=252081602 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_kmac_err_chk.252081602 |
| Directory | /workspace/11.rom_ctrl_kmac_err_chk/latest |
| Test location | /workspace/coverage/default/11.rom_ctrl_max_throughput_chk.39654769 |
| Short name | T199 |
| Test name | |
| Test status | |
| Simulation time | 3001517612 ps |
| CPU time | 17.01 seconds |
| Started | May 05 12:46:15 PM PDT 24 |
| Finished | May 05 12:46:33 PM PDT 24 |
| Peak memory | 211748 kb |
| Host | smart-e9c0d97d-01af-433c-a536-780cf5a5ba26 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=39654769 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_max_throughput_chk.39654769 |
| Directory | /workspace/11.rom_ctrl_max_throughput_chk/latest |
| Test location | /workspace/coverage/default/11.rom_ctrl_smoke.2060071005 |
| Short name | T278 |
| Test name | |
| Test status | |
| Simulation time | 717668411 ps |
| CPU time | 9.86 seconds |
| Started | May 05 12:46:14 PM PDT 24 |
| Finished | May 05 12:46:25 PM PDT 24 |
| Peak memory | 213212 kb |
| Host | smart-1d8bd45b-798c-4667-9a8f-365ac7476d8b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2060071005 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_smoke.2060071005 |
| Directory | /workspace/11.rom_ctrl_smoke/latest |
| Test location | /workspace/coverage/default/11.rom_ctrl_stress_all.554077063 |
| Short name | T356 |
| Test name | |
| Test status | |
| Simulation time | 1908881544 ps |
| CPU time | 16.96 seconds |
| Started | May 05 12:46:13 PM PDT 24 |
| Finished | May 05 12:46:30 PM PDT 24 |
| Peak memory | 212064 kb |
| Host | smart-14040b99-df82-4129-9d12-c2ce62fe7657 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=554077063 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test + UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 11.rom_ctrl_stress_all.554077063 |
| Directory | /workspace/11.rom_ctrl_stress_all/latest |
| Test location | /workspace/coverage/default/12.rom_ctrl_alert_test.3744041021 |
| Short name | T190 |
| Test name | |
| Test status | |
| Simulation time | 11676360483 ps |
| CPU time | 9.17 seconds |
| Started | May 05 12:46:15 PM PDT 24 |
| Finished | May 05 12:46:26 PM PDT 24 |
| Peak memory | 211764 kb |
| Host | smart-3111225f-2574-43f5-bdeb-184e1c2fc33b |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3744041021 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_alert_test.3744041021 |
| Directory | /workspace/12.rom_ctrl_alert_test/latest |
| Test location | /workspace/coverage/default/12.rom_ctrl_corrupt_sig_fatal_chk.1739105032 |
| Short name | T194 |
| Test name | |
| Test status | |
| Simulation time | 75952133175 ps |
| CPU time | 346.39 seconds |
| Started | May 05 12:46:14 PM PDT 24 |
| Finished | May 05 12:52:01 PM PDT 24 |
| Peak memory | 231300 kb |
| Host | smart-055889eb-f955-40fa-b787-ab17df8588de |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1739105032 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_ corrupt_sig_fatal_chk.1739105032 |
| Directory | /workspace/12.rom_ctrl_corrupt_sig_fatal_chk/latest |
| Test location | /workspace/coverage/default/12.rom_ctrl_max_throughput_chk.1429287521 |
| Short name | T203 |
| Test name | |
| Test status | |
| Simulation time | 2763486753 ps |
| CPU time | 13.9 seconds |
| Started | May 05 12:46:21 PM PDT 24 |
| Finished | May 05 12:46:35 PM PDT 24 |
| Peak memory | 211720 kb |
| Host | smart-1d38fa67-fbb7-435c-90e9-f5e1674451cc |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1429287521 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_max_throughput_chk.1429287521 |
| Directory | /workspace/12.rom_ctrl_max_throughput_chk/latest |
| Test location | /workspace/coverage/default/12.rom_ctrl_smoke.3269725708 |
| Short name | T297 |
| Test name | |
| Test status | |
| Simulation time | 5342120123 ps |
| CPU time | 30.95 seconds |
| Started | May 05 12:46:15 PM PDT 24 |
| Finished | May 05 12:46:47 PM PDT 24 |
| Peak memory | 213648 kb |
| Host | smart-ce548698-3001-4611-be37-77e84174cc8f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3269725708 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_smoke.3269725708 |
| Directory | /workspace/12.rom_ctrl_smoke/latest |
| Test location | /workspace/coverage/default/12.rom_ctrl_stress_all.3271922609 |
| Short name | T308 |
| Test name | |
| Test status | |
| Simulation time | 60629122708 ps |
| CPU time | 138.21 seconds |
| Started | May 05 12:46:14 PM PDT 24 |
| Finished | May 05 12:48:33 PM PDT 24 |
| Peak memory | 219888 kb |
| Host | smart-1fa52da8-e8fd-40c7-95a7-59e84fb3cd84 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3271922609 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm _name 12.rom_ctrl_stress_all.3271922609 |
| Directory | /workspace/12.rom_ctrl_stress_all/latest |
| Test location | /workspace/coverage/default/12.rom_ctrl_stress_all_with_rand_reset.3265720407 |
| Short name | T42 |
| Test name | |
| Test status | |
| Simulation time | 23725286000 ps |
| CPU time | 919.96 seconds |
| Started | May 05 12:46:14 PM PDT 24 |
| Finished | May 05 01:01:35 PM PDT 24 |
| Peak memory | 228520 kb |
| Host | smart-f3cf1fe4-0069-47c9-830e-9d996d1c2069 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3265720407 -assert nop ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_stress_all_with_rand_reset.3265720407 |
| Directory | /workspace/12.rom_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/13.rom_ctrl_alert_test.1354425855 |
| Short name | T55 |
| Test name | |
| Test status | |
| Simulation time | 950588366 ps |
| CPU time | 7.62 seconds |
| Started | May 05 12:46:09 PM PDT 24 |
| Finished | May 05 12:46:17 PM PDT 24 |
| Peak memory | 211204 kb |
| Host | smart-82099309-da3d-4e2c-8498-fbef0f6da983 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1354425855 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_alert_test.1354425855 |
| Directory | /workspace/13.rom_ctrl_alert_test/latest |
| Test location | /workspace/coverage/default/13.rom_ctrl_corrupt_sig_fatal_chk.1791207649 |
| Short name | T340 |
| Test name | |
| Test status | |
| Simulation time | 2003807298 ps |
| CPU time | 146.67 seconds |
| Started | May 05 12:46:09 PM PDT 24 |
| Finished | May 05 12:48:37 PM PDT 24 |
| Peak memory | 234456 kb |
| Host | smart-c6715e31-3621-4ba6-a093-e3011e8fab78 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1791207649 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_ corrupt_sig_fatal_chk.1791207649 |
| Directory | /workspace/13.rom_ctrl_corrupt_sig_fatal_chk/latest |
| Test location | /workspace/coverage/default/13.rom_ctrl_kmac_err_chk.262039950 |
| Short name | T142 |
| Test name | |
| Test status | |
| Simulation time | 1888334948 ps |
| CPU time | 21.05 seconds |
| Started | May 05 12:46:16 PM PDT 24 |
| Finished | May 05 12:46:38 PM PDT 24 |
| Peak memory | 212372 kb |
| Host | smart-8c452473-139b-4269-b077-504ea1ed1247 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=262039950 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_kmac_err_chk.262039950 |
| Directory | /workspace/13.rom_ctrl_kmac_err_chk/latest |
| Test location | /workspace/coverage/default/13.rom_ctrl_max_throughput_chk.667882128 |
| Short name | T148 |
| Test name | |
| Test status | |
| Simulation time | 2531502276 ps |
| CPU time | 9.09 seconds |
| Started | May 05 12:46:15 PM PDT 24 |
| Finished | May 05 12:46:26 PM PDT 24 |
| Peak memory | 211756 kb |
| Host | smart-5e37c155-1039-4040-ad8b-dbfe6b5243b7 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=667882128 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_max_throughput_chk.667882128 |
| Directory | /workspace/13.rom_ctrl_max_throughput_chk/latest |
| Test location | /workspace/coverage/default/13.rom_ctrl_stress_all.613868473 |
| Short name | T258 |
| Test name | |
| Test status | |
| Simulation time | 5208351208 ps |
| CPU time | 47.37 seconds |
| Started | May 05 12:46:15 PM PDT 24 |
| Finished | May 05 12:47:04 PM PDT 24 |
| Peak memory | 213692 kb |
| Host | smart-b4f37923-bf57-41c1-b35f-16fc08f75937 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=613868473 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test + UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 13.rom_ctrl_stress_all.613868473 |
| Directory | /workspace/13.rom_ctrl_stress_all/latest |
| Test location | /workspace/coverage/default/14.rom_ctrl_alert_test.1346829654 |
| Short name | T196 |
| Test name | |
| Test status | |
| Simulation time | 481126834 ps |
| CPU time | 5.04 seconds |
| Started | May 05 12:46:17 PM PDT 24 |
| Finished | May 05 12:46:23 PM PDT 24 |
| Peak memory | 211644 kb |
| Host | smart-12928241-78c4-4c2f-84d3-ddc5a8c55ecf |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1346829654 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_alert_test.1346829654 |
| Directory | /workspace/14.rom_ctrl_alert_test/latest |
| Test location | /workspace/coverage/default/14.rom_ctrl_corrupt_sig_fatal_chk.628132499 |
| Short name | T208 |
| Test name | |
| Test status | |
| Simulation time | 5698206086 ps |
| CPU time | 84.83 seconds |
| Started | May 05 12:46:12 PM PDT 24 |
| Finished | May 05 12:47:37 PM PDT 24 |
| Peak memory | 220676 kb |
| Host | smart-cbe8744b-b079-4370-b079-534ccf325e96 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=628132499 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt _sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_c orrupt_sig_fatal_chk.628132499 |
| Directory | /workspace/14.rom_ctrl_corrupt_sig_fatal_chk/latest |
| Test location | /workspace/coverage/default/14.rom_ctrl_kmac_err_chk.2611909608 |
| Short name | T352 |
| Test name | |
| Test status | |
| Simulation time | 4412505982 ps |
| CPU time | 35.13 seconds |
| Started | May 05 12:46:20 PM PDT 24 |
| Finished | May 05 12:46:56 PM PDT 24 |
| Peak memory | 211856 kb |
| Host | smart-b3cc2be6-d4c2-4866-bee1-c71e650fb4fe |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2611909608 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_kmac_err_chk.2611909608 |
| Directory | /workspace/14.rom_ctrl_kmac_err_chk/latest |
| Test location | /workspace/coverage/default/14.rom_ctrl_max_throughput_chk.1892321334 |
| Short name | T295 |
| Test name | |
| Test status | |
| Simulation time | 5166402279 ps |
| CPU time | 12.48 seconds |
| Started | May 05 12:46:14 PM PDT 24 |
| Finished | May 05 12:46:28 PM PDT 24 |
| Peak memory | 211724 kb |
| Host | smart-e8d26036-dc77-4267-828a-16bcf008a88b |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1892321334 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_max_throughput_chk.1892321334 |
| Directory | /workspace/14.rom_ctrl_max_throughput_chk/latest |
| Test location | /workspace/coverage/default/14.rom_ctrl_smoke.1024446616 |
| Short name | T257 |
| Test name | |
| Test status | |
| Simulation time | 5850703312 ps |
| CPU time | 21.46 seconds |
| Started | May 05 12:46:15 PM PDT 24 |
| Finished | May 05 12:46:38 PM PDT 24 |
| Peak memory | 214188 kb |
| Host | smart-37729e88-43f4-4e85-b3b0-6d9ab4d17988 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1024446616 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_smoke.1024446616 |
| Directory | /workspace/14.rom_ctrl_smoke/latest |
| Test location | /workspace/coverage/default/14.rom_ctrl_stress_all.2839970866 |
| Short name | T351 |
| Test name | |
| Test status | |
| Simulation time | 1919166301 ps |
| CPU time | 16.02 seconds |
| Started | May 05 12:46:09 PM PDT 24 |
| Finished | May 05 12:46:25 PM PDT 24 |
| Peak memory | 215000 kb |
| Host | smart-b9f2409f-5ab8-46ac-ae83-ef9086e7454e |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2839970866 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm _name 14.rom_ctrl_stress_all.2839970866 |
| Directory | /workspace/14.rom_ctrl_stress_all/latest |
| Test location | /workspace/coverage/default/15.rom_ctrl_alert_test.60186122 |
| Short name | T136 |
| Test name | |
| Test status | |
| Simulation time | 1506252101 ps |
| CPU time | 8.95 seconds |
| Started | May 05 12:46:16 PM PDT 24 |
| Finished | May 05 12:46:26 PM PDT 24 |
| Peak memory | 211652 kb |
| Host | smart-468522e2-4706-40b5-8a16-e5a784507269 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=60186122 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_alert_test.60186122 |
| Directory | /workspace/15.rom_ctrl_alert_test/latest |
| Test location | /workspace/coverage/default/15.rom_ctrl_corrupt_sig_fatal_chk.2824647690 |
| Short name | T337 |
| Test name | |
| Test status | |
| Simulation time | 72487613136 ps |
| CPU time | 266.92 seconds |
| Started | May 05 12:46:15 PM PDT 24 |
| Finished | May 05 12:50:43 PM PDT 24 |
| Peak memory | 219028 kb |
| Host | smart-f800990d-05e5-43f5-8c5e-144d56cab361 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2824647690 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_ corrupt_sig_fatal_chk.2824647690 |
| Directory | /workspace/15.rom_ctrl_corrupt_sig_fatal_chk/latest |
| Test location | /workspace/coverage/default/15.rom_ctrl_kmac_err_chk.3352041916 |
| Short name | T285 |
| Test name | |
| Test status | |
| Simulation time | 1243751952 ps |
| CPU time | 11.3 seconds |
| Started | May 05 12:46:20 PM PDT 24 |
| Finished | May 05 12:46:32 PM PDT 24 |
| Peak memory | 212216 kb |
| Host | smart-acc30818-48cd-487f-8069-c0287ac77a84 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3352041916 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_kmac_err_chk.3352041916 |
| Directory | /workspace/15.rom_ctrl_kmac_err_chk/latest |
| Test location | /workspace/coverage/default/15.rom_ctrl_max_throughput_chk.1748651379 |
| Short name | T302 |
| Test name | |
| Test status | |
| Simulation time | 13472220553 ps |
| CPU time | 14.4 seconds |
| Started | May 05 12:46:20 PM PDT 24 |
| Finished | May 05 12:46:35 PM PDT 24 |
| Peak memory | 211672 kb |
| Host | smart-8729028d-8cd1-40bc-8424-177648adfbc3 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1748651379 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_max_throughput_chk.1748651379 |
| Directory | /workspace/15.rom_ctrl_max_throughput_chk/latest |
| Test location | /workspace/coverage/default/15.rom_ctrl_smoke.2039694078 |
| Short name | T202 |
| Test name | |
| Test status | |
| Simulation time | 702048640 ps |
| CPU time | 9.56 seconds |
| Started | May 05 12:46:23 PM PDT 24 |
| Finished | May 05 12:46:33 PM PDT 24 |
| Peak memory | 219848 kb |
| Host | smart-14a3dd01-3e8f-4133-bb62-278a42749ef7 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2039694078 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_smoke.2039694078 |
| Directory | /workspace/15.rom_ctrl_smoke/latest |
| Test location | /workspace/coverage/default/15.rom_ctrl_stress_all.1694295404 |
| Short name | T348 |
| Test name | |
| Test status | |
| Simulation time | 6836373569 ps |
| CPU time | 29.23 seconds |
| Started | May 05 12:46:14 PM PDT 24 |
| Finished | May 05 12:46:45 PM PDT 24 |
| Peak memory | 215168 kb |
| Host | smart-5a1f2f28-c76b-4a91-b4c2-1d8c298c45b4 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1694295404 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm _name 15.rom_ctrl_stress_all.1694295404 |
| Directory | /workspace/15.rom_ctrl_stress_all/latest |
| Test location | /workspace/coverage/default/16.rom_ctrl_alert_test.3693833579 |
| Short name | T53 |
| Test name | |
| Test status | |
| Simulation time | 2001544891 ps |
| CPU time | 15.25 seconds |
| Started | May 05 12:46:16 PM PDT 24 |
| Finished | May 05 12:46:33 PM PDT 24 |
| Peak memory | 211632 kb |
| Host | smart-8fe8ef98-9d4a-4607-bd58-5a6361388306 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3693833579 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_alert_test.3693833579 |
| Directory | /workspace/16.rom_ctrl_alert_test/latest |
| Test location | /workspace/coverage/default/16.rom_ctrl_corrupt_sig_fatal_chk.2638312114 |
| Short name | T365 |
| Test name | |
| Test status | |
| Simulation time | 52837624013 ps |
| CPU time | 520.15 seconds |
| Started | May 05 12:46:27 PM PDT 24 |
| Finished | May 05 12:55:08 PM PDT 24 |
| Peak memory | 228956 kb |
| Host | smart-4d8849a0-1db0-47f4-afd8-4d92bac90481 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2638312114 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_ corrupt_sig_fatal_chk.2638312114 |
| Directory | /workspace/16.rom_ctrl_corrupt_sig_fatal_chk/latest |
| Test location | /workspace/coverage/default/16.rom_ctrl_kmac_err_chk.1285249748 |
| Short name | T133 |
| Test name | |
| Test status | |
| Simulation time | 5326527997 ps |
| CPU time | 26.76 seconds |
| Started | May 05 12:46:20 PM PDT 24 |
| Finished | May 05 12:46:47 PM PDT 24 |
| Peak memory | 212524 kb |
| Host | smart-9e862ea3-977c-4aad-95c0-cd200a5be757 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1285249748 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_kmac_err_chk.1285249748 |
| Directory | /workspace/16.rom_ctrl_kmac_err_chk/latest |
| Test location | /workspace/coverage/default/16.rom_ctrl_stress_all.2200051022 |
| Short name | T234 |
| Test name | |
| Test status | |
| Simulation time | 33002813187 ps |
| CPU time | 88.06 seconds |
| Started | May 05 12:46:15 PM PDT 24 |
| Finished | May 05 12:47:44 PM PDT 24 |
| Peak memory | 219888 kb |
| Host | smart-3a076772-6050-4213-acfa-4bff83302d45 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2200051022 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm _name 16.rom_ctrl_stress_all.2200051022 |
| Directory | /workspace/16.rom_ctrl_stress_all/latest |
| Test location | /workspace/coverage/default/17.rom_ctrl_alert_test.232870765 |
| Short name | T216 |
| Test name | |
| Test status | |
| Simulation time | 1382254811 ps |
| CPU time | 12.68 seconds |
| Started | May 05 12:46:20 PM PDT 24 |
| Finished | May 05 12:46:34 PM PDT 24 |
| Peak memory | 211588 kb |
| Host | smart-a2e43b26-c399-460e-971c-3c51e72bdbcc |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=232870765 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_alert_test.232870765 |
| Directory | /workspace/17.rom_ctrl_alert_test/latest |
| Test location | /workspace/coverage/default/17.rom_ctrl_corrupt_sig_fatal_chk.3626842221 |
| Short name | T6 |
| Test name | |
| Test status | |
| Simulation time | 94595992218 ps |
| CPU time | 237.95 seconds |
| Started | May 05 12:46:22 PM PDT 24 |
| Finished | May 05 12:50:21 PM PDT 24 |
| Peak memory | 222504 kb |
| Host | smart-f8a6dcbc-14c0-4070-a739-ab4938346dd2 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3626842221 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_ corrupt_sig_fatal_chk.3626842221 |
| Directory | /workspace/17.rom_ctrl_corrupt_sig_fatal_chk/latest |
| Test location | /workspace/coverage/default/17.rom_ctrl_kmac_err_chk.3588123302 |
| Short name | T294 |
| Test name | |
| Test status | |
| Simulation time | 2855495447 ps |
| CPU time | 25.27 seconds |
| Started | May 05 12:46:16 PM PDT 24 |
| Finished | May 05 12:46:42 PM PDT 24 |
| Peak memory | 212520 kb |
| Host | smart-543c17fc-5f27-4eb7-947f-adb624fa447f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3588123302 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_kmac_err_chk.3588123302 |
| Directory | /workspace/17.rom_ctrl_kmac_err_chk/latest |
| Test location | /workspace/coverage/default/17.rom_ctrl_max_throughput_chk.3152829616 |
| Short name | T130 |
| Test name | |
| Test status | |
| Simulation time | 1615865864 ps |
| CPU time | 10.4 seconds |
| Started | May 05 12:46:16 PM PDT 24 |
| Finished | May 05 12:46:28 PM PDT 24 |
| Peak memory | 211548 kb |
| Host | smart-4533ac24-fdec-4e74-9cfd-ad38d127445f |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3152829616 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_max_throughput_chk.3152829616 |
| Directory | /workspace/17.rom_ctrl_max_throughput_chk/latest |
| Test location | /workspace/coverage/default/17.rom_ctrl_smoke.3676329650 |
| Short name | T158 |
| Test name | |
| Test status | |
| Simulation time | 33546387698 ps |
| CPU time | 31.99 seconds |
| Started | May 05 12:46:15 PM PDT 24 |
| Finished | May 05 12:46:49 PM PDT 24 |
| Peak memory | 219944 kb |
| Host | smart-764da5cb-bde8-45dd-a020-775ffe08182a |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3676329650 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_smoke.3676329650 |
| Directory | /workspace/17.rom_ctrl_smoke/latest |
| Test location | /workspace/coverage/default/17.rom_ctrl_stress_all.2766076020 |
| Short name | T246 |
| Test name | |
| Test status | |
| Simulation time | 12142769853 ps |
| CPU time | 56.38 seconds |
| Started | May 05 12:46:15 PM PDT 24 |
| Finished | May 05 12:47:13 PM PDT 24 |
| Peak memory | 219896 kb |
| Host | smart-4467eae6-fa05-49c7-a690-a410ab7230e0 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2766076020 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm _name 17.rom_ctrl_stress_all.2766076020 |
| Directory | /workspace/17.rom_ctrl_stress_all/latest |
| Test location | /workspace/coverage/default/18.rom_ctrl_alert_test.1215656282 |
| Short name | T259 |
| Test name | |
| Test status | |
| Simulation time | 3752505901 ps |
| CPU time | 14.66 seconds |
| Started | May 05 12:46:21 PM PDT 24 |
| Finished | May 05 12:46:36 PM PDT 24 |
| Peak memory | 211812 kb |
| Host | smart-cebd2101-a33e-4553-84c4-544ae5219c44 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1215656282 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_alert_test.1215656282 |
| Directory | /workspace/18.rom_ctrl_alert_test/latest |
| Test location | /workspace/coverage/default/18.rom_ctrl_corrupt_sig_fatal_chk.452604494 |
| Short name | T235 |
| Test name | |
| Test status | |
| Simulation time | 35310849988 ps |
| CPU time | 227.78 seconds |
| Started | May 05 12:46:22 PM PDT 24 |
| Finished | May 05 12:50:10 PM PDT 24 |
| Peak memory | 233424 kb |
| Host | smart-cc552388-6d79-48e1-9229-fb16c6228bca |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=452604494 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt _sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_c orrupt_sig_fatal_chk.452604494 |
| Directory | /workspace/18.rom_ctrl_corrupt_sig_fatal_chk/latest |
| Test location | /workspace/coverage/default/18.rom_ctrl_kmac_err_chk.229439632 |
| Short name | T243 |
| Test name | |
| Test status | |
| Simulation time | 3065930213 ps |
| CPU time | 27.44 seconds |
| Started | May 05 12:46:20 PM PDT 24 |
| Finished | May 05 12:46:48 PM PDT 24 |
| Peak memory | 212400 kb |
| Host | smart-a74324d5-c3c4-48e3-a925-33ac9a7710b1 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=229439632 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_kmac_err_chk.229439632 |
| Directory | /workspace/18.rom_ctrl_kmac_err_chk/latest |
| Test location | /workspace/coverage/default/18.rom_ctrl_max_throughput_chk.219963915 |
| Short name | T248 |
| Test name | |
| Test status | |
| Simulation time | 6479955453 ps |
| CPU time | 14.12 seconds |
| Started | May 05 12:46:21 PM PDT 24 |
| Finished | May 05 12:46:36 PM PDT 24 |
| Peak memory | 211760 kb |
| Host | smart-27fbc4fc-7418-40df-96b1-ad56f8b3228d |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=219963915 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_max_throughput_chk.219963915 |
| Directory | /workspace/18.rom_ctrl_max_throughput_chk/latest |
| Test location | /workspace/coverage/default/18.rom_ctrl_smoke.2132861794 |
| Short name | T143 |
| Test name | |
| Test status | |
| Simulation time | 12273866860 ps |
| CPU time | 31.45 seconds |
| Started | May 05 12:46:21 PM PDT 24 |
| Finished | May 05 12:46:53 PM PDT 24 |
| Peak memory | 214168 kb |
| Host | smart-6f9e03d8-3fa7-4b38-8d22-2c619164587b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2132861794 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_smoke.2132861794 |
| Directory | /workspace/18.rom_ctrl_smoke/latest |
| Test location | /workspace/coverage/default/18.rom_ctrl_stress_all.1549749707 |
| Short name | T71 |
| Test name | |
| Test status | |
| Simulation time | 27059748348 ps |
| CPU time | 65.4 seconds |
| Started | May 05 12:46:24 PM PDT 24 |
| Finished | May 05 12:47:30 PM PDT 24 |
| Peak memory | 219820 kb |
| Host | smart-e7f1f6a9-ef47-4ad8-bcf2-cfaede3e4d80 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1549749707 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm _name 18.rom_ctrl_stress_all.1549749707 |
| Directory | /workspace/18.rom_ctrl_stress_all/latest |
| Test location | /workspace/coverage/default/19.rom_ctrl_corrupt_sig_fatal_chk.203979152 |
| Short name | T301 |
| Test name | |
| Test status | |
| Simulation time | 34000401044 ps |
| CPU time | 110.33 seconds |
| Started | May 05 12:46:20 PM PDT 24 |
| Finished | May 05 12:48:11 PM PDT 24 |
| Peak memory | 229036 kb |
| Host | smart-e4e7bba3-384b-4ea2-8a11-e567f4059cdd |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=203979152 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt _sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_c orrupt_sig_fatal_chk.203979152 |
| Directory | /workspace/19.rom_ctrl_corrupt_sig_fatal_chk/latest |
| Test location | /workspace/coverage/default/19.rom_ctrl_kmac_err_chk.2475002929 |
| Short name | T159 |
| Test name | |
| Test status | |
| Simulation time | 7347696772 ps |
| CPU time | 32.15 seconds |
| Started | May 05 12:46:25 PM PDT 24 |
| Finished | May 05 12:46:58 PM PDT 24 |
| Peak memory | 212884 kb |
| Host | smart-1ffed8fd-135f-4571-9934-b16530b9b8a9 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2475002929 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_kmac_err_chk.2475002929 |
| Directory | /workspace/19.rom_ctrl_kmac_err_chk/latest |
| Test location | /workspace/coverage/default/19.rom_ctrl_max_throughput_chk.442269088 |
| Short name | T106 |
| Test name | |
| Test status | |
| Simulation time | 1139262233 ps |
| CPU time | 11.58 seconds |
| Started | May 05 12:46:20 PM PDT 24 |
| Finished | May 05 12:46:32 PM PDT 24 |
| Peak memory | 211652 kb |
| Host | smart-0ee148e0-b774-4289-b7da-7b12c83b059c |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=442269088 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_max_throughput_chk.442269088 |
| Directory | /workspace/19.rom_ctrl_max_throughput_chk/latest |
| Test location | /workspace/coverage/default/19.rom_ctrl_smoke.3175087826 |
| Short name | T247 |
| Test name | |
| Test status | |
| Simulation time | 15702990027 ps |
| CPU time | 40.34 seconds |
| Started | May 05 12:46:23 PM PDT 24 |
| Finished | May 05 12:47:04 PM PDT 24 |
| Peak memory | 214404 kb |
| Host | smart-b2ef38f7-a5f8-4faf-80ac-4707b245ef6e |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3175087826 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_smoke.3175087826 |
| Directory | /workspace/19.rom_ctrl_smoke/latest |
| Test location | /workspace/coverage/default/19.rom_ctrl_stress_all.1480353616 |
| Short name | T123 |
| Test name | |
| Test status | |
| Simulation time | 8148528881 ps |
| CPU time | 28.91 seconds |
| Started | May 05 12:46:21 PM PDT 24 |
| Finished | May 05 12:46:50 PM PDT 24 |
| Peak memory | 215812 kb |
| Host | smart-8d04dd32-4b2d-4720-85e1-6a5f77a5dd60 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1480353616 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm _name 19.rom_ctrl_stress_all.1480353616 |
| Directory | /workspace/19.rom_ctrl_stress_all/latest |
| Test location | /workspace/coverage/default/19.rom_ctrl_stress_all_with_rand_reset.207214509 |
| Short name | T45 |
| Test name | |
| Test status | |
| Simulation time | 62719924234 ps |
| CPU time | 2360.07 seconds |
| Started | May 05 12:46:20 PM PDT 24 |
| Finished | May 05 01:25:41 PM PDT 24 |
| Peak memory | 235176 kb |
| Host | smart-bba2ea92-7462-4f9c-9f83-3174a16f7f86 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=207214509 -assert nopo stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera ge/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_stress_all_with_rand_reset.207214509 |
| Directory | /workspace/19.rom_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/2.rom_ctrl_alert_test.2579276398 |
| Short name | T92 |
| Test name | |
| Test status | |
| Simulation time | 2146441759 ps |
| CPU time | 11.11 seconds |
| Started | May 05 12:46:03 PM PDT 24 |
| Finished | May 05 12:46:15 PM PDT 24 |
| Peak memory | 211648 kb |
| Host | smart-e4d2b400-3535-419a-9f34-b99f581d9f9b |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2579276398 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_alert_test.2579276398 |
| Directory | /workspace/2.rom_ctrl_alert_test/latest |
| Test location | /workspace/coverage/default/2.rom_ctrl_corrupt_sig_fatal_chk.2625385719 |
| Short name | T336 |
| Test name | |
| Test status | |
| Simulation time | 21592293725 ps |
| CPU time | 236.15 seconds |
| Started | May 05 12:46:07 PM PDT 24 |
| Finished | May 05 12:50:04 PM PDT 24 |
| Peak memory | 228224 kb |
| Host | smart-668009a2-6a0e-40d2-8145-97c781b28cf4 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2625385719 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_c orrupt_sig_fatal_chk.2625385719 |
| Directory | /workspace/2.rom_ctrl_corrupt_sig_fatal_chk/latest |
| Test location | /workspace/coverage/default/2.rom_ctrl_kmac_err_chk.2683513021 |
| Short name | T213 |
| Test name | |
| Test status | |
| Simulation time | 275000531 ps |
| CPU time | 10.8 seconds |
| Started | May 05 12:46:11 PM PDT 24 |
| Finished | May 05 12:46:23 PM PDT 24 |
| Peak memory | 212560 kb |
| Host | smart-43f5e097-38f7-4b95-bd4b-37aec07a3b61 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2683513021 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_kmac_err_chk.2683513021 |
| Directory | /workspace/2.rom_ctrl_kmac_err_chk/latest |
| Test location | /workspace/coverage/default/2.rom_ctrl_max_throughput_chk.1292186790 |
| Short name | T309 |
| Test name | |
| Test status | |
| Simulation time | 96659133 ps |
| CPU time | 5.58 seconds |
| Started | May 05 12:46:13 PM PDT 24 |
| Finished | May 05 12:46:19 PM PDT 24 |
| Peak memory | 211804 kb |
| Host | smart-52426e54-667f-4939-9a8c-53b5ba519023 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1292186790 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_max_throughput_chk.1292186790 |
| Directory | /workspace/2.rom_ctrl_max_throughput_chk/latest |
| Test location | /workspace/coverage/default/2.rom_ctrl_sec_cm.2774974345 |
| Short name | T5 |
| Test name | |
| Test status | |
| Simulation time | 1475572430 ps |
| CPU time | 55.68 seconds |
| Started | May 05 12:46:15 PM PDT 24 |
| Finished | May 05 12:47:12 PM PDT 24 |
| Peak memory | 230592 kb |
| Host | smart-caeac707-cb15-4b04-991e-7bfb7a0a74e2 |
| User | root |
| Command | /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2774974345 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_sec_cm.2774974345 |
| Directory | /workspace/2.rom_ctrl_sec_cm/latest |
| Test location | /workspace/coverage/default/2.rom_ctrl_smoke.1192350477 |
| Short name | T149 |
| Test name | |
| Test status | |
| Simulation time | 2977666271 ps |
| CPU time | 9.65 seconds |
| Started | May 05 12:45:59 PM PDT 24 |
| Finished | May 05 12:46:09 PM PDT 24 |
| Peak memory | 219948 kb |
| Host | smart-41c5e234-47d0-40e4-ba3b-eb26e9a66887 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1192350477 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_smoke.1192350477 |
| Directory | /workspace/2.rom_ctrl_smoke/latest |
| Test location | /workspace/coverage/default/2.rom_ctrl_stress_all.540834084 |
| Short name | T161 |
| Test name | |
| Test status | |
| Simulation time | 3024534026 ps |
| CPU time | 20.6 seconds |
| Started | May 05 12:46:08 PM PDT 24 |
| Finished | May 05 12:46:30 PM PDT 24 |
| Peak memory | 219916 kb |
| Host | smart-34c51ffc-a0c2-4e1b-aecf-0a57b8df1101 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=540834084 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test + UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 2.rom_ctrl_stress_all.540834084 |
| Directory | /workspace/2.rom_ctrl_stress_all/latest |
| Test location | /workspace/coverage/default/20.rom_ctrl_alert_test.3097546223 |
| Short name | T265 |
| Test name | |
| Test status | |
| Simulation time | 4288227107 ps |
| CPU time | 16.59 seconds |
| Started | May 05 12:46:26 PM PDT 24 |
| Finished | May 05 12:46:44 PM PDT 24 |
| Peak memory | 211716 kb |
| Host | smart-352097a2-da48-4a2f-a900-e6d92e41abed |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3097546223 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_alert_test.3097546223 |
| Directory | /workspace/20.rom_ctrl_alert_test/latest |
| Test location | /workspace/coverage/default/20.rom_ctrl_corrupt_sig_fatal_chk.475728003 |
| Short name | T37 |
| Test name | |
| Test status | |
| Simulation time | 10378279724 ps |
| CPU time | 161.11 seconds |
| Started | May 05 12:46:28 PM PDT 24 |
| Finished | May 05 12:49:10 PM PDT 24 |
| Peak memory | 214060 kb |
| Host | smart-be5d080b-1add-4836-9ad0-57d5d661b761 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=475728003 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt _sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_c orrupt_sig_fatal_chk.475728003 |
| Directory | /workspace/20.rom_ctrl_corrupt_sig_fatal_chk/latest |
| Test location | /workspace/coverage/default/20.rom_ctrl_max_throughput_chk.926598339 |
| Short name | T122 |
| Test name | |
| Test status | |
| Simulation time | 2964182147 ps |
| CPU time | 9.78 seconds |
| Started | May 05 12:46:33 PM PDT 24 |
| Finished | May 05 12:46:43 PM PDT 24 |
| Peak memory | 211716 kb |
| Host | smart-178e8d6c-8ef9-4953-b3bc-f5ae9b6099f6 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=926598339 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_max_throughput_chk.926598339 |
| Directory | /workspace/20.rom_ctrl_max_throughput_chk/latest |
| Test location | /workspace/coverage/default/20.rom_ctrl_smoke.2098701551 |
| Short name | T249 |
| Test name | |
| Test status | |
| Simulation time | 265581917 ps |
| CPU time | 10.37 seconds |
| Started | May 05 12:46:25 PM PDT 24 |
| Finished | May 05 12:46:36 PM PDT 24 |
| Peak memory | 214132 kb |
| Host | smart-482d4c18-a65d-4897-ae6b-2b2d318a3b81 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2098701551 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_smoke.2098701551 |
| Directory | /workspace/20.rom_ctrl_smoke/latest |
| Test location | /workspace/coverage/default/20.rom_ctrl_stress_all.1616584564 |
| Short name | T187 |
| Test name | |
| Test status | |
| Simulation time | 16062183600 ps |
| CPU time | 34.28 seconds |
| Started | May 05 12:46:26 PM PDT 24 |
| Finished | May 05 12:47:01 PM PDT 24 |
| Peak memory | 215496 kb |
| Host | smart-97a4c9e2-3c95-4ee9-bc4c-88305d8217ae |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1616584564 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm _name 20.rom_ctrl_stress_all.1616584564 |
| Directory | /workspace/20.rom_ctrl_stress_all/latest |
| Test location | /workspace/coverage/default/21.rom_ctrl_alert_test.4113794986 |
| Short name | T251 |
| Test name | |
| Test status | |
| Simulation time | 3364191720 ps |
| CPU time | 10.12 seconds |
| Started | May 05 12:46:27 PM PDT 24 |
| Finished | May 05 12:46:38 PM PDT 24 |
| Peak memory | 211788 kb |
| Host | smart-763cdfee-bd9c-42b6-b2d8-a76dcef0927f |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4113794986 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_alert_test.4113794986 |
| Directory | /workspace/21.rom_ctrl_alert_test/latest |
| Test location | /workspace/coverage/default/21.rom_ctrl_corrupt_sig_fatal_chk.1276778601 |
| Short name | T290 |
| Test name | |
| Test status | |
| Simulation time | 21768379695 ps |
| CPU time | 213.39 seconds |
| Started | May 05 12:46:27 PM PDT 24 |
| Finished | May 05 12:50:01 PM PDT 24 |
| Peak memory | 245056 kb |
| Host | smart-669f9269-447a-445a-a7bb-9a5006d6fb03 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1276778601 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_ corrupt_sig_fatal_chk.1276778601 |
| Directory | /workspace/21.rom_ctrl_corrupt_sig_fatal_chk/latest |
| Test location | /workspace/coverage/default/21.rom_ctrl_kmac_err_chk.2054473183 |
| Short name | T293 |
| Test name | |
| Test status | |
| Simulation time | 11658489553 ps |
| CPU time | 19.34 seconds |
| Started | May 05 12:46:32 PM PDT 24 |
| Finished | May 05 12:46:52 PM PDT 24 |
| Peak memory | 218480 kb |
| Host | smart-2810070d-e9ce-417a-b476-caa79a34b2bc |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2054473183 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_kmac_err_chk.2054473183 |
| Directory | /workspace/21.rom_ctrl_kmac_err_chk/latest |
| Test location | /workspace/coverage/default/21.rom_ctrl_max_throughput_chk.2314367770 |
| Short name | T165 |
| Test name | |
| Test status | |
| Simulation time | 8285918827 ps |
| CPU time | 10.32 seconds |
| Started | May 05 12:46:26 PM PDT 24 |
| Finished | May 05 12:46:37 PM PDT 24 |
| Peak memory | 211728 kb |
| Host | smart-3e72299b-40ea-4853-a424-57671edfdae3 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2314367770 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_max_throughput_chk.2314367770 |
| Directory | /workspace/21.rom_ctrl_max_throughput_chk/latest |
| Test location | /workspace/coverage/default/21.rom_ctrl_smoke.1859218047 |
| Short name | T17 |
| Test name | |
| Test status | |
| Simulation time | 183559155 ps |
| CPU time | 9.71 seconds |
| Started | May 05 12:46:27 PM PDT 24 |
| Finished | May 05 12:46:37 PM PDT 24 |
| Peak memory | 212996 kb |
| Host | smart-a6d2d823-3306-43e6-884a-33c8fa0877af |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1859218047 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_smoke.1859218047 |
| Directory | /workspace/21.rom_ctrl_smoke/latest |
| Test location | /workspace/coverage/default/21.rom_ctrl_stress_all.3879833983 |
| Short name | T328 |
| Test name | |
| Test status | |
| Simulation time | 2409178828 ps |
| CPU time | 24.63 seconds |
| Started | May 05 12:46:28 PM PDT 24 |
| Finished | May 05 12:46:53 PM PDT 24 |
| Peak memory | 219912 kb |
| Host | smart-c584862c-7fba-41b4-9c8b-781a644dd896 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3879833983 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm _name 21.rom_ctrl_stress_all.3879833983 |
| Directory | /workspace/21.rom_ctrl_stress_all/latest |
| Test location | /workspace/coverage/default/22.rom_ctrl_alert_test.1770651335 |
| Short name | T197 |
| Test name | |
| Test status | |
| Simulation time | 333976929 ps |
| CPU time | 4.19 seconds |
| Started | May 05 12:46:34 PM PDT 24 |
| Finished | May 05 12:46:39 PM PDT 24 |
| Peak memory | 211644 kb |
| Host | smart-8441145a-2cfb-44fc-a99d-38d9da7ffd84 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1770651335 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_alert_test.1770651335 |
| Directory | /workspace/22.rom_ctrl_alert_test/latest |
| Test location | /workspace/coverage/default/22.rom_ctrl_corrupt_sig_fatal_chk.233723740 |
| Short name | T287 |
| Test name | |
| Test status | |
| Simulation time | 551399394843 ps |
| CPU time | 395.49 seconds |
| Started | May 05 12:46:27 PM PDT 24 |
| Finished | May 05 12:53:04 PM PDT 24 |
| Peak memory | 213060 kb |
| Host | smart-0bc75df8-1101-4d3a-a363-dbc954b880a3 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=233723740 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt _sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_c orrupt_sig_fatal_chk.233723740 |
| Directory | /workspace/22.rom_ctrl_corrupt_sig_fatal_chk/latest |
| Test location | /workspace/coverage/default/22.rom_ctrl_kmac_err_chk.69557780 |
| Short name | T215 |
| Test name | |
| Test status | |
| Simulation time | 16304211537 ps |
| CPU time | 31.62 seconds |
| Started | May 05 12:46:29 PM PDT 24 |
| Finished | May 05 12:47:01 PM PDT 24 |
| Peak memory | 211840 kb |
| Host | smart-5c1ac702-ddb8-4426-8763-7941d88a5ef5 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=69557780 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_kmac_err_chk.69557780 |
| Directory | /workspace/22.rom_ctrl_kmac_err_chk/latest |
| Test location | /workspace/coverage/default/22.rom_ctrl_max_throughput_chk.1103957015 |
| Short name | T304 |
| Test name | |
| Test status | |
| Simulation time | 386663301 ps |
| CPU time | 5.32 seconds |
| Started | May 05 12:46:27 PM PDT 24 |
| Finished | May 05 12:46:33 PM PDT 24 |
| Peak memory | 211608 kb |
| Host | smart-b96e0f7c-ae66-464e-a29e-9f967ef13938 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1103957015 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_max_throughput_chk.1103957015 |
| Directory | /workspace/22.rom_ctrl_max_throughput_chk/latest |
| Test location | /workspace/coverage/default/22.rom_ctrl_smoke.1775942326 |
| Short name | T260 |
| Test name | |
| Test status | |
| Simulation time | 10361570966 ps |
| CPU time | 18.08 seconds |
| Started | May 05 12:46:27 PM PDT 24 |
| Finished | May 05 12:46:46 PM PDT 24 |
| Peak memory | 214312 kb |
| Host | smart-24c9ad60-3812-4319-8782-0899e7176e30 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1775942326 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_smoke.1775942326 |
| Directory | /workspace/22.rom_ctrl_smoke/latest |
| Test location | /workspace/coverage/default/22.rom_ctrl_stress_all.2998681164 |
| Short name | T167 |
| Test name | |
| Test status | |
| Simulation time | 17079940759 ps |
| CPU time | 43.99 seconds |
| Started | May 05 12:46:32 PM PDT 24 |
| Finished | May 05 12:47:17 PM PDT 24 |
| Peak memory | 219912 kb |
| Host | smart-e360e94e-4a8f-40f8-821d-1bff41285c6f |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2998681164 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm _name 22.rom_ctrl_stress_all.2998681164 |
| Directory | /workspace/22.rom_ctrl_stress_all/latest |
| Test location | /workspace/coverage/default/22.rom_ctrl_stress_all_with_rand_reset.1698601948 |
| Short name | T322 |
| Test name | |
| Test status | |
| Simulation time | 232686898108 ps |
| CPU time | 2266.64 seconds |
| Started | May 05 12:46:37 PM PDT 24 |
| Finished | May 05 01:24:24 PM PDT 24 |
| Peak memory | 239184 kb |
| Host | smart-67c20666-3972-4f43-9a7c-d05bf1b611ea |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1698601948 -assert nop ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_stress_all_with_rand_reset.1698601948 |
| Directory | /workspace/22.rom_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/23.rom_ctrl_alert_test.2432118308 |
| Short name | T324 |
| Test name | |
| Test status | |
| Simulation time | 4613209154 ps |
| CPU time | 10.87 seconds |
| Started | May 05 12:46:34 PM PDT 24 |
| Finished | May 05 12:46:45 PM PDT 24 |
| Peak memory | 211748 kb |
| Host | smart-a3c0cca9-997a-42f0-bede-3ddeee2fed57 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2432118308 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_alert_test.2432118308 |
| Directory | /workspace/23.rom_ctrl_alert_test/latest |
| Test location | /workspace/coverage/default/23.rom_ctrl_corrupt_sig_fatal_chk.4076237391 |
| Short name | T212 |
| Test name | |
| Test status | |
| Simulation time | 3949205300 ps |
| CPU time | 65.37 seconds |
| Started | May 05 12:46:33 PM PDT 24 |
| Finished | May 05 12:47:39 PM PDT 24 |
| Peak memory | 237336 kb |
| Host | smart-70bcbf96-29e9-4703-bdf1-22262139eaab |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4076237391 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_ corrupt_sig_fatal_chk.4076237391 |
| Directory | /workspace/23.rom_ctrl_corrupt_sig_fatal_chk/latest |
| Test location | /workspace/coverage/default/23.rom_ctrl_kmac_err_chk.599360543 |
| Short name | T226 |
| Test name | |
| Test status | |
| Simulation time | 2591681104 ps |
| CPU time | 25.14 seconds |
| Started | May 05 12:46:33 PM PDT 24 |
| Finished | May 05 12:46:59 PM PDT 24 |
| Peak memory | 212276 kb |
| Host | smart-a9ba94af-b74f-4654-95b9-bb916ad84810 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=599360543 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_kmac_err_chk.599360543 |
| Directory | /workspace/23.rom_ctrl_kmac_err_chk/latest |
| Test location | /workspace/coverage/default/23.rom_ctrl_max_throughput_chk.1352928240 |
| Short name | T347 |
| Test name | |
| Test status | |
| Simulation time | 343902626 ps |
| CPU time | 7.67 seconds |
| Started | May 05 12:46:33 PM PDT 24 |
| Finished | May 05 12:46:41 PM PDT 24 |
| Peak memory | 211520 kb |
| Host | smart-b0f41840-dfd8-4580-acc4-6a2604be2c87 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1352928240 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_max_throughput_chk.1352928240 |
| Directory | /workspace/23.rom_ctrl_max_throughput_chk/latest |
| Test location | /workspace/coverage/default/23.rom_ctrl_smoke.2648587529 |
| Short name | T264 |
| Test name | |
| Test status | |
| Simulation time | 2521983985 ps |
| CPU time | 26.12 seconds |
| Started | May 05 12:46:31 PM PDT 24 |
| Finished | May 05 12:46:58 PM PDT 24 |
| Peak memory | 220024 kb |
| Host | smart-008be941-028a-4302-ab91-f29fb4c6c855 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2648587529 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_smoke.2648587529 |
| Directory | /workspace/23.rom_ctrl_smoke/latest |
| Test location | /workspace/coverage/default/23.rom_ctrl_stress_all.3371894960 |
| Short name | T253 |
| Test name | |
| Test status | |
| Simulation time | 3727166447 ps |
| CPU time | 23.31 seconds |
| Started | May 05 12:46:35 PM PDT 24 |
| Finished | May 05 12:46:59 PM PDT 24 |
| Peak memory | 213220 kb |
| Host | smart-21d139df-7d12-4e30-bbc2-7fc8474a46f6 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3371894960 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm _name 23.rom_ctrl_stress_all.3371894960 |
| Directory | /workspace/23.rom_ctrl_stress_all/latest |
| Test location | /workspace/coverage/default/23.rom_ctrl_stress_all_with_rand_reset.3992826286 |
| Short name | T335 |
| Test name | |
| Test status | |
| Simulation time | 54010882065 ps |
| CPU time | 2099.08 seconds |
| Started | May 05 12:46:35 PM PDT 24 |
| Finished | May 05 01:21:35 PM PDT 24 |
| Peak memory | 237044 kb |
| Host | smart-77d2737f-33b4-4056-bd7a-031dd7a66415 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3992826286 -assert nop ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_stress_all_with_rand_reset.3992826286 |
| Directory | /workspace/23.rom_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/24.rom_ctrl_alert_test.218705511 |
| Short name | T200 |
| Test name | |
| Test status | |
| Simulation time | 856766847 ps |
| CPU time | 9.33 seconds |
| Started | May 05 12:46:39 PM PDT 24 |
| Finished | May 05 12:46:49 PM PDT 24 |
| Peak memory | 211672 kb |
| Host | smart-357420ff-d8a8-4108-b4b3-6555c701ff1d |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=218705511 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_alert_test.218705511 |
| Directory | /workspace/24.rom_ctrl_alert_test/latest |
| Test location | /workspace/coverage/default/24.rom_ctrl_corrupt_sig_fatal_chk.870332833 |
| Short name | T155 |
| Test name | |
| Test status | |
| Simulation time | 2916091975 ps |
| CPU time | 83.54 seconds |
| Started | May 05 12:46:33 PM PDT 24 |
| Finished | May 05 12:47:58 PM PDT 24 |
| Peak memory | 212016 kb |
| Host | smart-b9a2b382-0a56-4fa6-926d-2675b2670670 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=870332833 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt _sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_c orrupt_sig_fatal_chk.870332833 |
| Directory | /workspace/24.rom_ctrl_corrupt_sig_fatal_chk/latest |
| Test location | /workspace/coverage/default/24.rom_ctrl_kmac_err_chk.1649386316 |
| Short name | T134 |
| Test name | |
| Test status | |
| Simulation time | 5331533345 ps |
| CPU time | 15.36 seconds |
| Started | May 05 12:46:31 PM PDT 24 |
| Finished | May 05 12:46:47 PM PDT 24 |
| Peak memory | 213044 kb |
| Host | smart-25b9502d-c221-4d24-a80c-c88e98fd9171 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1649386316 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_kmac_err_chk.1649386316 |
| Directory | /workspace/24.rom_ctrl_kmac_err_chk/latest |
| Test location | /workspace/coverage/default/24.rom_ctrl_max_throughput_chk.2651395493 |
| Short name | T94 |
| Test name | |
| Test status | |
| Simulation time | 2024943156 ps |
| CPU time | 17.11 seconds |
| Started | May 05 12:46:35 PM PDT 24 |
| Finished | May 05 12:46:53 PM PDT 24 |
| Peak memory | 211512 kb |
| Host | smart-bada626c-ec1d-4fc6-b032-7ebf51262126 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2651395493 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_max_throughput_chk.2651395493 |
| Directory | /workspace/24.rom_ctrl_max_throughput_chk/latest |
| Test location | /workspace/coverage/default/24.rom_ctrl_smoke.4286317702 |
| Short name | T11 |
| Test name | |
| Test status | |
| Simulation time | 9239101437 ps |
| CPU time | 24.44 seconds |
| Started | May 05 12:46:33 PM PDT 24 |
| Finished | May 05 12:46:58 PM PDT 24 |
| Peak memory | 219904 kb |
| Host | smart-d90d02da-6f52-4010-94ef-2b29ac21c003 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4286317702 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_smoke.4286317702 |
| Directory | /workspace/24.rom_ctrl_smoke/latest |
| Test location | /workspace/coverage/default/24.rom_ctrl_stress_all.3814772253 |
| Short name | T319 |
| Test name | |
| Test status | |
| Simulation time | 4194369580 ps |
| CPU time | 17.76 seconds |
| Started | May 05 12:46:33 PM PDT 24 |
| Finished | May 05 12:46:52 PM PDT 24 |
| Peak memory | 211700 kb |
| Host | smart-2957caa6-152e-48cb-af92-579a8f5b21e3 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3814772253 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm _name 24.rom_ctrl_stress_all.3814772253 |
| Directory | /workspace/24.rom_ctrl_stress_all/latest |
| Test location | /workspace/coverage/default/24.rom_ctrl_stress_all_with_rand_reset.2234058395 |
| Short name | T43 |
| Test name | |
| Test status | |
| Simulation time | 76544516492 ps |
| CPU time | 1581.71 seconds |
| Started | May 05 12:46:34 PM PDT 24 |
| Finished | May 05 01:12:56 PM PDT 24 |
| Peak memory | 238124 kb |
| Host | smart-0023cabc-f42e-4181-ad93-38c86a6ee1a5 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2234058395 -assert nop ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_stress_all_with_rand_reset.2234058395 |
| Directory | /workspace/24.rom_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/25.rom_ctrl_alert_test.2072840755 |
| Short name | T162 |
| Test name | |
| Test status | |
| Simulation time | 1332836202 ps |
| CPU time | 12.57 seconds |
| Started | May 05 12:46:33 PM PDT 24 |
| Finished | May 05 12:46:47 PM PDT 24 |
| Peak memory | 211628 kb |
| Host | smart-0b34b35f-a737-45e8-8c7d-0030e3946542 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2072840755 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_alert_test.2072840755 |
| Directory | /workspace/25.rom_ctrl_alert_test/latest |
| Test location | /workspace/coverage/default/25.rom_ctrl_corrupt_sig_fatal_chk.977683439 |
| Short name | T39 |
| Test name | |
| Test status | |
| Simulation time | 5469396118 ps |
| CPU time | 130.24 seconds |
| Started | May 05 12:46:33 PM PDT 24 |
| Finished | May 05 12:48:44 PM PDT 24 |
| Peak memory | 229116 kb |
| Host | smart-01fa4a94-887e-4d9d-beb2-ddf1c83cc8be |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=977683439 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt _sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_c orrupt_sig_fatal_chk.977683439 |
| Directory | /workspace/25.rom_ctrl_corrupt_sig_fatal_chk/latest |
| Test location | /workspace/coverage/default/25.rom_ctrl_kmac_err_chk.624777068 |
| Short name | T31 |
| Test name | |
| Test status | |
| Simulation time | 3347964630 ps |
| CPU time | 28.88 seconds |
| Started | May 05 12:46:37 PM PDT 24 |
| Finished | May 05 12:47:06 PM PDT 24 |
| Peak memory | 212424 kb |
| Host | smart-35e36dab-1780-4e1e-ae63-67506bbfe07f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=624777068 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_kmac_err_chk.624777068 |
| Directory | /workspace/25.rom_ctrl_kmac_err_chk/latest |
| Test location | /workspace/coverage/default/25.rom_ctrl_max_throughput_chk.3302703185 |
| Short name | T145 |
| Test name | |
| Test status | |
| Simulation time | 6333717955 ps |
| CPU time | 13.78 seconds |
| Started | May 05 12:46:35 PM PDT 24 |
| Finished | May 05 12:46:49 PM PDT 24 |
| Peak memory | 211668 kb |
| Host | smart-b4f7ec79-8cef-46f8-acdc-04673e828186 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3302703185 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_max_throughput_chk.3302703185 |
| Directory | /workspace/25.rom_ctrl_max_throughput_chk/latest |
| Test location | /workspace/coverage/default/25.rom_ctrl_smoke.2564310354 |
| Short name | T16 |
| Test name | |
| Test status | |
| Simulation time | 3436877591 ps |
| CPU time | 28.44 seconds |
| Started | May 05 12:46:37 PM PDT 24 |
| Finished | May 05 12:47:06 PM PDT 24 |
| Peak memory | 213680 kb |
| Host | smart-a4ef6479-b30b-4118-b3ba-4842f0c9192c |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2564310354 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_smoke.2564310354 |
| Directory | /workspace/25.rom_ctrl_smoke/latest |
| Test location | /workspace/coverage/default/25.rom_ctrl_stress_all.184158328 |
| Short name | T72 |
| Test name | |
| Test status | |
| Simulation time | 2092702449 ps |
| CPU time | 15.51 seconds |
| Started | May 05 12:46:31 PM PDT 24 |
| Finished | May 05 12:46:48 PM PDT 24 |
| Peak memory | 214612 kb |
| Host | smart-807aea54-7ca0-44eb-9c2c-ea4a127d98d7 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=184158328 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test + UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 25.rom_ctrl_stress_all.184158328 |
| Directory | /workspace/25.rom_ctrl_stress_all/latest |
| Test location | /workspace/coverage/default/26.rom_ctrl_alert_test.3470560151 |
| Short name | T349 |
| Test name | |
| Test status | |
| Simulation time | 1709868030 ps |
| CPU time | 7.02 seconds |
| Started | May 05 12:46:38 PM PDT 24 |
| Finished | May 05 12:46:46 PM PDT 24 |
| Peak memory | 211644 kb |
| Host | smart-51833016-6a35-4dce-a878-816cda06dadb |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3470560151 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_alert_test.3470560151 |
| Directory | /workspace/26.rom_ctrl_alert_test/latest |
| Test location | /workspace/coverage/default/26.rom_ctrl_corrupt_sig_fatal_chk.710614188 |
| Short name | T366 |
| Test name | |
| Test status | |
| Simulation time | 24968034492 ps |
| CPU time | 209.77 seconds |
| Started | May 05 12:46:39 PM PDT 24 |
| Finished | May 05 12:50:09 PM PDT 24 |
| Peak memory | 229624 kb |
| Host | smart-3b8fcf18-5ee1-446b-8b4b-1eb421d1d464 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=710614188 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt _sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_c orrupt_sig_fatal_chk.710614188 |
| Directory | /workspace/26.rom_ctrl_corrupt_sig_fatal_chk/latest |
| Test location | /workspace/coverage/default/26.rom_ctrl_kmac_err_chk.3963807475 |
| Short name | T174 |
| Test name | |
| Test status | |
| Simulation time | 664900320 ps |
| CPU time | 14.25 seconds |
| Started | May 05 12:46:35 PM PDT 24 |
| Finished | May 05 12:46:49 PM PDT 24 |
| Peak memory | 212288 kb |
| Host | smart-78972621-0b08-4c6f-8738-c01d9e6dccb6 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3963807475 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_kmac_err_chk.3963807475 |
| Directory | /workspace/26.rom_ctrl_kmac_err_chk/latest |
| Test location | /workspace/coverage/default/26.rom_ctrl_max_throughput_chk.1929141692 |
| Short name | T137 |
| Test name | |
| Test status | |
| Simulation time | 13319286006 ps |
| CPU time | 12.54 seconds |
| Started | May 05 12:46:32 PM PDT 24 |
| Finished | May 05 12:46:46 PM PDT 24 |
| Peak memory | 211728 kb |
| Host | smart-66fe3bf1-38fd-44db-b236-893be5639baf |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1929141692 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_max_throughput_chk.1929141692 |
| Directory | /workspace/26.rom_ctrl_max_throughput_chk/latest |
| Test location | /workspace/coverage/default/26.rom_ctrl_smoke.2487178273 |
| Short name | T13 |
| Test name | |
| Test status | |
| Simulation time | 5738658076 ps |
| CPU time | 16.86 seconds |
| Started | May 05 12:46:35 PM PDT 24 |
| Finished | May 05 12:46:52 PM PDT 24 |
| Peak memory | 219288 kb |
| Host | smart-a0b880ba-dc3d-4dce-b04c-d01f5982fa75 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2487178273 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_smoke.2487178273 |
| Directory | /workspace/26.rom_ctrl_smoke/latest |
| Test location | /workspace/coverage/default/26.rom_ctrl_stress_all.4292196947 |
| Short name | T231 |
| Test name | |
| Test status | |
| Simulation time | 8673948357 ps |
| CPU time | 35.99 seconds |
| Started | May 05 12:46:31 PM PDT 24 |
| Finished | May 05 12:47:07 PM PDT 24 |
| Peak memory | 214088 kb |
| Host | smart-f00a7926-316b-4ce9-ae86-77e797501bae |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4292196947 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm _name 26.rom_ctrl_stress_all.4292196947 |
| Directory | /workspace/26.rom_ctrl_stress_all/latest |
| Test location | /workspace/coverage/default/27.rom_ctrl_alert_test.1524989254 |
| Short name | T346 |
| Test name | |
| Test status | |
| Simulation time | 344269788 ps |
| CPU time | 6.45 seconds |
| Started | May 05 12:46:47 PM PDT 24 |
| Finished | May 05 12:46:54 PM PDT 24 |
| Peak memory | 211620 kb |
| Host | smart-522ad44d-6bd1-47de-8910-b37eeb974020 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1524989254 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_alert_test.1524989254 |
| Directory | /workspace/27.rom_ctrl_alert_test/latest |
| Test location | /workspace/coverage/default/27.rom_ctrl_corrupt_sig_fatal_chk.3484030804 |
| Short name | T198 |
| Test name | |
| Test status | |
| Simulation time | 14270169729 ps |
| CPU time | 172.39 seconds |
| Started | May 05 12:46:37 PM PDT 24 |
| Finished | May 05 12:49:29 PM PDT 24 |
| Peak memory | 237748 kb |
| Host | smart-c8441f34-5902-48a1-a51a-97612e3bee52 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3484030804 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_ corrupt_sig_fatal_chk.3484030804 |
| Directory | /workspace/27.rom_ctrl_corrupt_sig_fatal_chk/latest |
| Test location | /workspace/coverage/default/27.rom_ctrl_kmac_err_chk.1640029644 |
| Short name | T266 |
| Test name | |
| Test status | |
| Simulation time | 8173043804 ps |
| CPU time | 18.37 seconds |
| Started | May 05 12:46:38 PM PDT 24 |
| Finished | May 05 12:46:57 PM PDT 24 |
| Peak memory | 213288 kb |
| Host | smart-164a6d3d-1233-48d9-a729-6938b79017e7 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1640029644 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_kmac_err_chk.1640029644 |
| Directory | /workspace/27.rom_ctrl_kmac_err_chk/latest |
| Test location | /workspace/coverage/default/27.rom_ctrl_max_throughput_chk.793217469 |
| Short name | T271 |
| Test name | |
| Test status | |
| Simulation time | 8924294798 ps |
| CPU time | 16.78 seconds |
| Started | May 05 12:46:38 PM PDT 24 |
| Finished | May 05 12:46:55 PM PDT 24 |
| Peak memory | 211740 kb |
| Host | smart-b039aed6-d377-4ffb-80f3-3b4b8bf602eb |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=793217469 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_max_throughput_chk.793217469 |
| Directory | /workspace/27.rom_ctrl_max_throughput_chk/latest |
| Test location | /workspace/coverage/default/27.rom_ctrl_smoke.790801546 |
| Short name | T186 |
| Test name | |
| Test status | |
| Simulation time | 3393860035 ps |
| CPU time | 33.54 seconds |
| Started | May 05 12:46:39 PM PDT 24 |
| Finished | May 05 12:47:13 PM PDT 24 |
| Peak memory | 213908 kb |
| Host | smart-71381dd1-c907-4dd6-8c55-359a85fe1f80 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=790801546 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_smoke.790801546 |
| Directory | /workspace/27.rom_ctrl_smoke/latest |
| Test location | /workspace/coverage/default/27.rom_ctrl_stress_all.1866695463 |
| Short name | T185 |
| Test name | |
| Test status | |
| Simulation time | 196130756 ps |
| CPU time | 13.36 seconds |
| Started | May 05 12:46:40 PM PDT 24 |
| Finished | May 05 12:46:54 PM PDT 24 |
| Peak memory | 214236 kb |
| Host | smart-fd597740-4f43-452c-bae9-cc496a4bfaa3 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1866695463 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm _name 27.rom_ctrl_stress_all.1866695463 |
| Directory | /workspace/27.rom_ctrl_stress_all/latest |
| Test location | /workspace/coverage/default/28.rom_ctrl_alert_test.1908202611 |
| Short name | T300 |
| Test name | |
| Test status | |
| Simulation time | 15764889859 ps |
| CPU time | 10.82 seconds |
| Started | May 05 12:46:38 PM PDT 24 |
| Finished | May 05 12:46:49 PM PDT 24 |
| Peak memory | 211780 kb |
| Host | smart-7629d483-e679-4366-97ca-e088bd6bbb55 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1908202611 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_alert_test.1908202611 |
| Directory | /workspace/28.rom_ctrl_alert_test/latest |
| Test location | /workspace/coverage/default/28.rom_ctrl_kmac_err_chk.3306532516 |
| Short name | T323 |
| Test name | |
| Test status | |
| Simulation time | 7800239480 ps |
| CPU time | 31.93 seconds |
| Started | May 05 12:46:39 PM PDT 24 |
| Finished | May 05 12:47:11 PM PDT 24 |
| Peak memory | 212424 kb |
| Host | smart-a17809cd-7413-4208-a2b5-19bad5e40d4c |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3306532516 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_kmac_err_chk.3306532516 |
| Directory | /workspace/28.rom_ctrl_kmac_err_chk/latest |
| Test location | /workspace/coverage/default/28.rom_ctrl_max_throughput_chk.2054362059 |
| Short name | T267 |
| Test name | |
| Test status | |
| Simulation time | 1207458504 ps |
| CPU time | 12.69 seconds |
| Started | May 05 12:46:38 PM PDT 24 |
| Finished | May 05 12:46:52 PM PDT 24 |
| Peak memory | 211632 kb |
| Host | smart-2a726f79-b72a-49f5-b403-e2acd22d2242 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2054362059 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_max_throughput_chk.2054362059 |
| Directory | /workspace/28.rom_ctrl_max_throughput_chk/latest |
| Test location | /workspace/coverage/default/28.rom_ctrl_smoke.549923560 |
| Short name | T151 |
| Test name | |
| Test status | |
| Simulation time | 2082662398 ps |
| CPU time | 22.87 seconds |
| Started | May 05 12:46:38 PM PDT 24 |
| Finished | May 05 12:47:02 PM PDT 24 |
| Peak memory | 214204 kb |
| Host | smart-1cb88212-35ab-4f98-8dc1-adc818a44eca |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=549923560 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_smoke.549923560 |
| Directory | /workspace/28.rom_ctrl_smoke/latest |
| Test location | /workspace/coverage/default/28.rom_ctrl_stress_all.1573298549 |
| Short name | T176 |
| Test name | |
| Test status | |
| Simulation time | 1375712265 ps |
| CPU time | 19.23 seconds |
| Started | May 05 12:46:39 PM PDT 24 |
| Finished | May 05 12:46:59 PM PDT 24 |
| Peak memory | 214540 kb |
| Host | smart-a55781c6-96d5-420b-844f-fb9b40ae0bc1 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1573298549 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm _name 28.rom_ctrl_stress_all.1573298549 |
| Directory | /workspace/28.rom_ctrl_stress_all/latest |
| Test location | /workspace/coverage/default/28.rom_ctrl_stress_all_with_rand_reset.3252667403 |
| Short name | T23 |
| Test name | |
| Test status | |
| Simulation time | 49861107253 ps |
| CPU time | 1898.97 seconds |
| Started | May 05 12:46:40 PM PDT 24 |
| Finished | May 05 01:18:20 PM PDT 24 |
| Peak memory | 236392 kb |
| Host | smart-b051cbb2-5dce-4e97-9808-2f71d23de72e |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3252667403 -assert nop ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_stress_all_with_rand_reset.3252667403 |
| Directory | /workspace/28.rom_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/29.rom_ctrl_alert_test.3304129288 |
| Short name | T250 |
| Test name | |
| Test status | |
| Simulation time | 11312909791 ps |
| CPU time | 13.43 seconds |
| Started | May 05 12:46:51 PM PDT 24 |
| Finished | May 05 12:47:05 PM PDT 24 |
| Peak memory | 211748 kb |
| Host | smart-beb3a555-2774-4194-81a1-427e53481dff |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3304129288 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_alert_test.3304129288 |
| Directory | /workspace/29.rom_ctrl_alert_test/latest |
| Test location | /workspace/coverage/default/29.rom_ctrl_corrupt_sig_fatal_chk.3238054854 |
| Short name | T359 |
| Test name | |
| Test status | |
| Simulation time | 60420113239 ps |
| CPU time | 317.06 seconds |
| Started | May 05 12:46:42 PM PDT 24 |
| Finished | May 05 12:51:59 PM PDT 24 |
| Peak memory | 213036 kb |
| Host | smart-230f1e15-a882-4c9a-a6cc-fdea20e5487a |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3238054854 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_ corrupt_sig_fatal_chk.3238054854 |
| Directory | /workspace/29.rom_ctrl_corrupt_sig_fatal_chk/latest |
| Test location | /workspace/coverage/default/29.rom_ctrl_kmac_err_chk.2221224663 |
| Short name | T140 |
| Test name | |
| Test status | |
| Simulation time | 2916712560 ps |
| CPU time | 26.91 seconds |
| Started | May 05 12:46:46 PM PDT 24 |
| Finished | May 05 12:47:13 PM PDT 24 |
| Peak memory | 212348 kb |
| Host | smart-9339b4cb-7c4a-40a6-9236-a12dff01eff9 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2221224663 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_kmac_err_chk.2221224663 |
| Directory | /workspace/29.rom_ctrl_kmac_err_chk/latest |
| Test location | /workspace/coverage/default/29.rom_ctrl_max_throughput_chk.3980302929 |
| Short name | T89 |
| Test name | |
| Test status | |
| Simulation time | 1983672368 ps |
| CPU time | 10.76 seconds |
| Started | May 05 12:46:46 PM PDT 24 |
| Finished | May 05 12:46:58 PM PDT 24 |
| Peak memory | 211564 kb |
| Host | smart-ddaebbc0-7cb7-4ab3-b81b-086d363dd6e3 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3980302929 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_max_throughput_chk.3980302929 |
| Directory | /workspace/29.rom_ctrl_max_throughput_chk/latest |
| Test location | /workspace/coverage/default/29.rom_ctrl_smoke.3105337737 |
| Short name | T7 |
| Test name | |
| Test status | |
| Simulation time | 5317433306 ps |
| CPU time | 24.48 seconds |
| Started | May 05 12:46:38 PM PDT 24 |
| Finished | May 05 12:47:03 PM PDT 24 |
| Peak memory | 214072 kb |
| Host | smart-93e6ce19-fbcf-4f79-80a9-ab35084fd6d4 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3105337737 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_smoke.3105337737 |
| Directory | /workspace/29.rom_ctrl_smoke/latest |
| Test location | /workspace/coverage/default/29.rom_ctrl_stress_all.2383278574 |
| Short name | T57 |
| Test name | |
| Test status | |
| Simulation time | 1488197612 ps |
| CPU time | 32.46 seconds |
| Started | May 05 12:46:39 PM PDT 24 |
| Finished | May 05 12:47:12 PM PDT 24 |
| Peak memory | 216504 kb |
| Host | smart-1643b2c0-071a-4419-b560-60d444c63bc3 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2383278574 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm _name 29.rom_ctrl_stress_all.2383278574 |
| Directory | /workspace/29.rom_ctrl_stress_all/latest |
| Test location | /workspace/coverage/default/29.rom_ctrl_stress_all_with_rand_reset.3618716571 |
| Short name | T21 |
| Test name | |
| Test status | |
| Simulation time | 139540135096 ps |
| CPU time | 1301.1 seconds |
| Started | May 05 12:46:46 PM PDT 24 |
| Finished | May 05 01:08:28 PM PDT 24 |
| Peak memory | 233936 kb |
| Host | smart-24508be7-081e-4334-b282-5afa336c7cb9 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3618716571 -assert nop ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_stress_all_with_rand_reset.3618716571 |
| Directory | /workspace/29.rom_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/3.rom_ctrl_alert_test.2576662720 |
| Short name | T124 |
| Test name | |
| Test status | |
| Simulation time | 174998835 ps |
| CPU time | 4.26 seconds |
| Started | May 05 12:46:13 PM PDT 24 |
| Finished | May 05 12:46:18 PM PDT 24 |
| Peak memory | 211584 kb |
| Host | smart-f8025dec-fbf6-45bf-9677-8d4af02b97f3 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2576662720 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_alert_test.2576662720 |
| Directory | /workspace/3.rom_ctrl_alert_test/latest |
| Test location | /workspace/coverage/default/3.rom_ctrl_corrupt_sig_fatal_chk.2573652958 |
| Short name | T236 |
| Test name | |
| Test status | |
| Simulation time | 28511555861 ps |
| CPU time | 109.45 seconds |
| Started | May 05 12:46:18 PM PDT 24 |
| Finished | May 05 12:48:08 PM PDT 24 |
| Peak memory | 230552 kb |
| Host | smart-18dfd89d-c1c0-4293-9fe0-80a87c3ab7d0 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2573652958 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_c orrupt_sig_fatal_chk.2573652958 |
| Directory | /workspace/3.rom_ctrl_corrupt_sig_fatal_chk/latest |
| Test location | /workspace/coverage/default/3.rom_ctrl_kmac_err_chk.4038730101 |
| Short name | T245 |
| Test name | |
| Test status | |
| Simulation time | 521067264 ps |
| CPU time | 11.05 seconds |
| Started | May 05 12:46:15 PM PDT 24 |
| Finished | May 05 12:46:28 PM PDT 24 |
| Peak memory | 212360 kb |
| Host | smart-4f5070e5-193d-4c48-a7b3-c7893cca725f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4038730101 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_kmac_err_chk.4038730101 |
| Directory | /workspace/3.rom_ctrl_kmac_err_chk/latest |
| Test location | /workspace/coverage/default/3.rom_ctrl_max_throughput_chk.2607213943 |
| Short name | T210 |
| Test name | |
| Test status | |
| Simulation time | 184354682 ps |
| CPU time | 5.39 seconds |
| Started | May 05 12:46:14 PM PDT 24 |
| Finished | May 05 12:46:20 PM PDT 24 |
| Peak memory | 211540 kb |
| Host | smart-7e281d73-b4b1-435c-8a92-bcd9c2e8c267 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2607213943 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_max_throughput_chk.2607213943 |
| Directory | /workspace/3.rom_ctrl_max_throughput_chk/latest |
| Test location | /workspace/coverage/default/3.rom_ctrl_smoke.1134835244 |
| Short name | T320 |
| Test name | |
| Test status | |
| Simulation time | 747080937 ps |
| CPU time | 9.87 seconds |
| Started | May 05 12:46:08 PM PDT 24 |
| Finished | May 05 12:46:19 PM PDT 24 |
| Peak memory | 219868 kb |
| Host | smart-2c93d725-fc82-4d1e-ac9b-5f28eba3889e |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1134835244 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_smoke.1134835244 |
| Directory | /workspace/3.rom_ctrl_smoke/latest |
| Test location | /workspace/coverage/default/3.rom_ctrl_stress_all.3184871491 |
| Short name | T244 |
| Test name | |
| Test status | |
| Simulation time | 2584399073 ps |
| CPU time | 38.14 seconds |
| Started | May 05 12:46:07 PM PDT 24 |
| Finished | May 05 12:46:46 PM PDT 24 |
| Peak memory | 215716 kb |
| Host | smart-8cf68d0b-bf71-481e-8956-40651e567567 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3184871491 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm _name 3.rom_ctrl_stress_all.3184871491 |
| Directory | /workspace/3.rom_ctrl_stress_all/latest |
| Test location | /workspace/coverage/default/30.rom_ctrl_alert_test.4188768625 |
| Short name | T333 |
| Test name | |
| Test status | |
| Simulation time | 1549587354 ps |
| CPU time | 5.03 seconds |
| Started | May 05 12:46:41 PM PDT 24 |
| Finished | May 05 12:46:47 PM PDT 24 |
| Peak memory | 211696 kb |
| Host | smart-29027d69-8dca-4d4a-939b-2263f386b8b3 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4188768625 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_alert_test.4188768625 |
| Directory | /workspace/30.rom_ctrl_alert_test/latest |
| Test location | /workspace/coverage/default/30.rom_ctrl_corrupt_sig_fatal_chk.2036233793 |
| Short name | T153 |
| Test name | |
| Test status | |
| Simulation time | 42868784691 ps |
| CPU time | 388.02 seconds |
| Started | May 05 12:46:46 PM PDT 24 |
| Finished | May 05 12:53:15 PM PDT 24 |
| Peak memory | 237120 kb |
| Host | smart-6cac4d65-dc60-49a7-bcb8-cc871ca873e0 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2036233793 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_ corrupt_sig_fatal_chk.2036233793 |
| Directory | /workspace/30.rom_ctrl_corrupt_sig_fatal_chk/latest |
| Test location | /workspace/coverage/default/30.rom_ctrl_kmac_err_chk.2900750557 |
| Short name | T125 |
| Test name | |
| Test status | |
| Simulation time | 1537860234 ps |
| CPU time | 18.74 seconds |
| Started | May 05 12:46:47 PM PDT 24 |
| Finished | May 05 12:47:06 PM PDT 24 |
| Peak memory | 211692 kb |
| Host | smart-7024caee-6828-4132-a1b3-9df0c5708a0d |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2900750557 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_kmac_err_chk.2900750557 |
| Directory | /workspace/30.rom_ctrl_kmac_err_chk/latest |
| Test location | /workspace/coverage/default/30.rom_ctrl_max_throughput_chk.1243502419 |
| Short name | T242 |
| Test name | |
| Test status | |
| Simulation time | 1042260998 ps |
| CPU time | 11.79 seconds |
| Started | May 05 12:46:46 PM PDT 24 |
| Finished | May 05 12:46:59 PM PDT 24 |
| Peak memory | 211552 kb |
| Host | smart-82543791-f3c7-474d-929a-e8e0051552be |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1243502419 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_max_throughput_chk.1243502419 |
| Directory | /workspace/30.rom_ctrl_max_throughput_chk/latest |
| Test location | /workspace/coverage/default/30.rom_ctrl_smoke.2142895160 |
| Short name | T12 |
| Test name | |
| Test status | |
| Simulation time | 689263401 ps |
| CPU time | 10.12 seconds |
| Started | May 05 12:46:46 PM PDT 24 |
| Finished | May 05 12:46:57 PM PDT 24 |
| Peak memory | 219828 kb |
| Host | smart-2d96652b-b6eb-4e3b-9abc-06673d0824eb |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2142895160 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_smoke.2142895160 |
| Directory | /workspace/30.rom_ctrl_smoke/latest |
| Test location | /workspace/coverage/default/30.rom_ctrl_stress_all.495882393 |
| Short name | T316 |
| Test name | |
| Test status | |
| Simulation time | 5468770103 ps |
| CPU time | 44.05 seconds |
| Started | May 05 12:46:47 PM PDT 24 |
| Finished | May 05 12:47:32 PM PDT 24 |
| Peak memory | 217100 kb |
| Host | smart-223d996b-1d6a-4a72-a3b1-95bebf157e6c |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=495882393 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test + UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 30.rom_ctrl_stress_all.495882393 |
| Directory | /workspace/30.rom_ctrl_stress_all/latest |
| Test location | /workspace/coverage/default/30.rom_ctrl_stress_all_with_rand_reset.3866459391 |
| Short name | T20 |
| Test name | |
| Test status | |
| Simulation time | 42458619285 ps |
| CPU time | 1296.1 seconds |
| Started | May 05 12:46:50 PM PDT 24 |
| Finished | May 05 01:08:27 PM PDT 24 |
| Peak memory | 228284 kb |
| Host | smart-ac77ab8e-54a9-4dd2-b566-cdd9385c7ec2 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3866459391 -assert nop ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_stress_all_with_rand_reset.3866459391 |
| Directory | /workspace/30.rom_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/31.rom_ctrl_alert_test.3686307440 |
| Short name | T279 |
| Test name | |
| Test status | |
| Simulation time | 4123397072 ps |
| CPU time | 16.3 seconds |
| Started | May 05 12:46:49 PM PDT 24 |
| Finished | May 05 12:47:05 PM PDT 24 |
| Peak memory | 211724 kb |
| Host | smart-b9a1deef-3789-41e5-bec7-d97264c5e05a |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3686307440 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_alert_test.3686307440 |
| Directory | /workspace/31.rom_ctrl_alert_test/latest |
| Test location | /workspace/coverage/default/31.rom_ctrl_corrupt_sig_fatal_chk.4078412139 |
| Short name | T166 |
| Test name | |
| Test status | |
| Simulation time | 3202576584 ps |
| CPU time | 59.31 seconds |
| Started | May 05 12:46:50 PM PDT 24 |
| Finished | May 05 12:47:50 PM PDT 24 |
| Peak memory | 233180 kb |
| Host | smart-d5edcdf6-ab7f-430e-878d-b5f3c2ab399d |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4078412139 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_ corrupt_sig_fatal_chk.4078412139 |
| Directory | /workspace/31.rom_ctrl_corrupt_sig_fatal_chk/latest |
| Test location | /workspace/coverage/default/31.rom_ctrl_kmac_err_chk.3093713468 |
| Short name | T181 |
| Test name | |
| Test status | |
| Simulation time | 11502292959 ps |
| CPU time | 25.76 seconds |
| Started | May 05 12:46:46 PM PDT 24 |
| Finished | May 05 12:47:12 PM PDT 24 |
| Peak memory | 211880 kb |
| Host | smart-3b770c88-2f0e-479d-9a6b-3036d98adfe9 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3093713468 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_kmac_err_chk.3093713468 |
| Directory | /workspace/31.rom_ctrl_kmac_err_chk/latest |
| Test location | /workspace/coverage/default/31.rom_ctrl_max_throughput_chk.2216834115 |
| Short name | T368 |
| Test name | |
| Test status | |
| Simulation time | 4665112807 ps |
| CPU time | 11.82 seconds |
| Started | May 05 12:46:46 PM PDT 24 |
| Finished | May 05 12:46:59 PM PDT 24 |
| Peak memory | 211736 kb |
| Host | smart-8e6d3755-16c8-47b6-aae5-9feb6d04b7d6 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2216834115 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_max_throughput_chk.2216834115 |
| Directory | /workspace/31.rom_ctrl_max_throughput_chk/latest |
| Test location | /workspace/coverage/default/31.rom_ctrl_smoke.2588897084 |
| Short name | T367 |
| Test name | |
| Test status | |
| Simulation time | 11259067784 ps |
| CPU time | 26.15 seconds |
| Started | May 05 12:46:47 PM PDT 24 |
| Finished | May 05 12:47:14 PM PDT 24 |
| Peak memory | 219932 kb |
| Host | smart-334ca391-61a1-4f52-8694-4eb178835ca0 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2588897084 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_smoke.2588897084 |
| Directory | /workspace/31.rom_ctrl_smoke/latest |
| Test location | /workspace/coverage/default/32.rom_ctrl_alert_test.1677863821 |
| Short name | T129 |
| Test name | |
| Test status | |
| Simulation time | 298233669 ps |
| CPU time | 4.23 seconds |
| Started | May 05 12:46:50 PM PDT 24 |
| Finished | May 05 12:46:55 PM PDT 24 |
| Peak memory | 211492 kb |
| Host | smart-10b50724-8faf-48a5-96b0-4393341c8615 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1677863821 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_alert_test.1677863821 |
| Directory | /workspace/32.rom_ctrl_alert_test/latest |
| Test location | /workspace/coverage/default/32.rom_ctrl_corrupt_sig_fatal_chk.3604447314 |
| Short name | T284 |
| Test name | |
| Test status | |
| Simulation time | 300780844197 ps |
| CPU time | 257.44 seconds |
| Started | May 05 12:46:50 PM PDT 24 |
| Finished | May 05 12:51:08 PM PDT 24 |
| Peak memory | 231196 kb |
| Host | smart-6973b517-813e-433b-9dab-c99e39b3b005 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3604447314 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_ corrupt_sig_fatal_chk.3604447314 |
| Directory | /workspace/32.rom_ctrl_corrupt_sig_fatal_chk/latest |
| Test location | /workspace/coverage/default/32.rom_ctrl_kmac_err_chk.1093536708 |
| Short name | T191 |
| Test name | |
| Test status | |
| Simulation time | 3155599243 ps |
| CPU time | 27.66 seconds |
| Started | May 05 12:46:50 PM PDT 24 |
| Finished | May 05 12:47:19 PM PDT 24 |
| Peak memory | 212428 kb |
| Host | smart-ebd8f7cd-d82e-4248-aee0-42dc0d9d6ac2 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1093536708 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_kmac_err_chk.1093536708 |
| Directory | /workspace/32.rom_ctrl_kmac_err_chk/latest |
| Test location | /workspace/coverage/default/32.rom_ctrl_max_throughput_chk.3881857438 |
| Short name | T107 |
| Test name | |
| Test status | |
| Simulation time | 2798671657 ps |
| CPU time | 13.01 seconds |
| Started | May 05 12:46:50 PM PDT 24 |
| Finished | May 05 12:47:03 PM PDT 24 |
| Peak memory | 211672 kb |
| Host | smart-5297c8e9-cbb8-4905-a585-261ada832869 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3881857438 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_max_throughput_chk.3881857438 |
| Directory | /workspace/32.rom_ctrl_max_throughput_chk/latest |
| Test location | /workspace/coverage/default/32.rom_ctrl_smoke.1695499245 |
| Short name | T150 |
| Test name | |
| Test status | |
| Simulation time | 8200466545 ps |
| CPU time | 34.79 seconds |
| Started | May 05 12:46:47 PM PDT 24 |
| Finished | May 05 12:47:23 PM PDT 24 |
| Peak memory | 219956 kb |
| Host | smart-0073dfb4-f514-411e-990e-9791cb90efb9 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1695499245 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_smoke.1695499245 |
| Directory | /workspace/32.rom_ctrl_smoke/latest |
| Test location | /workspace/coverage/default/32.rom_ctrl_stress_all.2590621027 |
| Short name | T163 |
| Test name | |
| Test status | |
| Simulation time | 27485019756 ps |
| CPU time | 26.71 seconds |
| Started | May 05 12:46:56 PM PDT 24 |
| Finished | May 05 12:47:23 PM PDT 24 |
| Peak memory | 219928 kb |
| Host | smart-7b325b87-506d-46d3-86ce-a588a1770ac1 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2590621027 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm _name 32.rom_ctrl_stress_all.2590621027 |
| Directory | /workspace/32.rom_ctrl_stress_all/latest |
| Test location | /workspace/coverage/default/32.rom_ctrl_stress_all_with_rand_reset.1531286322 |
| Short name | T109 |
| Test name | |
| Test status | |
| Simulation time | 16591666599 ps |
| CPU time | 5461.34 seconds |
| Started | May 05 12:46:46 PM PDT 24 |
| Finished | May 05 02:17:49 PM PDT 24 |
| Peak memory | 229160 kb |
| Host | smart-e98becac-5809-4896-a437-dcf59de30530 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1531286322 -assert nop ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_stress_all_with_rand_reset.1531286322 |
| Directory | /workspace/32.rom_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/33.rom_ctrl_alert_test.351559657 |
| Short name | T201 |
| Test name | |
| Test status | |
| Simulation time | 415889901 ps |
| CPU time | 7.13 seconds |
| Started | May 05 12:46:48 PM PDT 24 |
| Finished | May 05 12:46:56 PM PDT 24 |
| Peak memory | 211644 kb |
| Host | smart-bc59adb0-0484-43b9-b11a-9df34dd895c6 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=351559657 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_alert_test.351559657 |
| Directory | /workspace/33.rom_ctrl_alert_test/latest |
| Test location | /workspace/coverage/default/33.rom_ctrl_corrupt_sig_fatal_chk.1871096640 |
| Short name | T32 |
| Test name | |
| Test status | |
| Simulation time | 3818823172 ps |
| CPU time | 126.27 seconds |
| Started | May 05 12:46:49 PM PDT 24 |
| Finished | May 05 12:48:56 PM PDT 24 |
| Peak memory | 239260 kb |
| Host | smart-36a2b3ef-ab53-4e0b-84b0-2275ddf23eb9 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1871096640 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_ corrupt_sig_fatal_chk.1871096640 |
| Directory | /workspace/33.rom_ctrl_corrupt_sig_fatal_chk/latest |
| Test location | /workspace/coverage/default/33.rom_ctrl_kmac_err_chk.2934144954 |
| Short name | T135 |
| Test name | |
| Test status | |
| Simulation time | 16871453053 ps |
| CPU time | 23.73 seconds |
| Started | May 05 12:46:52 PM PDT 24 |
| Finished | May 05 12:47:16 PM PDT 24 |
| Peak memory | 212700 kb |
| Host | smart-79ce6aa1-e427-4541-9cb5-fea8f47dfe83 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2934144954 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_kmac_err_chk.2934144954 |
| Directory | /workspace/33.rom_ctrl_kmac_err_chk/latest |
| Test location | /workspace/coverage/default/33.rom_ctrl_max_throughput_chk.211181252 |
| Short name | T189 |
| Test name | |
| Test status | |
| Simulation time | 277641165 ps |
| CPU time | 6.04 seconds |
| Started | May 05 12:46:52 PM PDT 24 |
| Finished | May 05 12:46:58 PM PDT 24 |
| Peak memory | 211608 kb |
| Host | smart-db60c59e-3b75-44ce-beb2-1cd0a4855da8 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=211181252 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_max_throughput_chk.211181252 |
| Directory | /workspace/33.rom_ctrl_max_throughput_chk/latest |
| Test location | /workspace/coverage/default/33.rom_ctrl_smoke.3165666976 |
| Short name | T317 |
| Test name | |
| Test status | |
| Simulation time | 4244355006 ps |
| CPU time | 23.39 seconds |
| Started | May 05 12:46:48 PM PDT 24 |
| Finished | May 05 12:47:12 PM PDT 24 |
| Peak memory | 214112 kb |
| Host | smart-0f3b1b09-d6c6-4ea1-a9ed-618a7581b537 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3165666976 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_smoke.3165666976 |
| Directory | /workspace/33.rom_ctrl_smoke/latest |
| Test location | /workspace/coverage/default/33.rom_ctrl_stress_all.269814156 |
| Short name | T160 |
| Test name | |
| Test status | |
| Simulation time | 5225332755 ps |
| CPU time | 51.78 seconds |
| Started | May 05 12:46:48 PM PDT 24 |
| Finished | May 05 12:47:40 PM PDT 24 |
| Peak memory | 216832 kb |
| Host | smart-c3b1284e-3a27-48f8-bf4b-1bdbc035e6c8 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=269814156 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test + UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 33.rom_ctrl_stress_all.269814156 |
| Directory | /workspace/33.rom_ctrl_stress_all/latest |
| Test location | /workspace/coverage/default/34.rom_ctrl_alert_test.750830852 |
| Short name | T229 |
| Test name | |
| Test status | |
| Simulation time | 1925096740 ps |
| CPU time | 15.38 seconds |
| Started | May 05 12:47:00 PM PDT 24 |
| Finished | May 05 12:47:16 PM PDT 24 |
| Peak memory | 211580 kb |
| Host | smart-23792350-f1cb-4693-aac4-fd33a5aecc62 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=750830852 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_alert_test.750830852 |
| Directory | /workspace/34.rom_ctrl_alert_test/latest |
| Test location | /workspace/coverage/default/34.rom_ctrl_corrupt_sig_fatal_chk.1485411096 |
| Short name | T303 |
| Test name | |
| Test status | |
| Simulation time | 4510470673 ps |
| CPU time | 85.03 seconds |
| Started | May 05 12:46:48 PM PDT 24 |
| Finished | May 05 12:48:14 PM PDT 24 |
| Peak memory | 220152 kb |
| Host | smart-9eb40f59-f7cd-4dc1-b55c-933478545c9f |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1485411096 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_ corrupt_sig_fatal_chk.1485411096 |
| Directory | /workspace/34.rom_ctrl_corrupt_sig_fatal_chk/latest |
| Test location | /workspace/coverage/default/34.rom_ctrl_kmac_err_chk.2062802637 |
| Short name | T195 |
| Test name | |
| Test status | |
| Simulation time | 1328796373 ps |
| CPU time | 11.46 seconds |
| Started | May 05 12:46:51 PM PDT 24 |
| Finished | May 05 12:47:03 PM PDT 24 |
| Peak memory | 211732 kb |
| Host | smart-97bc0a4b-0c34-4369-8dde-5fe5569f7aa6 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2062802637 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_kmac_err_chk.2062802637 |
| Directory | /workspace/34.rom_ctrl_kmac_err_chk/latest |
| Test location | /workspace/coverage/default/34.rom_ctrl_max_throughput_chk.4133705679 |
| Short name | T138 |
| Test name | |
| Test status | |
| Simulation time | 187264164 ps |
| CPU time | 5.39 seconds |
| Started | May 05 12:46:50 PM PDT 24 |
| Finished | May 05 12:46:56 PM PDT 24 |
| Peak memory | 211520 kb |
| Host | smart-1de88a08-e998-4e2c-b86b-c0c0dbde3084 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=4133705679 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_max_throughput_chk.4133705679 |
| Directory | /workspace/34.rom_ctrl_max_throughput_chk/latest |
| Test location | /workspace/coverage/default/34.rom_ctrl_smoke.1071725291 |
| Short name | T232 |
| Test name | |
| Test status | |
| Simulation time | 2061738488 ps |
| CPU time | 26.32 seconds |
| Started | May 05 12:46:49 PM PDT 24 |
| Finished | May 05 12:47:16 PM PDT 24 |
| Peak memory | 213556 kb |
| Host | smart-7402916c-9786-4740-bac4-92385e0752db |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1071725291 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_smoke.1071725291 |
| Directory | /workspace/34.rom_ctrl_smoke/latest |
| Test location | /workspace/coverage/default/34.rom_ctrl_stress_all.286912306 |
| Short name | T315 |
| Test name | |
| Test status | |
| Simulation time | 3148377337 ps |
| CPU time | 14.41 seconds |
| Started | May 05 12:46:56 PM PDT 24 |
| Finished | May 05 12:47:11 PM PDT 24 |
| Peak memory | 212168 kb |
| Host | smart-96732e5b-dbdb-41c4-bc3b-6da758ebf47c |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=286912306 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test + UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 34.rom_ctrl_stress_all.286912306 |
| Directory | /workspace/34.rom_ctrl_stress_all/latest |
| Test location | /workspace/coverage/default/35.rom_ctrl_alert_test.3391238528 |
| Short name | T90 |
| Test name | |
| Test status | |
| Simulation time | 2210303328 ps |
| CPU time | 10.48 seconds |
| Started | May 05 12:46:57 PM PDT 24 |
| Finished | May 05 12:47:08 PM PDT 24 |
| Peak memory | 211796 kb |
| Host | smart-6a6ea8b2-17b0-47cb-8082-203534bab726 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3391238528 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_alert_test.3391238528 |
| Directory | /workspace/35.rom_ctrl_alert_test/latest |
| Test location | /workspace/coverage/default/35.rom_ctrl_corrupt_sig_fatal_chk.2140610743 |
| Short name | T239 |
| Test name | |
| Test status | |
| Simulation time | 1981986875 ps |
| CPU time | 125.34 seconds |
| Started | May 05 12:46:56 PM PDT 24 |
| Finished | May 05 12:49:02 PM PDT 24 |
| Peak memory | 236848 kb |
| Host | smart-c4e39cf3-790f-473c-b007-73cb4b240125 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2140610743 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_ corrupt_sig_fatal_chk.2140610743 |
| Directory | /workspace/35.rom_ctrl_corrupt_sig_fatal_chk/latest |
| Test location | /workspace/coverage/default/35.rom_ctrl_kmac_err_chk.3215424750 |
| Short name | T227 |
| Test name | |
| Test status | |
| Simulation time | 9021639863 ps |
| CPU time | 21.05 seconds |
| Started | May 05 12:46:56 PM PDT 24 |
| Finished | May 05 12:47:17 PM PDT 24 |
| Peak memory | 212696 kb |
| Host | smart-49ff1549-9dda-4115-8f38-850890e008b2 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3215424750 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_kmac_err_chk.3215424750 |
| Directory | /workspace/35.rom_ctrl_kmac_err_chk/latest |
| Test location | /workspace/coverage/default/35.rom_ctrl_max_throughput_chk.3740027954 |
| Short name | T282 |
| Test name | |
| Test status | |
| Simulation time | 2083887212 ps |
| CPU time | 17.23 seconds |
| Started | May 05 12:46:57 PM PDT 24 |
| Finished | May 05 12:47:15 PM PDT 24 |
| Peak memory | 211800 kb |
| Host | smart-f4bd2800-3946-4bf2-96ec-f4fc881793e7 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3740027954 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_max_throughput_chk.3740027954 |
| Directory | /workspace/35.rom_ctrl_max_throughput_chk/latest |
| Test location | /workspace/coverage/default/35.rom_ctrl_smoke.808493154 |
| Short name | T209 |
| Test name | |
| Test status | |
| Simulation time | 4867176621 ps |
| CPU time | 20.55 seconds |
| Started | May 05 12:46:57 PM PDT 24 |
| Finished | May 05 12:47:18 PM PDT 24 |
| Peak memory | 219916 kb |
| Host | smart-153f502a-718c-4d34-97d5-e3bd20d5fedb |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=808493154 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_smoke.808493154 |
| Directory | /workspace/35.rom_ctrl_smoke/latest |
| Test location | /workspace/coverage/default/35.rom_ctrl_stress_all.267063349 |
| Short name | T275 |
| Test name | |
| Test status | |
| Simulation time | 3482811883 ps |
| CPU time | 30.5 seconds |
| Started | May 05 12:46:56 PM PDT 24 |
| Finished | May 05 12:47:27 PM PDT 24 |
| Peak memory | 214768 kb |
| Host | smart-6bc2af50-76d6-4a09-9975-f4b52be3f924 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=267063349 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test + UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 35.rom_ctrl_stress_all.267063349 |
| Directory | /workspace/35.rom_ctrl_stress_all/latest |
| Test location | /workspace/coverage/default/35.rom_ctrl_stress_all_with_rand_reset.3071480096 |
| Short name | T274 |
| Test name | |
| Test status | |
| Simulation time | 28483285599 ps |
| CPU time | 781.35 seconds |
| Started | May 05 12:46:59 PM PDT 24 |
| Finished | May 05 01:00:01 PM PDT 24 |
| Peak memory | 236408 kb |
| Host | smart-37d59808-88e9-42a3-91ff-ead80741369b |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3071480096 -assert nop ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_stress_all_with_rand_reset.3071480096 |
| Directory | /workspace/35.rom_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/36.rom_ctrl_alert_test.1098475659 |
| Short name | T207 |
| Test name | |
| Test status | |
| Simulation time | 1672211908 ps |
| CPU time | 14.04 seconds |
| Started | May 05 12:46:55 PM PDT 24 |
| Finished | May 05 12:47:10 PM PDT 24 |
| Peak memory | 211692 kb |
| Host | smart-84e531d5-6c0e-4e13-97f5-9c2592a44cbc |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1098475659 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_alert_test.1098475659 |
| Directory | /workspace/36.rom_ctrl_alert_test/latest |
| Test location | /workspace/coverage/default/36.rom_ctrl_corrupt_sig_fatal_chk.1311033470 |
| Short name | T10 |
| Test name | |
| Test status | |
| Simulation time | 95141511381 ps |
| CPU time | 429.97 seconds |
| Started | May 05 12:46:56 PM PDT 24 |
| Finished | May 05 12:54:07 PM PDT 24 |
| Peak memory | 234556 kb |
| Host | smart-bf8570f4-8070-4384-b702-d02952518fda |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1311033470 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_ corrupt_sig_fatal_chk.1311033470 |
| Directory | /workspace/36.rom_ctrl_corrupt_sig_fatal_chk/latest |
| Test location | /workspace/coverage/default/36.rom_ctrl_kmac_err_chk.685388075 |
| Short name | T184 |
| Test name | |
| Test status | |
| Simulation time | 5574569596 ps |
| CPU time | 17.9 seconds |
| Started | May 05 12:46:59 PM PDT 24 |
| Finished | May 05 12:47:17 PM PDT 24 |
| Peak memory | 212740 kb |
| Host | smart-edcaa62d-092f-4f6a-a0f2-f629e27629c6 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=685388075 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_kmac_err_chk.685388075 |
| Directory | /workspace/36.rom_ctrl_kmac_err_chk/latest |
| Test location | /workspace/coverage/default/36.rom_ctrl_max_throughput_chk.517153651 |
| Short name | T255 |
| Test name | |
| Test status | |
| Simulation time | 1352662525 ps |
| CPU time | 12.63 seconds |
| Started | May 05 12:47:03 PM PDT 24 |
| Finished | May 05 12:47:16 PM PDT 24 |
| Peak memory | 211636 kb |
| Host | smart-5da895ac-4ac1-482f-a5db-50eee6b9ce41 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=517153651 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_max_throughput_chk.517153651 |
| Directory | /workspace/36.rom_ctrl_max_throughput_chk/latest |
| Test location | /workspace/coverage/default/36.rom_ctrl_smoke.3830812148 |
| Short name | T217 |
| Test name | |
| Test status | |
| Simulation time | 2308104884 ps |
| CPU time | 25.68 seconds |
| Started | May 05 12:46:58 PM PDT 24 |
| Finished | May 05 12:47:24 PM PDT 24 |
| Peak memory | 220176 kb |
| Host | smart-5d859325-b944-4d6c-9e5f-ab796e67b7ae |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3830812148 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_smoke.3830812148 |
| Directory | /workspace/36.rom_ctrl_smoke/latest |
| Test location | /workspace/coverage/default/36.rom_ctrl_stress_all.3852104068 |
| Short name | T154 |
| Test name | |
| Test status | |
| Simulation time | 8065948411 ps |
| CPU time | 8.65 seconds |
| Started | May 05 12:47:00 PM PDT 24 |
| Finished | May 05 12:47:09 PM PDT 24 |
| Peak memory | 211744 kb |
| Host | smart-96c4d6de-85f2-46b3-af53-cab559cf2dda |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3852104068 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm _name 36.rom_ctrl_stress_all.3852104068 |
| Directory | /workspace/36.rom_ctrl_stress_all/latest |
| Test location | /workspace/coverage/default/37.rom_ctrl_alert_test.2948560619 |
| Short name | T296 |
| Test name | |
| Test status | |
| Simulation time | 3610714590 ps |
| CPU time | 9.86 seconds |
| Started | May 05 12:47:01 PM PDT 24 |
| Finished | May 05 12:47:12 PM PDT 24 |
| Peak memory | 211864 kb |
| Host | smart-5eb143b3-ed6b-4a93-8a09-a9f64f97d0fa |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2948560619 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_alert_test.2948560619 |
| Directory | /workspace/37.rom_ctrl_alert_test/latest |
| Test location | /workspace/coverage/default/37.rom_ctrl_corrupt_sig_fatal_chk.4098570714 |
| Short name | T292 |
| Test name | |
| Test status | |
| Simulation time | 12625530559 ps |
| CPU time | 151.69 seconds |
| Started | May 05 12:46:58 PM PDT 24 |
| Finished | May 05 12:49:31 PM PDT 24 |
| Peak memory | 213068 kb |
| Host | smart-ec290838-2ce2-4b5d-a633-df0a0ea4e038 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4098570714 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_ corrupt_sig_fatal_chk.4098570714 |
| Directory | /workspace/37.rom_ctrl_corrupt_sig_fatal_chk/latest |
| Test location | /workspace/coverage/default/37.rom_ctrl_kmac_err_chk.4084663767 |
| Short name | T182 |
| Test name | |
| Test status | |
| Simulation time | 4793380649 ps |
| CPU time | 17.51 seconds |
| Started | May 05 12:46:59 PM PDT 24 |
| Finished | May 05 12:47:18 PM PDT 24 |
| Peak memory | 212556 kb |
| Host | smart-bad1a715-e629-4715-81c2-ed6c8b24c307 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4084663767 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_kmac_err_chk.4084663767 |
| Directory | /workspace/37.rom_ctrl_kmac_err_chk/latest |
| Test location | /workspace/coverage/default/37.rom_ctrl_max_throughput_chk.3964976507 |
| Short name | T353 |
| Test name | |
| Test status | |
| Simulation time | 880389715 ps |
| CPU time | 10.78 seconds |
| Started | May 05 12:46:59 PM PDT 24 |
| Finished | May 05 12:47:10 PM PDT 24 |
| Peak memory | 211528 kb |
| Host | smart-7c8f95a6-2ca5-4018-8281-8d291ed810ad |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3964976507 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_max_throughput_chk.3964976507 |
| Directory | /workspace/37.rom_ctrl_max_throughput_chk/latest |
| Test location | /workspace/coverage/default/37.rom_ctrl_smoke.3946268677 |
| Short name | T56 |
| Test name | |
| Test status | |
| Simulation time | 752899369 ps |
| CPU time | 10.47 seconds |
| Started | May 05 12:46:57 PM PDT 24 |
| Finished | May 05 12:47:08 PM PDT 24 |
| Peak memory | 213792 kb |
| Host | smart-c1adbe67-1c6c-4ee0-8304-9fcd3ab4a233 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3946268677 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_smoke.3946268677 |
| Directory | /workspace/37.rom_ctrl_smoke/latest |
| Test location | /workspace/coverage/default/37.rom_ctrl_stress_all.1956761293 |
| Short name | T273 |
| Test name | |
| Test status | |
| Simulation time | 34712220583 ps |
| CPU time | 92.28 seconds |
| Started | May 05 12:46:56 PM PDT 24 |
| Finished | May 05 12:48:29 PM PDT 24 |
| Peak memory | 218132 kb |
| Host | smart-580a654e-36bd-477e-8a0a-e00e0ed879cc |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1956761293 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm _name 37.rom_ctrl_stress_all.1956761293 |
| Directory | /workspace/37.rom_ctrl_stress_all/latest |
| Test location | /workspace/coverage/default/38.rom_ctrl_alert_test.906322273 |
| Short name | T146 |
| Test name | |
| Test status | |
| Simulation time | 403946529 ps |
| CPU time | 6.32 seconds |
| Started | May 05 12:46:58 PM PDT 24 |
| Finished | May 05 12:47:06 PM PDT 24 |
| Peak memory | 211580 kb |
| Host | smart-37460922-3892-4b3d-af70-c7a676cdf8d2 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=906322273 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_alert_test.906322273 |
| Directory | /workspace/38.rom_ctrl_alert_test/latest |
| Test location | /workspace/coverage/default/38.rom_ctrl_kmac_err_chk.120361681 |
| Short name | T240 |
| Test name | |
| Test status | |
| Simulation time | 3494459076 ps |
| CPU time | 29.41 seconds |
| Started | May 05 12:47:00 PM PDT 24 |
| Finished | May 05 12:47:30 PM PDT 24 |
| Peak memory | 212512 kb |
| Host | smart-71a219df-ae19-482c-80af-f00a56cde943 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=120361681 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_kmac_err_chk.120361681 |
| Directory | /workspace/38.rom_ctrl_kmac_err_chk/latest |
| Test location | /workspace/coverage/default/38.rom_ctrl_max_throughput_chk.673049664 |
| Short name | T327 |
| Test name | |
| Test status | |
| Simulation time | 173077683 ps |
| CPU time | 5.7 seconds |
| Started | May 05 12:46:58 PM PDT 24 |
| Finished | May 05 12:47:05 PM PDT 24 |
| Peak memory | 211512 kb |
| Host | smart-b3c1d927-ab41-48ce-8979-66b5263bb320 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=673049664 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_max_throughput_chk.673049664 |
| Directory | /workspace/38.rom_ctrl_max_throughput_chk/latest |
| Test location | /workspace/coverage/default/38.rom_ctrl_smoke.3286910706 |
| Short name | T68 |
| Test name | |
| Test status | |
| Simulation time | 14419048670 ps |
| CPU time | 34.74 seconds |
| Started | May 05 12:46:56 PM PDT 24 |
| Finished | May 05 12:47:31 PM PDT 24 |
| Peak memory | 214724 kb |
| Host | smart-dc4ad5ae-6604-47eb-8cc8-840eb7b6a957 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3286910706 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_smoke.3286910706 |
| Directory | /workspace/38.rom_ctrl_smoke/latest |
| Test location | /workspace/coverage/default/38.rom_ctrl_stress_all.2011342220 |
| Short name | T179 |
| Test name | |
| Test status | |
| Simulation time | 983691684 ps |
| CPU time | 34.95 seconds |
| Started | May 05 12:46:57 PM PDT 24 |
| Finished | May 05 12:47:33 PM PDT 24 |
| Peak memory | 215084 kb |
| Host | smart-800e9cb2-ccdb-4ba2-9b7e-ddc306e48414 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2011342220 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm _name 38.rom_ctrl_stress_all.2011342220 |
| Directory | /workspace/38.rom_ctrl_stress_all/latest |
| Test location | /workspace/coverage/default/39.rom_ctrl_alert_test.562808723 |
| Short name | T206 |
| Test name | |
| Test status | |
| Simulation time | 2087431029 ps |
| CPU time | 15.96 seconds |
| Started | May 05 12:47:00 PM PDT 24 |
| Finished | May 05 12:47:17 PM PDT 24 |
| Peak memory | 211668 kb |
| Host | smart-eef5f57a-a4d5-4178-9fe3-84ef9e0bc9dd |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=562808723 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_alert_test.562808723 |
| Directory | /workspace/39.rom_ctrl_alert_test/latest |
| Test location | /workspace/coverage/default/39.rom_ctrl_corrupt_sig_fatal_chk.1964375284 |
| Short name | T334 |
| Test name | |
| Test status | |
| Simulation time | 3691222866 ps |
| CPU time | 63.51 seconds |
| Started | May 05 12:46:59 PM PDT 24 |
| Finished | May 05 12:48:03 PM PDT 24 |
| Peak memory | 213128 kb |
| Host | smart-e1398ed1-7181-4b22-8e7c-c452c2662de6 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1964375284 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_ corrupt_sig_fatal_chk.1964375284 |
| Directory | /workspace/39.rom_ctrl_corrupt_sig_fatal_chk/latest |
| Test location | /workspace/coverage/default/39.rom_ctrl_kmac_err_chk.3598956750 |
| Short name | T269 |
| Test name | |
| Test status | |
| Simulation time | 12913013558 ps |
| CPU time | 29.42 seconds |
| Started | May 05 12:47:00 PM PDT 24 |
| Finished | May 05 12:47:30 PM PDT 24 |
| Peak memory | 212748 kb |
| Host | smart-b269aa8b-7a3a-452b-af57-27610153e0db |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3598956750 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_kmac_err_chk.3598956750 |
| Directory | /workspace/39.rom_ctrl_kmac_err_chk/latest |
| Test location | /workspace/coverage/default/39.rom_ctrl_max_throughput_chk.1587805449 |
| Short name | T97 |
| Test name | |
| Test status | |
| Simulation time | 2027310002 ps |
| CPU time | 11.43 seconds |
| Started | May 05 12:47:06 PM PDT 24 |
| Finished | May 05 12:47:18 PM PDT 24 |
| Peak memory | 211620 kb |
| Host | smart-937b4330-f649-401d-84d1-5dfa67958db9 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1587805449 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_max_throughput_chk.1587805449 |
| Directory | /workspace/39.rom_ctrl_max_throughput_chk/latest |
| Test location | /workspace/coverage/default/39.rom_ctrl_smoke.3336977177 |
| Short name | T70 |
| Test name | |
| Test status | |
| Simulation time | 3595337376 ps |
| CPU time | 31.77 seconds |
| Started | May 05 12:47:07 PM PDT 24 |
| Finished | May 05 12:47:40 PM PDT 24 |
| Peak memory | 219968 kb |
| Host | smart-762ec974-1f1c-42f9-8615-253eb84a7766 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3336977177 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_smoke.3336977177 |
| Directory | /workspace/39.rom_ctrl_smoke/latest |
| Test location | /workspace/coverage/default/39.rom_ctrl_stress_all.1517611302 |
| Short name | T95 |
| Test name | |
| Test status | |
| Simulation time | 14862615581 ps |
| CPU time | 38.1 seconds |
| Started | May 05 12:47:06 PM PDT 24 |
| Finished | May 05 12:47:45 PM PDT 24 |
| Peak memory | 219764 kb |
| Host | smart-854982ac-a403-49ce-8fdb-5129c43cde76 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1517611302 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm _name 39.rom_ctrl_stress_all.1517611302 |
| Directory | /workspace/39.rom_ctrl_stress_all/latest |
| Test location | /workspace/coverage/default/39.rom_ctrl_stress_all_with_rand_reset.953684589 |
| Short name | T41 |
| Test name | |
| Test status | |
| Simulation time | 190294549160 ps |
| CPU time | 1928.04 seconds |
| Started | May 05 12:47:03 PM PDT 24 |
| Finished | May 05 01:19:12 PM PDT 24 |
| Peak memory | 248400 kb |
| Host | smart-87f0a2b3-cdca-4862-b6d8-aaa59cfb7f79 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=953684589 -assert nopo stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera ge/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_stress_all_with_rand_reset.953684589 |
| Directory | /workspace/39.rom_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/4.rom_ctrl_alert_test.3842422283 |
| Short name | T370 |
| Test name | |
| Test status | |
| Simulation time | 4209090444 ps |
| CPU time | 16.47 seconds |
| Started | May 05 12:46:14 PM PDT 24 |
| Finished | May 05 12:46:31 PM PDT 24 |
| Peak memory | 211784 kb |
| Host | smart-4bf5b99f-124e-4f14-b271-dcbd93504de1 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3842422283 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_alert_test.3842422283 |
| Directory | /workspace/4.rom_ctrl_alert_test/latest |
| Test location | /workspace/coverage/default/4.rom_ctrl_corrupt_sig_fatal_chk.1415795822 |
| Short name | T221 |
| Test name | |
| Test status | |
| Simulation time | 87702562199 ps |
| CPU time | 214.56 seconds |
| Started | May 05 12:46:14 PM PDT 24 |
| Finished | May 05 12:49:50 PM PDT 24 |
| Peak memory | 228796 kb |
| Host | smart-0cec47fe-558e-4853-96ef-6df2217a279d |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1415795822 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_c orrupt_sig_fatal_chk.1415795822 |
| Directory | /workspace/4.rom_ctrl_corrupt_sig_fatal_chk/latest |
| Test location | /workspace/coverage/default/4.rom_ctrl_kmac_err_chk.3884904743 |
| Short name | T361 |
| Test name | |
| Test status | |
| Simulation time | 11589770138 ps |
| CPU time | 25.99 seconds |
| Started | May 05 12:46:14 PM PDT 24 |
| Finished | May 05 12:46:41 PM PDT 24 |
| Peak memory | 212620 kb |
| Host | smart-5e83f3fb-8949-4386-8d19-b776df3254e2 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3884904743 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_kmac_err_chk.3884904743 |
| Directory | /workspace/4.rom_ctrl_kmac_err_chk/latest |
| Test location | /workspace/coverage/default/4.rom_ctrl_max_throughput_chk.3385841260 |
| Short name | T204 |
| Test name | |
| Test status | |
| Simulation time | 2950225170 ps |
| CPU time | 9.89 seconds |
| Started | May 05 12:46:03 PM PDT 24 |
| Finished | May 05 12:46:14 PM PDT 24 |
| Peak memory | 211720 kb |
| Host | smart-1b7682ba-e359-4df7-b6da-41279aa298e6 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3385841260 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_max_throughput_chk.3385841260 |
| Directory | /workspace/4.rom_ctrl_max_throughput_chk/latest |
| Test location | /workspace/coverage/default/4.rom_ctrl_sec_cm.2475496685 |
| Short name | T36 |
| Test name | |
| Test status | |
| Simulation time | 2998508581 ps |
| CPU time | 102.49 seconds |
| Started | May 05 12:46:06 PM PDT 24 |
| Finished | May 05 12:47:49 PM PDT 24 |
| Peak memory | 231572 kb |
| Host | smart-c7d6038e-34fe-4f07-aabc-e376e56012d1 |
| User | root |
| Command | /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2475496685 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_sec_cm.2475496685 |
| Directory | /workspace/4.rom_ctrl_sec_cm/latest |
| Test location | /workspace/coverage/default/4.rom_ctrl_smoke.2745310656 |
| Short name | T27 |
| Test name | |
| Test status | |
| Simulation time | 6237562820 ps |
| CPU time | 31.34 seconds |
| Started | May 05 12:46:15 PM PDT 24 |
| Finished | May 05 12:46:48 PM PDT 24 |
| Peak memory | 219980 kb |
| Host | smart-43d10a5c-6936-4925-a3e1-b489a9ed599f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2745310656 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_smoke.2745310656 |
| Directory | /workspace/4.rom_ctrl_smoke/latest |
| Test location | /workspace/coverage/default/4.rom_ctrl_stress_all.2537247603 |
| Short name | T228 |
| Test name | |
| Test status | |
| Simulation time | 380588676 ps |
| CPU time | 15.57 seconds |
| Started | May 05 12:46:15 PM PDT 24 |
| Finished | May 05 12:46:32 PM PDT 24 |
| Peak memory | 213520 kb |
| Host | smart-3b0674c8-9675-4eba-96d7-f7c2b3ce9a33 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2537247603 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm _name 4.rom_ctrl_stress_all.2537247603 |
| Directory | /workspace/4.rom_ctrl_stress_all/latest |
| Test location | /workspace/coverage/default/40.rom_ctrl_alert_test.114610883 |
| Short name | T128 |
| Test name | |
| Test status | |
| Simulation time | 1838307753 ps |
| CPU time | 9.97 seconds |
| Started | May 05 12:47:04 PM PDT 24 |
| Finished | May 05 12:47:14 PM PDT 24 |
| Peak memory | 211672 kb |
| Host | smart-874810c7-f6a9-4cd9-aea7-794a6fc59fd0 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=114610883 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_alert_test.114610883 |
| Directory | /workspace/40.rom_ctrl_alert_test/latest |
| Test location | /workspace/coverage/default/40.rom_ctrl_corrupt_sig_fatal_chk.3830638102 |
| Short name | T38 |
| Test name | |
| Test status | |
| Simulation time | 96466527220 ps |
| CPU time | 242.98 seconds |
| Started | May 05 12:46:58 PM PDT 24 |
| Finished | May 05 12:51:02 PM PDT 24 |
| Peak memory | 237360 kb |
| Host | smart-ddcfd19b-9b78-42d9-95b6-79c0f728a388 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3830638102 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_ corrupt_sig_fatal_chk.3830638102 |
| Directory | /workspace/40.rom_ctrl_corrupt_sig_fatal_chk/latest |
| Test location | /workspace/coverage/default/40.rom_ctrl_kmac_err_chk.276833444 |
| Short name | T288 |
| Test name | |
| Test status | |
| Simulation time | 3138102876 ps |
| CPU time | 19.64 seconds |
| Started | May 05 12:47:05 PM PDT 24 |
| Finished | May 05 12:47:26 PM PDT 24 |
| Peak memory | 212284 kb |
| Host | smart-a22c2567-2e18-4839-bcbe-c90fa404ed8f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=276833444 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_kmac_err_chk.276833444 |
| Directory | /workspace/40.rom_ctrl_kmac_err_chk/latest |
| Test location | /workspace/coverage/default/40.rom_ctrl_max_throughput_chk.2176911659 |
| Short name | T205 |
| Test name | |
| Test status | |
| Simulation time | 1459705166 ps |
| CPU time | 13.92 seconds |
| Started | May 05 12:47:06 PM PDT 24 |
| Finished | May 05 12:47:21 PM PDT 24 |
| Peak memory | 211496 kb |
| Host | smart-55498185-f706-41a9-8d99-1a601f83d65e |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2176911659 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_max_throughput_chk.2176911659 |
| Directory | /workspace/40.rom_ctrl_max_throughput_chk/latest |
| Test location | /workspace/coverage/default/40.rom_ctrl_smoke.806414080 |
| Short name | T193 |
| Test name | |
| Test status | |
| Simulation time | 2949758977 ps |
| CPU time | 33.35 seconds |
| Started | May 05 12:47:01 PM PDT 24 |
| Finished | May 05 12:47:35 PM PDT 24 |
| Peak memory | 213576 kb |
| Host | smart-2ef84fc7-0121-4c6e-aa8f-055681499cc2 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=806414080 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_smoke.806414080 |
| Directory | /workspace/40.rom_ctrl_smoke/latest |
| Test location | /workspace/coverage/default/40.rom_ctrl_stress_all.183621691 |
| Short name | T299 |
| Test name | |
| Test status | |
| Simulation time | 12793859944 ps |
| CPU time | 49.68 seconds |
| Started | May 05 12:47:00 PM PDT 24 |
| Finished | May 05 12:47:50 PM PDT 24 |
| Peak memory | 219928 kb |
| Host | smart-1cc32c4d-4a79-4293-b79d-f81905266208 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=183621691 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test + UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 40.rom_ctrl_stress_all.183621691 |
| Directory | /workspace/40.rom_ctrl_stress_all/latest |
| Test location | /workspace/coverage/default/41.rom_ctrl_alert_test.4187891433 |
| Short name | T171 |
| Test name | |
| Test status | |
| Simulation time | 20420696301 ps |
| CPU time | 16.09 seconds |
| Started | May 05 12:47:07 PM PDT 24 |
| Finished | May 05 12:47:24 PM PDT 24 |
| Peak memory | 211768 kb |
| Host | smart-c3ff989f-4708-44f7-a2f0-a07c879e6317 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4187891433 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_alert_test.4187891433 |
| Directory | /workspace/41.rom_ctrl_alert_test/latest |
| Test location | /workspace/coverage/default/41.rom_ctrl_corrupt_sig_fatal_chk.3483710731 |
| Short name | T108 |
| Test name | |
| Test status | |
| Simulation time | 15512864704 ps |
| CPU time | 165.91 seconds |
| Started | May 05 12:46:59 PM PDT 24 |
| Finished | May 05 12:49:46 PM PDT 24 |
| Peak memory | 225692 kb |
| Host | smart-54bcd27e-2fed-4e47-823a-43a53668841e |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3483710731 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_ corrupt_sig_fatal_chk.3483710731 |
| Directory | /workspace/41.rom_ctrl_corrupt_sig_fatal_chk/latest |
| Test location | /workspace/coverage/default/41.rom_ctrl_kmac_err_chk.3704000881 |
| Short name | T183 |
| Test name | |
| Test status | |
| Simulation time | 3077018327 ps |
| CPU time | 14.22 seconds |
| Started | May 05 12:46:58 PM PDT 24 |
| Finished | May 05 12:47:13 PM PDT 24 |
| Peak memory | 211832 kb |
| Host | smart-78de08d6-56fd-4392-862c-4be56154012f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3704000881 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_kmac_err_chk.3704000881 |
| Directory | /workspace/41.rom_ctrl_kmac_err_chk/latest |
| Test location | /workspace/coverage/default/41.rom_ctrl_max_throughput_chk.1778387041 |
| Short name | T341 |
| Test name | |
| Test status | |
| Simulation time | 4132732537 ps |
| CPU time | 9.45 seconds |
| Started | May 05 12:47:10 PM PDT 24 |
| Finished | May 05 12:47:20 PM PDT 24 |
| Peak memory | 211740 kb |
| Host | smart-082159d1-a152-4945-a65c-04d032f17b5e |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1778387041 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_max_throughput_chk.1778387041 |
| Directory | /workspace/41.rom_ctrl_max_throughput_chk/latest |
| Test location | /workspace/coverage/default/41.rom_ctrl_smoke.3160458016 |
| Short name | T73 |
| Test name | |
| Test status | |
| Simulation time | 3584865384 ps |
| CPU time | 27.32 seconds |
| Started | May 05 12:46:59 PM PDT 24 |
| Finished | May 05 12:47:27 PM PDT 24 |
| Peak memory | 219956 kb |
| Host | smart-1e0e5e2e-30ac-4d65-9f03-ce197d30bf1c |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3160458016 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_smoke.3160458016 |
| Directory | /workspace/41.rom_ctrl_smoke/latest |
| Test location | /workspace/coverage/default/41.rom_ctrl_stress_all.189135988 |
| Short name | T233 |
| Test name | |
| Test status | |
| Simulation time | 1511249187 ps |
| CPU time | 21.18 seconds |
| Started | May 05 12:47:04 PM PDT 24 |
| Finished | May 05 12:47:26 PM PDT 24 |
| Peak memory | 215196 kb |
| Host | smart-21a9527e-65c7-4bb3-bc3c-b63ed0f64237 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=189135988 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test + UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 41.rom_ctrl_stress_all.189135988 |
| Directory | /workspace/41.rom_ctrl_stress_all/latest |
| Test location | /workspace/coverage/default/42.rom_ctrl_alert_test.3736137547 |
| Short name | T218 |
| Test name | |
| Test status | |
| Simulation time | 15915841682 ps |
| CPU time | 14.03 seconds |
| Started | May 05 12:47:06 PM PDT 24 |
| Finished | May 05 12:47:21 PM PDT 24 |
| Peak memory | 211728 kb |
| Host | smart-e0b40834-804f-4392-acd8-42eccb9de597 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3736137547 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_alert_test.3736137547 |
| Directory | /workspace/42.rom_ctrl_alert_test/latest |
| Test location | /workspace/coverage/default/42.rom_ctrl_corrupt_sig_fatal_chk.3055410312 |
| Short name | T263 |
| Test name | |
| Test status | |
| Simulation time | 1340796515 ps |
| CPU time | 89.93 seconds |
| Started | May 05 12:47:05 PM PDT 24 |
| Finished | May 05 12:48:36 PM PDT 24 |
| Peak memory | 236928 kb |
| Host | smart-4803f078-0962-4707-a132-44117d4221a6 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3055410312 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_ corrupt_sig_fatal_chk.3055410312 |
| Directory | /workspace/42.rom_ctrl_corrupt_sig_fatal_chk/latest |
| Test location | /workspace/coverage/default/42.rom_ctrl_kmac_err_chk.1563663708 |
| Short name | T261 |
| Test name | |
| Test status | |
| Simulation time | 6456916469 ps |
| CPU time | 18.96 seconds |
| Started | May 05 12:47:07 PM PDT 24 |
| Finished | May 05 12:47:27 PM PDT 24 |
| Peak memory | 211808 kb |
| Host | smart-f365637d-4f22-4607-804d-cd3b388a2a65 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1563663708 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_kmac_err_chk.1563663708 |
| Directory | /workspace/42.rom_ctrl_kmac_err_chk/latest |
| Test location | /workspace/coverage/default/42.rom_ctrl_max_throughput_chk.1433856624 |
| Short name | T345 |
| Test name | |
| Test status | |
| Simulation time | 1752242822 ps |
| CPU time | 8.29 seconds |
| Started | May 05 12:47:08 PM PDT 24 |
| Finished | May 05 12:47:17 PM PDT 24 |
| Peak memory | 211596 kb |
| Host | smart-e0050680-13de-4e14-9f27-9b749187043d |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1433856624 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_max_throughput_chk.1433856624 |
| Directory | /workspace/42.rom_ctrl_max_throughput_chk/latest |
| Test location | /workspace/coverage/default/42.rom_ctrl_smoke.661899724 |
| Short name | T188 |
| Test name | |
| Test status | |
| Simulation time | 4422006387 ps |
| CPU time | 34.35 seconds |
| Started | May 05 12:47:03 PM PDT 24 |
| Finished | May 05 12:47:38 PM PDT 24 |
| Peak memory | 214248 kb |
| Host | smart-37ba3473-0e35-49de-afd0-36fd49312273 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=661899724 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_smoke.661899724 |
| Directory | /workspace/42.rom_ctrl_smoke/latest |
| Test location | /workspace/coverage/default/42.rom_ctrl_stress_all.1468048184 |
| Short name | T314 |
| Test name | |
| Test status | |
| Simulation time | 3722592945 ps |
| CPU time | 18.63 seconds |
| Started | May 05 12:47:05 PM PDT 24 |
| Finished | May 05 12:47:24 PM PDT 24 |
| Peak memory | 211588 kb |
| Host | smart-ebfd5d9a-b830-4345-8c89-314c4825ec9b |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1468048184 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm _name 42.rom_ctrl_stress_all.1468048184 |
| Directory | /workspace/42.rom_ctrl_stress_all/latest |
| Test location | /workspace/coverage/default/43.rom_ctrl_alert_test.497615328 |
| Short name | T237 |
| Test name | |
| Test status | |
| Simulation time | 4453817724 ps |
| CPU time | 11.65 seconds |
| Started | May 05 12:47:05 PM PDT 24 |
| Finished | May 05 12:47:17 PM PDT 24 |
| Peak memory | 211788 kb |
| Host | smart-dda0cf36-2b4c-44eb-95d3-d3f5cd29f4d4 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=497615328 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_alert_test.497615328 |
| Directory | /workspace/43.rom_ctrl_alert_test/latest |
| Test location | /workspace/coverage/default/43.rom_ctrl_corrupt_sig_fatal_chk.3776598879 |
| Short name | T326 |
| Test name | |
| Test status | |
| Simulation time | 156677589039 ps |
| CPU time | 418.35 seconds |
| Started | May 05 12:47:07 PM PDT 24 |
| Finished | May 05 12:54:06 PM PDT 24 |
| Peak memory | 237256 kb |
| Host | smart-e043a6e4-8d8d-4ca3-9ac7-ec1ecda914f6 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3776598879 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_ corrupt_sig_fatal_chk.3776598879 |
| Directory | /workspace/43.rom_ctrl_corrupt_sig_fatal_chk/latest |
| Test location | /workspace/coverage/default/43.rom_ctrl_kmac_err_chk.339222246 |
| Short name | T127 |
| Test name | |
| Test status | |
| Simulation time | 2078460584 ps |
| CPU time | 21.71 seconds |
| Started | May 05 12:47:08 PM PDT 24 |
| Finished | May 05 12:47:30 PM PDT 24 |
| Peak memory | 211720 kb |
| Host | smart-c257a732-1e65-41a9-9761-b750469441a9 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=339222246 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_kmac_err_chk.339222246 |
| Directory | /workspace/43.rom_ctrl_kmac_err_chk/latest |
| Test location | /workspace/coverage/default/43.rom_ctrl_max_throughput_chk.1844123744 |
| Short name | T312 |
| Test name | |
| Test status | |
| Simulation time | 1210546420 ps |
| CPU time | 12.32 seconds |
| Started | May 05 12:47:10 PM PDT 24 |
| Finished | May 05 12:47:23 PM PDT 24 |
| Peak memory | 211556 kb |
| Host | smart-96ded917-ba16-41f5-a49a-603bba7647cc |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1844123744 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_max_throughput_chk.1844123744 |
| Directory | /workspace/43.rom_ctrl_max_throughput_chk/latest |
| Test location | /workspace/coverage/default/43.rom_ctrl_smoke.3116432479 |
| Short name | T214 |
| Test name | |
| Test status | |
| Simulation time | 4036890927 ps |
| CPU time | 33 seconds |
| Started | May 05 12:47:06 PM PDT 24 |
| Finished | May 05 12:47:40 PM PDT 24 |
| Peak memory | 219964 kb |
| Host | smart-5f2c6525-42b7-43cf-a58b-aaf6dd2844d7 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3116432479 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_smoke.3116432479 |
| Directory | /workspace/43.rom_ctrl_smoke/latest |
| Test location | /workspace/coverage/default/43.rom_ctrl_stress_all.4179845558 |
| Short name | T223 |
| Test name | |
| Test status | |
| Simulation time | 6433704332 ps |
| CPU time | 58.66 seconds |
| Started | May 05 12:47:04 PM PDT 24 |
| Finished | May 05 12:48:03 PM PDT 24 |
| Peak memory | 219924 kb |
| Host | smart-b1f9e16c-bc9d-4ff9-aa1c-842f5a408797 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4179845558 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm _name 43.rom_ctrl_stress_all.4179845558 |
| Directory | /workspace/43.rom_ctrl_stress_all/latest |
| Test location | /workspace/coverage/default/43.rom_ctrl_stress_all_with_rand_reset.1202549871 |
| Short name | T270 |
| Test name | |
| Test status | |
| Simulation time | 201856046832 ps |
| CPU time | 2129.04 seconds |
| Started | May 05 12:47:08 PM PDT 24 |
| Finished | May 05 01:22:38 PM PDT 24 |
| Peak memory | 228936 kb |
| Host | smart-93917023-ebfc-423d-9465-5e3a55f9ead0 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1202549871 -assert nop ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_stress_all_with_rand_reset.1202549871 |
| Directory | /workspace/43.rom_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/44.rom_ctrl_alert_test.2637203260 |
| Short name | T169 |
| Test name | |
| Test status | |
| Simulation time | 1565539893 ps |
| CPU time | 13.46 seconds |
| Started | May 05 12:47:03 PM PDT 24 |
| Finished | May 05 12:47:17 PM PDT 24 |
| Peak memory | 211652 kb |
| Host | smart-7607915d-2368-4c1b-ae2c-27fa28dec82a |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2637203260 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_alert_test.2637203260 |
| Directory | /workspace/44.rom_ctrl_alert_test/latest |
| Test location | /workspace/coverage/default/44.rom_ctrl_corrupt_sig_fatal_chk.2181479395 |
| Short name | T211 |
| Test name | |
| Test status | |
| Simulation time | 989092493 ps |
| CPU time | 71.49 seconds |
| Started | May 05 12:47:07 PM PDT 24 |
| Finished | May 05 12:48:20 PM PDT 24 |
| Peak memory | 228760 kb |
| Host | smart-9eb59d37-b1c7-497e-a231-06d69a2eae4a |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2181479395 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_ corrupt_sig_fatal_chk.2181479395 |
| Directory | /workspace/44.rom_ctrl_corrupt_sig_fatal_chk/latest |
| Test location | /workspace/coverage/default/44.rom_ctrl_kmac_err_chk.3586124581 |
| Short name | T344 |
| Test name | |
| Test status | |
| Simulation time | 3401135061 ps |
| CPU time | 28.7 seconds |
| Started | May 05 12:47:07 PM PDT 24 |
| Finished | May 05 12:47:37 PM PDT 24 |
| Peak memory | 212492 kb |
| Host | smart-154a8e4b-dfd5-400d-a0ab-7a9301ba77b2 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3586124581 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_kmac_err_chk.3586124581 |
| Directory | /workspace/44.rom_ctrl_kmac_err_chk/latest |
| Test location | /workspace/coverage/default/44.rom_ctrl_max_throughput_chk.1459686110 |
| Short name | T272 |
| Test name | |
| Test status | |
| Simulation time | 1207800238 ps |
| CPU time | 11.91 seconds |
| Started | May 05 12:47:06 PM PDT 24 |
| Finished | May 05 12:47:19 PM PDT 24 |
| Peak memory | 211620 kb |
| Host | smart-33cbaa51-43c5-44e6-820e-5f13e115c478 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1459686110 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_max_throughput_chk.1459686110 |
| Directory | /workspace/44.rom_ctrl_max_throughput_chk/latest |
| Test location | /workspace/coverage/default/44.rom_ctrl_smoke.3472973182 |
| Short name | T157 |
| Test name | |
| Test status | |
| Simulation time | 13903233099 ps |
| CPU time | 29.02 seconds |
| Started | May 05 12:47:06 PM PDT 24 |
| Finished | May 05 12:47:36 PM PDT 24 |
| Peak memory | 214840 kb |
| Host | smart-584a45af-5c71-45e4-b202-c4b3d2668b7b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3472973182 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_smoke.3472973182 |
| Directory | /workspace/44.rom_ctrl_smoke/latest |
| Test location | /workspace/coverage/default/44.rom_ctrl_stress_all.952106001 |
| Short name | T325 |
| Test name | |
| Test status | |
| Simulation time | 808890741 ps |
| CPU time | 22.04 seconds |
| Started | May 05 12:47:06 PM PDT 24 |
| Finished | May 05 12:47:29 PM PDT 24 |
| Peak memory | 219764 kb |
| Host | smart-a092207b-908c-4230-9252-c6573b60198e |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=952106001 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test + UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 44.rom_ctrl_stress_all.952106001 |
| Directory | /workspace/44.rom_ctrl_stress_all/latest |
| Test location | /workspace/coverage/default/45.rom_ctrl_alert_test.4244451422 |
| Short name | T2 |
| Test name | |
| Test status | |
| Simulation time | 1587292857 ps |
| CPU time | 9.03 seconds |
| Started | May 05 12:47:08 PM PDT 24 |
| Finished | May 05 12:47:18 PM PDT 24 |
| Peak memory | 211672 kb |
| Host | smart-2270a57f-91fc-4d30-bd6b-98d5208159d0 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4244451422 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_alert_test.4244451422 |
| Directory | /workspace/45.rom_ctrl_alert_test/latest |
| Test location | /workspace/coverage/default/45.rom_ctrl_corrupt_sig_fatal_chk.2849126926 |
| Short name | T175 |
| Test name | |
| Test status | |
| Simulation time | 157703205484 ps |
| CPU time | 384.21 seconds |
| Started | May 05 12:47:06 PM PDT 24 |
| Finished | May 05 12:53:31 PM PDT 24 |
| Peak memory | 230048 kb |
| Host | smart-9f2fad0a-1725-4147-819c-778e90911b92 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2849126926 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_ corrupt_sig_fatal_chk.2849126926 |
| Directory | /workspace/45.rom_ctrl_corrupt_sig_fatal_chk/latest |
| Test location | /workspace/coverage/default/45.rom_ctrl_kmac_err_chk.4177351934 |
| Short name | T96 |
| Test name | |
| Test status | |
| Simulation time | 4112097265 ps |
| CPU time | 33.62 seconds |
| Started | May 05 12:47:10 PM PDT 24 |
| Finished | May 05 12:47:44 PM PDT 24 |
| Peak memory | 212512 kb |
| Host | smart-ef693b4a-2908-496a-9a8b-ada11770a149 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4177351934 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_kmac_err_chk.4177351934 |
| Directory | /workspace/45.rom_ctrl_kmac_err_chk/latest |
| Test location | /workspace/coverage/default/45.rom_ctrl_max_throughput_chk.2718032663 |
| Short name | T281 |
| Test name | |
| Test status | |
| Simulation time | 382955632 ps |
| CPU time | 5.85 seconds |
| Started | May 05 12:47:10 PM PDT 24 |
| Finished | May 05 12:47:17 PM PDT 24 |
| Peak memory | 211796 kb |
| Host | smart-5dff0da0-78ed-4a99-9ae7-81d58b5ecb93 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2718032663 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_max_throughput_chk.2718032663 |
| Directory | /workspace/45.rom_ctrl_max_throughput_chk/latest |
| Test location | /workspace/coverage/default/45.rom_ctrl_smoke.2817386175 |
| Short name | T276 |
| Test name | |
| Test status | |
| Simulation time | 447404445 ps |
| CPU time | 13.35 seconds |
| Started | May 05 12:47:03 PM PDT 24 |
| Finished | May 05 12:47:17 PM PDT 24 |
| Peak memory | 213520 kb |
| Host | smart-1cd6e2c5-c6e9-4988-b4ca-67ebf0f692d3 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2817386175 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_smoke.2817386175 |
| Directory | /workspace/45.rom_ctrl_smoke/latest |
| Test location | /workspace/coverage/default/45.rom_ctrl_stress_all.3398715195 |
| Short name | T321 |
| Test name | |
| Test status | |
| Simulation time | 4375200720 ps |
| CPU time | 44.79 seconds |
| Started | May 05 12:47:10 PM PDT 24 |
| Finished | May 05 12:47:56 PM PDT 24 |
| Peak memory | 214384 kb |
| Host | smart-6675fc4e-6599-40d6-9d22-d45a0af128c6 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3398715195 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm _name 45.rom_ctrl_stress_all.3398715195 |
| Directory | /workspace/45.rom_ctrl_stress_all/latest |
| Test location | /workspace/coverage/default/45.rom_ctrl_stress_all_with_rand_reset.3629686583 |
| Short name | T332 |
| Test name | |
| Test status | |
| Simulation time | 144137831480 ps |
| CPU time | 1998.38 seconds |
| Started | May 05 12:47:11 PM PDT 24 |
| Finished | May 05 01:20:31 PM PDT 24 |
| Peak memory | 236396 kb |
| Host | smart-c961f50e-fa44-4617-881f-150d8b40ce63 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3629686583 -assert nop ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_stress_all_with_rand_reset.3629686583 |
| Directory | /workspace/45.rom_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/46.rom_ctrl_alert_test.3449333874 |
| Short name | T8 |
| Test name | |
| Test status | |
| Simulation time | 1145104799 ps |
| CPU time | 10.71 seconds |
| Started | May 05 12:47:13 PM PDT 24 |
| Finished | May 05 12:47:24 PM PDT 24 |
| Peak memory | 211648 kb |
| Host | smart-35afee66-3752-4753-bf8a-dc61ef522bc1 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3449333874 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_alert_test.3449333874 |
| Directory | /workspace/46.rom_ctrl_alert_test/latest |
| Test location | /workspace/coverage/default/46.rom_ctrl_kmac_err_chk.3761190578 |
| Short name | T24 |
| Test name | |
| Test status | |
| Simulation time | 340578615 ps |
| CPU time | 9.36 seconds |
| Started | May 05 12:47:10 PM PDT 24 |
| Finished | May 05 12:47:20 PM PDT 24 |
| Peak memory | 212304 kb |
| Host | smart-cbf497b1-122b-4dbe-a7cf-c6f7a26baa85 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3761190578 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_kmac_err_chk.3761190578 |
| Directory | /workspace/46.rom_ctrl_kmac_err_chk/latest |
| Test location | /workspace/coverage/default/46.rom_ctrl_max_throughput_chk.1823348859 |
| Short name | T91 |
| Test name | |
| Test status | |
| Simulation time | 5169647573 ps |
| CPU time | 9.73 seconds |
| Started | May 05 12:47:10 PM PDT 24 |
| Finished | May 05 12:47:21 PM PDT 24 |
| Peak memory | 211692 kb |
| Host | smart-56590361-1cf8-4cec-8ce4-fcd5016772bc |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1823348859 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_max_throughput_chk.1823348859 |
| Directory | /workspace/46.rom_ctrl_max_throughput_chk/latest |
| Test location | /workspace/coverage/default/46.rom_ctrl_smoke.964509923 |
| Short name | T350 |
| Test name | |
| Test status | |
| Simulation time | 1046577947 ps |
| CPU time | 11.86 seconds |
| Started | May 05 12:47:12 PM PDT 24 |
| Finished | May 05 12:47:24 PM PDT 24 |
| Peak memory | 213308 kb |
| Host | smart-d66081ec-5704-40fe-a7da-1dfa3a826280 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=964509923 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_smoke.964509923 |
| Directory | /workspace/46.rom_ctrl_smoke/latest |
| Test location | /workspace/coverage/default/46.rom_ctrl_stress_all.1569942656 |
| Short name | T67 |
| Test name | |
| Test status | |
| Simulation time | 966944058 ps |
| CPU time | 9.75 seconds |
| Started | May 05 12:47:11 PM PDT 24 |
| Finished | May 05 12:47:21 PM PDT 24 |
| Peak memory | 212452 kb |
| Host | smart-ef1c045e-9685-436a-a9b6-ef9e48b3c666 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1569942656 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm _name 46.rom_ctrl_stress_all.1569942656 |
| Directory | /workspace/46.rom_ctrl_stress_all/latest |
| Test location | /workspace/coverage/default/47.rom_ctrl_alert_test.3886210625 |
| Short name | T131 |
| Test name | |
| Test status | |
| Simulation time | 1142229759 ps |
| CPU time | 9.94 seconds |
| Started | May 05 12:47:14 PM PDT 24 |
| Finished | May 05 12:47:25 PM PDT 24 |
| Peak memory | 211644 kb |
| Host | smart-7b6e71bd-2c31-4e07-aace-e177be0cc4a6 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3886210625 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_alert_test.3886210625 |
| Directory | /workspace/47.rom_ctrl_alert_test/latest |
| Test location | /workspace/coverage/default/47.rom_ctrl_corrupt_sig_fatal_chk.636320132 |
| Short name | T339 |
| Test name | |
| Test status | |
| Simulation time | 2440373964 ps |
| CPU time | 151.56 seconds |
| Started | May 05 12:47:13 PM PDT 24 |
| Finished | May 05 12:49:45 PM PDT 24 |
| Peak memory | 213300 kb |
| Host | smart-67fa37ce-91fb-4b25-a649-f14a90336899 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=636320132 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt _sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_c orrupt_sig_fatal_chk.636320132 |
| Directory | /workspace/47.rom_ctrl_corrupt_sig_fatal_chk/latest |
| Test location | /workspace/coverage/default/47.rom_ctrl_kmac_err_chk.1482501677 |
| Short name | T241 |
| Test name | |
| Test status | |
| Simulation time | 2845660599 ps |
| CPU time | 24.92 seconds |
| Started | May 05 12:47:10 PM PDT 24 |
| Finished | May 05 12:47:36 PM PDT 24 |
| Peak memory | 212332 kb |
| Host | smart-f5526df7-0951-4344-b3dd-8eeb16a2aa8e |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1482501677 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_kmac_err_chk.1482501677 |
| Directory | /workspace/47.rom_ctrl_kmac_err_chk/latest |
| Test location | /workspace/coverage/default/47.rom_ctrl_max_throughput_chk.1294523815 |
| Short name | T132 |
| Test name | |
| Test status | |
| Simulation time | 2229171351 ps |
| CPU time | 17.07 seconds |
| Started | May 05 12:47:08 PM PDT 24 |
| Finished | May 05 12:47:26 PM PDT 24 |
| Peak memory | 211760 kb |
| Host | smart-8ef0f910-4552-48b5-905c-fd8481a5a6a3 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1294523815 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_max_throughput_chk.1294523815 |
| Directory | /workspace/47.rom_ctrl_max_throughput_chk/latest |
| Test location | /workspace/coverage/default/47.rom_ctrl_smoke.2591973093 |
| Short name | T360 |
| Test name | |
| Test status | |
| Simulation time | 4133034566 ps |
| CPU time | 18.79 seconds |
| Started | May 05 12:47:10 PM PDT 24 |
| Finished | May 05 12:47:29 PM PDT 24 |
| Peak memory | 212112 kb |
| Host | smart-7185742a-ecd5-48fc-a841-ab97aa11117b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2591973093 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_smoke.2591973093 |
| Directory | /workspace/47.rom_ctrl_smoke/latest |
| Test location | /workspace/coverage/default/47.rom_ctrl_stress_all.4133022349 |
| Short name | T262 |
| Test name | |
| Test status | |
| Simulation time | 2756227697 ps |
| CPU time | 40.46 seconds |
| Started | May 05 12:47:11 PM PDT 24 |
| Finished | May 05 12:47:52 PM PDT 24 |
| Peak memory | 217820 kb |
| Host | smart-3ab724fc-585d-4ab0-bad8-d06ba82681e9 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4133022349 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm _name 47.rom_ctrl_stress_all.4133022349 |
| Directory | /workspace/47.rom_ctrl_stress_all/latest |
| Test location | /workspace/coverage/default/48.rom_ctrl_alert_test.2445411396 |
| Short name | T177 |
| Test name | |
| Test status | |
| Simulation time | 2335520016 ps |
| CPU time | 8.13 seconds |
| Started | May 05 12:47:10 PM PDT 24 |
| Finished | May 05 12:47:19 PM PDT 24 |
| Peak memory | 211740 kb |
| Host | smart-8168537c-c8e6-4b27-a876-d0a62a0a095d |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2445411396 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_alert_test.2445411396 |
| Directory | /workspace/48.rom_ctrl_alert_test/latest |
| Test location | /workspace/coverage/default/48.rom_ctrl_corrupt_sig_fatal_chk.2273658274 |
| Short name | T173 |
| Test name | |
| Test status | |
| Simulation time | 15702566318 ps |
| CPU time | 164.13 seconds |
| Started | May 05 12:47:10 PM PDT 24 |
| Finished | May 05 12:49:55 PM PDT 24 |
| Peak memory | 237380 kb |
| Host | smart-31cba8fd-19c6-4818-bd30-8d5451229bcb |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2273658274 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_ corrupt_sig_fatal_chk.2273658274 |
| Directory | /workspace/48.rom_ctrl_corrupt_sig_fatal_chk/latest |
| Test location | /workspace/coverage/default/48.rom_ctrl_kmac_err_chk.1470995415 |
| Short name | T26 |
| Test name | |
| Test status | |
| Simulation time | 4249207359 ps |
| CPU time | 35.61 seconds |
| Started | May 05 12:47:12 PM PDT 24 |
| Finished | May 05 12:47:49 PM PDT 24 |
| Peak memory | 212268 kb |
| Host | smart-9e2ddff8-ac79-4e5c-b863-595d7e45a677 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1470995415 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_kmac_err_chk.1470995415 |
| Directory | /workspace/48.rom_ctrl_kmac_err_chk/latest |
| Test location | /workspace/coverage/default/48.rom_ctrl_max_throughput_chk.989428384 |
| Short name | T318 |
| Test name | |
| Test status | |
| Simulation time | 1716241520 ps |
| CPU time | 14.94 seconds |
| Started | May 05 12:47:10 PM PDT 24 |
| Finished | May 05 12:47:26 PM PDT 24 |
| Peak memory | 211632 kb |
| Host | smart-37d0cd79-5c6c-423c-9869-a7485f330fe1 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=989428384 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_max_throughput_chk.989428384 |
| Directory | /workspace/48.rom_ctrl_max_throughput_chk/latest |
| Test location | /workspace/coverage/default/48.rom_ctrl_smoke.636045133 |
| Short name | T357 |
| Test name | |
| Test status | |
| Simulation time | 15098514547 ps |
| CPU time | 28.97 seconds |
| Started | May 05 12:47:15 PM PDT 24 |
| Finished | May 05 12:47:45 PM PDT 24 |
| Peak memory | 214656 kb |
| Host | smart-3b0ca2ae-e008-4c77-b1de-0fb0662af342 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=636045133 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_smoke.636045133 |
| Directory | /workspace/48.rom_ctrl_smoke/latest |
| Test location | /workspace/coverage/default/48.rom_ctrl_stress_all.1677623956 |
| Short name | T311 |
| Test name | |
| Test status | |
| Simulation time | 11581678973 ps |
| CPU time | 18.97 seconds |
| Started | May 05 12:47:16 PM PDT 24 |
| Finished | May 05 12:47:35 PM PDT 24 |
| Peak memory | 211588 kb |
| Host | smart-fbf0fbc8-f1bf-4a71-a86a-c09dccdaf20e |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1677623956 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm _name 48.rom_ctrl_stress_all.1677623956 |
| Directory | /workspace/48.rom_ctrl_stress_all/latest |
| Test location | /workspace/coverage/default/49.rom_ctrl_alert_test.3540648259 |
| Short name | T343 |
| Test name | |
| Test status | |
| Simulation time | 3500112425 ps |
| CPU time | 9.72 seconds |
| Started | May 05 12:47:15 PM PDT 24 |
| Finished | May 05 12:47:26 PM PDT 24 |
| Peak memory | 211752 kb |
| Host | smart-48e2fc7f-f044-4d6d-9f43-07edd72ce45d |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3540648259 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_alert_test.3540648259 |
| Directory | /workspace/49.rom_ctrl_alert_test/latest |
| Test location | /workspace/coverage/default/49.rom_ctrl_corrupt_sig_fatal_chk.1487280887 |
| Short name | T338 |
| Test name | |
| Test status | |
| Simulation time | 30023910831 ps |
| CPU time | 299.23 seconds |
| Started | May 05 12:47:16 PM PDT 24 |
| Finished | May 05 12:52:16 PM PDT 24 |
| Peak memory | 219232 kb |
| Host | smart-081f322d-d321-45be-9fcf-ba7fde042324 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1487280887 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_ corrupt_sig_fatal_chk.1487280887 |
| Directory | /workspace/49.rom_ctrl_corrupt_sig_fatal_chk/latest |
| Test location | /workspace/coverage/default/49.rom_ctrl_kmac_err_chk.2295067268 |
| Short name | T256 |
| Test name | |
| Test status | |
| Simulation time | 2981916065 ps |
| CPU time | 14.23 seconds |
| Started | May 05 12:47:15 PM PDT 24 |
| Finished | May 05 12:47:30 PM PDT 24 |
| Peak memory | 212272 kb |
| Host | smart-d5b9ddfc-c6a7-4b4d-8057-68dbc741e8df |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2295067268 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_kmac_err_chk.2295067268 |
| Directory | /workspace/49.rom_ctrl_kmac_err_chk/latest |
| Test location | /workspace/coverage/default/49.rom_ctrl_max_throughput_chk.2231538998 |
| Short name | T363 |
| Test name | |
| Test status | |
| Simulation time | 1924274805 ps |
| CPU time | 15.55 seconds |
| Started | May 05 12:47:09 PM PDT 24 |
| Finished | May 05 12:47:25 PM PDT 24 |
| Peak memory | 211616 kb |
| Host | smart-dafca990-0126-4797-9926-07dd65d24fbb |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2231538998 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_max_throughput_chk.2231538998 |
| Directory | /workspace/49.rom_ctrl_max_throughput_chk/latest |
| Test location | /workspace/coverage/default/49.rom_ctrl_smoke.2968086310 |
| Short name | T369 |
| Test name | |
| Test status | |
| Simulation time | 9951455633 ps |
| CPU time | 27.58 seconds |
| Started | May 05 12:47:10 PM PDT 24 |
| Finished | May 05 12:47:39 PM PDT 24 |
| Peak memory | 219900 kb |
| Host | smart-59415a9d-7a0a-4af6-9585-f3ddbd66ee98 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2968086310 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_smoke.2968086310 |
| Directory | /workspace/49.rom_ctrl_smoke/latest |
| Test location | /workspace/coverage/default/49.rom_ctrl_stress_all.1403636862 |
| Short name | T358 |
| Test name | |
| Test status | |
| Simulation time | 429317078 ps |
| CPU time | 22.73 seconds |
| Started | May 05 12:47:10 PM PDT 24 |
| Finished | May 05 12:47:33 PM PDT 24 |
| Peak memory | 215732 kb |
| Host | smart-778fe3c1-7b14-4006-8497-5a298879717f |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1403636862 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm _name 49.rom_ctrl_stress_all.1403636862 |
| Directory | /workspace/49.rom_ctrl_stress_all/latest |
| Test location | /workspace/coverage/default/5.rom_ctrl_alert_test.2329426357 |
| Short name | T9 |
| Test name | |
| Test status | |
| Simulation time | 294997762 ps |
| CPU time | 6.34 seconds |
| Started | May 05 12:46:13 PM PDT 24 |
| Finished | May 05 12:46:21 PM PDT 24 |
| Peak memory | 211644 kb |
| Host | smart-0fefe7bd-4726-4c10-88e7-3576669d6dd1 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2329426357 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_alert_test.2329426357 |
| Directory | /workspace/5.rom_ctrl_alert_test/latest |
| Test location | /workspace/coverage/default/5.rom_ctrl_corrupt_sig_fatal_chk.241432110 |
| Short name | T280 |
| Test name | |
| Test status | |
| Simulation time | 1869881625 ps |
| CPU time | 119.64 seconds |
| Started | May 05 12:46:06 PM PDT 24 |
| Finished | May 05 12:48:07 PM PDT 24 |
| Peak memory | 237852 kb |
| Host | smart-02de8a33-c87a-4ff3-bbab-b8a768c87cd5 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=241432110 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt _sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_co rrupt_sig_fatal_chk.241432110 |
| Directory | /workspace/5.rom_ctrl_corrupt_sig_fatal_chk/latest |
| Test location | /workspace/coverage/default/5.rom_ctrl_kmac_err_chk.296328242 |
| Short name | T126 |
| Test name | |
| Test status | |
| Simulation time | 2132874902 ps |
| CPU time | 22.23 seconds |
| Started | May 05 12:46:14 PM PDT 24 |
| Finished | May 05 12:46:37 PM PDT 24 |
| Peak memory | 212088 kb |
| Host | smart-daf7a1f9-cdc3-403c-9613-c5ef064bbaf2 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=296328242 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_kmac_err_chk.296328242 |
| Directory | /workspace/5.rom_ctrl_kmac_err_chk/latest |
| Test location | /workspace/coverage/default/5.rom_ctrl_max_throughput_chk.1756642815 |
| Short name | T362 |
| Test name | |
| Test status | |
| Simulation time | 2766919785 ps |
| CPU time | 12.75 seconds |
| Started | May 05 12:46:09 PM PDT 24 |
| Finished | May 05 12:46:22 PM PDT 24 |
| Peak memory | 211668 kb |
| Host | smart-8651bfa7-0a25-4aee-bc26-897a0365cb0d |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1756642815 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_max_throughput_chk.1756642815 |
| Directory | /workspace/5.rom_ctrl_max_throughput_chk/latest |
| Test location | /workspace/coverage/default/5.rom_ctrl_smoke.2590500405 |
| Short name | T310 |
| Test name | |
| Test status | |
| Simulation time | 1160865917 ps |
| CPU time | 21.02 seconds |
| Started | May 05 12:46:14 PM PDT 24 |
| Finished | May 05 12:46:37 PM PDT 24 |
| Peak memory | 219864 kb |
| Host | smart-af295b94-7b84-4362-b7cd-b35e8b90ac78 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2590500405 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_smoke.2590500405 |
| Directory | /workspace/5.rom_ctrl_smoke/latest |
| Test location | /workspace/coverage/default/5.rom_ctrl_stress_all.4112647534 |
| Short name | T224 |
| Test name | |
| Test status | |
| Simulation time | 5739993602 ps |
| CPU time | 15.17 seconds |
| Started | May 05 12:46:05 PM PDT 24 |
| Finished | May 05 12:46:21 PM PDT 24 |
| Peak memory | 211556 kb |
| Host | smart-262f0452-1e45-4586-bc29-5e4f6328d32c |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4112647534 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm _name 5.rom_ctrl_stress_all.4112647534 |
| Directory | /workspace/5.rom_ctrl_stress_all/latest |
| Test location | /workspace/coverage/default/6.rom_ctrl_alert_test.3887606327 |
| Short name | T170 |
| Test name | |
| Test status | |
| Simulation time | 1213614048 ps |
| CPU time | 11.65 seconds |
| Started | May 05 12:46:05 PM PDT 24 |
| Finished | May 05 12:46:18 PM PDT 24 |
| Peak memory | 211664 kb |
| Host | smart-aaf2afd8-2e81-47fc-8f8f-9e9fc86a24c0 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3887606327 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_alert_test.3887606327 |
| Directory | /workspace/6.rom_ctrl_alert_test/latest |
| Test location | /workspace/coverage/default/6.rom_ctrl_corrupt_sig_fatal_chk.2759159789 |
| Short name | T29 |
| Test name | |
| Test status | |
| Simulation time | 100908043233 ps |
| CPU time | 447.97 seconds |
| Started | May 05 12:46:06 PM PDT 24 |
| Finished | May 05 12:53:35 PM PDT 24 |
| Peak memory | 213488 kb |
| Host | smart-bdff87c2-a198-483f-93dd-f2e6c0f0c201 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2759159789 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_c orrupt_sig_fatal_chk.2759159789 |
| Directory | /workspace/6.rom_ctrl_corrupt_sig_fatal_chk/latest |
| Test location | /workspace/coverage/default/6.rom_ctrl_kmac_err_chk.98460985 |
| Short name | T192 |
| Test name | |
| Test status | |
| Simulation time | 1386487199 ps |
| CPU time | 11.75 seconds |
| Started | May 05 12:46:06 PM PDT 24 |
| Finished | May 05 12:46:18 PM PDT 24 |
| Peak memory | 212420 kb |
| Host | smart-a10b60e3-d7d1-4d4a-bfd2-6c81024fa806 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=98460985 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_kmac_err_chk.98460985 |
| Directory | /workspace/6.rom_ctrl_kmac_err_chk/latest |
| Test location | /workspace/coverage/default/6.rom_ctrl_max_throughput_chk.831977658 |
| Short name | T144 |
| Test name | |
| Test status | |
| Simulation time | 1202945162 ps |
| CPU time | 12.15 seconds |
| Started | May 05 12:46:07 PM PDT 24 |
| Finished | May 05 12:46:20 PM PDT 24 |
| Peak memory | 211620 kb |
| Host | smart-d9a2e7d7-e3ce-48db-817f-ba4fb3e1cfdf |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=831977658 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_max_throughput_chk.831977658 |
| Directory | /workspace/6.rom_ctrl_max_throughput_chk/latest |
| Test location | /workspace/coverage/default/6.rom_ctrl_smoke.3130657029 |
| Short name | T19 |
| Test name | |
| Test status | |
| Simulation time | 2137233530 ps |
| CPU time | 16.52 seconds |
| Started | May 05 12:46:09 PM PDT 24 |
| Finished | May 05 12:46:26 PM PDT 24 |
| Peak memory | 219776 kb |
| Host | smart-55541c48-1b4b-4d38-a0a8-1088f5f6b10d |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3130657029 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_smoke.3130657029 |
| Directory | /workspace/6.rom_ctrl_smoke/latest |
| Test location | /workspace/coverage/default/6.rom_ctrl_stress_all.2424193186 |
| Short name | T291 |
| Test name | |
| Test status | |
| Simulation time | 416821134 ps |
| CPU time | 21.48 seconds |
| Started | May 05 12:46:17 PM PDT 24 |
| Finished | May 05 12:46:39 PM PDT 24 |
| Peak memory | 216808 kb |
| Host | smart-578c10d5-1b71-4e96-8c55-4bb939c45c43 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2424193186 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm _name 6.rom_ctrl_stress_all.2424193186 |
| Directory | /workspace/6.rom_ctrl_stress_all/latest |
| Test location | /workspace/coverage/default/7.rom_ctrl_alert_test.1304537661 |
| Short name | T307 |
| Test name | |
| Test status | |
| Simulation time | 3919938600 ps |
| CPU time | 15.16 seconds |
| Started | May 05 12:46:06 PM PDT 24 |
| Finished | May 05 12:46:22 PM PDT 24 |
| Peak memory | 211804 kb |
| Host | smart-a958322b-368e-448f-8d3d-af87e914c9e9 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1304537661 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_alert_test.1304537661 |
| Directory | /workspace/7.rom_ctrl_alert_test/latest |
| Test location | /workspace/coverage/default/7.rom_ctrl_corrupt_sig_fatal_chk.935200394 |
| Short name | T230 |
| Test name | |
| Test status | |
| Simulation time | 15542417732 ps |
| CPU time | 147.34 seconds |
| Started | May 05 12:46:16 PM PDT 24 |
| Finished | May 05 12:48:44 PM PDT 24 |
| Peak memory | 236848 kb |
| Host | smart-2185c9b4-01c5-4f09-a331-d14fe3e712f7 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=935200394 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt _sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_co rrupt_sig_fatal_chk.935200394 |
| Directory | /workspace/7.rom_ctrl_corrupt_sig_fatal_chk/latest |
| Test location | /workspace/coverage/default/7.rom_ctrl_kmac_err_chk.1255263726 |
| Short name | T342 |
| Test name | |
| Test status | |
| Simulation time | 3109285375 ps |
| CPU time | 21.4 seconds |
| Started | May 05 12:46:07 PM PDT 24 |
| Finished | May 05 12:46:29 PM PDT 24 |
| Peak memory | 212588 kb |
| Host | smart-c903dd38-6a14-4d48-89e0-ae6969b25d8b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1255263726 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_kmac_err_chk.1255263726 |
| Directory | /workspace/7.rom_ctrl_kmac_err_chk/latest |
| Test location | /workspace/coverage/default/7.rom_ctrl_max_throughput_chk.40832955 |
| Short name | T225 |
| Test name | |
| Test status | |
| Simulation time | 634319462 ps |
| CPU time | 5.56 seconds |
| Started | May 05 12:46:10 PM PDT 24 |
| Finished | May 05 12:46:16 PM PDT 24 |
| Peak memory | 211540 kb |
| Host | smart-0b761931-ac8c-4474-a302-6fca22881647 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=40832955 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_max_throughput_chk.40832955 |
| Directory | /workspace/7.rom_ctrl_max_throughput_chk/latest |
| Test location | /workspace/coverage/default/7.rom_ctrl_smoke.2181388748 |
| Short name | T93 |
| Test name | |
| Test status | |
| Simulation time | 3253136047 ps |
| CPU time | 28.14 seconds |
| Started | May 05 12:46:13 PM PDT 24 |
| Finished | May 05 12:46:42 PM PDT 24 |
| Peak memory | 219888 kb |
| Host | smart-3e6c73ad-7a4e-44fe-a236-970902c98f9f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2181388748 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_smoke.2181388748 |
| Directory | /workspace/7.rom_ctrl_smoke/latest |
| Test location | /workspace/coverage/default/7.rom_ctrl_stress_all.2726460838 |
| Short name | T306 |
| Test name | |
| Test status | |
| Simulation time | 202678782 ps |
| CPU time | 11.54 seconds |
| Started | May 05 12:46:06 PM PDT 24 |
| Finished | May 05 12:46:19 PM PDT 24 |
| Peak memory | 212692 kb |
| Host | smart-a7399c23-5f2f-40ed-8f90-0e7fa5ecd2e3 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2726460838 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm _name 7.rom_ctrl_stress_all.2726460838 |
| Directory | /workspace/7.rom_ctrl_stress_all/latest |
| Test location | /workspace/coverage/default/8.rom_ctrl_alert_test.3411975569 |
| Short name | T364 |
| Test name | |
| Test status | |
| Simulation time | 1634695098 ps |
| CPU time | 13.94 seconds |
| Started | May 05 12:46:14 PM PDT 24 |
| Finished | May 05 12:46:29 PM PDT 24 |
| Peak memory | 211656 kb |
| Host | smart-e854fce0-07b0-40ab-9d3d-7cd7efdd73b3 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3411975569 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_alert_test.3411975569 |
| Directory | /workspace/8.rom_ctrl_alert_test/latest |
| Test location | /workspace/coverage/default/8.rom_ctrl_corrupt_sig_fatal_chk.1605022898 |
| Short name | T219 |
| Test name | |
| Test status | |
| Simulation time | 26016344421 ps |
| CPU time | 155.22 seconds |
| Started | May 05 12:46:16 PM PDT 24 |
| Finished | May 05 12:48:52 PM PDT 24 |
| Peak memory | 237340 kb |
| Host | smart-2e4c4114-d517-4bf2-bab0-b2434e09c761 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1605022898 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_c orrupt_sig_fatal_chk.1605022898 |
| Directory | /workspace/8.rom_ctrl_corrupt_sig_fatal_chk/latest |
| Test location | /workspace/coverage/default/8.rom_ctrl_kmac_err_chk.3052003029 |
| Short name | T25 |
| Test name | |
| Test status | |
| Simulation time | 173044122 ps |
| CPU time | 9.26 seconds |
| Started | May 05 12:46:06 PM PDT 24 |
| Finished | May 05 12:46:16 PM PDT 24 |
| Peak memory | 211748 kb |
| Host | smart-9b841168-e603-42c8-a3d4-117ca76ba9c5 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3052003029 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_kmac_err_chk.3052003029 |
| Directory | /workspace/8.rom_ctrl_kmac_err_chk/latest |
| Test location | /workspace/coverage/default/8.rom_ctrl_max_throughput_chk.2831021489 |
| Short name | T283 |
| Test name | |
| Test status | |
| Simulation time | 2027700012 ps |
| CPU time | 16.86 seconds |
| Started | May 05 12:46:12 PM PDT 24 |
| Finished | May 05 12:46:30 PM PDT 24 |
| Peak memory | 211552 kb |
| Host | smart-d1de25e8-0dbb-4935-9e11-e574b43c0926 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2831021489 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_max_throughput_chk.2831021489 |
| Directory | /workspace/8.rom_ctrl_max_throughput_chk/latest |
| Test location | /workspace/coverage/default/8.rom_ctrl_smoke.2014620180 |
| Short name | T220 |
| Test name | |
| Test status | |
| Simulation time | 369858343 ps |
| CPU time | 9.86 seconds |
| Started | May 05 12:46:14 PM PDT 24 |
| Finished | May 05 12:46:25 PM PDT 24 |
| Peak memory | 213732 kb |
| Host | smart-be0c3635-18ac-40e3-aadc-e660910993fe |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2014620180 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_smoke.2014620180 |
| Directory | /workspace/8.rom_ctrl_smoke/latest |
| Test location | /workspace/coverage/default/8.rom_ctrl_stress_all.618933069 |
| Short name | T178 |
| Test name | |
| Test status | |
| Simulation time | 12872821997 ps |
| CPU time | 57.11 seconds |
| Started | May 05 12:46:18 PM PDT 24 |
| Finished | May 05 12:47:15 PM PDT 24 |
| Peak memory | 214532 kb |
| Host | smart-f314c721-bea6-4eed-983a-fdeab8256916 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=618933069 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test + UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 8.rom_ctrl_stress_all.618933069 |
| Directory | /workspace/8.rom_ctrl_stress_all/latest |
| Test location | /workspace/coverage/default/8.rom_ctrl_stress_all_with_rand_reset.3833950337 |
| Short name | T44 |
| Test name | |
| Test status | |
| Simulation time | 40683176397 ps |
| CPU time | 839.85 seconds |
| Started | May 05 12:46:07 PM PDT 24 |
| Finished | May 05 01:00:07 PM PDT 24 |
| Peak memory | 230320 kb |
| Host | smart-d506ec6c-e11c-4684-9cfa-35fa028bae35 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3833950337 -assert nop ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_stress_all_with_rand_reset.3833950337 |
| Directory | /workspace/8.rom_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/9.rom_ctrl_alert_test.418640716 |
| Short name | T54 |
| Test name | |
| Test status | |
| Simulation time | 6512624159 ps |
| CPU time | 13.3 seconds |
| Started | May 05 12:46:17 PM PDT 24 |
| Finished | May 05 12:46:31 PM PDT 24 |
| Peak memory | 211816 kb |
| Host | smart-ad4d16b3-c038-446b-81c5-b93c629c4dbc |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=418640716 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_alert_test.418640716 |
| Directory | /workspace/9.rom_ctrl_alert_test/latest |
| Test location | /workspace/coverage/default/9.rom_ctrl_corrupt_sig_fatal_chk.28765653 |
| Short name | T355 |
| Test name | |
| Test status | |
| Simulation time | 45526167990 ps |
| CPU time | 250.76 seconds |
| Started | May 05 12:46:13 PM PDT 24 |
| Finished | May 05 12:50:24 PM PDT 24 |
| Peak memory | 233868 kb |
| Host | smart-56a35a95-99b6-4a4c-b367-425841751be2 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28765653 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_ sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_cor rupt_sig_fatal_chk.28765653 |
| Directory | /workspace/9.rom_ctrl_corrupt_sig_fatal_chk/latest |
| Test location | /workspace/coverage/default/9.rom_ctrl_kmac_err_chk.430828563 |
| Short name | T30 |
| Test name | |
| Test status | |
| Simulation time | 3685132605 ps |
| CPU time | 31.58 seconds |
| Started | May 05 12:46:08 PM PDT 24 |
| Finished | May 05 12:46:41 PM PDT 24 |
| Peak memory | 212492 kb |
| Host | smart-52f37931-9183-499e-8887-16646ce54bf7 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=430828563 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_kmac_err_chk.430828563 |
| Directory | /workspace/9.rom_ctrl_kmac_err_chk/latest |
| Test location | /workspace/coverage/default/9.rom_ctrl_max_throughput_chk.3715542095 |
| Short name | T1 |
| Test name | |
| Test status | |
| Simulation time | 2165484791 ps |
| CPU time | 17.44 seconds |
| Started | May 05 12:46:14 PM PDT 24 |
| Finished | May 05 12:46:33 PM PDT 24 |
| Peak memory | 211688 kb |
| Host | smart-ad6d45c7-8e48-4047-aacd-10fe927b17c6 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3715542095 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_max_throughput_chk.3715542095 |
| Directory | /workspace/9.rom_ctrl_max_throughput_chk/latest |
| Test location | /workspace/coverage/default/9.rom_ctrl_smoke.4230745793 |
| Short name | T147 |
| Test name | |
| Test status | |
| Simulation time | 7815864625 ps |
| CPU time | 20.82 seconds |
| Started | May 05 12:46:13 PM PDT 24 |
| Finished | May 05 12:46:34 PM PDT 24 |
| Peak memory | 214652 kb |
| Host | smart-3b4fe00b-b9c8-431c-a03c-9f53c2fa3747 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4230745793 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_smoke.4230745793 |
| Directory | /workspace/9.rom_ctrl_smoke/latest |
| Test location | /workspace/coverage/default/9.rom_ctrl_stress_all.2046330364 |
| Short name | T238 |
| Test name | |
| Test status | |
| Simulation time | 1694921259 ps |
| CPU time | 19.5 seconds |
| Started | May 05 12:46:18 PM PDT 24 |
| Finished | May 05 12:46:38 PM PDT 24 |
| Peak memory | 211448 kb |
| Host | smart-55d84971-cd7a-4108-8e16-32898856da5f |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2046330364 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm _name 9.rom_ctrl_stress_all.2046330364 |
| Directory | /workspace/9.rom_ctrl_stress_all/latest |
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