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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
97.57 96.97 93.01 97.88 100.00 98.69 98.03 98.37


Total test records in report: 462
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T300 /workspace/coverage/default/31.rom_ctrl_kmac_err_chk.275057500 May 07 12:39:04 PM PDT 24 May 07 12:39:16 PM PDT 24 1277763565 ps
T301 /workspace/coverage/default/34.rom_ctrl_corrupt_sig_fatal_chk.2091633620 May 07 12:39:04 PM PDT 24 May 07 12:42:08 PM PDT 24 67670405133 ps
T302 /workspace/coverage/default/38.rom_ctrl_smoke.3682218269 May 07 12:39:05 PM PDT 24 May 07 12:39:38 PM PDT 24 7037735372 ps
T303 /workspace/coverage/default/6.rom_ctrl_corrupt_sig_fatal_chk.3081695184 May 07 12:38:50 PM PDT 24 May 07 12:42:13 PM PDT 24 92701848631 ps
T304 /workspace/coverage/default/39.rom_ctrl_alert_test.2860154892 May 07 12:39:01 PM PDT 24 May 07 12:39:20 PM PDT 24 3828081033 ps
T305 /workspace/coverage/default/24.rom_ctrl_kmac_err_chk.4015047345 May 07 12:39:07 PM PDT 24 May 07 12:39:38 PM PDT 24 6683394426 ps
T306 /workspace/coverage/default/37.rom_ctrl_alert_test.22070568 May 07 12:39:12 PM PDT 24 May 07 12:39:19 PM PDT 24 347269292 ps
T307 /workspace/coverage/default/16.rom_ctrl_alert_test.386129518 May 07 12:39:00 PM PDT 24 May 07 12:39:16 PM PDT 24 5091777910 ps
T308 /workspace/coverage/default/17.rom_ctrl_max_throughput_chk.2391848388 May 07 12:38:56 PM PDT 24 May 07 12:39:04 PM PDT 24 358370997 ps
T309 /workspace/coverage/default/5.rom_ctrl_kmac_err_chk.1498991921 May 07 12:38:52 PM PDT 24 May 07 12:39:04 PM PDT 24 170702093 ps
T310 /workspace/coverage/default/2.rom_ctrl_corrupt_sig_fatal_chk.1551172895 May 07 12:38:43 PM PDT 24 May 07 12:42:28 PM PDT 24 18328228826 ps
T311 /workspace/coverage/default/36.rom_ctrl_smoke.1336615465 May 07 12:39:06 PM PDT 24 May 07 12:39:21 PM PDT 24 1709197985 ps
T34 /workspace/coverage/default/0.rom_ctrl_sec_cm.393782879 May 07 12:38:37 PM PDT 24 May 07 12:39:39 PM PDT 24 5107156493 ps
T312 /workspace/coverage/default/21.rom_ctrl_kmac_err_chk.1898723960 May 07 12:38:53 PM PDT 24 May 07 12:39:15 PM PDT 24 6227571607 ps
T313 /workspace/coverage/default/43.rom_ctrl_corrupt_sig_fatal_chk.1977066384 May 07 12:39:15 PM PDT 24 May 07 12:44:42 PM PDT 24 24791569526 ps
T314 /workspace/coverage/default/49.rom_ctrl_max_throughput_chk.2354625635 May 07 12:39:27 PM PDT 24 May 07 12:39:35 PM PDT 24 188682262 ps
T315 /workspace/coverage/default/35.rom_ctrl_corrupt_sig_fatal_chk.769710882 May 07 12:39:18 PM PDT 24 May 07 12:40:47 PM PDT 24 1499377994 ps
T35 /workspace/coverage/default/4.rom_ctrl_sec_cm.745458594 May 07 12:38:46 PM PDT 24 May 07 12:39:39 PM PDT 24 543201838 ps
T316 /workspace/coverage/default/47.rom_ctrl_smoke.1429603115 May 07 12:39:20 PM PDT 24 May 07 12:39:56 PM PDT 24 3775487774 ps
T317 /workspace/coverage/default/11.rom_ctrl_smoke.3601618484 May 07 12:38:57 PM PDT 24 May 07 12:39:23 PM PDT 24 1969094565 ps
T318 /workspace/coverage/default/4.rom_ctrl_max_throughput_chk.4055039512 May 07 12:39:00 PM PDT 24 May 07 12:39:09 PM PDT 24 404011379 ps
T319 /workspace/coverage/default/16.rom_ctrl_corrupt_sig_fatal_chk.1997848098 May 07 12:38:59 PM PDT 24 May 07 12:40:21 PM PDT 24 15442402947 ps
T320 /workspace/coverage/default/23.rom_ctrl_alert_test.952840843 May 07 12:39:12 PM PDT 24 May 07 12:39:27 PM PDT 24 6457166630 ps
T321 /workspace/coverage/default/0.rom_ctrl_kmac_err_chk.534141323 May 07 12:38:49 PM PDT 24 May 07 12:39:01 PM PDT 24 692410477 ps
T322 /workspace/coverage/default/41.rom_ctrl_max_throughput_chk.3145110253 May 07 12:39:18 PM PDT 24 May 07 12:39:32 PM PDT 24 2140600575 ps
T323 /workspace/coverage/default/8.rom_ctrl_kmac_err_chk.392768110 May 07 12:38:47 PM PDT 24 May 07 12:39:07 PM PDT 24 1337905058 ps
T324 /workspace/coverage/default/37.rom_ctrl_smoke.3241518962 May 07 12:39:03 PM PDT 24 May 07 12:39:32 PM PDT 24 46645816716 ps
T325 /workspace/coverage/default/38.rom_ctrl_corrupt_sig_fatal_chk.4100238423 May 07 12:39:12 PM PDT 24 May 07 12:45:06 PM PDT 24 75744178880 ps
T326 /workspace/coverage/default/32.rom_ctrl_alert_test.3961073334 May 07 12:39:11 PM PDT 24 May 07 12:39:27 PM PDT 24 1749642240 ps
T327 /workspace/coverage/default/21.rom_ctrl_max_throughput_chk.2950859921 May 07 12:38:57 PM PDT 24 May 07 12:39:15 PM PDT 24 6294879599 ps
T328 /workspace/coverage/default/29.rom_ctrl_corrupt_sig_fatal_chk.3843322284 May 07 12:39:12 PM PDT 24 May 07 12:42:28 PM PDT 24 222713038808 ps
T329 /workspace/coverage/default/0.rom_ctrl_stress_all.10811071 May 07 12:38:45 PM PDT 24 May 07 12:39:26 PM PDT 24 17098361547 ps
T330 /workspace/coverage/default/19.rom_ctrl_alert_test.3688456664 May 07 12:38:57 PM PDT 24 May 07 12:39:15 PM PDT 24 1969935523 ps
T331 /workspace/coverage/default/31.rom_ctrl_max_throughput_chk.3216298746 May 07 12:39:11 PM PDT 24 May 07 12:39:29 PM PDT 24 7565237593 ps
T332 /workspace/coverage/default/12.rom_ctrl_kmac_err_chk.3187133587 May 07 12:38:59 PM PDT 24 May 07 12:39:13 PM PDT 24 334074626 ps
T101 /workspace/coverage/default/36.rom_ctrl_max_throughput_chk.1086431302 May 07 12:39:12 PM PDT 24 May 07 12:39:19 PM PDT 24 97358046 ps
T333 /workspace/coverage/default/0.rom_ctrl_alert_test.2532375440 May 07 12:38:39 PM PDT 24 May 07 12:38:52 PM PDT 24 2412628697 ps
T334 /workspace/coverage/default/10.rom_ctrl_alert_test.2197590222 May 07 12:39:02 PM PDT 24 May 07 12:39:09 PM PDT 24 88071440 ps
T335 /workspace/coverage/default/3.rom_ctrl_corrupt_sig_fatal_chk.332246976 May 07 12:38:56 PM PDT 24 May 07 12:39:54 PM PDT 24 1590312096 ps
T336 /workspace/coverage/default/39.rom_ctrl_max_throughput_chk.1803100122 May 07 12:39:12 PM PDT 24 May 07 12:39:26 PM PDT 24 15048103715 ps
T337 /workspace/coverage/default/34.rom_ctrl_smoke.1457467031 May 07 12:39:05 PM PDT 24 May 07 12:39:46 PM PDT 24 4955301473 ps
T338 /workspace/coverage/default/8.rom_ctrl_alert_test.905510520 May 07 12:39:01 PM PDT 24 May 07 12:39:08 PM PDT 24 86331174 ps
T339 /workspace/coverage/default/31.rom_ctrl_alert_test.2946013942 May 07 12:39:16 PM PDT 24 May 07 12:39:28 PM PDT 24 863709931 ps
T340 /workspace/coverage/default/27.rom_ctrl_max_throughput_chk.105155427 May 07 12:39:09 PM PDT 24 May 07 12:39:20 PM PDT 24 6714590275 ps
T341 /workspace/coverage/default/7.rom_ctrl_corrupt_sig_fatal_chk.915133403 May 07 12:38:55 PM PDT 24 May 07 12:40:08 PM PDT 24 1038368285 ps
T342 /workspace/coverage/default/9.rom_ctrl_alert_test.221836058 May 07 12:38:56 PM PDT 24 May 07 12:39:11 PM PDT 24 5460701103 ps
T343 /workspace/coverage/default/28.rom_ctrl_max_throughput_chk.2349843875 May 07 12:38:53 PM PDT 24 May 07 12:39:13 PM PDT 24 11343772109 ps
T344 /workspace/coverage/default/33.rom_ctrl_kmac_err_chk.1189215488 May 07 12:39:05 PM PDT 24 May 07 12:39:35 PM PDT 24 5788998147 ps
T345 /workspace/coverage/default/11.rom_ctrl_max_throughput_chk.2998282732 May 07 12:39:03 PM PDT 24 May 07 12:39:16 PM PDT 24 1706404660 ps
T346 /workspace/coverage/default/33.rom_ctrl_stress_all_with_rand_reset.847250675 May 07 12:39:10 PM PDT 24 May 07 02:40:08 PM PDT 24 46948711302 ps
T347 /workspace/coverage/default/48.rom_ctrl_alert_test.3013333616 May 07 12:39:19 PM PDT 24 May 07 12:39:38 PM PDT 24 8390210707 ps
T348 /workspace/coverage/default/32.rom_ctrl_kmac_err_chk.150020182 May 07 12:39:07 PM PDT 24 May 07 12:39:22 PM PDT 24 497795572 ps
T349 /workspace/coverage/default/9.rom_ctrl_smoke.3284264854 May 07 12:38:59 PM PDT 24 May 07 12:39:27 PM PDT 24 9877387156 ps
T350 /workspace/coverage/default/11.rom_ctrl_stress_all.2429917323 May 07 12:38:59 PM PDT 24 May 07 12:40:02 PM PDT 24 6279054826 ps
T351 /workspace/coverage/default/26.rom_ctrl_stress_all.913659650 May 07 12:38:59 PM PDT 24 May 07 12:40:47 PM PDT 24 11594618633 ps
T352 /workspace/coverage/default/23.rom_ctrl_stress_all.3828804870 May 07 12:39:15 PM PDT 24 May 07 12:39:35 PM PDT 24 1756739513 ps
T353 /workspace/coverage/default/26.rom_ctrl_alert_test.2358550161 May 07 12:39:01 PM PDT 24 May 07 12:39:20 PM PDT 24 7704844669 ps
T354 /workspace/coverage/default/41.rom_ctrl_smoke.2173763429 May 07 12:39:12 PM PDT 24 May 07 12:39:33 PM PDT 24 1695344129 ps
T355 /workspace/coverage/default/7.rom_ctrl_smoke.2004487831 May 07 12:39:08 PM PDT 24 May 07 12:39:20 PM PDT 24 213734036 ps
T356 /workspace/coverage/default/20.rom_ctrl_alert_test.3081080181 May 07 12:39:04 PM PDT 24 May 07 12:39:12 PM PDT 24 1120428820 ps
T357 /workspace/coverage/default/4.rom_ctrl_smoke.3325356787 May 07 12:38:49 PM PDT 24 May 07 12:39:01 PM PDT 24 210098843 ps
T358 /workspace/coverage/default/16.rom_ctrl_stress_all.598483748 May 07 12:38:52 PM PDT 24 May 07 12:39:40 PM PDT 24 8994957844 ps
T359 /workspace/coverage/default/3.rom_ctrl_kmac_err_chk.2880419209 May 07 12:38:52 PM PDT 24 May 07 12:39:20 PM PDT 24 2992703571 ps
T112 /workspace/coverage/default/10.rom_ctrl_stress_all_with_rand_reset.441135545 May 07 12:38:59 PM PDT 24 May 07 12:54:03 PM PDT 24 211069970262 ps
T360 /workspace/coverage/default/25.rom_ctrl_corrupt_sig_fatal_chk.4018157618 May 07 12:39:03 PM PDT 24 May 07 12:45:04 PM PDT 24 62215901080 ps
T361 /workspace/coverage/default/43.rom_ctrl_stress_all.3061569226 May 07 12:39:18 PM PDT 24 May 07 12:40:01 PM PDT 24 12761080460 ps
T362 /workspace/coverage/default/49.rom_ctrl_kmac_err_chk.2872871913 May 07 12:39:14 PM PDT 24 May 07 12:39:39 PM PDT 24 2259597021 ps
T52 /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_mem_rw_with_rand_reset.3367633569 May 07 12:38:21 PM PDT 24 May 07 12:38:36 PM PDT 24 24261050800 ps
T363 /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_errors.3017721981 May 07 12:38:13 PM PDT 24 May 07 12:38:23 PM PDT 24 87215165 ps
T53 /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_rw.2885647974 May 07 12:38:41 PM PDT 24 May 07 12:38:52 PM PDT 24 1962641060 ps
T54 /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_mem_rw_with_rand_reset.2267705771 May 07 12:38:52 PM PDT 24 May 07 12:39:12 PM PDT 24 2071906101 ps
T364 /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_partial_access.3941230863 May 07 12:38:31 PM PDT 24 May 07 12:38:36 PM PDT 24 90850261 ps
T60 /workspace/coverage/cover_reg_top/11.rom_ctrl_passthru_mem_tl_intg_err.200168024 May 07 12:38:47 PM PDT 24 May 07 12:40:33 PM PDT 24 12551455347 ps
T61 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_aliasing.378043122 May 07 12:38:30 PM PDT 24 May 07 12:38:45 PM PDT 24 10097523974 ps
T62 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_hw_reset.603471668 May 07 12:38:32 PM PDT 24 May 07 12:38:43 PM PDT 24 1589382002 ps
T365 /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_errors.203933751 May 07 12:38:47 PM PDT 24 May 07 12:39:02 PM PDT 24 4588119562 ps
T96 /workspace/coverage/cover_reg_top/1.rom_ctrl_passthru_mem_tl_intg_err.3856394615 May 07 12:38:11 PM PDT 24 May 07 12:38:35 PM PDT 24 2772217609 ps
T366 /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_errors.3385430869 May 07 12:38:40 PM PDT 24 May 07 12:38:51 PM PDT 24 903812973 ps
T102 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_aliasing.3451866405 May 07 12:38:15 PM PDT 24 May 07 12:38:27 PM PDT 24 867451486 ps
T63 /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_rw.3812519477 May 07 12:38:33 PM PDT 24 May 07 12:38:47 PM PDT 24 7141438696 ps
T97 /workspace/coverage/cover_reg_top/0.rom_ctrl_same_csr_outstanding.3080231307 May 07 12:38:31 PM PDT 24 May 07 12:38:38 PM PDT 24 91254361 ps
T103 /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_rw.184826328 May 07 12:38:36 PM PDT 24 May 07 12:38:50 PM PDT 24 2798836709 ps
T49 /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_intg_err.4264871638 May 07 12:38:46 PM PDT 24 May 07 12:39:56 PM PDT 24 864982554 ps
T64 /workspace/coverage/cover_reg_top/14.rom_ctrl_passthru_mem_tl_intg_err.3478115011 May 07 12:38:29 PM PDT 24 May 07 12:39:03 PM PDT 24 580653078 ps
T65 /workspace/coverage/cover_reg_top/9.rom_ctrl_same_csr_outstanding.1741312345 May 07 12:38:36 PM PDT 24 May 07 12:38:48 PM PDT 24 13228370760 ps
T50 /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_intg_err.2426018221 May 07 12:38:21 PM PDT 24 May 07 12:39:44 PM PDT 24 1988842686 ps
T66 /workspace/coverage/cover_reg_top/18.rom_ctrl_passthru_mem_tl_intg_err.2754172195 May 07 12:38:47 PM PDT 24 May 07 12:39:38 PM PDT 24 3678939284 ps
T51 /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_intg_err.2035756117 May 07 12:38:15 PM PDT 24 May 07 12:39:05 PM PDT 24 6045389512 ps
T367 /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_walk.2709424206 May 07 12:38:27 PM PDT 24 May 07 12:38:33 PM PDT 24 553304286 ps
T67 /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_rw.3570371008 May 07 12:38:25 PM PDT 24 May 07 12:38:40 PM PDT 24 20326516019 ps
T368 /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_walk.1266595416 May 07 12:38:11 PM PDT 24 May 07 12:38:27 PM PDT 24 5861246112 ps
T369 /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_mem_rw_with_rand_reset.852688805 May 07 12:38:41 PM PDT 24 May 07 12:38:55 PM PDT 24 2710573707 ps
T68 /workspace/coverage/cover_reg_top/7.rom_ctrl_passthru_mem_tl_intg_err.3793491871 May 07 12:38:25 PM PDT 24 May 07 12:39:09 PM PDT 24 16596206656 ps
T370 /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_errors.4083118663 May 07 12:38:30 PM PDT 24 May 07 12:38:38 PM PDT 24 85422017 ps
T371 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_hw_reset.4047411431 May 07 12:38:35 PM PDT 24 May 07 12:38:48 PM PDT 24 1805914514 ps
T372 /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_errors.829060387 May 07 12:38:40 PM PDT 24 May 07 12:38:51 PM PDT 24 2275025228 ps
T373 /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_mem_rw_with_rand_reset.4266014276 May 07 12:38:30 PM PDT 24 May 07 12:38:36 PM PDT 24 410294796 ps
T98 /workspace/coverage/cover_reg_top/1.rom_ctrl_same_csr_outstanding.3809218768 May 07 12:38:25 PM PDT 24 May 07 12:38:33 PM PDT 24 519785630 ps
T99 /workspace/coverage/cover_reg_top/4.rom_ctrl_same_csr_outstanding.3598411332 May 07 12:38:34 PM PDT 24 May 07 12:38:46 PM PDT 24 7488080738 ps
T374 /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_errors.2711917227 May 07 12:38:25 PM PDT 24 May 07 12:38:45 PM PDT 24 5809883273 ps
T375 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_rw.1140270421 May 07 12:38:36 PM PDT 24 May 07 12:38:42 PM PDT 24 232069148 ps
T376 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_mem_rw_with_rand_reset.3530171263 May 07 12:38:27 PM PDT 24 May 07 12:38:37 PM PDT 24 554400637 ps
T76 /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_rw.2016241313 May 07 12:38:33 PM PDT 24 May 07 12:38:39 PM PDT 24 177776451 ps
T377 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_bit_bash.1954916823 May 07 12:38:32 PM PDT 24 May 07 12:38:48 PM PDT 24 1820361273 ps
T115 /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_intg_err.264725304 May 07 12:38:38 PM PDT 24 May 07 12:39:16 PM PDT 24 702529471 ps
T378 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_mem_rw_with_rand_reset.4259819592 May 07 12:38:47 PM PDT 24 May 07 12:38:54 PM PDT 24 412279161 ps
T379 /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_rw.1471802310 May 07 12:38:35 PM PDT 24 May 07 12:38:40 PM PDT 24 333394132 ps
T380 /workspace/coverage/cover_reg_top/15.rom_ctrl_passthru_mem_tl_intg_err.2278087919 May 07 12:38:33 PM PDT 24 May 07 12:39:02 PM PDT 24 572122423 ps
T381 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_rw.3294083868 May 07 12:38:31 PM PDT 24 May 07 12:38:43 PM PDT 24 4902095644 ps
T382 /workspace/coverage/cover_reg_top/0.rom_ctrl_passthru_mem_tl_intg_err.2326414218 May 07 12:38:35 PM PDT 24 May 07 12:39:28 PM PDT 24 10862498865 ps
T77 /workspace/coverage/cover_reg_top/12.rom_ctrl_passthru_mem_tl_intg_err.3242852334 May 07 12:38:35 PM PDT 24 May 07 12:39:27 PM PDT 24 21953505634 ps
T100 /workspace/coverage/cover_reg_top/10.rom_ctrl_same_csr_outstanding.2445196453 May 07 12:38:30 PM PDT 24 May 07 12:38:38 PM PDT 24 372798475 ps
T383 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_bit_bash.892094619 May 07 12:38:12 PM PDT 24 May 07 12:38:29 PM PDT 24 5985767943 ps
T384 /workspace/coverage/cover_reg_top/11.rom_ctrl_same_csr_outstanding.1172940994 May 07 12:38:31 PM PDT 24 May 07 12:38:42 PM PDT 24 667630257 ps
T385 /workspace/coverage/cover_reg_top/13.rom_ctrl_same_csr_outstanding.2282945301 May 07 12:38:35 PM PDT 24 May 07 12:38:41 PM PDT 24 320905568 ps
T386 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_mem_rw_with_rand_reset.186800130 May 07 12:38:25 PM PDT 24 May 07 12:38:31 PM PDT 24 210925608 ps
T387 /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_mem_rw_with_rand_reset.3195677931 May 07 12:38:24 PM PDT 24 May 07 12:38:35 PM PDT 24 3122494656 ps
T388 /workspace/coverage/cover_reg_top/8.rom_ctrl_same_csr_outstanding.3619716403 May 07 12:38:21 PM PDT 24 May 07 12:38:35 PM PDT 24 15428565229 ps
T389 /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_mem_rw_with_rand_reset.3107660398 May 07 12:38:15 PM PDT 24 May 07 12:38:34 PM PDT 24 8173398631 ps
T78 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_bit_bash.8888103 May 07 12:38:22 PM PDT 24 May 07 12:38:30 PM PDT 24 1375910911 ps
T390 /workspace/coverage/cover_reg_top/19.rom_ctrl_same_csr_outstanding.272591170 May 07 12:38:48 PM PDT 24 May 07 12:39:05 PM PDT 24 6720056837 ps
T391 /workspace/coverage/cover_reg_top/5.rom_ctrl_same_csr_outstanding.4144840235 May 07 12:38:39 PM PDT 24 May 07 12:38:51 PM PDT 24 1394256487 ps
T392 /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_rw.252456380 May 07 12:38:30 PM PDT 24 May 07 12:38:36 PM PDT 24 88141028 ps
T393 /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_mem_rw_with_rand_reset.2191181833 May 07 12:38:59 PM PDT 24 May 07 12:39:19 PM PDT 24 2133006243 ps
T79 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_aliasing.2133991436 May 07 12:38:20 PM PDT 24 May 07 12:38:38 PM PDT 24 8505874186 ps
T80 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_hw_reset.3703337475 May 07 12:38:19 PM PDT 24 May 07 12:38:38 PM PDT 24 2061879637 ps
T394 /workspace/coverage/cover_reg_top/6.rom_ctrl_same_csr_outstanding.1844334999 May 07 12:38:38 PM PDT 24 May 07 12:38:56 PM PDT 24 8353905843 ps
T395 /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_errors.261370275 May 07 12:38:50 PM PDT 24 May 07 12:39:07 PM PDT 24 1457659507 ps
T81 /workspace/coverage/cover_reg_top/3.rom_ctrl_passthru_mem_tl_intg_err.1230678125 May 07 12:38:26 PM PDT 24 May 07 12:39:27 PM PDT 24 28840937752 ps
T396 /workspace/coverage/cover_reg_top/2.rom_ctrl_same_csr_outstanding.342062299 May 07 12:38:27 PM PDT 24 May 07 12:38:34 PM PDT 24 338053335 ps
T397 /workspace/coverage/cover_reg_top/18.rom_ctrl_same_csr_outstanding.146033122 May 07 12:38:41 PM PDT 24 May 07 12:38:55 PM PDT 24 2842791125 ps
T398 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_aliasing.1169019295 May 07 12:38:33 PM PDT 24 May 07 12:38:39 PM PDT 24 168130052 ps
T399 /workspace/coverage/cover_reg_top/7.rom_ctrl_same_csr_outstanding.931549686 May 07 12:38:13 PM PDT 24 May 07 12:38:29 PM PDT 24 7453069159 ps
T400 /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_errors.714382718 May 07 12:38:52 PM PDT 24 May 07 12:39:04 PM PDT 24 2119979999 ps
T116 /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_intg_err.1243656817 May 07 12:38:45 PM PDT 24 May 07 12:39:29 PM PDT 24 4950267612 ps
T401 /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_partial_access.426159966 May 07 12:38:13 PM PDT 24 May 07 12:38:21 PM PDT 24 347290338 ps
T402 /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_walk.1518654617 May 07 12:38:14 PM PDT 24 May 07 12:38:29 PM PDT 24 1183638687 ps
T82 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_rw.2279386449 May 07 12:38:15 PM PDT 24 May 07 12:38:29 PM PDT 24 1223149671 ps
T403 /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_walk.2053225474 May 07 12:38:47 PM PDT 24 May 07 12:38:53 PM PDT 24 347593393 ps
T404 /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_mem_rw_with_rand_reset.15735431 May 07 12:38:47 PM PDT 24 May 07 12:39:03 PM PDT 24 1566267425 ps
T405 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_rw.2110302633 May 07 12:38:22 PM PDT 24 May 07 12:38:32 PM PDT 24 6432519139 ps
T406 /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_partial_access.3976697490 May 07 12:38:12 PM PDT 24 May 07 12:38:23 PM PDT 24 802772500 ps
T117 /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_intg_err.545947176 May 07 12:38:42 PM PDT 24 May 07 12:39:28 PM PDT 24 3378786217 ps
T85 /workspace/coverage/cover_reg_top/5.rom_ctrl_passthru_mem_tl_intg_err.514264283 May 07 12:38:21 PM PDT 24 May 07 12:39:30 PM PDT 24 31799609064 ps
T407 /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_errors.673830056 May 07 12:38:14 PM PDT 24 May 07 12:38:27 PM PDT 24 2128032774 ps
T408 /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_errors.2728857996 May 07 12:38:21 PM PDT 24 May 07 12:38:37 PM PDT 24 1037824383 ps
T113 /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_intg_err.1889991021 May 07 12:38:26 PM PDT 24 May 07 12:39:47 PM PDT 24 35502040239 ps
T409 /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_rw.3143909596 May 07 12:38:35 PM PDT 24 May 07 12:38:50 PM PDT 24 1436123114 ps
T410 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_bit_bash.3784028159 May 07 12:38:26 PM PDT 24 May 07 12:38:31 PM PDT 24 89085886 ps
T411 /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_mem_rw_with_rand_reset.3157186087 May 07 12:38:26 PM PDT 24 May 07 12:38:32 PM PDT 24 95475086 ps
T412 /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_rw.3546530754 May 07 12:38:23 PM PDT 24 May 07 12:38:29 PM PDT 24 171347235 ps
T413 /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_rw.1383492607 May 07 12:38:19 PM PDT 24 May 07 12:38:32 PM PDT 24 2416814215 ps
T414 /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_errors.3316764802 May 07 12:38:28 PM PDT 24 May 07 12:38:44 PM PDT 24 2704919546 ps
T415 /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_errors.663646057 May 07 12:38:31 PM PDT 24 May 07 12:38:40 PM PDT 24 824744600 ps
T114 /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_intg_err.134761648 May 07 12:38:41 PM PDT 24 May 07 12:40:00 PM PDT 24 6159512012 ps
T416 /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_rw.1427049621 May 07 12:38:39 PM PDT 24 May 07 12:38:47 PM PDT 24 5296805870 ps
T417 /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_errors.602574779 May 07 12:38:26 PM PDT 24 May 07 12:38:47 PM PDT 24 1887772200 ps
T418 /workspace/coverage/cover_reg_top/9.rom_ctrl_passthru_mem_tl_intg_err.3243387048 May 07 12:38:34 PM PDT 24 May 07 12:39:35 PM PDT 24 7707272342 ps
T419 /workspace/coverage/cover_reg_top/3.rom_ctrl_same_csr_outstanding.4240772965 May 07 12:38:20 PM PDT 24 May 07 12:38:25 PM PDT 24 86391951 ps
T420 /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_mem_rw_with_rand_reset.1206068595 May 07 12:38:37 PM PDT 24 May 07 12:38:47 PM PDT 24 13483928126 ps
T421 /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_errors.2888437143 May 07 12:38:32 PM PDT 24 May 07 12:38:49 PM PDT 24 6759593845 ps
T119 /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_intg_err.3214024088 May 07 12:38:20 PM PDT 24 May 07 12:39:03 PM PDT 24 1292955958 ps
T118 /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_intg_err.4172657033 May 07 12:38:27 PM PDT 24 May 07 12:39:39 PM PDT 24 530435813 ps
T422 /workspace/coverage/cover_reg_top/6.rom_ctrl_passthru_mem_tl_intg_err.2392856824 May 07 12:38:23 PM PDT 24 May 07 12:38:54 PM PDT 24 6725916096 ps
T423 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_mem_rw_with_rand_reset.3223461571 May 07 12:38:24 PM PDT 24 May 07 12:38:35 PM PDT 24 1566733630 ps
T120 /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_intg_err.1095770068 May 07 12:38:36 PM PDT 24 May 07 12:39:48 PM PDT 24 622457938 ps
T424 /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_walk.823740343 May 07 12:38:17 PM PDT 24 May 07 12:38:31 PM PDT 24 13074630451 ps
T425 /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_mem_rw_with_rand_reset.985610090 May 07 12:38:31 PM PDT 24 May 07 12:38:37 PM PDT 24 611345692 ps
T426 /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_rw.2177210026 May 07 12:38:54 PM PDT 24 May 07 12:39:02 PM PDT 24 622236909 ps
T427 /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_errors.1381703544 May 07 12:38:53 PM PDT 24 May 07 12:39:05 PM PDT 24 1372360956 ps
T83 /workspace/coverage/cover_reg_top/8.rom_ctrl_passthru_mem_tl_intg_err.3249099182 May 07 12:38:14 PM PDT 24 May 07 12:39:10 PM PDT 24 11786610308 ps
T428 /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_partial_access.3748417824 May 07 12:38:23 PM PDT 24 May 07 12:38:40 PM PDT 24 7718363737 ps
T429 /workspace/coverage/cover_reg_top/12.rom_ctrl_same_csr_outstanding.4040086989 May 07 12:38:41 PM PDT 24 May 07 12:39:00 PM PDT 24 1921221354 ps
T430 /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_mem_rw_with_rand_reset.2313529791 May 07 12:38:37 PM PDT 24 May 07 12:38:52 PM PDT 24 3323641620 ps
T122 /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_intg_err.2396367966 May 07 12:38:43 PM PDT 24 May 07 12:39:31 PM PDT 24 11992214613 ps
T431 /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_mem_rw_with_rand_reset.3836933166 May 07 12:38:41 PM PDT 24 May 07 12:38:46 PM PDT 24 95674059 ps
T432 /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_errors.3276877535 May 07 12:38:15 PM PDT 24 May 07 12:38:31 PM PDT 24 1193057804 ps
T433 /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_intg_err.4156622398 May 07 12:38:36 PM PDT 24 May 07 12:39:48 PM PDT 24 2042192488 ps
T434 /workspace/coverage/cover_reg_top/16.rom_ctrl_passthru_mem_tl_intg_err.2721788416 May 07 12:38:48 PM PDT 24 May 07 12:40:32 PM PDT 24 69908894451 ps
T435 /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_mem_rw_with_rand_reset.3730033879 May 07 12:38:14 PM PDT 24 May 07 12:38:26 PM PDT 24 975127950 ps
T436 /workspace/coverage/cover_reg_top/14.rom_ctrl_same_csr_outstanding.183258106 May 07 12:38:47 PM PDT 24 May 07 12:38:53 PM PDT 24 175438172 ps
T437 /workspace/coverage/cover_reg_top/15.rom_ctrl_same_csr_outstanding.4031056965 May 07 12:38:42 PM PDT 24 May 07 12:38:55 PM PDT 24 3657814308 ps
T438 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_mem_rw_with_rand_reset.1680442855 May 07 12:38:37 PM PDT 24 May 07 12:38:43 PM PDT 24 534148898 ps
T439 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_bit_bash.1051553299 May 07 12:38:27 PM PDT 24 May 07 12:38:41 PM PDT 24 1370766814 ps
T440 /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_errors.2583129589 May 07 12:38:14 PM PDT 24 May 07 12:38:27 PM PDT 24 595593655 ps
T84 /workspace/coverage/cover_reg_top/19.rom_ctrl_passthru_mem_tl_intg_err.1132334153 May 07 12:38:30 PM PDT 24 May 07 12:38:58 PM PDT 24 2337987915 ps
T441 /workspace/coverage/cover_reg_top/17.rom_ctrl_same_csr_outstanding.4185341523 May 07 12:38:36 PM PDT 24 May 07 12:38:47 PM PDT 24 2430233545 ps
T442 /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_rw.57635441 May 07 12:38:43 PM PDT 24 May 07 12:38:58 PM PDT 24 5736188646 ps
T443 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_rw.4007749241 May 07 12:38:18 PM PDT 24 May 07 12:38:34 PM PDT 24 6339818353 ps
T121 /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_intg_err.2299827727 May 07 12:38:55 PM PDT 24 May 07 12:40:07 PM PDT 24 474408407 ps
T444 /workspace/coverage/cover_reg_top/17.rom_ctrl_passthru_mem_tl_intg_err.529700742 May 07 12:38:46 PM PDT 24 May 07 12:39:24 PM PDT 24 2694557760 ps
T445 /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_intg_err.936604456 May 07 12:38:40 PM PDT 24 May 07 12:39:24 PM PDT 24 5433254155 ps
T446 /workspace/coverage/cover_reg_top/10.rom_ctrl_passthru_mem_tl_intg_err.1930785786 May 07 12:38:36 PM PDT 24 May 07 12:39:40 PM PDT 24 100708723135 ps
T447 /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_rw.648298286 May 07 12:38:26 PM PDT 24 May 07 12:38:43 PM PDT 24 8241456700 ps
T448 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_hw_reset.2519273955 May 07 12:38:45 PM PDT 24 May 07 12:39:06 PM PDT 24 2103129195 ps
T449 /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_errors.2887282389 May 07 12:38:32 PM PDT 24 May 07 12:38:43 PM PDT 24 468980468 ps
T450 /workspace/coverage/cover_reg_top/16.rom_ctrl_same_csr_outstanding.145869090 May 07 12:38:48 PM PDT 24 May 07 12:38:57 PM PDT 24 373595045 ps
T451 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_aliasing.373875428 May 07 12:38:23 PM PDT 24 May 07 12:38:38 PM PDT 24 1626583089 ps
T452 /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_errors.3057109817 May 07 12:38:36 PM PDT 24 May 07 12:38:50 PM PDT 24 984781826 ps
T453 /workspace/coverage/cover_reg_top/4.rom_ctrl_passthru_mem_tl_intg_err.2568465271 May 07 12:38:26 PM PDT 24 May 07 12:39:16 PM PDT 24 5716013248 ps
T123 /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_intg_err.3380161679 May 07 12:38:34 PM PDT 24 May 07 12:39:46 PM PDT 24 555233636 ps
T454 /workspace/coverage/cover_reg_top/13.rom_ctrl_passthru_mem_tl_intg_err.1002767738 May 07 12:38:21 PM PDT 24 May 07 12:38:49 PM PDT 24 2355026595 ps
T125 /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_intg_err.4273205304 May 07 12:38:19 PM PDT 24 May 07 12:39:04 PM PDT 24 13356521121 ps
T455 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_hw_reset.2839575411 May 07 12:38:31 PM PDT 24 May 07 12:38:39 PM PDT 24 91384219 ps
T456 /workspace/coverage/cover_reg_top/2.rom_ctrl_passthru_mem_tl_intg_err.2985282581 May 07 12:38:26 PM PDT 24 May 07 12:39:00 PM PDT 24 5659458367 ps
T457 /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_errors.2698872562 May 07 12:38:09 PM PDT 24 May 07 12:38:31 PM PDT 24 7528287209 ps
T458 /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_mem_rw_with_rand_reset.3471610172 May 07 12:38:31 PM PDT 24 May 07 12:38:44 PM PDT 24 9875300596 ps
T124 /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_intg_err.2479620244 May 07 12:38:19 PM PDT 24 May 07 12:38:57 PM PDT 24 698803100 ps
T459 /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_partial_access.1641034013 May 07 12:38:46 PM PDT 24 May 07 12:38:52 PM PDT 24 130237647 ps
T460 /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_rw.581867981 May 07 12:38:48 PM PDT 24 May 07 12:39:05 PM PDT 24 1973681609 ps
T461 /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_intg_err.2287840592 May 07 12:38:40 PM PDT 24 May 07 12:39:51 PM PDT 24 274847468 ps
T462 /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_intg_err.1727854880 May 07 12:38:27 PM PDT 24 May 07 12:39:40 PM PDT 24 276799109 ps

Test location /workspace/coverage/default/14.rom_ctrl_stress_all_with_rand_reset.1859531482
Short name T2
Test name
Test status
Simulation time 129381559606 ps
CPU time 2535.84 seconds
Started May 07 12:38:53 PM PDT 24
Finished May 07 01:21:11 PM PDT 24
Peak memory 239280 kb
Host smart-95d1700f-5dc8-40e3-a8a1-7b98108c9586
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1859531482 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_stress_all_with_rand_reset.1859531482
Directory /workspace/14.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/23.rom_ctrl_corrupt_sig_fatal_chk.3749773115
Short name T8
Test name
Test status
Simulation time 239586958355 ps
CPU time 227 seconds
Started May 07 12:39:12 PM PDT 24
Finished May 07 12:43:01 PM PDT 24
Peak memory 234328 kb
Host smart-8f89c6e2-0bad-4f25-b170-a06dc43e3321
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3749773115 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_
corrupt_sig_fatal_chk.3749773115
Directory /workspace/23.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/11.rom_ctrl_corrupt_sig_fatal_chk.1478606323
Short name T19
Test name
Test status
Simulation time 41564671741 ps
CPU time 187.76 seconds
Started May 07 12:38:56 PM PDT 24
Finished May 07 12:42:07 PM PDT 24
Peak memory 238272 kb
Host smart-dd9f4c30-5f23-44f8-b4de-19c84a43899c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1478606323 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_
corrupt_sig_fatal_chk.1478606323
Directory /workspace/11.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_intg_err.2426018221
Short name T50
Test name
Test status
Simulation time 1988842686 ps
CPU time 81.38 seconds
Started May 07 12:38:21 PM PDT 24
Finished May 07 12:39:44 PM PDT 24
Peak memory 211420 kb
Host smart-89216141-2b63-4575-9cad-23cd761b1969
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2426018221 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_tl_in
tg_err.2426018221
Directory /workspace/1.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/17.rom_ctrl_stress_all_with_rand_reset.1429812432
Short name T43
Test name
Test status
Simulation time 79724911380 ps
CPU time 2710.29 seconds
Started May 07 12:38:55 PM PDT 24
Finished May 07 01:24:08 PM PDT 24
Peak memory 240580 kb
Host smart-cde399fb-1ac2-4bd3-8385-bc08a8ff662d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1429812432 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_stress_all_with_rand_reset.1429812432
Directory /workspace/17.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.rom_ctrl_sec_cm.1828023252
Short name T9
Test name
Test status
Simulation time 3750973087 ps
CPU time 124.44 seconds
Started May 07 12:39:00 PM PDT 24
Finished May 07 12:41:08 PM PDT 24
Peak memory 242644 kb
Host smart-2e2f711e-19d2-4414-9d0c-ac3e033b049e
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1828023252 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_sec_cm.1828023252
Directory /workspace/3.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_passthru_mem_tl_intg_err.3793491871
Short name T68
Test name
Test status
Simulation time 16596206656 ps
CPU time 43.55 seconds
Started May 07 12:38:25 PM PDT 24
Finished May 07 12:39:09 PM PDT 24
Peak memory 210632 kb
Host smart-434aa922-6be2-4d21-9ee1-c69bd4e06572
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3793491871 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_pa
ssthru_mem_tl_intg_err.3793491871
Directory /workspace/7.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/default/22.rom_ctrl_corrupt_sig_fatal_chk.4198665405
Short name T39
Test name
Test status
Simulation time 2545086153 ps
CPU time 148.24 seconds
Started May 07 12:39:16 PM PDT 24
Finished May 07 12:41:46 PM PDT 24
Peak memory 213452 kb
Host smart-f0b90c30-5234-42e5-9237-1358852c0a4c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4198665405 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_
corrupt_sig_fatal_chk.4198665405
Directory /workspace/22.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_intg_err.4264871638
Short name T49
Test name
Test status
Simulation time 864982554 ps
CPU time 68.26 seconds
Started May 07 12:38:46 PM PDT 24
Finished May 07 12:39:56 PM PDT 24
Peak memory 210700 kb
Host smart-da0407bc-7ef9-47c2-872d-03091d0f18d5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4264871638 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_tl_in
tg_err.4264871638
Directory /workspace/7.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/14.rom_ctrl_alert_test.3984349067
Short name T4
Test name
Test status
Simulation time 348225815 ps
CPU time 4.3 seconds
Started May 07 12:38:54 PM PDT 24
Finished May 07 12:39:02 PM PDT 24
Peak memory 211624 kb
Host smart-42811499-724f-49b3-b6f6-0d201438754c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3984349067 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_alert_test.3984349067
Directory /workspace/14.rom_ctrl_alert_test/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_passthru_mem_tl_intg_err.3478115011
Short name T64
Test name
Test status
Simulation time 580653078 ps
CPU time 26.76 seconds
Started May 07 12:38:29 PM PDT 24
Finished May 07 12:39:03 PM PDT 24
Peak memory 210564 kb
Host smart-2b3d9616-78fd-4685-91ac-687a7f875680
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3478115011 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_p
assthru_mem_tl_intg_err.3478115011
Directory /workspace/14.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/default/40.rom_ctrl_kmac_err_chk.3366415173
Short name T153
Test name
Test status
Simulation time 2137244291 ps
CPU time 16.07 seconds
Started May 07 12:39:13 PM PDT 24
Finished May 07 12:39:31 PM PDT 24
Peak memory 212456 kb
Host smart-66f65588-bcbb-49c0-be4f-df2ed83a3b3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3366415173 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_kmac_err_chk.3366415173
Directory /workspace/40.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/1.rom_ctrl_kmac_err_chk.1598344118
Short name T130
Test name
Test status
Simulation time 4615092698 ps
CPU time 23.62 seconds
Started May 07 12:38:52 PM PDT 24
Finished May 07 12:39:17 PM PDT 24
Peak memory 212704 kb
Host smart-0316e8bf-69fa-4727-8094-15d599ffb7d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1598344118 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_kmac_err_chk.1598344118
Directory /workspace/1.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/25.rom_ctrl_kmac_err_chk.3510539039
Short name T20
Test name
Test status
Simulation time 2146277274 ps
CPU time 22.96 seconds
Started May 07 12:38:59 PM PDT 24
Finished May 07 12:39:25 PM PDT 24
Peak memory 212016 kb
Host smart-9b089ea3-e25d-4a74-aef4-f7a836c2a00f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3510539039 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_kmac_err_chk.3510539039
Directory /workspace/25.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_intg_err.3380161679
Short name T123
Test name
Test status
Simulation time 555233636 ps
CPU time 69.69 seconds
Started May 07 12:38:34 PM PDT 24
Finished May 07 12:39:46 PM PDT 24
Peak memory 218784 kb
Host smart-941720e1-d8ac-45f9-8f93-4d677c5843a9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3380161679 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_tl_i
ntg_err.3380161679
Directory /workspace/16.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/17.rom_ctrl_smoke.2247477393
Short name T36
Test name
Test status
Simulation time 6705941925 ps
CPU time 17.47 seconds
Started May 07 12:39:00 PM PDT 24
Finished May 07 12:39:22 PM PDT 24
Peak memory 219992 kb
Host smart-84338bcf-0688-481a-98fe-f4e3a27511d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2247477393 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_smoke.2247477393
Directory /workspace/17.rom_ctrl_smoke/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_intg_err.2479620244
Short name T124
Test name
Test status
Simulation time 698803100 ps
CPU time 36.22 seconds
Started May 07 12:38:19 PM PDT 24
Finished May 07 12:38:57 PM PDT 24
Peak memory 210532 kb
Host smart-e263effb-c7ea-4cc6-91f7-b85b28b3ff99
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2479620244 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_tl_in
tg_err.2479620244
Directory /workspace/0.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/41.rom_ctrl_stress_all_with_rand_reset.1866195010
Short name T44
Test name
Test status
Simulation time 119274085063 ps
CPU time 4802.08 seconds
Started May 07 12:39:29 PM PDT 24
Finished May 07 01:59:32 PM PDT 24
Peak memory 252556 kb
Host smart-339b5982-6553-4811-b228-71aa322ffc51
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1866195010 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_stress_all_with_rand_reset.1866195010
Directory /workspace/41.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/18.rom_ctrl_corrupt_sig_fatal_chk.554555994
Short name T26
Test name
Test status
Simulation time 5132552761 ps
CPU time 94.73 seconds
Started May 07 12:39:08 PM PDT 24
Finished May 07 12:40:45 PM PDT 24
Peak memory 238316 kb
Host smart-19bca2e3-d8fc-4085-bc6f-96674afeaa07
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=554555994 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_c
orrupt_sig_fatal_chk.554555994
Directory /workspace/18.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/36.rom_ctrl_max_throughput_chk.1086431302
Short name T101
Test name
Test status
Simulation time 97358046 ps
CPU time 5.34 seconds
Started May 07 12:39:12 PM PDT 24
Finished May 07 12:39:19 PM PDT 24
Peak memory 211664 kb
Host smart-1f8504e6-a1e0-4b5e-abae-a58419dfc968
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1086431302 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_max_throughput_chk.1086431302
Directory /workspace/36.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_aliasing.378043122
Short name T61
Test name
Test status
Simulation time 10097523974 ps
CPU time 14.3 seconds
Started May 07 12:38:30 PM PDT 24
Finished May 07 12:38:45 PM PDT 24
Peak memory 210632 kb
Host smart-e81745fd-03d0-4742-b0e7-c8c5f2fdeb72
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=378043122 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_alias
ing.378043122
Directory /workspace/0.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_bit_bash.1954916823
Short name T377
Test name
Test status
Simulation time 1820361273 ps
CPU time 15.17 seconds
Started May 07 12:38:32 PM PDT 24
Finished May 07 12:38:48 PM PDT 24
Peak memory 210604 kb
Host smart-f3459f1b-cede-465f-9e6a-bbc7de1ec58c
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1954916823 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_bit_
bash.1954916823
Directory /workspace/0.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_hw_reset.4047411431
Short name T371
Test name
Test status
Simulation time 1805914514 ps
CPU time 12.47 seconds
Started May 07 12:38:35 PM PDT 24
Finished May 07 12:38:48 PM PDT 24
Peak memory 210560 kb
Host smart-c9e522d1-7b83-40e5-b60c-577319deafe7
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4047411431 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_hw_r
eset.4047411431
Directory /workspace/0.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_mem_rw_with_rand_reset.1680442855
Short name T438
Test name
Test status
Simulation time 534148898 ps
CPU time 4.88 seconds
Started May 07 12:38:37 PM PDT 24
Finished May 07 12:38:43 PM PDT 24
Peak memory 218744 kb
Host smart-4f3d6ea3-ca7b-45dd-bfd1-dfa130fa1303
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1680442855 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 0.rom_ctrl_csr_mem_rw_with_rand_reset.1680442855
Directory /workspace/0.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_rw.3294083868
Short name T381
Test name
Test status
Simulation time 4902095644 ps
CPU time 10.27 seconds
Started May 07 12:38:31 PM PDT 24
Finished May 07 12:38:43 PM PDT 24
Peak memory 210620 kb
Host smart-c6340deb-9ff8-483e-a8b4-650fab7f6bd8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3294083868 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_rw.3294083868
Directory /workspace/0.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_partial_access.426159966
Short name T401
Test name
Test status
Simulation time 347290338 ps
CPU time 4 seconds
Started May 07 12:38:13 PM PDT 24
Finished May 07 12:38:21 PM PDT 24
Peak memory 210420 kb
Host smart-b9157fd0-e0f5-4539-ac46-a0d85ad2af68
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=426159966 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl
_mem_partial_access.426159966
Directory /workspace/0.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_walk.2053225474
Short name T403
Test name
Test status
Simulation time 347593393 ps
CPU time 3.9 seconds
Started May 07 12:38:47 PM PDT 24
Finished May 07 12:38:53 PM PDT 24
Peak memory 210456 kb
Host smart-8abc2d32-82a1-4e7d-a434-296bcb259460
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2053225474 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_mem_walk
.2053225474
Directory /workspace/0.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_passthru_mem_tl_intg_err.2326414218
Short name T382
Test name
Test status
Simulation time 10862498865 ps
CPU time 51.25 seconds
Started May 07 12:38:35 PM PDT 24
Finished May 07 12:39:28 PM PDT 24
Peak memory 210676 kb
Host smart-9ef94e85-59d8-4576-bcb3-e0d5e0fc8b08
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2326414218 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_pa
ssthru_mem_tl_intg_err.2326414218
Directory /workspace/0.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_same_csr_outstanding.3080231307
Short name T97
Test name
Test status
Simulation time 91254361 ps
CPU time 5.93 seconds
Started May 07 12:38:31 PM PDT 24
Finished May 07 12:38:38 PM PDT 24
Peak memory 210512 kb
Host smart-10fdfb22-c5b5-43d3-8cbe-6b91f094fb37
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3080231307 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_c
trl_same_csr_outstanding.3080231307
Directory /workspace/0.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_errors.2698872562
Short name T457
Test name
Test status
Simulation time 7528287209 ps
CPU time 17.83 seconds
Started May 07 12:38:09 PM PDT 24
Finished May 07 12:38:31 PM PDT 24
Peak memory 214996 kb
Host smart-22dc3f3d-8467-45a9-a173-a78b3ee3a901
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2698872562 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_tl_errors.2698872562
Directory /workspace/0.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_aliasing.2133991436
Short name T79
Test name
Test status
Simulation time 8505874186 ps
CPU time 16.21 seconds
Started May 07 12:38:20 PM PDT 24
Finished May 07 12:38:38 PM PDT 24
Peak memory 210640 kb
Host smart-06aaabfd-c9b7-4bef-92f5-6f0c3398c799
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2133991436 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_alia
sing.2133991436
Directory /workspace/1.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_bit_bash.8888103
Short name T78
Test name
Test status
Simulation time 1375910911 ps
CPU time 6.69 seconds
Started May 07 12:38:22 PM PDT 24
Finished May 07 12:38:30 PM PDT 24
Peak memory 210568 kb
Host smart-7201afd0-082f-491b-afa1-e9aeda8e7aa0
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=8888103 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_bit_bas
h.8888103
Directory /workspace/1.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_hw_reset.3703337475
Short name T80
Test name
Test status
Simulation time 2061879637 ps
CPU time 17.22 seconds
Started May 07 12:38:19 PM PDT 24
Finished May 07 12:38:38 PM PDT 24
Peak memory 210544 kb
Host smart-589d50fd-9a7d-4bdd-ad53-9fd4e17de8a1
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3703337475 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_hw_r
eset.3703337475
Directory /workspace/1.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_mem_rw_with_rand_reset.4259819592
Short name T378
Test name
Test status
Simulation time 412279161 ps
CPU time 5.22 seconds
Started May 07 12:38:47 PM PDT 24
Finished May 07 12:38:54 PM PDT 24
Peak memory 218720 kb
Host smart-86b5ec11-0820-4ced-8696-59cc51629cc9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4259819592 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 1.rom_ctrl_csr_mem_rw_with_rand_reset.4259819592
Directory /workspace/1.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_rw.2279386449
Short name T82
Test name
Test status
Simulation time 1223149671 ps
CPU time 11.3 seconds
Started May 07 12:38:15 PM PDT 24
Finished May 07 12:38:29 PM PDT 24
Peak memory 210540 kb
Host smart-e952404e-61a9-4ed8-8045-841d6a59640d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2279386449 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_rw.2279386449
Directory /workspace/1.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_partial_access.1641034013
Short name T459
Test name
Test status
Simulation time 130237647 ps
CPU time 5 seconds
Started May 07 12:38:46 PM PDT 24
Finished May 07 12:38:52 PM PDT 24
Peak memory 210444 kb
Host smart-1c28986d-f50a-4787-9ceb-31aec9631a05
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1641034013 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctr
l_mem_partial_access.1641034013
Directory /workspace/1.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_walk.1518654617
Short name T402
Test name
Test status
Simulation time 1183638687 ps
CPU time 11.25 seconds
Started May 07 12:38:14 PM PDT 24
Finished May 07 12:38:29 PM PDT 24
Peak memory 210448 kb
Host smart-2c63cb86-001b-4e35-9ca2-61cfb8a5a216
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1518654617 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_mem_walk
.1518654617
Directory /workspace/1.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_passthru_mem_tl_intg_err.3856394615
Short name T96
Test name
Test status
Simulation time 2772217609 ps
CPU time 18.92 seconds
Started May 07 12:38:11 PM PDT 24
Finished May 07 12:38:35 PM PDT 24
Peak memory 210540 kb
Host smart-1028063f-c15d-49a8-bf29-8386da4e31f2
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3856394615 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_pa
ssthru_mem_tl_intg_err.3856394615
Directory /workspace/1.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_same_csr_outstanding.3809218768
Short name T98
Test name
Test status
Simulation time 519785630 ps
CPU time 6.14 seconds
Started May 07 12:38:25 PM PDT 24
Finished May 07 12:38:33 PM PDT 24
Peak memory 210564 kb
Host smart-87bdb97e-91f4-41e8-ab12-e2cbdd3331e6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3809218768 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_c
trl_same_csr_outstanding.3809218768
Directory /workspace/1.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_errors.3057109817
Short name T452
Test name
Test status
Simulation time 984781826 ps
CPU time 12.86 seconds
Started May 07 12:38:36 PM PDT 24
Finished May 07 12:38:50 PM PDT 24
Peak memory 218696 kb
Host smart-d61c0f72-d4d1-4f48-9974-6977cafc4424
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3057109817 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_tl_errors.3057109817
Directory /workspace/1.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_mem_rw_with_rand_reset.3836933166
Short name T431
Test name
Test status
Simulation time 95674059 ps
CPU time 4.95 seconds
Started May 07 12:38:41 PM PDT 24
Finished May 07 12:38:46 PM PDT 24
Peak memory 218772 kb
Host smart-c47b976f-362d-45ad-a67a-6f72d9b53f8d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3836933166 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 10.rom_ctrl_csr_mem_rw_with_rand_reset.3836933166
Directory /workspace/10.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_rw.3570371008
Short name T67
Test name
Test status
Simulation time 20326516019 ps
CPU time 13.98 seconds
Started May 07 12:38:25 PM PDT 24
Finished May 07 12:38:40 PM PDT 24
Peak memory 210580 kb
Host smart-d362f971-76fb-4200-8764-a40fe2b3bbe7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3570371008 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_csr_rw.3570371008
Directory /workspace/10.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_passthru_mem_tl_intg_err.1930785786
Short name T446
Test name
Test status
Simulation time 100708723135 ps
CPU time 62.42 seconds
Started May 07 12:38:36 PM PDT 24
Finished May 07 12:39:40 PM PDT 24
Peak memory 210700 kb
Host smart-4574722c-375f-41fd-95ab-55170b71a512
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1930785786 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_p
assthru_mem_tl_intg_err.1930785786
Directory /workspace/10.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_same_csr_outstanding.2445196453
Short name T100
Test name
Test status
Simulation time 372798475 ps
CPU time 6.26 seconds
Started May 07 12:38:30 PM PDT 24
Finished May 07 12:38:38 PM PDT 24
Peak memory 210764 kb
Host smart-66d4a000-c7d8-442d-8392-64d297864e6e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2445196453 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_
ctrl_same_csr_outstanding.2445196453
Directory /workspace/10.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_errors.663646057
Short name T415
Test name
Test status
Simulation time 824744600 ps
CPU time 7.81 seconds
Started May 07 12:38:31 PM PDT 24
Finished May 07 12:38:40 PM PDT 24
Peak memory 218828 kb
Host smart-c44dbcc5-1dc4-4a65-a5b3-d6bb122d8e7a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=663646057 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_tl_errors.663646057
Directory /workspace/10.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_intg_err.1727854880
Short name T462
Test name
Test status
Simulation time 276799109 ps
CPU time 71.25 seconds
Started May 07 12:38:27 PM PDT 24
Finished May 07 12:39:40 PM PDT 24
Peak memory 211500 kb
Host smart-fb446721-47a5-497b-b151-430b4a79911b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1727854880 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_tl_i
ntg_err.1727854880
Directory /workspace/10.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_mem_rw_with_rand_reset.2313529791
Short name T430
Test name
Test status
Simulation time 3323641620 ps
CPU time 14.08 seconds
Started May 07 12:38:37 PM PDT 24
Finished May 07 12:38:52 PM PDT 24
Peak memory 218796 kb
Host smart-3a21fa32-20f7-42a1-b73b-5a939ab088e3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2313529791 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 11.rom_ctrl_csr_mem_rw_with_rand_reset.2313529791
Directory /workspace/11.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_rw.3546530754
Short name T412
Test name
Test status
Simulation time 171347235 ps
CPU time 4.2 seconds
Started May 07 12:38:23 PM PDT 24
Finished May 07 12:38:29 PM PDT 24
Peak memory 210520 kb
Host smart-784a24f1-3016-4de6-bab7-13383e12e2fa
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3546530754 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_csr_rw.3546530754
Directory /workspace/11.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_passthru_mem_tl_intg_err.200168024
Short name T60
Test name
Test status
Simulation time 12551455347 ps
CPU time 103.46 seconds
Started May 07 12:38:47 PM PDT 24
Finished May 07 12:40:33 PM PDT 24
Peak memory 210556 kb
Host smart-936c2d31-d107-4ae2-a8c7-f97756e4dc4b
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=200168024 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_pa
ssthru_mem_tl_intg_err.200168024
Directory /workspace/11.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_same_csr_outstanding.1172940994
Short name T384
Test name
Test status
Simulation time 667630257 ps
CPU time 10.14 seconds
Started May 07 12:38:31 PM PDT 24
Finished May 07 12:38:42 PM PDT 24
Peak memory 210528 kb
Host smart-49f60922-4984-4cf3-8ba5-dea3af97701c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1172940994 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_
ctrl_same_csr_outstanding.1172940994
Directory /workspace/11.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_errors.602574779
Short name T417
Test name
Test status
Simulation time 1887772200 ps
CPU time 18.89 seconds
Started May 07 12:38:26 PM PDT 24
Finished May 07 12:38:47 PM PDT 24
Peak memory 218800 kb
Host smart-804f0dd7-bce1-44c3-b6e6-978c6e5c9d77
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=602574779 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_tl_errors.602574779
Directory /workspace/11.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_intg_err.2287840592
Short name T461
Test name
Test status
Simulation time 274847468 ps
CPU time 69.95 seconds
Started May 07 12:38:40 PM PDT 24
Finished May 07 12:39:51 PM PDT 24
Peak memory 211688 kb
Host smart-820f34f8-3edb-4d64-be1b-988af42d1ff9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2287840592 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_tl_i
ntg_err.2287840592
Directory /workspace/11.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_mem_rw_with_rand_reset.3471610172
Short name T458
Test name
Test status
Simulation time 9875300596 ps
CPU time 11.7 seconds
Started May 07 12:38:31 PM PDT 24
Finished May 07 12:38:44 PM PDT 24
Peak memory 213552 kb
Host smart-c0e11682-a5ce-458b-b650-8ba799ec73aa
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3471610172 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 12.rom_ctrl_csr_mem_rw_with_rand_reset.3471610172
Directory /workspace/12.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_rw.648298286
Short name T447
Test name
Test status
Simulation time 8241456700 ps
CPU time 16.29 seconds
Started May 07 12:38:26 PM PDT 24
Finished May 07 12:38:43 PM PDT 24
Peak memory 210604 kb
Host smart-cd80b271-8e88-4580-b00c-0fc3eea65a9c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=648298286 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_csr_rw.648298286
Directory /workspace/12.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_passthru_mem_tl_intg_err.3242852334
Short name T77
Test name
Test status
Simulation time 21953505634 ps
CPU time 50.03 seconds
Started May 07 12:38:35 PM PDT 24
Finished May 07 12:39:27 PM PDT 24
Peak memory 210632 kb
Host smart-d29d9a33-5c67-4770-8fd3-eb5dc0c9482d
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3242852334 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_p
assthru_mem_tl_intg_err.3242852334
Directory /workspace/12.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_same_csr_outstanding.4040086989
Short name T429
Test name
Test status
Simulation time 1921221354 ps
CPU time 17.59 seconds
Started May 07 12:38:41 PM PDT 24
Finished May 07 12:39:00 PM PDT 24
Peak memory 210544 kb
Host smart-f4004d0c-a810-4f9b-8c01-fe03e4bec5a1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4040086989 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_
ctrl_same_csr_outstanding.4040086989
Directory /workspace/12.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_errors.3385430869
Short name T366
Test name
Test status
Simulation time 903812973 ps
CPU time 10.13 seconds
Started May 07 12:38:40 PM PDT 24
Finished May 07 12:38:51 PM PDT 24
Peak memory 218624 kb
Host smart-9ea0562a-afe9-4227-93cf-96a3b5342be9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3385430869 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_tl_errors.3385430869
Directory /workspace/12.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_intg_err.1889991021
Short name T113
Test name
Test status
Simulation time 35502040239 ps
CPU time 80.46 seconds
Started May 07 12:38:26 PM PDT 24
Finished May 07 12:39:47 PM PDT 24
Peak memory 210752 kb
Host smart-02bad262-d97c-4184-804d-d0dcb8fb52b6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1889991021 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_tl_i
ntg_err.1889991021
Directory /workspace/12.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_mem_rw_with_rand_reset.3195677931
Short name T387
Test name
Test status
Simulation time 3122494656 ps
CPU time 9.16 seconds
Started May 07 12:38:24 PM PDT 24
Finished May 07 12:38:35 PM PDT 24
Peak memory 218840 kb
Host smart-580716ae-94bf-418b-b1e1-bb0c9633ed8a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3195677931 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 13.rom_ctrl_csr_mem_rw_with_rand_reset.3195677931
Directory /workspace/13.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_rw.184826328
Short name T103
Test name
Test status
Simulation time 2798836709 ps
CPU time 12.31 seconds
Started May 07 12:38:36 PM PDT 24
Finished May 07 12:38:50 PM PDT 24
Peak memory 210576 kb
Host smart-40b96505-26c6-4370-9ebb-84298b6bfd90
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=184826328 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_csr_rw.184826328
Directory /workspace/13.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_passthru_mem_tl_intg_err.1002767738
Short name T454
Test name
Test status
Simulation time 2355026595 ps
CPU time 27.74 seconds
Started May 07 12:38:21 PM PDT 24
Finished May 07 12:38:49 PM PDT 24
Peak memory 210568 kb
Host smart-42c8ded7-8ffe-41c0-80d8-a0b3baa3a9ba
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1002767738 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_p
assthru_mem_tl_intg_err.1002767738
Directory /workspace/13.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_same_csr_outstanding.2282945301
Short name T385
Test name
Test status
Simulation time 320905568 ps
CPU time 4.26 seconds
Started May 07 12:38:35 PM PDT 24
Finished May 07 12:38:41 PM PDT 24
Peak memory 210532 kb
Host smart-ef9ae1c5-01c7-4847-8a38-bf20194c9f9f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2282945301 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_
ctrl_same_csr_outstanding.2282945301
Directory /workspace/13.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_errors.2711917227
Short name T374
Test name
Test status
Simulation time 5809883273 ps
CPU time 17.92 seconds
Started May 07 12:38:25 PM PDT 24
Finished May 07 12:38:45 PM PDT 24
Peak memory 218848 kb
Host smart-b88c080f-781c-4cb8-890f-8ca0a89bb835
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2711917227 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_tl_errors.2711917227
Directory /workspace/13.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_intg_err.4156622398
Short name T433
Test name
Test status
Simulation time 2042192488 ps
CPU time 70.4 seconds
Started May 07 12:38:36 PM PDT 24
Finished May 07 12:39:48 PM PDT 24
Peak memory 210480 kb
Host smart-13caf465-8c35-4fc3-ae34-801fae2daf74
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4156622398 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_tl_i
ntg_err.4156622398
Directory /workspace/13.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_mem_rw_with_rand_reset.4266014276
Short name T373
Test name
Test status
Simulation time 410294796 ps
CPU time 4.97 seconds
Started May 07 12:38:30 PM PDT 24
Finished May 07 12:38:36 PM PDT 24
Peak memory 218672 kb
Host smart-e0d9d272-ab8d-4acb-8692-1790fdf76d0b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4266014276 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 14.rom_ctrl_csr_mem_rw_with_rand_reset.4266014276
Directory /workspace/14.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_rw.2177210026
Short name T426
Test name
Test status
Simulation time 622236909 ps
CPU time 5.33 seconds
Started May 07 12:38:54 PM PDT 24
Finished May 07 12:39:02 PM PDT 24
Peak memory 210480 kb
Host smart-999e9ce6-e642-4169-b773-e01639e3079f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2177210026 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_csr_rw.2177210026
Directory /workspace/14.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_same_csr_outstanding.183258106
Short name T436
Test name
Test status
Simulation time 175438172 ps
CPU time 4.2 seconds
Started May 07 12:38:47 PM PDT 24
Finished May 07 12:38:53 PM PDT 24
Peak memory 210532 kb
Host smart-b048a231-6aaf-4348-bda7-bf7d9d878b87
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=183258106 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_c
trl_same_csr_outstanding.183258106
Directory /workspace/14.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_errors.3316764802
Short name T414
Test name
Test status
Simulation time 2704919546 ps
CPU time 14.77 seconds
Started May 07 12:38:28 PM PDT 24
Finished May 07 12:38:44 PM PDT 24
Peak memory 218844 kb
Host smart-845fc912-0ca4-4eed-b471-1ad7862f895e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3316764802 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_tl_errors.3316764802
Directory /workspace/14.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_intg_err.2035756117
Short name T51
Test name
Test status
Simulation time 6045389512 ps
CPU time 47.28 seconds
Started May 07 12:38:15 PM PDT 24
Finished May 07 12:39:05 PM PDT 24
Peak memory 211420 kb
Host smart-7cff3574-6ffa-4666-9644-eb0e20036ad4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2035756117 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_tl_i
ntg_err.2035756117
Directory /workspace/14.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_mem_rw_with_rand_reset.15735431
Short name T404
Test name
Test status
Simulation time 1566267425 ps
CPU time 13.69 seconds
Started May 07 12:38:47 PM PDT 24
Finished May 07 12:39:03 PM PDT 24
Peak memory 218804 kb
Host smart-d8a69474-97d6-43ff-a0b9-52722c8f46c8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15735431 -assert nopostproc +UVM_TESTNAME=r
om_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 15.rom_ctrl_csr_mem_rw_with_rand_reset.15735431
Directory /workspace/15.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_rw.1471802310
Short name T379
Test name
Test status
Simulation time 333394132 ps
CPU time 4.23 seconds
Started May 07 12:38:35 PM PDT 24
Finished May 07 12:38:40 PM PDT 24
Peak memory 210492 kb
Host smart-6c286bca-3120-4614-bab5-edc390d6325b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1471802310 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_csr_rw.1471802310
Directory /workspace/15.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_passthru_mem_tl_intg_err.2278087919
Short name T380
Test name
Test status
Simulation time 572122423 ps
CPU time 27.79 seconds
Started May 07 12:38:33 PM PDT 24
Finished May 07 12:39:02 PM PDT 24
Peak memory 210540 kb
Host smart-1ca90cf0-3373-40d8-9e2e-920ac2e10b8a
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2278087919 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_p
assthru_mem_tl_intg_err.2278087919
Directory /workspace/15.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_same_csr_outstanding.4031056965
Short name T437
Test name
Test status
Simulation time 3657814308 ps
CPU time 11.19 seconds
Started May 07 12:38:42 PM PDT 24
Finished May 07 12:38:55 PM PDT 24
Peak memory 210596 kb
Host smart-178038d3-e36b-4b10-b766-9eaef68453ee
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4031056965 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_
ctrl_same_csr_outstanding.4031056965
Directory /workspace/15.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_errors.261370275
Short name T395
Test name
Test status
Simulation time 1457659507 ps
CPU time 15.27 seconds
Started May 07 12:38:50 PM PDT 24
Finished May 07 12:39:07 PM PDT 24
Peak memory 218796 kb
Host smart-1e95e762-5c90-4b58-89f5-f14a8ab91501
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=261370275 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_tl_errors.261370275
Directory /workspace/15.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_intg_err.2299827727
Short name T121
Test name
Test status
Simulation time 474408407 ps
CPU time 69.13 seconds
Started May 07 12:38:55 PM PDT 24
Finished May 07 12:40:07 PM PDT 24
Peak memory 211700 kb
Host smart-bdc9ca5c-bbd2-4d5a-83ca-3fe595ff4be4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2299827727 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_tl_i
ntg_err.2299827727
Directory /workspace/15.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_mem_rw_with_rand_reset.2267705771
Short name T54
Test name
Test status
Simulation time 2071906101 ps
CPU time 17.21 seconds
Started May 07 12:38:52 PM PDT 24
Finished May 07 12:39:12 PM PDT 24
Peak memory 218728 kb
Host smart-4488a343-35ec-4a80-bf52-ecb40858c53a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2267705771 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 16.rom_ctrl_csr_mem_rw_with_rand_reset.2267705771
Directory /workspace/16.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_rw.3143909596
Short name T409
Test name
Test status
Simulation time 1436123114 ps
CPU time 12.44 seconds
Started May 07 12:38:35 PM PDT 24
Finished May 07 12:38:50 PM PDT 24
Peak memory 210512 kb
Host smart-cc942aa6-077a-40fb-b2ef-e47bbe93ec70
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3143909596 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_csr_rw.3143909596
Directory /workspace/16.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_passthru_mem_tl_intg_err.2721788416
Short name T434
Test name
Test status
Simulation time 69908894451 ps
CPU time 101.06 seconds
Started May 07 12:38:48 PM PDT 24
Finished May 07 12:40:32 PM PDT 24
Peak memory 210608 kb
Host smart-76fc9193-d1fe-4d26-9a0b-a50e949b6992
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2721788416 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_p
assthru_mem_tl_intg_err.2721788416
Directory /workspace/16.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_same_csr_outstanding.145869090
Short name T450
Test name
Test status
Simulation time 373595045 ps
CPU time 6.63 seconds
Started May 07 12:38:48 PM PDT 24
Finished May 07 12:38:57 PM PDT 24
Peak memory 210452 kb
Host smart-b076b9d6-bca7-483e-a75b-049a2240b6a9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=145869090 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_c
trl_same_csr_outstanding.145869090
Directory /workspace/16.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_errors.1381703544
Short name T427
Test name
Test status
Simulation time 1372360956 ps
CPU time 9.45 seconds
Started May 07 12:38:53 PM PDT 24
Finished May 07 12:39:05 PM PDT 24
Peak memory 218788 kb
Host smart-a6dedf47-670c-42fe-875d-78f5d9e56d4e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1381703544 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_tl_errors.1381703544
Directory /workspace/16.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_mem_rw_with_rand_reset.1206068595
Short name T420
Test name
Test status
Simulation time 13483928126 ps
CPU time 9.42 seconds
Started May 07 12:38:37 PM PDT 24
Finished May 07 12:38:47 PM PDT 24
Peak memory 214800 kb
Host smart-7128dd83-1b2f-4b3e-b3df-e80f13acf697
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1206068595 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 17.rom_ctrl_csr_mem_rw_with_rand_reset.1206068595
Directory /workspace/17.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_rw.581867981
Short name T460
Test name
Test status
Simulation time 1973681609 ps
CPU time 15.1 seconds
Started May 07 12:38:48 PM PDT 24
Finished May 07 12:39:05 PM PDT 24
Peak memory 210544 kb
Host smart-dec51262-27ce-4ef0-8012-7824fd7f5384
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=581867981 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_csr_rw.581867981
Directory /workspace/17.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_passthru_mem_tl_intg_err.529700742
Short name T444
Test name
Test status
Simulation time 2694557760 ps
CPU time 35.97 seconds
Started May 07 12:38:46 PM PDT 24
Finished May 07 12:39:24 PM PDT 24
Peak memory 210632 kb
Host smart-f042be61-d492-4458-96c1-c89fbb7d2823
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=529700742 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_pa
ssthru_mem_tl_intg_err.529700742
Directory /workspace/17.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_same_csr_outstanding.4185341523
Short name T441
Test name
Test status
Simulation time 2430233545 ps
CPU time 9.51 seconds
Started May 07 12:38:36 PM PDT 24
Finished May 07 12:38:47 PM PDT 24
Peak memory 210608 kb
Host smart-f597699f-4d6e-4573-8356-8dd8ee648287
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4185341523 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_
ctrl_same_csr_outstanding.4185341523
Directory /workspace/17.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_errors.829060387
Short name T372
Test name
Test status
Simulation time 2275025228 ps
CPU time 10.3 seconds
Started May 07 12:38:40 PM PDT 24
Finished May 07 12:38:51 PM PDT 24
Peak memory 218908 kb
Host smart-8b7ed463-7bb9-4f0e-92e1-f61daefd626f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=829060387 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_tl_errors.829060387
Directory /workspace/17.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_intg_err.1095770068
Short name T120
Test name
Test status
Simulation time 622457938 ps
CPU time 71.03 seconds
Started May 07 12:38:36 PM PDT 24
Finished May 07 12:39:48 PM PDT 24
Peak memory 210568 kb
Host smart-e2977181-4902-497a-b629-d83fed6ab64d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1095770068 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_tl_i
ntg_err.1095770068
Directory /workspace/17.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_mem_rw_with_rand_reset.2191181833
Short name T393
Test name
Test status
Simulation time 2133006243 ps
CPU time 16.27 seconds
Started May 07 12:38:59 PM PDT 24
Finished May 07 12:39:19 PM PDT 24
Peak memory 218776 kb
Host smart-79216f68-e448-4b4d-86d2-bcf4bb61de00
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2191181833 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 18.rom_ctrl_csr_mem_rw_with_rand_reset.2191181833
Directory /workspace/18.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_rw.1427049621
Short name T416
Test name
Test status
Simulation time 5296805870 ps
CPU time 6.9 seconds
Started May 07 12:38:39 PM PDT 24
Finished May 07 12:38:47 PM PDT 24
Peak memory 210704 kb
Host smart-7a90ec3c-894f-469c-a53d-ac64c5998235
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1427049621 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_csr_rw.1427049621
Directory /workspace/18.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_passthru_mem_tl_intg_err.2754172195
Short name T66
Test name
Test status
Simulation time 3678939284 ps
CPU time 48.62 seconds
Started May 07 12:38:47 PM PDT 24
Finished May 07 12:39:38 PM PDT 24
Peak memory 210632 kb
Host smart-b5d89b57-da9b-4491-83c2-0b660423c265
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2754172195 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_p
assthru_mem_tl_intg_err.2754172195
Directory /workspace/18.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_same_csr_outstanding.146033122
Short name T397
Test name
Test status
Simulation time 2842791125 ps
CPU time 12.43 seconds
Started May 07 12:38:41 PM PDT 24
Finished May 07 12:38:55 PM PDT 24
Peak memory 210624 kb
Host smart-d55ab7ad-5d37-4052-b797-602e4bc432de
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=146033122 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_c
trl_same_csr_outstanding.146033122
Directory /workspace/18.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_errors.714382718
Short name T400
Test name
Test status
Simulation time 2119979999 ps
CPU time 9.94 seconds
Started May 07 12:38:52 PM PDT 24
Finished May 07 12:39:04 PM PDT 24
Peak memory 218792 kb
Host smart-e18fe49d-3ac3-4c23-b19f-aa30a0366abb
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=714382718 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_tl_errors.714382718
Directory /workspace/18.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_intg_err.1243656817
Short name T116
Test name
Test status
Simulation time 4950267612 ps
CPU time 42.55 seconds
Started May 07 12:38:45 PM PDT 24
Finished May 07 12:39:29 PM PDT 24
Peak memory 211744 kb
Host smart-63a66223-5ea0-4e9b-8dac-4e004ca3b5e6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1243656817 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_tl_i
ntg_err.1243656817
Directory /workspace/18.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_mem_rw_with_rand_reset.852688805
Short name T369
Test name
Test status
Simulation time 2710573707 ps
CPU time 12.85 seconds
Started May 07 12:38:41 PM PDT 24
Finished May 07 12:38:55 PM PDT 24
Peak memory 218848 kb
Host smart-a6ec78ab-af73-4529-8062-4a5306e556ac
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=852688805 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 19.rom_ctrl_csr_mem_rw_with_rand_reset.852688805
Directory /workspace/19.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_rw.2885647974
Short name T53
Test name
Test status
Simulation time 1962641060 ps
CPU time 10.12 seconds
Started May 07 12:38:41 PM PDT 24
Finished May 07 12:38:52 PM PDT 24
Peak memory 210564 kb
Host smart-66a802a7-eee4-4c2f-9f00-ae6f678b6211
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2885647974 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_csr_rw.2885647974
Directory /workspace/19.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_passthru_mem_tl_intg_err.1132334153
Short name T84
Test name
Test status
Simulation time 2337987915 ps
CPU time 27.45 seconds
Started May 07 12:38:30 PM PDT 24
Finished May 07 12:38:58 PM PDT 24
Peak memory 210532 kb
Host smart-4700a3ff-2969-4e05-bf35-353fea0d0852
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1132334153 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_p
assthru_mem_tl_intg_err.1132334153
Directory /workspace/19.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_same_csr_outstanding.272591170
Short name T390
Test name
Test status
Simulation time 6720056837 ps
CPU time 14.52 seconds
Started May 07 12:38:48 PM PDT 24
Finished May 07 12:39:05 PM PDT 24
Peak memory 210556 kb
Host smart-10b7b409-7363-46e1-938b-6f8d761dcc23
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=272591170 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_c
trl_same_csr_outstanding.272591170
Directory /workspace/19.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_errors.203933751
Short name T365
Test name
Test status
Simulation time 4588119562 ps
CPU time 12.92 seconds
Started May 07 12:38:47 PM PDT 24
Finished May 07 12:39:02 PM PDT 24
Peak memory 218816 kb
Host smart-40ef4312-3d1a-4908-9c0a-0d99427645bc
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=203933751 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_tl_errors.203933751
Directory /workspace/19.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_intg_err.545947176
Short name T117
Test name
Test status
Simulation time 3378786217 ps
CPU time 44.71 seconds
Started May 07 12:38:42 PM PDT 24
Finished May 07 12:39:28 PM PDT 24
Peak memory 211300 kb
Host smart-dbbaab93-4a1d-44a7-aff2-df261a1bf7e2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=545947176 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_tl_in
tg_err.545947176
Directory /workspace/19.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_aliasing.373875428
Short name T451
Test name
Test status
Simulation time 1626583089 ps
CPU time 13.4 seconds
Started May 07 12:38:23 PM PDT 24
Finished May 07 12:38:38 PM PDT 24
Peak memory 210552 kb
Host smart-9b0975a0-3cb9-4604-8c90-3a30cbf5a579
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=373875428 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_alias
ing.373875428
Directory /workspace/2.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_bit_bash.3784028159
Short name T410
Test name
Test status
Simulation time 89085886 ps
CPU time 4.54 seconds
Started May 07 12:38:26 PM PDT 24
Finished May 07 12:38:31 PM PDT 24
Peak memory 210448 kb
Host smart-93519c74-f22a-46f9-8d29-b389cc26099a
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3784028159 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_bit_
bash.3784028159
Directory /workspace/2.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_hw_reset.603471668
Short name T62
Test name
Test status
Simulation time 1589382002 ps
CPU time 9.44 seconds
Started May 07 12:38:32 PM PDT 24
Finished May 07 12:38:43 PM PDT 24
Peak memory 210560 kb
Host smart-80fb79f7-a240-4ee1-b57d-0ba278bf1d6a
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=603471668 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_hw_re
set.603471668
Directory /workspace/2.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_mem_rw_with_rand_reset.186800130
Short name T386
Test name
Test status
Simulation time 210925608 ps
CPU time 5.31 seconds
Started May 07 12:38:25 PM PDT 24
Finished May 07 12:38:31 PM PDT 24
Peak memory 218716 kb
Host smart-b61e3cf7-73c7-4494-8ef9-295a864ceff8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=186800130 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 2.rom_ctrl_csr_mem_rw_with_rand_reset.186800130
Directory /workspace/2.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_rw.1140270421
Short name T375
Test name
Test status
Simulation time 232069148 ps
CPU time 4.3 seconds
Started May 07 12:38:36 PM PDT 24
Finished May 07 12:38:42 PM PDT 24
Peak memory 210508 kb
Host smart-7e745929-c428-4e71-b76e-ad7098ef3537
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1140270421 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_rw.1140270421
Directory /workspace/2.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_partial_access.3748417824
Short name T428
Test name
Test status
Simulation time 7718363737 ps
CPU time 16.03 seconds
Started May 07 12:38:23 PM PDT 24
Finished May 07 12:38:40 PM PDT 24
Peak memory 210500 kb
Host smart-44401e09-2c64-484c-bc62-350b2ac0b9b1
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3748417824 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctr
l_mem_partial_access.3748417824
Directory /workspace/2.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_walk.823740343
Short name T424
Test name
Test status
Simulation time 13074630451 ps
CPU time 11.56 seconds
Started May 07 12:38:17 PM PDT 24
Finished May 07 12:38:31 PM PDT 24
Peak memory 210520 kb
Host smart-747c788d-a426-41ab-a3b1-96b1ef5536f4
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=823740343 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_mem_walk.
823740343
Directory /workspace/2.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_passthru_mem_tl_intg_err.2985282581
Short name T456
Test name
Test status
Simulation time 5659458367 ps
CPU time 33.13 seconds
Started May 07 12:38:26 PM PDT 24
Finished May 07 12:39:00 PM PDT 24
Peak memory 210660 kb
Host smart-1601ec2a-7183-4fdf-a024-e30a9a2332c7
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2985282581 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_pa
ssthru_mem_tl_intg_err.2985282581
Directory /workspace/2.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_same_csr_outstanding.342062299
Short name T396
Test name
Test status
Simulation time 338053335 ps
CPU time 5.49 seconds
Started May 07 12:38:27 PM PDT 24
Finished May 07 12:38:34 PM PDT 24
Peak memory 210448 kb
Host smart-30b02520-5c2c-4247-8912-2cf4db12bfcd
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=342062299 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ct
rl_same_csr_outstanding.342062299
Directory /workspace/2.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_errors.673830056
Short name T407
Test name
Test status
Simulation time 2128032774 ps
CPU time 9.56 seconds
Started May 07 12:38:14 PM PDT 24
Finished May 07 12:38:27 PM PDT 24
Peak memory 218848 kb
Host smart-371e9bb3-1f72-45cd-8e8c-3a5755d8fac9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=673830056 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_tl_errors.673830056
Directory /workspace/2.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_intg_err.3214024088
Short name T119
Test name
Test status
Simulation time 1292955958 ps
CPU time 42.71 seconds
Started May 07 12:38:20 PM PDT 24
Finished May 07 12:39:03 PM PDT 24
Peak memory 211312 kb
Host smart-62b7ff2c-360e-4161-9640-a2102f54af7c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3214024088 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_tl_in
tg_err.3214024088
Directory /workspace/2.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_aliasing.1169019295
Short name T398
Test name
Test status
Simulation time 168130052 ps
CPU time 4.19 seconds
Started May 07 12:38:33 PM PDT 24
Finished May 07 12:38:39 PM PDT 24
Peak memory 210416 kb
Host smart-f61e8a55-7087-4c54-a537-27fb0b9d47bb
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1169019295 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_alia
sing.1169019295
Directory /workspace/3.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_bit_bash.1051553299
Short name T439
Test name
Test status
Simulation time 1370766814 ps
CPU time 12.33 seconds
Started May 07 12:38:27 PM PDT 24
Finished May 07 12:38:41 PM PDT 24
Peak memory 210516 kb
Host smart-fd3dd002-852f-4450-b1d3-c10cef359206
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1051553299 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_bit_
bash.1051553299
Directory /workspace/3.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_hw_reset.2519273955
Short name T448
Test name
Test status
Simulation time 2103129195 ps
CPU time 19.05 seconds
Started May 07 12:38:45 PM PDT 24
Finished May 07 12:39:06 PM PDT 24
Peak memory 210560 kb
Host smart-a08fa997-6124-4355-93d4-97df0edb9f53
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2519273955 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_hw_r
eset.2519273955
Directory /workspace/3.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_mem_rw_with_rand_reset.3223461571
Short name T423
Test name
Test status
Simulation time 1566733630 ps
CPU time 9.25 seconds
Started May 07 12:38:24 PM PDT 24
Finished May 07 12:38:35 PM PDT 24
Peak memory 212776 kb
Host smart-f10d24aa-4971-4670-8db0-6a0eebc51b35
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3223461571 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 3.rom_ctrl_csr_mem_rw_with_rand_reset.3223461571
Directory /workspace/3.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_rw.4007749241
Short name T443
Test name
Test status
Simulation time 6339818353 ps
CPU time 14.05 seconds
Started May 07 12:38:18 PM PDT 24
Finished May 07 12:38:34 PM PDT 24
Peak memory 210612 kb
Host smart-960df023-a356-41c2-8722-412bc253a624
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4007749241 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_rw.4007749241
Directory /workspace/3.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_partial_access.3976697490
Short name T406
Test name
Test status
Simulation time 802772500 ps
CPU time 6.75 seconds
Started May 07 12:38:12 PM PDT 24
Finished May 07 12:38:23 PM PDT 24
Peak memory 210428 kb
Host smart-143ca837-9afd-4962-bca8-0d3eb03ef1a6
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3976697490 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctr
l_mem_partial_access.3976697490
Directory /workspace/3.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_walk.2709424206
Short name T367
Test name
Test status
Simulation time 553304286 ps
CPU time 4.12 seconds
Started May 07 12:38:27 PM PDT 24
Finished May 07 12:38:33 PM PDT 24
Peak memory 210500 kb
Host smart-706f4d00-8d35-4fe4-8816-c9f8e15b05f3
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2709424206 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_mem_walk
.2709424206
Directory /workspace/3.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_passthru_mem_tl_intg_err.1230678125
Short name T81
Test name
Test status
Simulation time 28840937752 ps
CPU time 59.66 seconds
Started May 07 12:38:26 PM PDT 24
Finished May 07 12:39:27 PM PDT 24
Peak memory 210664 kb
Host smart-09e2f82c-1c18-48c2-b1fd-5cc95bf2b9ac
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1230678125 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_pa
ssthru_mem_tl_intg_err.1230678125
Directory /workspace/3.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_same_csr_outstanding.4240772965
Short name T419
Test name
Test status
Simulation time 86391951 ps
CPU time 4.2 seconds
Started May 07 12:38:20 PM PDT 24
Finished May 07 12:38:25 PM PDT 24
Peak memory 210424 kb
Host smart-35b78b77-bb97-4fee-b5bb-295884838e97
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4240772965 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_c
trl_same_csr_outstanding.4240772965
Directory /workspace/3.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_errors.3276877535
Short name T432
Test name
Test status
Simulation time 1193057804 ps
CPU time 13.14 seconds
Started May 07 12:38:15 PM PDT 24
Finished May 07 12:38:31 PM PDT 24
Peak memory 218780 kb
Host smart-5b7a19b3-8f4c-4d05-8015-be26545ca050
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3276877535 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_tl_errors.3276877535
Directory /workspace/3.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_intg_err.264725304
Short name T115
Test name
Test status
Simulation time 702529471 ps
CPU time 36.58 seconds
Started May 07 12:38:38 PM PDT 24
Finished May 07 12:39:16 PM PDT 24
Peak memory 210564 kb
Host smart-7e3f3492-2dc2-4d33-a562-62d6119cf6d4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=264725304 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_tl_int
g_err.264725304
Directory /workspace/3.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_aliasing.3451866405
Short name T102
Test name
Test status
Simulation time 867451486 ps
CPU time 9.28 seconds
Started May 07 12:38:15 PM PDT 24
Finished May 07 12:38:27 PM PDT 24
Peak memory 210572 kb
Host smart-e7ba8555-f8e0-4a8c-9666-b2609619c238
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3451866405 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_alia
sing.3451866405
Directory /workspace/4.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_bit_bash.892094619
Short name T383
Test name
Test status
Simulation time 5985767943 ps
CPU time 12.42 seconds
Started May 07 12:38:12 PM PDT 24
Finished May 07 12:38:29 PM PDT 24
Peak memory 210504 kb
Host smart-fcbe0615-52bf-43db-8aae-746db528883d
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=892094619 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_bit_b
ash.892094619
Directory /workspace/4.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_hw_reset.2839575411
Short name T455
Test name
Test status
Simulation time 91384219 ps
CPU time 5.92 seconds
Started May 07 12:38:31 PM PDT 24
Finished May 07 12:38:39 PM PDT 24
Peak memory 210576 kb
Host smart-9a13d22e-39ab-4530-9032-f12d76914ce7
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2839575411 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_hw_r
eset.2839575411
Directory /workspace/4.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_mem_rw_with_rand_reset.3530171263
Short name T376
Test name
Test status
Simulation time 554400637 ps
CPU time 8.19 seconds
Started May 07 12:38:27 PM PDT 24
Finished May 07 12:38:37 PM PDT 24
Peak memory 218764 kb
Host smart-fc696228-790f-4b23-8814-b43f04368c29
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3530171263 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 4.rom_ctrl_csr_mem_rw_with_rand_reset.3530171263
Directory /workspace/4.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_rw.2110302633
Short name T405
Test name
Test status
Simulation time 6432519139 ps
CPU time 9.32 seconds
Started May 07 12:38:22 PM PDT 24
Finished May 07 12:38:32 PM PDT 24
Peak memory 210604 kb
Host smart-4bd473e7-1822-4883-b8bf-1045b9d7324e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2110302633 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_rw.2110302633
Directory /workspace/4.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_partial_access.3941230863
Short name T364
Test name
Test status
Simulation time 90850261 ps
CPU time 4.33 seconds
Started May 07 12:38:31 PM PDT 24
Finished May 07 12:38:36 PM PDT 24
Peak memory 210292 kb
Host smart-ef584977-6bbd-42f9-905e-6fff3da6b008
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3941230863 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctr
l_mem_partial_access.3941230863
Directory /workspace/4.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_walk.1266595416
Short name T368
Test name
Test status
Simulation time 5861246112 ps
CPU time 12.13 seconds
Started May 07 12:38:11 PM PDT 24
Finished May 07 12:38:27 PM PDT 24
Peak memory 210548 kb
Host smart-b9853019-4f38-444a-9381-81f771ec6361
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1266595416 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_mem_walk
.1266595416
Directory /workspace/4.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_passthru_mem_tl_intg_err.2568465271
Short name T453
Test name
Test status
Simulation time 5716013248 ps
CPU time 49.2 seconds
Started May 07 12:38:26 PM PDT 24
Finished May 07 12:39:16 PM PDT 24
Peak memory 210632 kb
Host smart-47a2830f-152d-477b-ba87-d625966ebe1a
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2568465271 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_pa
ssthru_mem_tl_intg_err.2568465271
Directory /workspace/4.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_same_csr_outstanding.3598411332
Short name T99
Test name
Test status
Simulation time 7488080738 ps
CPU time 9.54 seconds
Started May 07 12:38:34 PM PDT 24
Finished May 07 12:38:46 PM PDT 24
Peak memory 210608 kb
Host smart-7bde19a6-662e-42b6-8ad0-097180ebba8b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3598411332 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_c
trl_same_csr_outstanding.3598411332
Directory /workspace/4.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_errors.2887282389
Short name T449
Test name
Test status
Simulation time 468980468 ps
CPU time 9.7 seconds
Started May 07 12:38:32 PM PDT 24
Finished May 07 12:38:43 PM PDT 24
Peak memory 218776 kb
Host smart-8462db53-0b2c-4370-8e0e-71d3437d0040
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2887282389 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_tl_errors.2887282389
Directory /workspace/4.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_intg_err.4273205304
Short name T125
Test name
Test status
Simulation time 13356521121 ps
CPU time 43.69 seconds
Started May 07 12:38:19 PM PDT 24
Finished May 07 12:39:04 PM PDT 24
Peak memory 211552 kb
Host smart-35445115-6bab-4d4e-9871-564b1afe418a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4273205304 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_tl_in
tg_err.4273205304
Directory /workspace/4.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_mem_rw_with_rand_reset.3367633569
Short name T52
Test name
Test status
Simulation time 24261050800 ps
CPU time 14.38 seconds
Started May 07 12:38:21 PM PDT 24
Finished May 07 12:38:36 PM PDT 24
Peak memory 218836 kb
Host smart-0926b920-c6c8-4b3b-80c2-adf6146d0a24
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3367633569 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 5.rom_ctrl_csr_mem_rw_with_rand_reset.3367633569
Directory /workspace/5.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_rw.1383492607
Short name T413
Test name
Test status
Simulation time 2416814215 ps
CPU time 11.16 seconds
Started May 07 12:38:19 PM PDT 24
Finished May 07 12:38:32 PM PDT 24
Peak memory 210548 kb
Host smart-cb1cfc8f-0ad5-415c-855f-da7209f47a9c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1383492607 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_csr_rw.1383492607
Directory /workspace/5.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_passthru_mem_tl_intg_err.514264283
Short name T85
Test name
Test status
Simulation time 31799609064 ps
CPU time 67.68 seconds
Started May 07 12:38:21 PM PDT 24
Finished May 07 12:39:30 PM PDT 24
Peak memory 210672 kb
Host smart-206d9c82-7da4-4016-9782-a9cf5706a101
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=514264283 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_pas
sthru_mem_tl_intg_err.514264283
Directory /workspace/5.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_same_csr_outstanding.4144840235
Short name T391
Test name
Test status
Simulation time 1394256487 ps
CPU time 11.68 seconds
Started May 07 12:38:39 PM PDT 24
Finished May 07 12:38:51 PM PDT 24
Peak memory 210524 kb
Host smart-423bb1dc-3f59-4b9a-9548-987545fe7720
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4144840235 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_c
trl_same_csr_outstanding.4144840235
Directory /workspace/5.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_errors.3017721981
Short name T363
Test name
Test status
Simulation time 87215165 ps
CPU time 6.57 seconds
Started May 07 12:38:13 PM PDT 24
Finished May 07 12:38:23 PM PDT 24
Peak memory 218828 kb
Host smart-995daa3a-91e0-41e0-8e35-9d5180af6064
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3017721981 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_tl_errors.3017721981
Directory /workspace/5.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_intg_err.4172657033
Short name T118
Test name
Test status
Simulation time 530435813 ps
CPU time 70.43 seconds
Started May 07 12:38:27 PM PDT 24
Finished May 07 12:39:39 PM PDT 24
Peak memory 218632 kb
Host smart-dc8bf858-7e3d-4707-a42c-95d006fd515a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4172657033 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_tl_in
tg_err.4172657033
Directory /workspace/5.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_mem_rw_with_rand_reset.985610090
Short name T425
Test name
Test status
Simulation time 611345692 ps
CPU time 4.75 seconds
Started May 07 12:38:31 PM PDT 24
Finished May 07 12:38:37 PM PDT 24
Peak memory 213516 kb
Host smart-aacdaf56-f6d1-4e77-bcd6-24cf6a8e6668
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=985610090 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 6.rom_ctrl_csr_mem_rw_with_rand_reset.985610090
Directory /workspace/6.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_rw.252456380
Short name T392
Test name
Test status
Simulation time 88141028 ps
CPU time 4.08 seconds
Started May 07 12:38:30 PM PDT 24
Finished May 07 12:38:36 PM PDT 24
Peak memory 210484 kb
Host smart-39130a6b-fde5-43c7-ad8d-be35a0c4482c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=252456380 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_csr_rw.252456380
Directory /workspace/6.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_passthru_mem_tl_intg_err.2392856824
Short name T422
Test name
Test status
Simulation time 6725916096 ps
CPU time 30.16 seconds
Started May 07 12:38:23 PM PDT 24
Finished May 07 12:38:54 PM PDT 24
Peak memory 210668 kb
Host smart-8d8b5c29-8795-4974-b0f4-71d46f6ad922
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2392856824 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_pa
ssthru_mem_tl_intg_err.2392856824
Directory /workspace/6.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_same_csr_outstanding.1844334999
Short name T394
Test name
Test status
Simulation time 8353905843 ps
CPU time 16.91 seconds
Started May 07 12:38:38 PM PDT 24
Finished May 07 12:38:56 PM PDT 24
Peak memory 210616 kb
Host smart-66d75c6e-3087-4335-bb21-26fe51b3b7dd
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1844334999 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_c
trl_same_csr_outstanding.1844334999
Directory /workspace/6.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_errors.2728857996
Short name T408
Test name
Test status
Simulation time 1037824383 ps
CPU time 13.88 seconds
Started May 07 12:38:21 PM PDT 24
Finished May 07 12:38:37 PM PDT 24
Peak memory 218812 kb
Host smart-294f42b3-e70d-4b3b-acda-6ae9d6f3d25c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2728857996 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_tl_errors.2728857996
Directory /workspace/6.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_intg_err.936604456
Short name T445
Test name
Test status
Simulation time 5433254155 ps
CPU time 43.06 seconds
Started May 07 12:38:40 PM PDT 24
Finished May 07 12:39:24 PM PDT 24
Peak memory 211676 kb
Host smart-721d63c8-6179-41d1-8600-09d2fb0c0b19
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=936604456 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_tl_int
g_err.936604456
Directory /workspace/6.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_mem_rw_with_rand_reset.3107660398
Short name T389
Test name
Test status
Simulation time 8173398631 ps
CPU time 16.29 seconds
Started May 07 12:38:15 PM PDT 24
Finished May 07 12:38:34 PM PDT 24
Peak memory 218796 kb
Host smart-c711a8fe-df47-4bcc-9160-f75379075ca2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3107660398 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 7.rom_ctrl_csr_mem_rw_with_rand_reset.3107660398
Directory /workspace/7.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_rw.57635441
Short name T442
Test name
Test status
Simulation time 5736188646 ps
CPU time 13.57 seconds
Started May 07 12:38:43 PM PDT 24
Finished May 07 12:38:58 PM PDT 24
Peak memory 210512 kb
Host smart-7a68fad3-15f1-49ea-b3cf-95e7926fff60
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57635441 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_csr_rw.57635441
Directory /workspace/7.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_same_csr_outstanding.931549686
Short name T399
Test name
Test status
Simulation time 7453069159 ps
CPU time 11.76 seconds
Started May 07 12:38:13 PM PDT 24
Finished May 07 12:38:29 PM PDT 24
Peak memory 210648 kb
Host smart-21754e90-af97-47be-850e-938efc236177
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=931549686 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ct
rl_same_csr_outstanding.931549686
Directory /workspace/7.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_errors.2888437143
Short name T421
Test name
Test status
Simulation time 6759593845 ps
CPU time 16.42 seconds
Started May 07 12:38:32 PM PDT 24
Finished May 07 12:38:49 PM PDT 24
Peak memory 218856 kb
Host smart-c06a88a6-de83-4efa-94b5-e274e8c78667
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2888437143 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_tl_errors.2888437143
Directory /workspace/7.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_mem_rw_with_rand_reset.3730033879
Short name T435
Test name
Test status
Simulation time 975127950 ps
CPU time 8.45 seconds
Started May 07 12:38:14 PM PDT 24
Finished May 07 12:38:26 PM PDT 24
Peak memory 218744 kb
Host smart-aad1fed3-4915-489b-9292-047d43a531cc
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3730033879 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 8.rom_ctrl_csr_mem_rw_with_rand_reset.3730033879
Directory /workspace/8.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_rw.3812519477
Short name T63
Test name
Test status
Simulation time 7141438696 ps
CPU time 13.57 seconds
Started May 07 12:38:33 PM PDT 24
Finished May 07 12:38:47 PM PDT 24
Peak memory 210576 kb
Host smart-b1325e76-b259-4c81-a65a-0968154d8637
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3812519477 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_csr_rw.3812519477
Directory /workspace/8.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_passthru_mem_tl_intg_err.3249099182
Short name T83
Test name
Test status
Simulation time 11786610308 ps
CPU time 52.84 seconds
Started May 07 12:38:14 PM PDT 24
Finished May 07 12:39:10 PM PDT 24
Peak memory 210660 kb
Host smart-b6dd3a8e-daeb-4217-8ea7-87164661a639
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3249099182 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_pa
ssthru_mem_tl_intg_err.3249099182
Directory /workspace/8.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_same_csr_outstanding.3619716403
Short name T388
Test name
Test status
Simulation time 15428565229 ps
CPU time 11.82 seconds
Started May 07 12:38:21 PM PDT 24
Finished May 07 12:38:35 PM PDT 24
Peak memory 210608 kb
Host smart-cf459842-2e0d-466b-9810-c23bfbd06116
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3619716403 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_c
trl_same_csr_outstanding.3619716403
Directory /workspace/8.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_errors.4083118663
Short name T370
Test name
Test status
Simulation time 85422017 ps
CPU time 6.41 seconds
Started May 07 12:38:30 PM PDT 24
Finished May 07 12:38:38 PM PDT 24
Peak memory 218792 kb
Host smart-cbd595ae-332a-4b0b-84b0-d0345e4d12f9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4083118663 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_tl_errors.4083118663
Directory /workspace/8.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_intg_err.134761648
Short name T114
Test name
Test status
Simulation time 6159512012 ps
CPU time 78.5 seconds
Started May 07 12:38:41 PM PDT 24
Finished May 07 12:40:00 PM PDT 24
Peak memory 211884 kb
Host smart-646bf0cf-1757-4f0a-9c5a-f525d2ea4405
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=134761648 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_tl_int
g_err.134761648
Directory /workspace/8.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_mem_rw_with_rand_reset.3157186087
Short name T411
Test name
Test status
Simulation time 95475086 ps
CPU time 4.58 seconds
Started May 07 12:38:26 PM PDT 24
Finished May 07 12:38:32 PM PDT 24
Peak memory 213684 kb
Host smart-fad971df-12fa-4fdb-b30f-87ef6df631d1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3157186087 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 9.rom_ctrl_csr_mem_rw_with_rand_reset.3157186087
Directory /workspace/9.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_rw.2016241313
Short name T76
Test name
Test status
Simulation time 177776451 ps
CPU time 5.52 seconds
Started May 07 12:38:33 PM PDT 24
Finished May 07 12:38:39 PM PDT 24
Peak memory 210604 kb
Host smart-7d3b4194-15a7-4e0a-b85c-10c00fb3a8fa
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2016241313 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_csr_rw.2016241313
Directory /workspace/9.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_passthru_mem_tl_intg_err.3243387048
Short name T418
Test name
Test status
Simulation time 7707272342 ps
CPU time 58.81 seconds
Started May 07 12:38:34 PM PDT 24
Finished May 07 12:39:35 PM PDT 24
Peak memory 210680 kb
Host smart-794961fd-7b0d-4c22-9d51-af9d8375a824
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3243387048 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_pa
ssthru_mem_tl_intg_err.3243387048
Directory /workspace/9.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_same_csr_outstanding.1741312345
Short name T65
Test name
Test status
Simulation time 13228370760 ps
CPU time 11.02 seconds
Started May 07 12:38:36 PM PDT 24
Finished May 07 12:38:48 PM PDT 24
Peak memory 210580 kb
Host smart-037c2f8f-07e7-41ba-8da0-a7b59d42348e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1741312345 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_c
trl_same_csr_outstanding.1741312345
Directory /workspace/9.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_errors.2583129589
Short name T440
Test name
Test status
Simulation time 595593655 ps
CPU time 9.55 seconds
Started May 07 12:38:14 PM PDT 24
Finished May 07 12:38:27 PM PDT 24
Peak memory 218804 kb
Host smart-15f304a6-84c2-4069-adb4-e7dbf8e57202
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2583129589 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_tl_errors.2583129589
Directory /workspace/9.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_intg_err.2396367966
Short name T122
Test name
Test status
Simulation time 11992214613 ps
CPU time 46.16 seconds
Started May 07 12:38:43 PM PDT 24
Finished May 07 12:39:31 PM PDT 24
Peak memory 211344 kb
Host smart-1a4649c4-045d-4365-bbaa-be18ac6586db
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2396367966 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_tl_in
tg_err.2396367966
Directory /workspace/9.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/0.rom_ctrl_alert_test.2532375440
Short name T333
Test name
Test status
Simulation time 2412628697 ps
CPU time 12.49 seconds
Started May 07 12:38:39 PM PDT 24
Finished May 07 12:38:52 PM PDT 24
Peak memory 211832 kb
Host smart-4ebd8eaa-e6c1-4d5c-8642-e56e929bf6c2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2532375440 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_alert_test.2532375440
Directory /workspace/0.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/0.rom_ctrl_corrupt_sig_fatal_chk.3922859761
Short name T93
Test name
Test status
Simulation time 162979436666 ps
CPU time 353.01 seconds
Started May 07 12:38:44 PM PDT 24
Finished May 07 12:44:38 PM PDT 24
Peak memory 229076 kb
Host smart-c6fabfbd-526a-4dbd-9cdf-f7d591078774
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3922859761 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_c
orrupt_sig_fatal_chk.3922859761
Directory /workspace/0.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/0.rom_ctrl_kmac_err_chk.534141323
Short name T321
Test name
Test status
Simulation time 692410477 ps
CPU time 9.75 seconds
Started May 07 12:38:49 PM PDT 24
Finished May 07 12:39:01 PM PDT 24
Peak memory 212520 kb
Host smart-186f05fd-b6c1-476e-88e2-1fc704e128a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=534141323 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_kmac_err_chk.534141323
Directory /workspace/0.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/0.rom_ctrl_max_throughput_chk.2676302792
Short name T227
Test name
Test status
Simulation time 586979811 ps
CPU time 5.82 seconds
Started May 07 12:38:39 PM PDT 24
Finished May 07 12:38:46 PM PDT 24
Peak memory 211836 kb
Host smart-2fa828d2-1761-450b-a87b-e3b61bbcb52c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2676302792 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_max_throughput_chk.2676302792
Directory /workspace/0.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/0.rom_ctrl_sec_cm.393782879
Short name T34
Test name
Test status
Simulation time 5107156493 ps
CPU time 60.5 seconds
Started May 07 12:38:37 PM PDT 24
Finished May 07 12:39:39 PM PDT 24
Peak memory 237116 kb
Host smart-30a11b2f-4ee8-44b7-9685-09c3f3e572e2
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=393782879 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_sec_cm.393782879
Directory /workspace/0.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/0.rom_ctrl_smoke.2445287085
Short name T299
Test name
Test status
Simulation time 1102904086 ps
CPU time 17.11 seconds
Started May 07 12:38:44 PM PDT 24
Finished May 07 12:39:03 PM PDT 24
Peak memory 213564 kb
Host smart-19cec588-3971-41ef-b189-cdeb2bf145c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2445287085 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_smoke.2445287085
Directory /workspace/0.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/0.rom_ctrl_stress_all.10811071
Short name T329
Test name
Test status
Simulation time 17098361547 ps
CPU time 39.94 seconds
Started May 07 12:38:45 PM PDT 24
Finished May 07 12:39:26 PM PDT 24
Peak memory 215388 kb
Host smart-4f336149-07fa-4052-801b-4f74ad82cb48
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10811071 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +U
VM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n
ame 0.rom_ctrl_stress_all.10811071
Directory /workspace/0.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/1.rom_ctrl_alert_test.2650600101
Short name T298
Test name
Test status
Simulation time 2104235362 ps
CPU time 16.46 seconds
Started May 07 12:38:43 PM PDT 24
Finished May 07 12:39:06 PM PDT 24
Peak memory 211744 kb
Host smart-d7709a4c-5541-476d-9502-2b25f6fc85eb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2650600101 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_alert_test.2650600101
Directory /workspace/1.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/1.rom_ctrl_corrupt_sig_fatal_chk.1309386524
Short name T254
Test name
Test status
Simulation time 1773475793 ps
CPU time 109.98 seconds
Started May 07 12:38:53 PM PDT 24
Finished May 07 12:40:46 PM PDT 24
Peak memory 221852 kb
Host smart-deda0888-1ea3-48de-aafd-077a94f921bc
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1309386524 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_c
orrupt_sig_fatal_chk.1309386524
Directory /workspace/1.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/1.rom_ctrl_max_throughput_chk.504268708
Short name T161
Test name
Test status
Simulation time 412756086 ps
CPU time 5.74 seconds
Started May 07 12:38:52 PM PDT 24
Finished May 07 12:39:00 PM PDT 24
Peak memory 211668 kb
Host smart-f5dccb64-d086-4a31-9146-2c2a84671c93
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=504268708 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_max_throughput_chk.504268708
Directory /workspace/1.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/1.rom_ctrl_sec_cm.2062162143
Short name T30
Test name
Test status
Simulation time 9165358671 ps
CPU time 59.88 seconds
Started May 07 12:38:47 PM PDT 24
Finished May 07 12:39:48 PM PDT 24
Peak memory 237176 kb
Host smart-fd1cc015-89d5-4156-8450-b4d26b416a82
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2062162143 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_sec_cm.2062162143
Directory /workspace/1.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/1.rom_ctrl_smoke.1770082663
Short name T270
Test name
Test status
Simulation time 2989306092 ps
CPU time 14.83 seconds
Started May 07 12:38:35 PM PDT 24
Finished May 07 12:38:52 PM PDT 24
Peak memory 219992 kb
Host smart-69208ef6-09be-42fc-9af8-9b1c0f840eac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1770082663 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_smoke.1770082663
Directory /workspace/1.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/1.rom_ctrl_stress_all.3816004517
Short name T5
Test name
Test status
Simulation time 25903524385 ps
CPU time 48.73 seconds
Started May 07 12:38:50 PM PDT 24
Finished May 07 12:39:40 PM PDT 24
Peak memory 214452 kb
Host smart-80166078-d8c1-4fd9-a03f-64d8c696fb12
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3816004517 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 1.rom_ctrl_stress_all.3816004517
Directory /workspace/1.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/10.rom_ctrl_alert_test.2197590222
Short name T334
Test name
Test status
Simulation time 88071440 ps
CPU time 4.25 seconds
Started May 07 12:39:02 PM PDT 24
Finished May 07 12:39:09 PM PDT 24
Peak memory 211644 kb
Host smart-914cea49-686b-49d1-bb5b-20444474d775
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2197590222 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_alert_test.2197590222
Directory /workspace/10.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/10.rom_ctrl_corrupt_sig_fatal_chk.3755790820
Short name T292
Test name
Test status
Simulation time 11133146257 ps
CPU time 131.86 seconds
Started May 07 12:38:49 PM PDT 24
Finished May 07 12:41:03 PM PDT 24
Peak memory 228296 kb
Host smart-b04c6af9-8923-48f1-964a-ee877a6dcf6b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3755790820 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_
corrupt_sig_fatal_chk.3755790820
Directory /workspace/10.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/10.rom_ctrl_kmac_err_chk.1173855108
Short name T138
Test name
Test status
Simulation time 1646328539 ps
CPU time 14.99 seconds
Started May 07 12:39:01 PM PDT 24
Finished May 07 12:39:19 PM PDT 24
Peak memory 211748 kb
Host smart-a7211101-5af1-4cd3-bbb0-ee4996ec3534
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1173855108 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_kmac_err_chk.1173855108
Directory /workspace/10.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/10.rom_ctrl_max_throughput_chk.3499401717
Short name T110
Test name
Test status
Simulation time 7228300349 ps
CPU time 15.46 seconds
Started May 07 12:38:46 PM PDT 24
Finished May 07 12:39:04 PM PDT 24
Peak memory 211780 kb
Host smart-21053ae9-e17b-4026-a2b9-b365459961bb
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3499401717 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_max_throughput_chk.3499401717
Directory /workspace/10.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/10.rom_ctrl_smoke.4224869938
Short name T242
Test name
Test status
Simulation time 32853085005 ps
CPU time 43.46 seconds
Started May 07 12:38:48 PM PDT 24
Finished May 07 12:39:34 PM PDT 24
Peak memory 214772 kb
Host smart-89be0695-ea3b-444f-b250-e04fb36c5494
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4224869938 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_smoke.4224869938
Directory /workspace/10.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/10.rom_ctrl_stress_all.3605303859
Short name T162
Test name
Test status
Simulation time 8342228628 ps
CPU time 35.45 seconds
Started May 07 12:38:57 PM PDT 24
Finished May 07 12:39:36 PM PDT 24
Peak memory 214280 kb
Host smart-8a83a194-a66b-4523-b214-328760da41fa
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3605303859 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 10.rom_ctrl_stress_all.3605303859
Directory /workspace/10.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/10.rom_ctrl_stress_all_with_rand_reset.441135545
Short name T112
Test name
Test status
Simulation time 211069970262 ps
CPU time 900.6 seconds
Started May 07 12:38:59 PM PDT 24
Finished May 07 12:54:03 PM PDT 24
Peak memory 231444 kb
Host smart-847d6ff9-241a-4381-a1b3-27953b7d6b9f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=441135545 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_stress_all_with_rand_reset.441135545
Directory /workspace/10.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/11.rom_ctrl_alert_test.2744204073
Short name T189
Test name
Test status
Simulation time 1136938165 ps
CPU time 11.21 seconds
Started May 07 12:38:59 PM PDT 24
Finished May 07 12:39:13 PM PDT 24
Peak memory 211708 kb
Host smart-0ef5b0da-0745-4325-bd88-e995f4d851ef
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2744204073 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_alert_test.2744204073
Directory /workspace/11.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/11.rom_ctrl_kmac_err_chk.3823084755
Short name T131
Test name
Test status
Simulation time 2552668508 ps
CPU time 24.48 seconds
Started May 07 12:38:59 PM PDT 24
Finished May 07 12:39:27 PM PDT 24
Peak memory 211932 kb
Host smart-e6f8b525-b94e-4bd2-a314-c35a82fc5d89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3823084755 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_kmac_err_chk.3823084755
Directory /workspace/11.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/11.rom_ctrl_max_throughput_chk.2998282732
Short name T345
Test name
Test status
Simulation time 1706404660 ps
CPU time 10.39 seconds
Started May 07 12:39:03 PM PDT 24
Finished May 07 12:39:16 PM PDT 24
Peak memory 211588 kb
Host smart-3e30b8fc-574c-4797-948a-705925bbfa17
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2998282732 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_max_throughput_chk.2998282732
Directory /workspace/11.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/11.rom_ctrl_smoke.3601618484
Short name T317
Test name
Test status
Simulation time 1969094565 ps
CPU time 22.51 seconds
Started May 07 12:38:57 PM PDT 24
Finished May 07 12:39:23 PM PDT 24
Peak memory 214000 kb
Host smart-b0e5e312-a7e0-4136-ab40-c59f52889b54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3601618484 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_smoke.3601618484
Directory /workspace/11.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/11.rom_ctrl_stress_all.2429917323
Short name T350
Test name
Test status
Simulation time 6279054826 ps
CPU time 60.01 seconds
Started May 07 12:38:59 PM PDT 24
Finished May 07 12:40:02 PM PDT 24
Peak memory 218196 kb
Host smart-e3cfc14e-6ba9-405f-b591-0f9742129b42
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2429917323 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 11.rom_ctrl_stress_all.2429917323
Directory /workspace/11.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/11.rom_ctrl_stress_all_with_rand_reset.2972435281
Short name T48
Test name
Test status
Simulation time 22685924009 ps
CPU time 2218.88 seconds
Started May 07 12:38:59 PM PDT 24
Finished May 07 01:16:02 PM PDT 24
Peak memory 224828 kb
Host smart-8a58aaef-0cb5-4696-bfcc-e52a5761f1f7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2972435281 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_stress_all_with_rand_reset.2972435281
Directory /workspace/11.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/12.rom_ctrl_alert_test.2926834652
Short name T152
Test name
Test status
Simulation time 1459178651 ps
CPU time 12.64 seconds
Started May 07 12:38:51 PM PDT 24
Finished May 07 12:39:05 PM PDT 24
Peak memory 211704 kb
Host smart-2b8a7c05-e6fe-4cee-9efd-c076f5a930b0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2926834652 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_alert_test.2926834652
Directory /workspace/12.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/12.rom_ctrl_corrupt_sig_fatal_chk.730765569
Short name T210
Test name
Test status
Simulation time 26305708324 ps
CPU time 85.37 seconds
Started May 07 12:38:58 PM PDT 24
Finished May 07 12:40:27 PM PDT 24
Peak memory 231296 kb
Host smart-e1311b52-35aa-485f-bafe-30e5bd266ce0
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=730765569 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_c
orrupt_sig_fatal_chk.730765569
Directory /workspace/12.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/12.rom_ctrl_kmac_err_chk.3187133587
Short name T332
Test name
Test status
Simulation time 334074626 ps
CPU time 9.35 seconds
Started May 07 12:38:59 PM PDT 24
Finished May 07 12:39:13 PM PDT 24
Peak memory 212448 kb
Host smart-758e396f-a9c9-46b2-9444-deb601ba966f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3187133587 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_kmac_err_chk.3187133587
Directory /workspace/12.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/12.rom_ctrl_max_throughput_chk.2439953826
Short name T95
Test name
Test status
Simulation time 995463951 ps
CPU time 11.24 seconds
Started May 07 12:38:58 PM PDT 24
Finished May 07 12:39:13 PM PDT 24
Peak memory 211672 kb
Host smart-6bb77a00-6d6c-4025-9d6e-66b30d18c67c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2439953826 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_max_throughput_chk.2439953826
Directory /workspace/12.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/12.rom_ctrl_smoke.611558993
Short name T181
Test name
Test status
Simulation time 3120553810 ps
CPU time 16.06 seconds
Started May 07 12:38:56 PM PDT 24
Finished May 07 12:39:16 PM PDT 24
Peak memory 214448 kb
Host smart-0a5d42fe-757c-4104-a0b9-10e5b4c09277
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=611558993 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_smoke.611558993
Directory /workspace/12.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/12.rom_ctrl_stress_all.2170714482
Short name T278
Test name
Test status
Simulation time 16860742043 ps
CPU time 77.76 seconds
Started May 07 12:38:57 PM PDT 24
Finished May 07 12:40:18 PM PDT 24
Peak memory 217168 kb
Host smart-614cfb66-9ba2-461b-808c-6dfa1ff4b114
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2170714482 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 12.rom_ctrl_stress_all.2170714482
Directory /workspace/12.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/13.rom_ctrl_alert_test.1860787334
Short name T294
Test name
Test status
Simulation time 1316938331 ps
CPU time 6.6 seconds
Started May 07 12:38:59 PM PDT 24
Finished May 07 12:39:09 PM PDT 24
Peak memory 211688 kb
Host smart-205d3e57-ac30-41bc-b0a6-da4e7ea9eedc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1860787334 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_alert_test.1860787334
Directory /workspace/13.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/13.rom_ctrl_corrupt_sig_fatal_chk.3512834654
Short name T40
Test name
Test status
Simulation time 128437261421 ps
CPU time 387.6 seconds
Started May 07 12:38:58 PM PDT 24
Finished May 07 12:45:30 PM PDT 24
Peak memory 234768 kb
Host smart-43e73586-9c9c-4e9d-8543-0c51bc5ea2a9
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3512834654 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_
corrupt_sig_fatal_chk.3512834654
Directory /workspace/13.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/13.rom_ctrl_kmac_err_chk.2708276938
Short name T224
Test name
Test status
Simulation time 14443096994 ps
CPU time 29.35 seconds
Started May 07 12:38:44 PM PDT 24
Finished May 07 12:39:15 PM PDT 24
Peak memory 212584 kb
Host smart-97588bde-40d3-4d3f-874b-65ba65334fd7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2708276938 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_kmac_err_chk.2708276938
Directory /workspace/13.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/13.rom_ctrl_max_throughput_chk.1982828071
Short name T271
Test name
Test status
Simulation time 1386500259 ps
CPU time 13.33 seconds
Started May 07 12:38:57 PM PDT 24
Finished May 07 12:39:13 PM PDT 24
Peak memory 211652 kb
Host smart-a33d5399-870a-4f25-ac54-57d275e2b5cb
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1982828071 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_max_throughput_chk.1982828071
Directory /workspace/13.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/13.rom_ctrl_smoke.1320190778
Short name T208
Test name
Test status
Simulation time 3069242091 ps
CPU time 30.84 seconds
Started May 07 12:39:02 PM PDT 24
Finished May 07 12:39:36 PM PDT 24
Peak memory 219932 kb
Host smart-7dc0f3c9-dd72-476d-b684-02f66b1855ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1320190778 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_smoke.1320190778
Directory /workspace/13.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/13.rom_ctrl_stress_all.2066199144
Short name T261
Test name
Test status
Simulation time 117424498 ps
CPU time 6.01 seconds
Started May 07 12:39:01 PM PDT 24
Finished May 07 12:39:10 PM PDT 24
Peak memory 211672 kb
Host smart-c7560c66-826f-45d1-8ea3-22783504f095
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2066199144 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 13.rom_ctrl_stress_all.2066199144
Directory /workspace/13.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/14.rom_ctrl_corrupt_sig_fatal_chk.1738515840
Short name T24
Test name
Test status
Simulation time 1713541202 ps
CPU time 100.25 seconds
Started May 07 12:38:58 PM PDT 24
Finished May 07 12:40:42 PM PDT 24
Peak memory 220060 kb
Host smart-42f26bbe-f183-4595-85ad-cb5920fca077
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1738515840 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_
corrupt_sig_fatal_chk.1738515840
Directory /workspace/14.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/14.rom_ctrl_kmac_err_chk.2198963864
Short name T3
Test name
Test status
Simulation time 829690067 ps
CPU time 12.62 seconds
Started May 07 12:38:49 PM PDT 24
Finished May 07 12:39:04 PM PDT 24
Peak memory 212232 kb
Host smart-f0dcd18f-7699-49da-9ec7-18cc566e2aba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2198963864 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_kmac_err_chk.2198963864
Directory /workspace/14.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/14.rom_ctrl_max_throughput_chk.3213849565
Short name T219
Test name
Test status
Simulation time 1424883715 ps
CPU time 13.66 seconds
Started May 07 12:38:53 PM PDT 24
Finished May 07 12:39:10 PM PDT 24
Peak memory 211652 kb
Host smart-9c21ef71-61b4-4abf-a647-243f5018e508
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3213849565 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_max_throughput_chk.3213849565
Directory /workspace/14.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/14.rom_ctrl_smoke.2551544512
Short name T203
Test name
Test status
Simulation time 4049103832 ps
CPU time 26.65 seconds
Started May 07 12:38:59 PM PDT 24
Finished May 07 12:39:29 PM PDT 24
Peak memory 214064 kb
Host smart-d02f7c0f-9e4c-4211-b621-a81c522f0ddc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2551544512 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_smoke.2551544512
Directory /workspace/14.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/14.rom_ctrl_stress_all.2382411447
Short name T172
Test name
Test status
Simulation time 8323756982 ps
CPU time 18 seconds
Started May 07 12:38:56 PM PDT 24
Finished May 07 12:39:17 PM PDT 24
Peak memory 212868 kb
Host smart-36cad29f-8a54-4e2e-81d5-17ef48f40a1e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2382411447 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 14.rom_ctrl_stress_all.2382411447
Directory /workspace/14.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/15.rom_ctrl_alert_test.4147718674
Short name T179
Test name
Test status
Simulation time 85569713 ps
CPU time 4.22 seconds
Started May 07 12:38:51 PM PDT 24
Finished May 07 12:38:57 PM PDT 24
Peak memory 211716 kb
Host smart-53e3ca21-7412-4678-b4e1-bc3fa226e948
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4147718674 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_alert_test.4147718674
Directory /workspace/15.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/15.rom_ctrl_corrupt_sig_fatal_chk.897599936
Short name T250
Test name
Test status
Simulation time 26542911529 ps
CPU time 171.07 seconds
Started May 07 12:38:53 PM PDT 24
Finished May 07 12:41:47 PM PDT 24
Peak memory 231384 kb
Host smart-f3bfabdf-bc3f-421c-ac44-36e2f76c009c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=897599936 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_c
orrupt_sig_fatal_chk.897599936
Directory /workspace/15.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/15.rom_ctrl_kmac_err_chk.3524069246
Short name T229
Test name
Test status
Simulation time 1383905456 ps
CPU time 9.54 seconds
Started May 07 12:38:51 PM PDT 24
Finished May 07 12:39:08 PM PDT 24
Peak memory 212256 kb
Host smart-419c3c5e-94f8-4f98-884e-803f4417d866
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3524069246 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_kmac_err_chk.3524069246
Directory /workspace/15.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/15.rom_ctrl_max_throughput_chk.2425941475
Short name T237
Test name
Test status
Simulation time 7681369372 ps
CPU time 16.03 seconds
Started May 07 12:38:56 PM PDT 24
Finished May 07 12:39:15 PM PDT 24
Peak memory 211716 kb
Host smart-95d470c4-6ee6-4b83-bee4-25c6b509ee29
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2425941475 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_max_throughput_chk.2425941475
Directory /workspace/15.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/15.rom_ctrl_smoke.716542847
Short name T88
Test name
Test status
Simulation time 2987813511 ps
CPU time 31.03 seconds
Started May 07 12:38:57 PM PDT 24
Finished May 07 12:39:32 PM PDT 24
Peak memory 219992 kb
Host smart-2a43df7c-fd28-4209-a3fa-7c26874f9ea5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=716542847 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_smoke.716542847
Directory /workspace/15.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/15.rom_ctrl_stress_all.3351306690
Short name T59
Test name
Test status
Simulation time 672989797 ps
CPU time 10.61 seconds
Started May 07 12:39:05 PM PDT 24
Finished May 07 12:39:17 PM PDT 24
Peak memory 211480 kb
Host smart-cbc8170b-a6d9-4e58-9f22-b96abb894422
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3351306690 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 15.rom_ctrl_stress_all.3351306690
Directory /workspace/15.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/16.rom_ctrl_alert_test.386129518
Short name T307
Test name
Test status
Simulation time 5091777910 ps
CPU time 11.91 seconds
Started May 07 12:39:00 PM PDT 24
Finished May 07 12:39:16 PM PDT 24
Peak memory 211836 kb
Host smart-182d6411-d067-48e8-963a-7f60edfa2f31
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=386129518 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_alert_test.386129518
Directory /workspace/16.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/16.rom_ctrl_corrupt_sig_fatal_chk.1997848098
Short name T319
Test name
Test status
Simulation time 15442402947 ps
CPU time 78.39 seconds
Started May 07 12:38:59 PM PDT 24
Finished May 07 12:40:21 PM PDT 24
Peak memory 232784 kb
Host smart-55264260-7948-4647-bba5-5caf5b1a1a9f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1997848098 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_
corrupt_sig_fatal_chk.1997848098
Directory /workspace/16.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/16.rom_ctrl_kmac_err_chk.1969897391
Short name T190
Test name
Test status
Simulation time 5561025776 ps
CPU time 25.96 seconds
Started May 07 12:38:47 PM PDT 24
Finished May 07 12:39:15 PM PDT 24
Peak memory 212756 kb
Host smart-3aa4f23f-cad6-4b35-b7cc-8b8d2f6ead22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1969897391 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_kmac_err_chk.1969897391
Directory /workspace/16.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/16.rom_ctrl_max_throughput_chk.1911813703
Short name T288
Test name
Test status
Simulation time 8569374122 ps
CPU time 14.06 seconds
Started May 07 12:38:54 PM PDT 24
Finished May 07 12:39:11 PM PDT 24
Peak memory 211740 kb
Host smart-58eff797-ed76-4549-ad14-9c9b9c2f58e8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1911813703 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_max_throughput_chk.1911813703
Directory /workspace/16.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/16.rom_ctrl_smoke.2486682936
Short name T72
Test name
Test status
Simulation time 5986041151 ps
CPU time 21.55 seconds
Started May 07 12:38:55 PM PDT 24
Finished May 07 12:39:19 PM PDT 24
Peak memory 215304 kb
Host smart-5413e989-baac-4351-a99e-099e304ba7f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2486682936 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_smoke.2486682936
Directory /workspace/16.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/16.rom_ctrl_stress_all.598483748
Short name T358
Test name
Test status
Simulation time 8994957844 ps
CPU time 46.08 seconds
Started May 07 12:38:52 PM PDT 24
Finished May 07 12:39:40 PM PDT 24
Peak memory 219940 kb
Host smart-7377eb9d-b933-479c-ad5c-a485b916bc01
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=598483748 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 16.rom_ctrl_stress_all.598483748
Directory /workspace/16.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/17.rom_ctrl_alert_test.1011833710
Short name T139
Test name
Test status
Simulation time 3955583136 ps
CPU time 15.84 seconds
Started May 07 12:39:02 PM PDT 24
Finished May 07 12:39:21 PM PDT 24
Peak memory 211772 kb
Host smart-341f1a6d-b35d-46ff-a6fe-f3f14c8dc46a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1011833710 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_alert_test.1011833710
Directory /workspace/17.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/17.rom_ctrl_corrupt_sig_fatal_chk.1276346621
Short name T200
Test name
Test status
Simulation time 4968441516 ps
CPU time 87.85 seconds
Started May 07 12:38:56 PM PDT 24
Finished May 07 12:40:28 PM PDT 24
Peak memory 239484 kb
Host smart-16d30684-4c3d-43ae-8a01-325eea366e14
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1276346621 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_
corrupt_sig_fatal_chk.1276346621
Directory /workspace/17.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/17.rom_ctrl_kmac_err_chk.2867561755
Short name T296
Test name
Test status
Simulation time 4761076232 ps
CPU time 23.53 seconds
Started May 07 12:39:04 PM PDT 24
Finished May 07 12:39:30 PM PDT 24
Peak memory 212824 kb
Host smart-690fb05d-f0a8-4ca3-a67c-3dde70e9b62a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2867561755 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_kmac_err_chk.2867561755
Directory /workspace/17.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/17.rom_ctrl_max_throughput_chk.2391848388
Short name T308
Test name
Test status
Simulation time 358370997 ps
CPU time 5.5 seconds
Started May 07 12:38:56 PM PDT 24
Finished May 07 12:39:04 PM PDT 24
Peak memory 211664 kb
Host smart-05ef10ff-23ee-44d2-a51d-1e9483beeb64
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2391848388 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_max_throughput_chk.2391848388
Directory /workspace/17.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/17.rom_ctrl_stress_all.162405199
Short name T69
Test name
Test status
Simulation time 17563642931 ps
CPU time 43.4 seconds
Started May 07 12:39:06 PM PDT 24
Finished May 07 12:39:51 PM PDT 24
Peak memory 219920 kb
Host smart-1665bc5a-f39a-44a4-8f2d-e2c3b2a19d70
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=162405199 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 17.rom_ctrl_stress_all.162405199
Directory /workspace/17.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/18.rom_ctrl_alert_test.1596337396
Short name T215
Test name
Test status
Simulation time 2157229749 ps
CPU time 16.78 seconds
Started May 07 12:39:01 PM PDT 24
Finished May 07 12:39:21 PM PDT 24
Peak memory 211824 kb
Host smart-dfcea982-b48f-44a4-a1e1-2be2f6fc0f81
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1596337396 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_alert_test.1596337396
Directory /workspace/18.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/18.rom_ctrl_kmac_err_chk.2251223622
Short name T22
Test name
Test status
Simulation time 8212168041 ps
CPU time 21.99 seconds
Started May 07 12:38:55 PM PDT 24
Finished May 07 12:39:20 PM PDT 24
Peak memory 211896 kb
Host smart-d8bbbe84-8da9-4fd0-bbac-1d34c1b1e669
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2251223622 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_kmac_err_chk.2251223622
Directory /workspace/18.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/18.rom_ctrl_max_throughput_chk.2060118472
Short name T258
Test name
Test status
Simulation time 1411156196 ps
CPU time 7.83 seconds
Started May 07 12:39:04 PM PDT 24
Finished May 07 12:39:14 PM PDT 24
Peak memory 211672 kb
Host smart-f69566a8-91b1-44eb-9f7b-0f7afcba048b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2060118472 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_max_throughput_chk.2060118472
Directory /workspace/18.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/18.rom_ctrl_smoke.504735824
Short name T165
Test name
Test status
Simulation time 1410714547 ps
CPU time 10.02 seconds
Started May 07 12:39:06 PM PDT 24
Finished May 07 12:39:23 PM PDT 24
Peak memory 214296 kb
Host smart-4ad4e4d8-4c6f-41d7-a9e1-d8506cfcd5d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=504735824 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_smoke.504735824
Directory /workspace/18.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/18.rom_ctrl_stress_all.4114317647
Short name T74
Test name
Test status
Simulation time 823533696 ps
CPU time 14.46 seconds
Started May 07 12:38:58 PM PDT 24
Finished May 07 12:39:17 PM PDT 24
Peak memory 211792 kb
Host smart-ea1294ca-ab96-4de2-98df-13fb0457803c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4114317647 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 18.rom_ctrl_stress_all.4114317647
Directory /workspace/18.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/18.rom_ctrl_stress_all_with_rand_reset.3891119038
Short name T46
Test name
Test status
Simulation time 19232668001 ps
CPU time 5367.32 seconds
Started May 07 12:39:01 PM PDT 24
Finished May 07 02:08:32 PM PDT 24
Peak memory 236468 kb
Host smart-22abbe6f-74a4-42ff-a80d-efc42f87435b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3891119038 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_stress_all_with_rand_reset.3891119038
Directory /workspace/18.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/19.rom_ctrl_alert_test.3688456664
Short name T330
Test name
Test status
Simulation time 1969935523 ps
CPU time 15.37 seconds
Started May 07 12:38:57 PM PDT 24
Finished May 07 12:39:15 PM PDT 24
Peak memory 211708 kb
Host smart-042c7706-235e-4f98-bf76-35a536ce12f0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3688456664 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_alert_test.3688456664
Directory /workspace/19.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/19.rom_ctrl_corrupt_sig_fatal_chk.147708196
Short name T186
Test name
Test status
Simulation time 23818700913 ps
CPU time 135.56 seconds
Started May 07 12:38:53 PM PDT 24
Finished May 07 12:41:11 PM PDT 24
Peak memory 220240 kb
Host smart-f3c39315-82a8-46db-848b-8cb4cfea87df
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=147708196 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_c
orrupt_sig_fatal_chk.147708196
Directory /workspace/19.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/19.rom_ctrl_kmac_err_chk.3973487054
Short name T221
Test name
Test status
Simulation time 3327266873 ps
CPU time 28.89 seconds
Started May 07 12:38:58 PM PDT 24
Finished May 07 12:39:30 PM PDT 24
Peak memory 212260 kb
Host smart-8ff35b77-1868-422c-a734-c2245c63dd39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3973487054 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_kmac_err_chk.3973487054
Directory /workspace/19.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/19.rom_ctrl_max_throughput_chk.1416640255
Short name T195
Test name
Test status
Simulation time 1199165885 ps
CPU time 11.7 seconds
Started May 07 12:38:58 PM PDT 24
Finished May 07 12:39:13 PM PDT 24
Peak memory 211556 kb
Host smart-84b0652d-b019-4f97-8054-288dae3c26cd
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1416640255 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_max_throughput_chk.1416640255
Directory /workspace/19.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/19.rom_ctrl_smoke.3517924771
Short name T111
Test name
Test status
Simulation time 3564782094 ps
CPU time 31.16 seconds
Started May 07 12:38:53 PM PDT 24
Finished May 07 12:39:26 PM PDT 24
Peak memory 213496 kb
Host smart-7002af9c-d272-4aa8-ba34-0f6c49d81f93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3517924771 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_smoke.3517924771
Directory /workspace/19.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/19.rom_ctrl_stress_all.204617602
Short name T222
Test name
Test status
Simulation time 2513078522 ps
CPU time 22.02 seconds
Started May 07 12:39:11 PM PDT 24
Finished May 07 12:39:41 PM PDT 24
Peak memory 214392 kb
Host smart-ec392083-689c-4577-aa17-979872f81d10
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=204617602 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 19.rom_ctrl_stress_all.204617602
Directory /workspace/19.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/2.rom_ctrl_alert_test.2717718087
Short name T287
Test name
Test status
Simulation time 1659234407 ps
CPU time 4.29 seconds
Started May 07 12:38:46 PM PDT 24
Finished May 07 12:38:52 PM PDT 24
Peak memory 211800 kb
Host smart-c710b53f-d424-4a7e-b556-39b9fed11757
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2717718087 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_alert_test.2717718087
Directory /workspace/2.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/2.rom_ctrl_corrupt_sig_fatal_chk.1551172895
Short name T310
Test name
Test status
Simulation time 18328228826 ps
CPU time 222.57 seconds
Started May 07 12:38:43 PM PDT 24
Finished May 07 12:42:28 PM PDT 24
Peak memory 239332 kb
Host smart-b650eb95-eec6-4c8c-bd8a-c8113eae4296
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1551172895 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_c
orrupt_sig_fatal_chk.1551172895
Directory /workspace/2.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/2.rom_ctrl_kmac_err_chk.607631645
Short name T183
Test name
Test status
Simulation time 2448043143 ps
CPU time 23.8 seconds
Started May 07 12:38:54 PM PDT 24
Finished May 07 12:39:21 PM PDT 24
Peak memory 211884 kb
Host smart-59dc3542-5022-4831-9e2d-bef1978c1a01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=607631645 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_kmac_err_chk.607631645
Directory /workspace/2.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/2.rom_ctrl_max_throughput_chk.2633801583
Short name T226
Test name
Test status
Simulation time 3438124781 ps
CPU time 10.67 seconds
Started May 07 12:38:48 PM PDT 24
Finished May 07 12:39:01 PM PDT 24
Peak memory 211764 kb
Host smart-cf9a7274-e0ee-4267-9f2b-7c450066ff6c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2633801583 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_max_throughput_chk.2633801583
Directory /workspace/2.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/2.rom_ctrl_sec_cm.2760468265
Short name T29
Test name
Test status
Simulation time 1483754063 ps
CPU time 107.64 seconds
Started May 07 12:38:43 PM PDT 24
Finished May 07 12:40:33 PM PDT 24
Peak memory 230012 kb
Host smart-efe8fc6b-30aa-4adf-ba0c-523aead210dc
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2760468265 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_sec_cm.2760468265
Directory /workspace/2.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/2.rom_ctrl_smoke.1648797326
Short name T256
Test name
Test status
Simulation time 1325029478 ps
CPU time 9.66 seconds
Started May 07 12:39:13 PM PDT 24
Finished May 07 12:39:24 PM PDT 24
Peak memory 214200 kb
Host smart-cecd4c13-c494-4138-8824-1f10051dffd3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1648797326 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_smoke.1648797326
Directory /workspace/2.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/2.rom_ctrl_stress_all.4020354810
Short name T58
Test name
Test status
Simulation time 4850292763 ps
CPU time 18.51 seconds
Started May 07 12:38:54 PM PDT 24
Finished May 07 12:39:15 PM PDT 24
Peak memory 213988 kb
Host smart-d3ca44a1-eb07-402d-95d7-f5b67f9dc92a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4020354810 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 2.rom_ctrl_stress_all.4020354810
Directory /workspace/2.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/20.rom_ctrl_alert_test.3081080181
Short name T356
Test name
Test status
Simulation time 1120428820 ps
CPU time 6 seconds
Started May 07 12:39:04 PM PDT 24
Finished May 07 12:39:12 PM PDT 24
Peak memory 211616 kb
Host smart-c60d0739-c8b8-4674-8348-4912f4d5e88b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3081080181 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_alert_test.3081080181
Directory /workspace/20.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/20.rom_ctrl_corrupt_sig_fatal_chk.186932390
Short name T18
Test name
Test status
Simulation time 326536246274 ps
CPU time 432.24 seconds
Started May 07 12:39:10 PM PDT 24
Finished May 07 12:46:23 PM PDT 24
Peak memory 234348 kb
Host smart-81665198-2bc3-4fc7-b989-3a8158f3d8eb
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=186932390 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_c
orrupt_sig_fatal_chk.186932390
Directory /workspace/20.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/20.rom_ctrl_kmac_err_chk.171740608
Short name T277
Test name
Test status
Simulation time 4268706462 ps
CPU time 32.63 seconds
Started May 07 12:39:05 PM PDT 24
Finished May 07 12:39:39 PM PDT 24
Peak memory 212408 kb
Host smart-f14aeb01-468a-4add-8661-7610ffca4bcc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=171740608 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_kmac_err_chk.171740608
Directory /workspace/20.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/20.rom_ctrl_max_throughput_chk.2763996182
Short name T255
Test name
Test status
Simulation time 16019397940 ps
CPU time 16.9 seconds
Started May 07 12:38:58 PM PDT 24
Finished May 07 12:39:18 PM PDT 24
Peak memory 211744 kb
Host smart-ea5ad27e-e920-4651-9c72-313da58d0884
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2763996182 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_max_throughput_chk.2763996182
Directory /workspace/20.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/20.rom_ctrl_smoke.2279091910
Short name T269
Test name
Test status
Simulation time 707870498 ps
CPU time 10.39 seconds
Started May 07 12:38:52 PM PDT 24
Finished May 07 12:39:04 PM PDT 24
Peak memory 219988 kb
Host smart-22bf6bc5-4cff-4161-8c43-b542c53816cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2279091910 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_smoke.2279091910
Directory /workspace/20.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/20.rom_ctrl_stress_all.3066143224
Short name T136
Test name
Test status
Simulation time 3511117784 ps
CPU time 34.36 seconds
Started May 07 12:39:00 PM PDT 24
Finished May 07 12:39:38 PM PDT 24
Peak memory 215188 kb
Host smart-64e08c43-da1f-4de2-92b8-ab32035c4cc3
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3066143224 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 20.rom_ctrl_stress_all.3066143224
Directory /workspace/20.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/21.rom_ctrl_alert_test.1270366213
Short name T286
Test name
Test status
Simulation time 1469256426 ps
CPU time 13.37 seconds
Started May 07 12:39:01 PM PDT 24
Finished May 07 12:39:17 PM PDT 24
Peak memory 211192 kb
Host smart-de2e1b9d-d89a-4fd1-899f-89c7e133252b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1270366213 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_alert_test.1270366213
Directory /workspace/21.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/21.rom_ctrl_corrupt_sig_fatal_chk.3111517277
Short name T41
Test name
Test status
Simulation time 66533594274 ps
CPU time 224.33 seconds
Started May 07 12:38:56 PM PDT 24
Finished May 07 12:42:43 PM PDT 24
Peak memory 235320 kb
Host smart-989379af-8a6e-45a9-93d9-efd59a686ed0
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3111517277 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_
corrupt_sig_fatal_chk.3111517277
Directory /workspace/21.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/21.rom_ctrl_kmac_err_chk.1898723960
Short name T312
Test name
Test status
Simulation time 6227571607 ps
CPU time 19.69 seconds
Started May 07 12:38:53 PM PDT 24
Finished May 07 12:39:15 PM PDT 24
Peak memory 212736 kb
Host smart-eb88fc97-b1ba-4731-baa3-20650aed1f9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1898723960 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_kmac_err_chk.1898723960
Directory /workspace/21.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/21.rom_ctrl_max_throughput_chk.2950859921
Short name T327
Test name
Test status
Simulation time 6294879599 ps
CPU time 14.89 seconds
Started May 07 12:38:57 PM PDT 24
Finished May 07 12:39:15 PM PDT 24
Peak memory 211796 kb
Host smart-5f630085-d23c-4bc2-84a4-75c892950ac5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2950859921 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_max_throughput_chk.2950859921
Directory /workspace/21.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/21.rom_ctrl_smoke.3630172358
Short name T70
Test name
Test status
Simulation time 874318333 ps
CPU time 16.82 seconds
Started May 07 12:38:56 PM PDT 24
Finished May 07 12:39:16 PM PDT 24
Peak memory 214364 kb
Host smart-59fc4304-bb4a-4b95-ac4f-f849822b7603
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3630172358 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_smoke.3630172358
Directory /workspace/21.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/21.rom_ctrl_stress_all.1794116038
Short name T180
Test name
Test status
Simulation time 427635586 ps
CPU time 23.24 seconds
Started May 07 12:39:15 PM PDT 24
Finished May 07 12:39:40 PM PDT 24
Peak memory 215864 kb
Host smart-143f8775-cea6-4720-9202-a0fd9450f7a9
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1794116038 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 21.rom_ctrl_stress_all.1794116038
Directory /workspace/21.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/22.rom_ctrl_alert_test.2958170384
Short name T193
Test name
Test status
Simulation time 5114348003 ps
CPU time 11.79 seconds
Started May 07 12:38:58 PM PDT 24
Finished May 07 12:39:13 PM PDT 24
Peak memory 211676 kb
Host smart-04369db4-91e2-405f-b255-64534fc5a237
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2958170384 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_alert_test.2958170384
Directory /workspace/22.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/22.rom_ctrl_kmac_err_chk.2714292426
Short name T247
Test name
Test status
Simulation time 7354667786 ps
CPU time 30.95 seconds
Started May 07 12:39:07 PM PDT 24
Finished May 07 12:39:40 PM PDT 24
Peak memory 213128 kb
Host smart-bc46b613-e848-4c30-b85a-5803c9f09a74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2714292426 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_kmac_err_chk.2714292426
Directory /workspace/22.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/22.rom_ctrl_max_throughput_chk.3106241674
Short name T108
Test name
Test status
Simulation time 920446356 ps
CPU time 10.39 seconds
Started May 07 12:39:04 PM PDT 24
Finished May 07 12:39:17 PM PDT 24
Peak memory 211636 kb
Host smart-ad71640b-87b2-4101-8745-4a5d204d7d09
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3106241674 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_max_throughput_chk.3106241674
Directory /workspace/22.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/22.rom_ctrl_smoke.3554770467
Short name T251
Test name
Test status
Simulation time 3049586446 ps
CPU time 22.52 seconds
Started May 07 12:39:06 PM PDT 24
Finished May 07 12:39:35 PM PDT 24
Peak memory 214296 kb
Host smart-0f9d90e7-a63e-4f30-9cbc-43544c885e4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3554770467 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_smoke.3554770467
Directory /workspace/22.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/22.rom_ctrl_stress_all.2635374955
Short name T196
Test name
Test status
Simulation time 2400899474 ps
CPU time 31.75 seconds
Started May 07 12:38:55 PM PDT 24
Finished May 07 12:39:30 PM PDT 24
Peak memory 216288 kb
Host smart-91a91028-d680-49e3-8b6c-4bbf4f318c2a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2635374955 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 22.rom_ctrl_stress_all.2635374955
Directory /workspace/22.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/23.rom_ctrl_alert_test.952840843
Short name T320
Test name
Test status
Simulation time 6457166630 ps
CPU time 13.36 seconds
Started May 07 12:39:12 PM PDT 24
Finished May 07 12:39:27 PM PDT 24
Peak memory 211732 kb
Host smart-5b9f3c32-d200-4395-9363-f2f98960a18a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=952840843 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_alert_test.952840843
Directory /workspace/23.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/23.rom_ctrl_kmac_err_chk.3229177376
Short name T217
Test name
Test status
Simulation time 12686062221 ps
CPU time 28.29 seconds
Started May 07 12:39:12 PM PDT 24
Finished May 07 12:39:42 PM PDT 24
Peak memory 212680 kb
Host smart-d9d379c3-358d-4149-ab5c-be6b6a184466
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3229177376 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_kmac_err_chk.3229177376
Directory /workspace/23.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/23.rom_ctrl_max_throughput_chk.1300719035
Short name T140
Test name
Test status
Simulation time 368002177 ps
CPU time 7.08 seconds
Started May 07 12:39:00 PM PDT 24
Finished May 07 12:39:10 PM PDT 24
Peak memory 211676 kb
Host smart-5ad84a19-9684-49a2-b852-4c55db7fc11c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1300719035 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_max_throughput_chk.1300719035
Directory /workspace/23.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/23.rom_ctrl_smoke.3920890127
Short name T151
Test name
Test status
Simulation time 15039694742 ps
CPU time 31.14 seconds
Started May 07 12:38:56 PM PDT 24
Finished May 07 12:39:30 PM PDT 24
Peak memory 220016 kb
Host smart-938ae6a3-054e-43a3-bf75-e9dc6f9728d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3920890127 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_smoke.3920890127
Directory /workspace/23.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/23.rom_ctrl_stress_all.3828804870
Short name T352
Test name
Test status
Simulation time 1756739513 ps
CPU time 17.44 seconds
Started May 07 12:39:15 PM PDT 24
Finished May 07 12:39:35 PM PDT 24
Peak memory 212368 kb
Host smart-1b2dd423-1583-4be5-90ac-57a290ea93fc
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3828804870 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 23.rom_ctrl_stress_all.3828804870
Directory /workspace/23.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/23.rom_ctrl_stress_all_with_rand_reset.3717575153
Short name T14
Test name
Test status
Simulation time 208779566833 ps
CPU time 9455.63 seconds
Started May 07 12:38:57 PM PDT 24
Finished May 07 03:16:37 PM PDT 24
Peak memory 236940 kb
Host smart-691437cc-2cbe-405f-a252-83a0b5554d0c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3717575153 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_stress_all_with_rand_reset.3717575153
Directory /workspace/23.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/24.rom_ctrl_alert_test.2943014239
Short name T133
Test name
Test status
Simulation time 4129986110 ps
CPU time 9.76 seconds
Started May 07 12:39:11 PM PDT 24
Finished May 07 12:39:23 PM PDT 24
Peak memory 211800 kb
Host smart-1cd4a3f5-7877-46e3-b127-39b7eced7a9d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2943014239 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_alert_test.2943014239
Directory /workspace/24.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/24.rom_ctrl_corrupt_sig_fatal_chk.2217953309
Short name T276
Test name
Test status
Simulation time 89433001080 ps
CPU time 267.76 seconds
Started May 07 12:39:07 PM PDT 24
Finished May 07 12:43:37 PM PDT 24
Peak memory 240012 kb
Host smart-39b5e416-4c58-4e04-91bd-6046483fd4c5
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2217953309 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_
corrupt_sig_fatal_chk.2217953309
Directory /workspace/24.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/24.rom_ctrl_kmac_err_chk.4015047345
Short name T305
Test name
Test status
Simulation time 6683394426 ps
CPU time 29.22 seconds
Started May 07 12:39:07 PM PDT 24
Finished May 07 12:39:38 PM PDT 24
Peak memory 213004 kb
Host smart-91b5ba3d-070c-41a8-a322-6b0b50ed647b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4015047345 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_kmac_err_chk.4015047345
Directory /workspace/24.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/24.rom_ctrl_max_throughput_chk.3681763162
Short name T106
Test name
Test status
Simulation time 584264705 ps
CPU time 5.76 seconds
Started May 07 12:39:16 PM PDT 24
Finished May 07 12:39:25 PM PDT 24
Peak memory 211664 kb
Host smart-912a7839-0efb-4c9c-8aa2-dc6eccbd7b31
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3681763162 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_max_throughput_chk.3681763162
Directory /workspace/24.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/24.rom_ctrl_smoke.4021364628
Short name T150
Test name
Test status
Simulation time 3124698890 ps
CPU time 33.2 seconds
Started May 07 12:38:58 PM PDT 24
Finished May 07 12:39:39 PM PDT 24
Peak memory 220028 kb
Host smart-5dbbf9d7-602a-4c7f-a464-aa9e9ef05ff5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4021364628 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_smoke.4021364628
Directory /workspace/24.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/24.rom_ctrl_stress_all.556087083
Short name T209
Test name
Test status
Simulation time 435626864 ps
CPU time 15.24 seconds
Started May 07 12:38:58 PM PDT 24
Finished May 07 12:39:17 PM PDT 24
Peak memory 212668 kb
Host smart-6626a1fc-8ffa-473a-aff6-3630e19049c9
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=556087083 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 24.rom_ctrl_stress_all.556087083
Directory /workspace/24.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/25.rom_ctrl_alert_test.1078835036
Short name T159
Test name
Test status
Simulation time 1395406289 ps
CPU time 11.92 seconds
Started May 07 12:39:00 PM PDT 24
Finished May 07 12:39:16 PM PDT 24
Peak memory 211688 kb
Host smart-98710c1f-41e2-4d18-b4c7-b5568e9bf10d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1078835036 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_alert_test.1078835036
Directory /workspace/25.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/25.rom_ctrl_corrupt_sig_fatal_chk.4018157618
Short name T360
Test name
Test status
Simulation time 62215901080 ps
CPU time 358.47 seconds
Started May 07 12:39:03 PM PDT 24
Finished May 07 12:45:04 PM PDT 24
Peak memory 235308 kb
Host smart-41d010cf-9b75-4d5d-8178-c4cd64e3946d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4018157618 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_
corrupt_sig_fatal_chk.4018157618
Directory /workspace/25.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/25.rom_ctrl_max_throughput_chk.1854635110
Short name T260
Test name
Test status
Simulation time 4016602268 ps
CPU time 16.32 seconds
Started May 07 12:38:56 PM PDT 24
Finished May 07 12:39:16 PM PDT 24
Peak memory 211780 kb
Host smart-0f248d9d-59d4-4bec-bb29-d82159c5834c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1854635110 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_max_throughput_chk.1854635110
Directory /workspace/25.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/25.rom_ctrl_smoke.2886785146
Short name T147
Test name
Test status
Simulation time 27677830647 ps
CPU time 31.75 seconds
Started May 07 12:38:58 PM PDT 24
Finished May 07 12:39:33 PM PDT 24
Peak memory 214784 kb
Host smart-27eeb7a1-2bd8-4ecf-b5f4-cf077803f91f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2886785146 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_smoke.2886785146
Directory /workspace/25.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/25.rom_ctrl_stress_all.2205046918
Short name T235
Test name
Test status
Simulation time 4177053284 ps
CPU time 45.45 seconds
Started May 07 12:39:22 PM PDT 24
Finished May 07 12:40:09 PM PDT 24
Peak memory 216916 kb
Host smart-09fbc934-d556-4e54-b737-9234d3e2906a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2205046918 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 25.rom_ctrl_stress_all.2205046918
Directory /workspace/25.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/26.rom_ctrl_alert_test.2358550161
Short name T353
Test name
Test status
Simulation time 7704844669 ps
CPU time 15.86 seconds
Started May 07 12:39:01 PM PDT 24
Finished May 07 12:39:20 PM PDT 24
Peak memory 211744 kb
Host smart-0807138c-0159-41ce-a8e2-00e8b42e7da0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2358550161 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_alert_test.2358550161
Directory /workspace/26.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/26.rom_ctrl_corrupt_sig_fatal_chk.1682563378
Short name T212
Test name
Test status
Simulation time 27201632649 ps
CPU time 151.58 seconds
Started May 07 12:39:05 PM PDT 24
Finished May 07 12:41:38 PM PDT 24
Peak memory 229120 kb
Host smart-563b2ed8-7df1-4a53-8d0b-f8662179735e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1682563378 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_
corrupt_sig_fatal_chk.1682563378
Directory /workspace/26.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/26.rom_ctrl_kmac_err_chk.1026649518
Short name T171
Test name
Test status
Simulation time 507324188 ps
CPU time 13.28 seconds
Started May 07 12:38:59 PM PDT 24
Finished May 07 12:39:16 PM PDT 24
Peak memory 214548 kb
Host smart-16fff7dd-702d-41f2-8973-70f0394053b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1026649518 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_kmac_err_chk.1026649518
Directory /workspace/26.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/26.rom_ctrl_max_throughput_chk.2018614327
Short name T207
Test name
Test status
Simulation time 670762151 ps
CPU time 9.43 seconds
Started May 07 12:39:12 PM PDT 24
Finished May 07 12:39:23 PM PDT 24
Peak memory 211644 kb
Host smart-e10cd290-5888-4992-8e4c-64ed2fc5ff39
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2018614327 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_max_throughput_chk.2018614327
Directory /workspace/26.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/26.rom_ctrl_smoke.3533418832
Short name T293
Test name
Test status
Simulation time 1558776451 ps
CPU time 19.46 seconds
Started May 07 12:39:05 PM PDT 24
Finished May 07 12:39:26 PM PDT 24
Peak memory 219864 kb
Host smart-d309b206-9efb-4a6a-953e-00c6a42fbb06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3533418832 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_smoke.3533418832
Directory /workspace/26.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/26.rom_ctrl_stress_all.913659650
Short name T351
Test name
Test status
Simulation time 11594618633 ps
CPU time 104.67 seconds
Started May 07 12:38:59 PM PDT 24
Finished May 07 12:40:47 PM PDT 24
Peak memory 219952 kb
Host smart-a49c1102-60f2-4852-9dc1-8268b4e79387
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=913659650 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 26.rom_ctrl_stress_all.913659650
Directory /workspace/26.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/27.rom_ctrl_alert_test.1761211409
Short name T31
Test name
Test status
Simulation time 6465177475 ps
CPU time 13.68 seconds
Started May 07 12:39:11 PM PDT 24
Finished May 07 12:39:26 PM PDT 24
Peak memory 211828 kb
Host smart-94c28a5e-8e70-4f5b-b7eb-76780007290d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1761211409 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_alert_test.1761211409
Directory /workspace/27.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/27.rom_ctrl_corrupt_sig_fatal_chk.1029764893
Short name T246
Test name
Test status
Simulation time 23342257057 ps
CPU time 260.82 seconds
Started May 07 12:39:11 PM PDT 24
Finished May 07 12:43:34 PM PDT 24
Peak memory 237416 kb
Host smart-cb4825ac-8157-4dd3-980c-0d2de9290e8d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1029764893 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_
corrupt_sig_fatal_chk.1029764893
Directory /workspace/27.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/27.rom_ctrl_kmac_err_chk.2833877130
Short name T94
Test name
Test status
Simulation time 16339194154 ps
CPU time 22.26 seconds
Started May 07 12:39:04 PM PDT 24
Finished May 07 12:39:29 PM PDT 24
Peak memory 211908 kb
Host smart-23be558d-ee38-48a6-9a0c-0d891e4ff5b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2833877130 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_kmac_err_chk.2833877130
Directory /workspace/27.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/27.rom_ctrl_max_throughput_chk.105155427
Short name T340
Test name
Test status
Simulation time 6714590275 ps
CPU time 10.05 seconds
Started May 07 12:39:09 PM PDT 24
Finished May 07 12:39:20 PM PDT 24
Peak memory 211796 kb
Host smart-3a304d7b-dfab-45e7-ba1b-f5a8a4b1c67a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=105155427 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_max_throughput_chk.105155427
Directory /workspace/27.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/27.rom_ctrl_smoke.3282064962
Short name T173
Test name
Test status
Simulation time 5140234132 ps
CPU time 27.47 seconds
Started May 07 12:39:01 PM PDT 24
Finished May 07 12:39:32 PM PDT 24
Peak memory 214196 kb
Host smart-2d293e83-7f39-4131-a514-63e151ff44b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3282064962 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_smoke.3282064962
Directory /workspace/27.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/27.rom_ctrl_stress_all.2527028743
Short name T202
Test name
Test status
Simulation time 29113536739 ps
CPU time 66.3 seconds
Started May 07 12:38:59 PM PDT 24
Finished May 07 12:40:09 PM PDT 24
Peak memory 219932 kb
Host smart-0ae5dbc9-07d8-40ff-942e-56254594f643
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2527028743 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 27.rom_ctrl_stress_all.2527028743
Directory /workspace/27.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/28.rom_ctrl_alert_test.2055782020
Short name T128
Test name
Test status
Simulation time 7347175208 ps
CPU time 14.17 seconds
Started May 07 12:39:06 PM PDT 24
Finished May 07 12:39:22 PM PDT 24
Peak memory 211820 kb
Host smart-a9e43436-9fcb-4497-951c-90d172b7894c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2055782020 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_alert_test.2055782020
Directory /workspace/28.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/28.rom_ctrl_corrupt_sig_fatal_chk.2642402842
Short name T268
Test name
Test status
Simulation time 25294615616 ps
CPU time 261.15 seconds
Started May 07 12:39:05 PM PDT 24
Finished May 07 12:43:29 PM PDT 24
Peak memory 219180 kb
Host smart-ca46836c-b669-4d06-89e5-8695f9f963e2
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2642402842 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_
corrupt_sig_fatal_chk.2642402842
Directory /workspace/28.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/28.rom_ctrl_kmac_err_chk.3660541516
Short name T143
Test name
Test status
Simulation time 2489051500 ps
CPU time 10.85 seconds
Started May 07 12:39:04 PM PDT 24
Finished May 07 12:39:17 PM PDT 24
Peak memory 212516 kb
Host smart-b52bd755-c903-4615-9eae-8a7b3b485be8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3660541516 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_kmac_err_chk.3660541516
Directory /workspace/28.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/28.rom_ctrl_max_throughput_chk.2349843875
Short name T343
Test name
Test status
Simulation time 11343772109 ps
CPU time 17.35 seconds
Started May 07 12:38:53 PM PDT 24
Finished May 07 12:39:13 PM PDT 24
Peak memory 211764 kb
Host smart-33cd7ff5-5a01-49f6-aeec-666a47372c93
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2349843875 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_max_throughput_chk.2349843875
Directory /workspace/28.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/28.rom_ctrl_smoke.1621469530
Short name T253
Test name
Test status
Simulation time 4488123778 ps
CPU time 38.12 seconds
Started May 07 12:39:08 PM PDT 24
Finished May 07 12:39:48 PM PDT 24
Peak memory 214144 kb
Host smart-97d0eab2-7230-4b38-a33e-904745ed24b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1621469530 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_smoke.1621469530
Directory /workspace/28.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/28.rom_ctrl_stress_all.1692654516
Short name T204
Test name
Test status
Simulation time 6566891458 ps
CPU time 31.49 seconds
Started May 07 12:38:57 PM PDT 24
Finished May 07 12:39:32 PM PDT 24
Peak memory 214272 kb
Host smart-5c8f47ad-f77e-4bf0-9008-766ed5b53e05
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1692654516 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 28.rom_ctrl_stress_all.1692654516
Directory /workspace/28.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/29.rom_ctrl_alert_test.2474376349
Short name T87
Test name
Test status
Simulation time 85496374 ps
CPU time 4.25 seconds
Started May 07 12:39:03 PM PDT 24
Finished May 07 12:39:10 PM PDT 24
Peak memory 211700 kb
Host smart-2d459346-7800-4f9b-87a9-8f0b43fb6c0e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2474376349 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_alert_test.2474376349
Directory /workspace/29.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/29.rom_ctrl_corrupt_sig_fatal_chk.3843322284
Short name T328
Test name
Test status
Simulation time 222713038808 ps
CPU time 194.27 seconds
Started May 07 12:39:12 PM PDT 24
Finished May 07 12:42:28 PM PDT 24
Peak memory 234244 kb
Host smart-76bbbf04-947a-4578-89ae-682eee64a129
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3843322284 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_
corrupt_sig_fatal_chk.3843322284
Directory /workspace/29.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/29.rom_ctrl_kmac_err_chk.375233173
Short name T185
Test name
Test status
Simulation time 6005172695 ps
CPU time 27.55 seconds
Started May 07 12:39:07 PM PDT 24
Finished May 07 12:39:36 PM PDT 24
Peak memory 212424 kb
Host smart-37827f1d-b97b-4292-860f-5ea2d1260599
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=375233173 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_kmac_err_chk.375233173
Directory /workspace/29.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/29.rom_ctrl_max_throughput_chk.2517121681
Short name T188
Test name
Test status
Simulation time 5007954878 ps
CPU time 12.26 seconds
Started May 07 12:39:07 PM PDT 24
Finished May 07 12:39:21 PM PDT 24
Peak memory 211748 kb
Host smart-7b0539b8-58df-4e65-b383-2765dee57ab9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2517121681 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_max_throughput_chk.2517121681
Directory /workspace/29.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/29.rom_ctrl_smoke.889563285
Short name T17
Test name
Test status
Simulation time 13679188707 ps
CPU time 33.01 seconds
Started May 07 12:39:13 PM PDT 24
Finished May 07 12:39:53 PM PDT 24
Peak memory 214528 kb
Host smart-8f7d1951-9e7a-4bc6-bf08-0fa818b18d15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=889563285 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_smoke.889563285
Directory /workspace/29.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/29.rom_ctrl_stress_all.1233155962
Short name T201
Test name
Test status
Simulation time 1409091232 ps
CPU time 18.75 seconds
Started May 07 12:39:02 PM PDT 24
Finished May 07 12:39:24 PM PDT 24
Peak memory 213720 kb
Host smart-7a123631-46a0-4848-96f2-04e5668b23e0
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1233155962 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 29.rom_ctrl_stress_all.1233155962
Directory /workspace/29.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/3.rom_ctrl_alert_test.1041684047
Short name T160
Test name
Test status
Simulation time 840449621 ps
CPU time 9.56 seconds
Started May 07 12:38:38 PM PDT 24
Finished May 07 12:38:49 PM PDT 24
Peak memory 211660 kb
Host smart-362c0e85-6be7-4bcc-b936-64d33c9344ba
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1041684047 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_alert_test.1041684047
Directory /workspace/3.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/3.rom_ctrl_corrupt_sig_fatal_chk.332246976
Short name T335
Test name
Test status
Simulation time 1590312096 ps
CPU time 55.05 seconds
Started May 07 12:38:56 PM PDT 24
Finished May 07 12:39:54 PM PDT 24
Peak memory 228700 kb
Host smart-6e84c73d-11b5-4650-91e7-323a11f78c03
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=332246976 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_co
rrupt_sig_fatal_chk.332246976
Directory /workspace/3.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/3.rom_ctrl_kmac_err_chk.2880419209
Short name T359
Test name
Test status
Simulation time 2992703571 ps
CPU time 26.33 seconds
Started May 07 12:38:52 PM PDT 24
Finished May 07 12:39:20 PM PDT 24
Peak memory 212420 kb
Host smart-e8d1e5fe-55df-48b3-8f01-e5c1dde364b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2880419209 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_kmac_err_chk.2880419209
Directory /workspace/3.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/3.rom_ctrl_max_throughput_chk.884309476
Short name T104
Test name
Test status
Simulation time 8367131418 ps
CPU time 16.8 seconds
Started May 07 12:39:00 PM PDT 24
Finished May 07 12:39:20 PM PDT 24
Peak memory 211816 kb
Host smart-afe1d484-4932-455d-b564-977827226194
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=884309476 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_max_throughput_chk.884309476
Directory /workspace/3.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/3.rom_ctrl_smoke.4182313667
Short name T275
Test name
Test status
Simulation time 185108767 ps
CPU time 10.12 seconds
Started May 07 12:38:48 PM PDT 24
Finished May 07 12:39:01 PM PDT 24
Peak memory 212720 kb
Host smart-986078fe-f351-4ce0-9885-b9935cb38dc9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4182313667 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_smoke.4182313667
Directory /workspace/3.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/3.rom_ctrl_stress_all.1001440099
Short name T73
Test name
Test status
Simulation time 3032520159 ps
CPU time 36.17 seconds
Started May 07 12:38:45 PM PDT 24
Finished May 07 12:39:23 PM PDT 24
Peak memory 214624 kb
Host smart-8187d71b-3162-41c6-a88b-d4a9011ccf0d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1001440099 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 3.rom_ctrl_stress_all.1001440099
Directory /workspace/3.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/30.rom_ctrl_alert_test.2251044017
Short name T290
Test name
Test status
Simulation time 1027894829 ps
CPU time 8.93 seconds
Started May 07 12:39:01 PM PDT 24
Finished May 07 12:39:14 PM PDT 24
Peak memory 211704 kb
Host smart-c48647e1-555f-413a-b37e-0983fea27287
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2251044017 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_alert_test.2251044017
Directory /workspace/30.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/30.rom_ctrl_corrupt_sig_fatal_chk.1614620253
Short name T257
Test name
Test status
Simulation time 16130879845 ps
CPU time 218.86 seconds
Started May 07 12:39:01 PM PDT 24
Finished May 07 12:42:43 PM PDT 24
Peak memory 229592 kb
Host smart-0cd8aa28-1179-4892-8785-d14a0a95a8aa
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1614620253 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_
corrupt_sig_fatal_chk.1614620253
Directory /workspace/30.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/30.rom_ctrl_kmac_err_chk.4254697585
Short name T166
Test name
Test status
Simulation time 176075723 ps
CPU time 9.28 seconds
Started May 07 12:39:08 PM PDT 24
Finished May 07 12:39:19 PM PDT 24
Peak memory 212260 kb
Host smart-36bd8248-7c65-4f23-86bb-d5d36198a0c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4254697585 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_kmac_err_chk.4254697585
Directory /workspace/30.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/30.rom_ctrl_max_throughput_chk.503048295
Short name T192
Test name
Test status
Simulation time 948368066 ps
CPU time 11.83 seconds
Started May 07 12:38:55 PM PDT 24
Finished May 07 12:39:09 PM PDT 24
Peak memory 211832 kb
Host smart-286ef80a-fc12-49e8-a19c-43b83840e6b8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=503048295 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_max_throughput_chk.503048295
Directory /workspace/30.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/30.rom_ctrl_smoke.1999713106
Short name T7
Test name
Test status
Simulation time 710469760 ps
CPU time 9.57 seconds
Started May 07 12:38:59 PM PDT 24
Finished May 07 12:39:13 PM PDT 24
Peak memory 219904 kb
Host smart-c54c1536-ceed-408a-8e03-8aec1debf6ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1999713106 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_smoke.1999713106
Directory /workspace/30.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/30.rom_ctrl_stress_all.2056300863
Short name T259
Test name
Test status
Simulation time 475385368 ps
CPU time 26.13 seconds
Started May 07 12:39:04 PM PDT 24
Finished May 07 12:39:32 PM PDT 24
Peak memory 214092 kb
Host smart-f4a22594-f195-42f7-a4d2-87b44ccbd495
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2056300863 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 30.rom_ctrl_stress_all.2056300863
Directory /workspace/30.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/30.rom_ctrl_stress_all_with_rand_reset.2830247294
Short name T47
Test name
Test status
Simulation time 43090738152 ps
CPU time 4993.75 seconds
Started May 07 12:38:58 PM PDT 24
Finished May 07 02:02:16 PM PDT 24
Peak memory 236464 kb
Host smart-616d2b56-24f4-423f-a427-2c93786827e6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2830247294 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_stress_all_with_rand_reset.2830247294
Directory /workspace/30.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.rom_ctrl_alert_test.2946013942
Short name T339
Test name
Test status
Simulation time 863709931 ps
CPU time 9.67 seconds
Started May 07 12:39:16 PM PDT 24
Finished May 07 12:39:28 PM PDT 24
Peak memory 211696 kb
Host smart-28eb605e-154a-4d66-9bcb-59debf4c924e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2946013942 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_alert_test.2946013942
Directory /workspace/31.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/31.rom_ctrl_corrupt_sig_fatal_chk.3595172500
Short name T25
Test name
Test status
Simulation time 45023721703 ps
CPU time 424.04 seconds
Started May 07 12:38:58 PM PDT 24
Finished May 07 12:46:06 PM PDT 24
Peak memory 225444 kb
Host smart-513ce78f-0015-46fa-a4c8-2c1f442f8c6c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3595172500 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_
corrupt_sig_fatal_chk.3595172500
Directory /workspace/31.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/31.rom_ctrl_kmac_err_chk.275057500
Short name T300
Test name
Test status
Simulation time 1277763565 ps
CPU time 9.38 seconds
Started May 07 12:39:04 PM PDT 24
Finished May 07 12:39:16 PM PDT 24
Peak memory 212484 kb
Host smart-89639565-cde6-4b6c-8bbf-5f6467e45bb4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=275057500 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_kmac_err_chk.275057500
Directory /workspace/31.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/31.rom_ctrl_max_throughput_chk.3216298746
Short name T331
Test name
Test status
Simulation time 7565237593 ps
CPU time 16.27 seconds
Started May 07 12:39:11 PM PDT 24
Finished May 07 12:39:29 PM PDT 24
Peak memory 211760 kb
Host smart-a78c01d4-a195-4896-9441-27bf6c2be9c5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3216298746 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_max_throughput_chk.3216298746
Directory /workspace/31.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/31.rom_ctrl_smoke.3991095564
Short name T71
Test name
Test status
Simulation time 189234968 ps
CPU time 9.73 seconds
Started May 07 12:39:08 PM PDT 24
Finished May 07 12:39:20 PM PDT 24
Peak memory 213296 kb
Host smart-ba5a1cfe-fe11-4cb3-9499-413e02052182
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3991095564 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_smoke.3991095564
Directory /workspace/31.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/31.rom_ctrl_stress_all.79078626
Short name T107
Test name
Test status
Simulation time 1358304740 ps
CPU time 15.02 seconds
Started May 07 12:39:12 PM PDT 24
Finished May 07 12:39:29 PM PDT 24
Peak memory 212720 kb
Host smart-61397c04-78ba-4baf-982d-aa05369f2650
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=79078626 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +U
VM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n
ame 31.rom_ctrl_stress_all.79078626
Directory /workspace/31.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/32.rom_ctrl_alert_test.3961073334
Short name T326
Test name
Test status
Simulation time 1749642240 ps
CPU time 14.79 seconds
Started May 07 12:39:11 PM PDT 24
Finished May 07 12:39:27 PM PDT 24
Peak memory 211712 kb
Host smart-bc7db26b-207e-463b-87cf-4a0f63af760a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3961073334 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_alert_test.3961073334
Directory /workspace/32.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/32.rom_ctrl_corrupt_sig_fatal_chk.1566791820
Short name T27
Test name
Test status
Simulation time 1422681777 ps
CPU time 88.33 seconds
Started May 07 12:39:00 PM PDT 24
Finished May 07 12:40:32 PM PDT 24
Peak memory 221232 kb
Host smart-c1379b62-4525-46ae-be6d-10bcbeeaa9f4
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1566791820 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_
corrupt_sig_fatal_chk.1566791820
Directory /workspace/32.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/32.rom_ctrl_kmac_err_chk.150020182
Short name T348
Test name
Test status
Simulation time 497795572 ps
CPU time 13.14 seconds
Started May 07 12:39:07 PM PDT 24
Finished May 07 12:39:22 PM PDT 24
Peak memory 212264 kb
Host smart-c7cbf588-1e36-46c7-bade-5f31a476d1f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=150020182 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_kmac_err_chk.150020182
Directory /workspace/32.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/32.rom_ctrl_max_throughput_chk.538025889
Short name T148
Test name
Test status
Simulation time 226813951 ps
CPU time 6.13 seconds
Started May 07 12:38:59 PM PDT 24
Finished May 07 12:39:09 PM PDT 24
Peak memory 211656 kb
Host smart-713aa19e-b3ae-438d-969d-70816c69ed17
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=538025889 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_max_throughput_chk.538025889
Directory /workspace/32.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/32.rom_ctrl_smoke.1614782849
Short name T244
Test name
Test status
Simulation time 903838761 ps
CPU time 10.46 seconds
Started May 07 12:38:59 PM PDT 24
Finished May 07 12:39:13 PM PDT 24
Peak memory 214132 kb
Host smart-503a34ce-da6a-45e1-bbf2-c5b9fc8833d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1614782849 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_smoke.1614782849
Directory /workspace/32.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/32.rom_ctrl_stress_all.2412406627
Short name T38
Test name
Test status
Simulation time 20223254188 ps
CPU time 44.46 seconds
Started May 07 12:39:13 PM PDT 24
Finished May 07 12:39:59 PM PDT 24
Peak memory 217428 kb
Host smart-099cc8e3-38e0-464e-918b-96fb3ddddd8a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2412406627 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 32.rom_ctrl_stress_all.2412406627
Directory /workspace/32.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/33.rom_ctrl_alert_test.4006753348
Short name T56
Test name
Test status
Simulation time 498151277 ps
CPU time 7.32 seconds
Started May 07 12:39:05 PM PDT 24
Finished May 07 12:39:14 PM PDT 24
Peak memory 211696 kb
Host smart-81b09720-260c-4399-981a-fe428c4fcf6f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4006753348 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_alert_test.4006753348
Directory /workspace/33.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/33.rom_ctrl_corrupt_sig_fatal_chk.399147676
Short name T175
Test name
Test status
Simulation time 1413297965 ps
CPU time 81.12 seconds
Started May 07 12:39:00 PM PDT 24
Finished May 07 12:40:25 PM PDT 24
Peak memory 228440 kb
Host smart-715701ea-88b6-4d5c-bf7e-45ba6774f430
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=399147676 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_c
orrupt_sig_fatal_chk.399147676
Directory /workspace/33.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/33.rom_ctrl_kmac_err_chk.1189215488
Short name T344
Test name
Test status
Simulation time 5788998147 ps
CPU time 27.58 seconds
Started May 07 12:39:05 PM PDT 24
Finished May 07 12:39:35 PM PDT 24
Peak memory 212816 kb
Host smart-c3ee9097-3117-4223-84c2-30822fe83e97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1189215488 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_kmac_err_chk.1189215488
Directory /workspace/33.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/33.rom_ctrl_max_throughput_chk.690749552
Short name T105
Test name
Test status
Simulation time 6446065934 ps
CPU time 15.3 seconds
Started May 07 12:39:16 PM PDT 24
Finished May 07 12:39:34 PM PDT 24
Peak memory 211792 kb
Host smart-595b33a9-644d-47b3-961c-35ac033b2df1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=690749552 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_max_throughput_chk.690749552
Directory /workspace/33.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/33.rom_ctrl_smoke.3125449026
Short name T146
Test name
Test status
Simulation time 3184847358 ps
CPU time 19.35 seconds
Started May 07 12:39:15 PM PDT 24
Finished May 07 12:39:36 PM PDT 24
Peak memory 213668 kb
Host smart-0c7e42f8-b9db-4a9f-a8de-15d1b1013016
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3125449026 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_smoke.3125449026
Directory /workspace/33.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/33.rom_ctrl_stress_all.1125583262
Short name T156
Test name
Test status
Simulation time 1346535226 ps
CPU time 12.09 seconds
Started May 07 12:39:10 PM PDT 24
Finished May 07 12:39:24 PM PDT 24
Peak memory 219844 kb
Host smart-c3c437cd-c569-4afa-bc45-370552b11aa8
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1125583262 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 33.rom_ctrl_stress_all.1125583262
Directory /workspace/33.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/33.rom_ctrl_stress_all_with_rand_reset.847250675
Short name T346
Test name
Test status
Simulation time 46948711302 ps
CPU time 7255.43 seconds
Started May 07 12:39:10 PM PDT 24
Finished May 07 02:40:08 PM PDT 24
Peak memory 236448 kb
Host smart-dbb64251-7d5b-4338-96fe-870f11d6f8a7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=847250675 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_stress_all_with_rand_reset.847250675
Directory /workspace/33.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.rom_ctrl_alert_test.146835356
Short name T282
Test name
Test status
Simulation time 2136606898 ps
CPU time 16.05 seconds
Started May 07 12:39:11 PM PDT 24
Finished May 07 12:39:29 PM PDT 24
Peak memory 211628 kb
Host smart-d627a017-49e9-4b43-b6d5-4b5ca7a53fa4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=146835356 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_alert_test.146835356
Directory /workspace/34.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/34.rom_ctrl_corrupt_sig_fatal_chk.2091633620
Short name T301
Test name
Test status
Simulation time 67670405133 ps
CPU time 181.59 seconds
Started May 07 12:39:04 PM PDT 24
Finished May 07 12:42:08 PM PDT 24
Peak memory 238312 kb
Host smart-ab252d74-4b49-4460-8191-a00afdaca7a6
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2091633620 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_
corrupt_sig_fatal_chk.2091633620
Directory /workspace/34.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/34.rom_ctrl_kmac_err_chk.554348941
Short name T220
Test name
Test status
Simulation time 53722622091 ps
CPU time 24.95 seconds
Started May 07 12:39:06 PM PDT 24
Finished May 07 12:39:33 PM PDT 24
Peak memory 212824 kb
Host smart-5c43d3e1-d591-4c7a-8f2e-9270cf3bca66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=554348941 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_kmac_err_chk.554348941
Directory /workspace/34.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/34.rom_ctrl_max_throughput_chk.2904528685
Short name T37
Test name
Test status
Simulation time 5708818939 ps
CPU time 13.65 seconds
Started May 07 12:39:10 PM PDT 24
Finished May 07 12:39:26 PM PDT 24
Peak memory 211764 kb
Host smart-a4cd9816-21e5-42bc-a2ba-f5db7e22fe67
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2904528685 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_max_throughput_chk.2904528685
Directory /workspace/34.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/34.rom_ctrl_smoke.1457467031
Short name T337
Test name
Test status
Simulation time 4955301473 ps
CPU time 38.73 seconds
Started May 07 12:39:05 PM PDT 24
Finished May 07 12:39:46 PM PDT 24
Peak memory 213272 kb
Host smart-ef133de2-647c-4322-ae08-f3954ddb5256
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1457467031 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_smoke.1457467031
Directory /workspace/34.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/34.rom_ctrl_stress_all.3398716590
Short name T284
Test name
Test status
Simulation time 6354335544 ps
CPU time 64.4 seconds
Started May 07 12:39:00 PM PDT 24
Finished May 07 12:40:08 PM PDT 24
Peak memory 219972 kb
Host smart-0f9e60e6-40de-4784-8657-0e154059feef
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3398716590 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 34.rom_ctrl_stress_all.3398716590
Directory /workspace/34.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/35.rom_ctrl_alert_test.2219084788
Short name T194
Test name
Test status
Simulation time 1028293870 ps
CPU time 10.47 seconds
Started May 07 12:39:09 PM PDT 24
Finished May 07 12:39:21 PM PDT 24
Peak memory 211708 kb
Host smart-e9aee167-0a65-4b0c-87b1-c17997cfe546
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2219084788 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_alert_test.2219084788
Directory /workspace/35.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/35.rom_ctrl_corrupt_sig_fatal_chk.769710882
Short name T315
Test name
Test status
Simulation time 1499377994 ps
CPU time 86.85 seconds
Started May 07 12:39:18 PM PDT 24
Finished May 07 12:40:47 PM PDT 24
Peak memory 237188 kb
Host smart-a7cd2dd7-4b5b-4feb-9b36-8f05073b5479
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=769710882 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_c
orrupt_sig_fatal_chk.769710882
Directory /workspace/35.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/35.rom_ctrl_kmac_err_chk.456631270
Short name T267
Test name
Test status
Simulation time 597135469 ps
CPU time 13.34 seconds
Started May 07 12:38:58 PM PDT 24
Finished May 07 12:39:15 PM PDT 24
Peak memory 212548 kb
Host smart-6cce64c5-0db1-4119-9d96-3b535e7ab0e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=456631270 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_kmac_err_chk.456631270
Directory /workspace/35.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/35.rom_ctrl_max_throughput_chk.3414434361
Short name T225
Test name
Test status
Simulation time 1076595103 ps
CPU time 7.27 seconds
Started May 07 12:39:06 PM PDT 24
Finished May 07 12:39:15 PM PDT 24
Peak memory 211652 kb
Host smart-ce88f179-67aa-4d22-89fa-2ce431e6e96e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3414434361 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_max_throughput_chk.3414434361
Directory /workspace/35.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/35.rom_ctrl_smoke.3275587241
Short name T279
Test name
Test status
Simulation time 3273203845 ps
CPU time 32.77 seconds
Started May 07 12:39:02 PM PDT 24
Finished May 07 12:39:38 PM PDT 24
Peak memory 213488 kb
Host smart-aed4b582-0f65-49a0-b98a-34634bb6668a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3275587241 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_smoke.3275587241
Directory /workspace/35.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/35.rom_ctrl_stress_all.3585424544
Short name T144
Test name
Test status
Simulation time 2046304767 ps
CPU time 36.29 seconds
Started May 07 12:38:57 PM PDT 24
Finished May 07 12:39:37 PM PDT 24
Peak memory 219848 kb
Host smart-b4ad6b1c-32e1-4802-8ca2-3adee9af5555
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3585424544 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 35.rom_ctrl_stress_all.3585424544
Directory /workspace/35.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/36.rom_ctrl_alert_test.3470903226
Short name T163
Test name
Test status
Simulation time 2376315905 ps
CPU time 7.27 seconds
Started May 07 12:39:03 PM PDT 24
Finished May 07 12:39:13 PM PDT 24
Peak memory 211828 kb
Host smart-c303dbb7-8164-4f2e-9f18-6ea2c7a84894
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3470903226 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_alert_test.3470903226
Directory /workspace/36.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/36.rom_ctrl_corrupt_sig_fatal_chk.3628750815
Short name T223
Test name
Test status
Simulation time 198830249404 ps
CPU time 337.03 seconds
Started May 07 12:39:42 PM PDT 24
Finished May 07 12:45:21 PM PDT 24
Peak memory 235420 kb
Host smart-8ae56a45-5840-45c3-aa01-1f5aadd96b59
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3628750815 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_
corrupt_sig_fatal_chk.3628750815
Directory /workspace/36.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/36.rom_ctrl_kmac_err_chk.3559586012
Short name T228
Test name
Test status
Simulation time 14115307463 ps
CPU time 30.38 seconds
Started May 07 12:39:08 PM PDT 24
Finished May 07 12:39:40 PM PDT 24
Peak memory 212620 kb
Host smart-e049c9b0-554f-405e-8d46-5fffc251bdb8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3559586012 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_kmac_err_chk.3559586012
Directory /workspace/36.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/36.rom_ctrl_smoke.1336615465
Short name T311
Test name
Test status
Simulation time 1709197985 ps
CPU time 13.11 seconds
Started May 07 12:39:06 PM PDT 24
Finished May 07 12:39:21 PM PDT 24
Peak memory 213960 kb
Host smart-b98f0abf-3870-4942-8c90-c89224b7fb62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1336615465 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_smoke.1336615465
Directory /workspace/36.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/36.rom_ctrl_stress_all.3565690352
Short name T241
Test name
Test status
Simulation time 5478154146 ps
CPU time 16.17 seconds
Started May 07 12:39:10 PM PDT 24
Finished May 07 12:39:27 PM PDT 24
Peak memory 211616 kb
Host smart-cb07151a-964d-411e-94b7-b91ca4bbc206
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3565690352 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 36.rom_ctrl_stress_all.3565690352
Directory /workspace/36.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/37.rom_ctrl_alert_test.22070568
Short name T306
Test name
Test status
Simulation time 347269292 ps
CPU time 4.31 seconds
Started May 07 12:39:12 PM PDT 24
Finished May 07 12:39:19 PM PDT 24
Peak memory 211708 kb
Host smart-636ae08c-f656-421b-bcbf-5550d64c1893
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22070568 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_alert_test.22070568
Directory /workspace/37.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/37.rom_ctrl_corrupt_sig_fatal_chk.2605660167
Short name T252
Test name
Test status
Simulation time 2471468481 ps
CPU time 68.6 seconds
Started May 07 12:39:05 PM PDT 24
Finished May 07 12:40:16 PM PDT 24
Peak memory 219208 kb
Host smart-ec708338-121e-43f1-8ed8-11a009d8d4b9
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2605660167 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_
corrupt_sig_fatal_chk.2605660167
Directory /workspace/37.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/37.rom_ctrl_max_throughput_chk.1255661657
Short name T187
Test name
Test status
Simulation time 7851891895 ps
CPU time 16.48 seconds
Started May 07 12:39:05 PM PDT 24
Finished May 07 12:39:24 PM PDT 24
Peak memory 211776 kb
Host smart-7eb6bcb4-3b27-425f-a352-f24518d560ab
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1255661657 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_max_throughput_chk.1255661657
Directory /workspace/37.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/37.rom_ctrl_smoke.3241518962
Short name T324
Test name
Test status
Simulation time 46645816716 ps
CPU time 26.85 seconds
Started May 07 12:39:03 PM PDT 24
Finished May 07 12:39:32 PM PDT 24
Peak memory 214900 kb
Host smart-7a11a3c3-5e1c-40a4-93af-46228461b205
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3241518962 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_smoke.3241518962
Directory /workspace/37.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/37.rom_ctrl_stress_all.2228364242
Short name T273
Test name
Test status
Simulation time 13883061706 ps
CPU time 46.21 seconds
Started May 07 12:39:18 PM PDT 24
Finished May 07 12:40:07 PM PDT 24
Peak memory 219272 kb
Host smart-6f6584a3-fab5-47a2-84e9-09925373d2a4
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2228364242 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 37.rom_ctrl_stress_all.2228364242
Directory /workspace/37.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/38.rom_ctrl_alert_test.3264442298
Short name T33
Test name
Test status
Simulation time 423031554 ps
CPU time 5.62 seconds
Started May 07 12:39:16 PM PDT 24
Finished May 07 12:39:24 PM PDT 24
Peak memory 211700 kb
Host smart-7c6555c6-493f-4d7b-bc3b-972218a1f349
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3264442298 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_alert_test.3264442298
Directory /workspace/38.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/38.rom_ctrl_corrupt_sig_fatal_chk.4100238423
Short name T325
Test name
Test status
Simulation time 75744178880 ps
CPU time 352.02 seconds
Started May 07 12:39:12 PM PDT 24
Finished May 07 12:45:06 PM PDT 24
Peak memory 228848 kb
Host smart-1bc34916-8219-4788-bb73-8bbc1613cedc
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4100238423 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_
corrupt_sig_fatal_chk.4100238423
Directory /workspace/38.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/38.rom_ctrl_kmac_err_chk.973732958
Short name T231
Test name
Test status
Simulation time 3432336842 ps
CPU time 14.82 seconds
Started May 07 12:39:17 PM PDT 24
Finished May 07 12:39:34 PM PDT 24
Peak memory 212364 kb
Host smart-29bee242-84d1-431b-84f8-240980910551
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=973732958 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_kmac_err_chk.973732958
Directory /workspace/38.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/38.rom_ctrl_max_throughput_chk.22464172
Short name T169
Test name
Test status
Simulation time 196199163 ps
CPU time 5.82 seconds
Started May 07 12:39:12 PM PDT 24
Finished May 07 12:39:19 PM PDT 24
Peak memory 211660 kb
Host smart-8250bbaa-127c-46cd-b649-84aecf901327
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=22464172 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_max_throughput_chk.22464172
Directory /workspace/38.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/38.rom_ctrl_smoke.3682218269
Short name T302
Test name
Test status
Simulation time 7037735372 ps
CPU time 30.92 seconds
Started May 07 12:39:05 PM PDT 24
Finished May 07 12:39:38 PM PDT 24
Peak memory 214200 kb
Host smart-f36d59df-20a5-43be-86fb-ea5887797051
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3682218269 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_smoke.3682218269
Directory /workspace/38.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/38.rom_ctrl_stress_all.3062232860
Short name T295
Test name
Test status
Simulation time 3981754743 ps
CPU time 30.73 seconds
Started May 07 12:39:17 PM PDT 24
Finished May 07 12:39:50 PM PDT 24
Peak memory 214464 kb
Host smart-ea3fda58-0865-4feb-8ff3-f8cba8abcc04
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3062232860 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 38.rom_ctrl_stress_all.3062232860
Directory /workspace/38.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/38.rom_ctrl_stress_all_with_rand_reset.543836458
Short name T289
Test name
Test status
Simulation time 53402295035 ps
CPU time 2012.44 seconds
Started May 07 12:39:17 PM PDT 24
Finished May 07 01:12:52 PM PDT 24
Peak memory 236456 kb
Host smart-165ea259-98be-4211-8654-e9e4d7084d1c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=543836458 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_stress_all_with_rand_reset.543836458
Directory /workspace/38.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.rom_ctrl_alert_test.2860154892
Short name T304
Test name
Test status
Simulation time 3828081033 ps
CPU time 15.76 seconds
Started May 07 12:39:01 PM PDT 24
Finished May 07 12:39:20 PM PDT 24
Peak memory 211828 kb
Host smart-f05ea2e9-e657-4145-8b33-0436d759732c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2860154892 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_alert_test.2860154892
Directory /workspace/39.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/39.rom_ctrl_corrupt_sig_fatal_chk.216095714
Short name T264
Test name
Test status
Simulation time 12799289805 ps
CPU time 147.29 seconds
Started May 07 12:39:06 PM PDT 24
Finished May 07 12:41:35 PM PDT 24
Peak memory 237688 kb
Host smart-ddddd0fc-0d35-49ac-889e-157b0e658b55
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=216095714 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_c
orrupt_sig_fatal_chk.216095714
Directory /workspace/39.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/39.rom_ctrl_kmac_err_chk.1756456123
Short name T230
Test name
Test status
Simulation time 1107937155 ps
CPU time 9.52 seconds
Started May 07 12:39:09 PM PDT 24
Finished May 07 12:39:20 PM PDT 24
Peak memory 212276 kb
Host smart-8edbac87-6ce4-41bc-88d2-ed2c9334ce3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1756456123 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_kmac_err_chk.1756456123
Directory /workspace/39.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/39.rom_ctrl_max_throughput_chk.1803100122
Short name T336
Test name
Test status
Simulation time 15048103715 ps
CPU time 12.48 seconds
Started May 07 12:39:12 PM PDT 24
Finished May 07 12:39:26 PM PDT 24
Peak memory 211716 kb
Host smart-56c81852-7e2e-4dff-b664-afe2c39195a8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1803100122 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_max_throughput_chk.1803100122
Directory /workspace/39.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/39.rom_ctrl_smoke.1715461029
Short name T199
Test name
Test status
Simulation time 3971988870 ps
CPU time 16.47 seconds
Started May 07 12:39:06 PM PDT 24
Finished May 07 12:39:25 PM PDT 24
Peak memory 214148 kb
Host smart-2d0ed9d3-157c-4982-b770-2addd80b2c61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1715461029 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_smoke.1715461029
Directory /workspace/39.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/39.rom_ctrl_stress_all.440377001
Short name T157
Test name
Test status
Simulation time 617304849 ps
CPU time 16.08 seconds
Started May 07 12:39:10 PM PDT 24
Finished May 07 12:39:28 PM PDT 24
Peak memory 213688 kb
Host smart-1dc75aeb-40ac-40fc-b8b3-aa0ecc583bec
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=440377001 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 39.rom_ctrl_stress_all.440377001
Directory /workspace/39.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/4.rom_ctrl_alert_test.603010213
Short name T132
Test name
Test status
Simulation time 171689861 ps
CPU time 4.22 seconds
Started May 07 12:38:55 PM PDT 24
Finished May 07 12:39:01 PM PDT 24
Peak memory 211708 kb
Host smart-e76094f8-c663-406c-8dbe-1333ac14b4dd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=603010213 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_alert_test.603010213
Directory /workspace/4.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/4.rom_ctrl_corrupt_sig_fatal_chk.3949079175
Short name T232
Test name
Test status
Simulation time 38644632247 ps
CPU time 212.33 seconds
Started May 07 12:38:42 PM PDT 24
Finished May 07 12:42:17 PM PDT 24
Peak memory 239964 kb
Host smart-4dc9eec1-05c9-44d6-a2f9-973c04cf0381
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3949079175 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_c
orrupt_sig_fatal_chk.3949079175
Directory /workspace/4.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/4.rom_ctrl_kmac_err_chk.3291290322
Short name T15
Test name
Test status
Simulation time 792577032 ps
CPU time 9.43 seconds
Started May 07 12:39:02 PM PDT 24
Finished May 07 12:39:14 PM PDT 24
Peak memory 212836 kb
Host smart-593f8bc8-4689-48f0-9d18-bd739c04eac8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3291290322 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_kmac_err_chk.3291290322
Directory /workspace/4.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/4.rom_ctrl_max_throughput_chk.4055039512
Short name T318
Test name
Test status
Simulation time 404011379 ps
CPU time 5.41 seconds
Started May 07 12:39:00 PM PDT 24
Finished May 07 12:39:09 PM PDT 24
Peak memory 211692 kb
Host smart-06b69dea-0aa9-44e0-9287-5ce27fe15719
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4055039512 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_max_throughput_chk.4055039512
Directory /workspace/4.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/4.rom_ctrl_sec_cm.745458594
Short name T35
Test name
Test status
Simulation time 543201838 ps
CPU time 52.17 seconds
Started May 07 12:38:46 PM PDT 24
Finished May 07 12:39:39 PM PDT 24
Peak memory 237160 kb
Host smart-a650f12e-ea46-4378-8f82-26fcec15e9e3
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=745458594 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_sec_cm.745458594
Directory /workspace/4.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/4.rom_ctrl_smoke.3325356787
Short name T357
Test name
Test status
Simulation time 210098843 ps
CPU time 10.08 seconds
Started May 07 12:38:49 PM PDT 24
Finished May 07 12:39:01 PM PDT 24
Peak memory 213844 kb
Host smart-5e3cfeca-2444-4353-8466-82bf57ab1beb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3325356787 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_smoke.3325356787
Directory /workspace/4.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/4.rom_ctrl_stress_all.2932709017
Short name T75
Test name
Test status
Simulation time 508703109 ps
CPU time 7.92 seconds
Started May 07 12:38:51 PM PDT 24
Finished May 07 12:39:00 PM PDT 24
Peak memory 211692 kb
Host smart-eb8fb22a-357c-412b-bc65-f66502d601f4
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2932709017 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 4.rom_ctrl_stress_all.2932709017
Directory /workspace/4.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/40.rom_ctrl_alert_test.2727782423
Short name T234
Test name
Test status
Simulation time 6364937348 ps
CPU time 16.78 seconds
Started May 07 12:39:34 PM PDT 24
Finished May 07 12:39:52 PM PDT 24
Peak memory 211820 kb
Host smart-40492d5c-4c36-4ff9-8817-6eef5dd1e676
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2727782423 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_alert_test.2727782423
Directory /workspace/40.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/40.rom_ctrl_corrupt_sig_fatal_chk.3457259683
Short name T263
Test name
Test status
Simulation time 44162456375 ps
CPU time 415.34 seconds
Started May 07 12:39:13 PM PDT 24
Finished May 07 12:46:11 PM PDT 24
Peak memory 237356 kb
Host smart-d4999168-6357-4ce4-99fc-c43daaf356be
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3457259683 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_
corrupt_sig_fatal_chk.3457259683
Directory /workspace/40.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/40.rom_ctrl_max_throughput_chk.911491982
Short name T127
Test name
Test status
Simulation time 165480689 ps
CPU time 5.59 seconds
Started May 07 12:39:11 PM PDT 24
Finished May 07 12:39:18 PM PDT 24
Peak memory 211628 kb
Host smart-1cc1484c-671c-4320-8b77-f84c4b13a80a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=911491982 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_max_throughput_chk.911491982
Directory /workspace/40.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/40.rom_ctrl_smoke.3035881085
Short name T142
Test name
Test status
Simulation time 942973305 ps
CPU time 10.11 seconds
Started May 07 12:39:13 PM PDT 24
Finished May 07 12:39:25 PM PDT 24
Peak memory 219888 kb
Host smart-70315b91-ce1c-4dd9-bacd-049fc1844ce2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3035881085 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_smoke.3035881085
Directory /workspace/40.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/40.rom_ctrl_stress_all.1983965777
Short name T13
Test name
Test status
Simulation time 7239442923 ps
CPU time 29.81 seconds
Started May 07 12:39:16 PM PDT 24
Finished May 07 12:39:48 PM PDT 24
Peak memory 219940 kb
Host smart-fe2442dd-28e1-42d8-b2ba-ffe4996a4298
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1983965777 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 40.rom_ctrl_stress_all.1983965777
Directory /workspace/40.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/41.rom_ctrl_alert_test.1649465553
Short name T55
Test name
Test status
Simulation time 585912984 ps
CPU time 7.89 seconds
Started May 07 12:39:14 PM PDT 24
Finished May 07 12:39:24 PM PDT 24
Peak memory 211700 kb
Host smart-765a9dc1-bdfc-4225-a473-b699112264c6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1649465553 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_alert_test.1649465553
Directory /workspace/41.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/41.rom_ctrl_corrupt_sig_fatal_chk.1182881544
Short name T211
Test name
Test status
Simulation time 81432611874 ps
CPU time 247.2 seconds
Started May 07 12:39:24 PM PDT 24
Finished May 07 12:43:32 PM PDT 24
Peak memory 233844 kb
Host smart-382d1f50-dd54-4cba-bc76-8c4b924a38b7
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1182881544 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_
corrupt_sig_fatal_chk.1182881544
Directory /workspace/41.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/41.rom_ctrl_kmac_err_chk.4241951058
Short name T283
Test name
Test status
Simulation time 2956718577 ps
CPU time 25.83 seconds
Started May 07 12:39:29 PM PDT 24
Finished May 07 12:39:56 PM PDT 24
Peak memory 212508 kb
Host smart-c6026bd1-38fc-4ba9-a51e-29141e0ed9cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4241951058 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_kmac_err_chk.4241951058
Directory /workspace/41.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/41.rom_ctrl_max_throughput_chk.3145110253
Short name T322
Test name
Test status
Simulation time 2140600575 ps
CPU time 11.72 seconds
Started May 07 12:39:18 PM PDT 24
Finished May 07 12:39:32 PM PDT 24
Peak memory 211664 kb
Host smart-560be27c-3ebd-4ab8-a187-ef43ad793a4b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3145110253 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_max_throughput_chk.3145110253
Directory /workspace/41.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/41.rom_ctrl_smoke.2173763429
Short name T354
Test name
Test status
Simulation time 1695344129 ps
CPU time 19.73 seconds
Started May 07 12:39:12 PM PDT 24
Finished May 07 12:39:33 PM PDT 24
Peak memory 219908 kb
Host smart-20009cc5-5806-489d-b35b-ae0b5e556eac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2173763429 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_smoke.2173763429
Directory /workspace/41.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/41.rom_ctrl_stress_all.1001289714
Short name T248
Test name
Test status
Simulation time 2340354638 ps
CPU time 26.64 seconds
Started May 07 12:39:15 PM PDT 24
Finished May 07 12:39:44 PM PDT 24
Peak memory 213760 kb
Host smart-7262095e-656d-4cf4-8a22-6ce4df6a6d9b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1001289714 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 41.rom_ctrl_stress_all.1001289714
Directory /workspace/41.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/42.rom_ctrl_alert_test.42710355
Short name T280
Test name
Test status
Simulation time 5271369928 ps
CPU time 10.23 seconds
Started May 07 12:39:14 PM PDT 24
Finished May 07 12:39:26 PM PDT 24
Peak memory 211832 kb
Host smart-4bc08b90-443c-4bc3-b60a-7d1fa4d0e9e7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42710355 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_alert_test.42710355
Directory /workspace/42.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/42.rom_ctrl_corrupt_sig_fatal_chk.915810143
Short name T170
Test name
Test status
Simulation time 13397644804 ps
CPU time 62.35 seconds
Started May 07 12:39:29 PM PDT 24
Finished May 07 12:40:32 PM PDT 24
Peak memory 238336 kb
Host smart-8e639ebf-1b71-4d77-b6b8-2fb98ee72857
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=915810143 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_c
orrupt_sig_fatal_chk.915810143
Directory /workspace/42.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/42.rom_ctrl_kmac_err_chk.498609836
Short name T216
Test name
Test status
Simulation time 14316691763 ps
CPU time 30.76 seconds
Started May 07 12:39:21 PM PDT 24
Finished May 07 12:39:53 PM PDT 24
Peak memory 212820 kb
Host smart-6b02d7c1-4e39-482d-bbe3-24a48ba71498
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=498609836 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_kmac_err_chk.498609836
Directory /workspace/42.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/42.rom_ctrl_max_throughput_chk.855662879
Short name T158
Test name
Test status
Simulation time 4108334902 ps
CPU time 13.69 seconds
Started May 07 12:38:57 PM PDT 24
Finished May 07 12:39:14 PM PDT 24
Peak memory 211784 kb
Host smart-7b1095cf-51e7-474d-b91b-28efa0a00828
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=855662879 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_max_throughput_chk.855662879
Directory /workspace/42.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/42.rom_ctrl_smoke.3692683293
Short name T12
Test name
Test status
Simulation time 1854493297 ps
CPU time 21.38 seconds
Started May 07 12:39:17 PM PDT 24
Finished May 07 12:39:41 PM PDT 24
Peak memory 214156 kb
Host smart-198b075d-4d9b-4a04-b919-a9007adb82db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3692683293 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_smoke.3692683293
Directory /workspace/42.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/42.rom_ctrl_stress_all.1818023911
Short name T297
Test name
Test status
Simulation time 6473780682 ps
CPU time 34.58 seconds
Started May 07 12:39:03 PM PDT 24
Finished May 07 12:39:40 PM PDT 24
Peak memory 215960 kb
Host smart-03f6413d-0aae-4eb4-95d6-6ac94278559f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1818023911 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 42.rom_ctrl_stress_all.1818023911
Directory /workspace/42.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/43.rom_ctrl_alert_test.4010803927
Short name T155
Test name
Test status
Simulation time 1143813025 ps
CPU time 10.91 seconds
Started May 07 12:39:10 PM PDT 24
Finished May 07 12:39:23 PM PDT 24
Peak memory 211716 kb
Host smart-4d20582e-bc11-458a-98db-62a5807695a1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4010803927 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_alert_test.4010803927
Directory /workspace/43.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/43.rom_ctrl_corrupt_sig_fatal_chk.1977066384
Short name T313
Test name
Test status
Simulation time 24791569526 ps
CPU time 324.51 seconds
Started May 07 12:39:15 PM PDT 24
Finished May 07 12:44:42 PM PDT 24
Peak memory 235288 kb
Host smart-a2124fad-7718-4ab9-a26d-230ff48619e0
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1977066384 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_
corrupt_sig_fatal_chk.1977066384
Directory /workspace/43.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/43.rom_ctrl_kmac_err_chk.3267779548
Short name T16
Test name
Test status
Simulation time 4403494245 ps
CPU time 21.46 seconds
Started May 07 12:39:04 PM PDT 24
Finished May 07 12:39:28 PM PDT 24
Peak memory 213248 kb
Host smart-25bc52fc-5d51-4b83-bd41-a7ed0bce2e4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3267779548 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_kmac_err_chk.3267779548
Directory /workspace/43.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/43.rom_ctrl_max_throughput_chk.810140437
Short name T11
Test name
Test status
Simulation time 1582886088 ps
CPU time 14.56 seconds
Started May 07 12:39:15 PM PDT 24
Finished May 07 12:39:31 PM PDT 24
Peak memory 211652 kb
Host smart-84d8fac2-9fb5-47e6-a8f5-aee3f9770a0e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=810140437 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_max_throughput_chk.810140437
Directory /workspace/43.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/43.rom_ctrl_smoke.3822297965
Short name T154
Test name
Test status
Simulation time 1902651852 ps
CPU time 17.05 seconds
Started May 07 12:39:15 PM PDT 24
Finished May 07 12:39:34 PM PDT 24
Peak memory 213700 kb
Host smart-c65a4af1-cf18-4c8a-9bae-aff2fd113aee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3822297965 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_smoke.3822297965
Directory /workspace/43.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/43.rom_ctrl_stress_all.3061569226
Short name T361
Test name
Test status
Simulation time 12761080460 ps
CPU time 41.31 seconds
Started May 07 12:39:18 PM PDT 24
Finished May 07 12:40:01 PM PDT 24
Peak memory 214536 kb
Host smart-71a16916-1897-4e53-8587-cd0da2e59939
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3061569226 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 43.rom_ctrl_stress_all.3061569226
Directory /workspace/43.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/44.rom_ctrl_alert_test.439965863
Short name T266
Test name
Test status
Simulation time 3830065282 ps
CPU time 14.32 seconds
Started May 07 12:39:29 PM PDT 24
Finished May 07 12:39:45 PM PDT 24
Peak memory 211828 kb
Host smart-db83e0c1-ad5f-47f1-8e05-bae0daec6f58
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=439965863 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_alert_test.439965863
Directory /workspace/44.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/44.rom_ctrl_corrupt_sig_fatal_chk.1472449894
Short name T206
Test name
Test status
Simulation time 98488284942 ps
CPU time 464.34 seconds
Started May 07 12:39:37 PM PDT 24
Finished May 07 12:47:23 PM PDT 24
Peak memory 237448 kb
Host smart-351a4156-dc63-4443-b574-db9a1894e6b8
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1472449894 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_
corrupt_sig_fatal_chk.1472449894
Directory /workspace/44.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/44.rom_ctrl_kmac_err_chk.1221031760
Short name T23
Test name
Test status
Simulation time 6817480091 ps
CPU time 20.53 seconds
Started May 07 12:39:15 PM PDT 24
Finished May 07 12:39:38 PM PDT 24
Peak memory 212964 kb
Host smart-6137b6c6-9f91-4800-b091-ed79e5199c96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1221031760 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_kmac_err_chk.1221031760
Directory /workspace/44.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/44.rom_ctrl_max_throughput_chk.2070322656
Short name T236
Test name
Test status
Simulation time 493240747 ps
CPU time 5.59 seconds
Started May 07 12:39:08 PM PDT 24
Finished May 07 12:39:15 PM PDT 24
Peak memory 211576 kb
Host smart-92235ec7-d174-485c-9a3f-e1cb741865f2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2070322656 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_max_throughput_chk.2070322656
Directory /workspace/44.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/44.rom_ctrl_smoke.3754125146
Short name T129
Test name
Test status
Simulation time 17838876120 ps
CPU time 35.46 seconds
Started May 07 12:39:10 PM PDT 24
Finished May 07 12:39:47 PM PDT 24
Peak memory 214452 kb
Host smart-020b9809-e836-46ef-86ff-3b3dbd05055a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3754125146 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_smoke.3754125146
Directory /workspace/44.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/44.rom_ctrl_stress_all.4155294563
Short name T213
Test name
Test status
Simulation time 8218757321 ps
CPU time 40.97 seconds
Started May 07 12:39:20 PM PDT 24
Finished May 07 12:40:02 PM PDT 24
Peak memory 219928 kb
Host smart-fe3b7484-aa5c-46fe-9d18-db18e4a509bd
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4155294563 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 44.rom_ctrl_stress_all.4155294563
Directory /workspace/44.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/44.rom_ctrl_stress_all_with_rand_reset.3875771938
Short name T42
Test name
Test status
Simulation time 101776166058 ps
CPU time 962.97 seconds
Started May 07 12:39:22 PM PDT 24
Finished May 07 12:55:26 PM PDT 24
Peak memory 229804 kb
Host smart-6e17d541-782c-4b31-a007-8411ec9e4f1d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3875771938 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_stress_all_with_rand_reset.3875771938
Directory /workspace/44.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.rom_ctrl_alert_test.2682198678
Short name T184
Test name
Test status
Simulation time 1266333917 ps
CPU time 12.49 seconds
Started May 07 12:39:15 PM PDT 24
Finished May 07 12:39:30 PM PDT 24
Peak memory 211672 kb
Host smart-2c38fae3-64de-4987-bcfc-2c95403b6e4a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2682198678 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_alert_test.2682198678
Directory /workspace/45.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/45.rom_ctrl_corrupt_sig_fatal_chk.552087909
Short name T28
Test name
Test status
Simulation time 57022449850 ps
CPU time 336.5 seconds
Started May 07 12:39:16 PM PDT 24
Finished May 07 12:44:55 PM PDT 24
Peak memory 237304 kb
Host smart-4fc765fe-547d-4df2-afd6-976baab9063b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=552087909 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_c
orrupt_sig_fatal_chk.552087909
Directory /workspace/45.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/45.rom_ctrl_kmac_err_chk.329879291
Short name T249
Test name
Test status
Simulation time 3162563400 ps
CPU time 27.3 seconds
Started May 07 12:39:21 PM PDT 24
Finished May 07 12:39:49 PM PDT 24
Peak memory 212580 kb
Host smart-058a384b-268a-4a88-b38c-4569722aeefd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=329879291 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_kmac_err_chk.329879291
Directory /workspace/45.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/45.rom_ctrl_max_throughput_chk.2482308112
Short name T141
Test name
Test status
Simulation time 98202060 ps
CPU time 5.43 seconds
Started May 07 12:39:15 PM PDT 24
Finished May 07 12:39:22 PM PDT 24
Peak memory 211664 kb
Host smart-2f33bf94-fb06-4b0f-be11-3680fde488eb
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2482308112 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_max_throughput_chk.2482308112
Directory /workspace/45.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/45.rom_ctrl_smoke.3187568082
Short name T6
Test name
Test status
Simulation time 847723061 ps
CPU time 15.47 seconds
Started May 07 12:39:17 PM PDT 24
Finished May 07 12:39:35 PM PDT 24
Peak memory 219900 kb
Host smart-9ec18d70-1f43-499c-8d16-73434e3a99f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3187568082 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_smoke.3187568082
Directory /workspace/45.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/45.rom_ctrl_stress_all.1415239826
Short name T10
Test name
Test status
Simulation time 11378809844 ps
CPU time 98.4 seconds
Started May 07 12:39:12 PM PDT 24
Finished May 07 12:40:53 PM PDT 24
Peak memory 219948 kb
Host smart-59f28f3c-ffd9-4a7f-a9b8-bedc0d2e9045
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1415239826 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 45.rom_ctrl_stress_all.1415239826
Directory /workspace/45.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/46.rom_ctrl_alert_test.433866160
Short name T32
Test name
Test status
Simulation time 256560540 ps
CPU time 6.2 seconds
Started May 07 12:39:31 PM PDT 24
Finished May 07 12:39:38 PM PDT 24
Peak memory 211632 kb
Host smart-3f6bacfb-f9d2-4b22-887e-f4c729b5aa25
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=433866160 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_alert_test.433866160
Directory /workspace/46.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/46.rom_ctrl_corrupt_sig_fatal_chk.2188879959
Short name T205
Test name
Test status
Simulation time 35278133273 ps
CPU time 339.83 seconds
Started May 07 12:39:25 PM PDT 24
Finished May 07 12:45:05 PM PDT 24
Peak memory 211968 kb
Host smart-7d6ec3a5-9c60-4030-be85-695e1eefc744
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2188879959 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_
corrupt_sig_fatal_chk.2188879959
Directory /workspace/46.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/46.rom_ctrl_kmac_err_chk.768568679
Short name T21
Test name
Test status
Simulation time 18994396589 ps
CPU time 23.77 seconds
Started May 07 12:39:09 PM PDT 24
Finished May 07 12:39:34 PM PDT 24
Peak memory 212716 kb
Host smart-71c35339-b186-4bd1-a540-b1c152f45a5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=768568679 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_kmac_err_chk.768568679
Directory /workspace/46.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/46.rom_ctrl_max_throughput_chk.381352699
Short name T262
Test name
Test status
Simulation time 203435284 ps
CPU time 5.46 seconds
Started May 07 12:39:35 PM PDT 24
Finished May 07 12:39:43 PM PDT 24
Peak memory 211612 kb
Host smart-8f3b8f8e-4d7a-421e-8db3-49eb7b15e3f7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=381352699 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_max_throughput_chk.381352699
Directory /workspace/46.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/46.rom_ctrl_smoke.2560490094
Short name T126
Test name
Test status
Simulation time 5189514077 ps
CPU time 18.47 seconds
Started May 07 12:39:34 PM PDT 24
Finished May 07 12:39:54 PM PDT 24
Peak memory 214048 kb
Host smart-83b2fe35-9bee-4c97-9b02-c06d9e46a222
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2560490094 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_smoke.2560490094
Directory /workspace/46.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/46.rom_ctrl_stress_all.1728278263
Short name T233
Test name
Test status
Simulation time 4418698164 ps
CPU time 49.93 seconds
Started May 07 12:39:18 PM PDT 24
Finished May 07 12:40:10 PM PDT 24
Peak memory 217844 kb
Host smart-542193cc-40d3-4e8c-bb4e-e3888f9723bb
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1728278263 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 46.rom_ctrl_stress_all.1728278263
Directory /workspace/46.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/46.rom_ctrl_stress_all_with_rand_reset.1114854175
Short name T45
Test name
Test status
Simulation time 174117239514 ps
CPU time 1662.68 seconds
Started May 07 12:39:16 PM PDT 24
Finished May 07 01:07:01 PM PDT 24
Peak memory 236476 kb
Host smart-27ed92db-4542-4341-8a32-1bab79b77d33
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1114854175 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_stress_all_with_rand_reset.1114854175
Directory /workspace/46.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.rom_ctrl_alert_test.4113793910
Short name T240
Test name
Test status
Simulation time 346692960 ps
CPU time 4.07 seconds
Started May 07 12:39:12 PM PDT 24
Finished May 07 12:39:18 PM PDT 24
Peak memory 211672 kb
Host smart-fe7c05a9-bd99-4ca5-935d-cddad5144d95
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4113793910 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_alert_test.4113793910
Directory /workspace/47.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/47.rom_ctrl_corrupt_sig_fatal_chk.3836220683
Short name T245
Test name
Test status
Simulation time 35211615528 ps
CPU time 253.89 seconds
Started May 07 12:39:15 PM PDT 24
Finished May 07 12:43:32 PM PDT 24
Peak memory 229096 kb
Host smart-39cf06e9-fba9-4f6c-a87a-26de9a0ce94b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3836220683 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_
corrupt_sig_fatal_chk.3836220683
Directory /workspace/47.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/47.rom_ctrl_kmac_err_chk.3760498402
Short name T134
Test name
Test status
Simulation time 1235406582 ps
CPU time 18.11 seconds
Started May 07 12:39:19 PM PDT 24
Finished May 07 12:39:39 PM PDT 24
Peak memory 212300 kb
Host smart-95d48cb0-329a-41e3-aa57-a810fba1b58d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3760498402 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_kmac_err_chk.3760498402
Directory /workspace/47.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/47.rom_ctrl_max_throughput_chk.1092070541
Short name T281
Test name
Test status
Simulation time 503878937 ps
CPU time 5.21 seconds
Started May 07 12:39:24 PM PDT 24
Finished May 07 12:39:30 PM PDT 24
Peak memory 211656 kb
Host smart-d1bd0489-a558-4e89-8e24-44cd0b36ba62
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1092070541 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_max_throughput_chk.1092070541
Directory /workspace/47.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/47.rom_ctrl_smoke.1429603115
Short name T316
Test name
Test status
Simulation time 3775487774 ps
CPU time 35.15 seconds
Started May 07 12:39:20 PM PDT 24
Finished May 07 12:39:56 PM PDT 24
Peak memory 220024 kb
Host smart-ecdeb532-44f6-4c91-9411-f8d9c33bf308
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1429603115 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_smoke.1429603115
Directory /workspace/47.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/47.rom_ctrl_stress_all.4054600909
Short name T198
Test name
Test status
Simulation time 4097162033 ps
CPU time 36.51 seconds
Started May 07 12:39:31 PM PDT 24
Finished May 07 12:40:08 PM PDT 24
Peak memory 213800 kb
Host smart-543a8e8c-d16d-4072-9cd8-c3d13f09de45
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4054600909 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 47.rom_ctrl_stress_all.4054600909
Directory /workspace/47.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/48.rom_ctrl_alert_test.3013333616
Short name T347
Test name
Test status
Simulation time 8390210707 ps
CPU time 16.82 seconds
Started May 07 12:39:19 PM PDT 24
Finished May 07 12:39:38 PM PDT 24
Peak memory 211716 kb
Host smart-5da985c0-ec64-49da-8326-41cc99371ae9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3013333616 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_alert_test.3013333616
Directory /workspace/48.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/48.rom_ctrl_corrupt_sig_fatal_chk.975166747
Short name T197
Test name
Test status
Simulation time 3480792256 ps
CPU time 121.74 seconds
Started May 07 12:39:29 PM PDT 24
Finished May 07 12:41:32 PM PDT 24
Peak memory 238260 kb
Host smart-e140af29-965a-4711-a079-cb596e13d3ab
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=975166747 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_c
orrupt_sig_fatal_chk.975166747
Directory /workspace/48.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/48.rom_ctrl_kmac_err_chk.4018423494
Short name T265
Test name
Test status
Simulation time 11357230065 ps
CPU time 26.5 seconds
Started May 07 12:39:20 PM PDT 24
Finished May 07 12:39:48 PM PDT 24
Peak memory 212836 kb
Host smart-08d39016-173b-4e5f-b7c3-7925a0849377
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4018423494 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_kmac_err_chk.4018423494
Directory /workspace/48.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/48.rom_ctrl_max_throughput_chk.358294760
Short name T177
Test name
Test status
Simulation time 781355733 ps
CPU time 9.27 seconds
Started May 07 12:39:21 PM PDT 24
Finished May 07 12:39:32 PM PDT 24
Peak memory 211676 kb
Host smart-7ca9255c-1907-4be4-8d22-b0dc73a72b34
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=358294760 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_max_throughput_chk.358294760
Directory /workspace/48.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/48.rom_ctrl_smoke.2972251137
Short name T137
Test name
Test status
Simulation time 3191928170 ps
CPU time 28.7 seconds
Started May 07 12:39:28 PM PDT 24
Finished May 07 12:39:58 PM PDT 24
Peak memory 220028 kb
Host smart-2b30c9ad-253f-4a06-b16d-4448bd874698
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2972251137 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_smoke.2972251137
Directory /workspace/48.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/48.rom_ctrl_stress_all.3713938810
Short name T291
Test name
Test status
Simulation time 1274233809 ps
CPU time 23.43 seconds
Started May 07 12:39:18 PM PDT 24
Finished May 07 12:39:44 PM PDT 24
Peak memory 216884 kb
Host smart-948620b8-9ab0-4cc3-97d7-7578369e9b83
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3713938810 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 48.rom_ctrl_stress_all.3713938810
Directory /workspace/48.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/49.rom_ctrl_alert_test.4228611842
Short name T191
Test name
Test status
Simulation time 1972146798 ps
CPU time 14.79 seconds
Started May 07 12:39:21 PM PDT 24
Finished May 07 12:39:37 PM PDT 24
Peak memory 211708 kb
Host smart-ac26ef34-fde1-44c9-8eb8-98e0629af0cd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4228611842 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_alert_test.4228611842
Directory /workspace/49.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/49.rom_ctrl_corrupt_sig_fatal_chk.727681422
Short name T178
Test name
Test status
Simulation time 16996617422 ps
CPU time 125.17 seconds
Started May 07 12:39:22 PM PDT 24
Finished May 07 12:41:29 PM PDT 24
Peak memory 228156 kb
Host smart-e751a801-d2e4-4ed3-9f6c-198a21ea8e10
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=727681422 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_c
orrupt_sig_fatal_chk.727681422
Directory /workspace/49.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/49.rom_ctrl_kmac_err_chk.2872871913
Short name T362
Test name
Test status
Simulation time 2259597021 ps
CPU time 23.06 seconds
Started May 07 12:39:14 PM PDT 24
Finished May 07 12:39:39 PM PDT 24
Peak memory 212388 kb
Host smart-ba0cbbce-3a3f-4d37-9838-30356e0decd3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2872871913 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_kmac_err_chk.2872871913
Directory /workspace/49.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/49.rom_ctrl_max_throughput_chk.2354625635
Short name T314
Test name
Test status
Simulation time 188682262 ps
CPU time 6.76 seconds
Started May 07 12:39:27 PM PDT 24
Finished May 07 12:39:35 PM PDT 24
Peak memory 211644 kb
Host smart-f327dbcf-36b3-4d53-b140-34cb08573feb
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2354625635 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_max_throughput_chk.2354625635
Directory /workspace/49.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/49.rom_ctrl_smoke.4172740654
Short name T272
Test name
Test status
Simulation time 1205264968 ps
CPU time 14.58 seconds
Started May 07 12:39:26 PM PDT 24
Finished May 07 12:39:42 PM PDT 24
Peak memory 219856 kb
Host smart-1433df29-f3c3-4fad-9150-f17f595bd0e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4172740654 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_smoke.4172740654
Directory /workspace/49.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/49.rom_ctrl_stress_all.2817462467
Short name T90
Test name
Test status
Simulation time 3295718577 ps
CPU time 15.27 seconds
Started May 07 12:39:06 PM PDT 24
Finished May 07 12:39:23 PM PDT 24
Peak memory 212068 kb
Host smart-1400afca-a42a-4718-87c0-a861e1373f62
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2817462467 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 49.rom_ctrl_stress_all.2817462467
Directory /workspace/49.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/5.rom_ctrl_alert_test.3045144471
Short name T89
Test name
Test status
Simulation time 347639842 ps
CPU time 4.35 seconds
Started May 07 12:38:54 PM PDT 24
Finished May 07 12:39:02 PM PDT 24
Peak memory 211676 kb
Host smart-7330ce7d-247b-4619-9421-eb4654f0f7a2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3045144471 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_alert_test.3045144471
Directory /workspace/5.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/5.rom_ctrl_corrupt_sig_fatal_chk.689558929
Short name T243
Test name
Test status
Simulation time 81750874940 ps
CPU time 368.7 seconds
Started May 07 12:38:57 PM PDT 24
Finished May 07 12:45:09 PM PDT 24
Peak memory 238296 kb
Host smart-d8e6663a-8a8b-40e0-85f8-5ed821e36e90
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=689558929 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_co
rrupt_sig_fatal_chk.689558929
Directory /workspace/5.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/5.rom_ctrl_kmac_err_chk.1498991921
Short name T309
Test name
Test status
Simulation time 170702093 ps
CPU time 9.64 seconds
Started May 07 12:38:52 PM PDT 24
Finished May 07 12:39:04 PM PDT 24
Peak memory 212488 kb
Host smart-04eca7e8-cbb3-4728-9fbb-858f2cb3b3d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1498991921 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_kmac_err_chk.1498991921
Directory /workspace/5.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/5.rom_ctrl_max_throughput_chk.3819699120
Short name T86
Test name
Test status
Simulation time 1115606308 ps
CPU time 12.48 seconds
Started May 07 12:38:48 PM PDT 24
Finished May 07 12:39:03 PM PDT 24
Peak memory 211564 kb
Host smart-9a4d416a-e6b5-4730-8f59-e7e77cae4b61
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3819699120 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_max_throughput_chk.3819699120
Directory /workspace/5.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/5.rom_ctrl_smoke.3939093576
Short name T218
Test name
Test status
Simulation time 3978568139 ps
CPU time 31.49 seconds
Started May 07 12:38:54 PM PDT 24
Finished May 07 12:39:28 PM PDT 24
Peak memory 213180 kb
Host smart-03e430f4-0ce7-4aa5-98b2-d8b354f8db53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3939093576 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_smoke.3939093576
Directory /workspace/5.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/5.rom_ctrl_stress_all.3011165220
Short name T145
Test name
Test status
Simulation time 2163836598 ps
CPU time 29.36 seconds
Started May 07 12:38:45 PM PDT 24
Finished May 07 12:39:15 PM PDT 24
Peak memory 219960 kb
Host smart-65b985a4-924e-41f7-b630-c595d6a3ed54
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3011165220 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 5.rom_ctrl_stress_all.3011165220
Directory /workspace/5.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/6.rom_ctrl_alert_test.3426301753
Short name T182
Test name
Test status
Simulation time 11284895799 ps
CPU time 15.52 seconds
Started May 07 12:38:52 PM PDT 24
Finished May 07 12:39:09 PM PDT 24
Peak memory 211836 kb
Host smart-430b5d49-9d6c-4943-aee6-dfff5c8471c0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3426301753 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_alert_test.3426301753
Directory /workspace/6.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/6.rom_ctrl_corrupt_sig_fatal_chk.3081695184
Short name T303
Test name
Test status
Simulation time 92701848631 ps
CPU time 200.65 seconds
Started May 07 12:38:50 PM PDT 24
Finished May 07 12:42:13 PM PDT 24
Peak memory 220260 kb
Host smart-452e68ae-74de-4438-bf45-1661d32c688d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3081695184 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_c
orrupt_sig_fatal_chk.3081695184
Directory /workspace/6.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/6.rom_ctrl_kmac_err_chk.2557257080
Short name T238
Test name
Test status
Simulation time 2040368849 ps
CPU time 22.2 seconds
Started May 07 12:38:52 PM PDT 24
Finished May 07 12:39:16 PM PDT 24
Peak memory 212440 kb
Host smart-e184ee1e-38e2-4c32-b723-ca2dfb221243
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2557257080 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_kmac_err_chk.2557257080
Directory /workspace/6.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/6.rom_ctrl_max_throughput_chk.939676800
Short name T109
Test name
Test status
Simulation time 8541924132 ps
CPU time 18.06 seconds
Started May 07 12:38:57 PM PDT 24
Finished May 07 12:39:18 PM PDT 24
Peak memory 211764 kb
Host smart-07fb30b9-797f-40c3-a80a-da0accb3adf9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=939676800 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_max_throughput_chk.939676800
Directory /workspace/6.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/6.rom_ctrl_smoke.2717835938
Short name T92
Test name
Test status
Simulation time 5511353433 ps
CPU time 30.91 seconds
Started May 07 12:38:47 PM PDT 24
Finished May 07 12:39:19 PM PDT 24
Peak memory 214404 kb
Host smart-11d46fc5-f751-424e-bf21-0f795ccaf328
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2717835938 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_smoke.2717835938
Directory /workspace/6.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/6.rom_ctrl_stress_all.2863122864
Short name T176
Test name
Test status
Simulation time 1029901301 ps
CPU time 16.77 seconds
Started May 07 12:38:48 PM PDT 24
Finished May 07 12:39:07 PM PDT 24
Peak memory 214288 kb
Host smart-e8ce871d-d4dd-43e0-a668-0649737ab28e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2863122864 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 6.rom_ctrl_stress_all.2863122864
Directory /workspace/6.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/7.rom_ctrl_alert_test.3455940437
Short name T57
Test name
Test status
Simulation time 85611470 ps
CPU time 4.37 seconds
Started May 07 12:38:44 PM PDT 24
Finished May 07 12:38:50 PM PDT 24
Peak memory 211692 kb
Host smart-5de8715e-d9d9-46c2-8076-ff40fbb02eba
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3455940437 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_alert_test.3455940437
Directory /workspace/7.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/7.rom_ctrl_corrupt_sig_fatal_chk.915133403
Short name T341
Test name
Test status
Simulation time 1038368285 ps
CPU time 69.7 seconds
Started May 07 12:38:55 PM PDT 24
Finished May 07 12:40:08 PM PDT 24
Peak memory 229000 kb
Host smart-012cbf2c-67e0-4337-815e-0002b9334004
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=915133403 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_co
rrupt_sig_fatal_chk.915133403
Directory /workspace/7.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/7.rom_ctrl_kmac_err_chk.2045735950
Short name T149
Test name
Test status
Simulation time 2974033698 ps
CPU time 25 seconds
Started May 07 12:38:59 PM PDT 24
Finished May 07 12:39:28 PM PDT 24
Peak memory 212344 kb
Host smart-79ca2ff0-9bc0-42ee-8d65-1a2fe6e180a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2045735950 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_kmac_err_chk.2045735950
Directory /workspace/7.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/7.rom_ctrl_max_throughput_chk.1633132663
Short name T135
Test name
Test status
Simulation time 221941928 ps
CPU time 7.2 seconds
Started May 07 12:38:51 PM PDT 24
Finished May 07 12:38:59 PM PDT 24
Peak memory 211616 kb
Host smart-ad07a266-3f8c-454d-a451-62c135ead816
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1633132663 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_max_throughput_chk.1633132663
Directory /workspace/7.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/7.rom_ctrl_smoke.2004487831
Short name T355
Test name
Test status
Simulation time 213734036 ps
CPU time 10.22 seconds
Started May 07 12:39:08 PM PDT 24
Finished May 07 12:39:20 PM PDT 24
Peak memory 214060 kb
Host smart-236b80a0-db5a-4f22-a2a9-da4d2d92ff83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2004487831 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_smoke.2004487831
Directory /workspace/7.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/7.rom_ctrl_stress_all.1897707858
Short name T274
Test name
Test status
Simulation time 4810385828 ps
CPU time 17.94 seconds
Started May 07 12:38:55 PM PDT 24
Finished May 07 12:39:15 PM PDT 24
Peak memory 215708 kb
Host smart-56a22169-bf67-4dfc-9902-7a1115775f39
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1897707858 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 7.rom_ctrl_stress_all.1897707858
Directory /workspace/7.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/8.rom_ctrl_alert_test.905510520
Short name T338
Test name
Test status
Simulation time 86331174 ps
CPU time 4.21 seconds
Started May 07 12:39:01 PM PDT 24
Finished May 07 12:39:08 PM PDT 24
Peak memory 211596 kb
Host smart-3a752643-a55f-4ed2-8c28-724897060ac9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=905510520 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_alert_test.905510520
Directory /workspace/8.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/8.rom_ctrl_corrupt_sig_fatal_chk.516921513
Short name T174
Test name
Test status
Simulation time 36723732405 ps
CPU time 351.86 seconds
Started May 07 12:38:48 PM PDT 24
Finished May 07 12:44:42 PM PDT 24
Peak memory 225192 kb
Host smart-a12e081c-b99e-41c8-b663-9fd4ccdf50e5
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=516921513 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_co
rrupt_sig_fatal_chk.516921513
Directory /workspace/8.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/8.rom_ctrl_kmac_err_chk.392768110
Short name T323
Test name
Test status
Simulation time 1337905058 ps
CPU time 18.24 seconds
Started May 07 12:38:47 PM PDT 24
Finished May 07 12:39:07 PM PDT 24
Peak memory 212360 kb
Host smart-82b5018b-15cc-48e9-8849-5190151cf4e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=392768110 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_kmac_err_chk.392768110
Directory /workspace/8.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/8.rom_ctrl_max_throughput_chk.1439110404
Short name T168
Test name
Test status
Simulation time 549412274 ps
CPU time 8.65 seconds
Started May 07 12:38:51 PM PDT 24
Finished May 07 12:39:01 PM PDT 24
Peak memory 211632 kb
Host smart-a55cb74c-7951-4314-a78f-e0e9b329bdd1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1439110404 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_max_throughput_chk.1439110404
Directory /workspace/8.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/8.rom_ctrl_smoke.1162283487
Short name T285
Test name
Test status
Simulation time 754125345 ps
CPU time 10.1 seconds
Started May 07 12:38:59 PM PDT 24
Finished May 07 12:39:12 PM PDT 24
Peak memory 219872 kb
Host smart-bfba8be4-0c1f-4d40-84d7-cf67164a64f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1162283487 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_smoke.1162283487
Directory /workspace/8.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/8.rom_ctrl_stress_all.220849586
Short name T167
Test name
Test status
Simulation time 486986519 ps
CPU time 27.18 seconds
Started May 07 12:39:05 PM PDT 24
Finished May 07 12:39:35 PM PDT 24
Peak memory 215736 kb
Host smart-bb2a69bd-6010-49d5-b78d-29f5b21a44e2
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=220849586 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 8.rom_ctrl_stress_all.220849586
Directory /workspace/8.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/8.rom_ctrl_stress_all_with_rand_reset.1488538837
Short name T1
Test name
Test status
Simulation time 329750891650 ps
CPU time 1652.76 seconds
Started May 07 12:38:54 PM PDT 24
Finished May 07 01:06:30 PM PDT 24
Peak memory 239416 kb
Host smart-97c401c9-43fc-4c33-bda8-a1d32468e4eb
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1488538837 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_stress_all_with_rand_reset.1488538837
Directory /workspace/8.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.rom_ctrl_alert_test.221836058
Short name T342
Test name
Test status
Simulation time 5460701103 ps
CPU time 12.58 seconds
Started May 07 12:38:56 PM PDT 24
Finished May 07 12:39:11 PM PDT 24
Peak memory 211796 kb
Host smart-c293a5bc-a9cb-48c8-a01f-22f3c0e50e4d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=221836058 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_alert_test.221836058
Directory /workspace/9.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/9.rom_ctrl_corrupt_sig_fatal_chk.609099461
Short name T214
Test name
Test status
Simulation time 1515668184 ps
CPU time 83.18 seconds
Started May 07 12:38:53 PM PDT 24
Finished May 07 12:40:19 PM PDT 24
Peak memory 231036 kb
Host smart-9b7fc95c-2c3f-4216-a50f-625b3827eb25
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=609099461 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_co
rrupt_sig_fatal_chk.609099461
Directory /workspace/9.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/9.rom_ctrl_kmac_err_chk.3706896454
Short name T91
Test name
Test status
Simulation time 8140388183 ps
CPU time 22.28 seconds
Started May 07 12:38:53 PM PDT 24
Finished May 07 12:39:18 PM PDT 24
Peak memory 212768 kb
Host smart-ad7cda30-3347-4b2f-bbc0-386290a8f604
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3706896454 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_kmac_err_chk.3706896454
Directory /workspace/9.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/9.rom_ctrl_max_throughput_chk.2630013735
Short name T164
Test name
Test status
Simulation time 1810850549 ps
CPU time 15.54 seconds
Started May 07 12:38:51 PM PDT 24
Finished May 07 12:39:09 PM PDT 24
Peak memory 211636 kb
Host smart-20d79a54-53c0-4555-a769-f5ba259a1638
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2630013735 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_max_throughput_chk.2630013735
Directory /workspace/9.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/9.rom_ctrl_smoke.3284264854
Short name T349
Test name
Test status
Simulation time 9877387156 ps
CPU time 24.73 seconds
Started May 07 12:38:59 PM PDT 24
Finished May 07 12:39:27 PM PDT 24
Peak memory 220012 kb
Host smart-fcee17e4-6595-4090-b956-2c04808ff6f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3284264854 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_smoke.3284264854
Directory /workspace/9.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/9.rom_ctrl_stress_all.225736336
Short name T239
Test name
Test status
Simulation time 3325104904 ps
CPU time 11.67 seconds
Started May 07 12:39:05 PM PDT 24
Finished May 07 12:39:19 PM PDT 24
Peak memory 211664 kb
Host smart-82e9f8c8-9643-4a2a-9013-690e00f303d7
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=225736336 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 9.rom_ctrl_stress_all.225736336
Directory /workspace/9.rom_ctrl_stress_all/latest
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