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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
97.52 96.97 93.01 97.88 100.00 98.37 98.03 98.37


Total test records in report: 471
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T297 /workspace/coverage/default/42.rom_ctrl_stress_all_with_rand_reset.2176829278 May 09 12:37:46 PM PDT 24 May 09 01:07:35 PM PDT 24 46798932835 ps
T298 /workspace/coverage/default/44.rom_ctrl_alert_test.3335132192 May 09 12:37:38 PM PDT 24 May 09 12:38:05 PM PDT 24 27127370617 ps
T299 /workspace/coverage/default/30.rom_ctrl_kmac_err_chk.114636727 May 09 12:37:41 PM PDT 24 May 09 12:38:26 PM PDT 24 17505470643 ps
T300 /workspace/coverage/default/5.rom_ctrl_corrupt_sig_fatal_chk.3352716483 May 09 12:37:28 PM PDT 24 May 09 12:41:19 PM PDT 24 24865592338 ps
T301 /workspace/coverage/default/22.rom_ctrl_kmac_err_chk.623819198 May 09 12:37:53 PM PDT 24 May 09 12:38:15 PM PDT 24 519586116 ps
T302 /workspace/coverage/default/20.rom_ctrl_stress_all_with_rand_reset.2440750724 May 09 12:37:50 PM PDT 24 May 09 12:55:52 PM PDT 24 27177997824 ps
T303 /workspace/coverage/default/23.rom_ctrl_stress_all.1128136503 May 09 12:37:43 PM PDT 24 May 09 12:38:16 PM PDT 24 377076841 ps
T304 /workspace/coverage/default/30.rom_ctrl_corrupt_sig_fatal_chk.760430451 May 09 12:37:41 PM PDT 24 May 09 12:40:19 PM PDT 24 6171597792 ps
T305 /workspace/coverage/default/9.rom_ctrl_smoke.4193972034 May 09 12:37:07 PM PDT 24 May 09 12:37:55 PM PDT 24 3928075336 ps
T306 /workspace/coverage/default/12.rom_ctrl_corrupt_sig_fatal_chk.3101491864 May 09 12:37:10 PM PDT 24 May 09 12:42:01 PM PDT 24 74503049786 ps
T307 /workspace/coverage/default/17.rom_ctrl_alert_test.71343454 May 09 12:37:35 PM PDT 24 May 09 12:37:50 PM PDT 24 171761187 ps
T308 /workspace/coverage/default/13.rom_ctrl_alert_test.4026072610 May 09 12:38:30 PM PDT 24 May 09 12:39:00 PM PDT 24 1776927854 ps
T309 /workspace/coverage/default/19.rom_ctrl_stress_all.3005237344 May 09 12:37:51 PM PDT 24 May 09 12:38:22 PM PDT 24 399365719 ps
T310 /workspace/coverage/default/43.rom_ctrl_smoke.3203012798 May 09 12:37:54 PM PDT 24 May 09 12:38:36 PM PDT 24 4640036759 ps
T311 /workspace/coverage/default/43.rom_ctrl_corrupt_sig_fatal_chk.944074139 May 09 12:37:56 PM PDT 24 May 09 12:43:53 PM PDT 24 40167500336 ps
T312 /workspace/coverage/default/24.rom_ctrl_max_throughput_chk.50956695 May 09 12:37:35 PM PDT 24 May 09 12:37:59 PM PDT 24 2593445262 ps
T313 /workspace/coverage/default/16.rom_ctrl_stress_all.1060924079 May 09 12:37:28 PM PDT 24 May 09 12:38:22 PM PDT 24 42237519905 ps
T314 /workspace/coverage/default/0.rom_ctrl_alert_test.1912127962 May 09 12:37:16 PM PDT 24 May 09 12:37:35 PM PDT 24 347440955 ps
T315 /workspace/coverage/default/7.rom_ctrl_kmac_err_chk.1325625257 May 09 12:37:27 PM PDT 24 May 09 12:38:11 PM PDT 24 7995999747 ps
T316 /workspace/coverage/default/42.rom_ctrl_kmac_err_chk.3822608385 May 09 12:37:48 PM PDT 24 May 09 12:38:18 PM PDT 24 1949212973 ps
T317 /workspace/coverage/default/48.rom_ctrl_max_throughput_chk.3594972746 May 09 12:37:44 PM PDT 24 May 09 12:38:13 PM PDT 24 11331841688 ps
T318 /workspace/coverage/default/11.rom_ctrl_max_throughput_chk.1059123573 May 09 12:37:36 PM PDT 24 May 09 12:38:04 PM PDT 24 12579861586 ps
T319 /workspace/coverage/default/13.rom_ctrl_smoke.3340007536 May 09 12:37:25 PM PDT 24 May 09 12:38:02 PM PDT 24 2235888215 ps
T320 /workspace/coverage/default/14.rom_ctrl_max_throughput_chk.2908918662 May 09 12:37:21 PM PDT 24 May 09 12:37:41 PM PDT 24 387219872 ps
T321 /workspace/coverage/default/26.rom_ctrl_smoke.1395893658 May 09 12:37:46 PM PDT 24 May 09 12:38:10 PM PDT 24 1416265968 ps
T322 /workspace/coverage/default/49.rom_ctrl_max_throughput_chk.235140993 May 09 12:38:06 PM PDT 24 May 09 12:38:40 PM PDT 24 2143223589 ps
T323 /workspace/coverage/default/38.rom_ctrl_max_throughput_chk.2968081483 May 09 12:38:38 PM PDT 24 May 09 12:39:01 PM PDT 24 146655731 ps
T324 /workspace/coverage/default/9.rom_ctrl_corrupt_sig_fatal_chk.1163656831 May 09 12:37:17 PM PDT 24 May 09 12:42:55 PM PDT 24 295568757351 ps
T325 /workspace/coverage/default/2.rom_ctrl_smoke.1923471144 May 09 12:37:21 PM PDT 24 May 09 12:37:51 PM PDT 24 2318102538 ps
T326 /workspace/coverage/default/7.rom_ctrl_stress_all.2986775855 May 09 12:37:15 PM PDT 24 May 09 12:38:21 PM PDT 24 6681438894 ps
T327 /workspace/coverage/default/29.rom_ctrl_alert_test.623128488 May 09 12:37:34 PM PDT 24 May 09 12:38:02 PM PDT 24 11902756497 ps
T328 /workspace/coverage/default/34.rom_ctrl_max_throughput_chk.3194937927 May 09 12:37:53 PM PDT 24 May 09 12:38:14 PM PDT 24 3144832338 ps
T31 /workspace/coverage/default/2.rom_ctrl_sec_cm.852994602 May 09 12:38:30 PM PDT 24 May 09 12:40:24 PM PDT 24 1198657948 ps
T329 /workspace/coverage/default/45.rom_ctrl_alert_test.1616867386 May 09 12:38:00 PM PDT 24 May 09 12:38:20 PM PDT 24 87160717 ps
T330 /workspace/coverage/default/27.rom_ctrl_alert_test.171755138 May 09 12:37:32 PM PDT 24 May 09 12:37:49 PM PDT 24 754329445 ps
T331 /workspace/coverage/default/17.rom_ctrl_corrupt_sig_fatal_chk.613993864 May 09 12:37:37 PM PDT 24 May 09 12:42:29 PM PDT 24 196956284517 ps
T332 /workspace/coverage/default/37.rom_ctrl_kmac_err_chk.3249077326 May 09 12:37:49 PM PDT 24 May 09 12:38:26 PM PDT 24 3038349254 ps
T333 /workspace/coverage/default/13.rom_ctrl_kmac_err_chk.1880660388 May 09 12:38:29 PM PDT 24 May 09 12:39:10 PM PDT 24 11133887180 ps
T334 /workspace/coverage/default/28.rom_ctrl_kmac_err_chk.2855677822 May 09 12:37:25 PM PDT 24 May 09 12:38:00 PM PDT 24 2131334986 ps
T335 /workspace/coverage/default/47.rom_ctrl_smoke.1715765273 May 09 12:37:49 PM PDT 24 May 09 12:38:17 PM PDT 24 2002446144 ps
T336 /workspace/coverage/default/30.rom_ctrl_max_throughput_chk.4159836125 May 09 12:38:43 PM PDT 24 May 09 12:39:05 PM PDT 24 575930512 ps
T337 /workspace/coverage/default/10.rom_ctrl_kmac_err_chk.701736345 May 09 12:37:26 PM PDT 24 May 09 12:38:00 PM PDT 24 3638459178 ps
T338 /workspace/coverage/default/30.rom_ctrl_smoke.2125126525 May 09 12:38:43 PM PDT 24 May 09 12:39:12 PM PDT 24 350114867 ps
T339 /workspace/coverage/default/23.rom_ctrl_max_throughput_chk.1684508679 May 09 12:37:33 PM PDT 24 May 09 12:37:58 PM PDT 24 1390436119 ps
T340 /workspace/coverage/default/6.rom_ctrl_kmac_err_chk.763561658 May 09 12:37:35 PM PDT 24 May 09 12:37:56 PM PDT 24 168786618 ps
T341 /workspace/coverage/default/12.rom_ctrl_kmac_err_chk.1298474921 May 09 12:38:33 PM PDT 24 May 09 12:39:09 PM PDT 24 1797484940 ps
T342 /workspace/coverage/default/0.rom_ctrl_stress_all.1546107507 May 09 12:37:22 PM PDT 24 May 09 12:38:10 PM PDT 24 656947211 ps
T343 /workspace/coverage/default/19.rom_ctrl_corrupt_sig_fatal_chk.989936816 May 09 12:37:37 PM PDT 24 May 09 12:43:01 PM PDT 24 31189785559 ps
T35 /workspace/coverage/default/4.rom_ctrl_sec_cm.2538636672 May 09 12:37:14 PM PDT 24 May 09 12:38:24 PM PDT 24 13002766427 ps
T344 /workspace/coverage/default/14.rom_ctrl_smoke.1266399626 May 09 12:38:29 PM PDT 24 May 09 12:38:59 PM PDT 24 613064918 ps
T345 /workspace/coverage/default/2.rom_ctrl_corrupt_sig_fatal_chk.753132074 May 09 12:37:16 PM PDT 24 May 09 12:38:41 PM PDT 24 5963155952 ps
T346 /workspace/coverage/default/14.rom_ctrl_stress_all.2691774387 May 09 12:37:23 PM PDT 24 May 09 12:39:08 PM PDT 24 18340402508 ps
T347 /workspace/coverage/default/42.rom_ctrl_corrupt_sig_fatal_chk.2955286097 May 09 12:37:55 PM PDT 24 May 09 12:41:50 PM PDT 24 40760808519 ps
T36 /workspace/coverage/default/0.rom_ctrl_sec_cm.3479591699 May 09 12:37:25 PM PDT 24 May 09 12:38:36 PM PDT 24 2850153749 ps
T348 /workspace/coverage/default/26.rom_ctrl_alert_test.1021933798 May 09 12:37:39 PM PDT 24 May 09 12:37:59 PM PDT 24 3544277598 ps
T349 /workspace/coverage/default/48.rom_ctrl_alert_test.672349829 May 09 12:38:04 PM PDT 24 May 09 12:38:26 PM PDT 24 1247182694 ps
T350 /workspace/coverage/default/29.rom_ctrl_max_throughput_chk.2172263643 May 09 12:37:49 PM PDT 24 May 09 12:38:07 PM PDT 24 425193153 ps
T351 /workspace/coverage/default/8.rom_ctrl_stress_all.4041667900 May 09 12:37:37 PM PDT 24 May 09 12:38:14 PM PDT 24 1392716720 ps
T352 /workspace/coverage/default/35.rom_ctrl_smoke.3388441772 May 09 12:37:56 PM PDT 24 May 09 12:38:25 PM PDT 24 848521131 ps
T353 /workspace/coverage/default/2.rom_ctrl_max_throughput_chk.234842773 May 09 12:37:21 PM PDT 24 May 09 12:37:48 PM PDT 24 2397126141 ps
T354 /workspace/coverage/default/40.rom_ctrl_alert_test.636149994 May 09 12:37:58 PM PDT 24 May 09 12:38:19 PM PDT 24 671845877 ps
T355 /workspace/coverage/default/22.rom_ctrl_max_throughput_chk.3923147517 May 09 12:37:43 PM PDT 24 May 09 12:38:01 PM PDT 24 829056824 ps
T356 /workspace/coverage/default/2.rom_ctrl_stress_all_with_rand_reset.3168293318 May 09 12:37:19 PM PDT 24 May 09 01:14:45 PM PDT 24 278298991594 ps
T357 /workspace/coverage/default/38.rom_ctrl_stress_all.1873521490 May 09 12:38:43 PM PDT 24 May 09 12:39:56 PM PDT 24 23479266388 ps
T358 /workspace/coverage/default/4.rom_ctrl_stress_all.4150193113 May 09 12:37:19 PM PDT 24 May 09 12:38:31 PM PDT 24 5531713425 ps
T359 /workspace/coverage/default/17.rom_ctrl_stress_all_with_rand_reset.3433508620 May 09 12:37:30 PM PDT 24 May 09 01:10:19 PM PDT 24 60535156146 ps
T360 /workspace/coverage/default/25.rom_ctrl_corrupt_sig_fatal_chk.417679783 May 09 12:37:31 PM PDT 24 May 09 12:39:31 PM PDT 24 1957139388 ps
T361 /workspace/coverage/default/14.rom_ctrl_alert_test.647156783 May 09 12:37:14 PM PDT 24 May 09 12:37:38 PM PDT 24 1995185752 ps
T362 /workspace/coverage/default/23.rom_ctrl_smoke.1052028826 May 09 12:37:27 PM PDT 24 May 09 12:38:02 PM PDT 24 1968637205 ps
T363 /workspace/coverage/default/49.rom_ctrl_alert_test.4044789034 May 09 12:37:58 PM PDT 24 May 09 12:38:26 PM PDT 24 1580390465 ps
T364 /workspace/coverage/default/46.rom_ctrl_smoke.1289499139 May 09 12:37:59 PM PDT 24 May 09 12:38:40 PM PDT 24 9915137643 ps
T365 /workspace/coverage/default/8.rom_ctrl_kmac_err_chk.3306050825 May 09 12:37:35 PM PDT 24 May 09 12:37:59 PM PDT 24 582661169 ps
T366 /workspace/coverage/default/0.rom_ctrl_smoke.3925411893 May 09 12:37:10 PM PDT 24 May 09 12:37:56 PM PDT 24 8022886963 ps
T367 /workspace/coverage/default/1.rom_ctrl_kmac_err_chk.2450122345 May 09 12:37:13 PM PDT 24 May 09 12:38:00 PM PDT 24 16309466472 ps
T368 /workspace/coverage/default/11.rom_ctrl_stress_all.3066408054 May 09 12:37:28 PM PDT 24 May 09 12:38:15 PM PDT 24 2985593746 ps
T369 /workspace/coverage/default/44.rom_ctrl_max_throughput_chk.59231584 May 09 12:37:36 PM PDT 24 May 09 12:38:04 PM PDT 24 2074991286 ps
T59 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_rw.3107576827 May 09 12:36:48 PM PDT 24 May 09 12:37:06 PM PDT 24 693612464 ps
T60 /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_rw.3143802226 May 09 12:37:05 PM PDT 24 May 09 12:37:26 PM PDT 24 3002810779 ps
T61 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_hw_reset.4099492278 May 09 12:37:18 PM PDT 24 May 09 12:37:49 PM PDT 24 7891344770 ps
T370 /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_errors.860620286 May 09 12:36:54 PM PDT 24 May 09 12:37:20 PM PDT 24 2573105631 ps
T65 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_rw.2354049739 May 09 12:36:37 PM PDT 24 May 09 12:36:58 PM PDT 24 7376635076 ps
T371 /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_mem_rw_with_rand_reset.2329037425 May 09 12:37:00 PM PDT 24 May 09 12:37:19 PM PDT 24 648825218 ps
T372 /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_mem_rw_with_rand_reset.998093093 May 09 12:37:17 PM PDT 24 May 09 12:37:41 PM PDT 24 951058768 ps
T373 /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_errors.3668334513 May 09 12:36:41 PM PDT 24 May 09 12:37:05 PM PDT 24 2629697169 ps
T56 /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_intg_err.218871370 May 09 12:37:00 PM PDT 24 May 09 12:38:23 PM PDT 24 2411539091 ps
T57 /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_intg_err.3705201876 May 09 12:37:05 PM PDT 24 May 09 12:38:03 PM PDT 24 6717021433 ps
T100 /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_rw.1879278328 May 09 12:37:18 PM PDT 24 May 09 12:37:48 PM PDT 24 15374624200 ps
T66 /workspace/coverage/cover_reg_top/12.rom_ctrl_passthru_mem_tl_intg_err.3994415411 May 09 12:37:04 PM PDT 24 May 09 12:37:43 PM PDT 24 1141044612 ps
T374 /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_mem_rw_with_rand_reset.3126696371 May 09 12:37:24 PM PDT 24 May 09 12:37:43 PM PDT 24 324295599 ps
T375 /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_errors.2732989692 May 09 12:36:45 PM PDT 24 May 09 12:37:07 PM PDT 24 3608118032 ps
T58 /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_intg_err.3334663620 May 09 12:36:45 PM PDT 24 May 09 12:38:11 PM PDT 24 12373450664 ps
T376 /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_errors.1727360312 May 09 12:36:49 PM PDT 24 May 09 12:37:15 PM PDT 24 1259436611 ps
T104 /workspace/coverage/cover_reg_top/18.rom_ctrl_passthru_mem_tl_intg_err.1423445219 May 09 12:37:31 PM PDT 24 May 09 12:38:38 PM PDT 24 12758837753 ps
T377 /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_mem_rw_with_rand_reset.33956906 May 09 12:37:10 PM PDT 24 May 09 12:37:37 PM PDT 24 485861492 ps
T378 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_mem_rw_with_rand_reset.1618395475 May 09 12:36:55 PM PDT 24 May 09 12:37:15 PM PDT 24 597467037 ps
T379 /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_errors.4103385432 May 09 12:37:06 PM PDT 24 May 09 12:37:32 PM PDT 24 1240716000 ps
T67 /workspace/coverage/cover_reg_top/7.rom_ctrl_passthru_mem_tl_intg_err.3798394427 May 09 12:36:48 PM PDT 24 May 09 12:37:17 PM PDT 24 362188741 ps
T105 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_aliasing.3506523042 May 09 12:37:04 PM PDT 24 May 09 12:37:29 PM PDT 24 7027081079 ps
T68 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_hw_reset.627986343 May 09 12:37:05 PM PDT 24 May 09 12:37:24 PM PDT 24 98498810 ps
T106 /workspace/coverage/cover_reg_top/3.rom_ctrl_passthru_mem_tl_intg_err.3535693197 May 09 12:37:10 PM PDT 24 May 09 12:38:28 PM PDT 24 15799938809 ps
T380 /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_partial_access.1558058699 May 09 12:37:00 PM PDT 24 May 09 12:37:21 PM PDT 24 1136936093 ps
T381 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_aliasing.1549875006 May 09 12:36:51 PM PDT 24 May 09 12:37:17 PM PDT 24 7246540960 ps
T112 /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_intg_err.3323034318 May 09 12:36:55 PM PDT 24 May 09 12:37:51 PM PDT 24 6055219306 ps
T69 /workspace/coverage/cover_reg_top/10.rom_ctrl_passthru_mem_tl_intg_err.508875416 May 09 12:37:21 PM PDT 24 May 09 12:38:19 PM PDT 24 2564541351 ps
T382 /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_walk.2401919436 May 09 12:36:44 PM PDT 24 May 09 12:36:58 PM PDT 24 333273842 ps
T383 /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_intg_err.3520711765 May 09 12:37:24 PM PDT 24 May 09 12:38:18 PM PDT 24 1342811852 ps
T70 /workspace/coverage/cover_reg_top/10.rom_ctrl_same_csr_outstanding.3922983874 May 09 12:37:01 PM PDT 24 May 09 12:37:35 PM PDT 24 10644472209 ps
T111 /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_intg_err.3639573280 May 09 12:37:05 PM PDT 24 May 09 12:38:26 PM PDT 24 2185059167 ps
T384 /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_errors.1952685070 May 09 12:37:05 PM PDT 24 May 09 12:37:33 PM PDT 24 6323466953 ps
T101 /workspace/coverage/cover_reg_top/1.rom_ctrl_same_csr_outstanding.3845214435 May 09 12:37:02 PM PDT 24 May 09 12:37:30 PM PDT 24 3729570005 ps
T385 /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_rw.307204295 May 09 12:36:47 PM PDT 24 May 09 12:37:13 PM PDT 24 4365405782 ps
T102 /workspace/coverage/cover_reg_top/8.rom_ctrl_passthru_mem_tl_intg_err.3095003852 May 09 12:37:00 PM PDT 24 May 09 12:38:14 PM PDT 24 25873480581 ps
T386 /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_walk.972951703 May 09 12:36:52 PM PDT 24 May 09 12:37:19 PM PDT 24 2120591199 ps
T71 /workspace/coverage/cover_reg_top/17.rom_ctrl_same_csr_outstanding.257767389 May 09 12:37:54 PM PDT 24 May 09 12:38:21 PM PDT 24 1874443728 ps
T387 /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_mem_rw_with_rand_reset.2871022194 May 09 12:37:11 PM PDT 24 May 09 12:37:32 PM PDT 24 1301941340 ps
T388 /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_mem_rw_with_rand_reset.2279320626 May 09 12:37:20 PM PDT 24 May 09 12:37:39 PM PDT 24 187277904 ps
T72 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_aliasing.2755109183 May 09 12:37:04 PM PDT 24 May 09 12:37:25 PM PDT 24 8861111244 ps
T73 /workspace/coverage/cover_reg_top/19.rom_ctrl_passthru_mem_tl_intg_err.866633846 May 09 12:37:37 PM PDT 24 May 09 12:38:22 PM PDT 24 10580979930 ps
T114 /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_intg_err.3637688003 May 09 12:37:17 PM PDT 24 May 09 12:38:17 PM PDT 24 27268475719 ps
T120 /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_intg_err.266872775 May 09 12:37:13 PM PDT 24 May 09 12:38:13 PM PDT 24 3615552160 ps
T103 /workspace/coverage/cover_reg_top/9.rom_ctrl_passthru_mem_tl_intg_err.2608922457 May 09 12:36:44 PM PDT 24 May 09 12:37:27 PM PDT 24 4972562229 ps
T389 /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_errors.78190500 May 09 12:37:10 PM PDT 24 May 09 12:37:34 PM PDT 24 2973606818 ps
T390 /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_rw.2262072585 May 09 12:36:45 PM PDT 24 May 09 12:37:00 PM PDT 24 431938965 ps
T391 /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_rw.2848257499 May 09 12:37:11 PM PDT 24 May 09 12:37:29 PM PDT 24 89181123 ps
T392 /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_partial_access.1338206728 May 09 12:36:45 PM PDT 24 May 09 12:37:08 PM PDT 24 1921850652 ps
T393 /workspace/coverage/cover_reg_top/15.rom_ctrl_passthru_mem_tl_intg_err.2344051655 May 09 12:37:02 PM PDT 24 May 09 12:37:41 PM PDT 24 558166080 ps
T394 /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_intg_err.3162667074 May 09 12:37:03 PM PDT 24 May 09 12:37:59 PM PDT 24 1383934339 ps
T80 /workspace/coverage/cover_reg_top/2.rom_ctrl_passthru_mem_tl_intg_err.4120911907 May 09 12:36:53 PM PDT 24 May 09 12:37:58 PM PDT 24 6300632892 ps
T395 /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_errors.3798824729 May 09 12:37:16 PM PDT 24 May 09 12:37:38 PM PDT 24 165464443 ps
T396 /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_errors.2187989038 May 09 12:37:07 PM PDT 24 May 09 12:37:34 PM PDT 24 3411708840 ps
T81 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_hw_reset.3031553006 May 09 12:36:58 PM PDT 24 May 09 12:37:23 PM PDT 24 1505875569 ps
T397 /workspace/coverage/cover_reg_top/5.rom_ctrl_same_csr_outstanding.3219053032 May 09 12:37:12 PM PDT 24 May 09 12:37:32 PM PDT 24 1039162542 ps
T113 /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_intg_err.2209033094 May 09 12:36:45 PM PDT 24 May 09 12:37:42 PM PDT 24 8543937257 ps
T82 /workspace/coverage/cover_reg_top/6.rom_ctrl_passthru_mem_tl_intg_err.650685256 May 09 12:37:28 PM PDT 24 May 09 12:38:41 PM PDT 24 33007853062 ps
T83 /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_rw.431729215 May 09 12:37:32 PM PDT 24 May 09 12:37:56 PM PDT 24 1441933940 ps
T398 /workspace/coverage/cover_reg_top/0.rom_ctrl_same_csr_outstanding.3280950572 May 09 12:36:47 PM PDT 24 May 09 12:37:06 PM PDT 24 1314971124 ps
T115 /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_intg_err.3312236704 May 09 12:37:03 PM PDT 24 May 09 12:38:31 PM PDT 24 7120765251 ps
T399 /workspace/coverage/cover_reg_top/19.rom_ctrl_same_csr_outstanding.2259564676 May 09 12:37:28 PM PDT 24 May 09 12:37:54 PM PDT 24 1484687494 ps
T400 /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_walk.240658882 May 09 12:36:54 PM PDT 24 May 09 12:37:18 PM PDT 24 24396388832 ps
T401 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_mem_rw_with_rand_reset.3824443898 May 09 12:36:52 PM PDT 24 May 09 12:37:14 PM PDT 24 1231705694 ps
T402 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_bit_bash.1472912616 May 09 12:37:24 PM PDT 24 May 09 12:37:43 PM PDT 24 348132295 ps
T403 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_aliasing.1717859460 May 09 12:36:46 PM PDT 24 May 09 12:37:11 PM PDT 24 18491231200 ps
T404 /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_mem_rw_with_rand_reset.3460891823 May 09 12:37:01 PM PDT 24 May 09 12:37:18 PM PDT 24 384543407 ps
T84 /workspace/coverage/cover_reg_top/13.rom_ctrl_passthru_mem_tl_intg_err.2940303224 May 09 12:37:29 PM PDT 24 May 09 12:39:02 PM PDT 24 9118834368 ps
T405 /workspace/coverage/cover_reg_top/1.rom_ctrl_passthru_mem_tl_intg_err.981255846 May 09 12:37:03 PM PDT 24 May 09 12:37:58 PM PDT 24 4359316417 ps
T117 /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_intg_err.2914993469 May 09 12:36:55 PM PDT 24 May 09 12:37:44 PM PDT 24 1247673001 ps
T406 /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_mem_rw_with_rand_reset.4211055621 May 09 12:37:04 PM PDT 24 May 09 12:37:31 PM PDT 24 1616967370 ps
T407 /workspace/coverage/cover_reg_top/15.rom_ctrl_same_csr_outstanding.4201762285 May 09 12:37:16 PM PDT 24 May 09 12:37:46 PM PDT 24 2037362299 ps
T408 /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_walk.3534044466 May 09 12:37:07 PM PDT 24 May 09 12:37:24 PM PDT 24 87087251 ps
T409 /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_errors.775961360 May 09 12:37:18 PM PDT 24 May 09 12:37:47 PM PDT 24 25498769054 ps
T410 /workspace/coverage/cover_reg_top/12.rom_ctrl_same_csr_outstanding.4017841828 May 09 12:37:14 PM PDT 24 May 09 12:37:38 PM PDT 24 347236060 ps
T411 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_bit_bash.627169013 May 09 12:37:01 PM PDT 24 May 09 12:37:17 PM PDT 24 168110081 ps
T412 /workspace/coverage/cover_reg_top/18.rom_ctrl_same_csr_outstanding.920453192 May 09 12:37:27 PM PDT 24 May 09 12:37:57 PM PDT 24 8184672368 ps
T121 /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_intg_err.62572456 May 09 12:37:21 PM PDT 24 May 09 12:38:49 PM PDT 24 1320501775 ps
T413 /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_errors.576595542 May 09 12:37:15 PM PDT 24 May 09 12:37:41 PM PDT 24 2653531228 ps
T414 /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_errors.1352932960 May 09 12:37:07 PM PDT 24 May 09 12:37:31 PM PDT 24 3597939631 ps
T415 /workspace/coverage/cover_reg_top/14.rom_ctrl_same_csr_outstanding.2881427879 May 09 12:37:24 PM PDT 24 May 09 12:37:47 PM PDT 24 864848503 ps
T416 /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_rw.582197708 May 09 12:37:04 PM PDT 24 May 09 12:37:30 PM PDT 24 1671715891 ps
T417 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_mem_rw_with_rand_reset.353368986 May 09 12:36:46 PM PDT 24 May 09 12:37:01 PM PDT 24 91303561 ps
T418 /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_mem_rw_with_rand_reset.3133664647 May 09 12:37:19 PM PDT 24 May 09 12:37:50 PM PDT 24 2125605762 ps
T419 /workspace/coverage/cover_reg_top/8.rom_ctrl_same_csr_outstanding.1648921224 May 09 12:36:55 PM PDT 24 May 09 12:37:10 PM PDT 24 415448853 ps
T420 /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_intg_err.804603795 May 09 12:37:10 PM PDT 24 May 09 12:38:36 PM PDT 24 681858489 ps
T421 /workspace/coverage/cover_reg_top/5.rom_ctrl_passthru_mem_tl_intg_err.1979204774 May 09 12:36:46 PM PDT 24 May 09 12:38:16 PM PDT 24 9946648647 ps
T422 /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_mem_rw_with_rand_reset.4263423916 May 09 12:37:11 PM PDT 24 May 09 12:37:37 PM PDT 24 2649809210 ps
T423 /workspace/coverage/cover_reg_top/7.rom_ctrl_same_csr_outstanding.3983372392 May 09 12:36:47 PM PDT 24 May 09 12:37:01 PM PDT 24 162384406 ps
T424 /workspace/coverage/cover_reg_top/13.rom_ctrl_same_csr_outstanding.2177554190 May 09 12:37:05 PM PDT 24 May 09 12:37:29 PM PDT 24 1220458735 ps
T425 /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_walk.846762260 May 09 12:36:51 PM PDT 24 May 09 12:37:15 PM PDT 24 1659986613 ps
T116 /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_intg_err.523493087 May 09 12:36:47 PM PDT 24 May 09 12:38:04 PM PDT 24 910166501 ps
T426 /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_rw.2374257508 May 09 12:37:33 PM PDT 24 May 09 12:37:53 PM PDT 24 1536009018 ps
T85 /workspace/coverage/cover_reg_top/17.rom_ctrl_passthru_mem_tl_intg_err.539946639 May 09 12:37:19 PM PDT 24 May 09 12:38:11 PM PDT 24 6066339630 ps
T427 /workspace/coverage/cover_reg_top/4.rom_ctrl_same_csr_outstanding.59910762 May 09 12:37:17 PM PDT 24 May 09 12:37:36 PM PDT 24 183063840 ps
T119 /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_intg_err.1823575905 May 09 12:36:45 PM PDT 24 May 09 12:37:40 PM PDT 24 3869522072 ps
T428 /workspace/coverage/cover_reg_top/4.rom_ctrl_passthru_mem_tl_intg_err.2631730348 May 09 12:36:54 PM PDT 24 May 09 12:38:09 PM PDT 24 7928690019 ps
T429 /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_rw.325531055 May 09 12:36:54 PM PDT 24 May 09 12:37:19 PM PDT 24 1824526669 ps
T86 /workspace/coverage/cover_reg_top/14.rom_ctrl_passthru_mem_tl_intg_err.1453075552 May 09 12:37:11 PM PDT 24 May 09 12:38:38 PM PDT 24 8321012020 ps
T430 /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_partial_access.1559856132 May 09 12:37:03 PM PDT 24 May 09 12:37:27 PM PDT 24 1705659198 ps
T431 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_bit_bash.4141078692 May 09 12:36:49 PM PDT 24 May 09 12:37:04 PM PDT 24 171384200 ps
T432 /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_mem_rw_with_rand_reset.2983129079 May 09 12:37:38 PM PDT 24 May 09 12:38:04 PM PDT 24 1808562821 ps
T433 /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_errors.732603436 May 09 12:37:02 PM PDT 24 May 09 12:37:31 PM PDT 24 4105755189 ps
T434 /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_intg_err.1830373731 May 09 12:37:06 PM PDT 24 May 09 12:38:25 PM PDT 24 1676151897 ps
T435 /workspace/coverage/cover_reg_top/16.rom_ctrl_same_csr_outstanding.3186212000 May 09 12:37:15 PM PDT 24 May 09 12:37:33 PM PDT 24 168037114 ps
T436 /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_mem_rw_with_rand_reset.4229873870 May 09 12:36:47 PM PDT 24 May 09 12:37:02 PM PDT 24 109214113 ps
T437 /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_mem_rw_with_rand_reset.948502745 May 09 12:37:12 PM PDT 24 May 09 12:37:34 PM PDT 24 509885263 ps
T438 /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_partial_access.4031418639 May 09 12:36:48 PM PDT 24 May 09 12:37:05 PM PDT 24 517886742 ps
T87 /workspace/coverage/cover_reg_top/0.rom_ctrl_passthru_mem_tl_intg_err.229468914 May 09 12:36:56 PM PDT 24 May 09 12:37:25 PM PDT 24 2102370098 ps
T439 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_aliasing.1126251193 May 09 12:36:47 PM PDT 24 May 09 12:37:10 PM PDT 24 1651892900 ps
T440 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_mem_rw_with_rand_reset.1175291476 May 09 12:37:28 PM PDT 24 May 09 12:37:51 PM PDT 24 7607710053 ps
T441 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_bit_bash.3698282119 May 09 12:37:08 PM PDT 24 May 09 12:37:37 PM PDT 24 2074604968 ps
T442 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_rw.2861255348 May 09 12:36:45 PM PDT 24 May 09 12:37:09 PM PDT 24 2585973089 ps
T443 /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_errors.2060142727 May 09 12:37:05 PM PDT 24 May 09 12:37:35 PM PDT 24 1689555298 ps
T444 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_rw.2300183573 May 09 12:37:18 PM PDT 24 May 09 12:37:46 PM PDT 24 1635398788 ps
T445 /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_mem_rw_with_rand_reset.4215121492 May 09 12:37:01 PM PDT 24 May 09 12:37:17 PM PDT 24 663586724 ps
T446 /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_intg_err.4011391295 May 09 12:37:13 PM PDT 24 May 09 12:38:39 PM PDT 24 1105582720 ps
T447 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_bit_bash.659179145 May 09 12:37:08 PM PDT 24 May 09 12:37:36 PM PDT 24 1793956506 ps
T448 /workspace/coverage/cover_reg_top/6.rom_ctrl_same_csr_outstanding.75225935 May 09 12:36:48 PM PDT 24 May 09 12:37:10 PM PDT 24 6183224022 ps
T449 /workspace/coverage/cover_reg_top/11.rom_ctrl_same_csr_outstanding.1122332270 May 09 12:37:32 PM PDT 24 May 09 12:37:56 PM PDT 24 6178380821 ps
T450 /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_rw.1592924708 May 09 12:37:37 PM PDT 24 May 09 12:38:00 PM PDT 24 2713454492 ps
T451 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_hw_reset.324933672 May 09 12:37:15 PM PDT 24 May 09 12:37:38 PM PDT 24 1372814228 ps
T452 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_mem_rw_with_rand_reset.615645363 May 09 12:36:43 PM PDT 24 May 09 12:36:57 PM PDT 24 374714745 ps
T88 /workspace/coverage/cover_reg_top/16.rom_ctrl_passthru_mem_tl_intg_err.1193914538 May 09 12:37:12 PM PDT 24 May 09 12:37:54 PM PDT 24 10765207084 ps
T453 /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_errors.4069933560 May 09 12:37:15 PM PDT 24 May 09 12:37:46 PM PDT 24 1321842251 ps
T454 /workspace/coverage/cover_reg_top/3.rom_ctrl_same_csr_outstanding.2717403967 May 09 12:37:38 PM PDT 24 May 09 12:38:01 PM PDT 24 5049286133 ps
T455 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_rw.4190409788 May 09 12:36:49 PM PDT 24 May 09 12:37:11 PM PDT 24 2228098613 ps
T456 /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_errors.1990004960 May 09 12:36:52 PM PDT 24 May 09 12:37:14 PM PDT 24 2568363227 ps
T457 /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_partial_access.4190265894 May 09 12:36:47 PM PDT 24 May 09 12:37:09 PM PDT 24 5942101835 ps
T458 /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_errors.3051706609 May 09 12:37:19 PM PDT 24 May 09 12:37:52 PM PDT 24 8212289157 ps
T459 /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_rw.3482985034 May 09 12:37:11 PM PDT 24 May 09 12:37:39 PM PDT 24 2963849373 ps
T118 /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_intg_err.247925683 May 09 12:37:13 PM PDT 24 May 09 12:38:18 PM PDT 24 8006607055 ps
T460 /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_errors.665167660 May 09 12:37:04 PM PDT 24 May 09 12:37:30 PM PDT 24 1382247092 ps
T461 /workspace/coverage/cover_reg_top/9.rom_ctrl_same_csr_outstanding.3740183051 May 09 12:37:24 PM PDT 24 May 09 12:37:50 PM PDT 24 2094494778 ps
T462 /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_intg_err.2783818707 May 09 12:37:10 PM PDT 24 May 09 12:38:35 PM PDT 24 5340321748 ps
T463 /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_rw.3406487568 May 09 12:37:03 PM PDT 24 May 09 12:37:20 PM PDT 24 863901920 ps
T464 /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_rw.1262242235 May 09 12:36:53 PM PDT 24 May 09 12:37:18 PM PDT 24 1648694593 ps
T465 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_hw_reset.4099454004 May 09 12:37:00 PM PDT 24 May 09 12:37:24 PM PDT 24 2074499675 ps
T89 /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_rw.3320756623 May 09 12:36:50 PM PDT 24 May 09 12:37:07 PM PDT 24 1644325989 ps
T466 /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_rw.3372457391 May 09 12:36:46 PM PDT 24 May 09 12:37:11 PM PDT 24 1732751818 ps
T467 /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_errors.3858074995 May 09 12:36:47 PM PDT 24 May 09 12:37:05 PM PDT 24 103049265 ps
T468 /workspace/coverage/cover_reg_top/2.rom_ctrl_same_csr_outstanding.3403128735 May 09 12:37:01 PM PDT 24 May 09 12:37:28 PM PDT 24 3824286103 ps
T469 /workspace/coverage/cover_reg_top/11.rom_ctrl_passthru_mem_tl_intg_err.212808502 May 09 12:37:14 PM PDT 24 May 09 12:38:33 PM PDT 24 8539735726 ps
T470 /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_mem_rw_with_rand_reset.1409132118 May 09 12:36:47 PM PDT 24 May 09 12:37:02 PM PDT 24 560887108 ps
T471 /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_errors.3149949733 May 09 12:37:21 PM PDT 24 May 09 12:37:46 PM PDT 24 256534181 ps

Test location /workspace/coverage/default/29.rom_ctrl_stress_all_with_rand_reset.2974095298
Short name T6
Test name
Test status
Simulation time 33242690771 ps
CPU time 629.6 seconds
Started May 09 12:37:55 PM PDT 24
Finished May 09 12:48:38 PM PDT 24
Peak memory 228760 kb
Host smart-39c5cb2e-6acd-4ba7-82ff-1c5f008a1f5b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2974095298 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_stress_all_with_rand_reset.2974095298
Directory /workspace/29.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.rom_ctrl_corrupt_sig_fatal_chk.733253599
Short name T7
Test name
Test status
Simulation time 9614514002 ps
CPU time 135.32 seconds
Started May 09 12:37:15 PM PDT 24
Finished May 09 12:39:44 PM PDT 24
Peak memory 237808 kb
Host smart-6490087c-48f8-43bd-a430-5c53d1743182
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=733253599 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_c
orrupt_sig_fatal_chk.733253599
Directory /workspace/10.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/46.rom_ctrl_corrupt_sig_fatal_chk.648641479
Short name T27
Test name
Test status
Simulation time 37697596128 ps
CPU time 378.55 seconds
Started May 09 12:38:06 PM PDT 24
Finished May 09 12:44:41 PM PDT 24
Peak memory 233460 kb
Host smart-033487cb-dfd8-4a9d-ac02-959272d3d765
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=648641479 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_c
orrupt_sig_fatal_chk.648641479
Directory /workspace/46.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_intg_err.3705201876
Short name T57
Test name
Test status
Simulation time 6717021433 ps
CPU time 46.49 seconds
Started May 09 12:37:05 PM PDT 24
Finished May 09 12:38:03 PM PDT 24
Peak memory 211832 kb
Host smart-eb853dbb-35be-4290-ae42-ef8468483ac9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3705201876 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_tl_i
ntg_err.3705201876
Directory /workspace/18.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/27.rom_ctrl_smoke.977063865
Short name T9
Test name
Test status
Simulation time 1065711026 ps
CPU time 16.35 seconds
Started May 09 12:37:32 PM PDT 24
Finished May 09 12:38:00 PM PDT 24
Peak memory 213960 kb
Host smart-94445d05-5d70-46d4-84d9-8380d7cbd6df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=977063865 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_smoke.977063865
Directory /workspace/27.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/3.rom_ctrl_sec_cm.2936813462
Short name T29
Test name
Test status
Simulation time 1976221244 ps
CPU time 97.96 seconds
Started May 09 12:38:26 PM PDT 24
Finished May 09 12:40:21 PM PDT 24
Peak memory 238340 kb
Host smart-2f9c3729-dc38-4590-9b42-82558e3db4c6
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2936813462 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_sec_cm.2936813462
Directory /workspace/3.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_passthru_mem_tl_intg_err.3994415411
Short name T66
Test name
Test status
Simulation time 1141044612 ps
CPU time 27.61 seconds
Started May 09 12:37:04 PM PDT 24
Finished May 09 12:37:43 PM PDT 24
Peak memory 210800 kb
Host smart-a49f9437-9393-4968-90fd-98cf6314c6e5
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3994415411 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_p
assthru_mem_tl_intg_err.3994415411
Directory /workspace/12.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_intg_err.3637688003
Short name T114
Test name
Test status
Simulation time 27268475719 ps
CPU time 46.09 seconds
Started May 09 12:37:17 PM PDT 24
Finished May 09 12:38:17 PM PDT 24
Peak memory 211692 kb
Host smart-b30bae38-db36-4f5e-aca7-60eb912cfe00
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3637688003 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_tl_in
tg_err.3637688003
Directory /workspace/8.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_intg_err.247925683
Short name T118
Test name
Test status
Simulation time 8006607055 ps
CPU time 46.15 seconds
Started May 09 12:37:13 PM PDT 24
Finished May 09 12:38:18 PM PDT 24
Peak memory 211740 kb
Host smart-7c9b34ef-47b3-4f85-aa77-f1da43d81b56
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=247925683 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_tl_int
g_err.247925683
Directory /workspace/6.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/10.rom_ctrl_alert_test.2537663981
Short name T62
Test name
Test status
Simulation time 2139872436 ps
CPU time 16.77 seconds
Started May 09 12:37:36 PM PDT 24
Finished May 09 12:38:04 PM PDT 24
Peak memory 211724 kb
Host smart-bab7be27-0cd2-4696-87e6-ff854f9e9640
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2537663981 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_alert_test.2537663981
Directory /workspace/10.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/37.rom_ctrl_smoke.2127011679
Short name T146
Test name
Test status
Simulation time 6751380258 ps
CPU time 40.26 seconds
Started May 09 12:37:32 PM PDT 24
Finished May 09 12:38:24 PM PDT 24
Peak memory 214440 kb
Host smart-f1d352bd-5af8-4b1f-9557-0375491c4bdd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2127011679 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_smoke.2127011679
Directory /workspace/37.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/0.rom_ctrl_kmac_err_chk.1928085485
Short name T26
Test name
Test status
Simulation time 6504693707 ps
CPU time 27.04 seconds
Started May 09 12:37:22 PM PDT 24
Finished May 09 12:38:04 PM PDT 24
Peak memory 213212 kb
Host smart-18c755fa-1d7d-4567-ac7a-e63788acb2ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1928085485 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_kmac_err_chk.1928085485
Directory /workspace/0.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/26.rom_ctrl_kmac_err_chk.3953143138
Short name T252
Test name
Test status
Simulation time 593397705 ps
CPU time 9.24 seconds
Started May 09 12:37:34 PM PDT 24
Finished May 09 12:37:55 PM PDT 24
Peak memory 212228 kb
Host smart-c0ec5140-5ea2-4d1a-85a6-fcc39bd54391
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3953143138 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_kmac_err_chk.3953143138
Directory /workspace/26.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_passthru_mem_tl_intg_err.3095003852
Short name T102
Test name
Test status
Simulation time 25873480581 ps
CPU time 62.88 seconds
Started May 09 12:37:00 PM PDT 24
Finished May 09 12:38:14 PM PDT 24
Peak memory 210928 kb
Host smart-f31c47aa-5ede-41ea-a636-0e41f8e4e5bf
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3095003852 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_pa
ssthru_mem_tl_intg_err.3095003852
Directory /workspace/8.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/default/17.rom_ctrl_stress_all.4033062016
Short name T16
Test name
Test status
Simulation time 1031469659 ps
CPU time 20.72 seconds
Started May 09 12:37:32 PM PDT 24
Finished May 09 12:38:05 PM PDT 24
Peak memory 219840 kb
Host smart-4013531e-f290-425e-9ffe-b5d330cc42d5
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4033062016 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 17.rom_ctrl_stress_all.4033062016
Directory /workspace/17.rom_ctrl_stress_all/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_intg_err.3334663620
Short name T58
Test name
Test status
Simulation time 12373450664 ps
CPU time 76.45 seconds
Started May 09 12:36:45 PM PDT 24
Finished May 09 12:38:11 PM PDT 24
Peak memory 212084 kb
Host smart-f2e19110-c6ec-4b2e-84a7-7f4f0dd12b8b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3334663620 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_tl_in
tg_err.3334663620
Directory /workspace/4.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_passthru_mem_tl_intg_err.2940303224
Short name T84
Test name
Test status
Simulation time 9118834368 ps
CPU time 80.91 seconds
Started May 09 12:37:29 PM PDT 24
Finished May 09 12:39:02 PM PDT 24
Peak memory 210940 kb
Host smart-f2ceedf0-7280-43bb-b001-7c5c592161c4
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2940303224 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_p
assthru_mem_tl_intg_err.2940303224
Directory /workspace/13.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/default/12.rom_ctrl_max_throughput_chk.3918817606
Short name T90
Test name
Test status
Simulation time 1991930178 ps
CPU time 16.08 seconds
Started May 09 12:37:17 PM PDT 24
Finished May 09 12:37:47 PM PDT 24
Peak memory 211644 kb
Host smart-60b4ff24-b796-4d08-8277-f6efd51bb9c4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3918817606 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_max_throughput_chk.3918817606
Directory /workspace/12.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/13.rom_ctrl_stress_all_with_rand_reset.1817355840
Short name T20
Test name
Test status
Simulation time 220224489057 ps
CPU time 1155.45 seconds
Started May 09 12:37:23 PM PDT 24
Finished May 09 12:56:53 PM PDT 24
Peak memory 232212 kb
Host smart-1c5deb7d-6705-4f0b-9420-83e78f1f4243
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1817355840 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_stress_all_with_rand_reset.1817355840
Directory /workspace/13.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/15.rom_ctrl_smoke.511685980
Short name T156
Test name
Test status
Simulation time 3860976074 ps
CPU time 31.91 seconds
Started May 09 12:37:29 PM PDT 24
Finished May 09 12:38:13 PM PDT 24
Peak memory 214176 kb
Host smart-3ee345b8-fc64-4a65-bee8-de221dc5dc03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=511685980 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_smoke.511685980
Directory /workspace/15.rom_ctrl_smoke/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_aliasing.1549875006
Short name T381
Test name
Test status
Simulation time 7246540960 ps
CPU time 15.14 seconds
Started May 09 12:36:51 PM PDT 24
Finished May 09 12:37:17 PM PDT 24
Peak memory 210848 kb
Host smart-89cdbb3f-b22e-4ea7-a699-83dbe63972ef
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1549875006 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_alia
sing.1549875006
Directory /workspace/0.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_bit_bash.1472912616
Short name T402
Test name
Test status
Simulation time 348132295 ps
CPU time 4.33 seconds
Started May 09 12:37:24 PM PDT 24
Finished May 09 12:37:43 PM PDT 24
Peak memory 210828 kb
Host smart-be3fa48e-028b-433b-880f-0782218f0647
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1472912616 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_bit_
bash.1472912616
Directory /workspace/0.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_hw_reset.324933672
Short name T451
Test name
Test status
Simulation time 1372814228 ps
CPU time 8.04 seconds
Started May 09 12:37:15 PM PDT 24
Finished May 09 12:37:38 PM PDT 24
Peak memory 210836 kb
Host smart-3a664e2c-91eb-4849-b9be-75a66149936a
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=324933672 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_hw_re
set.324933672
Directory /workspace/0.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_mem_rw_with_rand_reset.615645363
Short name T452
Test name
Test status
Simulation time 374714745 ps
CPU time 4.71 seconds
Started May 09 12:36:43 PM PDT 24
Finished May 09 12:36:57 PM PDT 24
Peak memory 219084 kb
Host smart-5bf63884-2265-4fcc-b238-75c28b90baed
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=615645363 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 0.rom_ctrl_csr_mem_rw_with_rand_reset.615645363
Directory /workspace/0.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_rw.2354049739
Short name T65
Test name
Test status
Simulation time 7376635076 ps
CPU time 14.15 seconds
Started May 09 12:36:37 PM PDT 24
Finished May 09 12:36:58 PM PDT 24
Peak memory 210952 kb
Host smart-72db3af7-03bd-4527-8eea-ea62d49ae77e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2354049739 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_rw.2354049739
Directory /workspace/0.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_partial_access.1558058699
Short name T380
Test name
Test status
Simulation time 1136936093 ps
CPU time 10.53 seconds
Started May 09 12:37:00 PM PDT 24
Finished May 09 12:37:21 PM PDT 24
Peak memory 210616 kb
Host smart-e3864876-dee2-4d45-bc7b-919c32a35942
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1558058699 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctr
l_mem_partial_access.1558058699
Directory /workspace/0.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_walk.3534044466
Short name T408
Test name
Test status
Simulation time 87087251 ps
CPU time 4.07 seconds
Started May 09 12:37:07 PM PDT 24
Finished May 09 12:37:24 PM PDT 24
Peak memory 210844 kb
Host smart-f2e413c5-ad7d-4ca7-a170-376ab0dc0b1b
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3534044466 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_mem_walk
.3534044466
Directory /workspace/0.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_passthru_mem_tl_intg_err.229468914
Short name T87
Test name
Test status
Simulation time 2102370098 ps
CPU time 18.86 seconds
Started May 09 12:36:56 PM PDT 24
Finished May 09 12:37:25 PM PDT 24
Peak memory 210868 kb
Host smart-21393c69-9d8c-4327-bfa3-5c04f5940051
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=229468914 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_pas
sthru_mem_tl_intg_err.229468914
Directory /workspace/0.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_same_csr_outstanding.3280950572
Short name T398
Test name
Test status
Simulation time 1314971124 ps
CPU time 8.37 seconds
Started May 09 12:36:47 PM PDT 24
Finished May 09 12:37:06 PM PDT 24
Peak memory 210876 kb
Host smart-6f545b9b-aeb2-4578-ba94-3feaa9db2001
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3280950572 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_c
trl_same_csr_outstanding.3280950572
Directory /workspace/0.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_errors.732603436
Short name T433
Test name
Test status
Simulation time 4105755189 ps
CPU time 17.24 seconds
Started May 09 12:37:02 PM PDT 24
Finished May 09 12:37:31 PM PDT 24
Peak memory 216212 kb
Host smart-f4f94fb2-3383-4def-8f68-f6c6ba9aa69a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=732603436 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_tl_errors.732603436
Directory /workspace/0.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_intg_err.218871370
Short name T56
Test name
Test status
Simulation time 2411539091 ps
CPU time 72.57 seconds
Started May 09 12:37:00 PM PDT 24
Finished May 09 12:38:23 PM PDT 24
Peak memory 212696 kb
Host smart-32a84613-128c-4615-98b9-d6b397d624a3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=218871370 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_tl_int
g_err.218871370
Directory /workspace/0.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_aliasing.3506523042
Short name T105
Test name
Test status
Simulation time 7027081079 ps
CPU time 13.87 seconds
Started May 09 12:37:04 PM PDT 24
Finished May 09 12:37:29 PM PDT 24
Peak memory 218848 kb
Host smart-764a8a7f-a62f-4d08-a1b4-7945a2572da6
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3506523042 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_alia
sing.3506523042
Directory /workspace/1.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_bit_bash.4141078692
Short name T431
Test name
Test status
Simulation time 171384200 ps
CPU time 4.62 seconds
Started May 09 12:36:49 PM PDT 24
Finished May 09 12:37:04 PM PDT 24
Peak memory 210772 kb
Host smart-ac9ca8d6-14c4-4b87-b262-3fe11371949b
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4141078692 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_bit_
bash.4141078692
Directory /workspace/1.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_hw_reset.627986343
Short name T68
Test name
Test status
Simulation time 98498810 ps
CPU time 7.4 seconds
Started May 09 12:37:05 PM PDT 24
Finished May 09 12:37:24 PM PDT 24
Peak memory 210952 kb
Host smart-144f4440-75af-4b49-93f5-600902ea56fe
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=627986343 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_hw_re
set.627986343
Directory /workspace/1.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_mem_rw_with_rand_reset.3824443898
Short name T401
Test name
Test status
Simulation time 1231705694 ps
CPU time 11.97 seconds
Started May 09 12:36:52 PM PDT 24
Finished May 09 12:37:14 PM PDT 24
Peak memory 215596 kb
Host smart-d8a20fd3-0918-4f44-8121-68631086ac3d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3824443898 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 1.rom_ctrl_csr_mem_rw_with_rand_reset.3824443898
Directory /workspace/1.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_rw.2300183573
Short name T444
Test name
Test status
Simulation time 1635398788 ps
CPU time 13.76 seconds
Started May 09 12:37:18 PM PDT 24
Finished May 09 12:37:46 PM PDT 24
Peak memory 210872 kb
Host smart-678d10fb-7b95-45e2-8925-01e42175ecea
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2300183573 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_rw.2300183573
Directory /workspace/1.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_partial_access.4031418639
Short name T438
Test name
Test status
Simulation time 517886742 ps
CPU time 7.41 seconds
Started May 09 12:36:48 PM PDT 24
Finished May 09 12:37:05 PM PDT 24
Peak memory 210760 kb
Host smart-2b764bed-8e3f-4681-a688-dacca4137aee
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4031418639 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctr
l_mem_partial_access.4031418639
Directory /workspace/1.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_walk.972951703
Short name T386
Test name
Test status
Simulation time 2120591199 ps
CPU time 15.86 seconds
Started May 09 12:36:52 PM PDT 24
Finished May 09 12:37:19 PM PDT 24
Peak memory 210816 kb
Host smart-3c8414b6-4d4c-4223-94a1-34d5b5aa3a26
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=972951703 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_mem_walk.
972951703
Directory /workspace/1.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_passthru_mem_tl_intg_err.981255846
Short name T405
Test name
Test status
Simulation time 4359316417 ps
CPU time 43.35 seconds
Started May 09 12:37:03 PM PDT 24
Finished May 09 12:37:58 PM PDT 24
Peak memory 210964 kb
Host smart-213b9a61-05d2-47e8-ab16-5a96713672c9
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=981255846 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_pas
sthru_mem_tl_intg_err.981255846
Directory /workspace/1.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_same_csr_outstanding.3845214435
Short name T101
Test name
Test status
Simulation time 3729570005 ps
CPU time 16.32 seconds
Started May 09 12:37:02 PM PDT 24
Finished May 09 12:37:30 PM PDT 24
Peak memory 210940 kb
Host smart-a100065b-2dd7-4c36-8aba-731a39687fed
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3845214435 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_c
trl_same_csr_outstanding.3845214435
Directory /workspace/1.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_errors.4103385432
Short name T379
Test name
Test status
Simulation time 1240716000 ps
CPU time 13.8 seconds
Started May 09 12:37:06 PM PDT 24
Finished May 09 12:37:32 PM PDT 24
Peak memory 219140 kb
Host smart-bfa14d00-2169-49af-a017-1b94af6c799e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4103385432 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_tl_errors.4103385432
Directory /workspace/1.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_intg_err.2209033094
Short name T113
Test name
Test status
Simulation time 8543937257 ps
CPU time 47.08 seconds
Started May 09 12:36:45 PM PDT 24
Finished May 09 12:37:42 PM PDT 24
Peak memory 212184 kb
Host smart-ff0dbd02-3668-489d-bd18-a26f9686c664
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2209033094 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_tl_in
tg_err.2209033094
Directory /workspace/1.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_mem_rw_with_rand_reset.3126696371
Short name T374
Test name
Test status
Simulation time 324295599 ps
CPU time 5.36 seconds
Started May 09 12:37:24 PM PDT 24
Finished May 09 12:37:43 PM PDT 24
Peak memory 219036 kb
Host smart-057e8a03-9fcb-45ac-ab25-9c8854eac66c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3126696371 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 10.rom_ctrl_csr_mem_rw_with_rand_reset.3126696371
Directory /workspace/10.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_rw.3482985034
Short name T459
Test name
Test status
Simulation time 2963849373 ps
CPU time 14.19 seconds
Started May 09 12:37:11 PM PDT 24
Finished May 09 12:37:39 PM PDT 24
Peak memory 210928 kb
Host smart-fb5f613c-2318-49d1-8d7a-d1bbe1e49103
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3482985034 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_csr_rw.3482985034
Directory /workspace/10.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_passthru_mem_tl_intg_err.508875416
Short name T69
Test name
Test status
Simulation time 2564541351 ps
CPU time 43.17 seconds
Started May 09 12:37:21 PM PDT 24
Finished May 09 12:38:19 PM PDT 24
Peak memory 210964 kb
Host smart-9062ccc7-96a3-406f-805b-22b9d2d04d9d
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=508875416 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_pa
ssthru_mem_tl_intg_err.508875416
Directory /workspace/10.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_same_csr_outstanding.3922983874
Short name T70
Test name
Test status
Simulation time 10644472209 ps
CPU time 17.04 seconds
Started May 09 12:37:01 PM PDT 24
Finished May 09 12:37:35 PM PDT 24
Peak memory 210952 kb
Host smart-32244616-e068-47de-a833-c132a5f0a2b8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3922983874 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_
ctrl_same_csr_outstanding.3922983874
Directory /workspace/10.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_errors.3051706609
Short name T458
Test name
Test status
Simulation time 8212289157 ps
CPU time 18.32 seconds
Started May 09 12:37:19 PM PDT 24
Finished May 09 12:37:52 PM PDT 24
Peak memory 219220 kb
Host smart-2195ea6e-3550-4871-adf9-a7872e219615
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3051706609 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_tl_errors.3051706609
Directory /workspace/10.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_intg_err.804603795
Short name T420
Test name
Test status
Simulation time 681858489 ps
CPU time 70.97 seconds
Started May 09 12:37:10 PM PDT 24
Finished May 09 12:38:36 PM PDT 24
Peak memory 211736 kb
Host smart-fc9ba58d-3953-400b-b254-5f0582b161c7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=804603795 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_tl_in
tg_err.804603795
Directory /workspace/10.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_mem_rw_with_rand_reset.2279320626
Short name T388
Test name
Test status
Simulation time 187277904 ps
CPU time 4.73 seconds
Started May 09 12:37:20 PM PDT 24
Finished May 09 12:37:39 PM PDT 24
Peak memory 219048 kb
Host smart-b8fa7aef-96a4-4db5-8a9c-581ed99fe440
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2279320626 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 11.rom_ctrl_csr_mem_rw_with_rand_reset.2279320626
Directory /workspace/11.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_rw.3143802226
Short name T60
Test name
Test status
Simulation time 3002810779 ps
CPU time 8.97 seconds
Started May 09 12:37:05 PM PDT 24
Finished May 09 12:37:26 PM PDT 24
Peak memory 210948 kb
Host smart-fb38fcdc-8c0a-440e-9008-c2588e8e0aa0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3143802226 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_csr_rw.3143802226
Directory /workspace/11.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_passthru_mem_tl_intg_err.212808502
Short name T469
Test name
Test status
Simulation time 8539735726 ps
CPU time 64.55 seconds
Started May 09 12:37:14 PM PDT 24
Finished May 09 12:38:33 PM PDT 24
Peak memory 210872 kb
Host smart-dc25f705-f3e5-4932-93ea-08b199fe49cc
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=212808502 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_pa
ssthru_mem_tl_intg_err.212808502
Directory /workspace/11.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_same_csr_outstanding.1122332270
Short name T449
Test name
Test status
Simulation time 6178380821 ps
CPU time 12.77 seconds
Started May 09 12:37:32 PM PDT 24
Finished May 09 12:37:56 PM PDT 24
Peak memory 210980 kb
Host smart-ec4556fd-d8fe-4786-b6b7-a2cd06af478b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1122332270 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_
ctrl_same_csr_outstanding.1122332270
Directory /workspace/11.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_errors.2060142727
Short name T443
Test name
Test status
Simulation time 1689555298 ps
CPU time 17.74 seconds
Started May 09 12:37:05 PM PDT 24
Finished May 09 12:37:35 PM PDT 24
Peak memory 219100 kb
Host smart-d639e360-a948-4c41-97b7-3f3551c7a066
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2060142727 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_tl_errors.2060142727
Directory /workspace/11.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_intg_err.266872775
Short name T120
Test name
Test status
Simulation time 3615552160 ps
CPU time 45.77 seconds
Started May 09 12:37:13 PM PDT 24
Finished May 09 12:38:13 PM PDT 24
Peak memory 219100 kb
Host smart-6b1cc678-c0f3-4f91-a12a-705e059b28af
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=266872775 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_tl_in
tg_err.266872775
Directory /workspace/11.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_mem_rw_with_rand_reset.4211055621
Short name T406
Test name
Test status
Simulation time 1616967370 ps
CPU time 14.32 seconds
Started May 09 12:37:04 PM PDT 24
Finished May 09 12:37:31 PM PDT 24
Peak memory 219084 kb
Host smart-66d44873-d1b2-4893-831d-cfd6a10a781c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4211055621 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 12.rom_ctrl_csr_mem_rw_with_rand_reset.4211055621
Directory /workspace/12.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_rw.2848257499
Short name T391
Test name
Test status
Simulation time 89181123 ps
CPU time 4.29 seconds
Started May 09 12:37:11 PM PDT 24
Finished May 09 12:37:29 PM PDT 24
Peak memory 211152 kb
Host smart-9be6bc10-83c8-4e29-91ba-b8770d231bd0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2848257499 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_csr_rw.2848257499
Directory /workspace/12.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_same_csr_outstanding.4017841828
Short name T410
Test name
Test status
Simulation time 347236060 ps
CPU time 4.41 seconds
Started May 09 12:37:14 PM PDT 24
Finished May 09 12:37:38 PM PDT 24
Peak memory 211132 kb
Host smart-f2ff2e66-ca58-48e6-b8d7-19a8f6a9adff
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4017841828 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_
ctrl_same_csr_outstanding.4017841828
Directory /workspace/12.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_errors.775961360
Short name T409
Test name
Test status
Simulation time 25498769054 ps
CPU time 14.71 seconds
Started May 09 12:37:18 PM PDT 24
Finished May 09 12:37:47 PM PDT 24
Peak memory 219168 kb
Host smart-df3b7cfe-cd76-4a18-89e5-5d05939f4ea7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=775961360 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_tl_errors.775961360
Directory /workspace/12.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_intg_err.3312236704
Short name T115
Test name
Test status
Simulation time 7120765251 ps
CPU time 76.56 seconds
Started May 09 12:37:03 PM PDT 24
Finished May 09 12:38:31 PM PDT 24
Peak memory 219112 kb
Host smart-6abbdb42-8df9-4727-933b-bcc9dbc36cf0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3312236704 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_tl_i
ntg_err.3312236704
Directory /workspace/12.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_mem_rw_with_rand_reset.4215121492
Short name T445
Test name
Test status
Simulation time 663586724 ps
CPU time 5.45 seconds
Started May 09 12:37:01 PM PDT 24
Finished May 09 12:37:17 PM PDT 24
Peak memory 212712 kb
Host smart-96b8f13d-37ed-437a-ab0c-efee2b12cc7a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4215121492 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 13.rom_ctrl_csr_mem_rw_with_rand_reset.4215121492
Directory /workspace/13.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_rw.1879278328
Short name T100
Test name
Test status
Simulation time 15374624200 ps
CPU time 16.19 seconds
Started May 09 12:37:18 PM PDT 24
Finished May 09 12:37:48 PM PDT 24
Peak memory 210968 kb
Host smart-6aab79bf-5b53-4313-8b2c-be84da93d9cb
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1879278328 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_csr_rw.1879278328
Directory /workspace/13.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_same_csr_outstanding.2177554190
Short name T424
Test name
Test status
Simulation time 1220458735 ps
CPU time 12.2 seconds
Started May 09 12:37:05 PM PDT 24
Finished May 09 12:37:29 PM PDT 24
Peak memory 210896 kb
Host smart-a6eb08cf-7660-47f1-934e-a48f2b6f4b0b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2177554190 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_
ctrl_same_csr_outstanding.2177554190
Directory /workspace/13.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_errors.3798824729
Short name T395
Test name
Test status
Simulation time 165464443 ps
CPU time 8.18 seconds
Started May 09 12:37:16 PM PDT 24
Finished May 09 12:37:38 PM PDT 24
Peak memory 219128 kb
Host smart-65460f73-785d-4f0e-995a-4a241aac36f1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3798824729 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_tl_errors.3798824729
Directory /workspace/13.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_intg_err.62572456
Short name T121
Test name
Test status
Simulation time 1320501775 ps
CPU time 73.31 seconds
Started May 09 12:37:21 PM PDT 24
Finished May 09 12:38:49 PM PDT 24
Peak memory 211876 kb
Host smart-271ef2f9-3a73-4f5e-ac99-3af19e12626a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=62572456 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_tl_int
g_err.62572456
Directory /workspace/13.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_mem_rw_with_rand_reset.33956906
Short name T377
Test name
Test status
Simulation time 485861492 ps
CPU time 8.04 seconds
Started May 09 12:37:10 PM PDT 24
Finished May 09 12:37:37 PM PDT 24
Peak memory 215136 kb
Host smart-ac2b174b-b70c-4107-b2e7-b6cb3c2bf274
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33956906 -assert nopostproc +UVM_TESTNAME=r
om_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 14.rom_ctrl_csr_mem_rw_with_rand_reset.33956906
Directory /workspace/14.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_rw.325531055
Short name T429
Test name
Test status
Simulation time 1824526669 ps
CPU time 14.21 seconds
Started May 09 12:36:54 PM PDT 24
Finished May 09 12:37:19 PM PDT 24
Peak memory 210828 kb
Host smart-a0fb922f-60d1-4eed-b6ba-edf3d39f8fee
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=325531055 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_csr_rw.325531055
Directory /workspace/14.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_passthru_mem_tl_intg_err.1453075552
Short name T86
Test name
Test status
Simulation time 8321012020 ps
CPU time 72.84 seconds
Started May 09 12:37:11 PM PDT 24
Finished May 09 12:38:38 PM PDT 24
Peak memory 210980 kb
Host smart-65ab251f-4b85-4399-9137-31ffb2880e43
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1453075552 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_p
assthru_mem_tl_intg_err.1453075552
Directory /workspace/14.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_same_csr_outstanding.2881427879
Short name T415
Test name
Test status
Simulation time 864848503 ps
CPU time 9.26 seconds
Started May 09 12:37:24 PM PDT 24
Finished May 09 12:37:47 PM PDT 24
Peak memory 210900 kb
Host smart-aa7a25ce-08f1-43d4-9775-c9bebccdca5e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2881427879 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_
ctrl_same_csr_outstanding.2881427879
Directory /workspace/14.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_errors.1952685070
Short name T384
Test name
Test status
Simulation time 6323466953 ps
CPU time 16.47 seconds
Started May 09 12:37:05 PM PDT 24
Finished May 09 12:37:33 PM PDT 24
Peak memory 216584 kb
Host smart-ac7a34dc-7596-4530-8a08-d7adb854130d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1952685070 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_tl_errors.1952685070
Directory /workspace/14.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_intg_err.4011391295
Short name T446
Test name
Test status
Simulation time 1105582720 ps
CPU time 71.3 seconds
Started May 09 12:37:13 PM PDT 24
Finished May 09 12:38:39 PM PDT 24
Peak memory 211944 kb
Host smart-300f2b0a-98e6-4227-ae2c-7d964e39bb9e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4011391295 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_tl_i
ntg_err.4011391295
Directory /workspace/14.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_mem_rw_with_rand_reset.2871022194
Short name T387
Test name
Test status
Simulation time 1301941340 ps
CPU time 6.89 seconds
Started May 09 12:37:11 PM PDT 24
Finished May 09 12:37:32 PM PDT 24
Peak memory 219052 kb
Host smart-aadbd3e4-9964-4bb2-be95-90367e29b986
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2871022194 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 15.rom_ctrl_csr_mem_rw_with_rand_reset.2871022194
Directory /workspace/15.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_rw.1262242235
Short name T464
Test name
Test status
Simulation time 1648694593 ps
CPU time 13.91 seconds
Started May 09 12:36:53 PM PDT 24
Finished May 09 12:37:18 PM PDT 24
Peak memory 210860 kb
Host smart-5c5089fe-747e-424e-8712-1a642dd38637
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1262242235 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_csr_rw.1262242235
Directory /workspace/15.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_passthru_mem_tl_intg_err.2344051655
Short name T393
Test name
Test status
Simulation time 558166080 ps
CPU time 27.94 seconds
Started May 09 12:37:02 PM PDT 24
Finished May 09 12:37:41 PM PDT 24
Peak memory 210824 kb
Host smart-f1b530ad-8dca-4d14-858b-636e057f5882
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2344051655 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_p
assthru_mem_tl_intg_err.2344051655
Directory /workspace/15.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_same_csr_outstanding.4201762285
Short name T407
Test name
Test status
Simulation time 2037362299 ps
CPU time 15.01 seconds
Started May 09 12:37:16 PM PDT 24
Finished May 09 12:37:46 PM PDT 24
Peak memory 210908 kb
Host smart-e4645a24-3188-4ff4-9868-75ae18d8d138
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4201762285 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_
ctrl_same_csr_outstanding.4201762285
Directory /workspace/15.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_errors.78190500
Short name T389
Test name
Test status
Simulation time 2973606818 ps
CPU time 10.71 seconds
Started May 09 12:37:10 PM PDT 24
Finished May 09 12:37:34 PM PDT 24
Peak memory 215604 kb
Host smart-c412b0ec-faa5-4a0f-a0db-b912ddc15fda
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78190500 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_tl_errors.78190500
Directory /workspace/15.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_intg_err.3162667074
Short name T394
Test name
Test status
Simulation time 1383934339 ps
CPU time 43.66 seconds
Started May 09 12:37:03 PM PDT 24
Finished May 09 12:37:59 PM PDT 24
Peak memory 211576 kb
Host smart-a389db7c-5ce7-4242-8ea5-e7539d2098a6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3162667074 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_tl_i
ntg_err.3162667074
Directory /workspace/15.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_mem_rw_with_rand_reset.3133664647
Short name T418
Test name
Test status
Simulation time 2125605762 ps
CPU time 15.78 seconds
Started May 09 12:37:19 PM PDT 24
Finished May 09 12:37:50 PM PDT 24
Peak memory 214904 kb
Host smart-0cf8b5f4-d481-4e79-9d2a-a7c9f9baa07e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3133664647 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 16.rom_ctrl_csr_mem_rw_with_rand_reset.3133664647
Directory /workspace/16.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_rw.431729215
Short name T83
Test name
Test status
Simulation time 1441933940 ps
CPU time 12.01 seconds
Started May 09 12:37:32 PM PDT 24
Finished May 09 12:37:56 PM PDT 24
Peak memory 210944 kb
Host smart-182b61a6-edd5-48c7-97ec-ac84ba847453
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=431729215 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_csr_rw.431729215
Directory /workspace/16.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_passthru_mem_tl_intg_err.1193914538
Short name T88
Test name
Test status
Simulation time 10765207084 ps
CPU time 27.71 seconds
Started May 09 12:37:12 PM PDT 24
Finished May 09 12:37:54 PM PDT 24
Peak memory 210952 kb
Host smart-84b092f9-1680-4361-b623-a43b670a65b7
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1193914538 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_p
assthru_mem_tl_intg_err.1193914538
Directory /workspace/16.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_same_csr_outstanding.3186212000
Short name T435
Test name
Test status
Simulation time 168037114 ps
CPU time 4.21 seconds
Started May 09 12:37:15 PM PDT 24
Finished May 09 12:37:33 PM PDT 24
Peak memory 210880 kb
Host smart-31ab0a46-40ff-498d-a7d4-6b2e49da3a76
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3186212000 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_
ctrl_same_csr_outstanding.3186212000
Directory /workspace/16.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_errors.3149949733
Short name T471
Test name
Test status
Simulation time 256534181 ps
CPU time 9.82 seconds
Started May 09 12:37:21 PM PDT 24
Finished May 09 12:37:46 PM PDT 24
Peak memory 215432 kb
Host smart-fe59f276-c01b-4b76-b42a-23ff4b54ea24
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3149949733 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_tl_errors.3149949733
Directory /workspace/16.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_intg_err.3323034318
Short name T112
Test name
Test status
Simulation time 6055219306 ps
CPU time 45.37 seconds
Started May 09 12:36:55 PM PDT 24
Finished May 09 12:37:51 PM PDT 24
Peak memory 211964 kb
Host smart-694f6e10-bb32-4b49-b650-817ef804b652
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3323034318 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_tl_i
ntg_err.3323034318
Directory /workspace/16.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_mem_rw_with_rand_reset.3460891823
Short name T404
Test name
Test status
Simulation time 384543407 ps
CPU time 5.01 seconds
Started May 09 12:37:01 PM PDT 24
Finished May 09 12:37:18 PM PDT 24
Peak memory 215292 kb
Host smart-80d1c8c7-c1c5-4726-a624-84d90ce72846
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3460891823 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 17.rom_ctrl_csr_mem_rw_with_rand_reset.3460891823
Directory /workspace/17.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_rw.582197708
Short name T416
Test name
Test status
Simulation time 1671715891 ps
CPU time 13.98 seconds
Started May 09 12:37:04 PM PDT 24
Finished May 09 12:37:30 PM PDT 24
Peak memory 210868 kb
Host smart-1e7a3528-fa34-494b-a956-6c2b68969899
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=582197708 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_csr_rw.582197708
Directory /workspace/17.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_passthru_mem_tl_intg_err.539946639
Short name T85
Test name
Test status
Simulation time 6066339630 ps
CPU time 37.42 seconds
Started May 09 12:37:19 PM PDT 24
Finished May 09 12:38:11 PM PDT 24
Peak memory 210952 kb
Host smart-4ac940bd-aa7e-4b18-bc2f-99ff7514fbbb
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=539946639 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_pa
ssthru_mem_tl_intg_err.539946639
Directory /workspace/17.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_same_csr_outstanding.257767389
Short name T71
Test name
Test status
Simulation time 1874443728 ps
CPU time 14.15 seconds
Started May 09 12:37:54 PM PDT 24
Finished May 09 12:38:21 PM PDT 24
Peak memory 210828 kb
Host smart-6fc84704-305b-4970-9333-83f1dde11478
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=257767389 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_c
trl_same_csr_outstanding.257767389
Directory /workspace/17.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_errors.860620286
Short name T370
Test name
Test status
Simulation time 2573105631 ps
CPU time 15.46 seconds
Started May 09 12:36:54 PM PDT 24
Finished May 09 12:37:20 PM PDT 24
Peak memory 215276 kb
Host smart-de5787f2-2570-482c-a927-82538b6c18f6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=860620286 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_tl_errors.860620286
Directory /workspace/17.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_intg_err.2914993469
Short name T117
Test name
Test status
Simulation time 1247673001 ps
CPU time 38.05 seconds
Started May 09 12:36:55 PM PDT 24
Finished May 09 12:37:44 PM PDT 24
Peak memory 210872 kb
Host smart-283af9fc-ddd2-418a-aae4-636fb0885c21
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2914993469 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_tl_i
ntg_err.2914993469
Directory /workspace/17.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_mem_rw_with_rand_reset.2329037425
Short name T371
Test name
Test status
Simulation time 648825218 ps
CPU time 8.41 seconds
Started May 09 12:37:00 PM PDT 24
Finished May 09 12:37:19 PM PDT 24
Peak memory 212092 kb
Host smart-23569aef-3634-4b68-8965-1cd0648bedb6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2329037425 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 18.rom_ctrl_csr_mem_rw_with_rand_reset.2329037425
Directory /workspace/18.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_rw.1592924708
Short name T450
Test name
Test status
Simulation time 2713454492 ps
CPU time 12.01 seconds
Started May 09 12:37:37 PM PDT 24
Finished May 09 12:38:00 PM PDT 24
Peak memory 210892 kb
Host smart-79b468dc-71a4-4aa6-884c-49e91c8633e5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1592924708 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_csr_rw.1592924708
Directory /workspace/18.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_passthru_mem_tl_intg_err.1423445219
Short name T104
Test name
Test status
Simulation time 12758837753 ps
CPU time 54.91 seconds
Started May 09 12:37:31 PM PDT 24
Finished May 09 12:38:38 PM PDT 24
Peak memory 210872 kb
Host smart-9842b37e-aace-47fe-ac2c-e4649e2dd276
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1423445219 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_p
assthru_mem_tl_intg_err.1423445219
Directory /workspace/18.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_same_csr_outstanding.920453192
Short name T412
Test name
Test status
Simulation time 8184672368 ps
CPU time 17.08 seconds
Started May 09 12:37:27 PM PDT 24
Finished May 09 12:37:57 PM PDT 24
Peak memory 210876 kb
Host smart-de8f5a02-1a21-4b5d-9b0b-b731c3b20973
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=920453192 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_c
trl_same_csr_outstanding.920453192
Directory /workspace/18.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_errors.665167660
Short name T460
Test name
Test status
Simulation time 1382247092 ps
CPU time 14.17 seconds
Started May 09 12:37:04 PM PDT 24
Finished May 09 12:37:30 PM PDT 24
Peak memory 215000 kb
Host smart-2eedf604-995c-4eae-802d-e91f881beeb0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=665167660 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_tl_errors.665167660
Directory /workspace/18.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_mem_rw_with_rand_reset.998093093
Short name T372
Test name
Test status
Simulation time 951058768 ps
CPU time 9.95 seconds
Started May 09 12:37:17 PM PDT 24
Finished May 09 12:37:41 PM PDT 24
Peak memory 214324 kb
Host smart-e111b064-8eab-4f13-9692-90df84816608
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=998093093 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 19.rom_ctrl_csr_mem_rw_with_rand_reset.998093093
Directory /workspace/19.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_rw.2374257508
Short name T426
Test name
Test status
Simulation time 1536009018 ps
CPU time 8.56 seconds
Started May 09 12:37:33 PM PDT 24
Finished May 09 12:37:53 PM PDT 24
Peak memory 210828 kb
Host smart-7ec7e761-cbbc-4883-9405-ae228fb9862c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2374257508 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_csr_rw.2374257508
Directory /workspace/19.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_passthru_mem_tl_intg_err.866633846
Short name T73
Test name
Test status
Simulation time 10580979930 ps
CPU time 34.04 seconds
Started May 09 12:37:37 PM PDT 24
Finished May 09 12:38:22 PM PDT 24
Peak memory 210936 kb
Host smart-07b76be7-3a9b-4c26-b5b8-c0951bffe834
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=866633846 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_pa
ssthru_mem_tl_intg_err.866633846
Directory /workspace/19.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_same_csr_outstanding.2259564676
Short name T399
Test name
Test status
Simulation time 1484687494 ps
CPU time 12.7 seconds
Started May 09 12:37:28 PM PDT 24
Finished May 09 12:37:54 PM PDT 24
Peak memory 210864 kb
Host smart-5ac7b4db-acbd-4e32-87d4-b6d6cf800f8c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2259564676 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_
ctrl_same_csr_outstanding.2259564676
Directory /workspace/19.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_errors.4069933560
Short name T453
Test name
Test status
Simulation time 1321842251 ps
CPU time 16.44 seconds
Started May 09 12:37:15 PM PDT 24
Finished May 09 12:37:46 PM PDT 24
Peak memory 219388 kb
Host smart-f0be5df7-f4ae-444a-85fd-f28b39f6e115
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4069933560 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_tl_errors.4069933560
Directory /workspace/19.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_intg_err.3520711765
Short name T383
Test name
Test status
Simulation time 1342811852 ps
CPU time 39.92 seconds
Started May 09 12:37:24 PM PDT 24
Finished May 09 12:38:18 PM PDT 24
Peak memory 211776 kb
Host smart-e3302f7c-5ef6-497e-b0e0-363bc29fd266
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3520711765 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_tl_i
ntg_err.3520711765
Directory /workspace/19.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_aliasing.2755109183
Short name T72
Test name
Test status
Simulation time 8861111244 ps
CPU time 10.11 seconds
Started May 09 12:37:04 PM PDT 24
Finished May 09 12:37:25 PM PDT 24
Peak memory 210932 kb
Host smart-64d2491b-4e49-4aa3-bdb4-f26b179c78c9
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2755109183 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_alia
sing.2755109183
Directory /workspace/2.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_bit_bash.3698282119
Short name T441
Test name
Test status
Simulation time 2074604968 ps
CPU time 16.1 seconds
Started May 09 12:37:08 PM PDT 24
Finished May 09 12:37:37 PM PDT 24
Peak memory 210928 kb
Host smart-74321bae-00cf-4a67-b155-ac77f10cb169
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3698282119 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_bit_
bash.3698282119
Directory /workspace/2.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_hw_reset.3031553006
Short name T81
Test name
Test status
Simulation time 1505875569 ps
CPU time 13.9 seconds
Started May 09 12:36:58 PM PDT 24
Finished May 09 12:37:23 PM PDT 24
Peak memory 210800 kb
Host smart-439a2d4e-15bd-4d59-ad24-bc82ed7211b1
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3031553006 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_hw_r
eset.3031553006
Directory /workspace/2.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_mem_rw_with_rand_reset.1618395475
Short name T378
Test name
Test status
Simulation time 597467037 ps
CPU time 8.24 seconds
Started May 09 12:36:55 PM PDT 24
Finished May 09 12:37:15 PM PDT 24
Peak memory 219084 kb
Host smart-b9000e0e-ed42-4987-a375-0b3635e14956
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1618395475 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 2.rom_ctrl_csr_mem_rw_with_rand_reset.1618395475
Directory /workspace/2.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_rw.3107576827
Short name T59
Test name
Test status
Simulation time 693612464 ps
CPU time 8.26 seconds
Started May 09 12:36:48 PM PDT 24
Finished May 09 12:37:06 PM PDT 24
Peak memory 210884 kb
Host smart-0bfa2c68-d5b4-41ef-97c2-b9655960d249
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3107576827 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_rw.3107576827
Directory /workspace/2.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_partial_access.1559856132
Short name T430
Test name
Test status
Simulation time 1705659198 ps
CPU time 12.68 seconds
Started May 09 12:37:03 PM PDT 24
Finished May 09 12:37:27 PM PDT 24
Peak memory 210760 kb
Host smart-d6e3406d-7ffa-4b0f-a145-89b21516b447
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1559856132 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctr
l_mem_partial_access.1559856132
Directory /workspace/2.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_walk.846762260
Short name T425
Test name
Test status
Simulation time 1659986613 ps
CPU time 13.68 seconds
Started May 09 12:36:51 PM PDT 24
Finished May 09 12:37:15 PM PDT 24
Peak memory 210776 kb
Host smart-f774224d-7761-4e3a-ae84-eb38dedfbeeb
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=846762260 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_mem_walk.
846762260
Directory /workspace/2.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_passthru_mem_tl_intg_err.4120911907
Short name T80
Test name
Test status
Simulation time 6300632892 ps
CPU time 54.56 seconds
Started May 09 12:36:53 PM PDT 24
Finished May 09 12:37:58 PM PDT 24
Peak memory 210980 kb
Host smart-4326d5ea-efa1-40f3-90dd-12f040ea8c41
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4120911907 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_pa
ssthru_mem_tl_intg_err.4120911907
Directory /workspace/2.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_same_csr_outstanding.3403128735
Short name T468
Test name
Test status
Simulation time 3824286103 ps
CPU time 14.94 seconds
Started May 09 12:37:01 PM PDT 24
Finished May 09 12:37:28 PM PDT 24
Peak memory 210940 kb
Host smart-32f29af0-7584-44cb-ad40-38237f21ca48
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3403128735 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_c
trl_same_csr_outstanding.3403128735
Directory /workspace/2.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_errors.2187989038
Short name T396
Test name
Test status
Simulation time 3411708840 ps
CPU time 14.92 seconds
Started May 09 12:37:07 PM PDT 24
Finished May 09 12:37:34 PM PDT 24
Peak memory 215292 kb
Host smart-d5fcb1f5-8017-48e9-9487-3540da551128
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2187989038 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_tl_errors.2187989038
Directory /workspace/2.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_intg_err.523493087
Short name T116
Test name
Test status
Simulation time 910166501 ps
CPU time 66.96 seconds
Started May 09 12:36:47 PM PDT 24
Finished May 09 12:38:04 PM PDT 24
Peak memory 212000 kb
Host smart-1ba7cca5-d0ed-47b4-a3a0-c8672bcd7559
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=523493087 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_tl_int
g_err.523493087
Directory /workspace/2.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_aliasing.1717859460
Short name T403
Test name
Test status
Simulation time 18491231200 ps
CPU time 14.22 seconds
Started May 09 12:36:46 PM PDT 24
Finished May 09 12:37:11 PM PDT 24
Peak memory 210884 kb
Host smart-23329be8-49a2-4b1c-9e54-a508ae6670e2
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1717859460 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_alia
sing.1717859460
Directory /workspace/3.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_bit_bash.659179145
Short name T447
Test name
Test status
Simulation time 1793956506 ps
CPU time 14.94 seconds
Started May 09 12:37:08 PM PDT 24
Finished May 09 12:37:36 PM PDT 24
Peak memory 210860 kb
Host smart-e943b001-115c-4c28-83e6-06962bf38c05
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=659179145 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_bit_b
ash.659179145
Directory /workspace/3.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_hw_reset.4099492278
Short name T61
Test name
Test status
Simulation time 7891344770 ps
CPU time 17.19 seconds
Started May 09 12:37:18 PM PDT 24
Finished May 09 12:37:49 PM PDT 24
Peak memory 210968 kb
Host smart-8b3905c9-affe-4106-9b5f-4db693ec7585
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4099492278 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_hw_r
eset.4099492278
Directory /workspace/3.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_mem_rw_with_rand_reset.353368986
Short name T417
Test name
Test status
Simulation time 91303561 ps
CPU time 4.59 seconds
Started May 09 12:36:46 PM PDT 24
Finished May 09 12:37:01 PM PDT 24
Peak memory 214408 kb
Host smart-94d8addb-d9c7-4d45-911d-ef02cd927342
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=353368986 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 3.rom_ctrl_csr_mem_rw_with_rand_reset.353368986
Directory /workspace/3.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_rw.4190409788
Short name T455
Test name
Test status
Simulation time 2228098613 ps
CPU time 10.72 seconds
Started May 09 12:36:49 PM PDT 24
Finished May 09 12:37:11 PM PDT 24
Peak memory 210888 kb
Host smart-0252ca51-3a2a-4801-b0f2-01dd4d70b7cb
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4190409788 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_rw.4190409788
Directory /workspace/3.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_partial_access.4190265894
Short name T457
Test name
Test status
Simulation time 5942101835 ps
CPU time 12.32 seconds
Started May 09 12:36:47 PM PDT 24
Finished May 09 12:37:09 PM PDT 24
Peak memory 210756 kb
Host smart-3a02776e-9b61-49c8-a434-76a0d18d0ee5
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4190265894 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctr
l_mem_partial_access.4190265894
Directory /workspace/3.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_walk.2401919436
Short name T382
Test name
Test status
Simulation time 333273842 ps
CPU time 4.1 seconds
Started May 09 12:36:44 PM PDT 24
Finished May 09 12:36:58 PM PDT 24
Peak memory 210752 kb
Host smart-33923f7b-472f-4f38-92ed-eac56552655d
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2401919436 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_mem_walk
.2401919436
Directory /workspace/3.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_passthru_mem_tl_intg_err.3535693197
Short name T106
Test name
Test status
Simulation time 15799938809 ps
CPU time 63.68 seconds
Started May 09 12:37:10 PM PDT 24
Finished May 09 12:38:28 PM PDT 24
Peak memory 210972 kb
Host smart-c38aae23-c897-4302-b02f-f8f58a60cb86
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3535693197 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_pa
ssthru_mem_tl_intg_err.3535693197
Directory /workspace/3.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_same_csr_outstanding.2717403967
Short name T454
Test name
Test status
Simulation time 5049286133 ps
CPU time 12.44 seconds
Started May 09 12:37:38 PM PDT 24
Finished May 09 12:38:01 PM PDT 24
Peak memory 210972 kb
Host smart-1aa9929e-52fc-4583-95d3-a22d18ad7a9a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2717403967 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_c
trl_same_csr_outstanding.2717403967
Directory /workspace/3.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_errors.1727360312
Short name T376
Test name
Test status
Simulation time 1259436611 ps
CPU time 15.02 seconds
Started May 09 12:36:49 PM PDT 24
Finished May 09 12:37:15 PM PDT 24
Peak memory 219140 kb
Host smart-84d765e3-1a99-422d-bc01-0ed7216b03cd
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1727360312 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_tl_errors.1727360312
Directory /workspace/3.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_intg_err.1823575905
Short name T119
Test name
Test status
Simulation time 3869522072 ps
CPU time 45.73 seconds
Started May 09 12:36:45 PM PDT 24
Finished May 09 12:37:40 PM PDT 24
Peak memory 211308 kb
Host smart-202cc098-f7d8-49b5-a5cf-f162d45975ee
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1823575905 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_tl_in
tg_err.1823575905
Directory /workspace/3.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_aliasing.1126251193
Short name T439
Test name
Test status
Simulation time 1651892900 ps
CPU time 13.4 seconds
Started May 09 12:36:47 PM PDT 24
Finished May 09 12:37:10 PM PDT 24
Peak memory 210816 kb
Host smart-bbf348cb-9680-4852-a133-d5f7a6c1025c
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1126251193 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_alia
sing.1126251193
Directory /workspace/4.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_bit_bash.627169013
Short name T411
Test name
Test status
Simulation time 168110081 ps
CPU time 4.64 seconds
Started May 09 12:37:01 PM PDT 24
Finished May 09 12:37:17 PM PDT 24
Peak memory 216804 kb
Host smart-2793690e-d2c0-40d0-a4da-feb74859f572
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=627169013 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_bit_b
ash.627169013
Directory /workspace/4.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_hw_reset.4099454004
Short name T465
Test name
Test status
Simulation time 2074499675 ps
CPU time 13.23 seconds
Started May 09 12:37:00 PM PDT 24
Finished May 09 12:37:24 PM PDT 24
Peak memory 210900 kb
Host smart-ad27bef7-dfd8-4029-88b4-8af1b16042a9
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4099454004 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_hw_r
eset.4099454004
Directory /workspace/4.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_mem_rw_with_rand_reset.1175291476
Short name T440
Test name
Test status
Simulation time 7607710053 ps
CPU time 10.09 seconds
Started May 09 12:37:28 PM PDT 24
Finished May 09 12:37:51 PM PDT 24
Peak memory 219196 kb
Host smart-9d8bdf52-9533-40a1-b08a-b5fe41367a4f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1175291476 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 4.rom_ctrl_csr_mem_rw_with_rand_reset.1175291476
Directory /workspace/4.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_rw.2861255348
Short name T442
Test name
Test status
Simulation time 2585973089 ps
CPU time 14.81 seconds
Started May 09 12:36:45 PM PDT 24
Finished May 09 12:37:09 PM PDT 24
Peak memory 210920 kb
Host smart-93c577e2-8d81-491c-9275-b092991a1614
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2861255348 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_rw.2861255348
Directory /workspace/4.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_partial_access.1338206728
Short name T392
Test name
Test status
Simulation time 1921850652 ps
CPU time 7.7 seconds
Started May 09 12:36:45 PM PDT 24
Finished May 09 12:37:08 PM PDT 24
Peak memory 210756 kb
Host smart-c9f1f335-f918-41f3-8f0d-6febfca5a685
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1338206728 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctr
l_mem_partial_access.1338206728
Directory /workspace/4.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_walk.240658882
Short name T400
Test name
Test status
Simulation time 24396388832 ps
CPU time 13.2 seconds
Started May 09 12:36:54 PM PDT 24
Finished May 09 12:37:18 PM PDT 24
Peak memory 210840 kb
Host smart-b381ba0a-d74c-442d-a09c-6486c80d12f5
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=240658882 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_mem_walk.
240658882
Directory /workspace/4.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_passthru_mem_tl_intg_err.2631730348
Short name T428
Test name
Test status
Simulation time 7928690019 ps
CPU time 62.92 seconds
Started May 09 12:36:54 PM PDT 24
Finished May 09 12:38:09 PM PDT 24
Peak memory 210872 kb
Host smart-e70f6c78-3781-45db-a93a-65bf9fd04bfa
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2631730348 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_pa
ssthru_mem_tl_intg_err.2631730348
Directory /workspace/4.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_same_csr_outstanding.59910762
Short name T427
Test name
Test status
Simulation time 183063840 ps
CPU time 4.17 seconds
Started May 09 12:37:17 PM PDT 24
Finished May 09 12:37:36 PM PDT 24
Peak memory 210836 kb
Host smart-bc075053-85e5-4e41-a707-bd8dbf7508da
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=59910762 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctr
l_same_csr_outstanding.59910762
Directory /workspace/4.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_errors.2732989692
Short name T375
Test name
Test status
Simulation time 3608118032 ps
CPU time 13.21 seconds
Started May 09 12:36:45 PM PDT 24
Finished May 09 12:37:07 PM PDT 24
Peak memory 219132 kb
Host smart-191b3122-d60d-4171-a688-34dad79051cf
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2732989692 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_tl_errors.2732989692
Directory /workspace/4.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_mem_rw_with_rand_reset.1409132118
Short name T470
Test name
Test status
Simulation time 560887108 ps
CPU time 5.68 seconds
Started May 09 12:36:47 PM PDT 24
Finished May 09 12:37:02 PM PDT 24
Peak memory 219124 kb
Host smart-9aca1634-b5ab-4efc-99d5-35885f257372
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1409132118 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 5.rom_ctrl_csr_mem_rw_with_rand_reset.1409132118
Directory /workspace/5.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_rw.2262072585
Short name T390
Test name
Test status
Simulation time 431938965 ps
CPU time 5.51 seconds
Started May 09 12:36:45 PM PDT 24
Finished May 09 12:37:00 PM PDT 24
Peak memory 217208 kb
Host smart-8be9f8a2-5cf9-4786-8ec0-a637a28ba286
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2262072585 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_csr_rw.2262072585
Directory /workspace/5.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_passthru_mem_tl_intg_err.1979204774
Short name T421
Test name
Test status
Simulation time 9946648647 ps
CPU time 80.19 seconds
Started May 09 12:36:46 PM PDT 24
Finished May 09 12:38:16 PM PDT 24
Peak memory 219148 kb
Host smart-520a315d-5fb9-49e5-b5de-f96286ed6876
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1979204774 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_pa
ssthru_mem_tl_intg_err.1979204774
Directory /workspace/5.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_same_csr_outstanding.3219053032
Short name T397
Test name
Test status
Simulation time 1039162542 ps
CPU time 5.44 seconds
Started May 09 12:37:12 PM PDT 24
Finished May 09 12:37:32 PM PDT 24
Peak memory 210904 kb
Host smart-dcf93f8b-7ab5-46be-ba92-16407889f9b3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3219053032 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_c
trl_same_csr_outstanding.3219053032
Directory /workspace/5.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_errors.3858074995
Short name T467
Test name
Test status
Simulation time 103049265 ps
CPU time 7.81 seconds
Started May 09 12:36:47 PM PDT 24
Finished May 09 12:37:05 PM PDT 24
Peak memory 219144 kb
Host smart-c40676e9-7767-4ef1-9791-d031639038f1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3858074995 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_tl_errors.3858074995
Directory /workspace/5.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_intg_err.1830373731
Short name T434
Test name
Test status
Simulation time 1676151897 ps
CPU time 66.53 seconds
Started May 09 12:37:06 PM PDT 24
Finished May 09 12:38:25 PM PDT 24
Peak memory 211940 kb
Host smart-3513517f-c6b7-433c-b205-6a012ae87604
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1830373731 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_tl_in
tg_err.1830373731
Directory /workspace/5.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_mem_rw_with_rand_reset.4229873870
Short name T436
Test name
Test status
Simulation time 109214113 ps
CPU time 4.94 seconds
Started May 09 12:36:47 PM PDT 24
Finished May 09 12:37:02 PM PDT 24
Peak memory 218996 kb
Host smart-7777e0eb-6a94-4954-bd70-3c76ed5813d3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4229873870 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 6.rom_ctrl_csr_mem_rw_with_rand_reset.4229873870
Directory /workspace/6.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_rw.307204295
Short name T385
Test name
Test status
Simulation time 4365405782 ps
CPU time 15.9 seconds
Started May 09 12:36:47 PM PDT 24
Finished May 09 12:37:13 PM PDT 24
Peak memory 210904 kb
Host smart-408f0d51-4564-4372-a62f-f3df31063d4a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=307204295 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_csr_rw.307204295
Directory /workspace/6.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_passthru_mem_tl_intg_err.650685256
Short name T82
Test name
Test status
Simulation time 33007853062 ps
CPU time 59.87 seconds
Started May 09 12:37:28 PM PDT 24
Finished May 09 12:38:41 PM PDT 24
Peak memory 210956 kb
Host smart-f6cfa49f-134f-4d36-bd0f-0ac9502ff458
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=650685256 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_pas
sthru_mem_tl_intg_err.650685256
Directory /workspace/6.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_same_csr_outstanding.75225935
Short name T448
Test name
Test status
Simulation time 6183224022 ps
CPU time 12.68 seconds
Started May 09 12:36:48 PM PDT 24
Finished May 09 12:37:10 PM PDT 24
Peak memory 210940 kb
Host smart-cbc90059-00e5-4a1c-ba6e-926a57b905a3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75225935 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctr
l_same_csr_outstanding.75225935
Directory /workspace/6.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_errors.3668334513
Short name T373
Test name
Test status
Simulation time 2629697169 ps
CPU time 16.2 seconds
Started May 09 12:36:41 PM PDT 24
Finished May 09 12:37:05 PM PDT 24
Peak memory 219112 kb
Host smart-924e0da1-0628-4f04-9e68-88518eb7f77f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3668334513 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_tl_errors.3668334513
Directory /workspace/6.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_mem_rw_with_rand_reset.4263423916
Short name T422
Test name
Test status
Simulation time 2649809210 ps
CPU time 12.01 seconds
Started May 09 12:37:11 PM PDT 24
Finished May 09 12:37:37 PM PDT 24
Peak memory 214328 kb
Host smart-e1354fc8-e66a-4f74-83d3-47c594da8a14
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4263423916 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 7.rom_ctrl_csr_mem_rw_with_rand_reset.4263423916
Directory /workspace/7.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_rw.3406487568
Short name T463
Test name
Test status
Simulation time 863901920 ps
CPU time 5.61 seconds
Started May 09 12:37:03 PM PDT 24
Finished May 09 12:37:20 PM PDT 24
Peak memory 210844 kb
Host smart-f0beaeef-0ce1-42ad-bd85-b5958dcb9a84
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3406487568 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_csr_rw.3406487568
Directory /workspace/7.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_passthru_mem_tl_intg_err.3798394427
Short name T67
Test name
Test status
Simulation time 362188741 ps
CPU time 18.62 seconds
Started May 09 12:36:48 PM PDT 24
Finished May 09 12:37:17 PM PDT 24
Peak memory 210824 kb
Host smart-9a4a87e2-d085-4465-8ae6-33bcb7e4c5dc
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3798394427 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_pa
ssthru_mem_tl_intg_err.3798394427
Directory /workspace/7.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_same_csr_outstanding.3983372392
Short name T423
Test name
Test status
Simulation time 162384406 ps
CPU time 4.22 seconds
Started May 09 12:36:47 PM PDT 24
Finished May 09 12:37:01 PM PDT 24
Peak memory 210876 kb
Host smart-65629bff-43a3-46fe-895a-ecd0a2a5be27
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3983372392 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_c
trl_same_csr_outstanding.3983372392
Directory /workspace/7.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_errors.576595542
Short name T413
Test name
Test status
Simulation time 2653531228 ps
CPU time 11.64 seconds
Started May 09 12:37:15 PM PDT 24
Finished May 09 12:37:41 PM PDT 24
Peak memory 219188 kb
Host smart-89a90b47-08da-4e18-b0ce-993b9bd5e336
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=576595542 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_tl_errors.576595542
Directory /workspace/7.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_intg_err.2783818707
Short name T462
Test name
Test status
Simulation time 5340321748 ps
CPU time 71.6 seconds
Started May 09 12:37:10 PM PDT 24
Finished May 09 12:38:35 PM PDT 24
Peak memory 219084 kb
Host smart-c0436bb7-6429-4b67-a468-6175cde95abe
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2783818707 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_tl_in
tg_err.2783818707
Directory /workspace/7.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_mem_rw_with_rand_reset.948502745
Short name T437
Test name
Test status
Simulation time 509885263 ps
CPU time 7.29 seconds
Started May 09 12:37:12 PM PDT 24
Finished May 09 12:37:34 PM PDT 24
Peak memory 212240 kb
Host smart-1c59a2bf-cb36-433a-a20c-a1df32943dab
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=948502745 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 8.rom_ctrl_csr_mem_rw_with_rand_reset.948502745
Directory /workspace/8.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_rw.3372457391
Short name T466
Test name
Test status
Simulation time 1732751818 ps
CPU time 14.55 seconds
Started May 09 12:36:46 PM PDT 24
Finished May 09 12:37:11 PM PDT 24
Peak memory 210796 kb
Host smart-9f7d3e8c-829a-42b4-810f-fbf60b987d58
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3372457391 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_csr_rw.3372457391
Directory /workspace/8.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_same_csr_outstanding.1648921224
Short name T419
Test name
Test status
Simulation time 415448853 ps
CPU time 4.11 seconds
Started May 09 12:36:55 PM PDT 24
Finished May 09 12:37:10 PM PDT 24
Peak memory 217608 kb
Host smart-099442bc-67df-4953-b1c6-a9281a9edafc
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1648921224 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_c
trl_same_csr_outstanding.1648921224
Directory /workspace/8.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_errors.1990004960
Short name T456
Test name
Test status
Simulation time 2568363227 ps
CPU time 11.62 seconds
Started May 09 12:36:52 PM PDT 24
Finished May 09 12:37:14 PM PDT 24
Peak memory 219136 kb
Host smart-ed78af81-a9a7-4e43-93d9-871bb0f25685
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1990004960 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_tl_errors.1990004960
Directory /workspace/8.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_mem_rw_with_rand_reset.2983129079
Short name T432
Test name
Test status
Simulation time 1808562821 ps
CPU time 14.38 seconds
Started May 09 12:37:38 PM PDT 24
Finished May 09 12:38:04 PM PDT 24
Peak memory 212096 kb
Host smart-44026ca1-a452-496b-9293-7874e51e5a39
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2983129079 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 9.rom_ctrl_csr_mem_rw_with_rand_reset.2983129079
Directory /workspace/9.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_rw.3320756623
Short name T89
Test name
Test status
Simulation time 1644325989 ps
CPU time 6.39 seconds
Started May 09 12:36:50 PM PDT 24
Finished May 09 12:37:07 PM PDT 24
Peak memory 210848 kb
Host smart-a2816e42-7a55-4857-b2cd-cef726327678
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3320756623 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_csr_rw.3320756623
Directory /workspace/9.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_passthru_mem_tl_intg_err.2608922457
Short name T103
Test name
Test status
Simulation time 4972562229 ps
CPU time 33.61 seconds
Started May 09 12:36:44 PM PDT 24
Finished May 09 12:37:27 PM PDT 24
Peak memory 210928 kb
Host smart-3e92f46d-07a2-483c-8399-0b1db0604380
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2608922457 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_pa
ssthru_mem_tl_intg_err.2608922457
Directory /workspace/9.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_same_csr_outstanding.3740183051
Short name T461
Test name
Test status
Simulation time 2094494778 ps
CPU time 11.13 seconds
Started May 09 12:37:24 PM PDT 24
Finished May 09 12:37:50 PM PDT 24
Peak memory 210916 kb
Host smart-f821975b-66ad-4253-8320-518eecb5483e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3740183051 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_c
trl_same_csr_outstanding.3740183051
Directory /workspace/9.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_errors.1352932960
Short name T414
Test name
Test status
Simulation time 3597939631 ps
CPU time 11.94 seconds
Started May 09 12:37:07 PM PDT 24
Finished May 09 12:37:31 PM PDT 24
Peak memory 219112 kb
Host smart-4a9ae34e-4067-462a-bcfb-1f854c95ffe7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1352932960 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_tl_errors.1352932960
Directory /workspace/9.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_intg_err.3639573280
Short name T111
Test name
Test status
Simulation time 2185059167 ps
CPU time 68.74 seconds
Started May 09 12:37:05 PM PDT 24
Finished May 09 12:38:26 PM PDT 24
Peak memory 219040 kb
Host smart-43f8fe59-9cf3-4269-af17-305d5cf60d34
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3639573280 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_tl_in
tg_err.3639573280
Directory /workspace/9.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/0.rom_ctrl_alert_test.1912127962
Short name T314
Test name
Test status
Simulation time 347440955 ps
CPU time 4.32 seconds
Started May 09 12:37:16 PM PDT 24
Finished May 09 12:37:35 PM PDT 24
Peak memory 211716 kb
Host smart-483b84b6-a8d4-41e1-b1d8-073ae5be437e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1912127962 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_alert_test.1912127962
Directory /workspace/0.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/0.rom_ctrl_corrupt_sig_fatal_chk.2582207719
Short name T8
Test name
Test status
Simulation time 125872300642 ps
CPU time 344.01 seconds
Started May 09 12:37:10 PM PDT 24
Finished May 09 12:43:07 PM PDT 24
Peak memory 221440 kb
Host smart-a2db5364-ab84-4eab-8d5e-091669d4156e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2582207719 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_c
orrupt_sig_fatal_chk.2582207719
Directory /workspace/0.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/0.rom_ctrl_max_throughput_chk.3070120545
Short name T10
Test name
Test status
Simulation time 167016760 ps
CPU time 5.54 seconds
Started May 09 12:37:24 PM PDT 24
Finished May 09 12:37:43 PM PDT 24
Peak memory 211548 kb
Host smart-2f4ea2d7-5b7a-4504-9e09-e3fc27198c23
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3070120545 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_max_throughput_chk.3070120545
Directory /workspace/0.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/0.rom_ctrl_sec_cm.3479591699
Short name T36
Test name
Test status
Simulation time 2850153749 ps
CPU time 57.12 seconds
Started May 09 12:37:25 PM PDT 24
Finished May 09 12:38:36 PM PDT 24
Peak memory 233792 kb
Host smart-66a14bda-f7cd-4a49-bd1b-8ee284eed87d
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3479591699 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_sec_cm.3479591699
Directory /workspace/0.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/0.rom_ctrl_smoke.3925411893
Short name T366
Test name
Test status
Simulation time 8022886963 ps
CPU time 32.56 seconds
Started May 09 12:37:10 PM PDT 24
Finished May 09 12:37:56 PM PDT 24
Peak memory 219940 kb
Host smart-630b4d07-ed10-4f13-8234-90db9ed6473c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3925411893 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_smoke.3925411893
Directory /workspace/0.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/0.rom_ctrl_stress_all.1546107507
Short name T342
Test name
Test status
Simulation time 656947211 ps
CPU time 33.62 seconds
Started May 09 12:37:22 PM PDT 24
Finished May 09 12:38:10 PM PDT 24
Peak memory 215828 kb
Host smart-4b4fc32b-caa5-4558-b898-5153a403f562
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1546107507 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 0.rom_ctrl_stress_all.1546107507
Directory /workspace/0.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/1.rom_ctrl_alert_test.802212221
Short name T1
Test name
Test status
Simulation time 2642255787 ps
CPU time 16.33 seconds
Started May 09 12:37:41 PM PDT 24
Finished May 09 12:38:08 PM PDT 24
Peak memory 211716 kb
Host smart-78741633-8d96-4f5a-a71d-c53d93a2b83d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=802212221 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_alert_test.802212221
Directory /workspace/1.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/1.rom_ctrl_corrupt_sig_fatal_chk.1432303490
Short name T47
Test name
Test status
Simulation time 131940172292 ps
CPU time 280.93 seconds
Started May 09 12:37:12 PM PDT 24
Finished May 09 12:42:06 PM PDT 24
Peak memory 212980 kb
Host smart-020cd3be-3c55-4cc2-9a0f-8eca80bc8bf1
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1432303490 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_c
orrupt_sig_fatal_chk.1432303490
Directory /workspace/1.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/1.rom_ctrl_kmac_err_chk.2450122345
Short name T367
Test name
Test status
Simulation time 16309466472 ps
CPU time 32.14 seconds
Started May 09 12:37:13 PM PDT 24
Finished May 09 12:38:00 PM PDT 24
Peak memory 213028 kb
Host smart-894e310b-e3e2-4c64-9140-ac5f4460b32a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2450122345 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_kmac_err_chk.2450122345
Directory /workspace/1.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/1.rom_ctrl_max_throughput_chk.3964329241
Short name T230
Test name
Test status
Simulation time 141927314 ps
CPU time 6.58 seconds
Started May 09 12:37:33 PM PDT 24
Finished May 09 12:37:51 PM PDT 24
Peak memory 211592 kb
Host smart-c94d0337-33af-4f3d-bba3-5d53e388c175
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3964329241 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_max_throughput_chk.3964329241
Directory /workspace/1.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/1.rom_ctrl_sec_cm.97593306
Short name T30
Test name
Test status
Simulation time 2815095237 ps
CPU time 59.2 seconds
Started May 09 12:37:13 PM PDT 24
Finished May 09 12:38:27 PM PDT 24
Peak memory 238532 kb
Host smart-553fc28b-7542-4ed9-98f4-9cb27838289b
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=97593306 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_sec_cm.97593306
Directory /workspace/1.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/1.rom_ctrl_smoke.465613135
Short name T74
Test name
Test status
Simulation time 514408637 ps
CPU time 14.74 seconds
Started May 09 12:37:00 PM PDT 24
Finished May 09 12:37:26 PM PDT 24
Peak memory 213848 kb
Host smart-ef5111cf-622c-4676-a5f4-e21a60491ecd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=465613135 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_smoke.465613135
Directory /workspace/1.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/1.rom_ctrl_stress_all.1912967666
Short name T213
Test name
Test status
Simulation time 3001217551 ps
CPU time 16.7 seconds
Started May 09 12:37:21 PM PDT 24
Finished May 09 12:37:52 PM PDT 24
Peak memory 212588 kb
Host smart-8d1f6936-5102-48ae-9d47-f76065202a03
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1912967666 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 1.rom_ctrl_stress_all.1912967666
Directory /workspace/1.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/10.rom_ctrl_kmac_err_chk.701736345
Short name T337
Test name
Test status
Simulation time 3638459178 ps
CPU time 20.02 seconds
Started May 09 12:37:26 PM PDT 24
Finished May 09 12:38:00 PM PDT 24
Peak memory 212480 kb
Host smart-ebd59f73-f957-459e-beca-0072b9295ed8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=701736345 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_kmac_err_chk.701736345
Directory /workspace/10.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/10.rom_ctrl_max_throughput_chk.589694455
Short name T221
Test name
Test status
Simulation time 1504729904 ps
CPU time 14.39 seconds
Started May 09 12:37:18 PM PDT 24
Finished May 09 12:37:46 PM PDT 24
Peak memory 211596 kb
Host smart-b1583e56-ac29-4411-aa85-4497627be628
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=589694455 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_max_throughput_chk.589694455
Directory /workspace/10.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/10.rom_ctrl_smoke.337936204
Short name T130
Test name
Test status
Simulation time 15599425705 ps
CPU time 32.62 seconds
Started May 09 12:37:29 PM PDT 24
Finished May 09 12:38:14 PM PDT 24
Peak memory 214844 kb
Host smart-44a85de3-8abf-411a-95a5-57af7c129ea4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=337936204 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_smoke.337936204
Directory /workspace/10.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/10.rom_ctrl_stress_all.3497727176
Short name T159
Test name
Test status
Simulation time 3934837043 ps
CPU time 40.12 seconds
Started May 09 12:37:19 PM PDT 24
Finished May 09 12:38:14 PM PDT 24
Peak memory 214136 kb
Host smart-14db3219-28d5-4b33-9e3d-a457c9859809
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3497727176 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 10.rom_ctrl_stress_all.3497727176
Directory /workspace/10.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/10.rom_ctrl_stress_all_with_rand_reset.3270044482
Short name T222
Test name
Test status
Simulation time 87096459540 ps
CPU time 6996.28 seconds
Started May 09 12:37:26 PM PDT 24
Finished May 09 02:34:17 PM PDT 24
Peak memory 237676 kb
Host smart-cff9b117-a887-41af-9b12-46b9ef73e25e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3270044482 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_stress_all_with_rand_reset.3270044482
Directory /workspace/10.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/11.rom_ctrl_alert_test.866344042
Short name T169
Test name
Test status
Simulation time 4660458796 ps
CPU time 15.35 seconds
Started May 09 12:37:27 PM PDT 24
Finished May 09 12:37:55 PM PDT 24
Peak memory 211844 kb
Host smart-8f345754-95d2-4149-a2e7-79a3bc2d3986
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=866344042 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_alert_test.866344042
Directory /workspace/11.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/11.rom_ctrl_corrupt_sig_fatal_chk.673200933
Short name T289
Test name
Test status
Simulation time 18581386980 ps
CPU time 257.87 seconds
Started May 09 12:37:15 PM PDT 24
Finished May 09 12:41:47 PM PDT 24
Peak memory 238616 kb
Host smart-3394260e-cef4-4c36-a0ec-9c3e16781c14
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=673200933 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_c
orrupt_sig_fatal_chk.673200933
Directory /workspace/11.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/11.rom_ctrl_kmac_err_chk.2046456191
Short name T161
Test name
Test status
Simulation time 9824116203 ps
CPU time 24.17 seconds
Started May 09 12:37:22 PM PDT 24
Finished May 09 12:38:01 PM PDT 24
Peak memory 212876 kb
Host smart-40d00f13-05bf-4d23-8d09-be8fa0d3bd57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2046456191 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_kmac_err_chk.2046456191
Directory /workspace/11.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/11.rom_ctrl_max_throughput_chk.1059123573
Short name T318
Test name
Test status
Simulation time 12579861586 ps
CPU time 17.81 seconds
Started May 09 12:37:36 PM PDT 24
Finished May 09 12:38:04 PM PDT 24
Peak memory 211664 kb
Host smart-825eda75-9b9a-4bf6-991c-d75d26204939
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1059123573 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_max_throughput_chk.1059123573
Directory /workspace/11.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/11.rom_ctrl_smoke.1000839636
Short name T280
Test name
Test status
Simulation time 2570897915 ps
CPU time 23.87 seconds
Started May 09 12:37:15 PM PDT 24
Finished May 09 12:37:53 PM PDT 24
Peak memory 213328 kb
Host smart-fe1e08f7-7efc-421c-8382-7dcc4cffef34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1000839636 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_smoke.1000839636
Directory /workspace/11.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/11.rom_ctrl_stress_all.3066408054
Short name T368
Test name
Test status
Simulation time 2985593746 ps
CPU time 34.76 seconds
Started May 09 12:37:28 PM PDT 24
Finished May 09 12:38:15 PM PDT 24
Peak memory 213960 kb
Host smart-02bd7929-a0a2-4715-a183-8d9a017846be
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3066408054 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 11.rom_ctrl_stress_all.3066408054
Directory /workspace/11.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/12.rom_ctrl_alert_test.645281071
Short name T33
Test name
Test status
Simulation time 87491512 ps
CPU time 4.37 seconds
Started May 09 12:37:36 PM PDT 24
Finished May 09 12:37:51 PM PDT 24
Peak memory 211648 kb
Host smart-fdffe7d5-ff2e-4891-ab68-32fc5e413322
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=645281071 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_alert_test.645281071
Directory /workspace/12.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/12.rom_ctrl_corrupt_sig_fatal_chk.3101491864
Short name T306
Test name
Test status
Simulation time 74503049786 ps
CPU time 277.51 seconds
Started May 09 12:37:10 PM PDT 24
Finished May 09 12:42:01 PM PDT 24
Peak memory 235360 kb
Host smart-621be9a7-3e28-4a90-a920-4fd0b9ac38be
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3101491864 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_
corrupt_sig_fatal_chk.3101491864
Directory /workspace/12.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/12.rom_ctrl_kmac_err_chk.1298474921
Short name T341
Test name
Test status
Simulation time 1797484940 ps
CPU time 19.82 seconds
Started May 09 12:38:33 PM PDT 24
Finished May 09 12:39:09 PM PDT 24
Peak memory 211816 kb
Host smart-970e9388-a9e0-439f-a5aa-a7f1cef9a9b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1298474921 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_kmac_err_chk.1298474921
Directory /workspace/12.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/12.rom_ctrl_smoke.733265844
Short name T129
Test name
Test status
Simulation time 722372717 ps
CPU time 9.55 seconds
Started May 09 12:37:29 PM PDT 24
Finished May 09 12:37:51 PM PDT 24
Peak memory 219888 kb
Host smart-3b318bde-8170-4e34-a68b-d044986694cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=733265844 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_smoke.733265844
Directory /workspace/12.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/12.rom_ctrl_stress_all.3811636078
Short name T137
Test name
Test status
Simulation time 7335605802 ps
CPU time 29.09 seconds
Started May 09 12:37:23 PM PDT 24
Finished May 09 12:38:06 PM PDT 24
Peak memory 219864 kb
Host smart-7dc5e558-2bd4-49a3-9ce3-0aa53878199c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3811636078 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 12.rom_ctrl_stress_all.3811636078
Directory /workspace/12.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/13.rom_ctrl_alert_test.4026072610
Short name T308
Test name
Test status
Simulation time 1776927854 ps
CPU time 13.77 seconds
Started May 09 12:38:30 PM PDT 24
Finished May 09 12:39:00 PM PDT 24
Peak memory 211352 kb
Host smart-39ebe3b5-7997-41dd-8f0d-e2029c504fbc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4026072610 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_alert_test.4026072610
Directory /workspace/13.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/13.rom_ctrl_corrupt_sig_fatal_chk.1697613459
Short name T296
Test name
Test status
Simulation time 40628124326 ps
CPU time 378.24 seconds
Started May 09 12:37:21 PM PDT 24
Finished May 09 12:43:54 PM PDT 24
Peak memory 221560 kb
Host smart-bdb75e7a-2271-4fc7-85fb-e694936f8768
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1697613459 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_
corrupt_sig_fatal_chk.1697613459
Directory /workspace/13.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/13.rom_ctrl_kmac_err_chk.1880660388
Short name T333
Test name
Test status
Simulation time 11133887180 ps
CPU time 25.3 seconds
Started May 09 12:38:29 PM PDT 24
Finished May 09 12:39:10 PM PDT 24
Peak memory 212316 kb
Host smart-d97adbf4-a846-4ef4-94e2-530d4965a93d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1880660388 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_kmac_err_chk.1880660388
Directory /workspace/13.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/13.rom_ctrl_max_throughput_chk.2485903880
Short name T97
Test name
Test status
Simulation time 725071102 ps
CPU time 6.59 seconds
Started May 09 12:37:14 PM PDT 24
Finished May 09 12:37:35 PM PDT 24
Peak memory 211660 kb
Host smart-1e7b310b-0c4a-4000-b06a-84c888399953
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2485903880 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_max_throughput_chk.2485903880
Directory /workspace/13.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/13.rom_ctrl_smoke.3340007536
Short name T319
Test name
Test status
Simulation time 2235888215 ps
CPU time 22.92 seconds
Started May 09 12:37:25 PM PDT 24
Finished May 09 12:38:02 PM PDT 24
Peak memory 213888 kb
Host smart-def5c12d-4ae9-4933-be42-db67cf72c203
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3340007536 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_smoke.3340007536
Directory /workspace/13.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/13.rom_ctrl_stress_all.1587898494
Short name T291
Test name
Test status
Simulation time 6628394308 ps
CPU time 42.6 seconds
Started May 09 12:37:14 PM PDT 24
Finished May 09 12:38:11 PM PDT 24
Peak memory 216684 kb
Host smart-d217b47c-8d39-4924-b86e-650ff67bf4d6
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1587898494 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 13.rom_ctrl_stress_all.1587898494
Directory /workspace/13.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/14.rom_ctrl_alert_test.647156783
Short name T361
Test name
Test status
Simulation time 1995185752 ps
CPU time 9.93 seconds
Started May 09 12:37:14 PM PDT 24
Finished May 09 12:37:38 PM PDT 24
Peak memory 211684 kb
Host smart-ec23bb85-7f9f-4ba0-a24d-e45094890976
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=647156783 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_alert_test.647156783
Directory /workspace/14.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/14.rom_ctrl_corrupt_sig_fatal_chk.3619111150
Short name T170
Test name
Test status
Simulation time 69110840926 ps
CPU time 334.03 seconds
Started May 09 12:37:19 PM PDT 24
Finished May 09 12:43:08 PM PDT 24
Peak memory 229292 kb
Host smart-1e392f71-1bfd-4d7d-a042-873464db6c2c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3619111150 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_
corrupt_sig_fatal_chk.3619111150
Directory /workspace/14.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/14.rom_ctrl_kmac_err_chk.1770089569
Short name T135
Test name
Test status
Simulation time 1587934078 ps
CPU time 17.15 seconds
Started May 09 12:37:32 PM PDT 24
Finished May 09 12:38:01 PM PDT 24
Peak memory 211612 kb
Host smart-ce3160be-6082-4be9-890b-9ff6c8ca3777
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1770089569 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_kmac_err_chk.1770089569
Directory /workspace/14.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/14.rom_ctrl_max_throughput_chk.2908918662
Short name T320
Test name
Test status
Simulation time 387219872 ps
CPU time 5.45 seconds
Started May 09 12:37:21 PM PDT 24
Finished May 09 12:37:41 PM PDT 24
Peak memory 211624 kb
Host smart-1f3837fc-04d1-4cf8-a96e-41be573da2f3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2908918662 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_max_throughput_chk.2908918662
Directory /workspace/14.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/14.rom_ctrl_smoke.1266399626
Short name T344
Test name
Test status
Simulation time 613064918 ps
CPU time 14.06 seconds
Started May 09 12:38:29 PM PDT 24
Finished May 09 12:38:59 PM PDT 24
Peak memory 219440 kb
Host smart-816aca0a-4899-4b4e-9840-17361f6bf350
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1266399626 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_smoke.1266399626
Directory /workspace/14.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/14.rom_ctrl_stress_all.2691774387
Short name T346
Test name
Test status
Simulation time 18340402508 ps
CPU time 90.99 seconds
Started May 09 12:37:23 PM PDT 24
Finished May 09 12:39:08 PM PDT 24
Peak memory 219908 kb
Host smart-05162aca-e772-495a-a477-8268a516a524
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2691774387 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 14.rom_ctrl_stress_all.2691774387
Directory /workspace/14.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/15.rom_ctrl_alert_test.1507785713
Short name T242
Test name
Test status
Simulation time 4916811083 ps
CPU time 11.58 seconds
Started May 09 12:37:42 PM PDT 24
Finished May 09 12:38:04 PM PDT 24
Peak memory 211768 kb
Host smart-e6948d5d-9783-4f3f-b711-09becd4dee41
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1507785713 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_alert_test.1507785713
Directory /workspace/15.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/15.rom_ctrl_corrupt_sig_fatal_chk.312746079
Short name T49
Test name
Test status
Simulation time 305160100453 ps
CPU time 449.05 seconds
Started May 09 12:37:19 PM PDT 24
Finished May 09 12:45:03 PM PDT 24
Peak memory 237244 kb
Host smart-bdfc8ceb-cf4c-44fb-ad5f-cab8087be9c8
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=312746079 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_c
orrupt_sig_fatal_chk.312746079
Directory /workspace/15.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/15.rom_ctrl_kmac_err_chk.2726521972
Short name T174
Test name
Test status
Simulation time 2645042630 ps
CPU time 18.04 seconds
Started May 09 12:37:27 PM PDT 24
Finished May 09 12:37:58 PM PDT 24
Peak memory 212556 kb
Host smart-9194dd8d-3dbc-480b-86c9-c62b1429533a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2726521972 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_kmac_err_chk.2726521972
Directory /workspace/15.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/15.rom_ctrl_max_throughput_chk.1538323384
Short name T218
Test name
Test status
Simulation time 98191879 ps
CPU time 5.53 seconds
Started May 09 12:37:13 PM PDT 24
Finished May 09 12:37:33 PM PDT 24
Peak memory 211640 kb
Host smart-12ea7159-0d72-4fdf-8114-6a7e5afbca6f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1538323384 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_max_throughput_chk.1538323384
Directory /workspace/15.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/15.rom_ctrl_stress_all.1479834013
Short name T215
Test name
Test status
Simulation time 37042919098 ps
CPU time 59.8 seconds
Started May 09 12:37:25 PM PDT 24
Finished May 09 12:38:38 PM PDT 24
Peak memory 217856 kb
Host smart-b7fe3da1-2de9-4fc4-a297-bbfebf1c1042
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1479834013 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 15.rom_ctrl_stress_all.1479834013
Directory /workspace/15.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/16.rom_ctrl_alert_test.1742498689
Short name T243
Test name
Test status
Simulation time 1821408983 ps
CPU time 12.96 seconds
Started May 09 12:37:22 PM PDT 24
Finished May 09 12:37:49 PM PDT 24
Peak memory 211612 kb
Host smart-02cb700a-0c31-46d0-b06c-80bb53c0c5d7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1742498689 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_alert_test.1742498689
Directory /workspace/16.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/16.rom_ctrl_corrupt_sig_fatal_chk.1176179126
Short name T239
Test name
Test status
Simulation time 89230182680 ps
CPU time 248.06 seconds
Started May 09 12:37:40 PM PDT 24
Finished May 09 12:41:59 PM PDT 24
Peak memory 237352 kb
Host smart-9e665e2f-f681-4ebf-8867-c4df0ee518ad
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1176179126 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_
corrupt_sig_fatal_chk.1176179126
Directory /workspace/16.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/16.rom_ctrl_kmac_err_chk.2433054144
Short name T2
Test name
Test status
Simulation time 1985094624 ps
CPU time 21.61 seconds
Started May 09 12:37:19 PM PDT 24
Finished May 09 12:37:56 PM PDT 24
Peak memory 211764 kb
Host smart-8ecdfcd8-3f75-4711-b5db-c32178dcd4ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2433054144 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_kmac_err_chk.2433054144
Directory /workspace/16.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/16.rom_ctrl_max_throughput_chk.417114365
Short name T203
Test name
Test status
Simulation time 1273001918 ps
CPU time 12.73 seconds
Started May 09 12:37:27 PM PDT 24
Finished May 09 12:37:53 PM PDT 24
Peak memory 211660 kb
Host smart-41b6fb17-5b51-4ee7-bebc-e167762e68ab
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=417114365 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_max_throughput_chk.417114365
Directory /workspace/16.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/16.rom_ctrl_smoke.408198867
Short name T180
Test name
Test status
Simulation time 2640213260 ps
CPU time 17.18 seconds
Started May 09 12:37:52 PM PDT 24
Finished May 09 12:38:20 PM PDT 24
Peak memory 219884 kb
Host smart-7c86c6fb-5634-4613-b955-6b314fda4556
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=408198867 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_smoke.408198867
Directory /workspace/16.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/16.rom_ctrl_stress_all.1060924079
Short name T313
Test name
Test status
Simulation time 42237519905 ps
CPU time 41.21 seconds
Started May 09 12:37:28 PM PDT 24
Finished May 09 12:38:22 PM PDT 24
Peak memory 219864 kb
Host smart-998c7080-c75e-4755-8f21-70758596c151
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1060924079 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 16.rom_ctrl_stress_all.1060924079
Directory /workspace/16.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/17.rom_ctrl_alert_test.71343454
Short name T307
Test name
Test status
Simulation time 171761187 ps
CPU time 4.12 seconds
Started May 09 12:37:35 PM PDT 24
Finished May 09 12:37:50 PM PDT 24
Peak memory 211716 kb
Host smart-525a1422-026b-43b1-8536-c6c067b852b5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71343454 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_alert_test.71343454
Directory /workspace/17.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/17.rom_ctrl_corrupt_sig_fatal_chk.613993864
Short name T331
Test name
Test status
Simulation time 196956284517 ps
CPU time 281.24 seconds
Started May 09 12:37:37 PM PDT 24
Finished May 09 12:42:29 PM PDT 24
Peak memory 221392 kb
Host smart-be273e9c-91e6-449e-a9b9-3190e01e1957
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=613993864 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_c
orrupt_sig_fatal_chk.613993864
Directory /workspace/17.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/17.rom_ctrl_kmac_err_chk.3163205454
Short name T196
Test name
Test status
Simulation time 7994177007 ps
CPU time 26.94 seconds
Started May 09 12:37:20 PM PDT 24
Finished May 09 12:38:01 PM PDT 24
Peak memory 212836 kb
Host smart-f6753db7-055d-46f6-baed-6b3d00b5287f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3163205454 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_kmac_err_chk.3163205454
Directory /workspace/17.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/17.rom_ctrl_max_throughput_chk.721765641
Short name T188
Test name
Test status
Simulation time 20295554869 ps
CPU time 16.71 seconds
Started May 09 12:37:30 PM PDT 24
Finished May 09 12:37:59 PM PDT 24
Peak memory 211740 kb
Host smart-7f6b97ef-3ef7-4aff-828b-4a4f83a779c9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=721765641 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_max_throughput_chk.721765641
Directory /workspace/17.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/17.rom_ctrl_smoke.2904529927
Short name T154
Test name
Test status
Simulation time 10236663925 ps
CPU time 24.06 seconds
Started May 09 12:38:30 PM PDT 24
Finished May 09 12:39:10 PM PDT 24
Peak memory 219588 kb
Host smart-0df9cb63-60d1-45c1-a97b-8ac8385ce042
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2904529927 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_smoke.2904529927
Directory /workspace/17.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/17.rom_ctrl_stress_all_with_rand_reset.3433508620
Short name T359
Test name
Test status
Simulation time 60535156146 ps
CPU time 1955.69 seconds
Started May 09 12:37:30 PM PDT 24
Finished May 09 01:10:19 PM PDT 24
Peak memory 239664 kb
Host smart-7eab74ae-683c-4846-80b8-63ef9e16dcee
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3433508620 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_stress_all_with_rand_reset.3433508620
Directory /workspace/17.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/18.rom_ctrl_alert_test.2575749871
Short name T197
Test name
Test status
Simulation time 1803572928 ps
CPU time 15 seconds
Started May 09 12:37:21 PM PDT 24
Finished May 09 12:37:50 PM PDT 24
Peak memory 211684 kb
Host smart-c29645e0-2407-42f4-a6c8-fb2abd4b1b6b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2575749871 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_alert_test.2575749871
Directory /workspace/18.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/18.rom_ctrl_corrupt_sig_fatal_chk.2280618031
Short name T133
Test name
Test status
Simulation time 83888742387 ps
CPU time 133.56 seconds
Started May 09 12:37:31 PM PDT 24
Finished May 09 12:39:57 PM PDT 24
Peak memory 230652 kb
Host smart-f1d12158-0f28-4157-ad35-851f4609acd4
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2280618031 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_
corrupt_sig_fatal_chk.2280618031
Directory /workspace/18.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/18.rom_ctrl_kmac_err_chk.2173185740
Short name T283
Test name
Test status
Simulation time 4062164161 ps
CPU time 31.68 seconds
Started May 09 12:37:37 PM PDT 24
Finished May 09 12:38:20 PM PDT 24
Peak memory 212424 kb
Host smart-6ed4a5f9-b2e7-4f9d-8eab-f7c8376760d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2173185740 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_kmac_err_chk.2173185740
Directory /workspace/18.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/18.rom_ctrl_max_throughput_chk.1939064735
Short name T94
Test name
Test status
Simulation time 184863903 ps
CPU time 6.86 seconds
Started May 09 12:37:56 PM PDT 24
Finished May 09 12:38:16 PM PDT 24
Peak memory 211504 kb
Host smart-1abf61d5-ad8b-4479-8a1c-dc89bfc37b97
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1939064735 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_max_throughput_chk.1939064735
Directory /workspace/18.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/18.rom_ctrl_smoke.673923663
Short name T163
Test name
Test status
Simulation time 2552415876 ps
CPU time 26.56 seconds
Started May 09 12:38:06 PM PDT 24
Finished May 09 12:38:51 PM PDT 24
Peak memory 212668 kb
Host smart-f688f08e-4a01-4dfb-9710-e196ad52f7f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=673923663 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_smoke.673923663
Directory /workspace/18.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/18.rom_ctrl_stress_all.2811815209
Short name T286
Test name
Test status
Simulation time 2123382803 ps
CPU time 17.72 seconds
Started May 09 12:37:35 PM PDT 24
Finished May 09 12:38:04 PM PDT 24
Peak memory 211536 kb
Host smart-5783be60-3e7f-4d15-bffe-f4c6efef58d4
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2811815209 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 18.rom_ctrl_stress_all.2811815209
Directory /workspace/18.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/19.rom_ctrl_alert_test.1635098970
Short name T158
Test name
Test status
Simulation time 1816377509 ps
CPU time 10.66 seconds
Started May 09 12:37:53 PM PDT 24
Finished May 09 12:38:15 PM PDT 24
Peak memory 211632 kb
Host smart-2e3205d0-30da-4334-980e-f1310b21bc97
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1635098970 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_alert_test.1635098970
Directory /workspace/19.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/19.rom_ctrl_corrupt_sig_fatal_chk.989936816
Short name T343
Test name
Test status
Simulation time 31189785559 ps
CPU time 311.99 seconds
Started May 09 12:37:37 PM PDT 24
Finished May 09 12:43:01 PM PDT 24
Peak memory 241364 kb
Host smart-d7cd8f3d-280a-43d5-ae96-88ece75eaeba
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=989936816 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_c
orrupt_sig_fatal_chk.989936816
Directory /workspace/19.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/19.rom_ctrl_kmac_err_chk.3935914329
Short name T132
Test name
Test status
Simulation time 345798707 ps
CPU time 11.92 seconds
Started May 09 12:37:54 PM PDT 24
Finished May 09 12:38:18 PM PDT 24
Peak memory 212980 kb
Host smart-fa6b81d9-89fd-49be-ac52-d96dac7c95ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3935914329 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_kmac_err_chk.3935914329
Directory /workspace/19.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/19.rom_ctrl_max_throughput_chk.2521108493
Short name T208
Test name
Test status
Simulation time 187278259 ps
CPU time 5.46 seconds
Started May 09 12:37:39 PM PDT 24
Finished May 09 12:37:55 PM PDT 24
Peak memory 211652 kb
Host smart-dfaa6543-33a4-471f-94b3-a7c6b290b2f0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2521108493 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_max_throughput_chk.2521108493
Directory /workspace/19.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/19.rom_ctrl_smoke.2077318327
Short name T167
Test name
Test status
Simulation time 363714258 ps
CPU time 12.22 seconds
Started May 09 12:37:26 PM PDT 24
Finished May 09 12:37:52 PM PDT 24
Peak memory 213748 kb
Host smart-e692beb9-00c8-408b-bf01-d411bd1691bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2077318327 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_smoke.2077318327
Directory /workspace/19.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/19.rom_ctrl_stress_all.3005237344
Short name T309
Test name
Test status
Simulation time 399365719 ps
CPU time 21.15 seconds
Started May 09 12:37:51 PM PDT 24
Finished May 09 12:38:22 PM PDT 24
Peak memory 219836 kb
Host smart-cb0303e5-b4d6-41dd-b96a-daff2070d682
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3005237344 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 19.rom_ctrl_stress_all.3005237344
Directory /workspace/19.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/2.rom_ctrl_alert_test.1559722842
Short name T128
Test name
Test status
Simulation time 85472989 ps
CPU time 4.31 seconds
Started May 09 12:37:44 PM PDT 24
Finished May 09 12:37:58 PM PDT 24
Peak memory 211704 kb
Host smart-68fb713b-6fd8-4083-bc70-ff2ffcd74732
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1559722842 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_alert_test.1559722842
Directory /workspace/2.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/2.rom_ctrl_corrupt_sig_fatal_chk.753132074
Short name T345
Test name
Test status
Simulation time 5963155952 ps
CPU time 70.41 seconds
Started May 09 12:37:16 PM PDT 24
Finished May 09 12:38:41 PM PDT 24
Peak memory 238244 kb
Host smart-449e892a-b4f2-4a3b-a943-9b5da0c1d9fb
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=753132074 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_co
rrupt_sig_fatal_chk.753132074
Directory /workspace/2.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/2.rom_ctrl_kmac_err_chk.3541850703
Short name T192
Test name
Test status
Simulation time 4477590027 ps
CPU time 29.4 seconds
Started May 09 12:37:11 PM PDT 24
Finished May 09 12:37:54 PM PDT 24
Peak memory 212548 kb
Host smart-b3bee132-20a3-4194-af99-47d73c44d280
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3541850703 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_kmac_err_chk.3541850703
Directory /workspace/2.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/2.rom_ctrl_max_throughput_chk.234842773
Short name T353
Test name
Test status
Simulation time 2397126141 ps
CPU time 12.14 seconds
Started May 09 12:37:21 PM PDT 24
Finished May 09 12:37:48 PM PDT 24
Peak memory 211756 kb
Host smart-c002ec8d-31fa-4b01-9749-63fa1532641b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=234842773 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_max_throughput_chk.234842773
Directory /workspace/2.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/2.rom_ctrl_sec_cm.852994602
Short name T31
Test name
Test status
Simulation time 1198657948 ps
CPU time 97.92 seconds
Started May 09 12:38:30 PM PDT 24
Finished May 09 12:40:24 PM PDT 24
Peak memory 236800 kb
Host smart-4e2405d4-e8a8-4974-92ec-df8b137cb9e3
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=852994602 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_sec_cm.852994602
Directory /workspace/2.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/2.rom_ctrl_smoke.1923471144
Short name T325
Test name
Test status
Simulation time 2318102538 ps
CPU time 15.05 seconds
Started May 09 12:37:21 PM PDT 24
Finished May 09 12:37:51 PM PDT 24
Peak memory 219944 kb
Host smart-51e6c8e3-e332-4522-aeed-86a721e0ab16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1923471144 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_smoke.1923471144
Directory /workspace/2.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/2.rom_ctrl_stress_all.4024529283
Short name T175
Test name
Test status
Simulation time 32518699447 ps
CPU time 75.48 seconds
Started May 09 12:38:30 PM PDT 24
Finished May 09 12:40:02 PM PDT 24
Peak memory 217468 kb
Host smart-eff22b4a-5e4b-446a-baa1-d9d5fabdbf76
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4024529283 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 2.rom_ctrl_stress_all.4024529283
Directory /workspace/2.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/2.rom_ctrl_stress_all_with_rand_reset.3168293318
Short name T356
Test name
Test status
Simulation time 278298991594 ps
CPU time 2231.82 seconds
Started May 09 12:37:19 PM PDT 24
Finished May 09 01:14:45 PM PDT 24
Peak memory 238788 kb
Host smart-b53510ad-5946-4616-9bba-5283fbd12639
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3168293318 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_stress_all_with_rand_reset.3168293318
Directory /workspace/2.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.rom_ctrl_alert_test.4171919220
Short name T273
Test name
Test status
Simulation time 1011057416 ps
CPU time 10.47 seconds
Started May 09 12:37:25 PM PDT 24
Finished May 09 12:37:49 PM PDT 24
Peak memory 211700 kb
Host smart-3e503a66-5fcc-4875-b779-dca00782c0f3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4171919220 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_alert_test.4171919220
Directory /workspace/20.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/20.rom_ctrl_corrupt_sig_fatal_chk.3280834663
Short name T96
Test name
Test status
Simulation time 20800518892 ps
CPU time 260.65 seconds
Started May 09 12:37:45 PM PDT 24
Finished May 09 12:42:15 PM PDT 24
Peak memory 238188 kb
Host smart-9c401214-b9e2-4582-9fb1-2d4a6f5bf949
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3280834663 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_
corrupt_sig_fatal_chk.3280834663
Directory /workspace/20.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/20.rom_ctrl_kmac_err_chk.1877127801
Short name T124
Test name
Test status
Simulation time 5666853217 ps
CPU time 24.51 seconds
Started May 09 12:37:25 PM PDT 24
Finished May 09 12:38:04 PM PDT 24
Peak memory 212828 kb
Host smart-76a6cbdf-2259-459d-88b3-70aff7936e80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1877127801 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_kmac_err_chk.1877127801
Directory /workspace/20.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/20.rom_ctrl_max_throughput_chk.867438204
Short name T209
Test name
Test status
Simulation time 2211294826 ps
CPU time 18.39 seconds
Started May 09 12:37:36 PM PDT 24
Finished May 09 12:38:05 PM PDT 24
Peak memory 211764 kb
Host smart-5dd42bb4-cc86-44a3-b263-3adcf862f7ed
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=867438204 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_max_throughput_chk.867438204
Directory /workspace/20.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/20.rom_ctrl_smoke.296635640
Short name T282
Test name
Test status
Simulation time 3159221414 ps
CPU time 30.18 seconds
Started May 09 12:37:23 PM PDT 24
Finished May 09 12:38:08 PM PDT 24
Peak memory 213784 kb
Host smart-91b88779-30cf-4044-be82-722cc7e00e23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=296635640 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_smoke.296635640
Directory /workspace/20.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/20.rom_ctrl_stress_all.3903447376
Short name T42
Test name
Test status
Simulation time 53836647013 ps
CPU time 31.51 seconds
Started May 09 12:37:42 PM PDT 24
Finished May 09 12:38:24 PM PDT 24
Peak memory 219924 kb
Host smart-2ee28761-6689-4767-8475-e91c19b3424d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3903447376 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 20.rom_ctrl_stress_all.3903447376
Directory /workspace/20.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/20.rom_ctrl_stress_all_with_rand_reset.2440750724
Short name T302
Test name
Test status
Simulation time 27177997824 ps
CPU time 1071.84 seconds
Started May 09 12:37:50 PM PDT 24
Finished May 09 12:55:52 PM PDT 24
Peak memory 236456 kb
Host smart-952734b0-9e88-4a95-a3a5-f06e9186bdb0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2440750724 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_stress_all_with_rand_reset.2440750724
Directory /workspace/20.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/21.rom_ctrl_alert_test.471592470
Short name T259
Test name
Test status
Simulation time 709444726 ps
CPU time 8.78 seconds
Started May 09 12:37:35 PM PDT 24
Finished May 09 12:37:55 PM PDT 24
Peak memory 211720 kb
Host smart-25a75de1-bbef-457d-8d70-865297679b50
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=471592470 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_alert_test.471592470
Directory /workspace/21.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/21.rom_ctrl_corrupt_sig_fatal_chk.1171711614
Short name T98
Test name
Test status
Simulation time 23169795649 ps
CPU time 119.99 seconds
Started May 09 12:37:34 PM PDT 24
Finished May 09 12:39:45 PM PDT 24
Peak memory 222732 kb
Host smart-5785c68b-f964-45c8-8af4-6ec7bad85116
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1171711614 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_
corrupt_sig_fatal_chk.1171711614
Directory /workspace/21.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/21.rom_ctrl_kmac_err_chk.2925096006
Short name T253
Test name
Test status
Simulation time 11233684677 ps
CPU time 17.4 seconds
Started May 09 12:37:24 PM PDT 24
Finished May 09 12:37:55 PM PDT 24
Peak memory 212796 kb
Host smart-996995fe-60dc-4a4b-9557-a31ce35d0b84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2925096006 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_kmac_err_chk.2925096006
Directory /workspace/21.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/21.rom_ctrl_max_throughput_chk.374493545
Short name T150
Test name
Test status
Simulation time 24946304698 ps
CPU time 16.48 seconds
Started May 09 12:37:50 PM PDT 24
Finished May 09 12:38:16 PM PDT 24
Peak memory 211620 kb
Host smart-57db527f-9a6d-48e2-9555-0b27360bdd32
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=374493545 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_max_throughput_chk.374493545
Directory /workspace/21.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/21.rom_ctrl_smoke.2569767233
Short name T267
Test name
Test status
Simulation time 1670072887 ps
CPU time 22.93 seconds
Started May 09 12:37:34 PM PDT 24
Finished May 09 12:38:08 PM PDT 24
Peak memory 219876 kb
Host smart-1aba2a6b-f9b2-40b2-a5b9-0efafa8ff29e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2569767233 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_smoke.2569767233
Directory /workspace/21.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/21.rom_ctrl_stress_all.4136858849
Short name T144
Test name
Test status
Simulation time 2651521885 ps
CPU time 19.05 seconds
Started May 09 12:37:34 PM PDT 24
Finished May 09 12:38:04 PM PDT 24
Peak memory 219908 kb
Host smart-a87bc60d-4d81-4c1c-af55-48dfca636692
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4136858849 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 21.rom_ctrl_stress_all.4136858849
Directory /workspace/21.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/22.rom_ctrl_alert_test.3296661846
Short name T171
Test name
Test status
Simulation time 255553659 ps
CPU time 6.03 seconds
Started May 09 12:38:03 PM PDT 24
Finished May 09 12:38:25 PM PDT 24
Peak memory 211712 kb
Host smart-7620d4ca-79e5-46a9-8b50-3e0708312b96
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3296661846 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_alert_test.3296661846
Directory /workspace/22.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/22.rom_ctrl_corrupt_sig_fatal_chk.3487133096
Short name T46
Test name
Test status
Simulation time 6953624745 ps
CPU time 158.58 seconds
Started May 09 12:37:33 PM PDT 24
Finished May 09 12:40:23 PM PDT 24
Peak memory 225636 kb
Host smart-6ec1dcaa-c5a5-4acf-a3de-25f39a694450
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3487133096 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_
corrupt_sig_fatal_chk.3487133096
Directory /workspace/22.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/22.rom_ctrl_kmac_err_chk.623819198
Short name T301
Test name
Test status
Simulation time 519586116 ps
CPU time 11.05 seconds
Started May 09 12:37:53 PM PDT 24
Finished May 09 12:38:15 PM PDT 24
Peak memory 211748 kb
Host smart-1acc4c18-5b19-4bf1-a4bc-dcaf2cb7b952
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=623819198 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_kmac_err_chk.623819198
Directory /workspace/22.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/22.rom_ctrl_max_throughput_chk.3923147517
Short name T355
Test name
Test status
Simulation time 829056824 ps
CPU time 8.13 seconds
Started May 09 12:37:43 PM PDT 24
Finished May 09 12:38:01 PM PDT 24
Peak memory 211656 kb
Host smart-5a373720-e783-47a7-a64b-7a0ff7d6b0b1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3923147517 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_max_throughput_chk.3923147517
Directory /workspace/22.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/22.rom_ctrl_smoke.1828306895
Short name T274
Test name
Test status
Simulation time 2006494936 ps
CPU time 21.06 seconds
Started May 09 12:37:34 PM PDT 24
Finished May 09 12:38:07 PM PDT 24
Peak memory 219820 kb
Host smart-8e67a116-2537-4649-b995-173a98946f4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1828306895 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_smoke.1828306895
Directory /workspace/22.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/22.rom_ctrl_stress_all.3527652501
Short name T142
Test name
Test status
Simulation time 15939154797 ps
CPU time 20.08 seconds
Started May 09 12:37:47 PM PDT 24
Finished May 09 12:38:17 PM PDT 24
Peak memory 212924 kb
Host smart-feee56e6-c8c2-4ff5-b67b-506779d90bb8
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3527652501 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 22.rom_ctrl_stress_all.3527652501
Directory /workspace/22.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/22.rom_ctrl_stress_all_with_rand_reset.4027893666
Short name T54
Test name
Test status
Simulation time 29715707646 ps
CPU time 1200.09 seconds
Started May 09 12:37:32 PM PDT 24
Finished May 09 12:57:45 PM PDT 24
Peak memory 232564 kb
Host smart-d1bfe41f-4616-476e-a4ba-19a750d01f83
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4027893666 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_stress_all_with_rand_reset.4027893666
Directory /workspace/22.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/23.rom_ctrl_alert_test.2658773694
Short name T290
Test name
Test status
Simulation time 1222986037 ps
CPU time 6.99 seconds
Started May 09 12:37:33 PM PDT 24
Finished May 09 12:37:52 PM PDT 24
Peak memory 211712 kb
Host smart-ba881820-26a3-4067-b782-909391b1d197
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2658773694 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_alert_test.2658773694
Directory /workspace/23.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/23.rom_ctrl_corrupt_sig_fatal_chk.415423602
Short name T228
Test name
Test status
Simulation time 133472721964 ps
CPU time 144.96 seconds
Started May 09 12:37:30 PM PDT 24
Finished May 09 12:40:08 PM PDT 24
Peak memory 213068 kb
Host smart-7d11e1b3-24f2-428d-aea5-097f6a8e14af
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=415423602 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_c
orrupt_sig_fatal_chk.415423602
Directory /workspace/23.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/23.rom_ctrl_kmac_err_chk.2962789091
Short name T181
Test name
Test status
Simulation time 3695546937 ps
CPU time 21.25 seconds
Started May 09 12:37:31 PM PDT 24
Finished May 09 12:38:04 PM PDT 24
Peak memory 212512 kb
Host smart-d8228bd5-e53d-421b-922b-1f013c78404e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2962789091 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_kmac_err_chk.2962789091
Directory /workspace/23.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/23.rom_ctrl_max_throughput_chk.1684508679
Short name T339
Test name
Test status
Simulation time 1390436119 ps
CPU time 13.39 seconds
Started May 09 12:37:33 PM PDT 24
Finished May 09 12:37:58 PM PDT 24
Peak memory 211624 kb
Host smart-a0ce4bcc-83ec-4e5a-bf81-fdbc3a56de38
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1684508679 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_max_throughput_chk.1684508679
Directory /workspace/23.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/23.rom_ctrl_smoke.1052028826
Short name T362
Test name
Test status
Simulation time 1968637205 ps
CPU time 21.49 seconds
Started May 09 12:37:27 PM PDT 24
Finished May 09 12:38:02 PM PDT 24
Peak memory 213344 kb
Host smart-79cd2973-b4a9-41ad-8e70-36e7f63de5ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1052028826 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_smoke.1052028826
Directory /workspace/23.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/23.rom_ctrl_stress_all.1128136503
Short name T303
Test name
Test status
Simulation time 377076841 ps
CPU time 22.03 seconds
Started May 09 12:37:43 PM PDT 24
Finished May 09 12:38:16 PM PDT 24
Peak memory 219824 kb
Host smart-79da21a2-48a2-48f4-8736-396313f53043
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1128136503 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 23.rom_ctrl_stress_all.1128136503
Directory /workspace/23.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/23.rom_ctrl_stress_all_with_rand_reset.1225967352
Short name T109
Test name
Test status
Simulation time 145445133323 ps
CPU time 4059.83 seconds
Started May 09 12:37:25 PM PDT 24
Finished May 09 01:45:19 PM PDT 24
Peak memory 236416 kb
Host smart-101682d6-c841-49de-b917-c5a80e260122
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1225967352 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_stress_all_with_rand_reset.1225967352
Directory /workspace/23.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/24.rom_ctrl_alert_test.2784486622
Short name T281
Test name
Test status
Simulation time 988589767 ps
CPU time 10.21 seconds
Started May 09 12:37:33 PM PDT 24
Finished May 09 12:37:55 PM PDT 24
Peak memory 211700 kb
Host smart-34eece27-1f77-4056-93ed-be16f2d80983
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2784486622 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_alert_test.2784486622
Directory /workspace/24.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/24.rom_ctrl_corrupt_sig_fatal_chk.1718668658
Short name T24
Test name
Test status
Simulation time 51168985398 ps
CPU time 247.27 seconds
Started May 09 12:37:44 PM PDT 24
Finished May 09 12:42:06 PM PDT 24
Peak memory 237652 kb
Host smart-f1729b75-dd3a-4960-91d0-9340f920306d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1718668658 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_
corrupt_sig_fatal_chk.1718668658
Directory /workspace/24.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/24.rom_ctrl_kmac_err_chk.3844408920
Short name T160
Test name
Test status
Simulation time 2567223530 ps
CPU time 23.76 seconds
Started May 09 12:37:40 PM PDT 24
Finished May 09 12:38:14 PM PDT 24
Peak memory 212448 kb
Host smart-9ae4b42b-aa8a-4ad3-8f2b-150706cd7f46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3844408920 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_kmac_err_chk.3844408920
Directory /workspace/24.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/24.rom_ctrl_max_throughput_chk.50956695
Short name T312
Test name
Test status
Simulation time 2593445262 ps
CPU time 13.1 seconds
Started May 09 12:37:35 PM PDT 24
Finished May 09 12:37:59 PM PDT 24
Peak memory 211772 kb
Host smart-a3d33034-edab-46ba-b637-a76b0bedac71
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=50956695 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_max_throughput_chk.50956695
Directory /workspace/24.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/24.rom_ctrl_smoke.1347152429
Short name T176
Test name
Test status
Simulation time 3670784638 ps
CPU time 34.7 seconds
Started May 09 12:37:52 PM PDT 24
Finished May 09 12:38:37 PM PDT 24
Peak memory 219956 kb
Host smart-49ed7d36-fc5c-4b0a-afaf-712296e7220f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1347152429 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_smoke.1347152429
Directory /workspace/24.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/24.rom_ctrl_stress_all.3629806434
Short name T246
Test name
Test status
Simulation time 18552956003 ps
CPU time 49.67 seconds
Started May 09 12:37:45 PM PDT 24
Finished May 09 12:38:44 PM PDT 24
Peak memory 214768 kb
Host smart-1ba643fc-c539-402e-9a94-dcf5682c4723
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3629806434 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 24.rom_ctrl_stress_all.3629806434
Directory /workspace/24.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/25.rom_ctrl_alert_test.1424286923
Short name T201
Test name
Test status
Simulation time 5450648616 ps
CPU time 14.23 seconds
Started May 09 12:37:31 PM PDT 24
Finished May 09 12:37:57 PM PDT 24
Peak memory 211732 kb
Host smart-3e7a92d3-7f7e-482e-854b-805e8cd1fda2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1424286923 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_alert_test.1424286923
Directory /workspace/25.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/25.rom_ctrl_corrupt_sig_fatal_chk.417679783
Short name T360
Test name
Test status
Simulation time 1957139388 ps
CPU time 108.19 seconds
Started May 09 12:37:31 PM PDT 24
Finished May 09 12:39:31 PM PDT 24
Peak memory 229152 kb
Host smart-976f0afd-a529-4cbf-bd62-de3e2a81cceb
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=417679783 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_c
orrupt_sig_fatal_chk.417679783
Directory /workspace/25.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/25.rom_ctrl_kmac_err_chk.261811785
Short name T148
Test name
Test status
Simulation time 7259064360 ps
CPU time 24.65 seconds
Started May 09 12:37:31 PM PDT 24
Finished May 09 12:38:08 PM PDT 24
Peak memory 213552 kb
Host smart-9ddc231a-ba2a-440b-8ee2-a11ee8a552bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=261811785 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_kmac_err_chk.261811785
Directory /workspace/25.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/25.rom_ctrl_max_throughput_chk.571003657
Short name T204
Test name
Test status
Simulation time 489424793 ps
CPU time 5.77 seconds
Started May 09 12:37:38 PM PDT 24
Finished May 09 12:37:55 PM PDT 24
Peak memory 211660 kb
Host smart-aec9ae73-20a5-44f5-938a-e2d63bf8a15a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=571003657 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_max_throughput_chk.571003657
Directory /workspace/25.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/25.rom_ctrl_smoke.3760900681
Short name T234
Test name
Test status
Simulation time 4683557109 ps
CPU time 14.44 seconds
Started May 09 12:37:26 PM PDT 24
Finished May 09 12:37:54 PM PDT 24
Peak memory 214100 kb
Host smart-653b7af6-fb62-4555-b34e-00ca2168f670
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3760900681 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_smoke.3760900681
Directory /workspace/25.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/25.rom_ctrl_stress_all.876930195
Short name T78
Test name
Test status
Simulation time 2747141651 ps
CPU time 29.53 seconds
Started May 09 12:37:44 PM PDT 24
Finished May 09 12:38:23 PM PDT 24
Peak memory 219904 kb
Host smart-5e193c6d-7d7f-4dd9-b0c1-1fcd4cc29d8e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=876930195 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 25.rom_ctrl_stress_all.876930195
Directory /workspace/25.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/26.rom_ctrl_alert_test.1021933798
Short name T348
Test name
Test status
Simulation time 3544277598 ps
CPU time 9.28 seconds
Started May 09 12:37:39 PM PDT 24
Finished May 09 12:37:59 PM PDT 24
Peak memory 211820 kb
Host smart-9f08265d-a263-446f-bf56-ea6a4c43a03a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1021933798 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_alert_test.1021933798
Directory /workspace/26.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/26.rom_ctrl_corrupt_sig_fatal_chk.2151197266
Short name T293
Test name
Test status
Simulation time 2530560928 ps
CPU time 151.33 seconds
Started May 09 12:37:31 PM PDT 24
Finished May 09 12:40:14 PM PDT 24
Peak memory 233448 kb
Host smart-1db0301a-7a34-4bc6-acdb-13c877f2cf0f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2151197266 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_
corrupt_sig_fatal_chk.2151197266
Directory /workspace/26.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/26.rom_ctrl_max_throughput_chk.2015245449
Short name T108
Test name
Test status
Simulation time 7937427355 ps
CPU time 16.91 seconds
Started May 09 12:37:44 PM PDT 24
Finished May 09 12:38:11 PM PDT 24
Peak memory 211728 kb
Host smart-6bb14143-968b-4626-a561-eb3b0498830e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2015245449 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_max_throughput_chk.2015245449
Directory /workspace/26.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/26.rom_ctrl_smoke.1395893658
Short name T321
Test name
Test status
Simulation time 1416265968 ps
CPU time 14.87 seconds
Started May 09 12:37:46 PM PDT 24
Finished May 09 12:38:10 PM PDT 24
Peak memory 214244 kb
Host smart-da9611bb-c248-42a7-a0f1-54c6ae3ca969
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1395893658 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_smoke.1395893658
Directory /workspace/26.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/26.rom_ctrl_stress_all.3600289446
Short name T77
Test name
Test status
Simulation time 32271228473 ps
CPU time 74.73 seconds
Started May 09 12:37:47 PM PDT 24
Finished May 09 12:39:11 PM PDT 24
Peak memory 219912 kb
Host smart-6e159637-890b-4db8-9853-070270ca40d2
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3600289446 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 26.rom_ctrl_stress_all.3600289446
Directory /workspace/26.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/26.rom_ctrl_stress_all_with_rand_reset.4063579956
Short name T11
Test name
Test status
Simulation time 63423635110 ps
CPU time 9106.07 seconds
Started May 09 12:37:33 PM PDT 24
Finished May 09 03:09:31 PM PDT 24
Peak memory 233316 kb
Host smart-cdf70938-658e-45cc-8312-18512e5d46cd
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4063579956 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_stress_all_with_rand_reset.4063579956
Directory /workspace/26.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/27.rom_ctrl_alert_test.171755138
Short name T330
Test name
Test status
Simulation time 754329445 ps
CPU time 4.14 seconds
Started May 09 12:37:32 PM PDT 24
Finished May 09 12:37:49 PM PDT 24
Peak memory 211676 kb
Host smart-03090536-1cdf-4174-b6ae-6ab3de8c42e0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=171755138 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_alert_test.171755138
Directory /workspace/27.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/27.rom_ctrl_corrupt_sig_fatal_chk.1626726809
Short name T231
Test name
Test status
Simulation time 26962917813 ps
CPU time 240.58 seconds
Started May 09 12:37:42 PM PDT 24
Finished May 09 12:41:52 PM PDT 24
Peak memory 237336 kb
Host smart-19cce6e6-d02a-4c30-b940-c40d9475dbc3
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1626726809 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_
corrupt_sig_fatal_chk.1626726809
Directory /workspace/27.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/27.rom_ctrl_kmac_err_chk.3428327599
Short name T22
Test name
Test status
Simulation time 341384603 ps
CPU time 9.2 seconds
Started May 09 12:37:47 PM PDT 24
Finished May 09 12:38:06 PM PDT 24
Peak memory 211732 kb
Host smart-6aa632db-00ce-4ec6-b03b-d1ef217fcdf4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3428327599 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_kmac_err_chk.3428327599
Directory /workspace/27.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/27.rom_ctrl_max_throughput_chk.2475393293
Short name T255
Test name
Test status
Simulation time 2624614225 ps
CPU time 12.78 seconds
Started May 09 12:37:40 PM PDT 24
Finished May 09 12:38:03 PM PDT 24
Peak memory 211740 kb
Host smart-ca5bc5cc-591f-44da-bac8-640af76fa8cc
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2475393293 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_max_throughput_chk.2475393293
Directory /workspace/27.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/27.rom_ctrl_stress_all.1837891415
Short name T5
Test name
Test status
Simulation time 3438625370 ps
CPU time 29.48 seconds
Started May 09 12:37:34 PM PDT 24
Finished May 09 12:38:15 PM PDT 24
Peak memory 219960 kb
Host smart-4ec91534-2f7d-412b-8389-f9120e85da6a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1837891415 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 27.rom_ctrl_stress_all.1837891415
Directory /workspace/27.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/28.rom_ctrl_alert_test.1622167415
Short name T217
Test name
Test status
Simulation time 1280397991 ps
CPU time 11.43 seconds
Started May 09 12:37:24 PM PDT 24
Finished May 09 12:37:49 PM PDT 24
Peak memory 211620 kb
Host smart-35deb13f-86c6-4192-a17e-535066390927
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1622167415 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_alert_test.1622167415
Directory /workspace/28.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/28.rom_ctrl_corrupt_sig_fatal_chk.3327351675
Short name T183
Test name
Test status
Simulation time 10460629276 ps
CPU time 120.61 seconds
Started May 09 12:37:31 PM PDT 24
Finished May 09 12:39:44 PM PDT 24
Peak memory 237608 kb
Host smart-dccc4e24-8750-465a-ba2e-1944ce48b626
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3327351675 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_
corrupt_sig_fatal_chk.3327351675
Directory /workspace/28.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/28.rom_ctrl_kmac_err_chk.2855677822
Short name T334
Test name
Test status
Simulation time 2131334986 ps
CPU time 21.7 seconds
Started May 09 12:37:25 PM PDT 24
Finished May 09 12:38:00 PM PDT 24
Peak memory 212456 kb
Host smart-9391b526-75ec-4802-93cc-e2ea46ed0441
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2855677822 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_kmac_err_chk.2855677822
Directory /workspace/28.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/28.rom_ctrl_max_throughput_chk.350861428
Short name T191
Test name
Test status
Simulation time 2914445088 ps
CPU time 13.64 seconds
Started May 09 12:37:45 PM PDT 24
Finished May 09 12:38:09 PM PDT 24
Peak memory 211744 kb
Host smart-a8bada50-8240-4d0a-86d0-51c7b0105179
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=350861428 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_max_throughput_chk.350861428
Directory /workspace/28.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/28.rom_ctrl_smoke.1026385411
Short name T14
Test name
Test status
Simulation time 3852225823 ps
CPU time 16.58 seconds
Started May 09 12:37:29 PM PDT 24
Finished May 09 12:37:58 PM PDT 24
Peak memory 214172 kb
Host smart-0f85d199-3df0-4276-b8fc-7f74f5297da8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1026385411 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_smoke.1026385411
Directory /workspace/28.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/28.rom_ctrl_stress_all.4149806641
Short name T275
Test name
Test status
Simulation time 899943550 ps
CPU time 25.13 seconds
Started May 09 12:37:35 PM PDT 24
Finished May 09 12:38:12 PM PDT 24
Peak memory 215340 kb
Host smart-f2f70dfb-9a5d-4301-b8ff-3f4dd4bdb053
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4149806641 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 28.rom_ctrl_stress_all.4149806641
Directory /workspace/28.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/29.rom_ctrl_alert_test.623128488
Short name T327
Test name
Test status
Simulation time 11902756497 ps
CPU time 16.48 seconds
Started May 09 12:37:34 PM PDT 24
Finished May 09 12:38:02 PM PDT 24
Peak memory 211872 kb
Host smart-35e9e0d4-6a27-477f-b153-debef3987407
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=623128488 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_alert_test.623128488
Directory /workspace/29.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/29.rom_ctrl_corrupt_sig_fatal_chk.3687545616
Short name T250
Test name
Test status
Simulation time 80571800656 ps
CPU time 144.13 seconds
Started May 09 12:37:50 PM PDT 24
Finished May 09 12:40:24 PM PDT 24
Peak memory 220492 kb
Host smart-d4e8aeac-9cc2-44a4-8c48-693ccc282f32
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3687545616 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_
corrupt_sig_fatal_chk.3687545616
Directory /workspace/29.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/29.rom_ctrl_kmac_err_chk.2602509193
Short name T45
Test name
Test status
Simulation time 12859830483 ps
CPU time 30.11 seconds
Started May 09 12:37:46 PM PDT 24
Finished May 09 12:38:26 PM PDT 24
Peak memory 212628 kb
Host smart-15326f8b-b013-4d12-94ce-27ebe9de05ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2602509193 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_kmac_err_chk.2602509193
Directory /workspace/29.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/29.rom_ctrl_max_throughput_chk.2172263643
Short name T350
Test name
Test status
Simulation time 425193153 ps
CPU time 8.33 seconds
Started May 09 12:37:49 PM PDT 24
Finished May 09 12:38:07 PM PDT 24
Peak memory 211544 kb
Host smart-2e05460d-939c-4194-bb8b-eac967aaaf99
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2172263643 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_max_throughput_chk.2172263643
Directory /workspace/29.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/29.rom_ctrl_smoke.2133599762
Short name T131
Test name
Test status
Simulation time 433021414 ps
CPU time 12.58 seconds
Started May 09 12:37:36 PM PDT 24
Finished May 09 12:37:59 PM PDT 24
Peak memory 219844 kb
Host smart-b74a1513-c7cb-4fb2-bc93-a07e3b16fbdf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2133599762 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_smoke.2133599762
Directory /workspace/29.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/29.rom_ctrl_stress_all.3980467219
Short name T64
Test name
Test status
Simulation time 15983735226 ps
CPU time 39.44 seconds
Started May 09 12:37:36 PM PDT 24
Finished May 09 12:38:27 PM PDT 24
Peak memory 214548 kb
Host smart-df9fa7cd-7d12-4599-a481-417c71c18edf
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3980467219 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 29.rom_ctrl_stress_all.3980467219
Directory /workspace/29.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/3.rom_ctrl_alert_test.605210042
Short name T200
Test name
Test status
Simulation time 3973765570 ps
CPU time 10.44 seconds
Started May 09 12:37:08 PM PDT 24
Finished May 09 12:37:31 PM PDT 24
Peak memory 211744 kb
Host smart-a041a019-240e-44fd-a09a-09c3b08dc843
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=605210042 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_alert_test.605210042
Directory /workspace/3.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/3.rom_ctrl_corrupt_sig_fatal_chk.2676599310
Short name T162
Test name
Test status
Simulation time 139163562846 ps
CPU time 291.31 seconds
Started May 09 12:38:10 PM PDT 24
Finished May 09 12:43:20 PM PDT 24
Peak memory 230248 kb
Host smart-ed2195a1-5861-47eb-87a9-c11f97c0dc9d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2676599310 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_c
orrupt_sig_fatal_chk.2676599310
Directory /workspace/3.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/3.rom_ctrl_kmac_err_chk.3035173284
Short name T165
Test name
Test status
Simulation time 7757016021 ps
CPU time 31.1 seconds
Started May 09 12:37:12 PM PDT 24
Finished May 09 12:37:58 PM PDT 24
Peak memory 213852 kb
Host smart-0400147c-f817-4e79-8edd-965ef2faeabb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3035173284 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_kmac_err_chk.3035173284
Directory /workspace/3.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/3.rom_ctrl_max_throughput_chk.568419824
Short name T95
Test name
Test status
Simulation time 24270409831 ps
CPU time 16.07 seconds
Started May 09 12:38:26 PM PDT 24
Finished May 09 12:38:58 PM PDT 24
Peak memory 211268 kb
Host smart-c40354df-1a1d-45cd-800b-cef275f529f2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=568419824 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_max_throughput_chk.568419824
Directory /workspace/3.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/3.rom_ctrl_smoke.2106910101
Short name T264
Test name
Test status
Simulation time 1344678004 ps
CPU time 19.07 seconds
Started May 09 12:38:30 PM PDT 24
Finished May 09 12:39:06 PM PDT 24
Peak memory 219520 kb
Host smart-b910ebe3-c49f-44f0-96c8-29d9299050cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2106910101 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_smoke.2106910101
Directory /workspace/3.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/3.rom_ctrl_stress_all.3206634118
Short name T238
Test name
Test status
Simulation time 17025929911 ps
CPU time 64.18 seconds
Started May 09 12:37:25 PM PDT 24
Finished May 09 12:38:43 PM PDT 24
Peak memory 217680 kb
Host smart-b03e0417-c7c4-4a28-8ef0-bd5535546133
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3206634118 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 3.rom_ctrl_stress_all.3206634118
Directory /workspace/3.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/3.rom_ctrl_stress_all_with_rand_reset.2756440268
Short name T39
Test name
Test status
Simulation time 106914581267 ps
CPU time 3904.92 seconds
Started May 09 12:37:17 PM PDT 24
Finished May 09 01:42:42 PM PDT 24
Peak memory 247880 kb
Host smart-c7b0286e-16dd-4b14-bfde-67d88e6045fd
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2756440268 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_stress_all_with_rand_reset.2756440268
Directory /workspace/3.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.rom_ctrl_alert_test.1455408845
Short name T139
Test name
Test status
Simulation time 786746868 ps
CPU time 9.15 seconds
Started May 09 12:37:50 PM PDT 24
Finished May 09 12:38:09 PM PDT 24
Peak memory 211656 kb
Host smart-a030faad-6bab-43c2-8fba-0010bf9ce928
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1455408845 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_alert_test.1455408845
Directory /workspace/30.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/30.rom_ctrl_corrupt_sig_fatal_chk.760430451
Short name T304
Test name
Test status
Simulation time 6171597792 ps
CPU time 147.21 seconds
Started May 09 12:37:41 PM PDT 24
Finished May 09 12:40:19 PM PDT 24
Peak memory 231296 kb
Host smart-829f8744-ff61-44bf-b4fe-906dd5bfbefa
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=760430451 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_c
orrupt_sig_fatal_chk.760430451
Directory /workspace/30.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/30.rom_ctrl_kmac_err_chk.114636727
Short name T299
Test name
Test status
Simulation time 17505470643 ps
CPU time 34.03 seconds
Started May 09 12:37:41 PM PDT 24
Finished May 09 12:38:26 PM PDT 24
Peak memory 212616 kb
Host smart-d3e3cd1a-5064-4b0b-b63a-6ce49dfa959f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=114636727 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_kmac_err_chk.114636727
Directory /workspace/30.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/30.rom_ctrl_max_throughput_chk.4159836125
Short name T336
Test name
Test status
Simulation time 575930512 ps
CPU time 5.28 seconds
Started May 09 12:38:43 PM PDT 24
Finished May 09 12:39:05 PM PDT 24
Peak memory 211172 kb
Host smart-54ee03b7-e2e8-41c3-833b-45e8747bef9a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4159836125 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_max_throughput_chk.4159836125
Directory /workspace/30.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/30.rom_ctrl_smoke.2125126525
Short name T338
Test name
Test status
Simulation time 350114867 ps
CPU time 11.88 seconds
Started May 09 12:38:43 PM PDT 24
Finished May 09 12:39:12 PM PDT 24
Peak memory 213072 kb
Host smart-559c4574-778e-4715-9ad0-df80e5f2f1cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2125126525 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_smoke.2125126525
Directory /workspace/30.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/30.rom_ctrl_stress_all.2414181999
Short name T214
Test name
Test status
Simulation time 7115834056 ps
CPU time 53.74 seconds
Started May 09 12:37:39 PM PDT 24
Finished May 09 12:38:43 PM PDT 24
Peak memory 213548 kb
Host smart-5f531b1f-3ac1-4726-93a7-56c8bded303a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2414181999 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 30.rom_ctrl_stress_all.2414181999
Directory /workspace/30.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/31.rom_ctrl_alert_test.4276350233
Short name T168
Test name
Test status
Simulation time 1147154531 ps
CPU time 11.56 seconds
Started May 09 12:37:39 PM PDT 24
Finished May 09 12:38:01 PM PDT 24
Peak memory 211700 kb
Host smart-fbd21c1e-d155-4d71-968d-a0fa17d0b96c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4276350233 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_alert_test.4276350233
Directory /workspace/31.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/31.rom_ctrl_corrupt_sig_fatal_chk.640578374
Short name T265
Test name
Test status
Simulation time 1636897746 ps
CPU time 99.85 seconds
Started May 09 12:37:50 PM PDT 24
Finished May 09 12:39:40 PM PDT 24
Peak memory 239256 kb
Host smart-c82c031c-a704-42d4-8216-fad435ff4957
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=640578374 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_c
orrupt_sig_fatal_chk.640578374
Directory /workspace/31.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/31.rom_ctrl_kmac_err_chk.881980320
Short name T220
Test name
Test status
Simulation time 11832338435 ps
CPU time 20.27 seconds
Started May 09 12:37:34 PM PDT 24
Finished May 09 12:38:05 PM PDT 24
Peak memory 213336 kb
Host smart-87846bf6-93f8-4e67-93d8-750948f6f602
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=881980320 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_kmac_err_chk.881980320
Directory /workspace/31.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/31.rom_ctrl_max_throughput_chk.2614252849
Short name T247
Test name
Test status
Simulation time 1292226741 ps
CPU time 13.18 seconds
Started May 09 12:37:34 PM PDT 24
Finished May 09 12:37:59 PM PDT 24
Peak memory 211888 kb
Host smart-9bf5eebd-4088-40f8-9757-a67c0e7ff7c9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2614252849 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_max_throughput_chk.2614252849
Directory /workspace/31.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/31.rom_ctrl_smoke.345753580
Short name T41
Test name
Test status
Simulation time 15832560513 ps
CPU time 37.68 seconds
Started May 09 12:37:35 PM PDT 24
Finished May 09 12:38:24 PM PDT 24
Peak memory 219936 kb
Host smart-4a7f257a-4d8c-401f-85e4-0ebbfb3b9425
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=345753580 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_smoke.345753580
Directory /workspace/31.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/31.rom_ctrl_stress_all.1598499342
Short name T153
Test name
Test status
Simulation time 618690279 ps
CPU time 25.49 seconds
Started May 09 12:38:09 PM PDT 24
Finished May 09 12:38:52 PM PDT 24
Peak memory 214560 kb
Host smart-0d83cd77-98fc-4570-92a8-4e36ca458f97
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1598499342 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 31.rom_ctrl_stress_all.1598499342
Directory /workspace/31.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/31.rom_ctrl_stress_all_with_rand_reset.3349112790
Short name T249
Test name
Test status
Simulation time 22603215405 ps
CPU time 4310.96 seconds
Started May 09 12:37:49 PM PDT 24
Finished May 09 01:49:50 PM PDT 24
Peak memory 228216 kb
Host smart-ca5e1928-39cc-42f5-84af-1b1b38e7dfbd
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3349112790 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_stress_all_with_rand_reset.3349112790
Directory /workspace/31.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.rom_ctrl_alert_test.265106170
Short name T40
Test name
Test status
Simulation time 1960772027 ps
CPU time 15.76 seconds
Started May 09 12:37:33 PM PDT 24
Finished May 09 12:38:00 PM PDT 24
Peak memory 211652 kb
Host smart-bf59dc99-2ac7-4aa1-a439-02be9e216746
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=265106170 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_alert_test.265106170
Directory /workspace/32.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/32.rom_ctrl_corrupt_sig_fatal_chk.1192548621
Short name T13
Test name
Test status
Simulation time 47934338361 ps
CPU time 454.51 seconds
Started May 09 12:37:49 PM PDT 24
Finished May 09 12:45:33 PM PDT 24
Peak memory 229112 kb
Host smart-6076640a-88ee-485a-be9d-c1084fd271a4
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1192548621 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_
corrupt_sig_fatal_chk.1192548621
Directory /workspace/32.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/32.rom_ctrl_kmac_err_chk.1321451660
Short name T21
Test name
Test status
Simulation time 477322852 ps
CPU time 9.37 seconds
Started May 09 12:37:37 PM PDT 24
Finished May 09 12:37:57 PM PDT 24
Peak memory 211872 kb
Host smart-f696e3c3-5284-4c49-861f-cd5d41ab3069
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1321451660 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_kmac_err_chk.1321451660
Directory /workspace/32.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/32.rom_ctrl_max_throughput_chk.4247435787
Short name T107
Test name
Test status
Simulation time 491389938 ps
CPU time 8.71 seconds
Started May 09 12:37:38 PM PDT 24
Finished May 09 12:37:58 PM PDT 24
Peak memory 211620 kb
Host smart-598a3c54-47e9-4c79-a873-80cc4589a2fe
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4247435787 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_max_throughput_chk.4247435787
Directory /workspace/32.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/32.rom_ctrl_smoke.2261055650
Short name T152
Test name
Test status
Simulation time 2237075900 ps
CPU time 10.28 seconds
Started May 09 12:37:37 PM PDT 24
Finished May 09 12:37:58 PM PDT 24
Peak memory 219920 kb
Host smart-0cecc707-382f-476d-86a4-0f840382c7ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2261055650 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_smoke.2261055650
Directory /workspace/32.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/32.rom_ctrl_stress_all.553531836
Short name T219
Test name
Test status
Simulation time 1358219934 ps
CPU time 15.42 seconds
Started May 09 12:37:38 PM PDT 24
Finished May 09 12:38:05 PM PDT 24
Peak memory 214464 kb
Host smart-38ae2a14-b27b-4523-a4d3-043b6f4a30b5
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=553531836 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 32.rom_ctrl_stress_all.553531836
Directory /workspace/32.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/33.rom_ctrl_alert_test.2807698807
Short name T184
Test name
Test status
Simulation time 8640096678 ps
CPU time 16.86 seconds
Started May 09 12:37:37 PM PDT 24
Finished May 09 12:38:05 PM PDT 24
Peak memory 211820 kb
Host smart-0b2c97a6-67b9-423b-a1f0-c63674cac4ec
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2807698807 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_alert_test.2807698807
Directory /workspace/33.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/33.rom_ctrl_corrupt_sig_fatal_chk.1890271505
Short name T254
Test name
Test status
Simulation time 32285846509 ps
CPU time 289.04 seconds
Started May 09 12:37:38 PM PDT 24
Finished May 09 12:42:38 PM PDT 24
Peak memory 229152 kb
Host smart-8b26f5cb-cb6c-441e-979e-56cd5ff61d65
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1890271505 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_
corrupt_sig_fatal_chk.1890271505
Directory /workspace/33.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/33.rom_ctrl_kmac_err_chk.4091421713
Short name T134
Test name
Test status
Simulation time 2390444584 ps
CPU time 13.38 seconds
Started May 09 12:38:00 PM PDT 24
Finished May 09 12:38:29 PM PDT 24
Peak memory 212452 kb
Host smart-45a640e1-d606-4299-a787-ab65971e13c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4091421713 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_kmac_err_chk.4091421713
Directory /workspace/33.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/33.rom_ctrl_max_throughput_chk.2412460527
Short name T284
Test name
Test status
Simulation time 372072769 ps
CPU time 5.84 seconds
Started May 09 12:37:34 PM PDT 24
Finished May 09 12:37:51 PM PDT 24
Peak memory 211888 kb
Host smart-b5114899-78e2-465c-baa8-7ea9bfe06fdc
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2412460527 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_max_throughput_chk.2412460527
Directory /workspace/33.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/33.rom_ctrl_smoke.3181400613
Short name T277
Test name
Test status
Simulation time 18592756238 ps
CPU time 35.62 seconds
Started May 09 12:37:35 PM PDT 24
Finished May 09 12:38:21 PM PDT 24
Peak memory 214292 kb
Host smart-5b7bab8a-aa8d-4dc6-bf0b-a97111c13b3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3181400613 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_smoke.3181400613
Directory /workspace/33.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/33.rom_ctrl_stress_all.3223532475
Short name T17
Test name
Test status
Simulation time 8663293832 ps
CPU time 49.79 seconds
Started May 09 12:37:39 PM PDT 24
Finished May 09 12:38:39 PM PDT 24
Peak memory 219956 kb
Host smart-cc41ceba-3b7e-46ec-a18c-f1a9eff48983
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3223532475 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 33.rom_ctrl_stress_all.3223532475
Directory /workspace/33.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/34.rom_ctrl_alert_test.2380948240
Short name T127
Test name
Test status
Simulation time 89154135 ps
CPU time 4.22 seconds
Started May 09 12:37:50 PM PDT 24
Finished May 09 12:38:04 PM PDT 24
Peak memory 211716 kb
Host smart-0489bac6-dcbd-4676-a5e3-1825d607fb38
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2380948240 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_alert_test.2380948240
Directory /workspace/34.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/34.rom_ctrl_corrupt_sig_fatal_chk.92979192
Short name T3
Test name
Test status
Simulation time 29280138192 ps
CPU time 136.39 seconds
Started May 09 12:38:35 PM PDT 24
Finished May 09 12:41:08 PM PDT 24
Peak memory 231104 kb
Host smart-bf5ab168-360f-4f16-b0d3-a6d3a074d87c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=92979192 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_
sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_co
rrupt_sig_fatal_chk.92979192
Directory /workspace/34.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/34.rom_ctrl_kmac_err_chk.1616223300
Short name T295
Test name
Test status
Simulation time 2822881783 ps
CPU time 25.93 seconds
Started May 09 12:37:58 PM PDT 24
Finished May 09 12:38:39 PM PDT 24
Peak memory 212476 kb
Host smart-5c9fc3c1-e33b-4cbd-be9f-1fb2f0a09c74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1616223300 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_kmac_err_chk.1616223300
Directory /workspace/34.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/34.rom_ctrl_max_throughput_chk.3194937927
Short name T328
Test name
Test status
Simulation time 3144832338 ps
CPU time 10.21 seconds
Started May 09 12:37:53 PM PDT 24
Finished May 09 12:38:14 PM PDT 24
Peak memory 211752 kb
Host smart-c806817b-92da-427a-b478-a72ca1c6699b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3194937927 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_max_throughput_chk.3194937927
Directory /workspace/34.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/34.rom_ctrl_smoke.1001356762
Short name T75
Test name
Test status
Simulation time 4140596586 ps
CPU time 24.52 seconds
Started May 09 12:38:43 PM PDT 24
Finished May 09 12:39:24 PM PDT 24
Peak memory 212912 kb
Host smart-3fd8e360-bb38-4007-a0cf-7d7e9ab2f85c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1001356762 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_smoke.1001356762
Directory /workspace/34.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/34.rom_ctrl_stress_all.3824750329
Short name T151
Test name
Test status
Simulation time 5359721500 ps
CPU time 27.37 seconds
Started May 09 12:37:31 PM PDT 24
Finished May 09 12:38:11 PM PDT 24
Peak memory 214044 kb
Host smart-f3aa19b3-f43c-4428-a433-34a86b840934
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3824750329 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 34.rom_ctrl_stress_all.3824750329
Directory /workspace/34.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/35.rom_ctrl_alert_test.2926710523
Short name T260
Test name
Test status
Simulation time 334300643 ps
CPU time 4.2 seconds
Started May 09 12:37:36 PM PDT 24
Finished May 09 12:37:52 PM PDT 24
Peak memory 211676 kb
Host smart-92e800ed-1d72-40a1-934f-e1acc44ee4d0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2926710523 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_alert_test.2926710523
Directory /workspace/35.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/35.rom_ctrl_corrupt_sig_fatal_chk.4294306716
Short name T292
Test name
Test status
Simulation time 1835486029 ps
CPU time 51.81 seconds
Started May 09 12:38:35 PM PDT 24
Finished May 09 12:39:44 PM PDT 24
Peak memory 219612 kb
Host smart-cf1db893-75a8-49fb-9fec-d25c7bf410c9
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4294306716 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_
corrupt_sig_fatal_chk.4294306716
Directory /workspace/35.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/35.rom_ctrl_kmac_err_chk.3267640271
Short name T205
Test name
Test status
Simulation time 21571383912 ps
CPU time 24.83 seconds
Started May 09 12:37:44 PM PDT 24
Finished May 09 12:38:19 PM PDT 24
Peak memory 212584 kb
Host smart-cec0805a-a261-4fd5-9dbd-fb14ed9d0ce1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3267640271 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_kmac_err_chk.3267640271
Directory /workspace/35.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/35.rom_ctrl_max_throughput_chk.2656528089
Short name T199
Test name
Test status
Simulation time 244894030 ps
CPU time 6.74 seconds
Started May 09 12:37:35 PM PDT 24
Finished May 09 12:37:53 PM PDT 24
Peak memory 211616 kb
Host smart-f3536de7-6091-4837-826c-6f3dae1725d1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2656528089 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_max_throughput_chk.2656528089
Directory /workspace/35.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/35.rom_ctrl_smoke.3388441772
Short name T352
Test name
Test status
Simulation time 848521131 ps
CPU time 16.07 seconds
Started May 09 12:37:56 PM PDT 24
Finished May 09 12:38:25 PM PDT 24
Peak memory 219856 kb
Host smart-e6b8d4e3-e386-48dd-91d5-48a5dda5d2c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3388441772 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_smoke.3388441772
Directory /workspace/35.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/35.rom_ctrl_stress_all.2592872347
Short name T207
Test name
Test status
Simulation time 12478581796 ps
CPU time 30.54 seconds
Started May 09 12:37:49 PM PDT 24
Finished May 09 12:38:29 PM PDT 24
Peak memory 219908 kb
Host smart-f8345838-bb8c-414e-bd7f-3bc367fdfee1
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2592872347 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 35.rom_ctrl_stress_all.2592872347
Directory /workspace/35.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/35.rom_ctrl_stress_all_with_rand_reset.2281151038
Short name T51
Test name
Test status
Simulation time 192563880924 ps
CPU time 6430.49 seconds
Started May 09 12:37:35 PM PDT 24
Finished May 09 02:24:57 PM PDT 24
Peak memory 236408 kb
Host smart-bf51767c-f703-4fb9-9c83-59b78f79847c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2281151038 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_stress_all_with_rand_reset.2281151038
Directory /workspace/35.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.rom_ctrl_alert_test.3563667355
Short name T32
Test name
Test status
Simulation time 26056919199 ps
CPU time 17.24 seconds
Started May 09 12:38:03 PM PDT 24
Finished May 09 12:38:36 PM PDT 24
Peak memory 211808 kb
Host smart-0489baef-9c63-4dc6-b0ae-408f01490e4b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3563667355 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_alert_test.3563667355
Directory /workspace/36.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/36.rom_ctrl_corrupt_sig_fatal_chk.3437740542
Short name T202
Test name
Test status
Simulation time 18206684441 ps
CPU time 153.01 seconds
Started May 09 12:38:35 PM PDT 24
Finished May 09 12:41:25 PM PDT 24
Peak memory 211748 kb
Host smart-3187c9f1-1d2b-4d21-b4ff-16021a7f4056
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3437740542 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_
corrupt_sig_fatal_chk.3437740542
Directory /workspace/36.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/36.rom_ctrl_kmac_err_chk.848178177
Short name T178
Test name
Test status
Simulation time 1881411918 ps
CPU time 20.14 seconds
Started May 09 12:37:50 PM PDT 24
Finished May 09 12:38:19 PM PDT 24
Peak memory 211668 kb
Host smart-5aa3ce78-2a61-4c5d-ad03-29c19d0fb6ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=848178177 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_kmac_err_chk.848178177
Directory /workspace/36.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/36.rom_ctrl_max_throughput_chk.802050608
Short name T241
Test name
Test status
Simulation time 464530897 ps
CPU time 8.42 seconds
Started May 09 12:37:57 PM PDT 24
Finished May 09 12:38:19 PM PDT 24
Peak memory 211616 kb
Host smart-49d7f96e-693a-4fd2-833c-2b59ac5108a5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=802050608 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_max_throughput_chk.802050608
Directory /workspace/36.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/36.rom_ctrl_smoke.1269473618
Short name T198
Test name
Test status
Simulation time 2448541212 ps
CPU time 23.68 seconds
Started May 09 12:37:47 PM PDT 24
Finished May 09 12:38:21 PM PDT 24
Peak memory 213376 kb
Host smart-9a93300f-c974-4ce4-80f0-75a9cf7eece0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1269473618 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_smoke.1269473618
Directory /workspace/36.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/36.rom_ctrl_stress_all.3574840843
Short name T12
Test name
Test status
Simulation time 1228448867 ps
CPU time 16.94 seconds
Started May 09 12:37:38 PM PDT 24
Finished May 09 12:38:06 PM PDT 24
Peak memory 219804 kb
Host smart-ef5a82a8-5583-47f4-97cb-287b5b1c525c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3574840843 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 36.rom_ctrl_stress_all.3574840843
Directory /workspace/36.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/37.rom_ctrl_alert_test.4187926422
Short name T285
Test name
Test status
Simulation time 933912873 ps
CPU time 9.67 seconds
Started May 09 12:37:48 PM PDT 24
Finished May 09 12:38:07 PM PDT 24
Peak memory 211680 kb
Host smart-9a55c3ad-c159-452a-98b5-fdac21c73294
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4187926422 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_alert_test.4187926422
Directory /workspace/37.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/37.rom_ctrl_corrupt_sig_fatal_chk.952862767
Short name T122
Test name
Test status
Simulation time 6126706110 ps
CPU time 107.24 seconds
Started May 09 12:37:33 PM PDT 24
Finished May 09 12:39:32 PM PDT 24
Peak memory 238768 kb
Host smart-9441e934-3568-4b09-aa11-452d936189cd
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=952862767 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_c
orrupt_sig_fatal_chk.952862767
Directory /workspace/37.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/37.rom_ctrl_kmac_err_chk.3249077326
Short name T332
Test name
Test status
Simulation time 3038349254 ps
CPU time 27.2 seconds
Started May 09 12:37:49 PM PDT 24
Finished May 09 12:38:26 PM PDT 24
Peak memory 212348 kb
Host smart-c9096735-737d-4273-8446-7a7fdb26e660
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3249077326 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_kmac_err_chk.3249077326
Directory /workspace/37.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/37.rom_ctrl_max_throughput_chk.1775099314
Short name T166
Test name
Test status
Simulation time 9172270576 ps
CPU time 16.62 seconds
Started May 09 12:37:46 PM PDT 24
Finished May 09 12:38:12 PM PDT 24
Peak memory 211660 kb
Host smart-0c223a5a-86f4-4241-bb06-ff0cdcc6c492
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1775099314 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_max_throughput_chk.1775099314
Directory /workspace/37.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/37.rom_ctrl_stress_all.2866656625
Short name T145
Test name
Test status
Simulation time 9357134735 ps
CPU time 53.49 seconds
Started May 09 12:38:35 PM PDT 24
Finished May 09 12:39:45 PM PDT 24
Peak memory 217496 kb
Host smart-d7a7699d-a428-4457-9979-a24304eee5e0
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2866656625 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 37.rom_ctrl_stress_all.2866656625
Directory /workspace/37.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/38.rom_ctrl_alert_test.932790018
Short name T287
Test name
Test status
Simulation time 171905894 ps
CPU time 4.25 seconds
Started May 09 12:37:51 PM PDT 24
Finished May 09 12:38:05 PM PDT 24
Peak memory 211600 kb
Host smart-f21b985b-db33-4032-89b4-7b54412391e1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=932790018 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_alert_test.932790018
Directory /workspace/38.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/38.rom_ctrl_corrupt_sig_fatal_chk.1365058871
Short name T236
Test name
Test status
Simulation time 50181711742 ps
CPU time 173.71 seconds
Started May 09 12:37:51 PM PDT 24
Finished May 09 12:40:56 PM PDT 24
Peak memory 238308 kb
Host smart-0470af90-170f-4483-8396-a6a851934a3b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1365058871 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_
corrupt_sig_fatal_chk.1365058871
Directory /workspace/38.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/38.rom_ctrl_kmac_err_chk.1539466056
Short name T92
Test name
Test status
Simulation time 5466246781 ps
CPU time 19.68 seconds
Started May 09 12:38:47 PM PDT 24
Finished May 09 12:39:22 PM PDT 24
Peak memory 212192 kb
Host smart-97173785-a58a-4c3d-937e-af4fedd1e42f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1539466056 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_kmac_err_chk.1539466056
Directory /workspace/38.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/38.rom_ctrl_max_throughput_chk.2968081483
Short name T323
Test name
Test status
Simulation time 146655731 ps
CPU time 5.47 seconds
Started May 09 12:38:38 PM PDT 24
Finished May 09 12:39:01 PM PDT 24
Peak memory 210708 kb
Host smart-3aac8a87-1e4c-40f4-a0ba-a8353d4f10fe
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2968081483 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_max_throughput_chk.2968081483
Directory /workspace/38.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/38.rom_ctrl_smoke.2992410739
Short name T79
Test name
Test status
Simulation time 184784648 ps
CPU time 9.93 seconds
Started May 09 12:38:35 PM PDT 24
Finished May 09 12:39:02 PM PDT 24
Peak memory 218072 kb
Host smart-325d4f4e-4e8f-4d4c-b3ab-ea828a66b837
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2992410739 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_smoke.2992410739
Directory /workspace/38.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/38.rom_ctrl_stress_all.1873521490
Short name T357
Test name
Test status
Simulation time 23479266388 ps
CPU time 56.19 seconds
Started May 09 12:38:43 PM PDT 24
Finished May 09 12:39:56 PM PDT 24
Peak memory 219476 kb
Host smart-7eac2ae3-a656-41ff-a753-d4fbdcde7fe6
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1873521490 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 38.rom_ctrl_stress_all.1873521490
Directory /workspace/38.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/39.rom_ctrl_alert_test.1539116321
Short name T179
Test name
Test status
Simulation time 89013693 ps
CPU time 4.19 seconds
Started May 09 12:37:50 PM PDT 24
Finished May 09 12:38:04 PM PDT 24
Peak memory 211692 kb
Host smart-37bde5b9-5d95-490e-a1c0-43b90aea8387
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1539116321 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_alert_test.1539116321
Directory /workspace/39.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/39.rom_ctrl_corrupt_sig_fatal_chk.3155152418
Short name T294
Test name
Test status
Simulation time 11799692554 ps
CPU time 149.19 seconds
Started May 09 12:37:45 PM PDT 24
Finished May 09 12:40:24 PM PDT 24
Peak memory 228808 kb
Host smart-5d536e19-00ce-41a6-a319-e968db2ef98b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3155152418 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_
corrupt_sig_fatal_chk.3155152418
Directory /workspace/39.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/39.rom_ctrl_kmac_err_chk.3087174731
Short name T272
Test name
Test status
Simulation time 15010529796 ps
CPU time 28.44 seconds
Started May 09 12:37:37 PM PDT 24
Finished May 09 12:38:16 PM PDT 24
Peak memory 212596 kb
Host smart-47de0467-8640-4d18-939b-45c3de3264ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3087174731 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_kmac_err_chk.3087174731
Directory /workspace/39.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/39.rom_ctrl_max_throughput_chk.4131005092
Short name T157
Test name
Test status
Simulation time 1220983704 ps
CPU time 7.62 seconds
Started May 09 12:37:58 PM PDT 24
Finished May 09 12:38:20 PM PDT 24
Peak memory 211620 kb
Host smart-c6cb5e57-ddac-4a8c-bcb0-a7176eec6c0c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4131005092 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_max_throughput_chk.4131005092
Directory /workspace/39.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/39.rom_ctrl_smoke.1760984761
Short name T37
Test name
Test status
Simulation time 186186100 ps
CPU time 10.15 seconds
Started May 09 12:37:39 PM PDT 24
Finished May 09 12:38:00 PM PDT 24
Peak memory 213648 kb
Host smart-e0801e93-d948-49a7-a0e0-d9827a41f585
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1760984761 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_smoke.1760984761
Directory /workspace/39.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/39.rom_ctrl_stress_all.942922767
Short name T44
Test name
Test status
Simulation time 2612244099 ps
CPU time 34.65 seconds
Started May 09 12:37:48 PM PDT 24
Finished May 09 12:38:32 PM PDT 24
Peak memory 215860 kb
Host smart-4b3d9f0a-2d1e-4fd8-81a9-7f03fbf8d6a8
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=942922767 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 39.rom_ctrl_stress_all.942922767
Directory /workspace/39.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/4.rom_ctrl_alert_test.584261668
Short name T278
Test name
Test status
Simulation time 347499686 ps
CPU time 4.26 seconds
Started May 09 12:37:05 PM PDT 24
Finished May 09 12:37:21 PM PDT 24
Peak memory 211704 kb
Host smart-0c05b772-fda2-47eb-b355-64ef47f20824
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=584261668 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_alert_test.584261668
Directory /workspace/4.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/4.rom_ctrl_corrupt_sig_fatal_chk.815366435
Short name T261
Test name
Test status
Simulation time 27687135912 ps
CPU time 249.62 seconds
Started May 09 12:37:13 PM PDT 24
Finished May 09 12:41:37 PM PDT 24
Peak memory 234608 kb
Host smart-5f2f86e2-9403-43e3-9e96-46315c052835
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=815366435 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_co
rrupt_sig_fatal_chk.815366435
Directory /workspace/4.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/4.rom_ctrl_kmac_err_chk.886515765
Short name T266
Test name
Test status
Simulation time 1275303630 ps
CPU time 9.29 seconds
Started May 09 12:37:12 PM PDT 24
Finished May 09 12:37:36 PM PDT 24
Peak memory 212232 kb
Host smart-6b156508-f439-415f-9c8c-dae2f1b35d3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=886515765 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_kmac_err_chk.886515765
Directory /workspace/4.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/4.rom_ctrl_max_throughput_chk.2205264806
Short name T269
Test name
Test status
Simulation time 1238948719 ps
CPU time 7.16 seconds
Started May 09 12:37:13 PM PDT 24
Finished May 09 12:37:35 PM PDT 24
Peak memory 211644 kb
Host smart-815ec464-2aa8-461b-b660-c306c6e00e62
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2205264806 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_max_throughput_chk.2205264806
Directory /workspace/4.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/4.rom_ctrl_sec_cm.2538636672
Short name T35
Test name
Test status
Simulation time 13002766427 ps
CPU time 55.31 seconds
Started May 09 12:37:14 PM PDT 24
Finished May 09 12:38:24 PM PDT 24
Peak memory 237228 kb
Host smart-7fad4a5f-67b7-43e2-9a4c-3d950d96f9df
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2538636672 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_sec_cm.2538636672
Directory /workspace/4.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/4.rom_ctrl_smoke.2811759023
Short name T173
Test name
Test status
Simulation time 1957620336 ps
CPU time 16.55 seconds
Started May 09 12:37:40 PM PDT 24
Finished May 09 12:38:07 PM PDT 24
Peak memory 213840 kb
Host smart-35cc0c4f-3e37-4197-b687-f267739ff726
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2811759023 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_smoke.2811759023
Directory /workspace/4.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/4.rom_ctrl_stress_all.4150193113
Short name T358
Test name
Test status
Simulation time 5531713425 ps
CPU time 57.74 seconds
Started May 09 12:37:19 PM PDT 24
Finished May 09 12:38:31 PM PDT 24
Peak memory 217360 kb
Host smart-dd2220f6-f0d1-4703-bd10-e15ae731e301
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4150193113 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 4.rom_ctrl_stress_all.4150193113
Directory /workspace/4.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/40.rom_ctrl_alert_test.636149994
Short name T354
Test name
Test status
Simulation time 671845877 ps
CPU time 6.55 seconds
Started May 09 12:37:58 PM PDT 24
Finished May 09 12:38:19 PM PDT 24
Peak memory 211692 kb
Host smart-4f6addd5-95f3-4f1f-902a-cc6321e7df17
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=636149994 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_alert_test.636149994
Directory /workspace/40.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/40.rom_ctrl_corrupt_sig_fatal_chk.2212071032
Short name T186
Test name
Test status
Simulation time 4093943195 ps
CPU time 112.76 seconds
Started May 09 12:37:58 PM PDT 24
Finished May 09 12:40:05 PM PDT 24
Peak memory 213132 kb
Host smart-fee208d9-69ea-4aa5-84a0-b36c4c9b2876
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2212071032 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_
corrupt_sig_fatal_chk.2212071032
Directory /workspace/40.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/40.rom_ctrl_kmac_err_chk.4130472193
Short name T235
Test name
Test status
Simulation time 12648622457 ps
CPU time 27.04 seconds
Started May 09 12:37:54 PM PDT 24
Finished May 09 12:38:33 PM PDT 24
Peak memory 212656 kb
Host smart-d2404966-49c0-4a1f-88f5-0e75dec1737e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4130472193 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_kmac_err_chk.4130472193
Directory /workspace/40.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/40.rom_ctrl_max_throughput_chk.501451713
Short name T229
Test name
Test status
Simulation time 1643808599 ps
CPU time 14.99 seconds
Started May 09 12:37:59 PM PDT 24
Finished May 09 12:38:29 PM PDT 24
Peak memory 211624 kb
Host smart-01f2cddc-e996-41bf-8284-b595ffba1494
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=501451713 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_max_throughput_chk.501451713
Directory /workspace/40.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/40.rom_ctrl_smoke.59220998
Short name T123
Test name
Test status
Simulation time 12149627848 ps
CPU time 26.69 seconds
Started May 09 12:37:52 PM PDT 24
Finished May 09 12:38:30 PM PDT 24
Peak memory 219960 kb
Host smart-5080362d-c504-4c2f-b820-6a94ed89af12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=59220998 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_smoke.59220998
Directory /workspace/40.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/40.rom_ctrl_stress_all.3034122762
Short name T193
Test name
Test status
Simulation time 10486067929 ps
CPU time 46.08 seconds
Started May 09 12:37:39 PM PDT 24
Finished May 09 12:38:35 PM PDT 24
Peak memory 219968 kb
Host smart-7b2a1755-ec4f-414b-9e05-e6dc4d348f30
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3034122762 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 40.rom_ctrl_stress_all.3034122762
Directory /workspace/40.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/40.rom_ctrl_stress_all_with_rand_reset.1628434180
Short name T182
Test name
Test status
Simulation time 33392809827 ps
CPU time 1236.52 seconds
Started May 09 12:37:59 PM PDT 24
Finished May 09 12:58:51 PM PDT 24
Peak memory 230416 kb
Host smart-427c9fc4-b20e-4039-9c27-1e6d91bdbc69
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1628434180 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_stress_all_with_rand_reset.1628434180
Directory /workspace/40.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.rom_ctrl_alert_test.1946203338
Short name T212
Test name
Test status
Simulation time 7363656827 ps
CPU time 15.09 seconds
Started May 09 12:38:00 PM PDT 24
Finished May 09 12:38:31 PM PDT 24
Peak memory 211840 kb
Host smart-5ea449c0-dc5b-4652-8fea-898fcc15c7c0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1946203338 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_alert_test.1946203338
Directory /workspace/41.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/41.rom_ctrl_corrupt_sig_fatal_chk.1559871409
Short name T268
Test name
Test status
Simulation time 111907676423 ps
CPU time 270.16 seconds
Started May 09 12:37:36 PM PDT 24
Finished May 09 12:42:17 PM PDT 24
Peak memory 238364 kb
Host smart-bde63cb2-320f-4321-af5f-a87ba4081333
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1559871409 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_
corrupt_sig_fatal_chk.1559871409
Directory /workspace/41.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/41.rom_ctrl_kmac_err_chk.2715999584
Short name T172
Test name
Test status
Simulation time 9139358704 ps
CPU time 28.06 seconds
Started May 09 12:37:55 PM PDT 24
Finished May 09 12:38:36 PM PDT 24
Peak memory 212824 kb
Host smart-25dda0a9-bb8c-4301-bda7-22be6eaedbac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2715999584 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_kmac_err_chk.2715999584
Directory /workspace/41.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/41.rom_ctrl_max_throughput_chk.2932234552
Short name T194
Test name
Test status
Simulation time 1538583823 ps
CPU time 7.77 seconds
Started May 09 12:37:37 PM PDT 24
Finished May 09 12:37:55 PM PDT 24
Peak memory 211664 kb
Host smart-f1512fa2-1e14-45ce-8ffa-90e191c21eea
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2932234552 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_max_throughput_chk.2932234552
Directory /workspace/41.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/41.rom_ctrl_smoke.868203337
Short name T141
Test name
Test status
Simulation time 2188248014 ps
CPU time 25.42 seconds
Started May 09 12:37:45 PM PDT 24
Finished May 09 12:38:21 PM PDT 24
Peak memory 213724 kb
Host smart-2269ff47-b4b7-4568-a3d0-739f30f648b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=868203337 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_smoke.868203337
Directory /workspace/41.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/41.rom_ctrl_stress_all.3042095529
Short name T187
Test name
Test status
Simulation time 13956411100 ps
CPU time 26.14 seconds
Started May 09 12:37:57 PM PDT 24
Finished May 09 12:38:38 PM PDT 24
Peak memory 219968 kb
Host smart-ad74010c-e905-409a-bfaa-2d8d43a88c87
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3042095529 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 41.rom_ctrl_stress_all.3042095529
Directory /workspace/41.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/42.rom_ctrl_alert_test.175494675
Short name T91
Test name
Test status
Simulation time 692624098 ps
CPU time 4.25 seconds
Started May 09 12:37:49 PM PDT 24
Finished May 09 12:38:03 PM PDT 24
Peak memory 211620 kb
Host smart-d16558fd-ddf0-45d0-9f5e-789ddea1d847
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=175494675 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_alert_test.175494675
Directory /workspace/42.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/42.rom_ctrl_corrupt_sig_fatal_chk.2955286097
Short name T347
Test name
Test status
Simulation time 40760808519 ps
CPU time 221.15 seconds
Started May 09 12:37:55 PM PDT 24
Finished May 09 12:41:50 PM PDT 24
Peak memory 234708 kb
Host smart-bdfe5ef6-07be-4ca2-a6c2-2ec6c1390159
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2955286097 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_
corrupt_sig_fatal_chk.2955286097
Directory /workspace/42.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/42.rom_ctrl_kmac_err_chk.3822608385
Short name T316
Test name
Test status
Simulation time 1949212973 ps
CPU time 21.07 seconds
Started May 09 12:37:48 PM PDT 24
Finished May 09 12:38:18 PM PDT 24
Peak memory 212424 kb
Host smart-9b3b8b42-fdb9-4af6-b098-5d7165106a8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3822608385 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_kmac_err_chk.3822608385
Directory /workspace/42.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/42.rom_ctrl_max_throughput_chk.2067675655
Short name T155
Test name
Test status
Simulation time 99976422 ps
CPU time 5.55 seconds
Started May 09 12:37:56 PM PDT 24
Finished May 09 12:38:14 PM PDT 24
Peak memory 211596 kb
Host smart-6e5d088e-84f1-4365-9bc5-7748a1006f1c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2067675655 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_max_throughput_chk.2067675655
Directory /workspace/42.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/42.rom_ctrl_smoke.3956022682
Short name T288
Test name
Test status
Simulation time 15491740982 ps
CPU time 18.05 seconds
Started May 09 12:37:39 PM PDT 24
Finished May 09 12:38:07 PM PDT 24
Peak memory 220036 kb
Host smart-be0935c7-fa8f-4cc5-bfde-72510c77a6f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3956022682 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_smoke.3956022682
Directory /workspace/42.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/42.rom_ctrl_stress_all.3079442394
Short name T195
Test name
Test status
Simulation time 8461952384 ps
CPU time 90.84 seconds
Started May 09 12:37:47 PM PDT 24
Finished May 09 12:39:28 PM PDT 24
Peak memory 219936 kb
Host smart-e3bf694b-8273-4200-a6c3-67a77bf542e0
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3079442394 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 42.rom_ctrl_stress_all.3079442394
Directory /workspace/42.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/42.rom_ctrl_stress_all_with_rand_reset.2176829278
Short name T297
Test name
Test status
Simulation time 46798932835 ps
CPU time 1778.5 seconds
Started May 09 12:37:46 PM PDT 24
Finished May 09 01:07:35 PM PDT 24
Peak memory 228636 kb
Host smart-be235259-58bc-48bf-b6d5-fd77af9175cf
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2176829278 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_stress_all_with_rand_reset.2176829278
Directory /workspace/42.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.rom_ctrl_alert_test.1261175501
Short name T262
Test name
Test status
Simulation time 1617899418 ps
CPU time 9.52 seconds
Started May 09 12:37:59 PM PDT 24
Finished May 09 12:38:24 PM PDT 24
Peak memory 211720 kb
Host smart-68b239f0-98e5-4e17-9ce3-3b101a87c82a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1261175501 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_alert_test.1261175501
Directory /workspace/43.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/43.rom_ctrl_corrupt_sig_fatal_chk.944074139
Short name T311
Test name
Test status
Simulation time 40167500336 ps
CPU time 342.75 seconds
Started May 09 12:37:56 PM PDT 24
Finished May 09 12:43:53 PM PDT 24
Peak memory 228860 kb
Host smart-174c18c4-3462-45fb-be59-abc22d6dc34b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=944074139 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_c
orrupt_sig_fatal_chk.944074139
Directory /workspace/43.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/43.rom_ctrl_kmac_err_chk.1510674724
Short name T23
Test name
Test status
Simulation time 340616623 ps
CPU time 9.26 seconds
Started May 09 12:38:05 PM PDT 24
Finished May 09 12:38:32 PM PDT 24
Peak memory 212160 kb
Host smart-7dc89e6e-4bc5-4cf5-9d25-ecc2bf57004b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1510674724 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_kmac_err_chk.1510674724
Directory /workspace/43.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/43.rom_ctrl_max_throughput_chk.3158965954
Short name T270
Test name
Test status
Simulation time 1250695759 ps
CPU time 6.59 seconds
Started May 09 12:37:38 PM PDT 24
Finished May 09 12:37:55 PM PDT 24
Peak memory 211664 kb
Host smart-4a299308-8144-4f37-8d58-de861e6fede3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3158965954 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_max_throughput_chk.3158965954
Directory /workspace/43.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/43.rom_ctrl_smoke.3203012798
Short name T310
Test name
Test status
Simulation time 4640036759 ps
CPU time 30.81 seconds
Started May 09 12:37:54 PM PDT 24
Finished May 09 12:38:36 PM PDT 24
Peak memory 219984 kb
Host smart-ae181c29-8d2e-4ea2-876d-7b46202706d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3203012798 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_smoke.3203012798
Directory /workspace/43.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/43.rom_ctrl_stress_all.3220195600
Short name T206
Test name
Test status
Simulation time 2139191000 ps
CPU time 24.79 seconds
Started May 09 12:37:34 PM PDT 24
Finished May 09 12:38:10 PM PDT 24
Peak memory 215188 kb
Host smart-20883edb-fbe6-4d7f-ae17-21fb00510213
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3220195600 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 43.rom_ctrl_stress_all.3220195600
Directory /workspace/43.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/44.rom_ctrl_alert_test.3335132192
Short name T298
Test name
Test status
Simulation time 27127370617 ps
CPU time 15.89 seconds
Started May 09 12:37:38 PM PDT 24
Finished May 09 12:38:05 PM PDT 24
Peak memory 211804 kb
Host smart-df692bd4-0159-4c26-9d2e-8fa15054f99b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3335132192 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_alert_test.3335132192
Directory /workspace/44.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/44.rom_ctrl_corrupt_sig_fatal_chk.2584577511
Short name T28
Test name
Test status
Simulation time 113296871229 ps
CPU time 290.46 seconds
Started May 09 12:37:55 PM PDT 24
Finished May 09 12:42:59 PM PDT 24
Peak memory 238376 kb
Host smart-dde95c46-ac22-4d4c-b134-148fd070906f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2584577511 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_
corrupt_sig_fatal_chk.2584577511
Directory /workspace/44.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/44.rom_ctrl_kmac_err_chk.2699053657
Short name T256
Test name
Test status
Simulation time 13842223284 ps
CPU time 33.29 seconds
Started May 09 12:38:03 PM PDT 24
Finished May 09 12:38:53 PM PDT 24
Peak memory 212656 kb
Host smart-f08991b0-704f-49d5-824b-5d0f56d48724
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2699053657 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_kmac_err_chk.2699053657
Directory /workspace/44.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/44.rom_ctrl_max_throughput_chk.59231584
Short name T369
Test name
Test status
Simulation time 2074991286 ps
CPU time 17.03 seconds
Started May 09 12:37:36 PM PDT 24
Finished May 09 12:38:04 PM PDT 24
Peak memory 211644 kb
Host smart-862e93fd-db0a-487e-a099-b64df09aac46
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=59231584 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_max_throughput_chk.59231584
Directory /workspace/44.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/44.rom_ctrl_smoke.528570932
Short name T226
Test name
Test status
Simulation time 8544240660 ps
CPU time 26.17 seconds
Started May 09 12:37:58 PM PDT 24
Finished May 09 12:38:38 PM PDT 24
Peak memory 215444 kb
Host smart-b7b6a7e5-f4e9-4484-aa40-55d2da9730de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=528570932 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_smoke.528570932
Directory /workspace/44.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/44.rom_ctrl_stress_all.2887398038
Short name T227
Test name
Test status
Simulation time 7654661968 ps
CPU time 32.78 seconds
Started May 09 12:38:04 PM PDT 24
Finished May 09 12:38:53 PM PDT 24
Peak memory 214548 kb
Host smart-e74fee2e-a472-4bd5-a705-859203aa3180
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2887398038 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 44.rom_ctrl_stress_all.2887398038
Directory /workspace/44.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/44.rom_ctrl_stress_all_with_rand_reset.2474802524
Short name T43
Test name
Test status
Simulation time 56382364582 ps
CPU time 1463.35 seconds
Started May 09 12:37:37 PM PDT 24
Finished May 09 01:02:11 PM PDT 24
Peak memory 232900 kb
Host smart-1d4c8aa5-02e1-4bc9-ab39-e70e86bdbe01
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2474802524 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_stress_all_with_rand_reset.2474802524
Directory /workspace/44.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.rom_ctrl_alert_test.1616867386
Short name T329
Test name
Test status
Simulation time 87160717 ps
CPU time 4.15 seconds
Started May 09 12:38:00 PM PDT 24
Finished May 09 12:38:20 PM PDT 24
Peak memory 211680 kb
Host smart-571945f2-5d90-4ddb-b014-31dceb7686d2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1616867386 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_alert_test.1616867386
Directory /workspace/45.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/45.rom_ctrl_corrupt_sig_fatal_chk.1588463022
Short name T189
Test name
Test status
Simulation time 2097405099 ps
CPU time 131.09 seconds
Started May 09 12:37:53 PM PDT 24
Finished May 09 12:40:15 PM PDT 24
Peak memory 237968 kb
Host smart-45f83433-7ba9-423c-9cd9-d48134c47708
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1588463022 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_
corrupt_sig_fatal_chk.1588463022
Directory /workspace/45.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/45.rom_ctrl_kmac_err_chk.3934547373
Short name T138
Test name
Test status
Simulation time 2275798302 ps
CPU time 20.2 seconds
Started May 09 12:37:46 PM PDT 24
Finished May 09 12:38:17 PM PDT 24
Peak memory 212532 kb
Host smart-b71913be-3868-4eaf-873f-cf284bef0829
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3934547373 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_kmac_err_chk.3934547373
Directory /workspace/45.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/45.rom_ctrl_max_throughput_chk.415981436
Short name T233
Test name
Test status
Simulation time 2602394677 ps
CPU time 7.62 seconds
Started May 09 12:37:55 PM PDT 24
Finished May 09 12:38:16 PM PDT 24
Peak memory 211740 kb
Host smart-02105572-c3a4-43d4-9d3c-8356027891e9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=415981436 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_max_throughput_chk.415981436
Directory /workspace/45.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/45.rom_ctrl_smoke.2585171339
Short name T147
Test name
Test status
Simulation time 4154105251 ps
CPU time 16.27 seconds
Started May 09 12:37:54 PM PDT 24
Finished May 09 12:38:23 PM PDT 24
Peak memory 219968 kb
Host smart-7cab0040-ac6c-4360-85af-a4bcbb737577
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2585171339 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_smoke.2585171339
Directory /workspace/45.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/45.rom_ctrl_stress_all.4006863411
Short name T240
Test name
Test status
Simulation time 4715583885 ps
CPU time 56.4 seconds
Started May 09 12:37:38 PM PDT 24
Finished May 09 12:38:45 PM PDT 24
Peak memory 214196 kb
Host smart-f7032f35-6421-4773-863d-18d8b63a38a9
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4006863411 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 45.rom_ctrl_stress_all.4006863411
Directory /workspace/45.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/45.rom_ctrl_stress_all_with_rand_reset.2738285676
Short name T50
Test name
Test status
Simulation time 64080271218 ps
CPU time 577.78 seconds
Started May 09 12:37:37 PM PDT 24
Finished May 09 12:47:26 PM PDT 24
Peak memory 229108 kb
Host smart-8f2de726-6448-4664-82a5-fcda50e86afa
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2738285676 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_stress_all_with_rand_reset.2738285676
Directory /workspace/45.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.rom_ctrl_alert_test.257034465
Short name T143
Test name
Test status
Simulation time 3875149136 ps
CPU time 8.71 seconds
Started May 09 12:38:04 PM PDT 24
Finished May 09 12:38:29 PM PDT 24
Peak memory 211840 kb
Host smart-222cabe6-0258-4f33-858f-d717360a13d1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=257034465 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_alert_test.257034465
Directory /workspace/46.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/46.rom_ctrl_kmac_err_chk.438582598
Short name T18
Test name
Test status
Simulation time 2566965647 ps
CPU time 25.21 seconds
Started May 09 12:37:47 PM PDT 24
Finished May 09 12:38:22 PM PDT 24
Peak memory 212464 kb
Host smart-182888f0-4f49-487c-8db1-630b2f82422e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=438582598 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_kmac_err_chk.438582598
Directory /workspace/46.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/46.rom_ctrl_max_throughput_chk.370499340
Short name T177
Test name
Test status
Simulation time 519983052 ps
CPU time 5.88 seconds
Started May 09 12:37:46 PM PDT 24
Finished May 09 12:38:02 PM PDT 24
Peak memory 211572 kb
Host smart-5e1ae1da-9396-47ae-b01c-64d8673cc9b7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=370499340 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_max_throughput_chk.370499340
Directory /workspace/46.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/46.rom_ctrl_smoke.1289499139
Short name T364
Test name
Test status
Simulation time 9915137643 ps
CPU time 25.86 seconds
Started May 09 12:37:59 PM PDT 24
Finished May 09 12:38:40 PM PDT 24
Peak memory 219968 kb
Host smart-04427484-af0a-4c3f-bec8-4980dcd0ec71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1289499139 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_smoke.1289499139
Directory /workspace/46.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/46.rom_ctrl_stress_all.2068109816
Short name T251
Test name
Test status
Simulation time 1410105696 ps
CPU time 32.29 seconds
Started May 09 12:37:37 PM PDT 24
Finished May 09 12:38:20 PM PDT 24
Peak memory 215428 kb
Host smart-3235bad3-6eef-493c-805f-5e5a7eacfab6
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2068109816 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 46.rom_ctrl_stress_all.2068109816
Directory /workspace/46.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/47.rom_ctrl_alert_test.1525505731
Short name T244
Test name
Test status
Simulation time 2445163021 ps
CPU time 11.71 seconds
Started May 09 12:37:49 PM PDT 24
Finished May 09 12:38:11 PM PDT 24
Peak memory 211820 kb
Host smart-2dbd5fa4-803e-467a-9159-2c19b1fcd796
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1525505731 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_alert_test.1525505731
Directory /workspace/47.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/47.rom_ctrl_corrupt_sig_fatal_chk.942544909
Short name T248
Test name
Test status
Simulation time 1125374085 ps
CPU time 72.89 seconds
Started May 09 12:38:05 PM PDT 24
Finished May 09 12:39:35 PM PDT 24
Peak memory 231096 kb
Host smart-6e782613-152f-4202-b26e-39e2b92d0c79
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=942544909 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_c
orrupt_sig_fatal_chk.942544909
Directory /workspace/47.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/47.rom_ctrl_kmac_err_chk.4041423448
Short name T258
Test name
Test status
Simulation time 722114559 ps
CPU time 9.46 seconds
Started May 09 12:38:04 PM PDT 24
Finished May 09 12:38:31 PM PDT 24
Peak memory 212316 kb
Host smart-99a339cf-9433-4c24-afdc-2b27206684d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4041423448 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_kmac_err_chk.4041423448
Directory /workspace/47.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/47.rom_ctrl_max_throughput_chk.76929061
Short name T149
Test name
Test status
Simulation time 954642990 ps
CPU time 11.39 seconds
Started May 09 12:37:47 PM PDT 24
Finished May 09 12:38:08 PM PDT 24
Peak memory 211644 kb
Host smart-b88993f7-8614-4413-978d-f42329fa6a97
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=76929061 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_max_throughput_chk.76929061
Directory /workspace/47.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/47.rom_ctrl_smoke.1715765273
Short name T335
Test name
Test status
Simulation time 2002446144 ps
CPU time 18.54 seconds
Started May 09 12:37:49 PM PDT 24
Finished May 09 12:38:17 PM PDT 24
Peak memory 213824 kb
Host smart-e7032f8c-00e1-44b2-a2a2-4eb17256912c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1715765273 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_smoke.1715765273
Directory /workspace/47.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/47.rom_ctrl_stress_all.4233427407
Short name T125
Test name
Test status
Simulation time 7845875386 ps
CPU time 17.59 seconds
Started May 09 12:38:06 PM PDT 24
Finished May 09 12:38:40 PM PDT 24
Peak memory 214400 kb
Host smart-53971762-7967-49ea-b989-53b2887b2726
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4233427407 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 47.rom_ctrl_stress_all.4233427407
Directory /workspace/47.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/47.rom_ctrl_stress_all_with_rand_reset.3818228348
Short name T110
Test name
Test status
Simulation time 482988325603 ps
CPU time 4646.8 seconds
Started May 09 12:37:58 PM PDT 24
Finished May 09 01:55:41 PM PDT 24
Peak memory 261044 kb
Host smart-a42f8f6e-c282-47ca-900e-5b9fb21105b8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3818228348 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_stress_all_with_rand_reset.3818228348
Directory /workspace/47.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.rom_ctrl_alert_test.672349829
Short name T349
Test name
Test status
Simulation time 1247182694 ps
CPU time 5.1 seconds
Started May 09 12:38:04 PM PDT 24
Finished May 09 12:38:26 PM PDT 24
Peak memory 211700 kb
Host smart-7de1c501-c831-4ff5-9c20-eee6bfc13150
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=672349829 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_alert_test.672349829
Directory /workspace/48.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/48.rom_ctrl_corrupt_sig_fatal_chk.2523616340
Short name T223
Test name
Test status
Simulation time 80167045977 ps
CPU time 236.66 seconds
Started May 09 12:38:01 PM PDT 24
Finished May 09 12:42:13 PM PDT 24
Peak memory 238304 kb
Host smart-80c2d7fc-4f77-4f2f-8222-8856878df824
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2523616340 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_
corrupt_sig_fatal_chk.2523616340
Directory /workspace/48.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/48.rom_ctrl_kmac_err_chk.90975130
Short name T263
Test name
Test status
Simulation time 3480546814 ps
CPU time 29.75 seconds
Started May 09 12:38:02 PM PDT 24
Finished May 09 12:38:48 PM PDT 24
Peak memory 212400 kb
Host smart-1f681df2-98b3-4fca-9547-a2b61d0ac336
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=90975130 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_kmac_err_chk.90975130
Directory /workspace/48.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/48.rom_ctrl_max_throughput_chk.3594972746
Short name T317
Test name
Test status
Simulation time 11331841688 ps
CPU time 13.98 seconds
Started May 09 12:37:44 PM PDT 24
Finished May 09 12:38:13 PM PDT 24
Peak memory 211772 kb
Host smart-bc960517-431e-4727-ae3f-e5967a7b39c1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3594972746 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_max_throughput_chk.3594972746
Directory /workspace/48.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/48.rom_ctrl_smoke.24765425
Short name T237
Test name
Test status
Simulation time 382375537 ps
CPU time 10.1 seconds
Started May 09 12:37:51 PM PDT 24
Finished May 09 12:38:12 PM PDT 24
Peak memory 219844 kb
Host smart-f61dcff0-52f7-4790-ba16-f9425c29a114
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=24765425 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_smoke.24765425
Directory /workspace/48.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/48.rom_ctrl_stress_all.135921895
Short name T279
Test name
Test status
Simulation time 4149316874 ps
CPU time 52.91 seconds
Started May 09 12:37:53 PM PDT 24
Finished May 09 12:38:57 PM PDT 24
Peak memory 217000 kb
Host smart-682ad2c5-b094-45f3-bfd1-1777074fee0e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=135921895 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 48.rom_ctrl_stress_all.135921895
Directory /workspace/48.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/48.rom_ctrl_stress_all_with_rand_reset.1844441086
Short name T53
Test name
Test status
Simulation time 244887217636 ps
CPU time 1449.87 seconds
Started May 09 12:38:05 PM PDT 24
Finished May 09 01:02:32 PM PDT 24
Peak memory 236440 kb
Host smart-7a4c3298-0eec-4357-a909-5ed0fe34e73d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1844441086 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_stress_all_with_rand_reset.1844441086
Directory /workspace/48.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/49.rom_ctrl_alert_test.4044789034
Short name T363
Test name
Test status
Simulation time 1580390465 ps
CPU time 13.4 seconds
Started May 09 12:37:58 PM PDT 24
Finished May 09 12:38:26 PM PDT 24
Peak memory 211712 kb
Host smart-a12ea27c-9bb2-404d-a424-3708a440dc5f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4044789034 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_alert_test.4044789034
Directory /workspace/49.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/49.rom_ctrl_corrupt_sig_fatal_chk.1499393706
Short name T164
Test name
Test status
Simulation time 94750677208 ps
CPU time 227.18 seconds
Started May 09 12:37:56 PM PDT 24
Finished May 09 12:41:57 PM PDT 24
Peak memory 230924 kb
Host smart-a45ea30c-7546-4f88-b0ec-79e2b53e4aea
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1499393706 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_
corrupt_sig_fatal_chk.1499393706
Directory /workspace/49.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/49.rom_ctrl_kmac_err_chk.1869065023
Short name T257
Test name
Test status
Simulation time 170042240 ps
CPU time 9.58 seconds
Started May 09 12:37:52 PM PDT 24
Finished May 09 12:38:12 PM PDT 24
Peak memory 212228 kb
Host smart-a04c05ec-dcdb-42b1-9045-c04ff13b524a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1869065023 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_kmac_err_chk.1869065023
Directory /workspace/49.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/49.rom_ctrl_max_throughput_chk.235140993
Short name T322
Test name
Test status
Simulation time 2143223589 ps
CPU time 17.41 seconds
Started May 09 12:38:06 PM PDT 24
Finished May 09 12:38:40 PM PDT 24
Peak memory 211640 kb
Host smart-cdba257b-0892-4589-8fd1-8b5e812e10b9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=235140993 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_max_throughput_chk.235140993
Directory /workspace/49.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/49.rom_ctrl_smoke.3179038399
Short name T271
Test name
Test status
Simulation time 4302927356 ps
CPU time 34.81 seconds
Started May 09 12:38:01 PM PDT 24
Finished May 09 12:38:52 PM PDT 24
Peak memory 213424 kb
Host smart-6d6c4f20-f0d4-4bb5-8d61-d4b3db3f67fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3179038399 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_smoke.3179038399
Directory /workspace/49.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/49.rom_ctrl_stress_all.3174549781
Short name T4
Test name
Test status
Simulation time 2890887028 ps
CPU time 17.1 seconds
Started May 09 12:38:03 PM PDT 24
Finished May 09 12:38:37 PM PDT 24
Peak memory 211644 kb
Host smart-5fcbf575-31de-4dfb-9003-62e79a2fce2c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3174549781 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 49.rom_ctrl_stress_all.3174549781
Directory /workspace/49.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/5.rom_ctrl_alert_test.2294195387
Short name T34
Test name
Test status
Simulation time 4940251152 ps
CPU time 11.57 seconds
Started May 09 12:37:11 PM PDT 24
Finished May 09 12:37:37 PM PDT 24
Peak memory 211816 kb
Host smart-cd327a79-f6b2-4d88-8c6e-deba1ceb898e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2294195387 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_alert_test.2294195387
Directory /workspace/5.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/5.rom_ctrl_corrupt_sig_fatal_chk.3352716483
Short name T300
Test name
Test status
Simulation time 24865592338 ps
CPU time 218.25 seconds
Started May 09 12:37:28 PM PDT 24
Finished May 09 12:41:19 PM PDT 24
Peak memory 213324 kb
Host smart-5c380ac9-5a9a-4cc7-bc1f-6d941180f23c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3352716483 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_c
orrupt_sig_fatal_chk.3352716483
Directory /workspace/5.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/5.rom_ctrl_kmac_err_chk.3629844385
Short name T211
Test name
Test status
Simulation time 11268364594 ps
CPU time 26.18 seconds
Started May 09 12:37:20 PM PDT 24
Finished May 09 12:38:01 PM PDT 24
Peak memory 212740 kb
Host smart-9c590211-5182-4c0c-8d91-e5ae302669f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3629844385 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_kmac_err_chk.3629844385
Directory /workspace/5.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/5.rom_ctrl_max_throughput_chk.1217110809
Short name T99
Test name
Test status
Simulation time 9064725711 ps
CPU time 15.87 seconds
Started May 09 12:37:20 PM PDT 24
Finished May 09 12:37:51 PM PDT 24
Peak memory 211668 kb
Host smart-4271aee8-0d6c-4089-957a-9e3d86133154
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1217110809 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_max_throughput_chk.1217110809
Directory /workspace/5.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/5.rom_ctrl_smoke.570191609
Short name T224
Test name
Test status
Simulation time 1225568562 ps
CPU time 13.42 seconds
Started May 09 12:37:22 PM PDT 24
Finished May 09 12:37:50 PM PDT 24
Peak memory 213296 kb
Host smart-1367060d-49ef-400d-91b2-18fdde7f3920
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=570191609 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_smoke.570191609
Directory /workspace/5.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/5.rom_ctrl_stress_all.1466718415
Short name T25
Test name
Test status
Simulation time 52313264825 ps
CPU time 89.94 seconds
Started May 09 12:37:10 PM PDT 24
Finished May 09 12:38:55 PM PDT 24
Peak memory 219896 kb
Host smart-290ab0a6-dd36-4c82-aa37-06bfc332358c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1466718415 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 5.rom_ctrl_stress_all.1466718415
Directory /workspace/5.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/6.rom_ctrl_alert_test.4256408089
Short name T232
Test name
Test status
Simulation time 861413834 ps
CPU time 9.42 seconds
Started May 09 12:37:18 PM PDT 24
Finished May 09 12:37:42 PM PDT 24
Peak memory 211652 kb
Host smart-9012a803-19f3-4fd7-8f05-ad45f1657298
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4256408089 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_alert_test.4256408089
Directory /workspace/6.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/6.rom_ctrl_corrupt_sig_fatal_chk.1986871816
Short name T185
Test name
Test status
Simulation time 4144970212 ps
CPU time 59.51 seconds
Started May 09 12:37:22 PM PDT 24
Finished May 09 12:38:36 PM PDT 24
Peak memory 221032 kb
Host smart-44e89f10-2729-4d18-b2a2-68e95c3ca21b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1986871816 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_c
orrupt_sig_fatal_chk.1986871816
Directory /workspace/6.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/6.rom_ctrl_kmac_err_chk.763561658
Short name T340
Test name
Test status
Simulation time 168786618 ps
CPU time 9.93 seconds
Started May 09 12:37:35 PM PDT 24
Finished May 09 12:37:56 PM PDT 24
Peak memory 211768 kb
Host smart-71b1cf1d-7224-42f8-be79-39dc255df70f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=763561658 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_kmac_err_chk.763561658
Directory /workspace/6.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/6.rom_ctrl_max_throughput_chk.4292239568
Short name T126
Test name
Test status
Simulation time 20480238432 ps
CPU time 15.25 seconds
Started May 09 12:37:32 PM PDT 24
Finished May 09 12:38:00 PM PDT 24
Peak memory 211716 kb
Host smart-979d4099-c71e-4ce5-84af-e0476c308582
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4292239568 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_max_throughput_chk.4292239568
Directory /workspace/6.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/6.rom_ctrl_smoke.2783170021
Short name T76
Test name
Test status
Simulation time 4514642884 ps
CPU time 17.86 seconds
Started May 09 12:37:16 PM PDT 24
Finished May 09 12:37:49 PM PDT 24
Peak memory 219908 kb
Host smart-62a5a62f-ed0d-4f83-ba0b-d6641b4b7816
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2783170021 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_smoke.2783170021
Directory /workspace/6.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/6.rom_ctrl_stress_all.1924134876
Short name T225
Test name
Test status
Simulation time 4904295661 ps
CPU time 30.65 seconds
Started May 09 12:37:12 PM PDT 24
Finished May 09 12:37:57 PM PDT 24
Peak memory 214356 kb
Host smart-ae1791f8-e648-47d8-8274-7ac5f17a5bdd
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1924134876 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 6.rom_ctrl_stress_all.1924134876
Directory /workspace/6.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/6.rom_ctrl_stress_all_with_rand_reset.94614945
Short name T19
Test name
Test status
Simulation time 22054101934 ps
CPU time 823.73 seconds
Started May 09 12:37:24 PM PDT 24
Finished May 09 12:51:21 PM PDT 24
Peak memory 233976 kb
Host smart-436e0900-a3fb-4548-a282-040abf1ab5d0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=94614945 -assert nopos
tproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_stress_all_with_rand_reset.94614945
Directory /workspace/6.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.rom_ctrl_alert_test.3844030551
Short name T136
Test name
Test status
Simulation time 1512750051 ps
CPU time 13.15 seconds
Started May 09 12:37:24 PM PDT 24
Finished May 09 12:37:51 PM PDT 24
Peak memory 211708 kb
Host smart-cb22284b-795d-4e60-b255-05f59a51e6f6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3844030551 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_alert_test.3844030551
Directory /workspace/7.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/7.rom_ctrl_corrupt_sig_fatal_chk.1493555557
Short name T38
Test name
Test status
Simulation time 1368403186 ps
CPU time 74.57 seconds
Started May 09 12:37:13 PM PDT 24
Finished May 09 12:38:42 PM PDT 24
Peak memory 238132 kb
Host smart-ba0b317e-255e-42fe-a67f-0bc0a4c6ca9d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1493555557 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_c
orrupt_sig_fatal_chk.1493555557
Directory /workspace/7.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/7.rom_ctrl_kmac_err_chk.1325625257
Short name T315
Test name
Test status
Simulation time 7995999747 ps
CPU time 31.35 seconds
Started May 09 12:37:27 PM PDT 24
Finished May 09 12:38:11 PM PDT 24
Peak memory 213092 kb
Host smart-3901e955-d56e-42f0-8b6b-66f268edcd8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1325625257 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_kmac_err_chk.1325625257
Directory /workspace/7.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/7.rom_ctrl_max_throughput_chk.4129357330
Short name T15
Test name
Test status
Simulation time 1492965871 ps
CPU time 9.52 seconds
Started May 09 12:37:40 PM PDT 24
Finished May 09 12:38:00 PM PDT 24
Peak memory 211504 kb
Host smart-c59fd3ab-fa00-4c2b-b99e-6d4481afc7f5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4129357330 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_max_throughput_chk.4129357330
Directory /workspace/7.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/7.rom_ctrl_smoke.2438647563
Short name T93
Test name
Test status
Simulation time 4989722877 ps
CPU time 23.95 seconds
Started May 09 12:37:24 PM PDT 24
Finished May 09 12:38:02 PM PDT 24
Peak memory 214324 kb
Host smart-977c2134-0fc5-4fd5-b70d-9cda987fd669
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2438647563 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_smoke.2438647563
Directory /workspace/7.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/7.rom_ctrl_stress_all.2986775855
Short name T326
Test name
Test status
Simulation time 6681438894 ps
CPU time 51.52 seconds
Started May 09 12:37:15 PM PDT 24
Finished May 09 12:38:21 PM PDT 24
Peak memory 219964 kb
Host smart-2eacce64-59ee-47ee-adb1-109454067a19
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2986775855 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 7.rom_ctrl_stress_all.2986775855
Directory /workspace/7.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/8.rom_ctrl_alert_test.2010210614
Short name T210
Test name
Test status
Simulation time 8186838047 ps
CPU time 16.14 seconds
Started May 09 12:37:27 PM PDT 24
Finished May 09 12:37:56 PM PDT 24
Peak memory 211848 kb
Host smart-fcef5d07-ce2b-42c1-831a-fa8269e2d0cf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2010210614 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_alert_test.2010210614
Directory /workspace/8.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/8.rom_ctrl_corrupt_sig_fatal_chk.1273409488
Short name T48
Test name
Test status
Simulation time 17262869661 ps
CPU time 239.61 seconds
Started May 09 12:37:15 PM PDT 24
Finished May 09 12:41:29 PM PDT 24
Peak memory 232160 kb
Host smart-d928b331-868c-40f1-b24b-bf4bcebf5e1f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1273409488 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_c
orrupt_sig_fatal_chk.1273409488
Directory /workspace/8.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/8.rom_ctrl_kmac_err_chk.3306050825
Short name T365
Test name
Test status
Simulation time 582661169 ps
CPU time 13.17 seconds
Started May 09 12:37:35 PM PDT 24
Finished May 09 12:37:59 PM PDT 24
Peak memory 212532 kb
Host smart-a9bd66f4-30cf-49bf-b4c7-af1b96dd9ac8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3306050825 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_kmac_err_chk.3306050825
Directory /workspace/8.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/8.rom_ctrl_max_throughput_chk.3063678802
Short name T245
Test name
Test status
Simulation time 1683218038 ps
CPU time 14.54 seconds
Started May 09 12:37:19 PM PDT 24
Finished May 09 12:37:48 PM PDT 24
Peak memory 211564 kb
Host smart-e4ea3616-1520-4b64-b532-3e6fb70a25fb
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3063678802 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_max_throughput_chk.3063678802
Directory /workspace/8.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/8.rom_ctrl_smoke.3937455995
Short name T276
Test name
Test status
Simulation time 2110761021 ps
CPU time 14.58 seconds
Started May 09 12:37:16 PM PDT 24
Finished May 09 12:37:45 PM PDT 24
Peak memory 219896 kb
Host smart-7a99f33c-2538-4002-b75b-8f1a31783817
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3937455995 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_smoke.3937455995
Directory /workspace/8.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/8.rom_ctrl_stress_all.4041667900
Short name T351
Test name
Test status
Simulation time 1392716720 ps
CPU time 26.47 seconds
Started May 09 12:37:37 PM PDT 24
Finished May 09 12:38:14 PM PDT 24
Peak memory 216544 kb
Host smart-9d0dd3c1-b249-4607-a702-f56499240617
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4041667900 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 8.rom_ctrl_stress_all.4041667900
Directory /workspace/8.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/8.rom_ctrl_stress_all_with_rand_reset.1354286167
Short name T55
Test name
Test status
Simulation time 380188572293 ps
CPU time 1334.25 seconds
Started May 09 12:37:12 PM PDT 24
Finished May 09 12:59:40 PM PDT 24
Peak memory 234096 kb
Host smart-c128fd1d-17e2-4132-84f3-499a5fddc056
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1354286167 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_stress_all_with_rand_reset.1354286167
Directory /workspace/8.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.rom_ctrl_alert_test.3081373739
Short name T190
Test name
Test status
Simulation time 91854627 ps
CPU time 4.11 seconds
Started May 09 12:37:13 PM PDT 24
Finished May 09 12:37:32 PM PDT 24
Peak memory 211724 kb
Host smart-bd3ceb0e-2454-4811-905b-20b632096eb1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3081373739 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_alert_test.3081373739
Directory /workspace/9.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/9.rom_ctrl_corrupt_sig_fatal_chk.1163656831
Short name T324
Test name
Test status
Simulation time 295568757351 ps
CPU time 323.87 seconds
Started May 09 12:37:17 PM PDT 24
Finished May 09 12:42:55 PM PDT 24
Peak memory 219984 kb
Host smart-7ecb36ab-c636-4a3c-ad47-d8794474c342
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1163656831 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_c
orrupt_sig_fatal_chk.1163656831
Directory /workspace/9.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/9.rom_ctrl_kmac_err_chk.2031665702
Short name T140
Test name
Test status
Simulation time 2535903373 ps
CPU time 18.26 seconds
Started May 09 12:37:26 PM PDT 24
Finished May 09 12:37:57 PM PDT 24
Peak memory 212312 kb
Host smart-ef7bc4bb-6714-450c-a8b5-f0f9cad3e6f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2031665702 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_kmac_err_chk.2031665702
Directory /workspace/9.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/9.rom_ctrl_max_throughput_chk.3271102991
Short name T216
Test name
Test status
Simulation time 822245296 ps
CPU time 10.54 seconds
Started May 09 12:37:10 PM PDT 24
Finished May 09 12:37:34 PM PDT 24
Peak memory 211576 kb
Host smart-5b8cc9e7-08f1-4756-9988-4fae8bf39547
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3271102991 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_max_throughput_chk.3271102991
Directory /workspace/9.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/9.rom_ctrl_smoke.4193972034
Short name T305
Test name
Test status
Simulation time 3928075336 ps
CPU time 35.77 seconds
Started May 09 12:37:07 PM PDT 24
Finished May 09 12:37:55 PM PDT 24
Peak memory 213456 kb
Host smart-700d20fa-8123-4a45-836c-fe7a60f5905f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4193972034 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_smoke.4193972034
Directory /workspace/9.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/9.rom_ctrl_stress_all.1148989211
Short name T63
Test name
Test status
Simulation time 49072449852 ps
CPU time 60.52 seconds
Started May 09 12:37:18 PM PDT 24
Finished May 09 12:38:38 PM PDT 24
Peak memory 219960 kb
Host smart-89ea6cb2-7376-4ff6-850a-1115cf3e009d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1148989211 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 9.rom_ctrl_stress_all.1148989211
Directory /workspace/9.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/9.rom_ctrl_stress_all_with_rand_reset.177097047
Short name T52
Test name
Test status
Simulation time 18102135587 ps
CPU time 3632.76 seconds
Started May 09 12:37:17 PM PDT 24
Finished May 09 01:38:04 PM PDT 24
Peak memory 236432 kb
Host smart-aa715e09-5a2a-4a54-8994-41c74f8e19ea
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=177097047 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_stress_all_with_rand_reset.177097047
Directory /workspace/9.rom_ctrl_stress_all_with_rand_reset/latest
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