| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
| 97.49 | 96.97 | 93.01 | 97.88 | 100.00 | 98.37 | 98.03 | 98.14 |
| T297 | /workspace/coverage/default/45.rom_ctrl_max_throughput_chk.3744337907 | May 12 01:06:30 PM PDT 24 | May 12 01:06:42 PM PDT 24 | 1002817821 ps | ||
| T298 | /workspace/coverage/default/33.rom_ctrl_kmac_err_chk.2232748612 | May 12 01:06:10 PM PDT 24 | May 12 01:06:36 PM PDT 24 | 2746444236 ps | ||
| T299 | /workspace/coverage/default/6.rom_ctrl_alert_test.2521895558 | May 12 01:05:25 PM PDT 24 | May 12 01:05:43 PM PDT 24 | 4278321435 ps | ||
| T300 | /workspace/coverage/default/22.rom_ctrl_max_throughput_chk.4019698259 | May 12 01:05:48 PM PDT 24 | May 12 01:05:58 PM PDT 24 | 625971184 ps | ||
| T301 | /workspace/coverage/default/37.rom_ctrl_smoke.3027271205 | May 12 01:06:12 PM PDT 24 | May 12 01:06:48 PM PDT 24 | 4442759504 ps | ||
| T302 | /workspace/coverage/default/13.rom_ctrl_kmac_err_chk.3253988167 | May 12 01:05:38 PM PDT 24 | May 12 01:06:07 PM PDT 24 | 57263802372 ps | ||
| T303 | /workspace/coverage/default/26.rom_ctrl_alert_test.2580724745 | May 12 01:05:54 PM PDT 24 | May 12 01:06:04 PM PDT 24 | 3268554896 ps | ||
| T304 | /workspace/coverage/default/3.rom_ctrl_max_throughput_chk.3129610522 | May 12 01:05:20 PM PDT 24 | May 12 01:05:26 PM PDT 24 | 96189563 ps | ||
| T305 | /workspace/coverage/default/26.rom_ctrl_kmac_err_chk.2120961542 | May 12 01:05:55 PM PDT 24 | May 12 01:06:26 PM PDT 24 | 13910047645 ps | ||
| T306 | /workspace/coverage/default/17.rom_ctrl_kmac_err_chk.977618791 | May 12 01:05:45 PM PDT 24 | May 12 01:05:55 PM PDT 24 | 1847536904 ps | ||
| T307 | /workspace/coverage/default/33.rom_ctrl_max_throughput_chk.3608207045 | May 12 01:06:02 PM PDT 24 | May 12 01:06:17 PM PDT 24 | 2835410918 ps | ||
| T308 | /workspace/coverage/default/13.rom_ctrl_smoke.3572912345 | May 12 01:05:39 PM PDT 24 | May 12 01:05:49 PM PDT 24 | 708602062 ps | ||
| T309 | /workspace/coverage/default/27.rom_ctrl_stress_all.693507612 | May 12 01:05:55 PM PDT 24 | May 12 01:06:14 PM PDT 24 | 12480649881 ps | ||
| T310 | /workspace/coverage/default/32.rom_ctrl_stress_all.4143349076 | May 12 01:06:02 PM PDT 24 | May 12 01:06:58 PM PDT 24 | 9702645177 ps | ||
| T311 | /workspace/coverage/default/45.rom_ctrl_smoke.2345931618 | May 12 01:06:23 PM PDT 24 | May 12 01:06:56 PM PDT 24 | 5872916335 ps | ||
| T312 | /workspace/coverage/default/1.rom_ctrl_max_throughput_chk.2972109359 | May 12 01:05:14 PM PDT 24 | May 12 01:05:29 PM PDT 24 | 13059629612 ps | ||
| T313 | /workspace/coverage/default/24.rom_ctrl_max_throughput_chk.223059318 | May 12 01:05:51 PM PDT 24 | May 12 01:06:03 PM PDT 24 | 3587054561 ps | ||
| T314 | /workspace/coverage/default/28.rom_ctrl_corrupt_sig_fatal_chk.3293788684 | May 12 01:05:53 PM PDT 24 | May 12 01:09:20 PM PDT 24 | 27702718416 ps | ||
| T315 | /workspace/coverage/default/39.rom_ctrl_max_throughput_chk.1421335911 | May 12 01:06:15 PM PDT 24 | May 12 01:06:28 PM PDT 24 | 1240345263 ps | ||
| T316 | /workspace/coverage/default/15.rom_ctrl_corrupt_sig_fatal_chk.2061698157 | May 12 01:05:40 PM PDT 24 | May 12 01:07:59 PM PDT 24 | 2092794481 ps | ||
| T317 | /workspace/coverage/default/43.rom_ctrl_corrupt_sig_fatal_chk.1579136216 | May 12 01:06:22 PM PDT 24 | May 12 01:13:40 PM PDT 24 | 196272549104 ps | ||
| T318 | /workspace/coverage/default/33.rom_ctrl_alert_test.2139115277 | May 12 01:06:01 PM PDT 24 | May 12 01:06:13 PM PDT 24 | 4237483264 ps | ||
| T319 | /workspace/coverage/default/9.rom_ctrl_corrupt_sig_fatal_chk.3402112742 | May 12 01:05:28 PM PDT 24 | May 12 01:09:17 PM PDT 24 | 87131354645 ps | ||
| T320 | /workspace/coverage/default/21.rom_ctrl_max_throughput_chk.188771771 | May 12 01:05:48 PM PDT 24 | May 12 01:05:55 PM PDT 24 | 938376482 ps | ||
| T321 | /workspace/coverage/default/14.rom_ctrl_alert_test.2353525809 | May 12 01:05:38 PM PDT 24 | May 12 01:05:55 PM PDT 24 | 2144445742 ps | ||
| T322 | /workspace/coverage/default/8.rom_ctrl_kmac_err_chk.2500646105 | May 12 01:05:30 PM PDT 24 | May 12 01:05:58 PM PDT 24 | 8655782320 ps | ||
| T323 | /workspace/coverage/default/36.rom_ctrl_stress_all.2648473000 | May 12 01:06:06 PM PDT 24 | May 12 01:07:33 PM PDT 24 | 8478591902 ps | ||
| T324 | /workspace/coverage/default/42.rom_ctrl_stress_all_with_rand_reset.4150131628 | May 12 01:06:20 PM PDT 24 | May 12 01:45:51 PM PDT 24 | 124393284559 ps | ||
| T325 | /workspace/coverage/default/43.rom_ctrl_kmac_err_chk.1505041389 | May 12 01:06:23 PM PDT 24 | May 12 01:06:54 PM PDT 24 | 3358855473 ps | ||
| T326 | /workspace/coverage/default/12.rom_ctrl_kmac_err_chk.2463091485 | May 12 01:05:34 PM PDT 24 | May 12 01:06:03 PM PDT 24 | 18846888446 ps | ||
| T327 | /workspace/coverage/default/17.rom_ctrl_stress_all.3553581787 | May 12 01:05:45 PM PDT 24 | May 12 01:06:28 PM PDT 24 | 3778185418 ps | ||
| T328 | /workspace/coverage/default/0.rom_ctrl_smoke.3683705782 | May 12 01:05:13 PM PDT 24 | May 12 01:05:35 PM PDT 24 | 2696353589 ps | ||
| T329 | /workspace/coverage/default/48.rom_ctrl_stress_all.2780472349 | May 12 01:06:31 PM PDT 24 | May 12 01:06:59 PM PDT 24 | 10815864508 ps | ||
| T330 | /workspace/coverage/default/38.rom_ctrl_smoke.431208501 | May 12 01:06:14 PM PDT 24 | May 12 01:06:42 PM PDT 24 | 1971984550 ps | ||
| T331 | /workspace/coverage/default/43.rom_ctrl_stress_all.1576432656 | May 12 01:06:21 PM PDT 24 | May 12 01:07:12 PM PDT 24 | 4988315161 ps | ||
| T332 | /workspace/coverage/default/35.rom_ctrl_corrupt_sig_fatal_chk.3678459662 | May 12 01:06:08 PM PDT 24 | May 12 01:10:33 PM PDT 24 | 86175171760 ps | ||
| T333 | /workspace/coverage/default/41.rom_ctrl_stress_all.2340119815 | May 12 01:06:15 PM PDT 24 | May 12 01:07:19 PM PDT 24 | 6288583089 ps | ||
| T334 | /workspace/coverage/default/4.rom_ctrl_kmac_err_chk.1174940585 | May 12 01:05:19 PM PDT 24 | May 12 01:05:54 PM PDT 24 | 10502257136 ps | ||
| T335 | /workspace/coverage/default/24.rom_ctrl_alert_test.2956841242 | May 12 01:05:50 PM PDT 24 | May 12 01:06:05 PM PDT 24 | 1725516498 ps | ||
| T336 | /workspace/coverage/default/2.rom_ctrl_corrupt_sig_fatal_chk.3236669890 | May 12 01:05:18 PM PDT 24 | May 12 01:08:28 PM PDT 24 | 125527622240 ps | ||
| T337 | /workspace/coverage/default/19.rom_ctrl_max_throughput_chk.1235299292 | May 12 01:05:48 PM PDT 24 | May 12 01:06:00 PM PDT 24 | 11869189562 ps | ||
| T338 | /workspace/coverage/default/10.rom_ctrl_kmac_err_chk.2981449496 | May 12 01:05:33 PM PDT 24 | May 12 01:05:46 PM PDT 24 | 2204667589 ps | ||
| T339 | /workspace/coverage/default/46.rom_ctrl_alert_test.1930713754 | May 12 01:06:28 PM PDT 24 | May 12 01:06:40 PM PDT 24 | 1122338792 ps | ||
| T340 | /workspace/coverage/default/44.rom_ctrl_alert_test.3926587907 | May 12 01:06:21 PM PDT 24 | May 12 01:06:29 PM PDT 24 | 425374846 ps | ||
| T341 | /workspace/coverage/default/10.rom_ctrl_smoke.1554943929 | May 12 01:05:29 PM PDT 24 | May 12 01:05:55 PM PDT 24 | 4792893809 ps | ||
| T342 | /workspace/coverage/default/4.rom_ctrl_corrupt_sig_fatal_chk.2905946132 | May 12 01:05:19 PM PDT 24 | May 12 01:08:45 PM PDT 24 | 39480289295 ps | ||
| T343 | /workspace/coverage/default/46.rom_ctrl_smoke.2236853175 | May 12 01:06:29 PM PDT 24 | May 12 01:06:52 PM PDT 24 | 1863330338 ps | ||
| T344 | /workspace/coverage/default/11.rom_ctrl_smoke.1509377876 | May 12 01:05:35 PM PDT 24 | May 12 01:05:57 PM PDT 24 | 3810121359 ps | ||
| T345 | /workspace/coverage/default/10.rom_ctrl_alert_test.554130691 | May 12 01:05:33 PM PDT 24 | May 12 01:05:41 PM PDT 24 | 995833798 ps | ||
| T346 | /workspace/coverage/default/7.rom_ctrl_corrupt_sig_fatal_chk.2021279272 | May 12 01:05:24 PM PDT 24 | May 12 01:07:35 PM PDT 24 | 33917653636 ps | ||
| T347 | /workspace/coverage/default/7.rom_ctrl_stress_all.2211018188 | May 12 01:05:25 PM PDT 24 | May 12 01:05:39 PM PDT 24 | 4042120233 ps | ||
| T348 | /workspace/coverage/default/25.rom_ctrl_stress_all.3850898878 | May 12 01:05:50 PM PDT 24 | May 12 01:06:07 PM PDT 24 | 1178229879 ps | ||
| T349 | /workspace/coverage/default/5.rom_ctrl_alert_test.2691355464 | May 12 01:05:25 PM PDT 24 | May 12 01:05:30 PM PDT 24 | 167981108 ps | ||
| T350 | /workspace/coverage/default/12.rom_ctrl_stress_all.4268950621 | May 12 01:05:33 PM PDT 24 | May 12 01:06:02 PM PDT 24 | 3099871738 ps | ||
| T351 | /workspace/coverage/default/17.rom_ctrl_smoke.1823040951 | May 12 01:05:43 PM PDT 24 | May 12 01:06:02 PM PDT 24 | 1083922289 ps | ||
| T352 | /workspace/coverage/default/47.rom_ctrl_alert_test.3499904557 | May 12 01:06:31 PM PDT 24 | May 12 01:06:39 PM PDT 24 | 846976734 ps | ||
| T353 | /workspace/coverage/default/47.rom_ctrl_kmac_err_chk.3709905824 | May 12 01:06:27 PM PDT 24 | May 12 01:06:41 PM PDT 24 | 2058108369 ps | ||
| T354 | /workspace/coverage/default/19.rom_ctrl_corrupt_sig_fatal_chk.1695479103 | May 12 01:05:46 PM PDT 24 | May 12 01:07:26 PM PDT 24 | 6935687491 ps | ||
| T355 | /workspace/coverage/default/16.rom_ctrl_alert_test.1291176411 | May 12 01:05:44 PM PDT 24 | May 12 01:05:52 PM PDT 24 | 382906034 ps | ||
| T356 | /workspace/coverage/default/46.rom_ctrl_corrupt_sig_fatal_chk.49077179 | May 12 01:06:30 PM PDT 24 | May 12 01:10:10 PM PDT 24 | 86569681003 ps | ||
| T357 | /workspace/coverage/default/18.rom_ctrl_smoke.968420741 | May 12 01:05:47 PM PDT 24 | May 12 01:06:17 PM PDT 24 | 12997409210 ps | ||
| T358 | /workspace/coverage/default/35.rom_ctrl_stress_all_with_rand_reset.1598027097 | May 12 01:06:06 PM PDT 24 | May 12 01:19:02 PM PDT 24 | 75821238061 ps | ||
| T359 | /workspace/coverage/default/29.rom_ctrl_max_throughput_chk.2185903205 | May 12 01:05:57 PM PDT 24 | May 12 01:06:12 PM PDT 24 | 5459495677 ps | ||
| T360 | /workspace/coverage/default/27.rom_ctrl_kmac_err_chk.3698280147 | May 12 01:05:54 PM PDT 24 | May 12 01:06:16 PM PDT 24 | 1753744385 ps | ||
| T361 | /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_errors.2402412585 | May 12 01:05:12 PM PDT 24 | May 12 01:05:28 PM PDT 24 | 13147370727 ps | ||
| T51 | /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_rw.2522325933 | May 12 01:05:00 PM PDT 24 | May 12 01:05:16 PM PDT 24 | 3935370000 ps | ||
| T52 | /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_rw.1980788724 | May 12 01:05:02 PM PDT 24 | May 12 01:05:07 PM PDT 24 | 85524801 ps | ||
| T53 | /workspace/coverage/cover_reg_top/12.rom_ctrl_passthru_mem_tl_intg_err.1016550922 | May 12 01:05:06 PM PDT 24 | May 12 01:05:51 PM PDT 24 | 4540532902 ps | ||
| T87 | /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_hw_reset.1265292315 | May 12 01:04:52 PM PDT 24 | May 12 01:05:06 PM PDT 24 | 4112801354 ps | ||
| T362 | /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_mem_rw_with_rand_reset.596574654 | May 12 01:05:02 PM PDT 24 | May 12 01:05:16 PM PDT 24 | 1414617924 ps | ||
| T363 | /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_errors.3821514665 | May 12 01:04:53 PM PDT 24 | May 12 01:05:10 PM PDT 24 | 5424121729 ps | ||
| T48 | /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_intg_err.3861347264 | May 12 01:05:12 PM PDT 24 | May 12 01:06:31 PM PDT 24 | 2259937531 ps | ||
| T56 | /workspace/coverage/cover_reg_top/0.rom_ctrl_same_csr_outstanding.1316917653 | May 12 01:04:51 PM PDT 24 | May 12 01:05:02 PM PDT 24 | 1822205598 ps | ||
| T57 | /workspace/coverage/cover_reg_top/11.rom_ctrl_same_csr_outstanding.2702321756 | May 12 01:05:03 PM PDT 24 | May 12 01:05:20 PM PDT 24 | 2895436161 ps | ||
| T58 | /workspace/coverage/cover_reg_top/10.rom_ctrl_passthru_mem_tl_intg_err.2961973410 | May 12 01:05:04 PM PDT 24 | May 12 01:05:59 PM PDT 24 | 12778935398 ps | ||
| T49 | /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_intg_err.1949076535 | May 12 01:05:06 PM PDT 24 | May 12 01:06:22 PM PDT 24 | 3058462676 ps | ||
| T88 | /workspace/coverage/cover_reg_top/7.rom_ctrl_passthru_mem_tl_intg_err.1473625279 | May 12 01:05:06 PM PDT 24 | May 12 01:06:44 PM PDT 24 | 51349425957 ps | ||
| T89 | /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_rw.3017993469 | May 12 01:05:07 PM PDT 24 | May 12 01:05:20 PM PDT 24 | 1387428138 ps | ||
| T50 | /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_intg_err.3377863447 | May 12 01:04:50 PM PDT 24 | May 12 01:06:04 PM PDT 24 | 1150941124 ps | ||
| T59 | /workspace/coverage/cover_reg_top/4.rom_ctrl_same_csr_outstanding.633977017 | May 12 01:05:00 PM PDT 24 | May 12 01:05:09 PM PDT 24 | 2654526467 ps | ||
| T60 | /workspace/coverage/cover_reg_top/18.rom_ctrl_passthru_mem_tl_intg_err.4137574983 | May 12 01:05:12 PM PDT 24 | May 12 01:05:43 PM PDT 24 | 7991264385 ps | ||
| T81 | /workspace/coverage/cover_reg_top/6.rom_ctrl_same_csr_outstanding.3110376210 | May 12 01:05:04 PM PDT 24 | May 12 01:05:17 PM PDT 24 | 3074345839 ps | ||
| T96 | /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_intg_err.375578160 | May 12 01:05:06 PM PDT 24 | May 12 01:05:44 PM PDT 24 | 966375620 ps | ||
| T364 | /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_rw.2112894756 | May 12 01:04:56 PM PDT 24 | May 12 01:05:04 PM PDT 24 | 344479523 ps | ||
| T365 | /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_errors.2839326438 | May 12 01:05:14 PM PDT 24 | May 12 01:05:25 PM PDT 24 | 333984292 ps | ||
| T366 | /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_rw.2009636436 | May 12 01:05:09 PM PDT 24 | May 12 01:05:19 PM PDT 24 | 1860890690 ps | ||
| T61 | /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_rw.3841729 | May 12 01:05:05 PM PDT 24 | May 12 01:05:09 PM PDT 24 | 828774897 ps | ||
| T100 | /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_intg_err.2403920944 | May 12 01:05:06 PM PDT 24 | May 12 01:06:19 PM PDT 24 | 3476950776 ps | ||
| T62 | /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_aliasing.2617305412 | May 12 01:05:03 PM PDT 24 | May 12 01:05:10 PM PDT 24 | 2056786496 ps | ||
| T367 | /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_rw.4010081259 | May 12 01:05:13 PM PDT 24 | May 12 01:05:22 PM PDT 24 | 501120034 ps | ||
| T368 | /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_mem_rw_with_rand_reset.1031156039 | May 12 01:05:04 PM PDT 24 | May 12 01:05:16 PM PDT 24 | 6379697807 ps | ||
| T369 | /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_errors.2943615199 | May 12 01:05:14 PM PDT 24 | May 12 01:05:25 PM PDT 24 | 831214046 ps | ||
| T370 | /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_aliasing.172664144 | May 12 01:04:50 PM PDT 24 | May 12 01:05:08 PM PDT 24 | 4101195220 ps | ||
| T101 | /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_intg_err.941066121 | May 12 01:05:07 PM PDT 24 | May 12 01:05:47 PM PDT 24 | 5934760706 ps | ||
| T371 | /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_mem_rw_with_rand_reset.3756012398 | May 12 01:04:51 PM PDT 24 | May 12 01:05:07 PM PDT 24 | 4202599663 ps | ||
| T372 | /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_errors.3607151391 | May 12 01:04:57 PM PDT 24 | May 12 01:05:07 PM PDT 24 | 148147867 ps | ||
| T373 | /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_errors.175417672 | May 12 01:04:45 PM PDT 24 | May 12 01:04:52 PM PDT 24 | 85386553 ps | ||
| T63 | /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_rw.3299393104 | May 12 01:05:06 PM PDT 24 | May 12 01:05:11 PM PDT 24 | 298695237 ps | ||
| T64 | /workspace/coverage/cover_reg_top/1.rom_ctrl_passthru_mem_tl_intg_err.1772084802 | May 12 01:04:52 PM PDT 24 | May 12 01:05:56 PM PDT 24 | 30973298163 ps | ||
| T374 | /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_mem_rw_with_rand_reset.561587530 | May 12 01:04:53 PM PDT 24 | May 12 01:05:00 PM PDT 24 | 1042745793 ps | ||
| T71 | /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_rw.3021435013 | May 12 01:05:07 PM PDT 24 | May 12 01:05:16 PM PDT 24 | 617408455 ps | ||
| T82 | /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_rw.133663516 | May 12 01:04:55 PM PDT 24 | May 12 01:05:08 PM PDT 24 | 1609947499 ps | ||
| T375 | /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_errors.1080591296 | May 12 01:05:01 PM PDT 24 | May 12 01:05:08 PM PDT 24 | 592136845 ps | ||
| T376 | /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_partial_access.3939458522 | May 12 01:04:55 PM PDT 24 | May 12 01:05:00 PM PDT 24 | 168045294 ps | ||
| T83 | /workspace/coverage/cover_reg_top/18.rom_ctrl_same_csr_outstanding.1248653239 | May 12 01:05:13 PM PDT 24 | May 12 01:05:28 PM PDT 24 | 6358537462 ps | ||
| T377 | /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_errors.3902327807 | May 12 01:05:06 PM PDT 24 | May 12 01:05:24 PM PDT 24 | 1872799003 ps | ||
| T84 | /workspace/coverage/cover_reg_top/14.rom_ctrl_same_csr_outstanding.1455993372 | May 12 01:05:06 PM PDT 24 | May 12 01:05:12 PM PDT 24 | 362108845 ps | ||
| T378 | /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_mem_rw_with_rand_reset.2891874236 | May 12 01:05:02 PM PDT 24 | May 12 01:05:14 PM PDT 24 | 2131320841 ps | ||
| T379 | /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_mem_rw_with_rand_reset.2141193258 | May 12 01:05:11 PM PDT 24 | May 12 01:05:19 PM PDT 24 | 1320682689 ps | ||
| T380 | /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_mem_rw_with_rand_reset.704740750 | May 12 01:05:13 PM PDT 24 | May 12 01:05:19 PM PDT 24 | 726306068 ps | ||
| T381 | /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_mem_rw_with_rand_reset.2828384278 | May 12 01:04:58 PM PDT 24 | May 12 01:05:14 PM PDT 24 | 1879468917 ps | ||
| T382 | /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_errors.3351797203 | May 12 01:05:12 PM PDT 24 | May 12 01:05:31 PM PDT 24 | 3415264232 ps | ||
| T72 | /workspace/coverage/cover_reg_top/11.rom_ctrl_passthru_mem_tl_intg_err.510730289 | May 12 01:05:12 PM PDT 24 | May 12 01:05:53 PM PDT 24 | 12850768126 ps | ||
| T383 | /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_bit_bash.2309703292 | May 12 01:04:56 PM PDT 24 | May 12 01:05:05 PM PDT 24 | 2139462532 ps | ||
| T384 | /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_errors.723286753 | May 12 01:05:04 PM PDT 24 | May 12 01:05:21 PM PDT 24 | 2137455641 ps | ||
| T85 | /workspace/coverage/cover_reg_top/15.rom_ctrl_same_csr_outstanding.3026257492 | May 12 01:05:12 PM PDT 24 | May 12 01:05:27 PM PDT 24 | 1993207007 ps | ||
| T385 | /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_errors.3392085348 | May 12 01:05:00 PM PDT 24 | May 12 01:05:17 PM PDT 24 | 5936491142 ps | ||
| T386 | /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_errors.623119943 | May 12 01:04:58 PM PDT 24 | May 12 01:05:13 PM PDT 24 | 5754536456 ps | ||
| T387 | /workspace/coverage/cover_reg_top/13.rom_ctrl_same_csr_outstanding.2203303839 | May 12 01:05:06 PM PDT 24 | May 12 01:05:25 PM PDT 24 | 30735498391 ps | ||
| T388 | /workspace/coverage/cover_reg_top/16.rom_ctrl_same_csr_outstanding.3058317192 | May 12 01:05:15 PM PDT 24 | May 12 01:05:27 PM PDT 24 | 2162955061 ps | ||
| T389 | /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_errors.2604056291 | May 12 01:04:51 PM PDT 24 | May 12 01:05:09 PM PDT 24 | 3347931288 ps | ||
| T104 | /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_intg_err.694481904 | May 12 01:05:13 PM PDT 24 | May 12 01:05:54 PM PDT 24 | 3665973162 ps | ||
| T390 | /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_rw.4223683202 | May 12 01:05:01 PM PDT 24 | May 12 01:05:10 PM PDT 24 | 2748351531 ps | ||
| T97 | /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_intg_err.2665150813 | May 12 01:05:12 PM PDT 24 | May 12 01:05:53 PM PDT 24 | 10367713130 ps | ||
| T73 | /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_aliasing.3803491838 | May 12 01:04:56 PM PDT 24 | May 12 01:05:13 PM PDT 24 | 8593736606 ps | ||
| T391 | /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_hw_reset.2322010415 | May 12 01:04:55 PM PDT 24 | May 12 01:05:09 PM PDT 24 | 1047967545 ps | ||
| T392 | /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_mem_rw_with_rand_reset.2366404402 | May 12 01:05:02 PM PDT 24 | May 12 01:05:14 PM PDT 24 | 8474792791 ps | ||
| T393 | /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_intg_err.4193148536 | May 12 01:05:02 PM PDT 24 | May 12 01:05:48 PM PDT 24 | 7578530502 ps | ||
| T394 | /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_mem_rw_with_rand_reset.2266664142 | May 12 01:05:12 PM PDT 24 | May 12 01:05:25 PM PDT 24 | 2293471138 ps | ||
| T74 | /workspace/coverage/cover_reg_top/16.rom_ctrl_passthru_mem_tl_intg_err.440175882 | May 12 01:05:11 PM PDT 24 | May 12 01:06:18 PM PDT 24 | 28318352676 ps | ||
| T75 | /workspace/coverage/cover_reg_top/13.rom_ctrl_passthru_mem_tl_intg_err.1153807885 | May 12 01:05:06 PM PDT 24 | May 12 01:05:35 PM PDT 24 | 9004269672 ps | ||
| T95 | /workspace/coverage/cover_reg_top/5.rom_ctrl_passthru_mem_tl_intg_err.473726241 | May 12 01:05:01 PM PDT 24 | May 12 01:06:06 PM PDT 24 | 8349166625 ps | ||
| T395 | /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_errors.1226314527 | May 12 01:05:05 PM PDT 24 | May 12 01:05:25 PM PDT 24 | 4878503380 ps | ||
| T396 | /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_mem_rw_with_rand_reset.1072386322 | May 12 01:05:06 PM PDT 24 | May 12 01:05:12 PM PDT 24 | 99058513 ps | ||
| T397 | /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_bit_bash.865577469 | May 12 01:04:57 PM PDT 24 | May 12 01:05:13 PM PDT 24 | 2054317969 ps | ||
| T398 | /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_errors.1023425220 | May 12 01:05:06 PM PDT 24 | May 12 01:05:22 PM PDT 24 | 4230814027 ps | ||
| T399 | /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_mem_rw_with_rand_reset.1568968149 | May 12 01:05:01 PM PDT 24 | May 12 01:05:14 PM PDT 24 | 2448920232 ps | ||
| T400 | /workspace/coverage/cover_reg_top/8.rom_ctrl_same_csr_outstanding.195304038 | May 12 01:05:01 PM PDT 24 | May 12 01:05:13 PM PDT 24 | 1142464332 ps | ||
| T401 | /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_walk.4107998105 | May 12 01:04:59 PM PDT 24 | May 12 01:05:12 PM PDT 24 | 4943662963 ps | ||
| T402 | /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_intg_err.1048789706 | May 12 01:05:13 PM PDT 24 | May 12 01:05:50 PM PDT 24 | 590444755 ps | ||
| T106 | /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_intg_err.4066006458 | May 12 01:05:12 PM PDT 24 | May 12 01:05:50 PM PDT 24 | 673858789 ps | ||
| T403 | /workspace/coverage/cover_reg_top/9.rom_ctrl_same_csr_outstanding.2271084181 | May 12 01:05:12 PM PDT 24 | May 12 01:05:21 PM PDT 24 | 1508103661 ps | ||
| T94 | /workspace/coverage/cover_reg_top/6.rom_ctrl_passthru_mem_tl_intg_err.57944843 | May 12 01:05:03 PM PDT 24 | May 12 01:05:53 PM PDT 24 | 21928910963 ps | ||
| T404 | /workspace/coverage/cover_reg_top/1.rom_ctrl_same_csr_outstanding.4173014287 | May 12 01:04:53 PM PDT 24 | May 12 01:05:09 PM PDT 24 | 8326847634 ps | ||
| T405 | /workspace/coverage/cover_reg_top/2.rom_ctrl_passthru_mem_tl_intg_err.2560235894 | May 12 01:04:53 PM PDT 24 | May 12 01:06:36 PM PDT 24 | 46544989088 ps | ||
| T406 | /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_errors.1138721794 | May 12 01:05:01 PM PDT 24 | May 12 01:05:14 PM PDT 24 | 1420662946 ps | ||
| T407 | /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_partial_access.2937339459 | May 12 01:04:45 PM PDT 24 | May 12 01:05:01 PM PDT 24 | 5442136933 ps | ||
| T98 | /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_intg_err.3745963608 | May 12 01:05:06 PM PDT 24 | May 12 01:05:53 PM PDT 24 | 7906036636 ps | ||
| T408 | /workspace/coverage/cover_reg_top/12.rom_ctrl_same_csr_outstanding.676428168 | May 12 01:05:06 PM PDT 24 | May 12 01:05:11 PM PDT 24 | 90779664 ps | ||
| T409 | /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_errors.3487022233 | May 12 01:05:07 PM PDT 24 | May 12 01:05:15 PM PDT 24 | 95825095 ps | ||
| T410 | /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_mem_rw_with_rand_reset.393871360 | May 12 01:05:03 PM PDT 24 | May 12 01:05:12 PM PDT 24 | 1645639801 ps | ||
| T411 | /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_rw.1478707598 | May 12 01:04:52 PM PDT 24 | May 12 01:05:07 PM PDT 24 | 6956488928 ps | ||
| T99 | /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_intg_err.160149272 | May 12 01:04:56 PM PDT 24 | May 12 01:06:15 PM PDT 24 | 36509247214 ps | ||
| T105 | /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_intg_err.138354074 | May 12 01:05:07 PM PDT 24 | May 12 01:06:20 PM PDT 24 | 2388492683 ps | ||
| T103 | /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_intg_err.1480582256 | May 12 01:05:04 PM PDT 24 | May 12 01:06:22 PM PDT 24 | 7630043352 ps | ||
| T412 | /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_intg_err.3752479910 | May 12 01:04:44 PM PDT 24 | May 12 01:05:21 PM PDT 24 | 2352470378 ps | ||
| T413 | /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_rw.3523536267 | May 12 01:04:55 PM PDT 24 | May 12 01:05:09 PM PDT 24 | 6523483114 ps | ||
| T414 | /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_mem_rw_with_rand_reset.2406478402 | May 12 01:05:03 PM PDT 24 | May 12 01:05:12 PM PDT 24 | 2021498787 ps | ||
| T415 | /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_intg_err.3457652300 | May 12 01:04:57 PM PDT 24 | May 12 01:05:43 PM PDT 24 | 10070098939 ps | ||
| T416 | /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_rw.3288672816 | May 12 01:05:03 PM PDT 24 | May 12 01:05:08 PM PDT 24 | 321331437 ps | ||
| T417 | /workspace/coverage/cover_reg_top/14.rom_ctrl_passthru_mem_tl_intg_err.148553148 | May 12 01:05:04 PM PDT 24 | May 12 01:05:49 PM PDT 24 | 15846063009 ps | ||
| T418 | /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_rw.2092440582 | May 12 01:05:13 PM PDT 24 | May 12 01:05:18 PM PDT 24 | 89282207 ps | ||
| T419 | /workspace/coverage/cover_reg_top/2.rom_ctrl_same_csr_outstanding.867722362 | May 12 01:04:57 PM PDT 24 | May 12 01:05:15 PM PDT 24 | 3994336378 ps | ||
| T420 | /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_mem_rw_with_rand_reset.826724433 | May 12 01:04:57 PM PDT 24 | May 12 01:05:10 PM PDT 24 | 2211414991 ps | ||
| T421 | /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_walk.2353229809 | May 12 01:04:56 PM PDT 24 | May 12 01:05:09 PM PDT 24 | 2826932719 ps | ||
| T422 | /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_rw.1687927481 | May 12 01:05:07 PM PDT 24 | May 12 01:05:22 PM PDT 24 | 6694471336 ps | ||
| T423 | /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_rw.4211075694 | May 12 01:05:17 PM PDT 24 | May 12 01:05:24 PM PDT 24 | 344812760 ps | ||
| T424 | /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_rw.2271988452 | May 12 01:05:12 PM PDT 24 | May 12 01:05:20 PM PDT 24 | 7212399386 ps | ||
| T77 | /workspace/coverage/cover_reg_top/4.rom_ctrl_passthru_mem_tl_intg_err.2921946719 | May 12 01:04:56 PM PDT 24 | May 12 01:05:24 PM PDT 24 | 541916998 ps | ||
| T425 | /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_partial_access.2269539210 | May 12 01:04:57 PM PDT 24 | May 12 01:05:01 PM PDT 24 | 520533904 ps | ||
| T426 | /workspace/coverage/cover_reg_top/15.rom_ctrl_passthru_mem_tl_intg_err.684651964 | May 12 01:05:08 PM PDT 24 | May 12 01:05:59 PM PDT 24 | 11050726853 ps | ||
| T427 | /workspace/coverage/cover_reg_top/10.rom_ctrl_same_csr_outstanding.1347118157 | May 12 01:05:12 PM PDT 24 | May 12 01:05:19 PM PDT 24 | 186047213 ps | ||
| T428 | /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_hw_reset.579724941 | May 12 01:04:49 PM PDT 24 | May 12 01:05:04 PM PDT 24 | 4222062852 ps | ||
| T429 | /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_intg_err.2100675671 | May 12 01:05:06 PM PDT 24 | May 12 01:05:48 PM PDT 24 | 5277497114 ps | ||
| T430 | /workspace/coverage/cover_reg_top/3.rom_ctrl_same_csr_outstanding.3363293340 | May 12 01:05:01 PM PDT 24 | May 12 01:05:06 PM PDT 24 | 88820605 ps | ||
| T431 | /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_rw.44410543 | May 12 01:05:02 PM PDT 24 | May 12 01:05:14 PM PDT 24 | 2177204152 ps | ||
| T432 | /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_walk.2676018980 | May 12 01:05:01 PM PDT 24 | May 12 01:05:11 PM PDT 24 | 1728303002 ps | ||
| T433 | /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_bit_bash.693500339 | May 12 01:04:51 PM PDT 24 | May 12 01:04:56 PM PDT 24 | 87543987 ps | ||
| T434 | /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_mem_rw_with_rand_reset.3232232429 | May 12 01:05:14 PM PDT 24 | May 12 01:05:25 PM PDT 24 | 1687018732 ps | ||
| T435 | /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_errors.1725201470 | May 12 01:05:01 PM PDT 24 | May 12 01:05:22 PM PDT 24 | 7342647482 ps | ||
| T436 | /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_mem_rw_with_rand_reset.1172006060 | May 12 01:05:12 PM PDT 24 | May 12 01:05:23 PM PDT 24 | 879973826 ps | ||
| T437 | /workspace/coverage/cover_reg_top/8.rom_ctrl_passthru_mem_tl_intg_err.1300111908 | May 12 01:05:01 PM PDT 24 | May 12 01:06:08 PM PDT 24 | 25814042709 ps | ||
| T438 | /workspace/coverage/cover_reg_top/17.rom_ctrl_same_csr_outstanding.2435515354 | May 12 01:05:12 PM PDT 24 | May 12 01:05:29 PM PDT 24 | 8347931113 ps | ||
| T439 | /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_partial_access.4176268433 | May 12 01:04:51 PM PDT 24 | May 12 01:05:06 PM PDT 24 | 7329482269 ps | ||
| T440 | /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_mem_rw_with_rand_reset.2322235456 | May 12 01:05:10 PM PDT 24 | May 12 01:05:25 PM PDT 24 | 1701080927 ps | ||
| T441 | /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_intg_err.3414624423 | May 12 01:04:52 PM PDT 24 | May 12 01:06:10 PM PDT 24 | 3586972558 ps | ||
| T442 | /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_hw_reset.2045947538 | May 12 01:04:55 PM PDT 24 | May 12 01:05:15 PM PDT 24 | 8940463292 ps | ||
| T443 | /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_errors.2465203356 | May 12 01:05:00 PM PDT 24 | May 12 01:05:15 PM PDT 24 | 3792139948 ps | ||
| T444 | /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_walk.137931026 | May 12 01:04:50 PM PDT 24 | May 12 01:04:57 PM PDT 24 | 1377249082 ps | ||
| T445 | /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_mem_rw_with_rand_reset.3653447976 | May 12 01:05:03 PM PDT 24 | May 12 01:05:16 PM PDT 24 | 1466316759 ps | ||
| T102 | /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_intg_err.2090495488 | May 12 01:05:00 PM PDT 24 | May 12 01:06:12 PM PDT 24 | 561168187 ps | ||
| T446 | /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_rw.949100103 | May 12 01:04:50 PM PDT 24 | May 12 01:05:02 PM PDT 24 | 1400163265 ps | ||
| T447 | /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_mem_rw_with_rand_reset.2936122453 | May 12 01:05:17 PM PDT 24 | May 12 01:05:25 PM PDT 24 | 450758135 ps | ||
| T448 | /workspace/coverage/cover_reg_top/19.rom_ctrl_same_csr_outstanding.2100962098 | May 12 01:05:17 PM PDT 24 | May 12 01:05:24 PM PDT 24 | 426984690 ps | ||
| T449 | /workspace/coverage/cover_reg_top/3.rom_ctrl_passthru_mem_tl_intg_err.1455771207 | May 12 01:04:57 PM PDT 24 | May 12 01:06:01 PM PDT 24 | 42494295929 ps | ||
| T450 | /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_partial_access.3798039658 | May 12 01:05:00 PM PDT 24 | May 12 01:05:12 PM PDT 24 | 1026875318 ps | ||
| T451 | /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_aliasing.399467704 | May 12 01:05:01 PM PDT 24 | May 12 01:05:15 PM PDT 24 | 1533375026 ps | ||
| T452 | /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_bit_bash.3175784633 | May 12 01:04:50 PM PDT 24 | May 12 01:05:04 PM PDT 24 | 6758671646 ps | ||
| T78 | /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_hw_reset.541257132 | May 12 01:04:54 PM PDT 24 | May 12 01:05:10 PM PDT 24 | 5637517798 ps | ||
| T79 | /workspace/coverage/cover_reg_top/0.rom_ctrl_passthru_mem_tl_intg_err.43426430 | May 12 01:04:44 PM PDT 24 | May 12 01:05:03 PM PDT 24 | 1491334626 ps | ||
| T453 | /workspace/coverage/cover_reg_top/7.rom_ctrl_same_csr_outstanding.2671011496 | May 12 01:05:07 PM PDT 24 | May 12 01:05:21 PM PDT 24 | 5401972102 ps | ||
| T454 | /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_aliasing.345646854 | May 12 01:04:50 PM PDT 24 | May 12 01:05:01 PM PDT 24 | 1039146208 ps | ||
| T455 | /workspace/coverage/cover_reg_top/5.rom_ctrl_same_csr_outstanding.3613254997 | May 12 01:05:03 PM PDT 24 | May 12 01:05:10 PM PDT 24 | 1365403829 ps | ||
| T456 | /workspace/coverage/cover_reg_top/17.rom_ctrl_passthru_mem_tl_intg_err.1627388022 | May 12 01:05:14 PM PDT 24 | May 12 01:06:01 PM PDT 24 | 6236051102 ps | ||
| T457 | /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_walk.1159328653 | May 12 01:04:45 PM PDT 24 | May 12 01:04:55 PM PDT 24 | 2523850851 ps | ||
| T458 | /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_bit_bash.1781189832 | May 12 01:04:56 PM PDT 24 | May 12 01:05:01 PM PDT 24 | 85468893 ps | ||
| T459 | /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_errors.3640133005 | May 12 01:05:01 PM PDT 24 | May 12 01:05:10 PM PDT 24 | 103727825 ps | ||
| T76 | /workspace/coverage/cover_reg_top/9.rom_ctrl_passthru_mem_tl_intg_err.2066983667 | May 12 01:05:01 PM PDT 24 | May 12 01:05:45 PM PDT 24 | 8480069271 ps | ||
| T80 | /workspace/coverage/cover_reg_top/19.rom_ctrl_passthru_mem_tl_intg_err.2680149439 | May 12 01:05:12 PM PDT 24 | May 12 01:05:41 PM PDT 24 | 579472880 ps |
| Test location | /workspace/coverage/default/22.rom_ctrl_stress_all_with_rand_reset.3594347085 |
| Short name | T9 |
| Test name | |
| Test status | |
| Simulation time | 55239256399 ps |
| CPU time | 1428.41 seconds |
| Started | May 12 01:05:50 PM PDT 24 |
| Finished | May 12 01:29:39 PM PDT 24 |
| Peak memory | 236320 kb |
| Host | smart-1bc16c43-d065-4ac8-b28b-57d9fd4f3504 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3594347085 -assert nop ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_stress_all_with_rand_reset.3594347085 |
| Directory | /workspace/22.rom_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/39.rom_ctrl_corrupt_sig_fatal_chk.1453635745 |
| Short name | T13 |
| Test name | |
| Test status | |
| Simulation time | 23306966944 ps |
| CPU time | 255.29 seconds |
| Started | May 12 01:06:15 PM PDT 24 |
| Finished | May 12 01:10:30 PM PDT 24 |
| Peak memory | 238208 kb |
| Host | smart-33194bf4-82bc-43bc-a1ce-33a77cd7ee60 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1453635745 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_ corrupt_sig_fatal_chk.1453635745 |
| Directory | /workspace/39.rom_ctrl_corrupt_sig_fatal_chk/latest |
| Test location | /workspace/coverage/default/44.rom_ctrl_stress_all.3080830072 |
| Short name | T6 |
| Test name | |
| Test status | |
| Simulation time | 21380079319 ps |
| CPU time | 89.62 seconds |
| Started | May 12 01:06:20 PM PDT 24 |
| Finished | May 12 01:07:50 PM PDT 24 |
| Peak memory | 219916 kb |
| Host | smart-92aa186c-7808-44b4-939f-eece7579c162 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3080830072 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm _name 44.rom_ctrl_stress_all.3080830072 |
| Directory | /workspace/44.rom_ctrl_stress_all/latest |
| Test location | /workspace/coverage/default/0.rom_ctrl_corrupt_sig_fatal_chk.2852513758 |
| Short name | T32 |
| Test name | |
| Test status | |
| Simulation time | 52806212825 ps |
| CPU time | 244.67 seconds |
| Started | May 12 01:05:18 PM PDT 24 |
| Finished | May 12 01:09:23 PM PDT 24 |
| Peak memory | 236384 kb |
| Host | smart-ea101fbb-5977-4f2d-a3ca-1a14c525f0ab |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2852513758 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_c orrupt_sig_fatal_chk.2852513758 |
| Directory | /workspace/0.rom_ctrl_corrupt_sig_fatal_chk/latest |
| Test location | /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_intg_err.2403920944 |
| Short name | T100 |
| Test name | |
| Test status | |
| Simulation time | 3476950776 ps |
| CPU time | 72.91 seconds |
| Started | May 12 01:05:06 PM PDT 24 |
| Finished | May 12 01:06:19 PM PDT 24 |
| Peak memory | 219116 kb |
| Host | smart-421adf5b-ee8f-4588-be33-370071d0451a |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2403920944 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_tl_in tg_err.2403920944 |
| Directory | /workspace/7.rom_ctrl_tl_intg_err/latest |
| Test location | /workspace/coverage/default/24.rom_ctrl_corrupt_sig_fatal_chk.2651494917 |
| Short name | T26 |
| Test name | |
| Test status | |
| Simulation time | 15392709292 ps |
| CPU time | 162.47 seconds |
| Started | May 12 01:05:47 PM PDT 24 |
| Finished | May 12 01:08:31 PM PDT 24 |
| Peak memory | 228900 kb |
| Host | smart-e096b19e-5fc8-4b76-989d-055a11a34e49 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2651494917 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_ corrupt_sig_fatal_chk.2651494917 |
| Directory | /workspace/24.rom_ctrl_corrupt_sig_fatal_chk/latest |
| Test location | /workspace/coverage/default/0.rom_ctrl_sec_cm.4159477818 |
| Short name | T15 |
| Test name | |
| Test status | |
| Simulation time | 3062785192 ps |
| CPU time | 106.47 seconds |
| Started | May 12 01:05:15 PM PDT 24 |
| Finished | May 12 01:07:02 PM PDT 24 |
| Peak memory | 237236 kb |
| Host | smart-d335b10c-b9ed-4f45-9b52-b8ad2eff56f5 |
| User | root |
| Command | /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4159477818 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_sec_cm.4159477818 |
| Directory | /workspace/0.rom_ctrl_sec_cm/latest |
| Test location | /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_rw.1980788724 |
| Short name | T52 |
| Test name | |
| Test status | |
| Simulation time | 85524801 ps |
| CPU time | 4.27 seconds |
| Started | May 12 01:05:02 PM PDT 24 |
| Finished | May 12 01:05:07 PM PDT 24 |
| Peak memory | 210744 kb |
| Host | smart-095be97e-075a-4efa-a373-75c1e4a6b068 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1980788724 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_csr_rw.1980788724 |
| Directory | /workspace/10.rom_ctrl_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_intg_err.1949076535 |
| Short name | T49 |
| Test name | |
| Test status | |
| Simulation time | 3058462676 ps |
| CPU time | 75.7 seconds |
| Started | May 12 01:05:06 PM PDT 24 |
| Finished | May 12 01:06:22 PM PDT 24 |
| Peak memory | 211936 kb |
| Host | smart-6ad83ea0-5a4c-4c4d-8405-1e51b6806b7a |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1949076535 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_tl_i ntg_err.1949076535 |
| Directory | /workspace/15.rom_ctrl_tl_intg_err/latest |
| Test location | /workspace/coverage/default/44.rom_ctrl_stress_all_with_rand_reset.279806876 |
| Short name | T44 |
| Test name | |
| Test status | |
| Simulation time | 11803169455 ps |
| CPU time | 446.17 seconds |
| Started | May 12 01:06:21 PM PDT 24 |
| Finished | May 12 01:13:48 PM PDT 24 |
| Peak memory | 229064 kb |
| Host | smart-b744a737-eaef-46b8-b3c8-7d301b764c6a |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=279806876 -assert nopo stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera ge/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_stress_all_with_rand_reset.279806876 |
| Directory | /workspace/44.rom_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/19.rom_ctrl_alert_test.3145263022 |
| Short name | T36 |
| Test name | |
| Test status | |
| Simulation time | 9094503109 ps |
| CPU time | 16.19 seconds |
| Started | May 12 01:05:45 PM PDT 24 |
| Finished | May 12 01:06:02 PM PDT 24 |
| Peak memory | 211680 kb |
| Host | smart-59f96bea-e3f6-4f5a-883a-7788886406f0 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3145263022 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_alert_test.3145263022 |
| Directory | /workspace/19.rom_ctrl_alert_test/latest |
| Test location | /workspace/coverage/default/18.rom_ctrl_kmac_err_chk.3900876654 |
| Short name | T107 |
| Test name | |
| Test status | |
| Simulation time | 5315476114 ps |
| CPU time | 33.95 seconds |
| Started | May 12 01:05:48 PM PDT 24 |
| Finished | May 12 01:06:23 PM PDT 24 |
| Peak memory | 212604 kb |
| Host | smart-337df142-cba8-485a-8f6d-5330f0fd703c |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3900876654 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_kmac_err_chk.3900876654 |
| Directory | /workspace/18.rom_ctrl_kmac_err_chk/latest |
| Test location | /workspace/coverage/default/1.rom_ctrl_kmac_err_chk.1789221621 |
| Short name | T194 |
| Test name | |
| Test status | |
| Simulation time | 171923192 ps |
| CPU time | 9.45 seconds |
| Started | May 12 01:05:20 PM PDT 24 |
| Finished | May 12 01:05:30 PM PDT 24 |
| Peak memory | 211656 kb |
| Host | smart-6935bc24-c6a3-450d-af9d-0e38204f2d8b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1789221621 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_kmac_err_chk.1789221621 |
| Directory | /workspace/1.rom_ctrl_kmac_err_chk/latest |
| Test location | /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_intg_err.3745963608 |
| Short name | T98 |
| Test name | |
| Test status | |
| Simulation time | 7906036636 ps |
| CPU time | 46.23 seconds |
| Started | May 12 01:05:06 PM PDT 24 |
| Finished | May 12 01:05:53 PM PDT 24 |
| Peak memory | 211936 kb |
| Host | smart-9d87324a-7e99-42d7-a623-4676b4301712 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3745963608 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_tl_i ntg_err.3745963608 |
| Directory | /workspace/14.rom_ctrl_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/16.rom_ctrl_passthru_mem_tl_intg_err.440175882 |
| Short name | T74 |
| Test name | |
| Test status | |
| Simulation time | 28318352676 ps |
| CPU time | 65.96 seconds |
| Started | May 12 01:05:11 PM PDT 24 |
| Finished | May 12 01:06:18 PM PDT 24 |
| Peak memory | 210928 kb |
| Host | smart-822c8c6c-661e-4072-b55e-28ad09fd9616 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=440175882 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl _common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_pa ssthru_mem_tl_intg_err.440175882 |
| Directory | /workspace/16.rom_ctrl_passthru_mem_tl_intg_err/latest |
| Test location | /workspace/coverage/default/20.rom_ctrl_smoke.2039564520 |
| Short name | T66 |
| Test name | |
| Test status | |
| Simulation time | 17125546472 ps |
| CPU time | 46.31 seconds |
| Started | May 12 01:05:45 PM PDT 24 |
| Finished | May 12 01:06:32 PM PDT 24 |
| Peak memory | 219856 kb |
| Host | smart-6c0892da-1069-400c-8140-6704a5aeacb8 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2039564520 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_smoke.2039564520 |
| Directory | /workspace/20.rom_ctrl_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/1.rom_ctrl_passthru_mem_tl_intg_err.1772084802 |
| Short name | T64 |
| Test name | |
| Test status | |
| Simulation time | 30973298163 ps |
| CPU time | 63.53 seconds |
| Started | May 12 01:04:52 PM PDT 24 |
| Finished | May 12 01:05:56 PM PDT 24 |
| Peak memory | 210832 kb |
| Host | smart-efbccf63-8dee-4481-bf75-764424e17f3c |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1772084802 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_pa ssthru_mem_tl_intg_err.1772084802 |
| Directory | /workspace/1.rom_ctrl_passthru_mem_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_intg_err.3414624423 |
| Short name | T441 |
| Test name | |
| Test status | |
| Simulation time | 3586972558 ps |
| CPU time | 78 seconds |
| Started | May 12 01:04:52 PM PDT 24 |
| Finished | May 12 01:06:10 PM PDT 24 |
| Peak memory | 219004 kb |
| Host | smart-31aee45d-d02c-4a7a-a496-c839a4105dc3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3414624423 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_tl_in tg_err.3414624423 |
| Directory | /workspace/1.rom_ctrl_tl_intg_err/latest |
| Test location | /workspace/coverage/default/28.rom_ctrl_max_throughput_chk.3897258012 |
| Short name | T86 |
| Test name | |
| Test status | |
| Simulation time | 5601606888 ps |
| CPU time | 15.49 seconds |
| Started | May 12 01:05:54 PM PDT 24 |
| Finished | May 12 01:06:10 PM PDT 24 |
| Peak memory | 211756 kb |
| Host | smart-9ac07d45-1f79-47a3-9bac-26044b119498 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3897258012 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_max_throughput_chk.3897258012 |
| Directory | /workspace/28.rom_ctrl_max_throughput_chk/latest |
| Test location | /workspace/coverage/default/37.rom_ctrl_stress_all_with_rand_reset.1989687439 |
| Short name | T19 |
| Test name | |
| Test status | |
| Simulation time | 165194080935 ps |
| CPU time | 2959.32 seconds |
| Started | May 12 01:06:10 PM PDT 24 |
| Finished | May 12 01:55:31 PM PDT 24 |
| Peak memory | 247076 kb |
| Host | smart-91f23944-21f6-43e2-ac4e-c1840b70efe0 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1989687439 -assert nop ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_stress_all_with_rand_reset.1989687439 |
| Directory | /workspace/37.rom_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_aliasing.172664144 |
| Short name | T370 |
| Test name | |
| Test status | |
| Simulation time | 4101195220 ps |
| CPU time | 16.81 seconds |
| Started | May 12 01:04:50 PM PDT 24 |
| Finished | May 12 01:05:08 PM PDT 24 |
| Peak memory | 210804 kb |
| Host | smart-ce34d34e-a24c-46d5-9c57-84f21852c9e7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=172664144 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_alias ing.172664144 |
| Directory | /workspace/0.rom_ctrl_csr_aliasing/latest |
| Test location | /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_bit_bash.693500339 |
| Short name | T433 |
| Test name | |
| Test status | |
| Simulation time | 87543987 ps |
| CPU time | 4.52 seconds |
| Started | May 12 01:04:51 PM PDT 24 |
| Finished | May 12 01:04:56 PM PDT 24 |
| Peak memory | 210736 kb |
| Host | smart-cb1e8296-4b3a-4759-96b2-b0fa3a6b72a2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=693500339 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_bit_b ash.693500339 |
| Directory | /workspace/0.rom_ctrl_csr_bit_bash/latest |
| Test location | /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_hw_reset.1265292315 |
| Short name | T87 |
| Test name | |
| Test status | |
| Simulation time | 4112801354 ps |
| CPU time | 13.23 seconds |
| Started | May 12 01:04:52 PM PDT 24 |
| Finished | May 12 01:05:06 PM PDT 24 |
| Peak memory | 210908 kb |
| Host | smart-55941d51-6ef8-48f5-ba8c-ffa13b7ed069 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1265292315 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_hw_r eset.1265292315 |
| Directory | /workspace/0.rom_ctrl_csr_hw_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_mem_rw_with_rand_reset.561587530 |
| Short name | T374 |
| Test name | |
| Test status | |
| Simulation time | 1042745793 ps |
| CPU time | 6.69 seconds |
| Started | May 12 01:04:53 PM PDT 24 |
| Finished | May 12 01:05:00 PM PDT 24 |
| Peak memory | 218944 kb |
| Host | smart-78a9ff43-e1e8-4635-b713-f54d99e05351 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=561587530 -assert nopostproc +UVM_TESTNAME= rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_mem_rw_with_rand_reset.561587530 |
| Directory | /workspace/0.rom_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_rw.1478707598 |
| Short name | T411 |
| Test name | |
| Test status | |
| Simulation time | 6956488928 ps |
| CPU time | 14.7 seconds |
| Started | May 12 01:04:52 PM PDT 24 |
| Finished | May 12 01:05:07 PM PDT 24 |
| Peak memory | 210804 kb |
| Host | smart-f80ab197-2029-49a6-94b0-856352ba5e11 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1478707598 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_rw.1478707598 |
| Directory | /workspace/0.rom_ctrl_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_partial_access.2937339459 |
| Short name | T407 |
| Test name | |
| Test status | |
| Simulation time | 5442136933 ps |
| CPU time | 15.41 seconds |
| Started | May 12 01:04:45 PM PDT 24 |
| Finished | May 12 01:05:01 PM PDT 24 |
| Peak memory | 210756 kb |
| Host | smart-7c91e871-2cb1-4049-a687-43be11450f49 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2937339459 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom _ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctr l_mem_partial_access.2937339459 |
| Directory | /workspace/0.rom_ctrl_mem_partial_access/latest |
| Test location | /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_walk.1159328653 |
| Short name | T457 |
| Test name | |
| Test status | |
| Simulation time | 2523850851 ps |
| CPU time | 9.02 seconds |
| Started | May 12 01:04:45 PM PDT 24 |
| Finished | May 12 01:04:55 PM PDT 24 |
| Peak memory | 210944 kb |
| Host | smart-3f8f8817-29dd-4233-9f5e-089d38895559 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1159328653 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_mem_walk .1159328653 |
| Directory | /workspace/0.rom_ctrl_mem_walk/latest |
| Test location | /workspace/coverage/cover_reg_top/0.rom_ctrl_passthru_mem_tl_intg_err.43426430 |
| Short name | T79 |
| Test name | |
| Test status | |
| Simulation time | 1491334626 ps |
| CPU time | 18.16 seconds |
| Started | May 12 01:04:44 PM PDT 24 |
| Finished | May 12 01:05:03 PM PDT 24 |
| Peak memory | 210776 kb |
| Host | smart-941475db-cb23-46ba-8b64-1deda946182f |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=43426430 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_pass thru_mem_tl_intg_err.43426430 |
| Directory | /workspace/0.rom_ctrl_passthru_mem_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/0.rom_ctrl_same_csr_outstanding.1316917653 |
| Short name | T56 |
| Test name | |
| Test status | |
| Simulation time | 1822205598 ps |
| CPU time | 9.89 seconds |
| Started | May 12 01:04:51 PM PDT 24 |
| Finished | May 12 01:05:02 PM PDT 24 |
| Peak memory | 210808 kb |
| Host | smart-4bb8d139-8426-4ca6-8acf-00ae0dedc519 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1316917653 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_c trl_same_csr_outstanding.1316917653 |
| Directory | /workspace/0.rom_ctrl_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_errors.175417672 |
| Short name | T373 |
| Test name | |
| Test status | |
| Simulation time | 85386553 ps |
| CPU time | 6.57 seconds |
| Started | May 12 01:04:45 PM PDT 24 |
| Finished | May 12 01:04:52 PM PDT 24 |
| Peak memory | 219252 kb |
| Host | smart-57e2b106-2833-4c97-bb0a-f26890fb7491 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=175417672 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_tl_errors.175417672 |
| Directory | /workspace/0.rom_ctrl_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_intg_err.3752479910 |
| Short name | T412 |
| Test name | |
| Test status | |
| Simulation time | 2352470378 ps |
| CPU time | 36.34 seconds |
| Started | May 12 01:04:44 PM PDT 24 |
| Finished | May 12 01:05:21 PM PDT 24 |
| Peak memory | 211480 kb |
| Host | smart-44812ba7-4096-41ad-ad36-fcd17ef70f6c |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3752479910 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_tl_in tg_err.3752479910 |
| Directory | /workspace/0.rom_ctrl_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_aliasing.345646854 |
| Short name | T454 |
| Test name | |
| Test status | |
| Simulation time | 1039146208 ps |
| CPU time | 10.18 seconds |
| Started | May 12 01:04:50 PM PDT 24 |
| Finished | May 12 01:05:01 PM PDT 24 |
| Peak memory | 210764 kb |
| Host | smart-e884e436-d31b-4e90-bbab-3c8cdaa43966 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=345646854 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_alias ing.345646854 |
| Directory | /workspace/1.rom_ctrl_csr_aliasing/latest |
| Test location | /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_bit_bash.3175784633 |
| Short name | T452 |
| Test name | |
| Test status | |
| Simulation time | 6758671646 ps |
| CPU time | 13.35 seconds |
| Started | May 12 01:04:50 PM PDT 24 |
| Finished | May 12 01:05:04 PM PDT 24 |
| Peak memory | 210780 kb |
| Host | smart-1b0d016a-f13f-4511-bcb1-96ad9a320b75 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3175784633 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_bit_ bash.3175784633 |
| Directory | /workspace/1.rom_ctrl_csr_bit_bash/latest |
| Test location | /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_hw_reset.579724941 |
| Short name | T428 |
| Test name | |
| Test status | |
| Simulation time | 4222062852 ps |
| CPU time | 14.9 seconds |
| Started | May 12 01:04:49 PM PDT 24 |
| Finished | May 12 01:05:04 PM PDT 24 |
| Peak memory | 210904 kb |
| Host | smart-47be8b1b-9779-45c3-8e1f-dc90a5851d45 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=579724941 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_hw_re set.579724941 |
| Directory | /workspace/1.rom_ctrl_csr_hw_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_mem_rw_with_rand_reset.3756012398 |
| Short name | T371 |
| Test name | |
| Test status | |
| Simulation time | 4202599663 ps |
| CPU time | 16.3 seconds |
| Started | May 12 01:04:51 PM PDT 24 |
| Finished | May 12 01:05:07 PM PDT 24 |
| Peak memory | 213080 kb |
| Host | smart-4a2f8adc-6262-4610-8a75-e079ae682eb5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3756012398 -assert nopostproc +UVM_TESTNAME =rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_mem_rw_with_rand_reset.3756012398 |
| Directory | /workspace/1.rom_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_rw.949100103 |
| Short name | T446 |
| Test name | |
| Test status | |
| Simulation time | 1400163265 ps |
| CPU time | 11.97 seconds |
| Started | May 12 01:04:50 PM PDT 24 |
| Finished | May 12 01:05:02 PM PDT 24 |
| Peak memory | 210740 kb |
| Host | smart-2a0ca185-94ea-440f-89c5-d649649153f8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=949100103 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_rw.949100103 |
| Directory | /workspace/1.rom_ctrl_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_partial_access.4176268433 |
| Short name | T439 |
| Test name | |
| Test status | |
| Simulation time | 7329482269 ps |
| CPU time | 15 seconds |
| Started | May 12 01:04:51 PM PDT 24 |
| Finished | May 12 01:05:06 PM PDT 24 |
| Peak memory | 210676 kb |
| Host | smart-f8d340ee-fcae-406a-8fb0-4136db91a825 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4176268433 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom _ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctr l_mem_partial_access.4176268433 |
| Directory | /workspace/1.rom_ctrl_mem_partial_access/latest |
| Test location | /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_walk.137931026 |
| Short name | T444 |
| Test name | |
| Test status | |
| Simulation time | 1377249082 ps |
| CPU time | 6.39 seconds |
| Started | May 12 01:04:50 PM PDT 24 |
| Finished | May 12 01:04:57 PM PDT 24 |
| Peak memory | 210692 kb |
| Host | smart-802cf381-51dd-45c4-b90a-762fa516d3e4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=137931026 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_mem_walk. 137931026 |
| Directory | /workspace/1.rom_ctrl_mem_walk/latest |
| Test location | /workspace/coverage/cover_reg_top/1.rom_ctrl_same_csr_outstanding.4173014287 |
| Short name | T404 |
| Test name | |
| Test status | |
| Simulation time | 8326847634 ps |
| CPU time | 15.51 seconds |
| Started | May 12 01:04:53 PM PDT 24 |
| Finished | May 12 01:05:09 PM PDT 24 |
| Peak memory | 210816 kb |
| Host | smart-cb24f2eb-d0f4-46da-ab95-0cfe2ede3f8c |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4173014287 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_c trl_same_csr_outstanding.4173014287 |
| Directory | /workspace/1.rom_ctrl_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_errors.3821514665 |
| Short name | T363 |
| Test name | |
| Test status | |
| Simulation time | 5424121729 ps |
| CPU time | 16.96 seconds |
| Started | May 12 01:04:53 PM PDT 24 |
| Finished | May 12 01:05:10 PM PDT 24 |
| Peak memory | 219184 kb |
| Host | smart-96041d6a-fd9a-4af8-9680-853e3dfdb1a9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3821514665 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_tl_errors.3821514665 |
| Directory | /workspace/1.rom_ctrl_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_mem_rw_with_rand_reset.596574654 |
| Short name | T362 |
| Test name | |
| Test status | |
| Simulation time | 1414617924 ps |
| CPU time | 12.7 seconds |
| Started | May 12 01:05:02 PM PDT 24 |
| Finished | May 12 01:05:16 PM PDT 24 |
| Peak memory | 214920 kb |
| Host | smart-66a185e9-9ed4-4b95-b5b5-a49592f6a73c |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=596574654 -assert nopostproc +UVM_TESTNAME= rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_csr_mem_rw_with_rand_reset.596574654 |
| Directory | /workspace/10.rom_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/10.rom_ctrl_passthru_mem_tl_intg_err.2961973410 |
| Short name | T58 |
| Test name | |
| Test status | |
| Simulation time | 12778935398 ps |
| CPU time | 54.02 seconds |
| Started | May 12 01:05:04 PM PDT 24 |
| Finished | May 12 01:05:59 PM PDT 24 |
| Peak memory | 210848 kb |
| Host | smart-d3d72660-3fdc-4a92-af48-c1284227b0b7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2961973410 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_p assthru_mem_tl_intg_err.2961973410 |
| Directory | /workspace/10.rom_ctrl_passthru_mem_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/10.rom_ctrl_same_csr_outstanding.1347118157 |
| Short name | T427 |
| Test name | |
| Test status | |
| Simulation time | 186047213 ps |
| CPU time | 6 seconds |
| Started | May 12 01:05:12 PM PDT 24 |
| Finished | May 12 01:05:19 PM PDT 24 |
| Peak memory | 210760 kb |
| Host | smart-152975f1-07b0-4898-8620-4ac77fa19607 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1347118157 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ ctrl_same_csr_outstanding.1347118157 |
| Directory | /workspace/10.rom_ctrl_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_errors.1080591296 |
| Short name | T375 |
| Test name | |
| Test status | |
| Simulation time | 592136845 ps |
| CPU time | 6.03 seconds |
| Started | May 12 01:05:01 PM PDT 24 |
| Finished | May 12 01:05:08 PM PDT 24 |
| Peak memory | 219328 kb |
| Host | smart-b65c3e8a-d8ac-4e19-be6e-f55edeabeceb |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1080591296 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_tl_errors.1080591296 |
| Directory | /workspace/10.rom_ctrl_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_intg_err.4193148536 |
| Short name | T393 |
| Test name | |
| Test status | |
| Simulation time | 7578530502 ps |
| CPU time | 45.5 seconds |
| Started | May 12 01:05:02 PM PDT 24 |
| Finished | May 12 01:05:48 PM PDT 24 |
| Peak memory | 211960 kb |
| Host | smart-93dbbdb6-ce16-47d8-87e4-1c3bcac7d427 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4193148536 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_tl_i ntg_err.4193148536 |
| Directory | /workspace/10.rom_ctrl_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_mem_rw_with_rand_reset.2266664142 |
| Short name | T394 |
| Test name | |
| Test status | |
| Simulation time | 2293471138 ps |
| CPU time | 11.18 seconds |
| Started | May 12 01:05:12 PM PDT 24 |
| Finished | May 12 01:05:25 PM PDT 24 |
| Peak memory | 214840 kb |
| Host | smart-ecbafed9-bbed-49d2-bb35-cad1ade3c1db |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2266664142 -assert nopostproc +UVM_TESTNAME =rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_csr_mem_rw_with_rand_reset.2266664142 |
| Directory | /workspace/11.rom_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_rw.44410543 |
| Short name | T431 |
| Test name | |
| Test status | |
| Simulation time | 2177204152 ps |
| CPU time | 11.23 seconds |
| Started | May 12 01:05:02 PM PDT 24 |
| Finished | May 12 01:05:14 PM PDT 24 |
| Peak memory | 210772 kb |
| Host | smart-2ea9c8bf-ff1c-43f3-ae1f-1e5b37a19f12 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44410543 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_csr_rw.44410543 |
| Directory | /workspace/11.rom_ctrl_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/11.rom_ctrl_passthru_mem_tl_intg_err.510730289 |
| Short name | T72 |
| Test name | |
| Test status | |
| Simulation time | 12850768126 ps |
| CPU time | 39.55 seconds |
| Started | May 12 01:05:12 PM PDT 24 |
| Finished | May 12 01:05:53 PM PDT 24 |
| Peak memory | 210848 kb |
| Host | smart-ceec5fe4-d740-4b2b-9e3a-d13a820b6757 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=510730289 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl _common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_pa ssthru_mem_tl_intg_err.510730289 |
| Directory | /workspace/11.rom_ctrl_passthru_mem_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/11.rom_ctrl_same_csr_outstanding.2702321756 |
| Short name | T57 |
| Test name | |
| Test status | |
| Simulation time | 2895436161 ps |
| CPU time | 15.81 seconds |
| Started | May 12 01:05:03 PM PDT 24 |
| Finished | May 12 01:05:20 PM PDT 24 |
| Peak memory | 210780 kb |
| Host | smart-e7bab906-a9da-4889-92a5-f289a2f1a3e6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2702321756 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ ctrl_same_csr_outstanding.2702321756 |
| Directory | /workspace/11.rom_ctrl_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_errors.3902327807 |
| Short name | T377 |
| Test name | |
| Test status | |
| Simulation time | 1872799003 ps |
| CPU time | 17.42 seconds |
| Started | May 12 01:05:06 PM PDT 24 |
| Finished | May 12 01:05:24 PM PDT 24 |
| Peak memory | 219124 kb |
| Host | smart-e75716d2-9d09-434f-946e-029cdebc0efb |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3902327807 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_tl_errors.3902327807 |
| Directory | /workspace/11.rom_ctrl_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_intg_err.941066121 |
| Short name | T101 |
| Test name | |
| Test status | |
| Simulation time | 5934760706 ps |
| CPU time | 39.65 seconds |
| Started | May 12 01:05:07 PM PDT 24 |
| Finished | May 12 01:05:47 PM PDT 24 |
| Peak memory | 211976 kb |
| Host | smart-e4255260-033c-4985-8c6d-5b4484854200 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=941066121 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_tl_in tg_err.941066121 |
| Directory | /workspace/11.rom_ctrl_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_mem_rw_with_rand_reset.1072386322 |
| Short name | T396 |
| Test name | |
| Test status | |
| Simulation time | 99058513 ps |
| CPU time | 4.92 seconds |
| Started | May 12 01:05:06 PM PDT 24 |
| Finished | May 12 01:05:12 PM PDT 24 |
| Peak memory | 219044 kb |
| Host | smart-5b594d80-3034-41ce-aabe-3345010193f5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1072386322 -assert nopostproc +UVM_TESTNAME =rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_csr_mem_rw_with_rand_reset.1072386322 |
| Directory | /workspace/12.rom_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_rw.3021435013 |
| Short name | T71 |
| Test name | |
| Test status | |
| Simulation time | 617408455 ps |
| CPU time | 8.32 seconds |
| Started | May 12 01:05:07 PM PDT 24 |
| Finished | May 12 01:05:16 PM PDT 24 |
| Peak memory | 210816 kb |
| Host | smart-7165b186-92f8-43eb-88d0-bdc74ed7d533 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3021435013 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_csr_rw.3021435013 |
| Directory | /workspace/12.rom_ctrl_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/12.rom_ctrl_passthru_mem_tl_intg_err.1016550922 |
| Short name | T53 |
| Test name | |
| Test status | |
| Simulation time | 4540532902 ps |
| CPU time | 44.72 seconds |
| Started | May 12 01:05:06 PM PDT 24 |
| Finished | May 12 01:05:51 PM PDT 24 |
| Peak memory | 210844 kb |
| Host | smart-755a9456-2b47-4a49-96c9-1e8c338710fa |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1016550922 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_p assthru_mem_tl_intg_err.1016550922 |
| Directory | /workspace/12.rom_ctrl_passthru_mem_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/12.rom_ctrl_same_csr_outstanding.676428168 |
| Short name | T408 |
| Test name | |
| Test status | |
| Simulation time | 90779664 ps |
| CPU time | 4.2 seconds |
| Started | May 12 01:05:06 PM PDT 24 |
| Finished | May 12 01:05:11 PM PDT 24 |
| Peak memory | 210764 kb |
| Host | smart-61718402-feae-4355-993b-783b16e467e8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=676428168 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_c trl_same_csr_outstanding.676428168 |
| Directory | /workspace/12.rom_ctrl_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_errors.1023425220 |
| Short name | T398 |
| Test name | |
| Test status | |
| Simulation time | 4230814027 ps |
| CPU time | 15.33 seconds |
| Started | May 12 01:05:06 PM PDT 24 |
| Finished | May 12 01:05:22 PM PDT 24 |
| Peak memory | 219076 kb |
| Host | smart-cd457d71-ea39-4da6-a005-6dcffb88641a |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1023425220 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_tl_errors.1023425220 |
| Directory | /workspace/12.rom_ctrl_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_intg_err.138354074 |
| Short name | T105 |
| Test name | |
| Test status | |
| Simulation time | 2388492683 ps |
| CPU time | 72.22 seconds |
| Started | May 12 01:05:07 PM PDT 24 |
| Finished | May 12 01:06:20 PM PDT 24 |
| Peak memory | 211584 kb |
| Host | smart-867649ea-9034-4cf8-83e8-a5d26a8de3e1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=138354074 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_tl_in tg_err.138354074 |
| Directory | /workspace/12.rom_ctrl_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_mem_rw_with_rand_reset.1172006060 |
| Short name | T436 |
| Test name | |
| Test status | |
| Simulation time | 879973826 ps |
| CPU time | 9.84 seconds |
| Started | May 12 01:05:12 PM PDT 24 |
| Finished | May 12 01:05:23 PM PDT 24 |
| Peak memory | 215684 kb |
| Host | smart-09534940-dc25-45d7-b0f9-9fd6905ee3f2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1172006060 -assert nopostproc +UVM_TESTNAME =rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_csr_mem_rw_with_rand_reset.1172006060 |
| Directory | /workspace/13.rom_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_rw.3017993469 |
| Short name | T89 |
| Test name | |
| Test status | |
| Simulation time | 1387428138 ps |
| CPU time | 11.96 seconds |
| Started | May 12 01:05:07 PM PDT 24 |
| Finished | May 12 01:05:20 PM PDT 24 |
| Peak memory | 210776 kb |
| Host | smart-deb7d266-be8e-45c3-8132-7652565ceeeb |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3017993469 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_csr_rw.3017993469 |
| Directory | /workspace/13.rom_ctrl_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/13.rom_ctrl_passthru_mem_tl_intg_err.1153807885 |
| Short name | T75 |
| Test name | |
| Test status | |
| Simulation time | 9004269672 ps |
| CPU time | 28.26 seconds |
| Started | May 12 01:05:06 PM PDT 24 |
| Finished | May 12 01:05:35 PM PDT 24 |
| Peak memory | 210904 kb |
| Host | smart-eb1a80ca-8d8b-4ec3-96bd-914b934c7d0c |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1153807885 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_p assthru_mem_tl_intg_err.1153807885 |
| Directory | /workspace/13.rom_ctrl_passthru_mem_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/13.rom_ctrl_same_csr_outstanding.2203303839 |
| Short name | T387 |
| Test name | |
| Test status | |
| Simulation time | 30735498391 ps |
| CPU time | 18.35 seconds |
| Started | May 12 01:05:06 PM PDT 24 |
| Finished | May 12 01:05:25 PM PDT 24 |
| Peak memory | 210772 kb |
| Host | smart-95f67bef-56ef-4564-b24c-18e98ca7ea28 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2203303839 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ ctrl_same_csr_outstanding.2203303839 |
| Directory | /workspace/13.rom_ctrl_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_errors.1226314527 |
| Short name | T395 |
| Test name | |
| Test status | |
| Simulation time | 4878503380 ps |
| CPU time | 19.32 seconds |
| Started | May 12 01:05:05 PM PDT 24 |
| Finished | May 12 01:05:25 PM PDT 24 |
| Peak memory | 216520 kb |
| Host | smart-e57952b4-5eb3-498d-b22a-570adb64a316 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1226314527 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_tl_errors.1226314527 |
| Directory | /workspace/13.rom_ctrl_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_intg_err.375578160 |
| Short name | T96 |
| Test name | |
| Test status | |
| Simulation time | 966375620 ps |
| CPU time | 37.1 seconds |
| Started | May 12 01:05:06 PM PDT 24 |
| Finished | May 12 01:05:44 PM PDT 24 |
| Peak memory | 211412 kb |
| Host | smart-e32529cd-b7d4-4dbb-9cd9-65d02b5ca711 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=375578160 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_tl_in tg_err.375578160 |
| Directory | /workspace/13.rom_ctrl_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_mem_rw_with_rand_reset.1031156039 |
| Short name | T368 |
| Test name | |
| Test status | |
| Simulation time | 6379697807 ps |
| CPU time | 11.8 seconds |
| Started | May 12 01:05:04 PM PDT 24 |
| Finished | May 12 01:05:16 PM PDT 24 |
| Peak memory | 214700 kb |
| Host | smart-aa92ca5e-822b-4437-914d-4298095df566 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1031156039 -assert nopostproc +UVM_TESTNAME =rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_csr_mem_rw_with_rand_reset.1031156039 |
| Directory | /workspace/14.rom_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_rw.2009636436 |
| Short name | T366 |
| Test name | |
| Test status | |
| Simulation time | 1860890690 ps |
| CPU time | 10 seconds |
| Started | May 12 01:05:09 PM PDT 24 |
| Finished | May 12 01:05:19 PM PDT 24 |
| Peak memory | 210848 kb |
| Host | smart-284943aa-9920-439e-949e-0c4c62069a68 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2009636436 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_csr_rw.2009636436 |
| Directory | /workspace/14.rom_ctrl_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/14.rom_ctrl_passthru_mem_tl_intg_err.148553148 |
| Short name | T417 |
| Test name | |
| Test status | |
| Simulation time | 15846063009 ps |
| CPU time | 44.59 seconds |
| Started | May 12 01:05:04 PM PDT 24 |
| Finished | May 12 01:05:49 PM PDT 24 |
| Peak memory | 210832 kb |
| Host | smart-bfb75058-08d0-4e3c-bf58-d9c9c2eb6e67 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=148553148 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl _common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_pa ssthru_mem_tl_intg_err.148553148 |
| Directory | /workspace/14.rom_ctrl_passthru_mem_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/14.rom_ctrl_same_csr_outstanding.1455993372 |
| Short name | T84 |
| Test name | |
| Test status | |
| Simulation time | 362108845 ps |
| CPU time | 5.88 seconds |
| Started | May 12 01:05:06 PM PDT 24 |
| Finished | May 12 01:05:12 PM PDT 24 |
| Peak memory | 210724 kb |
| Host | smart-ef3ed2ca-cc78-445b-a47f-dc25d0975722 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1455993372 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ ctrl_same_csr_outstanding.1455993372 |
| Directory | /workspace/14.rom_ctrl_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_errors.723286753 |
| Short name | T384 |
| Test name | |
| Test status | |
| Simulation time | 2137455641 ps |
| CPU time | 16.79 seconds |
| Started | May 12 01:05:04 PM PDT 24 |
| Finished | May 12 01:05:21 PM PDT 24 |
| Peak memory | 219000 kb |
| Host | smart-d7a1a679-1c11-4853-9a4c-a49a7e0e6f17 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=723286753 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_tl_errors.723286753 |
| Directory | /workspace/14.rom_ctrl_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_mem_rw_with_rand_reset.3232232429 |
| Short name | T434 |
| Test name | |
| Test status | |
| Simulation time | 1687018732 ps |
| CPU time | 9.39 seconds |
| Started | May 12 01:05:14 PM PDT 24 |
| Finished | May 12 01:05:25 PM PDT 24 |
| Peak memory | 218988 kb |
| Host | smart-bb63a77c-b780-409e-b13b-c48659a506fc |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3232232429 -assert nopostproc +UVM_TESTNAME =rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_csr_mem_rw_with_rand_reset.3232232429 |
| Directory | /workspace/15.rom_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_rw.1687927481 |
| Short name | T422 |
| Test name | |
| Test status | |
| Simulation time | 6694471336 ps |
| CPU time | 14.15 seconds |
| Started | May 12 01:05:07 PM PDT 24 |
| Finished | May 12 01:05:22 PM PDT 24 |
| Peak memory | 210920 kb |
| Host | smart-ef570ebb-6ab4-46dc-a8b8-7948c066e4d6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1687927481 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_csr_rw.1687927481 |
| Directory | /workspace/15.rom_ctrl_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/15.rom_ctrl_passthru_mem_tl_intg_err.684651964 |
| Short name | T426 |
| Test name | |
| Test status | |
| Simulation time | 11050726853 ps |
| CPU time | 50.86 seconds |
| Started | May 12 01:05:08 PM PDT 24 |
| Finished | May 12 01:05:59 PM PDT 24 |
| Peak memory | 210920 kb |
| Host | smart-03cd3960-f1f9-4442-bae3-d5bf0ebdb0f1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=684651964 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl _common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_pa ssthru_mem_tl_intg_err.684651964 |
| Directory | /workspace/15.rom_ctrl_passthru_mem_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/15.rom_ctrl_same_csr_outstanding.3026257492 |
| Short name | T85 |
| Test name | |
| Test status | |
| Simulation time | 1993207007 ps |
| CPU time | 14.99 seconds |
| Started | May 12 01:05:12 PM PDT 24 |
| Finished | May 12 01:05:27 PM PDT 24 |
| Peak memory | 210848 kb |
| Host | smart-ad29fa1f-8381-4e67-906a-66496c0b5602 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3026257492 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ ctrl_same_csr_outstanding.3026257492 |
| Directory | /workspace/15.rom_ctrl_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_errors.3487022233 |
| Short name | T409 |
| Test name | |
| Test status | |
| Simulation time | 95825095 ps |
| CPU time | 7.05 seconds |
| Started | May 12 01:05:07 PM PDT 24 |
| Finished | May 12 01:05:15 PM PDT 24 |
| Peak memory | 215060 kb |
| Host | smart-7c176562-f2f6-4a2d-8b9d-588c7880c112 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3487022233 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_tl_errors.3487022233 |
| Directory | /workspace/15.rom_ctrl_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_mem_rw_with_rand_reset.2322235456 |
| Short name | T440 |
| Test name | |
| Test status | |
| Simulation time | 1701080927 ps |
| CPU time | 14.14 seconds |
| Started | May 12 01:05:10 PM PDT 24 |
| Finished | May 12 01:05:25 PM PDT 24 |
| Peak memory | 218904 kb |
| Host | smart-98e8b228-babd-4761-a332-990299975875 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2322235456 -assert nopostproc +UVM_TESTNAME =rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_csr_mem_rw_with_rand_reset.2322235456 |
| Directory | /workspace/16.rom_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_rw.2092440582 |
| Short name | T418 |
| Test name | |
| Test status | |
| Simulation time | 89282207 ps |
| CPU time | 4.18 seconds |
| Started | May 12 01:05:13 PM PDT 24 |
| Finished | May 12 01:05:18 PM PDT 24 |
| Peak memory | 210812 kb |
| Host | smart-2c9e72da-f785-47e9-9258-cf334259056f |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2092440582 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_csr_rw.2092440582 |
| Directory | /workspace/16.rom_ctrl_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/16.rom_ctrl_same_csr_outstanding.3058317192 |
| Short name | T388 |
| Test name | |
| Test status | |
| Simulation time | 2162955061 ps |
| CPU time | 11.74 seconds |
| Started | May 12 01:05:15 PM PDT 24 |
| Finished | May 12 01:05:27 PM PDT 24 |
| Peak memory | 210780 kb |
| Host | smart-a24d65bc-cc51-485d-91ec-51c149ec1385 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3058317192 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ ctrl_same_csr_outstanding.3058317192 |
| Directory | /workspace/16.rom_ctrl_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_errors.3351797203 |
| Short name | T382 |
| Test name | |
| Test status | |
| Simulation time | 3415264232 ps |
| CPU time | 17.37 seconds |
| Started | May 12 01:05:12 PM PDT 24 |
| Finished | May 12 01:05:31 PM PDT 24 |
| Peak memory | 215220 kb |
| Host | smart-9f7575df-111a-4a3c-917d-804a5ead9894 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3351797203 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_tl_errors.3351797203 |
| Directory | /workspace/16.rom_ctrl_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_intg_err.2665150813 |
| Short name | T97 |
| Test name | |
| Test status | |
| Simulation time | 10367713130 ps |
| CPU time | 41.07 seconds |
| Started | May 12 01:05:12 PM PDT 24 |
| Finished | May 12 01:05:53 PM PDT 24 |
| Peak memory | 219024 kb |
| Host | smart-d0bbccc1-4954-4448-b1bd-e781182d0fff |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2665150813 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_tl_i ntg_err.2665150813 |
| Directory | /workspace/16.rom_ctrl_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_mem_rw_with_rand_reset.704740750 |
| Short name | T380 |
| Test name | |
| Test status | |
| Simulation time | 726306068 ps |
| CPU time | 5.34 seconds |
| Started | May 12 01:05:13 PM PDT 24 |
| Finished | May 12 01:05:19 PM PDT 24 |
| Peak memory | 218924 kb |
| Host | smart-18b8f194-deb6-4c9d-9689-ceb65ba2f9e6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=704740750 -assert nopostproc +UVM_TESTNAME= rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_csr_mem_rw_with_rand_reset.704740750 |
| Directory | /workspace/17.rom_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_rw.4010081259 |
| Short name | T367 |
| Test name | |
| Test status | |
| Simulation time | 501120034 ps |
| CPU time | 7.74 seconds |
| Started | May 12 01:05:13 PM PDT 24 |
| Finished | May 12 01:05:22 PM PDT 24 |
| Peak memory | 210764 kb |
| Host | smart-b84dc393-8b52-4833-b94e-1c5d9ed1a766 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4010081259 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_csr_rw.4010081259 |
| Directory | /workspace/17.rom_ctrl_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/17.rom_ctrl_passthru_mem_tl_intg_err.1627388022 |
| Short name | T456 |
| Test name | |
| Test status | |
| Simulation time | 6236051102 ps |
| CPU time | 46.54 seconds |
| Started | May 12 01:05:14 PM PDT 24 |
| Finished | May 12 01:06:01 PM PDT 24 |
| Peak memory | 210856 kb |
| Host | smart-dcb538b6-d2f8-42e0-953b-db85bfc29232 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1627388022 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_p assthru_mem_tl_intg_err.1627388022 |
| Directory | /workspace/17.rom_ctrl_passthru_mem_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/17.rom_ctrl_same_csr_outstanding.2435515354 |
| Short name | T438 |
| Test name | |
| Test status | |
| Simulation time | 8347931113 ps |
| CPU time | 16.35 seconds |
| Started | May 12 01:05:12 PM PDT 24 |
| Finished | May 12 01:05:29 PM PDT 24 |
| Peak memory | 210808 kb |
| Host | smart-8707e3eb-c031-414a-8668-7d3974c0c80e |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2435515354 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ ctrl_same_csr_outstanding.2435515354 |
| Directory | /workspace/17.rom_ctrl_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_errors.2839326438 |
| Short name | T365 |
| Test name | |
| Test status | |
| Simulation time | 333984292 ps |
| CPU time | 10.28 seconds |
| Started | May 12 01:05:14 PM PDT 24 |
| Finished | May 12 01:05:25 PM PDT 24 |
| Peak memory | 219104 kb |
| Host | smart-1dcf7236-98ab-49f9-aab8-aa6e4e11aa0d |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2839326438 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_tl_errors.2839326438 |
| Directory | /workspace/17.rom_ctrl_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_intg_err.1048789706 |
| Short name | T402 |
| Test name | |
| Test status | |
| Simulation time | 590444755 ps |
| CPU time | 36.62 seconds |
| Started | May 12 01:05:13 PM PDT 24 |
| Finished | May 12 01:05:50 PM PDT 24 |
| Peak memory | 211752 kb |
| Host | smart-f64c57d7-cfee-4b0d-ba56-c7978c847bed |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1048789706 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_tl_i ntg_err.1048789706 |
| Directory | /workspace/17.rom_ctrl_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_mem_rw_with_rand_reset.2141193258 |
| Short name | T379 |
| Test name | |
| Test status | |
| Simulation time | 1320682689 ps |
| CPU time | 7.07 seconds |
| Started | May 12 01:05:11 PM PDT 24 |
| Finished | May 12 01:05:19 PM PDT 24 |
| Peak memory | 218948 kb |
| Host | smart-d144cee5-5fec-4767-b079-bc4327aeb940 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2141193258 -assert nopostproc +UVM_TESTNAME =rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_csr_mem_rw_with_rand_reset.2141193258 |
| Directory | /workspace/18.rom_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_rw.2271988452 |
| Short name | T424 |
| Test name | |
| Test status | |
| Simulation time | 7212399386 ps |
| CPU time | 8.06 seconds |
| Started | May 12 01:05:12 PM PDT 24 |
| Finished | May 12 01:05:20 PM PDT 24 |
| Peak memory | 210776 kb |
| Host | smart-406b830d-4f39-42ce-b5a7-aeb3003ffb5c |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2271988452 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_csr_rw.2271988452 |
| Directory | /workspace/18.rom_ctrl_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/18.rom_ctrl_passthru_mem_tl_intg_err.4137574983 |
| Short name | T60 |
| Test name | |
| Test status | |
| Simulation time | 7991264385 ps |
| CPU time | 30.19 seconds |
| Started | May 12 01:05:12 PM PDT 24 |
| Finished | May 12 01:05:43 PM PDT 24 |
| Peak memory | 219012 kb |
| Host | smart-40f0b21a-009f-4acc-bd5c-171a11012f92 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4137574983 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_p assthru_mem_tl_intg_err.4137574983 |
| Directory | /workspace/18.rom_ctrl_passthru_mem_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/18.rom_ctrl_same_csr_outstanding.1248653239 |
| Short name | T83 |
| Test name | |
| Test status | |
| Simulation time | 6358537462 ps |
| CPU time | 13.95 seconds |
| Started | May 12 01:05:13 PM PDT 24 |
| Finished | May 12 01:05:28 PM PDT 24 |
| Peak memory | 211132 kb |
| Host | smart-7412afb1-b7db-4aae-8585-6d20fcb84386 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1248653239 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ ctrl_same_csr_outstanding.1248653239 |
| Directory | /workspace/18.rom_ctrl_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_errors.2943615199 |
| Short name | T369 |
| Test name | |
| Test status | |
| Simulation time | 831214046 ps |
| CPU time | 10.07 seconds |
| Started | May 12 01:05:14 PM PDT 24 |
| Finished | May 12 01:05:25 PM PDT 24 |
| Peak memory | 219004 kb |
| Host | smart-2ca3b1c3-d146-4550-8967-b6ce17daab5a |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2943615199 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_tl_errors.2943615199 |
| Directory | /workspace/18.rom_ctrl_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_intg_err.694481904 |
| Short name | T104 |
| Test name | |
| Test status | |
| Simulation time | 3665973162 ps |
| CPU time | 40.19 seconds |
| Started | May 12 01:05:13 PM PDT 24 |
| Finished | May 12 01:05:54 PM PDT 24 |
| Peak memory | 210900 kb |
| Host | smart-2a360819-0b48-474f-998f-331f6bdffad5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=694481904 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_tl_in tg_err.694481904 |
| Directory | /workspace/18.rom_ctrl_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_mem_rw_with_rand_reset.2936122453 |
| Short name | T447 |
| Test name | |
| Test status | |
| Simulation time | 450758135 ps |
| CPU time | 7.47 seconds |
| Started | May 12 01:05:17 PM PDT 24 |
| Finished | May 12 01:05:25 PM PDT 24 |
| Peak memory | 214504 kb |
| Host | smart-af90db5e-40c9-4abb-88f9-b57771afcfeb |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2936122453 -assert nopostproc +UVM_TESTNAME =rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_csr_mem_rw_with_rand_reset.2936122453 |
| Directory | /workspace/19.rom_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_rw.4211075694 |
| Short name | T423 |
| Test name | |
| Test status | |
| Simulation time | 344812760 ps |
| CPU time | 6.24 seconds |
| Started | May 12 01:05:17 PM PDT 24 |
| Finished | May 12 01:05:24 PM PDT 24 |
| Peak memory | 210824 kb |
| Host | smart-21e8eed9-6709-432f-8d98-1adc497761cd |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4211075694 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_csr_rw.4211075694 |
| Directory | /workspace/19.rom_ctrl_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/19.rom_ctrl_passthru_mem_tl_intg_err.2680149439 |
| Short name | T80 |
| Test name | |
| Test status | |
| Simulation time | 579472880 ps |
| CPU time | 28.19 seconds |
| Started | May 12 01:05:12 PM PDT 24 |
| Finished | May 12 01:05:41 PM PDT 24 |
| Peak memory | 210808 kb |
| Host | smart-613f5698-8bca-498f-93d7-bdf468e3c419 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2680149439 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_p assthru_mem_tl_intg_err.2680149439 |
| Directory | /workspace/19.rom_ctrl_passthru_mem_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/19.rom_ctrl_same_csr_outstanding.2100962098 |
| Short name | T448 |
| Test name | |
| Test status | |
| Simulation time | 426984690 ps |
| CPU time | 6.96 seconds |
| Started | May 12 01:05:17 PM PDT 24 |
| Finished | May 12 01:05:24 PM PDT 24 |
| Peak memory | 210824 kb |
| Host | smart-875fcb3d-b60a-49bf-a16e-db4d9aae4008 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2100962098 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ ctrl_same_csr_outstanding.2100962098 |
| Directory | /workspace/19.rom_ctrl_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_errors.2402412585 |
| Short name | T361 |
| Test name | |
| Test status | |
| Simulation time | 13147370727 ps |
| CPU time | 14.77 seconds |
| Started | May 12 01:05:12 PM PDT 24 |
| Finished | May 12 01:05:28 PM PDT 24 |
| Peak memory | 219076 kb |
| Host | smart-2ef8a3cb-2cd6-4b6c-ac1f-e60180b4f129 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2402412585 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_tl_errors.2402412585 |
| Directory | /workspace/19.rom_ctrl_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_intg_err.4066006458 |
| Short name | T106 |
| Test name | |
| Test status | |
| Simulation time | 673858789 ps |
| CPU time | 36.94 seconds |
| Started | May 12 01:05:12 PM PDT 24 |
| Finished | May 12 01:05:50 PM PDT 24 |
| Peak memory | 211804 kb |
| Host | smart-eba039e1-c93a-4cec-b95f-347bbdbbf012 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4066006458 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_tl_i ntg_err.4066006458 |
| Directory | /workspace/19.rom_ctrl_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_aliasing.3803491838 |
| Short name | T73 |
| Test name | |
| Test status | |
| Simulation time | 8593736606 ps |
| CPU time | 16.62 seconds |
| Started | May 12 01:04:56 PM PDT 24 |
| Finished | May 12 01:05:13 PM PDT 24 |
| Peak memory | 210948 kb |
| Host | smart-5b553fdc-aac5-4166-af2d-74cd5ef9787d |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3803491838 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_alia sing.3803491838 |
| Directory | /workspace/2.rom_ctrl_csr_aliasing/latest |
| Test location | /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_bit_bash.1781189832 |
| Short name | T458 |
| Test name | |
| Test status | |
| Simulation time | 85468893 ps |
| CPU time | 4.32 seconds |
| Started | May 12 01:04:56 PM PDT 24 |
| Finished | May 12 01:05:01 PM PDT 24 |
| Peak memory | 210760 kb |
| Host | smart-069bf9ed-21ab-4493-9b5d-773e62a65835 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1781189832 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_bit_ bash.1781189832 |
| Directory | /workspace/2.rom_ctrl_csr_bit_bash/latest |
| Test location | /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_hw_reset.2045947538 |
| Short name | T442 |
| Test name | |
| Test status | |
| Simulation time | 8940463292 ps |
| CPU time | 20.05 seconds |
| Started | May 12 01:04:55 PM PDT 24 |
| Finished | May 12 01:05:15 PM PDT 24 |
| Peak memory | 210924 kb |
| Host | smart-25715921-3f09-44fd-beea-1076152fe118 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2045947538 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_hw_r eset.2045947538 |
| Directory | /workspace/2.rom_ctrl_csr_hw_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_mem_rw_with_rand_reset.826724433 |
| Short name | T420 |
| Test name | |
| Test status | |
| Simulation time | 2211414991 ps |
| CPU time | 12.04 seconds |
| Started | May 12 01:04:57 PM PDT 24 |
| Finished | May 12 01:05:10 PM PDT 24 |
| Peak memory | 215700 kb |
| Host | smart-e12fb58f-adad-47a8-8462-aeee52dbd32c |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=826724433 -assert nopostproc +UVM_TESTNAME= rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_mem_rw_with_rand_reset.826724433 |
| Directory | /workspace/2.rom_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_rw.133663516 |
| Short name | T82 |
| Test name | |
| Test status | |
| Simulation time | 1609947499 ps |
| CPU time | 13.22 seconds |
| Started | May 12 01:04:55 PM PDT 24 |
| Finished | May 12 01:05:08 PM PDT 24 |
| Peak memory | 210812 kb |
| Host | smart-b5599af9-f6a1-4a97-95a8-6522c63ef3b4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=133663516 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_rw.133663516 |
| Directory | /workspace/2.rom_ctrl_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_partial_access.2269539210 |
| Short name | T425 |
| Test name | |
| Test status | |
| Simulation time | 520533904 ps |
| CPU time | 4.08 seconds |
| Started | May 12 01:04:57 PM PDT 24 |
| Finished | May 12 01:05:01 PM PDT 24 |
| Peak memory | 210572 kb |
| Host | smart-c9210ed9-378c-49ab-8362-913db907bb8b |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2269539210 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom _ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctr l_mem_partial_access.2269539210 |
| Directory | /workspace/2.rom_ctrl_mem_partial_access/latest |
| Test location | /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_walk.2353229809 |
| Short name | T421 |
| Test name | |
| Test status | |
| Simulation time | 2826932719 ps |
| CPU time | 12.53 seconds |
| Started | May 12 01:04:56 PM PDT 24 |
| Finished | May 12 01:05:09 PM PDT 24 |
| Peak memory | 210760 kb |
| Host | smart-5edf178d-d01f-498b-b219-95cfe9fb4cad |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2353229809 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_mem_walk .2353229809 |
| Directory | /workspace/2.rom_ctrl_mem_walk/latest |
| Test location | /workspace/coverage/cover_reg_top/2.rom_ctrl_passthru_mem_tl_intg_err.2560235894 |
| Short name | T405 |
| Test name | |
| Test status | |
| Simulation time | 46544989088 ps |
| CPU time | 102.17 seconds |
| Started | May 12 01:04:53 PM PDT 24 |
| Finished | May 12 01:06:36 PM PDT 24 |
| Peak memory | 210872 kb |
| Host | smart-b22ddfd4-cd17-478f-a887-9f15c6726996 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2560235894 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_pa ssthru_mem_tl_intg_err.2560235894 |
| Directory | /workspace/2.rom_ctrl_passthru_mem_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/2.rom_ctrl_same_csr_outstanding.867722362 |
| Short name | T419 |
| Test name | |
| Test status | |
| Simulation time | 3994336378 ps |
| CPU time | 17.5 seconds |
| Started | May 12 01:04:57 PM PDT 24 |
| Finished | May 12 01:05:15 PM PDT 24 |
| Peak memory | 210836 kb |
| Host | smart-2fea0852-f238-4985-a3d3-1a1af9cd85d8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=867722362 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ct rl_same_csr_outstanding.867722362 |
| Directory | /workspace/2.rom_ctrl_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_errors.2604056291 |
| Short name | T389 |
| Test name | |
| Test status | |
| Simulation time | 3347931288 ps |
| CPU time | 17.99 seconds |
| Started | May 12 01:04:51 PM PDT 24 |
| Finished | May 12 01:05:09 PM PDT 24 |
| Peak memory | 215324 kb |
| Host | smart-8b520513-0278-48e5-905b-0a0852fc5f43 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2604056291 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_tl_errors.2604056291 |
| Directory | /workspace/2.rom_ctrl_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_intg_err.3377863447 |
| Short name | T50 |
| Test name | |
| Test status | |
| Simulation time | 1150941124 ps |
| CPU time | 73.48 seconds |
| Started | May 12 01:04:50 PM PDT 24 |
| Finished | May 12 01:06:04 PM PDT 24 |
| Peak memory | 219052 kb |
| Host | smart-4a4c8ea1-91c1-4529-aa7a-5e407ea9e47f |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3377863447 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_tl_in tg_err.3377863447 |
| Directory | /workspace/2.rom_ctrl_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_aliasing.2617305412 |
| Short name | T62 |
| Test name | |
| Test status | |
| Simulation time | 2056786496 ps |
| CPU time | 6.28 seconds |
| Started | May 12 01:05:03 PM PDT 24 |
| Finished | May 12 01:05:10 PM PDT 24 |
| Peak memory | 210744 kb |
| Host | smart-58265057-5204-4160-908a-c031f2052325 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2617305412 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_alia sing.2617305412 |
| Directory | /workspace/3.rom_ctrl_csr_aliasing/latest |
| Test location | /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_bit_bash.2309703292 |
| Short name | T383 |
| Test name | |
| Test status | |
| Simulation time | 2139462532 ps |
| CPU time | 8.06 seconds |
| Started | May 12 01:04:56 PM PDT 24 |
| Finished | May 12 01:05:05 PM PDT 24 |
| Peak memory | 210812 kb |
| Host | smart-79e2c2b6-e7c3-4880-982d-bee48e2f8d59 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2309703292 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_bit_ bash.2309703292 |
| Directory | /workspace/3.rom_ctrl_csr_bit_bash/latest |
| Test location | /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_hw_reset.541257132 |
| Short name | T78 |
| Test name | |
| Test status | |
| Simulation time | 5637517798 ps |
| CPU time | 15.04 seconds |
| Started | May 12 01:04:54 PM PDT 24 |
| Finished | May 12 01:05:10 PM PDT 24 |
| Peak memory | 210832 kb |
| Host | smart-ad727381-a330-4267-a56c-c855aeb801e3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=541257132 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_hw_re set.541257132 |
| Directory | /workspace/3.rom_ctrl_csr_hw_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_mem_rw_with_rand_reset.2828384278 |
| Short name | T381 |
| Test name | |
| Test status | |
| Simulation time | 1879468917 ps |
| CPU time | 15.83 seconds |
| Started | May 12 01:04:58 PM PDT 24 |
| Finished | May 12 01:05:14 PM PDT 24 |
| Peak memory | 218996 kb |
| Host | smart-db65e78d-c2c6-4b01-b852-b89a7635843f |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2828384278 -assert nopostproc +UVM_TESTNAME =rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_mem_rw_with_rand_reset.2828384278 |
| Directory | /workspace/3.rom_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_rw.3523536267 |
| Short name | T413 |
| Test name | |
| Test status | |
| Simulation time | 6523483114 ps |
| CPU time | 13.85 seconds |
| Started | May 12 01:04:55 PM PDT 24 |
| Finished | May 12 01:05:09 PM PDT 24 |
| Peak memory | 210776 kb |
| Host | smart-7e79c06f-bac8-4130-bc87-07aac90476b3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3523536267 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_rw.3523536267 |
| Directory | /workspace/3.rom_ctrl_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_partial_access.3798039658 |
| Short name | T450 |
| Test name | |
| Test status | |
| Simulation time | 1026875318 ps |
| CPU time | 10.33 seconds |
| Started | May 12 01:05:00 PM PDT 24 |
| Finished | May 12 01:05:12 PM PDT 24 |
| Peak memory | 210616 kb |
| Host | smart-f3ff9b7d-3652-444b-b1b6-44a47a4e19b5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3798039658 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom _ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctr l_mem_partial_access.3798039658 |
| Directory | /workspace/3.rom_ctrl_mem_partial_access/latest |
| Test location | /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_walk.4107998105 |
| Short name | T401 |
| Test name | |
| Test status | |
| Simulation time | 4943662963 ps |
| CPU time | 11.89 seconds |
| Started | May 12 01:04:59 PM PDT 24 |
| Finished | May 12 01:05:12 PM PDT 24 |
| Peak memory | 210708 kb |
| Host | smart-a7492826-63c2-45e6-93e7-dde461910c21 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4107998105 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_mem_walk .4107998105 |
| Directory | /workspace/3.rom_ctrl_mem_walk/latest |
| Test location | /workspace/coverage/cover_reg_top/3.rom_ctrl_passthru_mem_tl_intg_err.1455771207 |
| Short name | T449 |
| Test name | |
| Test status | |
| Simulation time | 42494295929 ps |
| CPU time | 63.98 seconds |
| Started | May 12 01:04:57 PM PDT 24 |
| Finished | May 12 01:06:01 PM PDT 24 |
| Peak memory | 210880 kb |
| Host | smart-0f0381d4-7b9c-4c0c-9749-08c50712e8c9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1455771207 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_pa ssthru_mem_tl_intg_err.1455771207 |
| Directory | /workspace/3.rom_ctrl_passthru_mem_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/3.rom_ctrl_same_csr_outstanding.3363293340 |
| Short name | T430 |
| Test name | |
| Test status | |
| Simulation time | 88820605 ps |
| CPU time | 4.17 seconds |
| Started | May 12 01:05:01 PM PDT 24 |
| Finished | May 12 01:05:06 PM PDT 24 |
| Peak memory | 210684 kb |
| Host | smart-fbaa76cd-3a51-424a-b035-e066966822f9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3363293340 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_c trl_same_csr_outstanding.3363293340 |
| Directory | /workspace/3.rom_ctrl_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_errors.623119943 |
| Short name | T386 |
| Test name | |
| Test status | |
| Simulation time | 5754536456 ps |
| CPU time | 15.07 seconds |
| Started | May 12 01:04:58 PM PDT 24 |
| Finished | May 12 01:05:13 PM PDT 24 |
| Peak memory | 219340 kb |
| Host | smart-e5f3a315-9b45-48ac-8df3-f25c7b324888 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=623119943 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_tl_errors.623119943 |
| Directory | /workspace/3.rom_ctrl_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_intg_err.160149272 |
| Short name | T99 |
| Test name | |
| Test status | |
| Simulation time | 36509247214 ps |
| CPU time | 78.02 seconds |
| Started | May 12 01:04:56 PM PDT 24 |
| Finished | May 12 01:06:15 PM PDT 24 |
| Peak memory | 218948 kb |
| Host | smart-da0b162d-a72c-4b03-92a7-33f263b7003c |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=160149272 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_tl_int g_err.160149272 |
| Directory | /workspace/3.rom_ctrl_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_aliasing.399467704 |
| Short name | T451 |
| Test name | |
| Test status | |
| Simulation time | 1533375026 ps |
| CPU time | 13.13 seconds |
| Started | May 12 01:05:01 PM PDT 24 |
| Finished | May 12 01:05:15 PM PDT 24 |
| Peak memory | 210636 kb |
| Host | smart-33f3d6ae-4b58-4d9f-a0a6-003768b17dcb |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=399467704 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_alias ing.399467704 |
| Directory | /workspace/4.rom_ctrl_csr_aliasing/latest |
| Test location | /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_bit_bash.865577469 |
| Short name | T397 |
| Test name | |
| Test status | |
| Simulation time | 2054317969 ps |
| CPU time | 15.46 seconds |
| Started | May 12 01:04:57 PM PDT 24 |
| Finished | May 12 01:05:13 PM PDT 24 |
| Peak memory | 210780 kb |
| Host | smart-ef55a9d9-427a-4e36-8265-6607e18e82d7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=865577469 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_bit_b ash.865577469 |
| Directory | /workspace/4.rom_ctrl_csr_bit_bash/latest |
| Test location | /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_hw_reset.2322010415 |
| Short name | T391 |
| Test name | |
| Test status | |
| Simulation time | 1047967545 ps |
| CPU time | 13.54 seconds |
| Started | May 12 01:04:55 PM PDT 24 |
| Finished | May 12 01:05:09 PM PDT 24 |
| Peak memory | 210752 kb |
| Host | smart-b181d028-e061-4a8a-979f-bdfc6c62dd22 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2322010415 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_hw_r eset.2322010415 |
| Directory | /workspace/4.rom_ctrl_csr_hw_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_mem_rw_with_rand_reset.2366404402 |
| Short name | T392 |
| Test name | |
| Test status | |
| Simulation time | 8474792791 ps |
| CPU time | 10.69 seconds |
| Started | May 12 01:05:02 PM PDT 24 |
| Finished | May 12 01:05:14 PM PDT 24 |
| Peak memory | 219164 kb |
| Host | smart-3cf525f8-1a9c-4a87-8008-82907eb8d35e |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2366404402 -assert nopostproc +UVM_TESTNAME =rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_mem_rw_with_rand_reset.2366404402 |
| Directory | /workspace/4.rom_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_rw.2112894756 |
| Short name | T364 |
| Test name | |
| Test status | |
| Simulation time | 344479523 ps |
| CPU time | 6.5 seconds |
| Started | May 12 01:04:56 PM PDT 24 |
| Finished | May 12 01:05:04 PM PDT 24 |
| Peak memory | 210812 kb |
| Host | smart-388c5d2d-e9c6-42bd-abfd-4293531d0cc2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2112894756 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_rw.2112894756 |
| Directory | /workspace/4.rom_ctrl_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_partial_access.3939458522 |
| Short name | T376 |
| Test name | |
| Test status | |
| Simulation time | 168045294 ps |
| CPU time | 4.13 seconds |
| Started | May 12 01:04:55 PM PDT 24 |
| Finished | May 12 01:05:00 PM PDT 24 |
| Peak memory | 210724 kb |
| Host | smart-43c928bd-8296-4cf1-a49e-4876c4f1b9d5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3939458522 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom _ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctr l_mem_partial_access.3939458522 |
| Directory | /workspace/4.rom_ctrl_mem_partial_access/latest |
| Test location | /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_walk.2676018980 |
| Short name | T432 |
| Test name | |
| Test status | |
| Simulation time | 1728303002 ps |
| CPU time | 8.92 seconds |
| Started | May 12 01:05:01 PM PDT 24 |
| Finished | May 12 01:05:11 PM PDT 24 |
| Peak memory | 210584 kb |
| Host | smart-97ac1d53-0cd5-415c-889e-87cd7f240f18 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2676018980 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_mem_walk .2676018980 |
| Directory | /workspace/4.rom_ctrl_mem_walk/latest |
| Test location | /workspace/coverage/cover_reg_top/4.rom_ctrl_passthru_mem_tl_intg_err.2921946719 |
| Short name | T77 |
| Test name | |
| Test status | |
| Simulation time | 541916998 ps |
| CPU time | 27.68 seconds |
| Started | May 12 01:04:56 PM PDT 24 |
| Finished | May 12 01:05:24 PM PDT 24 |
| Peak memory | 210908 kb |
| Host | smart-d1307197-1a18-423c-9066-487b72c2506a |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2921946719 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_pa ssthru_mem_tl_intg_err.2921946719 |
| Directory | /workspace/4.rom_ctrl_passthru_mem_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/4.rom_ctrl_same_csr_outstanding.633977017 |
| Short name | T59 |
| Test name | |
| Test status | |
| Simulation time | 2654526467 ps |
| CPU time | 7.23 seconds |
| Started | May 12 01:05:00 PM PDT 24 |
| Finished | May 12 01:05:09 PM PDT 24 |
| Peak memory | 210876 kb |
| Host | smart-820218b0-9b06-473a-bd39-bad57f71c302 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=633977017 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ct rl_same_csr_outstanding.633977017 |
| Directory | /workspace/4.rom_ctrl_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_errors.3607151391 |
| Short name | T372 |
| Test name | |
| Test status | |
| Simulation time | 148147867 ps |
| CPU time | 9.99 seconds |
| Started | May 12 01:04:57 PM PDT 24 |
| Finished | May 12 01:05:07 PM PDT 24 |
| Peak memory | 219036 kb |
| Host | smart-61cfa526-57d4-4afc-8fff-2011d71ad99e |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3607151391 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_tl_errors.3607151391 |
| Directory | /workspace/4.rom_ctrl_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_intg_err.3457652300 |
| Short name | T415 |
| Test name | |
| Test status | |
| Simulation time | 10070098939 ps |
| CPU time | 45.57 seconds |
| Started | May 12 01:04:57 PM PDT 24 |
| Finished | May 12 01:05:43 PM PDT 24 |
| Peak memory | 212004 kb |
| Host | smart-02ce0dbe-8d30-4a59-84e9-9adb04a934ce |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3457652300 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_tl_in tg_err.3457652300 |
| Directory | /workspace/4.rom_ctrl_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_mem_rw_with_rand_reset.1568968149 |
| Short name | T399 |
| Test name | |
| Test status | |
| Simulation time | 2448920232 ps |
| CPU time | 11.66 seconds |
| Started | May 12 01:05:01 PM PDT 24 |
| Finished | May 12 01:05:14 PM PDT 24 |
| Peak memory | 212108 kb |
| Host | smart-5dfa3f20-c867-4090-8df1-2f6a26a5a7f5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1568968149 -assert nopostproc +UVM_TESTNAME =rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_csr_mem_rw_with_rand_reset.1568968149 |
| Directory | /workspace/5.rom_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_rw.3299393104 |
| Short name | T63 |
| Test name | |
| Test status | |
| Simulation time | 298695237 ps |
| CPU time | 4.06 seconds |
| Started | May 12 01:05:06 PM PDT 24 |
| Finished | May 12 01:05:11 PM PDT 24 |
| Peak memory | 210764 kb |
| Host | smart-3efc3b74-cea1-4f7f-b8a3-8856c01fd1ee |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3299393104 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_csr_rw.3299393104 |
| Directory | /workspace/5.rom_ctrl_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/5.rom_ctrl_passthru_mem_tl_intg_err.473726241 |
| Short name | T95 |
| Test name | |
| Test status | |
| Simulation time | 8349166625 ps |
| CPU time | 63.52 seconds |
| Started | May 12 01:05:01 PM PDT 24 |
| Finished | May 12 01:06:06 PM PDT 24 |
| Peak memory | 210824 kb |
| Host | smart-8eb60a40-8808-46ec-ba09-b6c6a64abd75 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=473726241 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl _common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_pas sthru_mem_tl_intg_err.473726241 |
| Directory | /workspace/5.rom_ctrl_passthru_mem_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/5.rom_ctrl_same_csr_outstanding.3613254997 |
| Short name | T455 |
| Test name | |
| Test status | |
| Simulation time | 1365403829 ps |
| CPU time | 6.29 seconds |
| Started | May 12 01:05:03 PM PDT 24 |
| Finished | May 12 01:05:10 PM PDT 24 |
| Peak memory | 210776 kb |
| Host | smart-97e03c75-b637-4f23-a567-2b3027b84b18 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3613254997 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_c trl_same_csr_outstanding.3613254997 |
| Directory | /workspace/5.rom_ctrl_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_errors.1725201470 |
| Short name | T435 |
| Test name | |
| Test status | |
| Simulation time | 7342647482 ps |
| CPU time | 20.15 seconds |
| Started | May 12 01:05:01 PM PDT 24 |
| Finished | May 12 01:05:22 PM PDT 24 |
| Peak memory | 219000 kb |
| Host | smart-7d26559c-806e-4843-80cf-048bb5c794dc |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1725201470 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_tl_errors.1725201470 |
| Directory | /workspace/5.rom_ctrl_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_intg_err.2090495488 |
| Short name | T102 |
| Test name | |
| Test status | |
| Simulation time | 561168187 ps |
| CPU time | 70.55 seconds |
| Started | May 12 01:05:00 PM PDT 24 |
| Finished | May 12 01:06:12 PM PDT 24 |
| Peak memory | 210836 kb |
| Host | smart-f8248ebe-2fac-495d-b2f4-973731b314e3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2090495488 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_tl_in tg_err.2090495488 |
| Directory | /workspace/5.rom_ctrl_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_mem_rw_with_rand_reset.2891874236 |
| Short name | T378 |
| Test name | |
| Test status | |
| Simulation time | 2131320841 ps |
| CPU time | 10.7 seconds |
| Started | May 12 01:05:02 PM PDT 24 |
| Finished | May 12 01:05:14 PM PDT 24 |
| Peak memory | 215484 kb |
| Host | smart-4b6da538-9bf9-404f-85c4-e334ed29f13d |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2891874236 -assert nopostproc +UVM_TESTNAME =rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_csr_mem_rw_with_rand_reset.2891874236 |
| Directory | /workspace/6.rom_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_rw.2522325933 |
| Short name | T51 |
| Test name | |
| Test status | |
| Simulation time | 3935370000 ps |
| CPU time | 15.04 seconds |
| Started | May 12 01:05:00 PM PDT 24 |
| Finished | May 12 01:05:16 PM PDT 24 |
| Peak memory | 210752 kb |
| Host | smart-9c9461ea-3741-49f4-98f2-4df215f8d314 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2522325933 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_csr_rw.2522325933 |
| Directory | /workspace/6.rom_ctrl_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/6.rom_ctrl_passthru_mem_tl_intg_err.57944843 |
| Short name | T94 |
| Test name | |
| Test status | |
| Simulation time | 21928910963 ps |
| CPU time | 49.45 seconds |
| Started | May 12 01:05:03 PM PDT 24 |
| Finished | May 12 01:05:53 PM PDT 24 |
| Peak memory | 210752 kb |
| Host | smart-29497ecc-9c37-4fa6-9ed4-e7710489f319 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57944843 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_pass thru_mem_tl_intg_err.57944843 |
| Directory | /workspace/6.rom_ctrl_passthru_mem_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/6.rom_ctrl_same_csr_outstanding.3110376210 |
| Short name | T81 |
| Test name | |
| Test status | |
| Simulation time | 3074345839 ps |
| CPU time | 12.74 seconds |
| Started | May 12 01:05:04 PM PDT 24 |
| Finished | May 12 01:05:17 PM PDT 24 |
| Peak memory | 210792 kb |
| Host | smart-79e8c0ea-c4f1-4a6e-9957-b162ed7c298a |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3110376210 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_c trl_same_csr_outstanding.3110376210 |
| Directory | /workspace/6.rom_ctrl_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_errors.3392085348 |
| Short name | T385 |
| Test name | |
| Test status | |
| Simulation time | 5936491142 ps |
| CPU time | 16.41 seconds |
| Started | May 12 01:05:00 PM PDT 24 |
| Finished | May 12 01:05:17 PM PDT 24 |
| Peak memory | 219196 kb |
| Host | smart-ed83a0ac-a32b-488b-aecc-6fa0869c2151 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3392085348 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_tl_errors.3392085348 |
| Directory | /workspace/6.rom_ctrl_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_intg_err.2100675671 |
| Short name | T429 |
| Test name | |
| Test status | |
| Simulation time | 5277497114 ps |
| CPU time | 41.65 seconds |
| Started | May 12 01:05:06 PM PDT 24 |
| Finished | May 12 01:05:48 PM PDT 24 |
| Peak memory | 210988 kb |
| Host | smart-8420c043-2228-41b5-a29f-1342b7f6e258 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2100675671 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_tl_in tg_err.2100675671 |
| Directory | /workspace/6.rom_ctrl_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_mem_rw_with_rand_reset.2406478402 |
| Short name | T414 |
| Test name | |
| Test status | |
| Simulation time | 2021498787 ps |
| CPU time | 7.91 seconds |
| Started | May 12 01:05:03 PM PDT 24 |
| Finished | May 12 01:05:12 PM PDT 24 |
| Peak memory | 219012 kb |
| Host | smart-ab0d7c9a-bf5c-4dfd-971d-863001a5c2c1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2406478402 -assert nopostproc +UVM_TESTNAME =rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_csr_mem_rw_with_rand_reset.2406478402 |
| Directory | /workspace/7.rom_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_rw.4223683202 |
| Short name | T390 |
| Test name | |
| Test status | |
| Simulation time | 2748351531 ps |
| CPU time | 8.37 seconds |
| Started | May 12 01:05:01 PM PDT 24 |
| Finished | May 12 01:05:10 PM PDT 24 |
| Peak memory | 210780 kb |
| Host | smart-5fe246ca-532d-46cc-bc05-735690539d91 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4223683202 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_csr_rw.4223683202 |
| Directory | /workspace/7.rom_ctrl_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/7.rom_ctrl_passthru_mem_tl_intg_err.1473625279 |
| Short name | T88 |
| Test name | |
| Test status | |
| Simulation time | 51349425957 ps |
| CPU time | 97.24 seconds |
| Started | May 12 01:05:06 PM PDT 24 |
| Finished | May 12 01:06:44 PM PDT 24 |
| Peak memory | 210916 kb |
| Host | smart-c5dbab38-0f30-4d4b-bd07-715a99c0cac6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1473625279 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_pa ssthru_mem_tl_intg_err.1473625279 |
| Directory | /workspace/7.rom_ctrl_passthru_mem_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/7.rom_ctrl_same_csr_outstanding.2671011496 |
| Short name | T453 |
| Test name | |
| Test status | |
| Simulation time | 5401972102 ps |
| CPU time | 13.56 seconds |
| Started | May 12 01:05:07 PM PDT 24 |
| Finished | May 12 01:05:21 PM PDT 24 |
| Peak memory | 210860 kb |
| Host | smart-bdf1f2f7-d8da-4102-9fae-4a9b5be0e4f3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2671011496 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_c trl_same_csr_outstanding.2671011496 |
| Directory | /workspace/7.rom_ctrl_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_errors.3640133005 |
| Short name | T459 |
| Test name | |
| Test status | |
| Simulation time | 103727825 ps |
| CPU time | 7.59 seconds |
| Started | May 12 01:05:01 PM PDT 24 |
| Finished | May 12 01:05:10 PM PDT 24 |
| Peak memory | 218988 kb |
| Host | smart-3d085b9e-4527-4315-95d7-14fb64c8bbbb |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3640133005 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_tl_errors.3640133005 |
| Directory | /workspace/7.rom_ctrl_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_mem_rw_with_rand_reset.3653447976 |
| Short name | T445 |
| Test name | |
| Test status | |
| Simulation time | 1466316759 ps |
| CPU time | 12.7 seconds |
| Started | May 12 01:05:03 PM PDT 24 |
| Finished | May 12 01:05:16 PM PDT 24 |
| Peak memory | 215844 kb |
| Host | smart-84fc7ab0-8f5a-44ab-8954-e2f2d3047f15 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3653447976 -assert nopostproc +UVM_TESTNAME =rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_csr_mem_rw_with_rand_reset.3653447976 |
| Directory | /workspace/8.rom_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_rw.3288672816 |
| Short name | T416 |
| Test name | |
| Test status | |
| Simulation time | 321331437 ps |
| CPU time | 4.25 seconds |
| Started | May 12 01:05:03 PM PDT 24 |
| Finished | May 12 01:05:08 PM PDT 24 |
| Peak memory | 210700 kb |
| Host | smart-10a6f82e-a454-4189-9934-2f82d1d0977c |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3288672816 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_csr_rw.3288672816 |
| Directory | /workspace/8.rom_ctrl_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/8.rom_ctrl_passthru_mem_tl_intg_err.1300111908 |
| Short name | T437 |
| Test name | |
| Test status | |
| Simulation time | 25814042709 ps |
| CPU time | 66.08 seconds |
| Started | May 12 01:05:01 PM PDT 24 |
| Finished | May 12 01:06:08 PM PDT 24 |
| Peak memory | 210884 kb |
| Host | smart-3df4dfa8-e39f-4ffe-9fde-7f585412321c |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1300111908 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_pa ssthru_mem_tl_intg_err.1300111908 |
| Directory | /workspace/8.rom_ctrl_passthru_mem_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/8.rom_ctrl_same_csr_outstanding.195304038 |
| Short name | T400 |
| Test name | |
| Test status | |
| Simulation time | 1142464332 ps |
| CPU time | 11.06 seconds |
| Started | May 12 01:05:01 PM PDT 24 |
| Finished | May 12 01:05:13 PM PDT 24 |
| Peak memory | 210712 kb |
| Host | smart-43e57b6f-8ce9-456b-a2ab-426006fe385b |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=195304038 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ct rl_same_csr_outstanding.195304038 |
| Directory | /workspace/8.rom_ctrl_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_errors.1138721794 |
| Short name | T406 |
| Test name | |
| Test status | |
| Simulation time | 1420662946 ps |
| CPU time | 12.08 seconds |
| Started | May 12 01:05:01 PM PDT 24 |
| Finished | May 12 01:05:14 PM PDT 24 |
| Peak memory | 215136 kb |
| Host | smart-f51f03d8-a887-40bb-9ccb-621f6cdead71 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1138721794 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_tl_errors.1138721794 |
| Directory | /workspace/8.rom_ctrl_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_intg_err.3861347264 |
| Short name | T48 |
| Test name | |
| Test status | |
| Simulation time | 2259937531 ps |
| CPU time | 77.82 seconds |
| Started | May 12 01:05:12 PM PDT 24 |
| Finished | May 12 01:06:31 PM PDT 24 |
| Peak memory | 219020 kb |
| Host | smart-4b4f9781-52e8-4e05-8d3f-232d58332de3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3861347264 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_tl_in tg_err.3861347264 |
| Directory | /workspace/8.rom_ctrl_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_mem_rw_with_rand_reset.393871360 |
| Short name | T410 |
| Test name | |
| Test status | |
| Simulation time | 1645639801 ps |
| CPU time | 8.91 seconds |
| Started | May 12 01:05:03 PM PDT 24 |
| Finished | May 12 01:05:12 PM PDT 24 |
| Peak memory | 211924 kb |
| Host | smart-47a17780-a84a-4a9e-9987-d09f2106fd06 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=393871360 -assert nopostproc +UVM_TESTNAME= rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_csr_mem_rw_with_rand_reset.393871360 |
| Directory | /workspace/9.rom_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_rw.3841729 |
| Short name | T61 |
| Test name | |
| Test status | |
| Simulation time | 828774897 ps |
| CPU time | 4.19 seconds |
| Started | May 12 01:05:05 PM PDT 24 |
| Finished | May 12 01:05:09 PM PDT 24 |
| Peak memory | 210752 kb |
| Host | smart-866cc34d-581a-40f9-8d1a-d1b2fd1c0bed |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3841729 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_csr_rw.3841729 |
| Directory | /workspace/9.rom_ctrl_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/9.rom_ctrl_passthru_mem_tl_intg_err.2066983667 |
| Short name | T76 |
| Test name | |
| Test status | |
| Simulation time | 8480069271 ps |
| CPU time | 42.61 seconds |
| Started | May 12 01:05:01 PM PDT 24 |
| Finished | May 12 01:05:45 PM PDT 24 |
| Peak memory | 210784 kb |
| Host | smart-133b263b-890c-48e7-af8e-f34c17471c90 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2066983667 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_pa ssthru_mem_tl_intg_err.2066983667 |
| Directory | /workspace/9.rom_ctrl_passthru_mem_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/9.rom_ctrl_same_csr_outstanding.2271084181 |
| Short name | T403 |
| Test name | |
| Test status | |
| Simulation time | 1508103661 ps |
| CPU time | 7.09 seconds |
| Started | May 12 01:05:12 PM PDT 24 |
| Finished | May 12 01:05:21 PM PDT 24 |
| Peak memory | 210760 kb |
| Host | smart-1e40f0fe-7a2b-48b8-bb66-67ceee727ada |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2271084181 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_c trl_same_csr_outstanding.2271084181 |
| Directory | /workspace/9.rom_ctrl_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_errors.2465203356 |
| Short name | T443 |
| Test name | |
| Test status | |
| Simulation time | 3792139948 ps |
| CPU time | 14.01 seconds |
| Started | May 12 01:05:00 PM PDT 24 |
| Finished | May 12 01:05:15 PM PDT 24 |
| Peak memory | 219428 kb |
| Host | smart-7b35e2ce-c45c-4633-a131-2b6c319d7d03 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2465203356 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_tl_errors.2465203356 |
| Directory | /workspace/9.rom_ctrl_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_intg_err.1480582256 |
| Short name | T103 |
| Test name | |
| Test status | |
| Simulation time | 7630043352 ps |
| CPU time | 76.94 seconds |
| Started | May 12 01:05:04 PM PDT 24 |
| Finished | May 12 01:06:22 PM PDT 24 |
| Peak memory | 212072 kb |
| Host | smart-95b819de-be04-407f-bac7-d312d7617dcf |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1480582256 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_tl_in tg_err.1480582256 |
| Directory | /workspace/9.rom_ctrl_tl_intg_err/latest |
| Test location | /workspace/coverage/default/0.rom_ctrl_alert_test.1698610206 |
| Short name | T153 |
| Test name | |
| Test status | |
| Simulation time | 1421291146 ps |
| CPU time | 8.59 seconds |
| Started | May 12 01:05:16 PM PDT 24 |
| Finished | May 12 01:05:25 PM PDT 24 |
| Peak memory | 211560 kb |
| Host | smart-44d971cb-a8e7-4033-912f-c4d53d1ed789 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1698610206 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_alert_test.1698610206 |
| Directory | /workspace/0.rom_ctrl_alert_test/latest |
| Test location | /workspace/coverage/default/0.rom_ctrl_kmac_err_chk.695135727 |
| Short name | T210 |
| Test name | |
| Test status | |
| Simulation time | 3177045007 ps |
| CPU time | 28.32 seconds |
| Started | May 12 01:05:15 PM PDT 24 |
| Finished | May 12 01:05:44 PM PDT 24 |
| Peak memory | 212440 kb |
| Host | smart-58ef2c75-634e-467a-bcd8-6bf999806fbe |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=695135727 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_kmac_err_chk.695135727 |
| Directory | /workspace/0.rom_ctrl_kmac_err_chk/latest |
| Test location | /workspace/coverage/default/0.rom_ctrl_max_throughput_chk.4075256051 |
| Short name | T138 |
| Test name | |
| Test status | |
| Simulation time | 1449987893 ps |
| CPU time | 14.49 seconds |
| Started | May 12 01:05:16 PM PDT 24 |
| Finished | May 12 01:05:31 PM PDT 24 |
| Peak memory | 211504 kb |
| Host | smart-ca6f1eba-a73d-4e5a-8899-6e024f0eaca4 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=4075256051 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_max_throughput_chk.4075256051 |
| Directory | /workspace/0.rom_ctrl_max_throughput_chk/latest |
| Test location | /workspace/coverage/default/0.rom_ctrl_smoke.3683705782 |
| Short name | T328 |
| Test name | |
| Test status | |
| Simulation time | 2696353589 ps |
| CPU time | 21.76 seconds |
| Started | May 12 01:05:13 PM PDT 24 |
| Finished | May 12 01:05:35 PM PDT 24 |
| Peak memory | 219928 kb |
| Host | smart-c29d9e65-3b55-47b9-b5d4-2ac2a102625b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3683705782 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_smoke.3683705782 |
| Directory | /workspace/0.rom_ctrl_smoke/latest |
| Test location | /workspace/coverage/default/0.rom_ctrl_stress_all.1034907357 |
| Short name | T166 |
| Test name | |
| Test status | |
| Simulation time | 3182895436 ps |
| CPU time | 41.42 seconds |
| Started | May 12 01:05:18 PM PDT 24 |
| Finished | May 12 01:06:00 PM PDT 24 |
| Peak memory | 215980 kb |
| Host | smart-b92e5172-6476-4e5a-94f0-4c757da4706e |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1034907357 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm _name 0.rom_ctrl_stress_all.1034907357 |
| Directory | /workspace/0.rom_ctrl_stress_all/latest |
| Test location | /workspace/coverage/default/1.rom_ctrl_alert_test.1590736083 |
| Short name | T273 |
| Test name | |
| Test status | |
| Simulation time | 3529122092 ps |
| CPU time | 14.26 seconds |
| Started | May 12 01:05:16 PM PDT 24 |
| Finished | May 12 01:05:30 PM PDT 24 |
| Peak memory | 211828 kb |
| Host | smart-fea618fc-75a9-49d3-8b48-6edca7760c74 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1590736083 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_alert_test.1590736083 |
| Directory | /workspace/1.rom_ctrl_alert_test/latest |
| Test location | /workspace/coverage/default/1.rom_ctrl_corrupt_sig_fatal_chk.1781919088 |
| Short name | T34 |
| Test name | |
| Test status | |
| Simulation time | 16566894965 ps |
| CPU time | 110.06 seconds |
| Started | May 12 01:05:14 PM PDT 24 |
| Finished | May 12 01:07:05 PM PDT 24 |
| Peak memory | 234096 kb |
| Host | smart-b579d0a0-5a42-4c67-aac0-a922f8826654 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1781919088 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_c orrupt_sig_fatal_chk.1781919088 |
| Directory | /workspace/1.rom_ctrl_corrupt_sig_fatal_chk/latest |
| Test location | /workspace/coverage/default/1.rom_ctrl_max_throughput_chk.2972109359 |
| Short name | T312 |
| Test name | |
| Test status | |
| Simulation time | 13059629612 ps |
| CPU time | 14.64 seconds |
| Started | May 12 01:05:14 PM PDT 24 |
| Finished | May 12 01:05:29 PM PDT 24 |
| Peak memory | 211744 kb |
| Host | smart-d3451788-9446-4e4d-9229-7f2deab172f7 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2972109359 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_max_throughput_chk.2972109359 |
| Directory | /workspace/1.rom_ctrl_max_throughput_chk/latest |
| Test location | /workspace/coverage/default/1.rom_ctrl_sec_cm.117152503 |
| Short name | T35 |
| Test name | |
| Test status | |
| Simulation time | 1675219275 ps |
| CPU time | 108.24 seconds |
| Started | May 12 01:05:20 PM PDT 24 |
| Finished | May 12 01:07:09 PM PDT 24 |
| Peak memory | 237036 kb |
| Host | smart-c8c68b29-3232-4f0b-a9b4-23aa38d0603f |
| User | root |
| Command | /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=117152503 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_sec_cm.117152503 |
| Directory | /workspace/1.rom_ctrl_sec_cm/latest |
| Test location | /workspace/coverage/default/1.rom_ctrl_smoke.969387782 |
| Short name | T218 |
| Test name | |
| Test status | |
| Simulation time | 349040193 ps |
| CPU time | 9.97 seconds |
| Started | May 12 01:05:18 PM PDT 24 |
| Finished | May 12 01:05:28 PM PDT 24 |
| Peak memory | 213652 kb |
| Host | smart-f5a3208d-9de1-43fc-85b0-7e8dc98f3725 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=969387782 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_smoke.969387782 |
| Directory | /workspace/1.rom_ctrl_smoke/latest |
| Test location | /workspace/coverage/default/1.rom_ctrl_stress_all.1204667475 |
| Short name | T295 |
| Test name | |
| Test status | |
| Simulation time | 3721254248 ps |
| CPU time | 26.7 seconds |
| Started | May 12 01:05:16 PM PDT 24 |
| Finished | May 12 01:05:44 PM PDT 24 |
| Peak memory | 219828 kb |
| Host | smart-4dc67e61-3f7c-4125-bf74-08e7a45fdecf |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1204667475 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm _name 1.rom_ctrl_stress_all.1204667475 |
| Directory | /workspace/1.rom_ctrl_stress_all/latest |
| Test location | /workspace/coverage/default/10.rom_ctrl_alert_test.554130691 |
| Short name | T345 |
| Test name | |
| Test status | |
| Simulation time | 995833798 ps |
| CPU time | 7.56 seconds |
| Started | May 12 01:05:33 PM PDT 24 |
| Finished | May 12 01:05:41 PM PDT 24 |
| Peak memory | 211596 kb |
| Host | smart-3f433046-8374-4a54-bf46-8b86e1dcd8f0 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=554130691 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_alert_test.554130691 |
| Directory | /workspace/10.rom_ctrl_alert_test/latest |
| Test location | /workspace/coverage/default/10.rom_ctrl_corrupt_sig_fatal_chk.298629559 |
| Short name | T176 |
| Test name | |
| Test status | |
| Simulation time | 98285081741 ps |
| CPU time | 374.22 seconds |
| Started | May 12 01:05:33 PM PDT 24 |
| Finished | May 12 01:11:48 PM PDT 24 |
| Peak memory | 237272 kb |
| Host | smart-19e27e42-0e3d-47f6-ac9e-75184fadd230 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=298629559 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt _sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_c orrupt_sig_fatal_chk.298629559 |
| Directory | /workspace/10.rom_ctrl_corrupt_sig_fatal_chk/latest |
| Test location | /workspace/coverage/default/10.rom_ctrl_kmac_err_chk.2981449496 |
| Short name | T338 |
| Test name | |
| Test status | |
| Simulation time | 2204667589 ps |
| CPU time | 13.44 seconds |
| Started | May 12 01:05:33 PM PDT 24 |
| Finished | May 12 01:05:46 PM PDT 24 |
| Peak memory | 212496 kb |
| Host | smart-2b553bd3-9a70-4ec1-89c5-67259c53a6f8 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2981449496 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_kmac_err_chk.2981449496 |
| Directory | /workspace/10.rom_ctrl_kmac_err_chk/latest |
| Test location | /workspace/coverage/default/10.rom_ctrl_max_throughput_chk.4233399461 |
| Short name | T141 |
| Test name | |
| Test status | |
| Simulation time | 1100766338 ps |
| CPU time | 11.79 seconds |
| Started | May 12 01:05:29 PM PDT 24 |
| Finished | May 12 01:05:41 PM PDT 24 |
| Peak memory | 211488 kb |
| Host | smart-58bf402e-b4bb-40c6-b969-45a5b68343a5 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=4233399461 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_max_throughput_chk.4233399461 |
| Directory | /workspace/10.rom_ctrl_max_throughput_chk/latest |
| Test location | /workspace/coverage/default/10.rom_ctrl_smoke.1554943929 |
| Short name | T341 |
| Test name | |
| Test status | |
| Simulation time | 4792893809 ps |
| CPU time | 26.24 seconds |
| Started | May 12 01:05:29 PM PDT 24 |
| Finished | May 12 01:05:55 PM PDT 24 |
| Peak memory | 219896 kb |
| Host | smart-4114219c-27fd-4aa2-bf86-501e5909df23 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1554943929 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_smoke.1554943929 |
| Directory | /workspace/10.rom_ctrl_smoke/latest |
| Test location | /workspace/coverage/default/10.rom_ctrl_stress_all.1135236860 |
| Short name | T154 |
| Test name | |
| Test status | |
| Simulation time | 3453283950 ps |
| CPU time | 17.09 seconds |
| Started | May 12 01:05:30 PM PDT 24 |
| Finished | May 12 01:05:48 PM PDT 24 |
| Peak memory | 219772 kb |
| Host | smart-952102d8-2a98-4ee5-ab09-a238e5f2856a |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1135236860 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm _name 10.rom_ctrl_stress_all.1135236860 |
| Directory | /workspace/10.rom_ctrl_stress_all/latest |
| Test location | /workspace/coverage/default/11.rom_ctrl_alert_test.1307784539 |
| Short name | T4 |
| Test name | |
| Test status | |
| Simulation time | 6713518148 ps |
| CPU time | 13.43 seconds |
| Started | May 12 01:05:37 PM PDT 24 |
| Finished | May 12 01:05:51 PM PDT 24 |
| Peak memory | 211668 kb |
| Host | smart-6b7e7a8d-8f16-4666-bf05-e296c86d7fc9 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1307784539 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_alert_test.1307784539 |
| Directory | /workspace/11.rom_ctrl_alert_test/latest |
| Test location | /workspace/coverage/default/11.rom_ctrl_corrupt_sig_fatal_chk.3842708697 |
| Short name | T179 |
| Test name | |
| Test status | |
| Simulation time | 60791520902 ps |
| CPU time | 313.39 seconds |
| Started | May 12 01:05:34 PM PDT 24 |
| Finished | May 12 01:10:48 PM PDT 24 |
| Peak memory | 235188 kb |
| Host | smart-ee6c1986-c78a-4235-bc86-df4c1803a424 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3842708697 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_ corrupt_sig_fatal_chk.3842708697 |
| Directory | /workspace/11.rom_ctrl_corrupt_sig_fatal_chk/latest |
| Test location | /workspace/coverage/default/11.rom_ctrl_kmac_err_chk.1240554729 |
| Short name | T185 |
| Test name | |
| Test status | |
| Simulation time | 5746662202 ps |
| CPU time | 27.22 seconds |
| Started | May 12 01:05:33 PM PDT 24 |
| Finished | May 12 01:06:00 PM PDT 24 |
| Peak memory | 212600 kb |
| Host | smart-567fc276-3176-49ed-b21b-e96103afa100 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1240554729 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_kmac_err_chk.1240554729 |
| Directory | /workspace/11.rom_ctrl_kmac_err_chk/latest |
| Test location | /workspace/coverage/default/11.rom_ctrl_max_throughput_chk.3342729101 |
| Short name | T259 |
| Test name | |
| Test status | |
| Simulation time | 1972855833 ps |
| CPU time | 17.53 seconds |
| Started | May 12 01:05:33 PM PDT 24 |
| Finished | May 12 01:05:51 PM PDT 24 |
| Peak memory | 211532 kb |
| Host | smart-70345380-061a-4bb6-8a41-9384d802b510 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3342729101 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_max_throughput_chk.3342729101 |
| Directory | /workspace/11.rom_ctrl_max_throughput_chk/latest |
| Test location | /workspace/coverage/default/11.rom_ctrl_smoke.1509377876 |
| Short name | T344 |
| Test name | |
| Test status | |
| Simulation time | 3810121359 ps |
| CPU time | 21.65 seconds |
| Started | May 12 01:05:35 PM PDT 24 |
| Finished | May 12 01:05:57 PM PDT 24 |
| Peak memory | 214208 kb |
| Host | smart-2c0f87db-faa0-43d3-b650-d2e51daec026 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1509377876 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_smoke.1509377876 |
| Directory | /workspace/11.rom_ctrl_smoke/latest |
| Test location | /workspace/coverage/default/11.rom_ctrl_stress_all.987951616 |
| Short name | T171 |
| Test name | |
| Test status | |
| Simulation time | 441372991 ps |
| CPU time | 12.85 seconds |
| Started | May 12 01:05:34 PM PDT 24 |
| Finished | May 12 01:05:47 PM PDT 24 |
| Peak memory | 214056 kb |
| Host | smart-2564e84a-3687-4303-bb09-76f8c1d21448 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=987951616 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test + UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 11.rom_ctrl_stress_all.987951616 |
| Directory | /workspace/11.rom_ctrl_stress_all/latest |
| Test location | /workspace/coverage/default/12.rom_ctrl_alert_test.3819158318 |
| Short name | T169 |
| Test name | |
| Test status | |
| Simulation time | 10845299070 ps |
| CPU time | 10.5 seconds |
| Started | May 12 01:05:39 PM PDT 24 |
| Finished | May 12 01:05:50 PM PDT 24 |
| Peak memory | 211680 kb |
| Host | smart-3afaf882-4fcd-4f8e-899d-5d1542f9fe10 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3819158318 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_alert_test.3819158318 |
| Directory | /workspace/12.rom_ctrl_alert_test/latest |
| Test location | /workspace/coverage/default/12.rom_ctrl_corrupt_sig_fatal_chk.1223730225 |
| Short name | T116 |
| Test name | |
| Test status | |
| Simulation time | 29431584838 ps |
| CPU time | 147.63 seconds |
| Started | May 12 01:05:34 PM PDT 24 |
| Finished | May 12 01:08:02 PM PDT 24 |
| Peak memory | 237080 kb |
| Host | smart-249fcabb-e8b2-4cc3-ade6-61ed77714b34 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1223730225 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_ corrupt_sig_fatal_chk.1223730225 |
| Directory | /workspace/12.rom_ctrl_corrupt_sig_fatal_chk/latest |
| Test location | /workspace/coverage/default/12.rom_ctrl_kmac_err_chk.2463091485 |
| Short name | T326 |
| Test name | |
| Test status | |
| Simulation time | 18846888446 ps |
| CPU time | 28.8 seconds |
| Started | May 12 01:05:34 PM PDT 24 |
| Finished | May 12 01:06:03 PM PDT 24 |
| Peak memory | 212552 kb |
| Host | smart-93d2df56-ef7b-4380-9220-45e3c5a4dc9b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2463091485 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_kmac_err_chk.2463091485 |
| Directory | /workspace/12.rom_ctrl_kmac_err_chk/latest |
| Test location | /workspace/coverage/default/12.rom_ctrl_max_throughput_chk.3759996541 |
| Short name | T267 |
| Test name | |
| Test status | |
| Simulation time | 95118102 ps |
| CPU time | 5.61 seconds |
| Started | May 12 01:05:34 PM PDT 24 |
| Finished | May 12 01:05:40 PM PDT 24 |
| Peak memory | 211476 kb |
| Host | smart-2f21987f-780e-49e7-a080-d898ece97eb3 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3759996541 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_max_throughput_chk.3759996541 |
| Directory | /workspace/12.rom_ctrl_max_throughput_chk/latest |
| Test location | /workspace/coverage/default/12.rom_ctrl_smoke.641621516 |
| Short name | T8 |
| Test name | |
| Test status | |
| Simulation time | 1882205221 ps |
| CPU time | 11.45 seconds |
| Started | May 12 01:05:36 PM PDT 24 |
| Finished | May 12 01:05:48 PM PDT 24 |
| Peak memory | 213840 kb |
| Host | smart-8ccdec21-490d-403e-ac74-92e14f7d22e3 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=641621516 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_smoke.641621516 |
| Directory | /workspace/12.rom_ctrl_smoke/latest |
| Test location | /workspace/coverage/default/12.rom_ctrl_stress_all.4268950621 |
| Short name | T350 |
| Test name | |
| Test status | |
| Simulation time | 3099871738 ps |
| CPU time | 28.7 seconds |
| Started | May 12 01:05:33 PM PDT 24 |
| Finished | May 12 01:06:02 PM PDT 24 |
| Peak memory | 219936 kb |
| Host | smart-a6f00380-ac71-4ce8-9a02-ce9422344627 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4268950621 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm _name 12.rom_ctrl_stress_all.4268950621 |
| Directory | /workspace/12.rom_ctrl_stress_all/latest |
| Test location | /workspace/coverage/default/13.rom_ctrl_alert_test.975104079 |
| Short name | T285 |
| Test name | |
| Test status | |
| Simulation time | 7661388393 ps |
| CPU time | 15.44 seconds |
| Started | May 12 01:05:40 PM PDT 24 |
| Finished | May 12 01:05:57 PM PDT 24 |
| Peak memory | 211812 kb |
| Host | smart-1c348807-10d6-4c33-99aa-b9dd87490a32 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=975104079 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_alert_test.975104079 |
| Directory | /workspace/13.rom_ctrl_alert_test/latest |
| Test location | /workspace/coverage/default/13.rom_ctrl_corrupt_sig_fatal_chk.401942010 |
| Short name | T200 |
| Test name | |
| Test status | |
| Simulation time | 16605716695 ps |
| CPU time | 222.75 seconds |
| Started | May 12 01:05:38 PM PDT 24 |
| Finished | May 12 01:09:22 PM PDT 24 |
| Peak memory | 241316 kb |
| Host | smart-c5c4076b-066f-42a3-9745-44a43b285083 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=401942010 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt _sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_c orrupt_sig_fatal_chk.401942010 |
| Directory | /workspace/13.rom_ctrl_corrupt_sig_fatal_chk/latest |
| Test location | /workspace/coverage/default/13.rom_ctrl_kmac_err_chk.3253988167 |
| Short name | T302 |
| Test name | |
| Test status | |
| Simulation time | 57263802372 ps |
| CPU time | 28.02 seconds |
| Started | May 12 01:05:38 PM PDT 24 |
| Finished | May 12 01:06:07 PM PDT 24 |
| Peak memory | 212780 kb |
| Host | smart-4ab3ad1d-dc1e-43ff-9ac1-e4be9b86e753 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3253988167 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_kmac_err_chk.3253988167 |
| Directory | /workspace/13.rom_ctrl_kmac_err_chk/latest |
| Test location | /workspace/coverage/default/13.rom_ctrl_max_throughput_chk.647802551 |
| Short name | T254 |
| Test name | |
| Test status | |
| Simulation time | 196957620 ps |
| CPU time | 5.84 seconds |
| Started | May 12 01:05:38 PM PDT 24 |
| Finished | May 12 01:05:44 PM PDT 24 |
| Peak memory | 211516 kb |
| Host | smart-c4b6751a-2bad-423f-8898-6969fc9fa339 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=647802551 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_max_throughput_chk.647802551 |
| Directory | /workspace/13.rom_ctrl_max_throughput_chk/latest |
| Test location | /workspace/coverage/default/13.rom_ctrl_smoke.3572912345 |
| Short name | T308 |
| Test name | |
| Test status | |
| Simulation time | 708602062 ps |
| CPU time | 9.91 seconds |
| Started | May 12 01:05:39 PM PDT 24 |
| Finished | May 12 01:05:49 PM PDT 24 |
| Peak memory | 219828 kb |
| Host | smart-42bbc7f1-c791-4065-a3ca-1b1b267924be |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3572912345 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_smoke.3572912345 |
| Directory | /workspace/13.rom_ctrl_smoke/latest |
| Test location | /workspace/coverage/default/13.rom_ctrl_stress_all.184204816 |
| Short name | T172 |
| Test name | |
| Test status | |
| Simulation time | 12096375491 ps |
| CPU time | 54.41 seconds |
| Started | May 12 01:05:39 PM PDT 24 |
| Finished | May 12 01:06:34 PM PDT 24 |
| Peak memory | 219864 kb |
| Host | smart-f841ec31-d973-49f6-a55f-9496d693450e |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=184204816 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test + UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 13.rom_ctrl_stress_all.184204816 |
| Directory | /workspace/13.rom_ctrl_stress_all/latest |
| Test location | /workspace/coverage/default/14.rom_ctrl_alert_test.2353525809 |
| Short name | T321 |
| Test name | |
| Test status | |
| Simulation time | 2144445742 ps |
| CPU time | 16.4 seconds |
| Started | May 12 01:05:38 PM PDT 24 |
| Finished | May 12 01:05:55 PM PDT 24 |
| Peak memory | 211612 kb |
| Host | smart-81dc9a3d-a72f-46a6-a3f4-b5c3e9c718cc |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2353525809 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_alert_test.2353525809 |
| Directory | /workspace/14.rom_ctrl_alert_test/latest |
| Test location | /workspace/coverage/default/14.rom_ctrl_corrupt_sig_fatal_chk.993571719 |
| Short name | T220 |
| Test name | |
| Test status | |
| Simulation time | 5859425386 ps |
| CPU time | 141.43 seconds |
| Started | May 12 01:05:39 PM PDT 24 |
| Finished | May 12 01:08:01 PM PDT 24 |
| Peak memory | 213516 kb |
| Host | smart-5e05f0ee-ad6e-4c89-be07-8554cbc5ca19 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=993571719 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt _sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_c orrupt_sig_fatal_chk.993571719 |
| Directory | /workspace/14.rom_ctrl_corrupt_sig_fatal_chk/latest |
| Test location | /workspace/coverage/default/14.rom_ctrl_kmac_err_chk.2269695713 |
| Short name | T257 |
| Test name | |
| Test status | |
| Simulation time | 1594494221 ps |
| CPU time | 12.11 seconds |
| Started | May 12 01:05:38 PM PDT 24 |
| Finished | May 12 01:05:51 PM PDT 24 |
| Peak memory | 212320 kb |
| Host | smart-5a0a2edd-237b-4673-8704-cd70970ac306 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2269695713 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_kmac_err_chk.2269695713 |
| Directory | /workspace/14.rom_ctrl_kmac_err_chk/latest |
| Test location | /workspace/coverage/default/14.rom_ctrl_max_throughput_chk.1002595600 |
| Short name | T232 |
| Test name | |
| Test status | |
| Simulation time | 596314197 ps |
| CPU time | 5.38 seconds |
| Started | May 12 01:05:44 PM PDT 24 |
| Finished | May 12 01:05:50 PM PDT 24 |
| Peak memory | 211548 kb |
| Host | smart-070d661d-737d-42be-89d7-53a84313c09c |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1002595600 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_max_throughput_chk.1002595600 |
| Directory | /workspace/14.rom_ctrl_max_throughput_chk/latest |
| Test location | /workspace/coverage/default/14.rom_ctrl_smoke.984239361 |
| Short name | T40 |
| Test name | |
| Test status | |
| Simulation time | 2669010229 ps |
| CPU time | 24.88 seconds |
| Started | May 12 01:05:39 PM PDT 24 |
| Finished | May 12 01:06:04 PM PDT 24 |
| Peak memory | 213700 kb |
| Host | smart-c19b5866-ee4a-4cf6-99b0-349982631975 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=984239361 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_smoke.984239361 |
| Directory | /workspace/14.rom_ctrl_smoke/latest |
| Test location | /workspace/coverage/default/14.rom_ctrl_stress_all.3602435653 |
| Short name | T262 |
| Test name | |
| Test status | |
| Simulation time | 2846932105 ps |
| CPU time | 22.9 seconds |
| Started | May 12 01:05:39 PM PDT 24 |
| Finished | May 12 01:06:02 PM PDT 24 |
| Peak memory | 211704 kb |
| Host | smart-ce7df0f2-902d-487f-a406-356d9cb03b14 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3602435653 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm _name 14.rom_ctrl_stress_all.3602435653 |
| Directory | /workspace/14.rom_ctrl_stress_all/latest |
| Test location | /workspace/coverage/default/15.rom_ctrl_alert_test.3693667842 |
| Short name | T140 |
| Test name | |
| Test status | |
| Simulation time | 85626045 ps |
| CPU time | 4.41 seconds |
| Started | May 12 01:05:48 PM PDT 24 |
| Finished | May 12 01:05:53 PM PDT 24 |
| Peak memory | 211680 kb |
| Host | smart-737d57e6-5132-4766-97fc-4d75af863cc4 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3693667842 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_alert_test.3693667842 |
| Directory | /workspace/15.rom_ctrl_alert_test/latest |
| Test location | /workspace/coverage/default/15.rom_ctrl_corrupt_sig_fatal_chk.2061698157 |
| Short name | T316 |
| Test name | |
| Test status | |
| Simulation time | 2092794481 ps |
| CPU time | 138.34 seconds |
| Started | May 12 01:05:40 PM PDT 24 |
| Finished | May 12 01:07:59 PM PDT 24 |
| Peak memory | 234320 kb |
| Host | smart-b9659b31-9822-4448-84bc-a44239e05552 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2061698157 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_ corrupt_sig_fatal_chk.2061698157 |
| Directory | /workspace/15.rom_ctrl_corrupt_sig_fatal_chk/latest |
| Test location | /workspace/coverage/default/15.rom_ctrl_kmac_err_chk.2588745283 |
| Short name | T270 |
| Test name | |
| Test status | |
| Simulation time | 4822622337 ps |
| CPU time | 23.74 seconds |
| Started | May 12 01:05:40 PM PDT 24 |
| Finished | May 12 01:06:05 PM PDT 24 |
| Peak memory | 211848 kb |
| Host | smart-bed3c7c9-38fe-46bb-afd9-39f43ef76dd2 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2588745283 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_kmac_err_chk.2588745283 |
| Directory | /workspace/15.rom_ctrl_kmac_err_chk/latest |
| Test location | /workspace/coverage/default/15.rom_ctrl_max_throughput_chk.2376800944 |
| Short name | T115 |
| Test name | |
| Test status | |
| Simulation time | 271451475 ps |
| CPU time | 6.65 seconds |
| Started | May 12 01:05:40 PM PDT 24 |
| Finished | May 12 01:05:47 PM PDT 24 |
| Peak memory | 211532 kb |
| Host | smart-0cb5e7cc-3e18-4233-9303-d5266009baae |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2376800944 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_max_throughput_chk.2376800944 |
| Directory | /workspace/15.rom_ctrl_max_throughput_chk/latest |
| Test location | /workspace/coverage/default/15.rom_ctrl_smoke.3070194518 |
| Short name | T149 |
| Test name | |
| Test status | |
| Simulation time | 1041483119 ps |
| CPU time | 19.47 seconds |
| Started | May 12 01:05:40 PM PDT 24 |
| Finished | May 12 01:06:00 PM PDT 24 |
| Peak memory | 213344 kb |
| Host | smart-6f337851-c3cd-4d8f-8589-d8427384eb86 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3070194518 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_smoke.3070194518 |
| Directory | /workspace/15.rom_ctrl_smoke/latest |
| Test location | /workspace/coverage/default/15.rom_ctrl_stress_all.2454365502 |
| Short name | T219 |
| Test name | |
| Test status | |
| Simulation time | 380316490 ps |
| CPU time | 22.08 seconds |
| Started | May 12 01:05:41 PM PDT 24 |
| Finished | May 12 01:06:03 PM PDT 24 |
| Peak memory | 219688 kb |
| Host | smart-b4d820fe-8e34-4b1b-94bd-f47f9d298f36 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2454365502 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm _name 15.rom_ctrl_stress_all.2454365502 |
| Directory | /workspace/15.rom_ctrl_stress_all/latest |
| Test location | /workspace/coverage/default/16.rom_ctrl_alert_test.1291176411 |
| Short name | T355 |
| Test name | |
| Test status | |
| Simulation time | 382906034 ps |
| CPU time | 7.24 seconds |
| Started | May 12 01:05:44 PM PDT 24 |
| Finished | May 12 01:05:52 PM PDT 24 |
| Peak memory | 211560 kb |
| Host | smart-d395f6d4-d2aa-412d-8a32-87bd4207940b |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1291176411 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_alert_test.1291176411 |
| Directory | /workspace/16.rom_ctrl_alert_test/latest |
| Test location | /workspace/coverage/default/16.rom_ctrl_corrupt_sig_fatal_chk.2658081755 |
| Short name | T20 |
| Test name | |
| Test status | |
| Simulation time | 117109946705 ps |
| CPU time | 327.85 seconds |
| Started | May 12 01:05:48 PM PDT 24 |
| Finished | May 12 01:11:17 PM PDT 24 |
| Peak memory | 237320 kb |
| Host | smart-1ac0c101-a7c1-4c45-8980-d3529c6e1f62 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2658081755 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_ corrupt_sig_fatal_chk.2658081755 |
| Directory | /workspace/16.rom_ctrl_corrupt_sig_fatal_chk/latest |
| Test location | /workspace/coverage/default/16.rom_ctrl_kmac_err_chk.251574126 |
| Short name | T239 |
| Test name | |
| Test status | |
| Simulation time | 3299826613 ps |
| CPU time | 28.45 seconds |
| Started | May 12 01:05:46 PM PDT 24 |
| Finished | May 12 01:06:15 PM PDT 24 |
| Peak memory | 212768 kb |
| Host | smart-13d3d354-4155-4a2c-88e0-92918a0d0c3d |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=251574126 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_kmac_err_chk.251574126 |
| Directory | /workspace/16.rom_ctrl_kmac_err_chk/latest |
| Test location | /workspace/coverage/default/16.rom_ctrl_max_throughput_chk.2749149603 |
| Short name | T92 |
| Test name | |
| Test status | |
| Simulation time | 775134458 ps |
| CPU time | 5.56 seconds |
| Started | May 12 01:05:44 PM PDT 24 |
| Finished | May 12 01:05:50 PM PDT 24 |
| Peak memory | 211480 kb |
| Host | smart-d30c6d90-2a5b-46d1-ab18-aee444b6a6b4 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2749149603 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_max_throughput_chk.2749149603 |
| Directory | /workspace/16.rom_ctrl_max_throughput_chk/latest |
| Test location | /workspace/coverage/default/16.rom_ctrl_smoke.3096833140 |
| Short name | T236 |
| Test name | |
| Test status | |
| Simulation time | 2739098246 ps |
| CPU time | 29.27 seconds |
| Started | May 12 01:05:42 PM PDT 24 |
| Finished | May 12 01:06:12 PM PDT 24 |
| Peak memory | 213084 kb |
| Host | smart-64f16be8-0b9d-4978-a929-77bd92e1a0a3 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3096833140 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_smoke.3096833140 |
| Directory | /workspace/16.rom_ctrl_smoke/latest |
| Test location | /workspace/coverage/default/16.rom_ctrl_stress_all.2921888766 |
| Short name | T130 |
| Test name | |
| Test status | |
| Simulation time | 46546859097 ps |
| CPU time | 64.58 seconds |
| Started | May 12 01:05:45 PM PDT 24 |
| Finished | May 12 01:06:50 PM PDT 24 |
| Peak memory | 217968 kb |
| Host | smart-456ffaf3-e45a-43a1-8541-73ee6f824021 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2921888766 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm _name 16.rom_ctrl_stress_all.2921888766 |
| Directory | /workspace/16.rom_ctrl_stress_all/latest |
| Test location | /workspace/coverage/default/17.rom_ctrl_alert_test.3001992560 |
| Short name | T128 |
| Test name | |
| Test status | |
| Simulation time | 5243959022 ps |
| CPU time | 12.11 seconds |
| Started | May 12 01:05:46 PM PDT 24 |
| Finished | May 12 01:05:58 PM PDT 24 |
| Peak memory | 211684 kb |
| Host | smart-93b8f837-b351-4a79-a820-b3d12f6da1f0 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3001992560 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_alert_test.3001992560 |
| Directory | /workspace/17.rom_ctrl_alert_test/latest |
| Test location | /workspace/coverage/default/17.rom_ctrl_corrupt_sig_fatal_chk.3958663710 |
| Short name | T160 |
| Test name | |
| Test status | |
| Simulation time | 2402406349 ps |
| CPU time | 137.69 seconds |
| Started | May 12 01:05:44 PM PDT 24 |
| Finished | May 12 01:08:02 PM PDT 24 |
| Peak memory | 228964 kb |
| Host | smart-a7006ea1-fec2-4704-bb6c-dedcd264f540 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3958663710 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_ corrupt_sig_fatal_chk.3958663710 |
| Directory | /workspace/17.rom_ctrl_corrupt_sig_fatal_chk/latest |
| Test location | /workspace/coverage/default/17.rom_ctrl_kmac_err_chk.977618791 |
| Short name | T306 |
| Test name | |
| Test status | |
| Simulation time | 1847536904 ps |
| CPU time | 9.69 seconds |
| Started | May 12 01:05:45 PM PDT 24 |
| Finished | May 12 01:05:55 PM PDT 24 |
| Peak memory | 212108 kb |
| Host | smart-eb315656-ade5-4295-aafc-4f0148917bb5 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=977618791 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_kmac_err_chk.977618791 |
| Directory | /workspace/17.rom_ctrl_kmac_err_chk/latest |
| Test location | /workspace/coverage/default/17.rom_ctrl_max_throughput_chk.1311458820 |
| Short name | T119 |
| Test name | |
| Test status | |
| Simulation time | 4118075224 ps |
| CPU time | 11.64 seconds |
| Started | May 12 01:05:47 PM PDT 24 |
| Finished | May 12 01:05:59 PM PDT 24 |
| Peak memory | 211600 kb |
| Host | smart-8efba312-3d82-45f1-baaf-34f92407dd72 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1311458820 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_max_throughput_chk.1311458820 |
| Directory | /workspace/17.rom_ctrl_max_throughput_chk/latest |
| Test location | /workspace/coverage/default/17.rom_ctrl_smoke.1823040951 |
| Short name | T351 |
| Test name | |
| Test status | |
| Simulation time | 1083922289 ps |
| CPU time | 18.25 seconds |
| Started | May 12 01:05:43 PM PDT 24 |
| Finished | May 12 01:06:02 PM PDT 24 |
| Peak memory | 214348 kb |
| Host | smart-51a771a7-a534-469c-9c07-480d6464f119 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1823040951 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_smoke.1823040951 |
| Directory | /workspace/17.rom_ctrl_smoke/latest |
| Test location | /workspace/coverage/default/17.rom_ctrl_stress_all.3553581787 |
| Short name | T327 |
| Test name | |
| Test status | |
| Simulation time | 3778185418 ps |
| CPU time | 41.99 seconds |
| Started | May 12 01:05:45 PM PDT 24 |
| Finished | May 12 01:06:28 PM PDT 24 |
| Peak memory | 216304 kb |
| Host | smart-02194439-a3d5-450a-be45-6976f35e57e2 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3553581787 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm _name 17.rom_ctrl_stress_all.3553581787 |
| Directory | /workspace/17.rom_ctrl_stress_all/latest |
| Test location | /workspace/coverage/default/18.rom_ctrl_alert_test.2344655490 |
| Short name | T294 |
| Test name | |
| Test status | |
| Simulation time | 6721659555 ps |
| CPU time | 13.34 seconds |
| Started | May 12 01:05:45 PM PDT 24 |
| Finished | May 12 01:05:59 PM PDT 24 |
| Peak memory | 211800 kb |
| Host | smart-ceccf785-f3c1-4601-a1b8-174a2e59aaa1 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2344655490 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_alert_test.2344655490 |
| Directory | /workspace/18.rom_ctrl_alert_test/latest |
| Test location | /workspace/coverage/default/18.rom_ctrl_corrupt_sig_fatal_chk.2453603629 |
| Short name | T33 |
| Test name | |
| Test status | |
| Simulation time | 19034310272 ps |
| CPU time | 259.1 seconds |
| Started | May 12 01:05:44 PM PDT 24 |
| Finished | May 12 01:10:04 PM PDT 24 |
| Peak memory | 213024 kb |
| Host | smart-2207b903-b4ed-4a4a-863a-f8ce159ab37d |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2453603629 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_ corrupt_sig_fatal_chk.2453603629 |
| Directory | /workspace/18.rom_ctrl_corrupt_sig_fatal_chk/latest |
| Test location | /workspace/coverage/default/18.rom_ctrl_max_throughput_chk.3394405986 |
| Short name | T275 |
| Test name | |
| Test status | |
| Simulation time | 1258302952 ps |
| CPU time | 10.61 seconds |
| Started | May 12 01:05:46 PM PDT 24 |
| Finished | May 12 01:05:57 PM PDT 24 |
| Peak memory | 211596 kb |
| Host | smart-fca3ac7d-6aa6-4fb1-9b70-9178c6419921 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3394405986 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_max_throughput_chk.3394405986 |
| Directory | /workspace/18.rom_ctrl_max_throughput_chk/latest |
| Test location | /workspace/coverage/default/18.rom_ctrl_smoke.968420741 |
| Short name | T357 |
| Test name | |
| Test status | |
| Simulation time | 12997409210 ps |
| CPU time | 30.27 seconds |
| Started | May 12 01:05:47 PM PDT 24 |
| Finished | May 12 01:06:17 PM PDT 24 |
| Peak memory | 219912 kb |
| Host | smart-28b9250e-d95d-47f5-88d4-efe98d3e0153 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=968420741 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_smoke.968420741 |
| Directory | /workspace/18.rom_ctrl_smoke/latest |
| Test location | /workspace/coverage/default/18.rom_ctrl_stress_all.3019416005 |
| Short name | T156 |
| Test name | |
| Test status | |
| Simulation time | 21107013362 ps |
| CPU time | 112.08 seconds |
| Started | May 12 01:05:48 PM PDT 24 |
| Finished | May 12 01:07:41 PM PDT 24 |
| Peak memory | 219928 kb |
| Host | smart-5fada46f-c654-4798-8b7c-ae4405859dbb |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3019416005 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm _name 18.rom_ctrl_stress_all.3019416005 |
| Directory | /workspace/18.rom_ctrl_stress_all/latest |
| Test location | /workspace/coverage/default/19.rom_ctrl_corrupt_sig_fatal_chk.1695479103 |
| Short name | T354 |
| Test name | |
| Test status | |
| Simulation time | 6935687491 ps |
| CPU time | 100.06 seconds |
| Started | May 12 01:05:46 PM PDT 24 |
| Finished | May 12 01:07:26 PM PDT 24 |
| Peak memory | 228960 kb |
| Host | smart-33a2cd43-a5ed-43ec-aaad-046deb1ab585 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1695479103 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_ corrupt_sig_fatal_chk.1695479103 |
| Directory | /workspace/19.rom_ctrl_corrupt_sig_fatal_chk/latest |
| Test location | /workspace/coverage/default/19.rom_ctrl_kmac_err_chk.1666257818 |
| Short name | T274 |
| Test name | |
| Test status | |
| Simulation time | 1276656319 ps |
| CPU time | 9.61 seconds |
| Started | May 12 01:05:45 PM PDT 24 |
| Finished | May 12 01:05:55 PM PDT 24 |
| Peak memory | 212320 kb |
| Host | smart-0242d6f6-26ae-4272-ac36-6515be4b4508 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1666257818 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_kmac_err_chk.1666257818 |
| Directory | /workspace/19.rom_ctrl_kmac_err_chk/latest |
| Test location | /workspace/coverage/default/19.rom_ctrl_max_throughput_chk.1235299292 |
| Short name | T337 |
| Test name | |
| Test status | |
| Simulation time | 11869189562 ps |
| CPU time | 10.76 seconds |
| Started | May 12 01:05:48 PM PDT 24 |
| Finished | May 12 01:06:00 PM PDT 24 |
| Peak memory | 211652 kb |
| Host | smart-6a57ff15-0eff-4af7-87b7-bb3a7e10fc79 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1235299292 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_max_throughput_chk.1235299292 |
| Directory | /workspace/19.rom_ctrl_max_throughput_chk/latest |
| Test location | /workspace/coverage/default/19.rom_ctrl_smoke.52820248 |
| Short name | T228 |
| Test name | |
| Test status | |
| Simulation time | 2392099844 ps |
| CPU time | 24.65 seconds |
| Started | May 12 01:05:45 PM PDT 24 |
| Finished | May 12 01:06:10 PM PDT 24 |
| Peak memory | 213332 kb |
| Host | smart-3d478b2c-4e5a-4657-84a4-74e61fbd3657 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=52820248 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_smoke.52820248 |
| Directory | /workspace/19.rom_ctrl_smoke/latest |
| Test location | /workspace/coverage/default/19.rom_ctrl_stress_all.3949305699 |
| Short name | T180 |
| Test name | |
| Test status | |
| Simulation time | 288817026 ps |
| CPU time | 16.29 seconds |
| Started | May 12 01:05:45 PM PDT 24 |
| Finished | May 12 01:06:02 PM PDT 24 |
| Peak memory | 213952 kb |
| Host | smart-8dcb2dd2-b422-4f97-b07b-dee3fa629a67 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3949305699 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm _name 19.rom_ctrl_stress_all.3949305699 |
| Directory | /workspace/19.rom_ctrl_stress_all/latest |
| Test location | /workspace/coverage/default/2.rom_ctrl_alert_test.2037581952 |
| Short name | T260 |
| Test name | |
| Test status | |
| Simulation time | 4772671652 ps |
| CPU time | 16.98 seconds |
| Started | May 12 01:05:23 PM PDT 24 |
| Finished | May 12 01:05:40 PM PDT 24 |
| Peak memory | 211776 kb |
| Host | smart-2a23627f-c7f8-4ca8-a4e3-3838656a4bcd |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2037581952 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_alert_test.2037581952 |
| Directory | /workspace/2.rom_ctrl_alert_test/latest |
| Test location | /workspace/coverage/default/2.rom_ctrl_corrupt_sig_fatal_chk.3236669890 |
| Short name | T336 |
| Test name | |
| Test status | |
| Simulation time | 125527622240 ps |
| CPU time | 189.12 seconds |
| Started | May 12 01:05:18 PM PDT 24 |
| Finished | May 12 01:08:28 PM PDT 24 |
| Peak memory | 236196 kb |
| Host | smart-a8db1839-1eab-403b-8f38-b80e2342307f |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3236669890 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_c orrupt_sig_fatal_chk.3236669890 |
| Directory | /workspace/2.rom_ctrl_corrupt_sig_fatal_chk/latest |
| Test location | /workspace/coverage/default/2.rom_ctrl_kmac_err_chk.710370836 |
| Short name | T205 |
| Test name | |
| Test status | |
| Simulation time | 11554379908 ps |
| CPU time | 25.52 seconds |
| Started | May 12 01:05:14 PM PDT 24 |
| Finished | May 12 01:05:40 PM PDT 24 |
| Peak memory | 211792 kb |
| Host | smart-770f9337-5f14-4dfd-aa89-4bdc14b6216b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=710370836 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_kmac_err_chk.710370836 |
| Directory | /workspace/2.rom_ctrl_kmac_err_chk/latest |
| Test location | /workspace/coverage/default/2.rom_ctrl_max_throughput_chk.3536971583 |
| Short name | T224 |
| Test name | |
| Test status | |
| Simulation time | 1644857155 ps |
| CPU time | 14.6 seconds |
| Started | May 12 01:05:15 PM PDT 24 |
| Finished | May 12 01:05:30 PM PDT 24 |
| Peak memory | 211644 kb |
| Host | smart-c9f3aacd-1284-4ecb-8bad-c943b060f19d |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3536971583 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_max_throughput_chk.3536971583 |
| Directory | /workspace/2.rom_ctrl_max_throughput_chk/latest |
| Test location | /workspace/coverage/default/2.rom_ctrl_sec_cm.3280515285 |
| Short name | T39 |
| Test name | |
| Test status | |
| Simulation time | 7256618143 ps |
| CPU time | 60.65 seconds |
| Started | May 12 01:05:19 PM PDT 24 |
| Finished | May 12 01:06:20 PM PDT 24 |
| Peak memory | 231176 kb |
| Host | smart-4fb06066-1bdc-4774-8acb-d6b72ee052a1 |
| User | root |
| Command | /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3280515285 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_sec_cm.3280515285 |
| Directory | /workspace/2.rom_ctrl_sec_cm/latest |
| Test location | /workspace/coverage/default/2.rom_ctrl_smoke.2912975070 |
| Short name | T233 |
| Test name | |
| Test status | |
| Simulation time | 3480955078 ps |
| CPU time | 26.42 seconds |
| Started | May 12 01:05:14 PM PDT 24 |
| Finished | May 12 01:05:41 PM PDT 24 |
| Peak memory | 213728 kb |
| Host | smart-15542cd2-c49d-4c57-9d8f-a42c4702680a |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2912975070 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_smoke.2912975070 |
| Directory | /workspace/2.rom_ctrl_smoke/latest |
| Test location | /workspace/coverage/default/2.rom_ctrl_stress_all.2144822599 |
| Short name | T126 |
| Test name | |
| Test status | |
| Simulation time | 2912185712 ps |
| CPU time | 29.23 seconds |
| Started | May 12 01:05:20 PM PDT 24 |
| Finished | May 12 01:05:50 PM PDT 24 |
| Peak memory | 213800 kb |
| Host | smart-9434a5f4-a1c3-40ec-8280-74d96a953a9f |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2144822599 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm _name 2.rom_ctrl_stress_all.2144822599 |
| Directory | /workspace/2.rom_ctrl_stress_all/latest |
| Test location | /workspace/coverage/default/20.rom_ctrl_alert_test.1646718857 |
| Short name | T268 |
| Test name | |
| Test status | |
| Simulation time | 362499886 ps |
| CPU time | 4.28 seconds |
| Started | May 12 01:05:43 PM PDT 24 |
| Finished | May 12 01:05:48 PM PDT 24 |
| Peak memory | 211580 kb |
| Host | smart-35b6e07d-33b7-41f0-bf1d-0f170d4bfc6f |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1646718857 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_alert_test.1646718857 |
| Directory | /workspace/20.rom_ctrl_alert_test/latest |
| Test location | /workspace/coverage/default/20.rom_ctrl_corrupt_sig_fatal_chk.3101523232 |
| Short name | T113 |
| Test name | |
| Test status | |
| Simulation time | 26888022971 ps |
| CPU time | 155.73 seconds |
| Started | May 12 01:05:46 PM PDT 24 |
| Finished | May 12 01:08:22 PM PDT 24 |
| Peak memory | 237584 kb |
| Host | smart-867ede84-2e2d-4364-93d5-fff8d56cce0a |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3101523232 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_ corrupt_sig_fatal_chk.3101523232 |
| Directory | /workspace/20.rom_ctrl_corrupt_sig_fatal_chk/latest |
| Test location | /workspace/coverage/default/20.rom_ctrl_kmac_err_chk.2304378538 |
| Short name | T182 |
| Test name | |
| Test status | |
| Simulation time | 14879176597 ps |
| CPU time | 20.3 seconds |
| Started | May 12 01:05:45 PM PDT 24 |
| Finished | May 12 01:06:06 PM PDT 24 |
| Peak memory | 212876 kb |
| Host | smart-8e8a62df-5849-4858-9026-47d6047f29fc |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2304378538 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_kmac_err_chk.2304378538 |
| Directory | /workspace/20.rom_ctrl_kmac_err_chk/latest |
| Test location | /workspace/coverage/default/20.rom_ctrl_max_throughput_chk.710880860 |
| Short name | T155 |
| Test name | |
| Test status | |
| Simulation time | 1394278076 ps |
| CPU time | 9.77 seconds |
| Started | May 12 01:05:48 PM PDT 24 |
| Finished | May 12 01:05:59 PM PDT 24 |
| Peak memory | 211560 kb |
| Host | smart-a61762b5-56e6-461d-a0f9-d5790d3ceffc |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=710880860 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_max_throughput_chk.710880860 |
| Directory | /workspace/20.rom_ctrl_max_throughput_chk/latest |
| Test location | /workspace/coverage/default/20.rom_ctrl_stress_all.4105703785 |
| Short name | T167 |
| Test name | |
| Test status | |
| Simulation time | 222408698 ps |
| CPU time | 14.25 seconds |
| Started | May 12 01:05:43 PM PDT 24 |
| Finished | May 12 01:05:57 PM PDT 24 |
| Peak memory | 212544 kb |
| Host | smart-1d5aca3a-b457-4dc1-b35c-85f6428001a0 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4105703785 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm _name 20.rom_ctrl_stress_all.4105703785 |
| Directory | /workspace/20.rom_ctrl_stress_all/latest |
| Test location | /workspace/coverage/default/21.rom_ctrl_alert_test.2273396513 |
| Short name | T124 |
| Test name | |
| Test status | |
| Simulation time | 1648824084 ps |
| CPU time | 14.22 seconds |
| Started | May 12 01:05:49 PM PDT 24 |
| Finished | May 12 01:06:04 PM PDT 24 |
| Peak memory | 211692 kb |
| Host | smart-55591d84-2fdb-477b-8bfa-8a74296eff1a |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2273396513 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_alert_test.2273396513 |
| Directory | /workspace/21.rom_ctrl_alert_test/latest |
| Test location | /workspace/coverage/default/21.rom_ctrl_corrupt_sig_fatal_chk.1723564258 |
| Short name | T30 |
| Test name | |
| Test status | |
| Simulation time | 72792198401 ps |
| CPU time | 158.27 seconds |
| Started | May 12 01:05:50 PM PDT 24 |
| Finished | May 12 01:08:29 PM PDT 24 |
| Peak memory | 219020 kb |
| Host | smart-fb476ac9-7224-4392-b00a-9d49d4c8dca0 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1723564258 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_ corrupt_sig_fatal_chk.1723564258 |
| Directory | /workspace/21.rom_ctrl_corrupt_sig_fatal_chk/latest |
| Test location | /workspace/coverage/default/21.rom_ctrl_kmac_err_chk.303588169 |
| Short name | T159 |
| Test name | |
| Test status | |
| Simulation time | 2118574951 ps |
| CPU time | 22.23 seconds |
| Started | May 12 01:05:50 PM PDT 24 |
| Finished | May 12 01:06:13 PM PDT 24 |
| Peak memory | 211652 kb |
| Host | smart-4fcb5237-4f39-4e06-a803-3c90fdfec9f3 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=303588169 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_kmac_err_chk.303588169 |
| Directory | /workspace/21.rom_ctrl_kmac_err_chk/latest |
| Test location | /workspace/coverage/default/21.rom_ctrl_max_throughput_chk.188771771 |
| Short name | T320 |
| Test name | |
| Test status | |
| Simulation time | 938376482 ps |
| CPU time | 5.57 seconds |
| Started | May 12 01:05:48 PM PDT 24 |
| Finished | May 12 01:05:55 PM PDT 24 |
| Peak memory | 211596 kb |
| Host | smart-21bf312a-394a-4677-9461-9959e642d754 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=188771771 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_max_throughput_chk.188771771 |
| Directory | /workspace/21.rom_ctrl_max_throughput_chk/latest |
| Test location | /workspace/coverage/default/21.rom_ctrl_smoke.3084273426 |
| Short name | T12 |
| Test name | |
| Test status | |
| Simulation time | 6456445921 ps |
| CPU time | 27.45 seconds |
| Started | May 12 01:05:48 PM PDT 24 |
| Finished | May 12 01:06:16 PM PDT 24 |
| Peak memory | 219880 kb |
| Host | smart-fed41a24-4b3c-46f3-bdcd-becfa6735dce |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3084273426 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_smoke.3084273426 |
| Directory | /workspace/21.rom_ctrl_smoke/latest |
| Test location | /workspace/coverage/default/21.rom_ctrl_stress_all.4165059478 |
| Short name | T69 |
| Test name | |
| Test status | |
| Simulation time | 2771982173 ps |
| CPU time | 20.58 seconds |
| Started | May 12 01:05:50 PM PDT 24 |
| Finished | May 12 01:06:12 PM PDT 24 |
| Peak memory | 219924 kb |
| Host | smart-c83d5a48-74cf-413e-9ef0-0b9a88485557 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4165059478 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm _name 21.rom_ctrl_stress_all.4165059478 |
| Directory | /workspace/21.rom_ctrl_stress_all/latest |
| Test location | /workspace/coverage/default/22.rom_ctrl_alert_test.2015948173 |
| Short name | T16 |
| Test name | |
| Test status | |
| Simulation time | 1423589565 ps |
| CPU time | 12.07 seconds |
| Started | May 12 01:05:53 PM PDT 24 |
| Finished | May 12 01:06:05 PM PDT 24 |
| Peak memory | 211592 kb |
| Host | smart-0ff28a1d-e105-4ce9-8edb-0ac6eacfcd78 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2015948173 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_alert_test.2015948173 |
| Directory | /workspace/22.rom_ctrl_alert_test/latest |
| Test location | /workspace/coverage/default/22.rom_ctrl_corrupt_sig_fatal_chk.3130325914 |
| Short name | T189 |
| Test name | |
| Test status | |
| Simulation time | 15181325812 ps |
| CPU time | 169.06 seconds |
| Started | May 12 01:05:49 PM PDT 24 |
| Finished | May 12 01:08:39 PM PDT 24 |
| Peak memory | 225404 kb |
| Host | smart-d314a2d2-0f42-4873-bd53-1b6070d1eb8b |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3130325914 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_ corrupt_sig_fatal_chk.3130325914 |
| Directory | /workspace/22.rom_ctrl_corrupt_sig_fatal_chk/latest |
| Test location | /workspace/coverage/default/22.rom_ctrl_kmac_err_chk.1916765127 |
| Short name | T237 |
| Test name | |
| Test status | |
| Simulation time | 22240055051 ps |
| CPU time | 24.2 seconds |
| Started | May 12 01:05:51 PM PDT 24 |
| Finished | May 12 01:06:15 PM PDT 24 |
| Peak memory | 212524 kb |
| Host | smart-53f8cddb-2a0d-47fd-87e4-4ab803f8bf01 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1916765127 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_kmac_err_chk.1916765127 |
| Directory | /workspace/22.rom_ctrl_kmac_err_chk/latest |
| Test location | /workspace/coverage/default/22.rom_ctrl_max_throughput_chk.4019698259 |
| Short name | T300 |
| Test name | |
| Test status | |
| Simulation time | 625971184 ps |
| CPU time | 9.32 seconds |
| Started | May 12 01:05:48 PM PDT 24 |
| Finished | May 12 01:05:58 PM PDT 24 |
| Peak memory | 211488 kb |
| Host | smart-8d47f671-ece7-4686-905f-12495617a050 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=4019698259 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_max_throughput_chk.4019698259 |
| Directory | /workspace/22.rom_ctrl_max_throughput_chk/latest |
| Test location | /workspace/coverage/default/22.rom_ctrl_smoke.4209573850 |
| Short name | T209 |
| Test name | |
| Test status | |
| Simulation time | 7276540739 ps |
| CPU time | 27.03 seconds |
| Started | May 12 01:05:49 PM PDT 24 |
| Finished | May 12 01:06:17 PM PDT 24 |
| Peak memory | 219960 kb |
| Host | smart-f6eda64c-1554-4075-9fad-44ebffcccf24 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4209573850 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_smoke.4209573850 |
| Directory | /workspace/22.rom_ctrl_smoke/latest |
| Test location | /workspace/coverage/default/22.rom_ctrl_stress_all.2849283041 |
| Short name | T243 |
| Test name | |
| Test status | |
| Simulation time | 468864900 ps |
| CPU time | 24.93 seconds |
| Started | May 12 01:05:49 PM PDT 24 |
| Finished | May 12 01:06:14 PM PDT 24 |
| Peak memory | 219644 kb |
| Host | smart-314ce02c-d829-4392-9dbd-6d82481b44b9 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2849283041 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm _name 22.rom_ctrl_stress_all.2849283041 |
| Directory | /workspace/22.rom_ctrl_stress_all/latest |
| Test location | /workspace/coverage/default/23.rom_ctrl_alert_test.3716291373 |
| Short name | T55 |
| Test name | |
| Test status | |
| Simulation time | 7134228050 ps |
| CPU time | 14.78 seconds |
| Started | May 12 01:05:52 PM PDT 24 |
| Finished | May 12 01:06:07 PM PDT 24 |
| Peak memory | 211960 kb |
| Host | smart-e5468c08-25d5-4e6d-bcd2-6af4cbeceac5 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3716291373 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_alert_test.3716291373 |
| Directory | /workspace/23.rom_ctrl_alert_test/latest |
| Test location | /workspace/coverage/default/23.rom_ctrl_corrupt_sig_fatal_chk.1037886996 |
| Short name | T125 |
| Test name | |
| Test status | |
| Simulation time | 3355669907 ps |
| CPU time | 101.73 seconds |
| Started | May 12 01:05:47 PM PDT 24 |
| Finished | May 12 01:07:30 PM PDT 24 |
| Peak memory | 238732 kb |
| Host | smart-0b8de3b7-3c78-41f0-8acf-36c64d65c7d4 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1037886996 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_ corrupt_sig_fatal_chk.1037886996 |
| Directory | /workspace/23.rom_ctrl_corrupt_sig_fatal_chk/latest |
| Test location | /workspace/coverage/default/23.rom_ctrl_kmac_err_chk.1075445475 |
| Short name | T23 |
| Test name | |
| Test status | |
| Simulation time | 175559355 ps |
| CPU time | 9.4 seconds |
| Started | May 12 01:05:49 PM PDT 24 |
| Finished | May 12 01:05:59 PM PDT 24 |
| Peak memory | 212284 kb |
| Host | smart-d953f061-6e79-447d-b0ee-3fd42ac2bc7b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1075445475 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_kmac_err_chk.1075445475 |
| Directory | /workspace/23.rom_ctrl_kmac_err_chk/latest |
| Test location | /workspace/coverage/default/23.rom_ctrl_max_throughput_chk.1432884051 |
| Short name | T129 |
| Test name | |
| Test status | |
| Simulation time | 13429610072 ps |
| CPU time | 11.98 seconds |
| Started | May 12 01:05:51 PM PDT 24 |
| Finished | May 12 01:06:03 PM PDT 24 |
| Peak memory | 211896 kb |
| Host | smart-b6dce1c5-d12a-48e5-8c2a-7a946c4c5cc5 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1432884051 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_max_throughput_chk.1432884051 |
| Directory | /workspace/23.rom_ctrl_max_throughput_chk/latest |
| Test location | /workspace/coverage/default/23.rom_ctrl_smoke.2513938109 |
| Short name | T280 |
| Test name | |
| Test status | |
| Simulation time | 2313479847 ps |
| CPU time | 26.04 seconds |
| Started | May 12 01:05:48 PM PDT 24 |
| Finished | May 12 01:06:15 PM PDT 24 |
| Peak memory | 212188 kb |
| Host | smart-bc478c0d-2712-47fe-b1b9-be74deb5fce3 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2513938109 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_smoke.2513938109 |
| Directory | /workspace/23.rom_ctrl_smoke/latest |
| Test location | /workspace/coverage/default/23.rom_ctrl_stress_all.3405753709 |
| Short name | T238 |
| Test name | |
| Test status | |
| Simulation time | 103509458 ps |
| CPU time | 8.43 seconds |
| Started | May 12 01:05:49 PM PDT 24 |
| Finished | May 12 01:05:58 PM PDT 24 |
| Peak memory | 211348 kb |
| Host | smart-24b47df1-b89e-4819-bff0-7930efdafdf0 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3405753709 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm _name 23.rom_ctrl_stress_all.3405753709 |
| Directory | /workspace/23.rom_ctrl_stress_all/latest |
| Test location | /workspace/coverage/default/24.rom_ctrl_alert_test.2956841242 |
| Short name | T335 |
| Test name | |
| Test status | |
| Simulation time | 1725516498 ps |
| CPU time | 14.5 seconds |
| Started | May 12 01:05:50 PM PDT 24 |
| Finished | May 12 01:06:05 PM PDT 24 |
| Peak memory | 211576 kb |
| Host | smart-74efcbbb-139d-49c1-8571-06e4111a962e |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2956841242 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_alert_test.2956841242 |
| Directory | /workspace/24.rom_ctrl_alert_test/latest |
| Test location | /workspace/coverage/default/24.rom_ctrl_kmac_err_chk.3802238653 |
| Short name | T28 |
| Test name | |
| Test status | |
| Simulation time | 17789287896 ps |
| CPU time | 32.13 seconds |
| Started | May 12 01:05:51 PM PDT 24 |
| Finished | May 12 01:06:24 PM PDT 24 |
| Peak memory | 213516 kb |
| Host | smart-66ac31e5-4495-4b08-8048-0881d3870f46 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3802238653 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_kmac_err_chk.3802238653 |
| Directory | /workspace/24.rom_ctrl_kmac_err_chk/latest |
| Test location | /workspace/coverage/default/24.rom_ctrl_max_throughput_chk.223059318 |
| Short name | T313 |
| Test name | |
| Test status | |
| Simulation time | 3587054561 ps |
| CPU time | 11.07 seconds |
| Started | May 12 01:05:51 PM PDT 24 |
| Finished | May 12 01:06:03 PM PDT 24 |
| Peak memory | 211580 kb |
| Host | smart-fdf083b9-8e22-4911-a223-671bf5b3de09 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=223059318 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_max_throughput_chk.223059318 |
| Directory | /workspace/24.rom_ctrl_max_throughput_chk/latest |
| Test location | /workspace/coverage/default/24.rom_ctrl_smoke.1079658193 |
| Short name | T240 |
| Test name | |
| Test status | |
| Simulation time | 1336118590 ps |
| CPU time | 18.75 seconds |
| Started | May 12 01:05:50 PM PDT 24 |
| Finished | May 12 01:06:10 PM PDT 24 |
| Peak memory | 213612 kb |
| Host | smart-a25b30ad-b7d4-4d80-ae7e-68c592593b58 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1079658193 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_smoke.1079658193 |
| Directory | /workspace/24.rom_ctrl_smoke/latest |
| Test location | /workspace/coverage/default/24.rom_ctrl_stress_all.2974068077 |
| Short name | T214 |
| Test name | |
| Test status | |
| Simulation time | 413014965 ps |
| CPU time | 12.27 seconds |
| Started | May 12 01:05:52 PM PDT 24 |
| Finished | May 12 01:06:04 PM PDT 24 |
| Peak memory | 214144 kb |
| Host | smart-4a502cc9-2a4b-472a-b31c-29b54b0dddc7 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2974068077 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm _name 24.rom_ctrl_stress_all.2974068077 |
| Directory | /workspace/24.rom_ctrl_stress_all/latest |
| Test location | /workspace/coverage/default/25.rom_ctrl_alert_test.1194705837 |
| Short name | T123 |
| Test name | |
| Test status | |
| Simulation time | 86331743 ps |
| CPU time | 4.32 seconds |
| Started | May 12 01:05:48 PM PDT 24 |
| Finished | May 12 01:05:53 PM PDT 24 |
| Peak memory | 211644 kb |
| Host | smart-17030772-3e60-474f-9984-4632a0f3b971 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1194705837 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_alert_test.1194705837 |
| Directory | /workspace/25.rom_ctrl_alert_test/latest |
| Test location | /workspace/coverage/default/25.rom_ctrl_corrupt_sig_fatal_chk.80776360 |
| Short name | T258 |
| Test name | |
| Test status | |
| Simulation time | 6474113192 ps |
| CPU time | 95.14 seconds |
| Started | May 12 01:05:51 PM PDT 24 |
| Finished | May 12 01:07:27 PM PDT 24 |
| Peak memory | 230884 kb |
| Host | smart-94c61428-688b-42b6-8158-222abdaf3268 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=80776360 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_ sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_co rrupt_sig_fatal_chk.80776360 |
| Directory | /workspace/25.rom_ctrl_corrupt_sig_fatal_chk/latest |
| Test location | /workspace/coverage/default/25.rom_ctrl_kmac_err_chk.3510285629 |
| Short name | T288 |
| Test name | |
| Test status | |
| Simulation time | 168544044 ps |
| CPU time | 9.15 seconds |
| Started | May 12 01:05:51 PM PDT 24 |
| Finished | May 12 01:06:00 PM PDT 24 |
| Peak memory | 212356 kb |
| Host | smart-3fb97281-d24d-43cc-9244-e85973d97bb7 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3510285629 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_kmac_err_chk.3510285629 |
| Directory | /workspace/25.rom_ctrl_kmac_err_chk/latest |
| Test location | /workspace/coverage/default/25.rom_ctrl_max_throughput_chk.3385545346 |
| Short name | T191 |
| Test name | |
| Test status | |
| Simulation time | 6005798306 ps |
| CPU time | 14.5 seconds |
| Started | May 12 01:05:50 PM PDT 24 |
| Finished | May 12 01:06:06 PM PDT 24 |
| Peak memory | 211768 kb |
| Host | smart-51ea7e13-7591-4848-9e65-e20e09d1f1e3 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3385545346 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_max_throughput_chk.3385545346 |
| Directory | /workspace/25.rom_ctrl_max_throughput_chk/latest |
| Test location | /workspace/coverage/default/25.rom_ctrl_smoke.1408013068 |
| Short name | T163 |
| Test name | |
| Test status | |
| Simulation time | 4606560315 ps |
| CPU time | 24.42 seconds |
| Started | May 12 01:05:49 PM PDT 24 |
| Finished | May 12 01:06:14 PM PDT 24 |
| Peak memory | 219844 kb |
| Host | smart-f07f9972-4565-4bc9-8c72-ab153acf8df8 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1408013068 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_smoke.1408013068 |
| Directory | /workspace/25.rom_ctrl_smoke/latest |
| Test location | /workspace/coverage/default/25.rom_ctrl_stress_all.3850898878 |
| Short name | T348 |
| Test name | |
| Test status | |
| Simulation time | 1178229879 ps |
| CPU time | 16.39 seconds |
| Started | May 12 01:05:50 PM PDT 24 |
| Finished | May 12 01:06:07 PM PDT 24 |
| Peak memory | 211564 kb |
| Host | smart-a19358bb-6858-4147-b086-9042482bb151 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3850898878 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm _name 25.rom_ctrl_stress_all.3850898878 |
| Directory | /workspace/25.rom_ctrl_stress_all/latest |
| Test location | /workspace/coverage/default/26.rom_ctrl_alert_test.2580724745 |
| Short name | T303 |
| Test name | |
| Test status | |
| Simulation time | 3268554896 ps |
| CPU time | 9.22 seconds |
| Started | May 12 01:05:54 PM PDT 24 |
| Finished | May 12 01:06:04 PM PDT 24 |
| Peak memory | 211676 kb |
| Host | smart-6de1ad59-24c7-47ab-9e15-48b3d4c1654b |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2580724745 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_alert_test.2580724745 |
| Directory | /workspace/26.rom_ctrl_alert_test/latest |
| Test location | /workspace/coverage/default/26.rom_ctrl_corrupt_sig_fatal_chk.2288226561 |
| Short name | T196 |
| Test name | |
| Test status | |
| Simulation time | 26183928011 ps |
| CPU time | 243.68 seconds |
| Started | May 12 01:05:55 PM PDT 24 |
| Finished | May 12 01:09:59 PM PDT 24 |
| Peak memory | 225404 kb |
| Host | smart-5b78fb36-4f4e-4f0f-9917-803cc0f5caff |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2288226561 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_ corrupt_sig_fatal_chk.2288226561 |
| Directory | /workspace/26.rom_ctrl_corrupt_sig_fatal_chk/latest |
| Test location | /workspace/coverage/default/26.rom_ctrl_kmac_err_chk.2120961542 |
| Short name | T305 |
| Test name | |
| Test status | |
| Simulation time | 13910047645 ps |
| CPU time | 30.69 seconds |
| Started | May 12 01:05:55 PM PDT 24 |
| Finished | May 12 01:06:26 PM PDT 24 |
| Peak memory | 212472 kb |
| Host | smart-bcf33180-b61d-43ec-9846-131fcd30365e |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2120961542 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_kmac_err_chk.2120961542 |
| Directory | /workspace/26.rom_ctrl_kmac_err_chk/latest |
| Test location | /workspace/coverage/default/26.rom_ctrl_max_throughput_chk.1427049593 |
| Short name | T291 |
| Test name | |
| Test status | |
| Simulation time | 1579478165 ps |
| CPU time | 13.57 seconds |
| Started | May 12 01:05:54 PM PDT 24 |
| Finished | May 12 01:06:07 PM PDT 24 |
| Peak memory | 211628 kb |
| Host | smart-f11dd196-3619-4ebb-85d4-533989ab2419 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1427049593 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_max_throughput_chk.1427049593 |
| Directory | /workspace/26.rom_ctrl_max_throughput_chk/latest |
| Test location | /workspace/coverage/default/26.rom_ctrl_smoke.2381861536 |
| Short name | T283 |
| Test name | |
| Test status | |
| Simulation time | 11839688717 ps |
| CPU time | 25.65 seconds |
| Started | May 12 01:05:51 PM PDT 24 |
| Finished | May 12 01:06:18 PM PDT 24 |
| Peak memory | 219992 kb |
| Host | smart-d89bcf43-f4f3-45e7-aa00-97f423307f73 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2381861536 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_smoke.2381861536 |
| Directory | /workspace/26.rom_ctrl_smoke/latest |
| Test location | /workspace/coverage/default/26.rom_ctrl_stress_all.2141255606 |
| Short name | T2 |
| Test name | |
| Test status | |
| Simulation time | 12206991352 ps |
| CPU time | 14.58 seconds |
| Started | May 12 01:05:50 PM PDT 24 |
| Finished | May 12 01:06:05 PM PDT 24 |
| Peak memory | 218740 kb |
| Host | smart-0c9170b5-79b8-45b8-aec5-2f1b82e7f39a |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2141255606 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm _name 26.rom_ctrl_stress_all.2141255606 |
| Directory | /workspace/26.rom_ctrl_stress_all/latest |
| Test location | /workspace/coverage/default/27.rom_ctrl_alert_test.2800198885 |
| Short name | T137 |
| Test name | |
| Test status | |
| Simulation time | 85873226 ps |
| CPU time | 4.36 seconds |
| Started | May 12 01:05:57 PM PDT 24 |
| Finished | May 12 01:06:02 PM PDT 24 |
| Peak memory | 211604 kb |
| Host | smart-38eb6928-6a32-4384-9ea5-c7f3044ee0fe |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2800198885 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_alert_test.2800198885 |
| Directory | /workspace/27.rom_ctrl_alert_test/latest |
| Test location | /workspace/coverage/default/27.rom_ctrl_corrupt_sig_fatal_chk.2919709605 |
| Short name | T249 |
| Test name | |
| Test status | |
| Simulation time | 33614198573 ps |
| CPU time | 288.9 seconds |
| Started | May 12 01:05:54 PM PDT 24 |
| Finished | May 12 01:10:44 PM PDT 24 |
| Peak memory | 230652 kb |
| Host | smart-7f1577dd-062b-433e-a3af-622319344a2c |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2919709605 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_ corrupt_sig_fatal_chk.2919709605 |
| Directory | /workspace/27.rom_ctrl_corrupt_sig_fatal_chk/latest |
| Test location | /workspace/coverage/default/27.rom_ctrl_kmac_err_chk.3698280147 |
| Short name | T360 |
| Test name | |
| Test status | |
| Simulation time | 1753744385 ps |
| CPU time | 21.1 seconds |
| Started | May 12 01:05:54 PM PDT 24 |
| Finished | May 12 01:06:16 PM PDT 24 |
| Peak memory | 212252 kb |
| Host | smart-f56cf903-c698-4715-a603-c9e50110dd08 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3698280147 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_kmac_err_chk.3698280147 |
| Directory | /workspace/27.rom_ctrl_kmac_err_chk/latest |
| Test location | /workspace/coverage/default/27.rom_ctrl_max_throughput_chk.2678216465 |
| Short name | T266 |
| Test name | |
| Test status | |
| Simulation time | 1158737749 ps |
| CPU time | 8.25 seconds |
| Started | May 12 01:05:53 PM PDT 24 |
| Finished | May 12 01:06:02 PM PDT 24 |
| Peak memory | 211464 kb |
| Host | smart-900359e6-477b-4676-8e3c-4325c70282cb |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2678216465 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_max_throughput_chk.2678216465 |
| Directory | /workspace/27.rom_ctrl_max_throughput_chk/latest |
| Test location | /workspace/coverage/default/27.rom_ctrl_smoke.2209888244 |
| Short name | T183 |
| Test name | |
| Test status | |
| Simulation time | 876600937 ps |
| CPU time | 9.95 seconds |
| Started | May 12 01:05:55 PM PDT 24 |
| Finished | May 12 01:06:05 PM PDT 24 |
| Peak memory | 214028 kb |
| Host | smart-f282c198-0264-477f-9ca2-946848aee59d |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2209888244 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_smoke.2209888244 |
| Directory | /workspace/27.rom_ctrl_smoke/latest |
| Test location | /workspace/coverage/default/27.rom_ctrl_stress_all.693507612 |
| Short name | T309 |
| Test name | |
| Test status | |
| Simulation time | 12480649881 ps |
| CPU time | 18.03 seconds |
| Started | May 12 01:05:55 PM PDT 24 |
| Finished | May 12 01:06:14 PM PDT 24 |
| Peak memory | 211532 kb |
| Host | smart-432626a7-a2d6-45cf-adb1-bd4d6bdcf534 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=693507612 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test + UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 27.rom_ctrl_stress_all.693507612 |
| Directory | /workspace/27.rom_ctrl_stress_all/latest |
| Test location | /workspace/coverage/default/28.rom_ctrl_alert_test.2429287833 |
| Short name | T261 |
| Test name | |
| Test status | |
| Simulation time | 85495177 ps |
| CPU time | 4.44 seconds |
| Started | May 12 01:06:01 PM PDT 24 |
| Finished | May 12 01:06:06 PM PDT 24 |
| Peak memory | 211576 kb |
| Host | smart-07f2d169-1da5-470f-a0ab-baaf41ee22d6 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2429287833 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_alert_test.2429287833 |
| Directory | /workspace/28.rom_ctrl_alert_test/latest |
| Test location | /workspace/coverage/default/28.rom_ctrl_corrupt_sig_fatal_chk.3293788684 |
| Short name | T314 |
| Test name | |
| Test status | |
| Simulation time | 27702718416 ps |
| CPU time | 206.46 seconds |
| Started | May 12 01:05:53 PM PDT 24 |
| Finished | May 12 01:09:20 PM PDT 24 |
| Peak memory | 237336 kb |
| Host | smart-34d1174b-e3bd-48d5-a376-9e1d9e98e8af |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3293788684 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_ corrupt_sig_fatal_chk.3293788684 |
| Directory | /workspace/28.rom_ctrl_corrupt_sig_fatal_chk/latest |
| Test location | /workspace/coverage/default/28.rom_ctrl_kmac_err_chk.3156059675 |
| Short name | T127 |
| Test name | |
| Test status | |
| Simulation time | 8195215198 ps |
| CPU time | 33.41 seconds |
| Started | May 12 01:05:57 PM PDT 24 |
| Finished | May 12 01:06:31 PM PDT 24 |
| Peak memory | 213044 kb |
| Host | smart-3657f49c-6290-4814-92d3-b300d75e8abf |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3156059675 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_kmac_err_chk.3156059675 |
| Directory | /workspace/28.rom_ctrl_kmac_err_chk/latest |
| Test location | /workspace/coverage/default/28.rom_ctrl_smoke.3531026040 |
| Short name | T139 |
| Test name | |
| Test status | |
| Simulation time | 15227829464 ps |
| CPU time | 35.22 seconds |
| Started | May 12 01:05:53 PM PDT 24 |
| Finished | May 12 01:06:29 PM PDT 24 |
| Peak memory | 214164 kb |
| Host | smart-06c43c18-d143-4944-ae2d-ca9d9d09e2ed |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3531026040 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_smoke.3531026040 |
| Directory | /workspace/28.rom_ctrl_smoke/latest |
| Test location | /workspace/coverage/default/28.rom_ctrl_stress_all.2900332757 |
| Short name | T235 |
| Test name | |
| Test status | |
| Simulation time | 23290896062 ps |
| CPU time | 18.18 seconds |
| Started | May 12 01:05:52 PM PDT 24 |
| Finished | May 12 01:06:11 PM PDT 24 |
| Peak memory | 219772 kb |
| Host | smart-18ebd417-6378-4897-bfa2-89bf37f2ffef |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2900332757 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm _name 28.rom_ctrl_stress_all.2900332757 |
| Directory | /workspace/28.rom_ctrl_stress_all/latest |
| Test location | /workspace/coverage/default/29.rom_ctrl_alert_test.2904608915 |
| Short name | T195 |
| Test name | |
| Test status | |
| Simulation time | 85684761 ps |
| CPU time | 4.3 seconds |
| Started | May 12 01:05:58 PM PDT 24 |
| Finished | May 12 01:06:03 PM PDT 24 |
| Peak memory | 211508 kb |
| Host | smart-24504a80-2815-4afa-98fd-eaf665827f0f |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2904608915 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_alert_test.2904608915 |
| Directory | /workspace/29.rom_ctrl_alert_test/latest |
| Test location | /workspace/coverage/default/29.rom_ctrl_corrupt_sig_fatal_chk.3101700951 |
| Short name | T234 |
| Test name | |
| Test status | |
| Simulation time | 134521142969 ps |
| CPU time | 319.7 seconds |
| Started | May 12 01:05:59 PM PDT 24 |
| Finished | May 12 01:11:19 PM PDT 24 |
| Peak memory | 238236 kb |
| Host | smart-b57ea791-87fe-4250-974a-1a6076aa0873 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3101700951 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_ corrupt_sig_fatal_chk.3101700951 |
| Directory | /workspace/29.rom_ctrl_corrupt_sig_fatal_chk/latest |
| Test location | /workspace/coverage/default/29.rom_ctrl_kmac_err_chk.66845089 |
| Short name | T168 |
| Test name | |
| Test status | |
| Simulation time | 3676902012 ps |
| CPU time | 31.22 seconds |
| Started | May 12 01:06:00 PM PDT 24 |
| Finished | May 12 01:06:32 PM PDT 24 |
| Peak memory | 212732 kb |
| Host | smart-48d45dfd-9f0f-4a46-a980-dd9061e790f9 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=66845089 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_kmac_err_chk.66845089 |
| Directory | /workspace/29.rom_ctrl_kmac_err_chk/latest |
| Test location | /workspace/coverage/default/29.rom_ctrl_max_throughput_chk.2185903205 |
| Short name | T359 |
| Test name | |
| Test status | |
| Simulation time | 5459495677 ps |
| CPU time | 14.18 seconds |
| Started | May 12 01:05:57 PM PDT 24 |
| Finished | May 12 01:06:12 PM PDT 24 |
| Peak memory | 211644 kb |
| Host | smart-7257270a-aa22-4d13-b220-bc0f90702690 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2185903205 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_max_throughput_chk.2185903205 |
| Directory | /workspace/29.rom_ctrl_max_throughput_chk/latest |
| Test location | /workspace/coverage/default/29.rom_ctrl_smoke.2495679473 |
| Short name | T223 |
| Test name | |
| Test status | |
| Simulation time | 49538878157 ps |
| CPU time | 26.44 seconds |
| Started | May 12 01:06:02 PM PDT 24 |
| Finished | May 12 01:06:29 PM PDT 24 |
| Peak memory | 219992 kb |
| Host | smart-14601411-7b6f-4c68-a1e8-6e4a77dd7646 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2495679473 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_smoke.2495679473 |
| Directory | /workspace/29.rom_ctrl_smoke/latest |
| Test location | /workspace/coverage/default/29.rom_ctrl_stress_all.1203790474 |
| Short name | T65 |
| Test name | |
| Test status | |
| Simulation time | 3143773527 ps |
| CPU time | 42.1 seconds |
| Started | May 12 01:05:59 PM PDT 24 |
| Finished | May 12 01:06:41 PM PDT 24 |
| Peak memory | 217152 kb |
| Host | smart-2a240912-3d4c-488d-ba36-a82f56caac57 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1203790474 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm _name 29.rom_ctrl_stress_all.1203790474 |
| Directory | /workspace/29.rom_ctrl_stress_all/latest |
| Test location | /workspace/coverage/default/3.rom_ctrl_alert_test.1835594544 |
| Short name | T142 |
| Test name | |
| Test status | |
| Simulation time | 473551091 ps |
| CPU time | 7.3 seconds |
| Started | May 12 01:05:23 PM PDT 24 |
| Finished | May 12 01:05:31 PM PDT 24 |
| Peak memory | 211580 kb |
| Host | smart-a24c9535-d062-4972-90c7-3def771ae455 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1835594544 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_alert_test.1835594544 |
| Directory | /workspace/3.rom_ctrl_alert_test/latest |
| Test location | /workspace/coverage/default/3.rom_ctrl_corrupt_sig_fatal_chk.3887897238 |
| Short name | T41 |
| Test name | |
| Test status | |
| Simulation time | 23591038298 ps |
| CPU time | 195.56 seconds |
| Started | May 12 01:05:19 PM PDT 24 |
| Finished | May 12 01:08:35 PM PDT 24 |
| Peak memory | 238228 kb |
| Host | smart-81ce2c36-3d5a-4bf7-832e-e9746aabb87e |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3887897238 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_c orrupt_sig_fatal_chk.3887897238 |
| Directory | /workspace/3.rom_ctrl_corrupt_sig_fatal_chk/latest |
| Test location | /workspace/coverage/default/3.rom_ctrl_kmac_err_chk.3216802154 |
| Short name | T27 |
| Test name | |
| Test status | |
| Simulation time | 36746641367 ps |
| CPU time | 31.87 seconds |
| Started | May 12 01:05:21 PM PDT 24 |
| Finished | May 12 01:05:53 PM PDT 24 |
| Peak memory | 212480 kb |
| Host | smart-de569a0c-9f98-42d1-b70c-2751107e0eb7 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3216802154 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_kmac_err_chk.3216802154 |
| Directory | /workspace/3.rom_ctrl_kmac_err_chk/latest |
| Test location | /workspace/coverage/default/3.rom_ctrl_max_throughput_chk.3129610522 |
| Short name | T304 |
| Test name | |
| Test status | |
| Simulation time | 96189563 ps |
| CPU time | 5.51 seconds |
| Started | May 12 01:05:20 PM PDT 24 |
| Finished | May 12 01:05:26 PM PDT 24 |
| Peak memory | 211504 kb |
| Host | smart-60b7ec3d-6061-4ea5-a6c8-24dee8bbb691 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3129610522 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_max_throughput_chk.3129610522 |
| Directory | /workspace/3.rom_ctrl_max_throughput_chk/latest |
| Test location | /workspace/coverage/default/3.rom_ctrl_sec_cm.4055104739 |
| Short name | T38 |
| Test name | |
| Test status | |
| Simulation time | 7660118383 ps |
| CPU time | 58.01 seconds |
| Started | May 12 01:05:19 PM PDT 24 |
| Finished | May 12 01:06:18 PM PDT 24 |
| Peak memory | 231072 kb |
| Host | smart-31d0b240-2292-443e-836f-9af7f50daea2 |
| User | root |
| Command | /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4055104739 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_sec_cm.4055104739 |
| Directory | /workspace/3.rom_ctrl_sec_cm/latest |
| Test location | /workspace/coverage/default/3.rom_ctrl_smoke.2894381096 |
| Short name | T161 |
| Test name | |
| Test status | |
| Simulation time | 447146898 ps |
| CPU time | 13.63 seconds |
| Started | May 12 01:05:20 PM PDT 24 |
| Finished | May 12 01:05:34 PM PDT 24 |
| Peak memory | 219756 kb |
| Host | smart-b46adbb8-bb9f-42a9-86a1-fa669bdcc770 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2894381096 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_smoke.2894381096 |
| Directory | /workspace/3.rom_ctrl_smoke/latest |
| Test location | /workspace/coverage/default/3.rom_ctrl_stress_all.844846696 |
| Short name | T206 |
| Test name | |
| Test status | |
| Simulation time | 5825205792 ps |
| CPU time | 54.75 seconds |
| Started | May 12 01:05:20 PM PDT 24 |
| Finished | May 12 01:06:16 PM PDT 24 |
| Peak memory | 214052 kb |
| Host | smart-448bf598-b0b9-438a-8935-ac2e2ef6433c |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=844846696 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test + UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 3.rom_ctrl_stress_all.844846696 |
| Directory | /workspace/3.rom_ctrl_stress_all/latest |
| Test location | /workspace/coverage/default/3.rom_ctrl_stress_all_with_rand_reset.4207041362 |
| Short name | T18 |
| Test name | |
| Test status | |
| Simulation time | 43321464649 ps |
| CPU time | 1230.5 seconds |
| Started | May 12 01:05:20 PM PDT 24 |
| Finished | May 12 01:25:51 PM PDT 24 |
| Peak memory | 236380 kb |
| Host | smart-d8392bc6-3517-4693-959b-f25301cea184 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4207041362 -assert nop ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_stress_all_with_rand_reset.4207041362 |
| Directory | /workspace/3.rom_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/30.rom_ctrl_alert_test.712531597 |
| Short name | T177 |
| Test name | |
| Test status | |
| Simulation time | 4429469503 ps |
| CPU time | 11.21 seconds |
| Started | May 12 01:05:59 PM PDT 24 |
| Finished | May 12 01:06:11 PM PDT 24 |
| Peak memory | 211724 kb |
| Host | smart-48bbe3e9-8d84-404c-b190-b9872f59fb1f |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=712531597 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_alert_test.712531597 |
| Directory | /workspace/30.rom_ctrl_alert_test/latest |
| Test location | /workspace/coverage/default/30.rom_ctrl_corrupt_sig_fatal_chk.458435247 |
| Short name | T247 |
| Test name | |
| Test status | |
| Simulation time | 21341300693 ps |
| CPU time | 245.55 seconds |
| Started | May 12 01:05:59 PM PDT 24 |
| Finished | May 12 01:10:05 PM PDT 24 |
| Peak memory | 215032 kb |
| Host | smart-24def52b-8305-42d1-a764-d67141f642a2 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=458435247 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt _sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_c orrupt_sig_fatal_chk.458435247 |
| Directory | /workspace/30.rom_ctrl_corrupt_sig_fatal_chk/latest |
| Test location | /workspace/coverage/default/30.rom_ctrl_kmac_err_chk.2025407376 |
| Short name | T290 |
| Test name | |
| Test status | |
| Simulation time | 8070309026 ps |
| CPU time | 33.15 seconds |
| Started | May 12 01:05:56 PM PDT 24 |
| Finished | May 12 01:06:29 PM PDT 24 |
| Peak memory | 212760 kb |
| Host | smart-3a196341-e565-4ed4-99b9-ef684d93a0f7 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2025407376 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_kmac_err_chk.2025407376 |
| Directory | /workspace/30.rom_ctrl_kmac_err_chk/latest |
| Test location | /workspace/coverage/default/30.rom_ctrl_max_throughput_chk.1098281794 |
| Short name | T279 |
| Test name | |
| Test status | |
| Simulation time | 2468219627 ps |
| CPU time | 11.27 seconds |
| Started | May 12 01:06:01 PM PDT 24 |
| Finished | May 12 01:06:13 PM PDT 24 |
| Peak memory | 211956 kb |
| Host | smart-6030c4fb-9b0f-4239-b04f-40abe846eaf0 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1098281794 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_max_throughput_chk.1098281794 |
| Directory | /workspace/30.rom_ctrl_max_throughput_chk/latest |
| Test location | /workspace/coverage/default/30.rom_ctrl_smoke.3525580554 |
| Short name | T25 |
| Test name | |
| Test status | |
| Simulation time | 3340635042 ps |
| CPU time | 15.99 seconds |
| Started | May 12 01:05:58 PM PDT 24 |
| Finished | May 12 01:06:14 PM PDT 24 |
| Peak memory | 219936 kb |
| Host | smart-d0111f52-234f-4fa0-a470-30bdbae1ed3b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3525580554 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_smoke.3525580554 |
| Directory | /workspace/30.rom_ctrl_smoke/latest |
| Test location | /workspace/coverage/default/30.rom_ctrl_stress_all.1342677113 |
| Short name | T158 |
| Test name | |
| Test status | |
| Simulation time | 3606441924 ps |
| CPU time | 46.08 seconds |
| Started | May 12 01:05:59 PM PDT 24 |
| Finished | May 12 01:06:45 PM PDT 24 |
| Peak memory | 219780 kb |
| Host | smart-77da1110-2a8d-4c42-8272-bf13dfae3874 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1342677113 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm _name 30.rom_ctrl_stress_all.1342677113 |
| Directory | /workspace/30.rom_ctrl_stress_all/latest |
| Test location | /workspace/coverage/default/31.rom_ctrl_alert_test.1320316143 |
| Short name | T143 |
| Test name | |
| Test status | |
| Simulation time | 1894107217 ps |
| CPU time | 14.79 seconds |
| Started | May 12 01:06:01 PM PDT 24 |
| Finished | May 12 01:06:17 PM PDT 24 |
| Peak memory | 211904 kb |
| Host | smart-f88f994a-e750-4a57-8434-1641a5effc73 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1320316143 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_alert_test.1320316143 |
| Directory | /workspace/31.rom_ctrl_alert_test/latest |
| Test location | /workspace/coverage/default/31.rom_ctrl_corrupt_sig_fatal_chk.692817000 |
| Short name | T146 |
| Test name | |
| Test status | |
| Simulation time | 5168338980 ps |
| CPU time | 94.12 seconds |
| Started | May 12 01:05:58 PM PDT 24 |
| Finished | May 12 01:07:32 PM PDT 24 |
| Peak memory | 226152 kb |
| Host | smart-302d4296-582f-4106-a4c2-27244321dd04 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=692817000 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt _sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_c orrupt_sig_fatal_chk.692817000 |
| Directory | /workspace/31.rom_ctrl_corrupt_sig_fatal_chk/latest |
| Test location | /workspace/coverage/default/31.rom_ctrl_kmac_err_chk.3285258118 |
| Short name | T181 |
| Test name | |
| Test status | |
| Simulation time | 2533513604 ps |
| CPU time | 11.93 seconds |
| Started | May 12 01:05:59 PM PDT 24 |
| Finished | May 12 01:06:11 PM PDT 24 |
| Peak memory | 212272 kb |
| Host | smart-3c49f1da-2c7a-4aeb-95a0-719842bbdd10 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3285258118 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_kmac_err_chk.3285258118 |
| Directory | /workspace/31.rom_ctrl_kmac_err_chk/latest |
| Test location | /workspace/coverage/default/31.rom_ctrl_max_throughput_chk.1744631748 |
| Short name | T109 |
| Test name | |
| Test status | |
| Simulation time | 6417421750 ps |
| CPU time | 14.21 seconds |
| Started | May 12 01:06:02 PM PDT 24 |
| Finished | May 12 01:06:17 PM PDT 24 |
| Peak memory | 211748 kb |
| Host | smart-8cb97983-80da-4873-9af3-3664faf8abac |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1744631748 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_max_throughput_chk.1744631748 |
| Directory | /workspace/31.rom_ctrl_max_throughput_chk/latest |
| Test location | /workspace/coverage/default/31.rom_ctrl_smoke.2232853918 |
| Short name | T204 |
| Test name | |
| Test status | |
| Simulation time | 1118483753 ps |
| CPU time | 10.47 seconds |
| Started | May 12 01:05:59 PM PDT 24 |
| Finished | May 12 01:06:10 PM PDT 24 |
| Peak memory | 219776 kb |
| Host | smart-fda6cc98-2ca5-4550-adc1-c28124275d4c |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2232853918 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_smoke.2232853918 |
| Directory | /workspace/31.rom_ctrl_smoke/latest |
| Test location | /workspace/coverage/default/31.rom_ctrl_stress_all.1240257864 |
| Short name | T7 |
| Test name | |
| Test status | |
| Simulation time | 2860482830 ps |
| CPU time | 45.01 seconds |
| Started | May 12 01:06:07 PM PDT 24 |
| Finished | May 12 01:06:53 PM PDT 24 |
| Peak memory | 219848 kb |
| Host | smart-2a61db8d-bee0-4444-8061-77a71f9d574a |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1240257864 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm _name 31.rom_ctrl_stress_all.1240257864 |
| Directory | /workspace/31.rom_ctrl_stress_all/latest |
| Test location | /workspace/coverage/default/31.rom_ctrl_stress_all_with_rand_reset.1367884475 |
| Short name | T17 |
| Test name | |
| Test status | |
| Simulation time | 50494975242 ps |
| CPU time | 2008.85 seconds |
| Started | May 12 01:06:02 PM PDT 24 |
| Finished | May 12 01:39:32 PM PDT 24 |
| Peak memory | 244632 kb |
| Host | smart-d3bc8536-fb28-48e3-99e0-d2b679391ff2 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1367884475 -assert nop ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_stress_all_with_rand_reset.1367884475 |
| Directory | /workspace/31.rom_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/32.rom_ctrl_alert_test.1518350696 |
| Short name | T133 |
| Test name | |
| Test status | |
| Simulation time | 171721254 ps |
| CPU time | 4.26 seconds |
| Started | May 12 01:06:03 PM PDT 24 |
| Finished | May 12 01:06:08 PM PDT 24 |
| Peak memory | 211680 kb |
| Host | smart-ddb7ccba-45a6-40c2-93b1-ff5cefa2331a |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1518350696 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_alert_test.1518350696 |
| Directory | /workspace/32.rom_ctrl_alert_test/latest |
| Test location | /workspace/coverage/default/32.rom_ctrl_corrupt_sig_fatal_chk.82728642 |
| Short name | T221 |
| Test name | |
| Test status | |
| Simulation time | 71620486350 ps |
| CPU time | 426.19 seconds |
| Started | May 12 01:06:04 PM PDT 24 |
| Finished | May 12 01:13:11 PM PDT 24 |
| Peak memory | 235220 kb |
| Host | smart-88b01c1f-af37-4531-94f3-23c8010e2dce |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82728642 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_ sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_co rrupt_sig_fatal_chk.82728642 |
| Directory | /workspace/32.rom_ctrl_corrupt_sig_fatal_chk/latest |
| Test location | /workspace/coverage/default/32.rom_ctrl_kmac_err_chk.547118408 |
| Short name | T151 |
| Test name | |
| Test status | |
| Simulation time | 6350775819 ps |
| CPU time | 29.04 seconds |
| Started | May 12 01:06:03 PM PDT 24 |
| Finished | May 12 01:06:33 PM PDT 24 |
| Peak memory | 212860 kb |
| Host | smart-0e085fed-fe26-4291-9a59-5db44e8fab65 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=547118408 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_kmac_err_chk.547118408 |
| Directory | /workspace/32.rom_ctrl_kmac_err_chk/latest |
| Test location | /workspace/coverage/default/32.rom_ctrl_max_throughput_chk.2082039511 |
| Short name | T170 |
| Test name | |
| Test status | |
| Simulation time | 225236892 ps |
| CPU time | 6.95 seconds |
| Started | May 12 01:06:10 PM PDT 24 |
| Finished | May 12 01:06:18 PM PDT 24 |
| Peak memory | 211540 kb |
| Host | smart-c80f8564-079c-4e24-93b1-e248c7fbd7f1 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2082039511 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_max_throughput_chk.2082039511 |
| Directory | /workspace/32.rom_ctrl_max_throughput_chk/latest |
| Test location | /workspace/coverage/default/32.rom_ctrl_smoke.1973718153 |
| Short name | T246 |
| Test name | |
| Test status | |
| Simulation time | 16801062320 ps |
| CPU time | 37.33 seconds |
| Started | May 12 01:06:02 PM PDT 24 |
| Finished | May 12 01:06:41 PM PDT 24 |
| Peak memory | 214732 kb |
| Host | smart-ce6221d8-a817-4817-8647-b1285f13bf81 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1973718153 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_smoke.1973718153 |
| Directory | /workspace/32.rom_ctrl_smoke/latest |
| Test location | /workspace/coverage/default/32.rom_ctrl_stress_all.4143349076 |
| Short name | T310 |
| Test name | |
| Test status | |
| Simulation time | 9702645177 ps |
| CPU time | 54.98 seconds |
| Started | May 12 01:06:02 PM PDT 24 |
| Finished | May 12 01:06:58 PM PDT 24 |
| Peak memory | 219760 kb |
| Host | smart-fd05d72d-6857-45fa-9af3-0fe3f9f78998 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4143349076 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm _name 32.rom_ctrl_stress_all.4143349076 |
| Directory | /workspace/32.rom_ctrl_stress_all/latest |
| Test location | /workspace/coverage/default/32.rom_ctrl_stress_all_with_rand_reset.495546645 |
| Short name | T46 |
| Test name | |
| Test status | |
| Simulation time | 196321250404 ps |
| CPU time | 2115.59 seconds |
| Started | May 12 01:06:08 PM PDT 24 |
| Finished | May 12 01:41:24 PM PDT 24 |
| Peak memory | 248824 kb |
| Host | smart-de7713e2-9697-4ac4-ad51-f23a68762ad9 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=495546645 -assert nopo stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera ge/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_stress_all_with_rand_reset.495546645 |
| Directory | /workspace/32.rom_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/33.rom_ctrl_alert_test.2139115277 |
| Short name | T318 |
| Test name | |
| Test status | |
| Simulation time | 4237483264 ps |
| CPU time | 11.58 seconds |
| Started | May 12 01:06:01 PM PDT 24 |
| Finished | May 12 01:06:13 PM PDT 24 |
| Peak memory | 211716 kb |
| Host | smart-420150a4-db68-4b85-bb3c-012ca2024795 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2139115277 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_alert_test.2139115277 |
| Directory | /workspace/33.rom_ctrl_alert_test/latest |
| Test location | /workspace/coverage/default/33.rom_ctrl_corrupt_sig_fatal_chk.1328895869 |
| Short name | T157 |
| Test name | |
| Test status | |
| Simulation time | 18288907538 ps |
| CPU time | 232.44 seconds |
| Started | May 12 01:06:10 PM PDT 24 |
| Finished | May 12 01:10:03 PM PDT 24 |
| Peak memory | 238216 kb |
| Host | smart-7d60de6f-3d4a-4e28-ac30-c382cfb31f34 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1328895869 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_ corrupt_sig_fatal_chk.1328895869 |
| Directory | /workspace/33.rom_ctrl_corrupt_sig_fatal_chk/latest |
| Test location | /workspace/coverage/default/33.rom_ctrl_kmac_err_chk.2232748612 |
| Short name | T298 |
| Test name | |
| Test status | |
| Simulation time | 2746444236 ps |
| CPU time | 24.97 seconds |
| Started | May 12 01:06:10 PM PDT 24 |
| Finished | May 12 01:06:36 PM PDT 24 |
| Peak memory | 212584 kb |
| Host | smart-4e6743ad-d212-4456-98f4-fe291cbcc188 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2232748612 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_kmac_err_chk.2232748612 |
| Directory | /workspace/33.rom_ctrl_kmac_err_chk/latest |
| Test location | /workspace/coverage/default/33.rom_ctrl_max_throughput_chk.3608207045 |
| Short name | T307 |
| Test name | |
| Test status | |
| Simulation time | 2835410918 ps |
| CPU time | 13.87 seconds |
| Started | May 12 01:06:02 PM PDT 24 |
| Finished | May 12 01:06:17 PM PDT 24 |
| Peak memory | 211748 kb |
| Host | smart-a6f44759-fa73-4093-939e-a3b8e16db8a5 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3608207045 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_max_throughput_chk.3608207045 |
| Directory | /workspace/33.rom_ctrl_max_throughput_chk/latest |
| Test location | /workspace/coverage/default/33.rom_ctrl_smoke.1599713607 |
| Short name | T68 |
| Test name | |
| Test status | |
| Simulation time | 7539108800 ps |
| CPU time | 34.27 seconds |
| Started | May 12 01:06:08 PM PDT 24 |
| Finished | May 12 01:06:43 PM PDT 24 |
| Peak memory | 219908 kb |
| Host | smart-78a16e5a-0252-4ba4-908b-547391e1adcd |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1599713607 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_smoke.1599713607 |
| Directory | /workspace/33.rom_ctrl_smoke/latest |
| Test location | /workspace/coverage/default/33.rom_ctrl_stress_all.2944690407 |
| Short name | T148 |
| Test name | |
| Test status | |
| Simulation time | 2735847435 ps |
| CPU time | 24.58 seconds |
| Started | May 12 01:06:05 PM PDT 24 |
| Finished | May 12 01:06:30 PM PDT 24 |
| Peak memory | 216784 kb |
| Host | smart-ffdbc51e-aa3f-416d-8d47-92f00b3a843e |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2944690407 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm _name 33.rom_ctrl_stress_all.2944690407 |
| Directory | /workspace/33.rom_ctrl_stress_all/latest |
| Test location | /workspace/coverage/default/34.rom_ctrl_alert_test.1500562534 |
| Short name | T241 |
| Test name | |
| Test status | |
| Simulation time | 3377344148 ps |
| CPU time | 14.69 seconds |
| Started | May 12 01:06:03 PM PDT 24 |
| Finished | May 12 01:06:18 PM PDT 24 |
| Peak memory | 211680 kb |
| Host | smart-263bd20c-7c7c-4a28-9f90-d6d19a037390 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1500562534 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_alert_test.1500562534 |
| Directory | /workspace/34.rom_ctrl_alert_test/latest |
| Test location | /workspace/coverage/default/34.rom_ctrl_corrupt_sig_fatal_chk.1767255836 |
| Short name | T152 |
| Test name | |
| Test status | |
| Simulation time | 131134998506 ps |
| CPU time | 367.69 seconds |
| Started | May 12 01:06:10 PM PDT 24 |
| Finished | May 12 01:12:19 PM PDT 24 |
| Peak memory | 234176 kb |
| Host | smart-a2e428c5-b9b3-4dad-a832-a3455f0a1e07 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1767255836 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_ corrupt_sig_fatal_chk.1767255836 |
| Directory | /workspace/34.rom_ctrl_corrupt_sig_fatal_chk/latest |
| Test location | /workspace/coverage/default/34.rom_ctrl_kmac_err_chk.3589513763 |
| Short name | T264 |
| Test name | |
| Test status | |
| Simulation time | 12334438456 ps |
| CPU time | 14.7 seconds |
| Started | May 12 01:06:03 PM PDT 24 |
| Finished | May 12 01:06:19 PM PDT 24 |
| Peak memory | 212680 kb |
| Host | smart-e336cda1-59c0-415f-b62b-161fb5f2fc7a |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3589513763 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_kmac_err_chk.3589513763 |
| Directory | /workspace/34.rom_ctrl_kmac_err_chk/latest |
| Test location | /workspace/coverage/default/34.rom_ctrl_max_throughput_chk.1883115758 |
| Short name | T190 |
| Test name | |
| Test status | |
| Simulation time | 232280193 ps |
| CPU time | 7.14 seconds |
| Started | May 12 01:06:04 PM PDT 24 |
| Finished | May 12 01:06:12 PM PDT 24 |
| Peak memory | 211648 kb |
| Host | smart-cd1c7f99-96c0-4470-82bc-84a362e706e5 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1883115758 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_max_throughput_chk.1883115758 |
| Directory | /workspace/34.rom_ctrl_max_throughput_chk/latest |
| Test location | /workspace/coverage/default/34.rom_ctrl_smoke.289285900 |
| Short name | T145 |
| Test name | |
| Test status | |
| Simulation time | 7914934612 ps |
| CPU time | 24.02 seconds |
| Started | May 12 01:06:10 PM PDT 24 |
| Finished | May 12 01:06:35 PM PDT 24 |
| Peak memory | 219924 kb |
| Host | smart-fe2768bf-424e-4abe-a5a9-4b5759240689 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=289285900 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_smoke.289285900 |
| Directory | /workspace/34.rom_ctrl_smoke/latest |
| Test location | /workspace/coverage/default/34.rom_ctrl_stress_all.772977082 |
| Short name | T225 |
| Test name | |
| Test status | |
| Simulation time | 1567745997 ps |
| CPU time | 25.01 seconds |
| Started | May 12 01:06:01 PM PDT 24 |
| Finished | May 12 01:06:27 PM PDT 24 |
| Peak memory | 215924 kb |
| Host | smart-aa43790d-b4f8-405e-a18e-aaf4e6101f0d |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=772977082 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test + UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 34.rom_ctrl_stress_all.772977082 |
| Directory | /workspace/34.rom_ctrl_stress_all/latest |
| Test location | /workspace/coverage/default/35.rom_ctrl_alert_test.1338800831 |
| Short name | T282 |
| Test name | |
| Test status | |
| Simulation time | 87377705 ps |
| CPU time | 4.32 seconds |
| Started | May 12 01:06:08 PM PDT 24 |
| Finished | May 12 01:06:13 PM PDT 24 |
| Peak memory | 211524 kb |
| Host | smart-7e2559ca-1b6a-4580-98a9-494f9f7b229a |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1338800831 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_alert_test.1338800831 |
| Directory | /workspace/35.rom_ctrl_alert_test/latest |
| Test location | /workspace/coverage/default/35.rom_ctrl_corrupt_sig_fatal_chk.3678459662 |
| Short name | T332 |
| Test name | |
| Test status | |
| Simulation time | 86175171760 ps |
| CPU time | 264.72 seconds |
| Started | May 12 01:06:08 PM PDT 24 |
| Finished | May 12 01:10:33 PM PDT 24 |
| Peak memory | 242104 kb |
| Host | smart-9941552e-1e72-471b-9532-916d571a3e42 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3678459662 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_ corrupt_sig_fatal_chk.3678459662 |
| Directory | /workspace/35.rom_ctrl_corrupt_sig_fatal_chk/latest |
| Test location | /workspace/coverage/default/35.rom_ctrl_kmac_err_chk.2359651547 |
| Short name | T296 |
| Test name | |
| Test status | |
| Simulation time | 15063238211 ps |
| CPU time | 32.09 seconds |
| Started | May 12 01:06:09 PM PDT 24 |
| Finished | May 12 01:06:42 PM PDT 24 |
| Peak memory | 212568 kb |
| Host | smart-149d143e-f9ed-45fe-9c1d-08d3a5253ed0 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2359651547 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_kmac_err_chk.2359651547 |
| Directory | /workspace/35.rom_ctrl_kmac_err_chk/latest |
| Test location | /workspace/coverage/default/35.rom_ctrl_max_throughput_chk.920407685 |
| Short name | T90 |
| Test name | |
| Test status | |
| Simulation time | 1509049380 ps |
| CPU time | 9.73 seconds |
| Started | May 12 01:06:08 PM PDT 24 |
| Finished | May 12 01:06:18 PM PDT 24 |
| Peak memory | 211640 kb |
| Host | smart-2a7ad117-ce57-4cc3-abf1-949b947cd5da |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=920407685 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_max_throughput_chk.920407685 |
| Directory | /workspace/35.rom_ctrl_max_throughput_chk/latest |
| Test location | /workspace/coverage/default/35.rom_ctrl_smoke.700891961 |
| Short name | T132 |
| Test name | |
| Test status | |
| Simulation time | 2373627531 ps |
| CPU time | 15.06 seconds |
| Started | May 12 01:06:02 PM PDT 24 |
| Finished | May 12 01:06:18 PM PDT 24 |
| Peak memory | 219864 kb |
| Host | smart-59c5c855-fa86-47fe-a8c2-cd715bb9d3ac |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=700891961 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_smoke.700891961 |
| Directory | /workspace/35.rom_ctrl_smoke/latest |
| Test location | /workspace/coverage/default/35.rom_ctrl_stress_all.2637808182 |
| Short name | T281 |
| Test name | |
| Test status | |
| Simulation time | 12739323172 ps |
| CPU time | 32.75 seconds |
| Started | May 12 01:06:08 PM PDT 24 |
| Finished | May 12 01:06:41 PM PDT 24 |
| Peak memory | 214212 kb |
| Host | smart-f2f4c152-68cf-401c-8b4b-47242332c77c |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2637808182 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm _name 35.rom_ctrl_stress_all.2637808182 |
| Directory | /workspace/35.rom_ctrl_stress_all/latest |
| Test location | /workspace/coverage/default/35.rom_ctrl_stress_all_with_rand_reset.1598027097 |
| Short name | T358 |
| Test name | |
| Test status | |
| Simulation time | 75821238061 ps |
| CPU time | 775.19 seconds |
| Started | May 12 01:06:06 PM PDT 24 |
| Finished | May 12 01:19:02 PM PDT 24 |
| Peak memory | 228256 kb |
| Host | smart-64035848-bef4-4206-ba13-54a6f0ecde8b |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1598027097 -assert nop ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_stress_all_with_rand_reset.1598027097 |
| Directory | /workspace/35.rom_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/36.rom_ctrl_alert_test.2335372130 |
| Short name | T284 |
| Test name | |
| Test status | |
| Simulation time | 89972680 ps |
| CPU time | 4.28 seconds |
| Started | May 12 01:06:12 PM PDT 24 |
| Finished | May 12 01:06:17 PM PDT 24 |
| Peak memory | 211556 kb |
| Host | smart-8056385a-aadf-4b95-9ba8-aaea1311d534 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2335372130 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_alert_test.2335372130 |
| Directory | /workspace/36.rom_ctrl_alert_test/latest |
| Test location | /workspace/coverage/default/36.rom_ctrl_corrupt_sig_fatal_chk.3216396707 |
| Short name | T198 |
| Test name | |
| Test status | |
| Simulation time | 37070661445 ps |
| CPU time | 363.68 seconds |
| Started | May 12 01:06:07 PM PDT 24 |
| Finished | May 12 01:12:11 PM PDT 24 |
| Peak memory | 238720 kb |
| Host | smart-8bf3a042-4ebc-40e0-9015-e9b36a356c38 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3216396707 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_ corrupt_sig_fatal_chk.3216396707 |
| Directory | /workspace/36.rom_ctrl_corrupt_sig_fatal_chk/latest |
| Test location | /workspace/coverage/default/36.rom_ctrl_kmac_err_chk.741861266 |
| Short name | T147 |
| Test name | |
| Test status | |
| Simulation time | 3190037136 ps |
| CPU time | 28.63 seconds |
| Started | May 12 01:06:09 PM PDT 24 |
| Finished | May 12 01:06:39 PM PDT 24 |
| Peak memory | 212620 kb |
| Host | smart-9526a1b7-c426-48f4-a5a1-8f023e4a58ee |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=741861266 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_kmac_err_chk.741861266 |
| Directory | /workspace/36.rom_ctrl_kmac_err_chk/latest |
| Test location | /workspace/coverage/default/36.rom_ctrl_max_throughput_chk.2868808716 |
| Short name | T251 |
| Test name | |
| Test status | |
| Simulation time | 7226593323 ps |
| CPU time | 17 seconds |
| Started | May 12 01:06:06 PM PDT 24 |
| Finished | May 12 01:06:24 PM PDT 24 |
| Peak memory | 211632 kb |
| Host | smart-a8cd08d6-a45c-42e3-bcae-fcae9db54eb5 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2868808716 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_max_throughput_chk.2868808716 |
| Directory | /workspace/36.rom_ctrl_max_throughput_chk/latest |
| Test location | /workspace/coverage/default/36.rom_ctrl_smoke.540824245 |
| Short name | T178 |
| Test name | |
| Test status | |
| Simulation time | 1939548579 ps |
| CPU time | 13.46 seconds |
| Started | May 12 01:06:07 PM PDT 24 |
| Finished | May 12 01:06:21 PM PDT 24 |
| Peak memory | 211740 kb |
| Host | smart-7e0f47ef-620f-429c-8fdc-37c15710b348 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=540824245 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_smoke.540824245 |
| Directory | /workspace/36.rom_ctrl_smoke/latest |
| Test location | /workspace/coverage/default/36.rom_ctrl_stress_all.2648473000 |
| Short name | T323 |
| Test name | |
| Test status | |
| Simulation time | 8478591902 ps |
| CPU time | 85.76 seconds |
| Started | May 12 01:06:06 PM PDT 24 |
| Finished | May 12 01:07:33 PM PDT 24 |
| Peak memory | 219880 kb |
| Host | smart-2b7c1452-6a78-44cf-bf90-f8e38f42107b |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2648473000 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm _name 36.rom_ctrl_stress_all.2648473000 |
| Directory | /workspace/36.rom_ctrl_stress_all/latest |
| Test location | /workspace/coverage/default/37.rom_ctrl_alert_test.3090052164 |
| Short name | T37 |
| Test name | |
| Test status | |
| Simulation time | 4388277554 ps |
| CPU time | 8.38 seconds |
| Started | May 12 01:06:12 PM PDT 24 |
| Finished | May 12 01:06:21 PM PDT 24 |
| Peak memory | 211696 kb |
| Host | smart-1a9d3acc-cf3f-4e61-91d0-34b809617067 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3090052164 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_alert_test.3090052164 |
| Directory | /workspace/37.rom_ctrl_alert_test/latest |
| Test location | /workspace/coverage/default/37.rom_ctrl_corrupt_sig_fatal_chk.3999442371 |
| Short name | T215 |
| Test name | |
| Test status | |
| Simulation time | 17360591746 ps |
| CPU time | 218.52 seconds |
| Started | May 12 01:06:12 PM PDT 24 |
| Finished | May 12 01:09:51 PM PDT 24 |
| Peak memory | 238184 kb |
| Host | smart-fefc6181-ab13-42bd-baf2-c835b6e40bb5 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3999442371 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_ corrupt_sig_fatal_chk.3999442371 |
| Directory | /workspace/37.rom_ctrl_corrupt_sig_fatal_chk/latest |
| Test location | /workspace/coverage/default/37.rom_ctrl_kmac_err_chk.2395810747 |
| Short name | T164 |
| Test name | |
| Test status | |
| Simulation time | 987664008 ps |
| CPU time | 16.1 seconds |
| Started | May 12 01:06:14 PM PDT 24 |
| Finished | May 12 01:06:31 PM PDT 24 |
| Peak memory | 212260 kb |
| Host | smart-c07c4c4e-dd2e-4b5e-b261-dcf76074cea0 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2395810747 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_kmac_err_chk.2395810747 |
| Directory | /workspace/37.rom_ctrl_kmac_err_chk/latest |
| Test location | /workspace/coverage/default/37.rom_ctrl_max_throughput_chk.3919186787 |
| Short name | T230 |
| Test name | |
| Test status | |
| Simulation time | 2757737071 ps |
| CPU time | 14.86 seconds |
| Started | May 12 01:06:15 PM PDT 24 |
| Finished | May 12 01:06:30 PM PDT 24 |
| Peak memory | 211680 kb |
| Host | smart-3ba569ed-f5ea-4b1a-8174-7ae6d856c68a |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3919186787 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_max_throughput_chk.3919186787 |
| Directory | /workspace/37.rom_ctrl_max_throughput_chk/latest |
| Test location | /workspace/coverage/default/37.rom_ctrl_smoke.3027271205 |
| Short name | T301 |
| Test name | |
| Test status | |
| Simulation time | 4442759504 ps |
| CPU time | 35.2 seconds |
| Started | May 12 01:06:12 PM PDT 24 |
| Finished | May 12 01:06:48 PM PDT 24 |
| Peak memory | 219992 kb |
| Host | smart-0e18f215-cdd8-47b1-8549-d139a8338106 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3027271205 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_smoke.3027271205 |
| Directory | /workspace/37.rom_ctrl_smoke/latest |
| Test location | /workspace/coverage/default/37.rom_ctrl_stress_all.2636579324 |
| Short name | T197 |
| Test name | |
| Test status | |
| Simulation time | 1664212001 ps |
| CPU time | 26.13 seconds |
| Started | May 12 01:06:13 PM PDT 24 |
| Finished | May 12 01:06:40 PM PDT 24 |
| Peak memory | 214900 kb |
| Host | smart-b0325c08-aad6-49d3-a2d1-98948778b987 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2636579324 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm _name 37.rom_ctrl_stress_all.2636579324 |
| Directory | /workspace/37.rom_ctrl_stress_all/latest |
| Test location | /workspace/coverage/default/38.rom_ctrl_alert_test.289444218 |
| Short name | T269 |
| Test name | |
| Test status | |
| Simulation time | 734137329 ps |
| CPU time | 8.53 seconds |
| Started | May 12 01:06:22 PM PDT 24 |
| Finished | May 12 01:06:31 PM PDT 24 |
| Peak memory | 211904 kb |
| Host | smart-6f81afeb-9378-444f-ac62-d9885f6ed95a |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=289444218 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_alert_test.289444218 |
| Directory | /workspace/38.rom_ctrl_alert_test/latest |
| Test location | /workspace/coverage/default/38.rom_ctrl_corrupt_sig_fatal_chk.1489054627 |
| Short name | T144 |
| Test name | |
| Test status | |
| Simulation time | 50509738415 ps |
| CPU time | 253.32 seconds |
| Started | May 12 01:06:11 PM PDT 24 |
| Finished | May 12 01:10:25 PM PDT 24 |
| Peak memory | 238268 kb |
| Host | smart-adcc6880-848b-466d-9350-dcf1ad4dfb7b |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1489054627 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_ corrupt_sig_fatal_chk.1489054627 |
| Directory | /workspace/38.rom_ctrl_corrupt_sig_fatal_chk/latest |
| Test location | /workspace/coverage/default/38.rom_ctrl_kmac_err_chk.909252321 |
| Short name | T292 |
| Test name | |
| Test status | |
| Simulation time | 693374270 ps |
| CPU time | 9.91 seconds |
| Started | May 12 01:06:13 PM PDT 24 |
| Finished | May 12 01:06:23 PM PDT 24 |
| Peak memory | 212148 kb |
| Host | smart-96841800-cb9e-4787-a6c2-dc9b638dbece |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=909252321 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_kmac_err_chk.909252321 |
| Directory | /workspace/38.rom_ctrl_kmac_err_chk/latest |
| Test location | /workspace/coverage/default/38.rom_ctrl_max_throughput_chk.1582024179 |
| Short name | T14 |
| Test name | |
| Test status | |
| Simulation time | 4447537637 ps |
| CPU time | 11.8 seconds |
| Started | May 12 01:06:12 PM PDT 24 |
| Finished | May 12 01:06:25 PM PDT 24 |
| Peak memory | 211640 kb |
| Host | smart-fc4811e7-876e-4ca8-a97a-1dd2fcc3a332 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1582024179 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_max_throughput_chk.1582024179 |
| Directory | /workspace/38.rom_ctrl_max_throughput_chk/latest |
| Test location | /workspace/coverage/default/38.rom_ctrl_smoke.431208501 |
| Short name | T330 |
| Test name | |
| Test status | |
| Simulation time | 1971984550 ps |
| CPU time | 28.45 seconds |
| Started | May 12 01:06:14 PM PDT 24 |
| Finished | May 12 01:06:42 PM PDT 24 |
| Peak memory | 219704 kb |
| Host | smart-fab1b4e2-fbcb-41ba-92e8-2f3324ac9e2f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=431208501 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_smoke.431208501 |
| Directory | /workspace/38.rom_ctrl_smoke/latest |
| Test location | /workspace/coverage/default/38.rom_ctrl_stress_all.4009763261 |
| Short name | T173 |
| Test name | |
| Test status | |
| Simulation time | 1567534587 ps |
| CPU time | 19.98 seconds |
| Started | May 12 01:06:13 PM PDT 24 |
| Finished | May 12 01:06:33 PM PDT 24 |
| Peak memory | 219664 kb |
| Host | smart-7dc0849f-8b1f-4b7b-9303-3ef46c82c206 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4009763261 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm _name 38.rom_ctrl_stress_all.4009763261 |
| Directory | /workspace/38.rom_ctrl_stress_all/latest |
| Test location | /workspace/coverage/default/38.rom_ctrl_stress_all_with_rand_reset.3461003589 |
| Short name | T45 |
| Test name | |
| Test status | |
| Simulation time | 399349948842 ps |
| CPU time | 3521.43 seconds |
| Started | May 12 01:06:15 PM PDT 24 |
| Finished | May 12 02:04:57 PM PDT 24 |
| Peak memory | 252788 kb |
| Host | smart-b527732f-f2d0-4a9d-814e-0a43691f21b8 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3461003589 -assert nop ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_stress_all_with_rand_reset.3461003589 |
| Directory | /workspace/38.rom_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/39.rom_ctrl_alert_test.2598805313 |
| Short name | T120 |
| Test name | |
| Test status | |
| Simulation time | 1481153200 ps |
| CPU time | 13.78 seconds |
| Started | May 12 01:06:16 PM PDT 24 |
| Finished | May 12 01:06:31 PM PDT 24 |
| Peak memory | 211840 kb |
| Host | smart-d223231a-cff7-42f9-9855-fe6f1834c962 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2598805313 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_alert_test.2598805313 |
| Directory | /workspace/39.rom_ctrl_alert_test/latest |
| Test location | /workspace/coverage/default/39.rom_ctrl_kmac_err_chk.463643671 |
| Short name | T245 |
| Test name | |
| Test status | |
| Simulation time | 8793483612 ps |
| CPU time | 35.25 seconds |
| Started | May 12 01:06:13 PM PDT 24 |
| Finished | May 12 01:06:49 PM PDT 24 |
| Peak memory | 212600 kb |
| Host | smart-9c749edf-a3c4-4713-af21-1c3b54f2b000 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=463643671 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_kmac_err_chk.463643671 |
| Directory | /workspace/39.rom_ctrl_kmac_err_chk/latest |
| Test location | /workspace/coverage/default/39.rom_ctrl_max_throughput_chk.1421335911 |
| Short name | T315 |
| Test name | |
| Test status | |
| Simulation time | 1240345263 ps |
| CPU time | 12.8 seconds |
| Started | May 12 01:06:15 PM PDT 24 |
| Finished | May 12 01:06:28 PM PDT 24 |
| Peak memory | 211836 kb |
| Host | smart-21bfdf7a-2e91-4850-8b01-40523e2d8d1a |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1421335911 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_max_throughput_chk.1421335911 |
| Directory | /workspace/39.rom_ctrl_max_throughput_chk/latest |
| Test location | /workspace/coverage/default/39.rom_ctrl_smoke.496843850 |
| Short name | T67 |
| Test name | |
| Test status | |
| Simulation time | 10197589198 ps |
| CPU time | 28.02 seconds |
| Started | May 12 01:06:11 PM PDT 24 |
| Finished | May 12 01:06:40 PM PDT 24 |
| Peak memory | 219960 kb |
| Host | smart-dd381d2c-d5f5-4e28-be51-3b0bb5c6f405 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=496843850 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_smoke.496843850 |
| Directory | /workspace/39.rom_ctrl_smoke/latest |
| Test location | /workspace/coverage/default/39.rom_ctrl_stress_all.2904841879 |
| Short name | T174 |
| Test name | |
| Test status | |
| Simulation time | 22489740004 ps |
| CPU time | 28.13 seconds |
| Started | May 12 01:06:11 PM PDT 24 |
| Finished | May 12 01:06:40 PM PDT 24 |
| Peak memory | 214296 kb |
| Host | smart-9b2943fb-dd8c-4921-bfa3-24289dada385 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2904841879 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm _name 39.rom_ctrl_stress_all.2904841879 |
| Directory | /workspace/39.rom_ctrl_stress_all/latest |
| Test location | /workspace/coverage/default/4.rom_ctrl_alert_test.3190114668 |
| Short name | T1 |
| Test name | |
| Test status | |
| Simulation time | 2572206832 ps |
| CPU time | 8.26 seconds |
| Started | May 12 01:05:22 PM PDT 24 |
| Finished | May 12 01:05:30 PM PDT 24 |
| Peak memory | 211828 kb |
| Host | smart-7bec3e1c-d284-4f95-8251-b3ba09f43e4a |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3190114668 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_alert_test.3190114668 |
| Directory | /workspace/4.rom_ctrl_alert_test/latest |
| Test location | /workspace/coverage/default/4.rom_ctrl_corrupt_sig_fatal_chk.2905946132 |
| Short name | T342 |
| Test name | |
| Test status | |
| Simulation time | 39480289295 ps |
| CPU time | 205.67 seconds |
| Started | May 12 01:05:19 PM PDT 24 |
| Finished | May 12 01:08:45 PM PDT 24 |
| Peak memory | 237240 kb |
| Host | smart-83461769-5b14-4f0a-9a17-a2b9eb462ad6 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2905946132 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_c orrupt_sig_fatal_chk.2905946132 |
| Directory | /workspace/4.rom_ctrl_corrupt_sig_fatal_chk/latest |
| Test location | /workspace/coverage/default/4.rom_ctrl_kmac_err_chk.1174940585 |
| Short name | T334 |
| Test name | |
| Test status | |
| Simulation time | 10502257136 ps |
| CPU time | 34.89 seconds |
| Started | May 12 01:05:19 PM PDT 24 |
| Finished | May 12 01:05:54 PM PDT 24 |
| Peak memory | 212616 kb |
| Host | smart-8ec6e8c4-3fa0-421a-ba29-678e7a0e355d |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1174940585 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_kmac_err_chk.1174940585 |
| Directory | /workspace/4.rom_ctrl_kmac_err_chk/latest |
| Test location | /workspace/coverage/default/4.rom_ctrl_max_throughput_chk.2772164696 |
| Short name | T188 |
| Test name | |
| Test status | |
| Simulation time | 360558185 ps |
| CPU time | 5.76 seconds |
| Started | May 12 01:05:20 PM PDT 24 |
| Finished | May 12 01:05:26 PM PDT 24 |
| Peak memory | 211636 kb |
| Host | smart-17e7cf2d-e1ad-47c7-aaac-68a9938adfbb |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2772164696 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_max_throughput_chk.2772164696 |
| Directory | /workspace/4.rom_ctrl_max_throughput_chk/latest |
| Test location | /workspace/coverage/default/4.rom_ctrl_sec_cm.1614676553 |
| Short name | T31 |
| Test name | |
| Test status | |
| Simulation time | 3486959095 ps |
| CPU time | 104.64 seconds |
| Started | May 12 01:05:18 PM PDT 24 |
| Finished | May 12 01:07:03 PM PDT 24 |
| Peak memory | 238180 kb |
| Host | smart-3ba1c736-5156-46ef-86cf-7cfdf4a6976d |
| User | root |
| Command | /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1614676553 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_sec_cm.1614676553 |
| Directory | /workspace/4.rom_ctrl_sec_cm/latest |
| Test location | /workspace/coverage/default/4.rom_ctrl_stress_all.3709054148 |
| Short name | T286 |
| Test name | |
| Test status | |
| Simulation time | 3323001292 ps |
| CPU time | 55.48 seconds |
| Started | May 12 01:05:19 PM PDT 24 |
| Finished | May 12 01:06:15 PM PDT 24 |
| Peak memory | 216736 kb |
| Host | smart-39dc2458-716b-4f31-b14b-99bcab909048 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3709054148 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm _name 4.rom_ctrl_stress_all.3709054148 |
| Directory | /workspace/4.rom_ctrl_stress_all/latest |
| Test location | /workspace/coverage/default/40.rom_ctrl_alert_test.109076132 |
| Short name | T131 |
| Test name | |
| Test status | |
| Simulation time | 1817168731 ps |
| CPU time | 10.19 seconds |
| Started | May 12 01:06:16 PM PDT 24 |
| Finished | May 12 01:06:26 PM PDT 24 |
| Peak memory | 211524 kb |
| Host | smart-20bf1062-f06d-4216-96a3-a0c6b1d763a2 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=109076132 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_alert_test.109076132 |
| Directory | /workspace/40.rom_ctrl_alert_test/latest |
| Test location | /workspace/coverage/default/40.rom_ctrl_corrupt_sig_fatal_chk.1702920833 |
| Short name | T263 |
| Test name | |
| Test status | |
| Simulation time | 53486960389 ps |
| CPU time | 514.17 seconds |
| Started | May 12 01:06:17 PM PDT 24 |
| Finished | May 12 01:14:53 PM PDT 24 |
| Peak memory | 226108 kb |
| Host | smart-1e07f923-6f88-4f6f-a7cd-393e99c68e7b |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1702920833 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_ corrupt_sig_fatal_chk.1702920833 |
| Directory | /workspace/40.rom_ctrl_corrupt_sig_fatal_chk/latest |
| Test location | /workspace/coverage/default/40.rom_ctrl_kmac_err_chk.720184929 |
| Short name | T184 |
| Test name | |
| Test status | |
| Simulation time | 13701956863 ps |
| CPU time | 28.75 seconds |
| Started | May 12 01:06:17 PM PDT 24 |
| Finished | May 12 01:06:46 PM PDT 24 |
| Peak memory | 212592 kb |
| Host | smart-59c8abd5-45bd-4a86-b1e8-bed80e53bc2a |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=720184929 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_kmac_err_chk.720184929 |
| Directory | /workspace/40.rom_ctrl_kmac_err_chk/latest |
| Test location | /workspace/coverage/default/40.rom_ctrl_max_throughput_chk.3434790784 |
| Short name | T111 |
| Test name | |
| Test status | |
| Simulation time | 1501365317 ps |
| CPU time | 10.08 seconds |
| Started | May 12 01:06:16 PM PDT 24 |
| Finished | May 12 01:06:26 PM PDT 24 |
| Peak memory | 211536 kb |
| Host | smart-dc179848-baba-4131-824c-7cb2c1c48dd0 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3434790784 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_max_throughput_chk.3434790784 |
| Directory | /workspace/40.rom_ctrl_max_throughput_chk/latest |
| Test location | /workspace/coverage/default/40.rom_ctrl_smoke.3990791186 |
| Short name | T248 |
| Test name | |
| Test status | |
| Simulation time | 8260238377 ps |
| CPU time | 36.73 seconds |
| Started | May 12 01:06:18 PM PDT 24 |
| Finished | May 12 01:06:55 PM PDT 24 |
| Peak memory | 219936 kb |
| Host | smart-21b5d55a-a099-4495-b324-a3a78dec16d4 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3990791186 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_smoke.3990791186 |
| Directory | /workspace/40.rom_ctrl_smoke/latest |
| Test location | /workspace/coverage/default/40.rom_ctrl_stress_all.4088064556 |
| Short name | T11 |
| Test name | |
| Test status | |
| Simulation time | 591875865 ps |
| CPU time | 24.87 seconds |
| Started | May 12 01:06:18 PM PDT 24 |
| Finished | May 12 01:06:43 PM PDT 24 |
| Peak memory | 215524 kb |
| Host | smart-67d9bffb-c106-4260-8318-53fb0142faad |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4088064556 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm _name 40.rom_ctrl_stress_all.4088064556 |
| Directory | /workspace/40.rom_ctrl_stress_all/latest |
| Test location | /workspace/coverage/default/41.rom_ctrl_alert_test.1176368575 |
| Short name | T289 |
| Test name | |
| Test status | |
| Simulation time | 88882640 ps |
| CPU time | 4.37 seconds |
| Started | May 12 01:06:17 PM PDT 24 |
| Finished | May 12 01:06:22 PM PDT 24 |
| Peak memory | 211576 kb |
| Host | smart-f2db60d6-2ceb-4470-9a5c-f4b28be00b2a |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1176368575 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_alert_test.1176368575 |
| Directory | /workspace/41.rom_ctrl_alert_test/latest |
| Test location | /workspace/coverage/default/41.rom_ctrl_corrupt_sig_fatal_chk.1664124271 |
| Short name | T122 |
| Test name | |
| Test status | |
| Simulation time | 11812354673 ps |
| CPU time | 209.05 seconds |
| Started | May 12 01:06:16 PM PDT 24 |
| Finished | May 12 01:09:45 PM PDT 24 |
| Peak memory | 233620 kb |
| Host | smart-20ba7e63-9665-41fc-9446-43dd3dd41d46 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1664124271 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_ corrupt_sig_fatal_chk.1664124271 |
| Directory | /workspace/41.rom_ctrl_corrupt_sig_fatal_chk/latest |
| Test location | /workspace/coverage/default/41.rom_ctrl_kmac_err_chk.803997920 |
| Short name | T256 |
| Test name | |
| Test status | |
| Simulation time | 16606179486 ps |
| CPU time | 33.14 seconds |
| Started | May 12 01:06:18 PM PDT 24 |
| Finished | May 12 01:06:52 PM PDT 24 |
| Peak memory | 213144 kb |
| Host | smart-a9820c44-2ebb-45a1-ad4e-d2eb0981c734 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=803997920 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_kmac_err_chk.803997920 |
| Directory | /workspace/41.rom_ctrl_kmac_err_chk/latest |
| Test location | /workspace/coverage/default/41.rom_ctrl_max_throughput_chk.2182333162 |
| Short name | T136 |
| Test name | |
| Test status | |
| Simulation time | 2322116323 ps |
| CPU time | 9.69 seconds |
| Started | May 12 01:06:17 PM PDT 24 |
| Finished | May 12 01:06:27 PM PDT 24 |
| Peak memory | 211688 kb |
| Host | smart-e513ea24-cb75-491b-83b6-ce1064846bf1 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2182333162 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_max_throughput_chk.2182333162 |
| Directory | /workspace/41.rom_ctrl_max_throughput_chk/latest |
| Test location | /workspace/coverage/default/41.rom_ctrl_smoke.2473780690 |
| Short name | T265 |
| Test name | |
| Test status | |
| Simulation time | 14384428716 ps |
| CPU time | 34.6 seconds |
| Started | May 12 01:06:18 PM PDT 24 |
| Finished | May 12 01:06:53 PM PDT 24 |
| Peak memory | 219916 kb |
| Host | smart-f441ee83-a125-4a68-b77f-df6a12db0f82 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2473780690 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_smoke.2473780690 |
| Directory | /workspace/41.rom_ctrl_smoke/latest |
| Test location | /workspace/coverage/default/41.rom_ctrl_stress_all.2340119815 |
| Short name | T333 |
| Test name | |
| Test status | |
| Simulation time | 6288583089 ps |
| CPU time | 63.44 seconds |
| Started | May 12 01:06:15 PM PDT 24 |
| Finished | May 12 01:07:19 PM PDT 24 |
| Peak memory | 217200 kb |
| Host | smart-e16c6c2f-904e-4a32-926b-84a11d5e1570 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2340119815 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm _name 41.rom_ctrl_stress_all.2340119815 |
| Directory | /workspace/41.rom_ctrl_stress_all/latest |
| Test location | /workspace/coverage/default/42.rom_ctrl_alert_test.1959032521 |
| Short name | T255 |
| Test name | |
| Test status | |
| Simulation time | 607996248 ps |
| CPU time | 7.93 seconds |
| Started | May 12 01:06:21 PM PDT 24 |
| Finished | May 12 01:06:30 PM PDT 24 |
| Peak memory | 211640 kb |
| Host | smart-30a97be3-b8e4-47fb-b323-1ad460ae7fdf |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1959032521 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_alert_test.1959032521 |
| Directory | /workspace/42.rom_ctrl_alert_test/latest |
| Test location | /workspace/coverage/default/42.rom_ctrl_corrupt_sig_fatal_chk.4127140515 |
| Short name | T203 |
| Test name | |
| Test status | |
| Simulation time | 1445559951 ps |
| CPU time | 96.88 seconds |
| Started | May 12 01:06:22 PM PDT 24 |
| Finished | May 12 01:07:59 PM PDT 24 |
| Peak memory | 238084 kb |
| Host | smart-b92ec025-fe1e-4add-baf7-9bc84b55e29a |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4127140515 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_ corrupt_sig_fatal_chk.4127140515 |
| Directory | /workspace/42.rom_ctrl_corrupt_sig_fatal_chk/latest |
| Test location | /workspace/coverage/default/42.rom_ctrl_kmac_err_chk.760189757 |
| Short name | T121 |
| Test name | |
| Test status | |
| Simulation time | 2759177617 ps |
| CPU time | 25.82 seconds |
| Started | May 12 01:06:26 PM PDT 24 |
| Finished | May 12 01:06:52 PM PDT 24 |
| Peak memory | 212316 kb |
| Host | smart-92fb3260-c25f-4a48-add1-7c457b74bb15 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=760189757 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_kmac_err_chk.760189757 |
| Directory | /workspace/42.rom_ctrl_kmac_err_chk/latest |
| Test location | /workspace/coverage/default/42.rom_ctrl_max_throughput_chk.3381681397 |
| Short name | T91 |
| Test name | |
| Test status | |
| Simulation time | 2985764119 ps |
| CPU time | 14.01 seconds |
| Started | May 12 01:06:16 PM PDT 24 |
| Finished | May 12 01:06:30 PM PDT 24 |
| Peak memory | 211624 kb |
| Host | smart-e547922b-c4bc-49c6-a8bb-ee91f9b97ca2 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3381681397 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_max_throughput_chk.3381681397 |
| Directory | /workspace/42.rom_ctrl_max_throughput_chk/latest |
| Test location | /workspace/coverage/default/42.rom_ctrl_smoke.3986023691 |
| Short name | T5 |
| Test name | |
| Test status | |
| Simulation time | 7051179719 ps |
| CPU time | 35.66 seconds |
| Started | May 12 01:06:17 PM PDT 24 |
| Finished | May 12 01:06:53 PM PDT 24 |
| Peak memory | 219824 kb |
| Host | smart-1f487432-8513-4245-bb2c-b45f921aa8cb |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3986023691 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_smoke.3986023691 |
| Directory | /workspace/42.rom_ctrl_smoke/latest |
| Test location | /workspace/coverage/default/42.rom_ctrl_stress_all.3497905949 |
| Short name | T187 |
| Test name | |
| Test status | |
| Simulation time | 39378400801 ps |
| CPU time | 33.34 seconds |
| Started | May 12 01:06:18 PM PDT 24 |
| Finished | May 12 01:06:52 PM PDT 24 |
| Peak memory | 214636 kb |
| Host | smart-7a16f1cf-f681-4c83-aac3-50e0a03249c8 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3497905949 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm _name 42.rom_ctrl_stress_all.3497905949 |
| Directory | /workspace/42.rom_ctrl_stress_all/latest |
| Test location | /workspace/coverage/default/42.rom_ctrl_stress_all_with_rand_reset.4150131628 |
| Short name | T324 |
| Test name | |
| Test status | |
| Simulation time | 124393284559 ps |
| CPU time | 2369.91 seconds |
| Started | May 12 01:06:20 PM PDT 24 |
| Finished | May 12 01:45:51 PM PDT 24 |
| Peak memory | 239320 kb |
| Host | smart-37ef27d2-0907-4fba-bdf8-da2a75bdaab4 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4150131628 -assert nop ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_stress_all_with_rand_reset.4150131628 |
| Directory | /workspace/42.rom_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/43.rom_ctrl_alert_test.3982308102 |
| Short name | T118 |
| Test name | |
| Test status | |
| Simulation time | 3827350065 ps |
| CPU time | 8.64 seconds |
| Started | May 12 01:06:21 PM PDT 24 |
| Finished | May 12 01:06:31 PM PDT 24 |
| Peak memory | 211736 kb |
| Host | smart-c6acba10-99d7-4fcf-93ae-6002e24975cd |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3982308102 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_alert_test.3982308102 |
| Directory | /workspace/43.rom_ctrl_alert_test/latest |
| Test location | /workspace/coverage/default/43.rom_ctrl_corrupt_sig_fatal_chk.1579136216 |
| Short name | T317 |
| Test name | |
| Test status | |
| Simulation time | 196272549104 ps |
| CPU time | 437.31 seconds |
| Started | May 12 01:06:22 PM PDT 24 |
| Finished | May 12 01:13:40 PM PDT 24 |
| Peak memory | 234168 kb |
| Host | smart-a6bc2ad5-b848-4d1d-8a42-f4cff6d53f6a |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1579136216 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_ corrupt_sig_fatal_chk.1579136216 |
| Directory | /workspace/43.rom_ctrl_corrupt_sig_fatal_chk/latest |
| Test location | /workspace/coverage/default/43.rom_ctrl_kmac_err_chk.1505041389 |
| Short name | T325 |
| Test name | |
| Test status | |
| Simulation time | 3358855473 ps |
| CPU time | 30.34 seconds |
| Started | May 12 01:06:23 PM PDT 24 |
| Finished | May 12 01:06:54 PM PDT 24 |
| Peak memory | 212176 kb |
| Host | smart-ec85d97c-faf1-459c-8768-7c767e8594e8 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1505041389 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_kmac_err_chk.1505041389 |
| Directory | /workspace/43.rom_ctrl_kmac_err_chk/latest |
| Test location | /workspace/coverage/default/43.rom_ctrl_max_throughput_chk.2083863911 |
| Short name | T276 |
| Test name | |
| Test status | |
| Simulation time | 720524833 ps |
| CPU time | 10.2 seconds |
| Started | May 12 01:06:21 PM PDT 24 |
| Finished | May 12 01:06:31 PM PDT 24 |
| Peak memory | 211476 kb |
| Host | smart-1a64b135-2f20-4838-9ee0-8d35cdd30eaa |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2083863911 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_max_throughput_chk.2083863911 |
| Directory | /workspace/43.rom_ctrl_max_throughput_chk/latest |
| Test location | /workspace/coverage/default/43.rom_ctrl_smoke.1091316806 |
| Short name | T192 |
| Test name | |
| Test status | |
| Simulation time | 2680727100 ps |
| CPU time | 27.26 seconds |
| Started | May 12 01:06:21 PM PDT 24 |
| Finished | May 12 01:06:48 PM PDT 24 |
| Peak memory | 214192 kb |
| Host | smart-56f069a4-91b5-4e94-b331-6ea7735ff5c8 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1091316806 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_smoke.1091316806 |
| Directory | /workspace/43.rom_ctrl_smoke/latest |
| Test location | /workspace/coverage/default/43.rom_ctrl_stress_all.1576432656 |
| Short name | T331 |
| Test name | |
| Test status | |
| Simulation time | 4988315161 ps |
| CPU time | 50.26 seconds |
| Started | May 12 01:06:21 PM PDT 24 |
| Finished | May 12 01:07:12 PM PDT 24 |
| Peak memory | 217700 kb |
| Host | smart-ad5613e2-5d77-4cdb-bf43-3aaf95a50d7f |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1576432656 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm _name 43.rom_ctrl_stress_all.1576432656 |
| Directory | /workspace/43.rom_ctrl_stress_all/latest |
| Test location | /workspace/coverage/default/44.rom_ctrl_alert_test.3926587907 |
| Short name | T340 |
| Test name | |
| Test status | |
| Simulation time | 425374846 ps |
| CPU time | 7.24 seconds |
| Started | May 12 01:06:21 PM PDT 24 |
| Finished | May 12 01:06:29 PM PDT 24 |
| Peak memory | 211672 kb |
| Host | smart-ba4b2bf3-e66b-42b6-b137-fb534dc858f0 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3926587907 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_alert_test.3926587907 |
| Directory | /workspace/44.rom_ctrl_alert_test/latest |
| Test location | /workspace/coverage/default/44.rom_ctrl_corrupt_sig_fatal_chk.1010272050 |
| Short name | T29 |
| Test name | |
| Test status | |
| Simulation time | 40710482303 ps |
| CPU time | 425.71 seconds |
| Started | May 12 01:06:21 PM PDT 24 |
| Finished | May 12 01:13:27 PM PDT 24 |
| Peak memory | 231204 kb |
| Host | smart-35bf5ae7-731b-4a87-9c91-e49072ce77d9 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1010272050 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_ corrupt_sig_fatal_chk.1010272050 |
| Directory | /workspace/44.rom_ctrl_corrupt_sig_fatal_chk/latest |
| Test location | /workspace/coverage/default/44.rom_ctrl_kmac_err_chk.2127038986 |
| Short name | T212 |
| Test name | |
| Test status | |
| Simulation time | 3913534061 ps |
| CPU time | 32.18 seconds |
| Started | May 12 01:06:24 PM PDT 24 |
| Finished | May 12 01:06:57 PM PDT 24 |
| Peak memory | 212548 kb |
| Host | smart-6689bcd6-ecc1-4494-9a52-6869fdb5d9bd |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2127038986 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_kmac_err_chk.2127038986 |
| Directory | /workspace/44.rom_ctrl_kmac_err_chk/latest |
| Test location | /workspace/coverage/default/44.rom_ctrl_max_throughput_chk.363407490 |
| Short name | T293 |
| Test name | |
| Test status | |
| Simulation time | 1319798885 ps |
| CPU time | 13.54 seconds |
| Started | May 12 01:06:21 PM PDT 24 |
| Finished | May 12 01:06:35 PM PDT 24 |
| Peak memory | 211512 kb |
| Host | smart-9012cd03-7f79-44fe-84ee-918769292043 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=363407490 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_max_throughput_chk.363407490 |
| Directory | /workspace/44.rom_ctrl_max_throughput_chk/latest |
| Test location | /workspace/coverage/default/44.rom_ctrl_smoke.1293447337 |
| Short name | T70 |
| Test name | |
| Test status | |
| Simulation time | 191800393 ps |
| CPU time | 10.48 seconds |
| Started | May 12 01:06:23 PM PDT 24 |
| Finished | May 12 01:06:34 PM PDT 24 |
| Peak memory | 219828 kb |
| Host | smart-4a9908d8-fd0a-49fd-9062-4cf2b1c82b86 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1293447337 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_smoke.1293447337 |
| Directory | /workspace/44.rom_ctrl_smoke/latest |
| Test location | /workspace/coverage/default/45.rom_ctrl_alert_test.2619295661 |
| Short name | T54 |
| Test name | |
| Test status | |
| Simulation time | 1614590470 ps |
| CPU time | 13.54 seconds |
| Started | May 12 01:06:27 PM PDT 24 |
| Finished | May 12 01:06:41 PM PDT 24 |
| Peak memory | 211576 kb |
| Host | smart-d8c0dd61-6448-4e05-8e5d-4b87a6be49f3 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2619295661 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_alert_test.2619295661 |
| Directory | /workspace/45.rom_ctrl_alert_test/latest |
| Test location | /workspace/coverage/default/45.rom_ctrl_corrupt_sig_fatal_chk.920842568 |
| Short name | T24 |
| Test name | |
| Test status | |
| Simulation time | 74387421916 ps |
| CPU time | 194.04 seconds |
| Started | May 12 01:06:31 PM PDT 24 |
| Finished | May 12 01:09:46 PM PDT 24 |
| Peak memory | 231228 kb |
| Host | smart-ad8e283b-8840-4fde-bb50-a68d9b2871e2 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=920842568 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt _sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_c orrupt_sig_fatal_chk.920842568 |
| Directory | /workspace/45.rom_ctrl_corrupt_sig_fatal_chk/latest |
| Test location | /workspace/coverage/default/45.rom_ctrl_kmac_err_chk.742225727 |
| Short name | T193 |
| Test name | |
| Test status | |
| Simulation time | 1645891440 ps |
| CPU time | 15.1 seconds |
| Started | May 12 01:06:31 PM PDT 24 |
| Finished | May 12 01:06:47 PM PDT 24 |
| Peak memory | 212628 kb |
| Host | smart-9ff67ce4-bf27-47f3-a566-bd78e612946a |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=742225727 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_kmac_err_chk.742225727 |
| Directory | /workspace/45.rom_ctrl_kmac_err_chk/latest |
| Test location | /workspace/coverage/default/45.rom_ctrl_max_throughput_chk.3744337907 |
| Short name | T297 |
| Test name | |
| Test status | |
| Simulation time | 1002817821 ps |
| CPU time | 11.23 seconds |
| Started | May 12 01:06:30 PM PDT 24 |
| Finished | May 12 01:06:42 PM PDT 24 |
| Peak memory | 211552 kb |
| Host | smart-545e2f78-473f-4328-a411-cfb618d62791 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3744337907 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_max_throughput_chk.3744337907 |
| Directory | /workspace/45.rom_ctrl_max_throughput_chk/latest |
| Test location | /workspace/coverage/default/45.rom_ctrl_smoke.2345931618 |
| Short name | T311 |
| Test name | |
| Test status | |
| Simulation time | 5872916335 ps |
| CPU time | 33.22 seconds |
| Started | May 12 01:06:23 PM PDT 24 |
| Finished | May 12 01:06:56 PM PDT 24 |
| Peak memory | 214392 kb |
| Host | smart-a96d162e-4336-44bf-be03-43332e15dc10 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2345931618 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_smoke.2345931618 |
| Directory | /workspace/45.rom_ctrl_smoke/latest |
| Test location | /workspace/coverage/default/45.rom_ctrl_stress_all.1286774336 |
| Short name | T226 |
| Test name | |
| Test status | |
| Simulation time | 663475595 ps |
| CPU time | 11.16 seconds |
| Started | May 12 01:06:27 PM PDT 24 |
| Finished | May 12 01:06:39 PM PDT 24 |
| Peak memory | 212372 kb |
| Host | smart-70639327-fa78-48bc-b28f-d478d02f79a2 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1286774336 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm _name 45.rom_ctrl_stress_all.1286774336 |
| Directory | /workspace/45.rom_ctrl_stress_all/latest |
| Test location | /workspace/coverage/default/46.rom_ctrl_alert_test.1930713754 |
| Short name | T339 |
| Test name | |
| Test status | |
| Simulation time | 1122338792 ps |
| CPU time | 11.2 seconds |
| Started | May 12 01:06:28 PM PDT 24 |
| Finished | May 12 01:06:40 PM PDT 24 |
| Peak memory | 211632 kb |
| Host | smart-d2caeb15-03e6-4805-a81e-f2eafd50e776 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1930713754 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_alert_test.1930713754 |
| Directory | /workspace/46.rom_ctrl_alert_test/latest |
| Test location | /workspace/coverage/default/46.rom_ctrl_corrupt_sig_fatal_chk.49077179 |
| Short name | T356 |
| Test name | |
| Test status | |
| Simulation time | 86569681003 ps |
| CPU time | 218.49 seconds |
| Started | May 12 01:06:30 PM PDT 24 |
| Finished | May 12 01:10:10 PM PDT 24 |
| Peak memory | 213020 kb |
| Host | smart-65fe8f3b-285e-49b7-b3f1-f124271c49ad |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49077179 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_ sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_co rrupt_sig_fatal_chk.49077179 |
| Directory | /workspace/46.rom_ctrl_corrupt_sig_fatal_chk/latest |
| Test location | /workspace/coverage/default/46.rom_ctrl_kmac_err_chk.2874742254 |
| Short name | T21 |
| Test name | |
| Test status | |
| Simulation time | 3873200322 ps |
| CPU time | 32.09 seconds |
| Started | May 12 01:06:28 PM PDT 24 |
| Finished | May 12 01:07:01 PM PDT 24 |
| Peak memory | 212216 kb |
| Host | smart-8552716c-e6e6-405e-be4f-0541614b655b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2874742254 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_kmac_err_chk.2874742254 |
| Directory | /workspace/46.rom_ctrl_kmac_err_chk/latest |
| Test location | /workspace/coverage/default/46.rom_ctrl_max_throughput_chk.352905700 |
| Short name | T135 |
| Test name | |
| Test status | |
| Simulation time | 771823560 ps |
| CPU time | 8.42 seconds |
| Started | May 12 01:06:29 PM PDT 24 |
| Finished | May 12 01:06:38 PM PDT 24 |
| Peak memory | 211528 kb |
| Host | smart-8e0be67f-253e-4da7-a3b8-5d1a35c4fdb1 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=352905700 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_max_throughput_chk.352905700 |
| Directory | /workspace/46.rom_ctrl_max_throughput_chk/latest |
| Test location | /workspace/coverage/default/46.rom_ctrl_smoke.2236853175 |
| Short name | T343 |
| Test name | |
| Test status | |
| Simulation time | 1863330338 ps |
| CPU time | 22.19 seconds |
| Started | May 12 01:06:29 PM PDT 24 |
| Finished | May 12 01:06:52 PM PDT 24 |
| Peak memory | 213384 kb |
| Host | smart-60c55aef-409d-4593-82c0-e70f34f52b29 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2236853175 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_smoke.2236853175 |
| Directory | /workspace/46.rom_ctrl_smoke/latest |
| Test location | /workspace/coverage/default/46.rom_ctrl_stress_all.2657357451 |
| Short name | T110 |
| Test name | |
| Test status | |
| Simulation time | 6350823408 ps |
| CPU time | 15.09 seconds |
| Started | May 12 01:06:28 PM PDT 24 |
| Finished | May 12 01:06:44 PM PDT 24 |
| Peak memory | 212284 kb |
| Host | smart-37c7182b-5c63-49dd-b785-93b228118d13 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2657357451 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm _name 46.rom_ctrl_stress_all.2657357451 |
| Directory | /workspace/46.rom_ctrl_stress_all/latest |
| Test location | /workspace/coverage/default/47.rom_ctrl_alert_test.3499904557 |
| Short name | T352 |
| Test name | |
| Test status | |
| Simulation time | 846976734 ps |
| CPU time | 6.6 seconds |
| Started | May 12 01:06:31 PM PDT 24 |
| Finished | May 12 01:06:39 PM PDT 24 |
| Peak memory | 211556 kb |
| Host | smart-6f134941-7265-40d7-a61b-6628ed44729d |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3499904557 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_alert_test.3499904557 |
| Directory | /workspace/47.rom_ctrl_alert_test/latest |
| Test location | /workspace/coverage/default/47.rom_ctrl_corrupt_sig_fatal_chk.1146526280 |
| Short name | T216 |
| Test name | |
| Test status | |
| Simulation time | 2031438587 ps |
| CPU time | 140.76 seconds |
| Started | May 12 01:06:26 PM PDT 24 |
| Finished | May 12 01:08:47 PM PDT 24 |
| Peak memory | 229400 kb |
| Host | smart-215423b5-8766-43af-934c-ce963356a399 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1146526280 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_ corrupt_sig_fatal_chk.1146526280 |
| Directory | /workspace/47.rom_ctrl_corrupt_sig_fatal_chk/latest |
| Test location | /workspace/coverage/default/47.rom_ctrl_kmac_err_chk.3709905824 |
| Short name | T353 |
| Test name | |
| Test status | |
| Simulation time | 2058108369 ps |
| CPU time | 13.39 seconds |
| Started | May 12 01:06:27 PM PDT 24 |
| Finished | May 12 01:06:41 PM PDT 24 |
| Peak memory | 212100 kb |
| Host | smart-5065aa49-fbf6-42a8-8824-aa8659dacd4d |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3709905824 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_kmac_err_chk.3709905824 |
| Directory | /workspace/47.rom_ctrl_kmac_err_chk/latest |
| Test location | /workspace/coverage/default/47.rom_ctrl_max_throughput_chk.681986987 |
| Short name | T277 |
| Test name | |
| Test status | |
| Simulation time | 994992946 ps |
| CPU time | 11.68 seconds |
| Started | May 12 01:06:29 PM PDT 24 |
| Finished | May 12 01:06:42 PM PDT 24 |
| Peak memory | 211504 kb |
| Host | smart-6b10ddfc-b05a-4651-91a4-3d1ca6b928ff |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=681986987 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_max_throughput_chk.681986987 |
| Directory | /workspace/47.rom_ctrl_max_throughput_chk/latest |
| Test location | /workspace/coverage/default/47.rom_ctrl_stress_all.2403580334 |
| Short name | T208 |
| Test name | |
| Test status | |
| Simulation time | 22266140249 ps |
| CPU time | 39.63 seconds |
| Started | May 12 01:06:28 PM PDT 24 |
| Finished | May 12 01:07:08 PM PDT 24 |
| Peak memory | 214500 kb |
| Host | smart-c073a151-8ee7-4297-a16d-0e49e14303d8 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2403580334 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm _name 47.rom_ctrl_stress_all.2403580334 |
| Directory | /workspace/47.rom_ctrl_stress_all/latest |
| Test location | /workspace/coverage/default/47.rom_ctrl_stress_all_with_rand_reset.1461594058 |
| Short name | T43 |
| Test name | |
| Test status | |
| Simulation time | 65764261686 ps |
| CPU time | 1282.77 seconds |
| Started | May 12 01:06:27 PM PDT 24 |
| Finished | May 12 01:27:51 PM PDT 24 |
| Peak memory | 236644 kb |
| Host | smart-b2d6e262-4870-4b56-b529-51a27d57c328 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1461594058 -assert nop ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_stress_all_with_rand_reset.1461594058 |
| Directory | /workspace/47.rom_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/48.rom_ctrl_alert_test.32995821 |
| Short name | T207 |
| Test name | |
| Test status | |
| Simulation time | 238584843 ps |
| CPU time | 4.31 seconds |
| Started | May 12 01:06:28 PM PDT 24 |
| Finished | May 12 01:06:33 PM PDT 24 |
| Peak memory | 211692 kb |
| Host | smart-a0276461-9a91-4f7b-b117-44b8b6554d11 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32995821 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_alert_test.32995821 |
| Directory | /workspace/48.rom_ctrl_alert_test/latest |
| Test location | /workspace/coverage/default/48.rom_ctrl_corrupt_sig_fatal_chk.86624996 |
| Short name | T108 |
| Test name | |
| Test status | |
| Simulation time | 8099452513 ps |
| CPU time | 93.33 seconds |
| Started | May 12 01:06:29 PM PDT 24 |
| Finished | May 12 01:08:03 PM PDT 24 |
| Peak memory | 238348 kb |
| Host | smart-4c86f974-20ff-453c-bc73-64a063950d38 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86624996 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_ sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_co rrupt_sig_fatal_chk.86624996 |
| Directory | /workspace/48.rom_ctrl_corrupt_sig_fatal_chk/latest |
| Test location | /workspace/coverage/default/48.rom_ctrl_kmac_err_chk.3153238658 |
| Short name | T202 |
| Test name | |
| Test status | |
| Simulation time | 692357690 ps |
| CPU time | 9.54 seconds |
| Started | May 12 01:06:27 PM PDT 24 |
| Finished | May 12 01:06:38 PM PDT 24 |
| Peak memory | 212164 kb |
| Host | smart-4ec6403a-40d5-44d2-a0c4-21ecdf3721ff |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3153238658 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_kmac_err_chk.3153238658 |
| Directory | /workspace/48.rom_ctrl_kmac_err_chk/latest |
| Test location | /workspace/coverage/default/48.rom_ctrl_max_throughput_chk.3053676498 |
| Short name | T278 |
| Test name | |
| Test status | |
| Simulation time | 6473446004 ps |
| CPU time | 13.32 seconds |
| Started | May 12 01:06:28 PM PDT 24 |
| Finished | May 12 01:06:42 PM PDT 24 |
| Peak memory | 211588 kb |
| Host | smart-cfbfbbc4-5cbe-4b21-a5db-74eb016c1f41 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3053676498 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_max_throughput_chk.3053676498 |
| Directory | /workspace/48.rom_ctrl_max_throughput_chk/latest |
| Test location | /workspace/coverage/default/48.rom_ctrl_smoke.1478641419 |
| Short name | T211 |
| Test name | |
| Test status | |
| Simulation time | 3935197835 ps |
| CPU time | 40.3 seconds |
| Started | May 12 01:06:26 PM PDT 24 |
| Finished | May 12 01:07:07 PM PDT 24 |
| Peak memory | 213836 kb |
| Host | smart-cad3f03a-b08e-4418-ae0f-21d467f26a3d |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1478641419 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_smoke.1478641419 |
| Directory | /workspace/48.rom_ctrl_smoke/latest |
| Test location | /workspace/coverage/default/48.rom_ctrl_stress_all.2780472349 |
| Short name | T329 |
| Test name | |
| Test status | |
| Simulation time | 10815864508 ps |
| CPU time | 26.78 seconds |
| Started | May 12 01:06:31 PM PDT 24 |
| Finished | May 12 01:06:59 PM PDT 24 |
| Peak memory | 215032 kb |
| Host | smart-95b58109-6530-47a3-b7af-3b6bb3eebedf |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2780472349 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm _name 48.rom_ctrl_stress_all.2780472349 |
| Directory | /workspace/48.rom_ctrl_stress_all/latest |
| Test location | /workspace/coverage/default/48.rom_ctrl_stress_all_with_rand_reset.1474201924 |
| Short name | T47 |
| Test name | |
| Test status | |
| Simulation time | 120717707081 ps |
| CPU time | 1927.57 seconds |
| Started | May 12 01:06:31 PM PDT 24 |
| Finished | May 12 01:38:39 PM PDT 24 |
| Peak memory | 231984 kb |
| Host | smart-19c30d6e-15a2-4e54-94a1-918c784d18e7 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1474201924 -assert nop ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_stress_all_with_rand_reset.1474201924 |
| Directory | /workspace/48.rom_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/49.rom_ctrl_alert_test.148239563 |
| Short name | T272 |
| Test name | |
| Test status | |
| Simulation time | 1470171279 ps |
| CPU time | 12.59 seconds |
| Started | May 12 01:06:31 PM PDT 24 |
| Finished | May 12 01:06:45 PM PDT 24 |
| Peak memory | 211692 kb |
| Host | smart-d131ed6a-80f4-43c7-b4fc-30bbdd95aa07 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=148239563 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_alert_test.148239563 |
| Directory | /workspace/49.rom_ctrl_alert_test/latest |
| Test location | /workspace/coverage/default/49.rom_ctrl_corrupt_sig_fatal_chk.1894393372 |
| Short name | T252 |
| Test name | |
| Test status | |
| Simulation time | 60624158132 ps |
| CPU time | 321.69 seconds |
| Started | May 12 01:06:34 PM PDT 24 |
| Finished | May 12 01:11:56 PM PDT 24 |
| Peak memory | 220036 kb |
| Host | smart-d8f7e44d-38bb-41ab-8f55-09eb41d05a10 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1894393372 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_ corrupt_sig_fatal_chk.1894393372 |
| Directory | /workspace/49.rom_ctrl_corrupt_sig_fatal_chk/latest |
| Test location | /workspace/coverage/default/49.rom_ctrl_kmac_err_chk.4285280024 |
| Short name | T22 |
| Test name | |
| Test status | |
| Simulation time | 16390415587 ps |
| CPU time | 32.86 seconds |
| Started | May 12 01:06:34 PM PDT 24 |
| Finished | May 12 01:07:07 PM PDT 24 |
| Peak memory | 213132 kb |
| Host | smart-838dfb06-d32a-4b35-a1dc-bddb061436d8 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4285280024 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_kmac_err_chk.4285280024 |
| Directory | /workspace/49.rom_ctrl_kmac_err_chk/latest |
| Test location | /workspace/coverage/default/49.rom_ctrl_max_throughput_chk.2693425737 |
| Short name | T117 |
| Test name | |
| Test status | |
| Simulation time | 2343985503 ps |
| CPU time | 12.55 seconds |
| Started | May 12 01:06:32 PM PDT 24 |
| Finished | May 12 01:06:45 PM PDT 24 |
| Peak memory | 211736 kb |
| Host | smart-93d82122-bda9-49c9-8e95-ebc8a72c2e88 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2693425737 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_max_throughput_chk.2693425737 |
| Directory | /workspace/49.rom_ctrl_max_throughput_chk/latest |
| Test location | /workspace/coverage/default/49.rom_ctrl_smoke.822999175 |
| Short name | T217 |
| Test name | |
| Test status | |
| Simulation time | 706670260 ps |
| CPU time | 14.6 seconds |
| Started | May 12 01:06:30 PM PDT 24 |
| Finished | May 12 01:06:45 PM PDT 24 |
| Peak memory | 212304 kb |
| Host | smart-213ae852-d066-46be-bc8c-26fb460f5d6b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=822999175 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_smoke.822999175 |
| Directory | /workspace/49.rom_ctrl_smoke/latest |
| Test location | /workspace/coverage/default/49.rom_ctrl_stress_all.3403989696 |
| Short name | T271 |
| Test name | |
| Test status | |
| Simulation time | 269405421 ps |
| CPU time | 6.85 seconds |
| Started | May 12 01:06:30 PM PDT 24 |
| Finished | May 12 01:06:38 PM PDT 24 |
| Peak memory | 211532 kb |
| Host | smart-a92fc228-f796-40ed-9612-bdb55404c1ed |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3403989696 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm _name 49.rom_ctrl_stress_all.3403989696 |
| Directory | /workspace/49.rom_ctrl_stress_all/latest |
| Test location | /workspace/coverage/default/49.rom_ctrl_stress_all_with_rand_reset.243205552 |
| Short name | T42 |
| Test name | |
| Test status | |
| Simulation time | 43782349739 ps |
| CPU time | 908.15 seconds |
| Started | May 12 01:06:33 PM PDT 24 |
| Finished | May 12 01:21:42 PM PDT 24 |
| Peak memory | 236288 kb |
| Host | smart-3233aea3-b7c2-4f79-8f73-d6010387324b |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=243205552 -assert nopo stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera ge/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_stress_all_with_rand_reset.243205552 |
| Directory | /workspace/49.rom_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/5.rom_ctrl_alert_test.2691355464 |
| Short name | T349 |
| Test name | |
| Test status | |
| Simulation time | 167981108 ps |
| CPU time | 4.32 seconds |
| Started | May 12 01:05:25 PM PDT 24 |
| Finished | May 12 01:05:30 PM PDT 24 |
| Peak memory | 211684 kb |
| Host | smart-a2319eac-0b7d-44b1-97d3-cbfb827d6f25 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2691355464 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_alert_test.2691355464 |
| Directory | /workspace/5.rom_ctrl_alert_test/latest |
| Test location | /workspace/coverage/default/5.rom_ctrl_corrupt_sig_fatal_chk.2920655811 |
| Short name | T199 |
| Test name | |
| Test status | |
| Simulation time | 21589741523 ps |
| CPU time | 136.42 seconds |
| Started | May 12 01:05:26 PM PDT 24 |
| Finished | May 12 01:07:42 PM PDT 24 |
| Peak memory | 238216 kb |
| Host | smart-35c63870-4029-4e0a-b84d-facb32586730 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2920655811 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_c orrupt_sig_fatal_chk.2920655811 |
| Directory | /workspace/5.rom_ctrl_corrupt_sig_fatal_chk/latest |
| Test location | /workspace/coverage/default/5.rom_ctrl_kmac_err_chk.3424252260 |
| Short name | T287 |
| Test name | |
| Test status | |
| Simulation time | 18959635214 ps |
| CPU time | 33.1 seconds |
| Started | May 12 01:05:23 PM PDT 24 |
| Finished | May 12 01:05:57 PM PDT 24 |
| Peak memory | 212756 kb |
| Host | smart-490dbd85-7164-4345-9270-f2742915f0dd |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3424252260 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_kmac_err_chk.3424252260 |
| Directory | /workspace/5.rom_ctrl_kmac_err_chk/latest |
| Test location | /workspace/coverage/default/5.rom_ctrl_max_throughput_chk.5830903 |
| Short name | T162 |
| Test name | |
| Test status | |
| Simulation time | 98847221 ps |
| CPU time | 5.43 seconds |
| Started | May 12 01:05:24 PM PDT 24 |
| Finished | May 12 01:05:31 PM PDT 24 |
| Peak memory | 211508 kb |
| Host | smart-fe1eae89-921f-46ca-aaaa-a11706874ceb |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=5830903 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_max_throughput_chk.5830903 |
| Directory | /workspace/5.rom_ctrl_max_throughput_chk/latest |
| Test location | /workspace/coverage/default/5.rom_ctrl_smoke.2563167367 |
| Short name | T213 |
| Test name | |
| Test status | |
| Simulation time | 375031761 ps |
| CPU time | 10.26 seconds |
| Started | May 12 01:05:26 PM PDT 24 |
| Finished | May 12 01:05:37 PM PDT 24 |
| Peak memory | 213428 kb |
| Host | smart-525813a1-fb81-4277-87e6-b86a0a1a6ab4 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2563167367 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_smoke.2563167367 |
| Directory | /workspace/5.rom_ctrl_smoke/latest |
| Test location | /workspace/coverage/default/6.rom_ctrl_alert_test.2521895558 |
| Short name | T299 |
| Test name | |
| Test status | |
| Simulation time | 4278321435 ps |
| CPU time | 17.79 seconds |
| Started | May 12 01:05:25 PM PDT 24 |
| Finished | May 12 01:05:43 PM PDT 24 |
| Peak memory | 211668 kb |
| Host | smart-928f6483-4e89-43aa-9c36-50aacf80d366 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2521895558 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_alert_test.2521895558 |
| Directory | /workspace/6.rom_ctrl_alert_test/latest |
| Test location | /workspace/coverage/default/6.rom_ctrl_corrupt_sig_fatal_chk.323882148 |
| Short name | T201 |
| Test name | |
| Test status | |
| Simulation time | 60543739273 ps |
| CPU time | 182.75 seconds |
| Started | May 12 01:05:24 PM PDT 24 |
| Finished | May 12 01:08:27 PM PDT 24 |
| Peak memory | 233576 kb |
| Host | smart-c57ba542-18e1-48d9-8fb5-8cf9a2bba1c0 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=323882148 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt _sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_co rrupt_sig_fatal_chk.323882148 |
| Directory | /workspace/6.rom_ctrl_corrupt_sig_fatal_chk/latest |
| Test location | /workspace/coverage/default/6.rom_ctrl_kmac_err_chk.771376060 |
| Short name | T3 |
| Test name | |
| Test status | |
| Simulation time | 10198185077 ps |
| CPU time | 24.06 seconds |
| Started | May 12 01:05:24 PM PDT 24 |
| Finished | May 12 01:05:49 PM PDT 24 |
| Peak memory | 212708 kb |
| Host | smart-42483951-4450-4e13-80f9-0dd40b4259e6 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=771376060 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_kmac_err_chk.771376060 |
| Directory | /workspace/6.rom_ctrl_kmac_err_chk/latest |
| Test location | /workspace/coverage/default/6.rom_ctrl_max_throughput_chk.1558005964 |
| Short name | T10 |
| Test name | |
| Test status | |
| Simulation time | 2231801173 ps |
| CPU time | 17.62 seconds |
| Started | May 12 01:05:24 PM PDT 24 |
| Finished | May 12 01:05:43 PM PDT 24 |
| Peak memory | 211608 kb |
| Host | smart-32ada97f-8086-4064-975a-f5194b673a37 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1558005964 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_max_throughput_chk.1558005964 |
| Directory | /workspace/6.rom_ctrl_max_throughput_chk/latest |
| Test location | /workspace/coverage/default/6.rom_ctrl_smoke.945970853 |
| Short name | T93 |
| Test name | |
| Test status | |
| Simulation time | 2262782589 ps |
| CPU time | 20.78 seconds |
| Started | May 12 01:05:26 PM PDT 24 |
| Finished | May 12 01:05:47 PM PDT 24 |
| Peak memory | 213444 kb |
| Host | smart-833524e1-201e-4baa-acb7-a7c46effa9a3 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=945970853 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_smoke.945970853 |
| Directory | /workspace/6.rom_ctrl_smoke/latest |
| Test location | /workspace/coverage/default/6.rom_ctrl_stress_all.1370462626 |
| Short name | T222 |
| Test name | |
| Test status | |
| Simulation time | 4583824727 ps |
| CPU time | 15.56 seconds |
| Started | May 12 01:05:24 PM PDT 24 |
| Finished | May 12 01:05:40 PM PDT 24 |
| Peak memory | 212500 kb |
| Host | smart-de04907e-9237-4139-9c6e-32c1cacba00a |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1370462626 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm _name 6.rom_ctrl_stress_all.1370462626 |
| Directory | /workspace/6.rom_ctrl_stress_all/latest |
| Test location | /workspace/coverage/default/7.rom_ctrl_alert_test.1631184004 |
| Short name | T186 |
| Test name | |
| Test status | |
| Simulation time | 2551116915 ps |
| CPU time | 16.5 seconds |
| Started | May 12 01:05:24 PM PDT 24 |
| Finished | May 12 01:05:42 PM PDT 24 |
| Peak memory | 211764 kb |
| Host | smart-e5531e39-95b9-4d70-b8f7-85166563c7bf |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1631184004 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_alert_test.1631184004 |
| Directory | /workspace/7.rom_ctrl_alert_test/latest |
| Test location | /workspace/coverage/default/7.rom_ctrl_corrupt_sig_fatal_chk.2021279272 |
| Short name | T346 |
| Test name | |
| Test status | |
| Simulation time | 33917653636 ps |
| CPU time | 130.06 seconds |
| Started | May 12 01:05:24 PM PDT 24 |
| Finished | May 12 01:07:35 PM PDT 24 |
| Peak memory | 233260 kb |
| Host | smart-6b81cc80-3b67-4626-ba0a-43cdf11ee6a0 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2021279272 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_c orrupt_sig_fatal_chk.2021279272 |
| Directory | /workspace/7.rom_ctrl_corrupt_sig_fatal_chk/latest |
| Test location | /workspace/coverage/default/7.rom_ctrl_kmac_err_chk.3714255898 |
| Short name | T112 |
| Test name | |
| Test status | |
| Simulation time | 1872077667 ps |
| CPU time | 17.96 seconds |
| Started | May 12 01:05:23 PM PDT 24 |
| Finished | May 12 01:05:41 PM PDT 24 |
| Peak memory | 212288 kb |
| Host | smart-e62f270e-48ee-43be-b70d-49f846503cd9 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3714255898 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_kmac_err_chk.3714255898 |
| Directory | /workspace/7.rom_ctrl_kmac_err_chk/latest |
| Test location | /workspace/coverage/default/7.rom_ctrl_max_throughput_chk.2729092219 |
| Short name | T244 |
| Test name | |
| Test status | |
| Simulation time | 135539693 ps |
| CPU time | 6.36 seconds |
| Started | May 12 01:05:26 PM PDT 24 |
| Finished | May 12 01:05:33 PM PDT 24 |
| Peak memory | 211508 kb |
| Host | smart-51b3f24d-e785-49b7-a04c-340cdb9771aa |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2729092219 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_max_throughput_chk.2729092219 |
| Directory | /workspace/7.rom_ctrl_max_throughput_chk/latest |
| Test location | /workspace/coverage/default/7.rom_ctrl_smoke.124368636 |
| Short name | T134 |
| Test name | |
| Test status | |
| Simulation time | 2324764359 ps |
| CPU time | 25.92 seconds |
| Started | May 12 01:05:24 PM PDT 24 |
| Finished | May 12 01:05:50 PM PDT 24 |
| Peak memory | 213584 kb |
| Host | smart-a4ea1325-9874-4f83-accf-90de7ae7444f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=124368636 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_smoke.124368636 |
| Directory | /workspace/7.rom_ctrl_smoke/latest |
| Test location | /workspace/coverage/default/7.rom_ctrl_stress_all.2211018188 |
| Short name | T347 |
| Test name | |
| Test status | |
| Simulation time | 4042120233 ps |
| CPU time | 13.42 seconds |
| Started | May 12 01:05:25 PM PDT 24 |
| Finished | May 12 01:05:39 PM PDT 24 |
| Peak memory | 211808 kb |
| Host | smart-0e7671ab-8990-4845-9a74-21d103c66cd3 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2211018188 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm _name 7.rom_ctrl_stress_all.2211018188 |
| Directory | /workspace/7.rom_ctrl_stress_all/latest |
| Test location | /workspace/coverage/default/8.rom_ctrl_alert_test.3095029485 |
| Short name | T227 |
| Test name | |
| Test status | |
| Simulation time | 637835904 ps |
| CPU time | 4.3 seconds |
| Started | May 12 01:05:35 PM PDT 24 |
| Finished | May 12 01:05:39 PM PDT 24 |
| Peak memory | 211844 kb |
| Host | smart-b88e5256-b90f-447f-8202-d7f5ddcb8acb |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3095029485 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_alert_test.3095029485 |
| Directory | /workspace/8.rom_ctrl_alert_test/latest |
| Test location | /workspace/coverage/default/8.rom_ctrl_corrupt_sig_fatal_chk.927388923 |
| Short name | T175 |
| Test name | |
| Test status | |
| Simulation time | 188646982352 ps |
| CPU time | 459.29 seconds |
| Started | May 12 01:05:32 PM PDT 24 |
| Finished | May 12 01:13:11 PM PDT 24 |
| Peak memory | 237144 kb |
| Host | smart-9d6db401-e8f9-4047-af8c-da37ef206a50 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=927388923 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt _sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_co rrupt_sig_fatal_chk.927388923 |
| Directory | /workspace/8.rom_ctrl_corrupt_sig_fatal_chk/latest |
| Test location | /workspace/coverage/default/8.rom_ctrl_kmac_err_chk.2500646105 |
| Short name | T322 |
| Test name | |
| Test status | |
| Simulation time | 8655782320 ps |
| CPU time | 27.77 seconds |
| Started | May 12 01:05:30 PM PDT 24 |
| Finished | May 12 01:05:58 PM PDT 24 |
| Peak memory | 212732 kb |
| Host | smart-ef7885c9-9ea0-4ddf-8c7a-4fe8fa2286cb |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2500646105 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_kmac_err_chk.2500646105 |
| Directory | /workspace/8.rom_ctrl_kmac_err_chk/latest |
| Test location | /workspace/coverage/default/8.rom_ctrl_max_throughput_chk.3246695613 |
| Short name | T229 |
| Test name | |
| Test status | |
| Simulation time | 3132351612 ps |
| CPU time | 11.44 seconds |
| Started | May 12 01:05:24 PM PDT 24 |
| Finished | May 12 01:05:37 PM PDT 24 |
| Peak memory | 211960 kb |
| Host | smart-a649c313-1fd3-4965-950d-9d6c1ab17767 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3246695613 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_max_throughput_chk.3246695613 |
| Directory | /workspace/8.rom_ctrl_max_throughput_chk/latest |
| Test location | /workspace/coverage/default/8.rom_ctrl_smoke.3573761837 |
| Short name | T250 |
| Test name | |
| Test status | |
| Simulation time | 701949950 ps |
| CPU time | 14.89 seconds |
| Started | May 12 01:05:24 PM PDT 24 |
| Finished | May 12 01:05:39 PM PDT 24 |
| Peak memory | 219776 kb |
| Host | smart-b976981b-13ab-4a27-9cd3-155be3dc7e67 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3573761837 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_smoke.3573761837 |
| Directory | /workspace/8.rom_ctrl_smoke/latest |
| Test location | /workspace/coverage/default/8.rom_ctrl_stress_all.4234163756 |
| Short name | T242 |
| Test name | |
| Test status | |
| Simulation time | 7139796351 ps |
| CPU time | 67.07 seconds |
| Started | May 12 01:05:29 PM PDT 24 |
| Finished | May 12 01:06:37 PM PDT 24 |
| Peak memory | 217532 kb |
| Host | smart-6dfc62ef-2ea1-428d-9f67-d2ce32a4b1b9 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4234163756 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm _name 8.rom_ctrl_stress_all.4234163756 |
| Directory | /workspace/8.rom_ctrl_stress_all/latest |
| Test location | /workspace/coverage/default/9.rom_ctrl_alert_test.4029560391 |
| Short name | T231 |
| Test name | |
| Test status | |
| Simulation time | 5798556956 ps |
| CPU time | 11.49 seconds |
| Started | May 12 01:05:29 PM PDT 24 |
| Finished | May 12 01:05:41 PM PDT 24 |
| Peak memory | 211740 kb |
| Host | smart-98dfd443-40e0-4e7f-82e5-dd3b883e86f4 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4029560391 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_alert_test.4029560391 |
| Directory | /workspace/9.rom_ctrl_alert_test/latest |
| Test location | /workspace/coverage/default/9.rom_ctrl_corrupt_sig_fatal_chk.3402112742 |
| Short name | T319 |
| Test name | |
| Test status | |
| Simulation time | 87131354645 ps |
| CPU time | 228.73 seconds |
| Started | May 12 01:05:28 PM PDT 24 |
| Finished | May 12 01:09:17 PM PDT 24 |
| Peak memory | 238320 kb |
| Host | smart-a710b97d-5af3-4d55-afc8-53b94d06a4c8 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3402112742 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_c orrupt_sig_fatal_chk.3402112742 |
| Directory | /workspace/9.rom_ctrl_corrupt_sig_fatal_chk/latest |
| Test location | /workspace/coverage/default/9.rom_ctrl_kmac_err_chk.1155919011 |
| Short name | T114 |
| Test name | |
| Test status | |
| Simulation time | 12012401984 ps |
| CPU time | 19.49 seconds |
| Started | May 12 01:05:32 PM PDT 24 |
| Finished | May 12 01:05:52 PM PDT 24 |
| Peak memory | 212600 kb |
| Host | smart-792bf6e4-9e5c-436c-9b4a-d38ee985f469 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1155919011 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_kmac_err_chk.1155919011 |
| Directory | /workspace/9.rom_ctrl_kmac_err_chk/latest |
| Test location | /workspace/coverage/default/9.rom_ctrl_max_throughput_chk.932501772 |
| Short name | T150 |
| Test name | |
| Test status | |
| Simulation time | 848533652 ps |
| CPU time | 8.47 seconds |
| Started | May 12 01:05:29 PM PDT 24 |
| Finished | May 12 01:05:38 PM PDT 24 |
| Peak memory | 211448 kb |
| Host | smart-fd379924-ade0-4a75-8fa5-f6d61f7b57fa |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=932501772 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_max_throughput_chk.932501772 |
| Directory | /workspace/9.rom_ctrl_max_throughput_chk/latest |
| Test location | /workspace/coverage/default/9.rom_ctrl_smoke.2395583858 |
| Short name | T165 |
| Test name | |
| Test status | |
| Simulation time | 16456753260 ps |
| CPU time | 35.31 seconds |
| Started | May 12 01:05:31 PM PDT 24 |
| Finished | May 12 01:06:06 PM PDT 24 |
| Peak memory | 214836 kb |
| Host | smart-9cf3f347-6074-455f-a50b-56035fd911e0 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2395583858 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_smoke.2395583858 |
| Directory | /workspace/9.rom_ctrl_smoke/latest |
| Test location | /workspace/coverage/default/9.rom_ctrl_stress_all.3302798746 |
| Short name | T253 |
| Test name | |
| Test status | |
| Simulation time | 3085107696 ps |
| CPU time | 34.85 seconds |
| Started | May 12 01:05:30 PM PDT 24 |
| Finished | May 12 01:06:05 PM PDT 24 |
| Peak memory | 219828 kb |
| Host | smart-7a544763-e224-457f-8f22-13456c9a2abf |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3302798746 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm _name 9.rom_ctrl_stress_all.3302798746 |
| Directory | /workspace/9.rom_ctrl_stress_all/latest |
| 0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |