Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
97.52 96.97 93.01 97.88 100.00 98.37 98.03 98.37


Total test records in report: 462
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html
T300 /workspace/coverage/default/23.rom_ctrl_alert_test.1665463416 May 14 12:51:24 PM PDT 24 May 14 12:51:30 PM PDT 24 171445584 ps
T32 /workspace/coverage/default/2.rom_ctrl_sec_cm.2966635526 May 14 12:51:01 PM PDT 24 May 14 12:52:06 PM PDT 24 8351583945 ps
T301 /workspace/coverage/default/32.rom_ctrl_alert_test.416369327 May 14 12:51:25 PM PDT 24 May 14 12:51:31 PM PDT 24 172006867 ps
T302 /workspace/coverage/default/31.rom_ctrl_alert_test.1559248144 May 14 12:51:33 PM PDT 24 May 14 12:51:48 PM PDT 24 5524685796 ps
T303 /workspace/coverage/default/39.rom_ctrl_kmac_err_chk.1391227917 May 14 12:51:42 PM PDT 24 May 14 12:52:16 PM PDT 24 7883173394 ps
T304 /workspace/coverage/default/48.rom_ctrl_corrupt_sig_fatal_chk.1081214880 May 14 12:51:47 PM PDT 24 May 14 12:55:04 PM PDT 24 21658933421 ps
T305 /workspace/coverage/default/39.rom_ctrl_smoke.2281311291 May 14 12:51:29 PM PDT 24 May 14 12:51:42 PM PDT 24 1081016740 ps
T306 /workspace/coverage/default/20.rom_ctrl_max_throughput_chk.491203772 May 14 12:51:16 PM PDT 24 May 14 12:51:27 PM PDT 24 2115248264 ps
T307 /workspace/coverage/default/40.rom_ctrl_alert_test.4042169986 May 14 12:51:31 PM PDT 24 May 14 12:51:38 PM PDT 24 171528013 ps
T308 /workspace/coverage/default/41.rom_ctrl_alert_test.3018660549 May 14 12:51:44 PM PDT 24 May 14 12:52:00 PM PDT 24 5854856753 ps
T309 /workspace/coverage/default/35.rom_ctrl_smoke.811614307 May 14 12:51:41 PM PDT 24 May 14 12:52:03 PM PDT 24 5631729600 ps
T310 /workspace/coverage/default/13.rom_ctrl_smoke.217579939 May 14 12:51:16 PM PDT 24 May 14 12:51:28 PM PDT 24 181948572 ps
T311 /workspace/coverage/default/10.rom_ctrl_smoke.3430953535 May 14 12:51:16 PM PDT 24 May 14 12:51:40 PM PDT 24 7969712545 ps
T312 /workspace/coverage/default/5.rom_ctrl_max_throughput_chk.2628858099 May 14 12:51:19 PM PDT 24 May 14 12:51:27 PM PDT 24 372939260 ps
T313 /workspace/coverage/default/36.rom_ctrl_smoke.3240654019 May 14 12:51:25 PM PDT 24 May 14 12:51:42 PM PDT 24 2435267628 ps
T314 /workspace/coverage/default/46.rom_ctrl_smoke.1742283416 May 14 12:51:46 PM PDT 24 May 14 12:51:59 PM PDT 24 185645340 ps
T315 /workspace/coverage/default/0.rom_ctrl_alert_test.3862061563 May 14 12:50:51 PM PDT 24 May 14 12:50:57 PM PDT 24 554395722 ps
T316 /workspace/coverage/default/49.rom_ctrl_smoke.1547377665 May 14 12:51:43 PM PDT 24 May 14 12:52:05 PM PDT 24 6904145839 ps
T317 /workspace/coverage/default/32.rom_ctrl_max_throughput_chk.2408784829 May 14 12:51:26 PM PDT 24 May 14 12:51:34 PM PDT 24 102644465 ps
T318 /workspace/coverage/default/2.rom_ctrl_corrupt_sig_fatal_chk.3723232047 May 14 12:50:53 PM PDT 24 May 14 12:53:57 PM PDT 24 18407897745 ps
T319 /workspace/coverage/default/37.rom_ctrl_max_throughput_chk.512062887 May 14 12:51:46 PM PDT 24 May 14 12:52:03 PM PDT 24 10506771742 ps
T320 /workspace/coverage/default/11.rom_ctrl_max_throughput_chk.888719068 May 14 12:51:01 PM PDT 24 May 14 12:51:11 PM PDT 24 2096684359 ps
T321 /workspace/coverage/default/13.rom_ctrl_stress_all.2128872886 May 14 12:51:07 PM PDT 24 May 14 12:52:08 PM PDT 24 10311503650 ps
T322 /workspace/coverage/default/21.rom_ctrl_max_throughput_chk.1794296624 May 14 12:51:22 PM PDT 24 May 14 12:51:41 PM PDT 24 3696066380 ps
T323 /workspace/coverage/default/13.rom_ctrl_stress_all_with_rand_reset.1644808906 May 14 12:51:12 PM PDT 24 May 14 12:54:58 PM PDT 24 21982279433 ps
T324 /workspace/coverage/default/13.rom_ctrl_kmac_err_chk.156494260 May 14 12:51:20 PM PDT 24 May 14 12:51:44 PM PDT 24 16331190015 ps
T325 /workspace/coverage/default/27.rom_ctrl_corrupt_sig_fatal_chk.3725595268 May 14 12:51:19 PM PDT 24 May 14 12:52:55 PM PDT 24 2860614106 ps
T326 /workspace/coverage/default/48.rom_ctrl_stress_all.1264433801 May 14 12:51:55 PM PDT 24 May 14 12:52:12 PM PDT 24 847119927 ps
T327 /workspace/coverage/default/17.rom_ctrl_kmac_err_chk.747741403 May 14 12:51:09 PM PDT 24 May 14 12:51:23 PM PDT 24 1004517134 ps
T328 /workspace/coverage/default/9.rom_ctrl_corrupt_sig_fatal_chk.3486052648 May 14 12:51:13 PM PDT 24 May 14 12:53:03 PM PDT 24 39759223534 ps
T329 /workspace/coverage/default/0.rom_ctrl_stress_all.72923896 May 14 12:50:50 PM PDT 24 May 14 12:51:50 PM PDT 24 5173584721 ps
T330 /workspace/coverage/default/49.rom_ctrl_alert_test.253477897 May 14 12:51:47 PM PDT 24 May 14 12:51:56 PM PDT 24 89128172 ps
T331 /workspace/coverage/default/3.rom_ctrl_stress_all.1853547790 May 14 12:50:51 PM PDT 24 May 14 12:52:06 PM PDT 24 8215775214 ps
T332 /workspace/coverage/default/45.rom_ctrl_kmac_err_chk.2076904489 May 14 12:51:42 PM PDT 24 May 14 12:52:13 PM PDT 24 3543446499 ps
T102 /workspace/coverage/default/39.rom_ctrl_stress_all_with_rand_reset.1106308358 May 14 12:51:38 PM PDT 24 May 14 01:46:16 PM PDT 24 83387528988 ps
T333 /workspace/coverage/default/28.rom_ctrl_stress_all_with_rand_reset.2986729530 May 14 12:51:20 PM PDT 24 May 14 01:02:43 PM PDT 24 74224366305 ps
T334 /workspace/coverage/default/1.rom_ctrl_max_throughput_chk.3043918298 May 14 12:50:53 PM PDT 24 May 14 12:51:01 PM PDT 24 95211537 ps
T335 /workspace/coverage/default/27.rom_ctrl_stress_all.95215625 May 14 12:51:28 PM PDT 24 May 14 12:52:12 PM PDT 24 12950992398 ps
T33 /workspace/coverage/default/4.rom_ctrl_sec_cm.1341046846 May 14 12:50:58 PM PDT 24 May 14 12:52:47 PM PDT 24 1466910131 ps
T336 /workspace/coverage/default/35.rom_ctrl_alert_test.1444563829 May 14 12:51:34 PM PDT 24 May 14 12:51:40 PM PDT 24 517891735 ps
T337 /workspace/coverage/default/0.rom_ctrl_max_throughput_chk.3011087224 May 14 12:50:49 PM PDT 24 May 14 12:51:00 PM PDT 24 707354993 ps
T338 /workspace/coverage/default/41.rom_ctrl_kmac_err_chk.1594990237 May 14 12:51:45 PM PDT 24 May 14 12:52:10 PM PDT 24 1970896142 ps
T339 /workspace/coverage/default/15.rom_ctrl_alert_test.2846412839 May 14 12:51:08 PM PDT 24 May 14 12:51:21 PM PDT 24 4252871550 ps
T340 /workspace/coverage/default/45.rom_ctrl_stress_all.2218905754 May 14 12:51:47 PM PDT 24 May 14 12:52:07 PM PDT 24 275319172 ps
T341 /workspace/coverage/default/25.rom_ctrl_kmac_err_chk.2671496566 May 14 12:51:17 PM PDT 24 May 14 12:51:47 PM PDT 24 6089570869 ps
T342 /workspace/coverage/default/31.rom_ctrl_smoke.1842069291 May 14 12:51:31 PM PDT 24 May 14 12:51:43 PM PDT 24 190217549 ps
T343 /workspace/coverage/default/28.rom_ctrl_smoke.843649814 May 14 12:51:26 PM PDT 24 May 14 12:52:11 PM PDT 24 10378636212 ps
T344 /workspace/coverage/default/38.rom_ctrl_kmac_err_chk.4195915609 May 14 12:51:35 PM PDT 24 May 14 12:52:02 PM PDT 24 4260765499 ps
T345 /workspace/coverage/default/13.rom_ctrl_max_throughput_chk.2983306980 May 14 12:51:19 PM PDT 24 May 14 12:51:30 PM PDT 24 1122757422 ps
T346 /workspace/coverage/default/16.rom_ctrl_stress_all.2018377701 May 14 12:51:20 PM PDT 24 May 14 12:51:46 PM PDT 24 2050590294 ps
T347 /workspace/coverage/default/12.rom_ctrl_smoke.3040306546 May 14 12:51:10 PM PDT 24 May 14 12:51:34 PM PDT 24 1898274872 ps
T348 /workspace/coverage/default/33.rom_ctrl_kmac_err_chk.1971562880 May 14 12:51:26 PM PDT 24 May 14 12:51:56 PM PDT 24 2967667792 ps
T349 /workspace/coverage/default/45.rom_ctrl_alert_test.230329683 May 14 12:51:46 PM PDT 24 May 14 12:51:56 PM PDT 24 1371829295 ps
T350 /workspace/coverage/default/22.rom_ctrl_corrupt_sig_fatal_chk.910651188 May 14 12:51:18 PM PDT 24 May 14 12:54:11 PM PDT 24 12048861249 ps
T351 /workspace/coverage/default/44.rom_ctrl_alert_test.3704587641 May 14 12:51:43 PM PDT 24 May 14 12:51:59 PM PDT 24 7332659818 ps
T352 /workspace/coverage/default/13.rom_ctrl_alert_test.774428417 May 14 12:51:20 PM PDT 24 May 14 12:51:32 PM PDT 24 396286101 ps
T353 /workspace/coverage/default/45.rom_ctrl_smoke.2886333014 May 14 12:51:49 PM PDT 24 May 14 12:52:16 PM PDT 24 24770605693 ps
T354 /workspace/coverage/default/24.rom_ctrl_stress_all.2160779483 May 14 12:51:21 PM PDT 24 May 14 12:52:16 PM PDT 24 9941347165 ps
T355 /workspace/coverage/default/19.rom_ctrl_corrupt_sig_fatal_chk.3381183810 May 14 12:51:01 PM PDT 24 May 14 12:55:16 PM PDT 24 28700739054 ps
T356 /workspace/coverage/default/47.rom_ctrl_corrupt_sig_fatal_chk.1757072934 May 14 12:51:43 PM PDT 24 May 14 12:54:41 PM PDT 24 65906925807 ps
T357 /workspace/coverage/default/47.rom_ctrl_kmac_err_chk.4253689217 May 14 12:51:49 PM PDT 24 May 14 12:52:03 PM PDT 24 1384103768 ps
T358 /workspace/coverage/default/35.rom_ctrl_kmac_err_chk.2017196792 May 14 12:51:38 PM PDT 24 May 14 12:51:55 PM PDT 24 6944243218 ps
T359 /workspace/coverage/default/43.rom_ctrl_stress_all.413798318 May 14 12:51:30 PM PDT 24 May 14 12:51:59 PM PDT 24 547835259 ps
T360 /workspace/coverage/default/26.rom_ctrl_alert_test.2772200434 May 14 12:51:23 PM PDT 24 May 14 12:51:29 PM PDT 24 85467553 ps
T361 /workspace/coverage/default/5.rom_ctrl_stress_all.86584203 May 14 12:51:16 PM PDT 24 May 14 12:51:35 PM PDT 24 1191416019 ps
T362 /workspace/coverage/default/3.rom_ctrl_kmac_err_chk.417559093 May 14 12:50:56 PM PDT 24 May 14 12:51:08 PM PDT 24 168933210 ps
T363 /workspace/coverage/default/26.rom_ctrl_corrupt_sig_fatal_chk.627710245 May 14 12:51:22 PM PDT 24 May 14 12:54:09 PM PDT 24 12028209291 ps
T51 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_aliasing.2056695327 May 14 12:51:59 PM PDT 24 May 14 12:52:17 PM PDT 24 7828503285 ps
T48 /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_intg_err.2425743193 May 14 12:52:05 PM PDT 24 May 14 12:52:44 PM PDT 24 368164267 ps
T52 /workspace/coverage/cover_reg_top/0.rom_ctrl_same_csr_outstanding.3524605109 May 14 12:51:50 PM PDT 24 May 14 12:52:08 PM PDT 24 16343531865 ps
T55 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_hw_reset.2412783104 May 14 12:52:02 PM PDT 24 May 14 12:52:14 PM PDT 24 639397090 ps
T364 /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_mem_rw_with_rand_reset.3691626190 May 14 12:52:01 PM PDT 24 May 14 12:52:12 PM PDT 24 1785605155 ps
T365 /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_mem_rw_with_rand_reset.1141450675 May 14 12:51:58 PM PDT 24 May 14 12:52:07 PM PDT 24 105790694 ps
T366 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_mem_rw_with_rand_reset.3448131571 May 14 12:52:03 PM PDT 24 May 14 12:52:12 PM PDT 24 445473508 ps
T92 /workspace/coverage/cover_reg_top/4.rom_ctrl_same_csr_outstanding.2907117088 May 14 12:51:52 PM PDT 24 May 14 12:52:08 PM PDT 24 4781964824 ps
T367 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_mem_rw_with_rand_reset.3338431099 May 14 12:51:50 PM PDT 24 May 14 12:51:59 PM PDT 24 90925039 ps
T96 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_hw_reset.3694362297 May 14 12:51:54 PM PDT 24 May 14 12:52:07 PM PDT 24 617427021 ps
T56 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_aliasing.3842861176 May 14 12:51:52 PM PDT 24 May 14 12:52:09 PM PDT 24 9685862130 ps
T97 /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_rw.2354599052 May 14 12:52:01 PM PDT 24 May 14 12:52:15 PM PDT 24 4101910251 ps
T368 /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_errors.2233363419 May 14 12:51:55 PM PDT 24 May 14 12:52:16 PM PDT 24 1677564993 ps
T369 /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_errors.4182483511 May 14 12:52:04 PM PDT 24 May 14 12:52:23 PM PDT 24 4221545884 ps
T57 /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_rw.334642239 May 14 12:52:04 PM PDT 24 May 14 12:52:14 PM PDT 24 830198851 ps
T98 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_aliasing.2811601053 May 14 12:51:55 PM PDT 24 May 14 12:52:08 PM PDT 24 1881816400 ps
T370 /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_errors.1374368599 May 14 12:51:49 PM PDT 24 May 14 12:52:11 PM PDT 24 1591475915 ps
T371 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_bit_bash.56526187 May 14 12:51:42 PM PDT 24 May 14 12:51:51 PM PDT 24 1509871594 ps
T49 /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_intg_err.3043087696 May 14 12:51:59 PM PDT 24 May 14 12:52:49 PM PDT 24 7384590215 ps
T58 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_rw.2607775849 May 14 12:51:50 PM PDT 24 May 14 12:52:04 PM PDT 24 3249235714 ps
T59 /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_rw.3746036540 May 14 12:52:05 PM PDT 24 May 14 12:52:11 PM PDT 24 332997820 ps
T372 /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_errors.509429609 May 14 12:52:12 PM PDT 24 May 14 12:52:25 PM PDT 24 5074351107 ps
T373 /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_mem_rw_with_rand_reset.1243810275 May 14 12:52:09 PM PDT 24 May 14 12:52:26 PM PDT 24 2415819509 ps
T60 /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_rw.949021399 May 14 12:52:12 PM PDT 24 May 14 12:52:23 PM PDT 24 851839190 ps
T374 /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_mem_rw_with_rand_reset.3942939334 May 14 12:51:56 PM PDT 24 May 14 12:52:07 PM PDT 24 617637617 ps
T375 /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_partial_access.4148044062 May 14 12:51:49 PM PDT 24 May 14 12:52:04 PM PDT 24 2013253267 ps
T376 /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_errors.1235124008 May 14 12:52:09 PM PDT 24 May 14 12:52:21 PM PDT 24 858477451 ps
T377 /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_walk.2930604393 May 14 12:52:02 PM PDT 24 May 14 12:52:08 PM PDT 24 333606767 ps
T61 /workspace/coverage/cover_reg_top/12.rom_ctrl_same_csr_outstanding.994324040 May 14 12:52:01 PM PDT 24 May 14 12:52:21 PM PDT 24 1941260010 ps
T62 /workspace/coverage/cover_reg_top/15.rom_ctrl_passthru_mem_tl_intg_err.1974552799 May 14 12:52:00 PM PDT 24 May 14 12:53:08 PM PDT 24 25812225257 ps
T50 /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_intg_err.4029591603 May 14 12:51:46 PM PDT 24 May 14 12:53:04 PM PDT 24 5982854080 ps
T378 /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_errors.1689588840 May 14 12:52:04 PM PDT 24 May 14 12:52:21 PM PDT 24 9821702097 ps
T379 /workspace/coverage/cover_reg_top/3.rom_ctrl_passthru_mem_tl_intg_err.884998709 May 14 12:51:51 PM PDT 24 May 14 12:52:15 PM PDT 24 383440426 ps
T103 /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_intg_err.4002945780 May 14 12:51:47 PM PDT 24 May 14 12:52:38 PM PDT 24 30530052348 ps
T380 /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_errors.4108539517 May 14 12:51:49 PM PDT 24 May 14 12:52:10 PM PDT 24 1947555523 ps
T381 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_mem_rw_with_rand_reset.3452610047 May 14 12:51:47 PM PDT 24 May 14 12:52:05 PM PDT 24 4885064870 ps
T63 /workspace/coverage/cover_reg_top/17.rom_ctrl_same_csr_outstanding.924907264 May 14 12:52:09 PM PDT 24 May 14 12:52:23 PM PDT 24 5270165737 ps
T382 /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_walk.4285257234 May 14 12:51:47 PM PDT 24 May 14 12:52:07 PM PDT 24 3876999746 ps
T108 /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_intg_err.2976449962 May 14 12:51:44 PM PDT 24 May 14 12:52:31 PM PDT 24 3306544702 ps
T70 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_rw.3741462917 May 14 12:51:56 PM PDT 24 May 14 12:52:05 PM PDT 24 289829884 ps
T383 /workspace/coverage/cover_reg_top/18.rom_ctrl_passthru_mem_tl_intg_err.2875200605 May 14 12:52:12 PM PDT 24 May 14 12:53:26 PM PDT 24 95828645312 ps
T384 /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_errors.311114738 May 14 12:52:05 PM PDT 24 May 14 12:52:20 PM PDT 24 5978634607 ps
T113 /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_intg_err.2390225882 May 14 12:51:59 PM PDT 24 May 14 12:53:11 PM PDT 24 250648720 ps
T71 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_hw_reset.4075324394 May 14 12:51:49 PM PDT 24 May 14 12:51:59 PM PDT 24 89553779 ps
T385 /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_partial_access.1095658634 May 14 12:51:44 PM PDT 24 May 14 12:51:55 PM PDT 24 691847802 ps
T386 /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_rw.225843748 May 14 12:52:04 PM PDT 24 May 14 12:52:19 PM PDT 24 13049858108 ps
T387 /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_rw.4097100030 May 14 12:51:57 PM PDT 24 May 14 12:52:09 PM PDT 24 3277441790 ps
T388 /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_rw.917574832 May 14 12:52:04 PM PDT 24 May 14 12:52:17 PM PDT 24 22959639322 ps
T389 /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_walk.1501606815 May 14 12:51:49 PM PDT 24 May 14 12:52:09 PM PDT 24 2028089910 ps
T111 /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_intg_err.3323981609 May 14 12:52:06 PM PDT 24 May 14 12:53:19 PM PDT 24 488719413 ps
T390 /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_intg_err.971345245 May 14 12:52:09 PM PDT 24 May 14 12:52:48 PM PDT 24 367891703 ps
T391 /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_errors.693439586 May 14 12:51:49 PM PDT 24 May 14 12:52:05 PM PDT 24 976986710 ps
T392 /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_rw.1963993945 May 14 12:52:01 PM PDT 24 May 14 12:52:08 PM PDT 24 89157418 ps
T93 /workspace/coverage/cover_reg_top/6.rom_ctrl_same_csr_outstanding.2610542297 May 14 12:51:57 PM PDT 24 May 14 12:52:18 PM PDT 24 9478610601 ps
T393 /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_errors.419828366 May 14 12:52:01 PM PDT 24 May 14 12:52:13 PM PDT 24 157094418 ps
T394 /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_errors.1767633263 May 14 12:52:09 PM PDT 24 May 14 12:52:25 PM PDT 24 1116649263 ps
T395 /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_rw.2795244945 May 14 12:52:10 PM PDT 24 May 14 12:52:16 PM PDT 24 332961807 ps
T396 /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_errors.3307345462 May 14 12:52:06 PM PDT 24 May 14 12:52:16 PM PDT 24 250968594 ps
T101 /workspace/coverage/cover_reg_top/2.rom_ctrl_passthru_mem_tl_intg_err.4020005002 May 14 12:51:49 PM PDT 24 May 14 12:52:40 PM PDT 24 4766181566 ps
T72 /workspace/coverage/cover_reg_top/19.rom_ctrl_passthru_mem_tl_intg_err.3905331044 May 14 12:52:09 PM PDT 24 May 14 12:53:08 PM PDT 24 49635481410 ps
T109 /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_intg_err.439482226 May 14 12:51:50 PM PDT 24 May 14 12:52:32 PM PDT 24 1432025175 ps
T94 /workspace/coverage/cover_reg_top/1.rom_ctrl_same_csr_outstanding.2217734745 May 14 12:51:54 PM PDT 24 May 14 12:52:04 PM PDT 24 182848635 ps
T397 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_bit_bash.1961660464 May 14 12:51:46 PM PDT 24 May 14 12:52:07 PM PDT 24 2171686663 ps
T95 /workspace/coverage/cover_reg_top/4.rom_ctrl_passthru_mem_tl_intg_err.3360418538 May 14 12:51:53 PM PDT 24 May 14 12:52:16 PM PDT 24 378153142 ps
T398 /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_errors.906200007 May 14 12:51:52 PM PDT 24 May 14 12:52:08 PM PDT 24 687082486 ps
T399 /workspace/coverage/cover_reg_top/16.rom_ctrl_same_csr_outstanding.1748939297 May 14 12:52:12 PM PDT 24 May 14 12:52:20 PM PDT 24 94678659 ps
T400 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_bit_bash.3225445710 May 14 12:51:45 PM PDT 24 May 14 12:52:04 PM PDT 24 2339460046 ps
T401 /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_partial_access.4067235222 May 14 12:52:00 PM PDT 24 May 14 12:52:16 PM PDT 24 5711597455 ps
T402 /workspace/coverage/cover_reg_top/8.rom_ctrl_same_csr_outstanding.2613281120 May 14 12:51:51 PM PDT 24 May 14 12:52:12 PM PDT 24 2181694873 ps
T403 /workspace/coverage/cover_reg_top/10.rom_ctrl_same_csr_outstanding.159959561 May 14 12:52:01 PM PDT 24 May 14 12:52:09 PM PDT 24 500897888 ps
T404 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_aliasing.1474312343 May 14 12:51:49 PM PDT 24 May 14 12:52:07 PM PDT 24 6024136757 ps
T73 /workspace/coverage/cover_reg_top/17.rom_ctrl_passthru_mem_tl_intg_err.288226838 May 14 12:52:09 PM PDT 24 May 14 12:52:38 PM PDT 24 1043617479 ps
T405 /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_mem_rw_with_rand_reset.3312872109 May 14 12:52:11 PM PDT 24 May 14 12:52:21 PM PDT 24 2406190669 ps
T406 /workspace/coverage/cover_reg_top/14.rom_ctrl_same_csr_outstanding.2514510170 May 14 12:51:59 PM PDT 24 May 14 12:52:11 PM PDT 24 2828452161 ps
T407 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_bit_bash.4237496526 May 14 12:51:54 PM PDT 24 May 14 12:52:06 PM PDT 24 541356349 ps
T110 /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_intg_err.1513267052 May 14 12:51:55 PM PDT 24 May 14 12:52:42 PM PDT 24 5766821511 ps
T408 /workspace/coverage/cover_reg_top/18.rom_ctrl_same_csr_outstanding.2530770825 May 14 12:52:09 PM PDT 24 May 14 12:52:23 PM PDT 24 2574936098 ps
T104 /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_intg_err.2645694353 May 14 12:51:51 PM PDT 24 May 14 12:52:43 PM PDT 24 4340580643 ps
T409 /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_mem_rw_with_rand_reset.751380615 May 14 12:52:01 PM PDT 24 May 14 12:52:14 PM PDT 24 1209102611 ps
T410 /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_mem_rw_with_rand_reset.610217744 May 14 12:51:58 PM PDT 24 May 14 12:52:13 PM PDT 24 2627250856 ps
T411 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_mem_rw_with_rand_reset.2168706425 May 14 12:51:48 PM PDT 24 May 14 12:52:05 PM PDT 24 2887836994 ps
T412 /workspace/coverage/cover_reg_top/7.rom_ctrl_passthru_mem_tl_intg_err.1886209140 May 14 12:52:03 PM PDT 24 May 14 12:53:19 PM PDT 24 15846833961 ps
T74 /workspace/coverage/cover_reg_top/5.rom_ctrl_passthru_mem_tl_intg_err.143099600 May 14 12:51:58 PM PDT 24 May 14 12:52:27 PM PDT 24 1017032711 ps
T413 /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_mem_rw_with_rand_reset.628373113 May 14 12:52:14 PM PDT 24 May 14 12:52:20 PM PDT 24 99264878 ps
T105 /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_intg_err.113221563 May 14 12:51:55 PM PDT 24 May 14 12:52:40 PM PDT 24 3345773853 ps
T414 /workspace/coverage/cover_reg_top/19.rom_ctrl_same_csr_outstanding.1676450402 May 14 12:52:10 PM PDT 24 May 14 12:52:21 PM PDT 24 1910637211 ps
T415 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_mem_rw_with_rand_reset.708844626 May 14 12:51:52 PM PDT 24 May 14 12:52:04 PM PDT 24 482968983 ps
T416 /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_rw.182309291 May 14 12:51:54 PM PDT 24 May 14 12:52:04 PM PDT 24 213780564 ps
T417 /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_errors.1520564025 May 14 12:51:47 PM PDT 24 May 14 12:52:07 PM PDT 24 3630980827 ps
T418 /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_mem_rw_with_rand_reset.3125859073 May 14 12:52:02 PM PDT 24 May 14 12:52:21 PM PDT 24 9448705550 ps
T419 /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_walk.644599012 May 14 12:51:49 PM PDT 24 May 14 12:51:57 PM PDT 24 1651471469 ps
T76 /workspace/coverage/cover_reg_top/13.rom_ctrl_passthru_mem_tl_intg_err.1011395468 May 14 12:52:00 PM PDT 24 May 14 12:53:18 PM PDT 24 15318483736 ps
T106 /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_intg_err.3491414607 May 14 12:51:59 PM PDT 24 May 14 12:53:13 PM PDT 24 9831773970 ps
T77 /workspace/coverage/cover_reg_top/1.rom_ctrl_passthru_mem_tl_intg_err.1074067314 May 14 12:51:50 PM PDT 24 May 14 12:53:13 PM PDT 24 17300620812 ps
T420 /workspace/coverage/cover_reg_top/5.rom_ctrl_same_csr_outstanding.3520597737 May 14 12:51:57 PM PDT 24 May 14 12:52:06 PM PDT 24 337898239 ps
T79 /workspace/coverage/cover_reg_top/12.rom_ctrl_passthru_mem_tl_intg_err.1820791595 May 14 12:52:06 PM PDT 24 May 14 12:53:11 PM PDT 24 38076585875 ps
T421 /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_intg_err.1146484847 May 14 12:51:53 PM PDT 24 May 14 12:52:41 PM PDT 24 6284120156 ps
T422 /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_mem_rw_with_rand_reset.3348359767 May 14 12:51:52 PM PDT 24 May 14 12:52:03 PM PDT 24 1706197867 ps
T423 /workspace/coverage/cover_reg_top/11.rom_ctrl_same_csr_outstanding.2696358535 May 14 12:52:07 PM PDT 24 May 14 12:52:25 PM PDT 24 2142145361 ps
T75 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_hw_reset.82193384 May 14 12:51:47 PM PDT 24 May 14 12:52:01 PM PDT 24 2221352532 ps
T424 /workspace/coverage/cover_reg_top/9.rom_ctrl_same_csr_outstanding.2706164084 May 14 12:51:56 PM PDT 24 May 14 12:52:09 PM PDT 24 2470367442 ps
T425 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_hw_reset.2175899382 May 14 12:52:04 PM PDT 24 May 14 12:52:12 PM PDT 24 356482767 ps
T426 /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_mem_rw_with_rand_reset.3051780580 May 14 12:51:52 PM PDT 24 May 14 12:52:10 PM PDT 24 1531187807 ps
T427 /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_errors.2712814441 May 14 12:52:00 PM PDT 24 May 14 12:52:23 PM PDT 24 2037172154 ps
T428 /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_errors.2775260386 May 14 12:51:52 PM PDT 24 May 14 12:52:07 PM PDT 24 290476287 ps
T429 /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_intg_err.1950858464 May 14 12:52:10 PM PDT 24 May 14 12:52:57 PM PDT 24 7887493892 ps
T430 /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_partial_access.2313860679 May 14 12:51:46 PM PDT 24 May 14 12:52:02 PM PDT 24 6159035846 ps
T431 /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_partial_access.3209850678 May 14 12:51:46 PM PDT 24 May 14 12:51:59 PM PDT 24 3804179104 ps
T432 /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_rw.893331813 May 14 12:51:54 PM PDT 24 May 14 12:52:10 PM PDT 24 5448544618 ps
T433 /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_mem_rw_with_rand_reset.2623815980 May 14 12:51:56 PM PDT 24 May 14 12:52:12 PM PDT 24 14194112844 ps
T434 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_bit_bash.157582889 May 14 12:51:51 PM PDT 24 May 14 12:52:13 PM PDT 24 8486320675 ps
T435 /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_errors.1027025307 May 14 12:51:52 PM PDT 24 May 14 12:52:11 PM PDT 24 4974066686 ps
T112 /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_intg_err.2895611521 May 14 12:51:57 PM PDT 24 May 14 12:53:19 PM PDT 24 1897598093 ps
T436 /workspace/coverage/cover_reg_top/9.rom_ctrl_passthru_mem_tl_intg_err.1340056862 May 14 12:51:59 PM PDT 24 May 14 12:53:04 PM PDT 24 7383564569 ps
T78 /workspace/coverage/cover_reg_top/8.rom_ctrl_passthru_mem_tl_intg_err.1387575697 May 14 12:51:55 PM PDT 24 May 14 12:52:35 PM PDT 24 12788020961 ps
T437 /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_errors.843057415 May 14 12:51:51 PM PDT 24 May 14 12:52:12 PM PDT 24 1623911344 ps
T80 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_aliasing.1676871416 May 14 12:51:50 PM PDT 24 May 14 12:51:59 PM PDT 24 348191909 ps
T438 /workspace/coverage/cover_reg_top/13.rom_ctrl_same_csr_outstanding.1516577843 May 14 12:52:04 PM PDT 24 May 14 12:52:21 PM PDT 24 8757735943 ps
T81 /workspace/coverage/cover_reg_top/16.rom_ctrl_passthru_mem_tl_intg_err.1380732787 May 14 12:52:09 PM PDT 24 May 14 12:53:01 PM PDT 24 24783269834 ps
T439 /workspace/coverage/cover_reg_top/2.rom_ctrl_same_csr_outstanding.4075689840 May 14 12:51:49 PM PDT 24 May 14 12:52:06 PM PDT 24 3415042192 ps
T107 /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_intg_err.2426729679 May 14 12:52:13 PM PDT 24 May 14 12:53:25 PM PDT 24 850322173 ps
T440 /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_errors.2142630040 May 14 12:51:55 PM PDT 24 May 14 12:52:11 PM PDT 24 3220566450 ps
T441 /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_intg_err.2203535173 May 14 12:52:06 PM PDT 24 May 14 12:52:55 PM PDT 24 4505989836 ps
T82 /workspace/coverage/cover_reg_top/6.rom_ctrl_passthru_mem_tl_intg_err.3779738514 May 14 12:52:08 PM PDT 24 May 14 12:53:28 PM PDT 24 9426935206 ps
T442 /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_intg_err.2904875677 May 14 12:52:08 PM PDT 24 May 14 12:53:27 PM PDT 24 2281255627 ps
T443 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_rw.607451331 May 14 12:51:59 PM PDT 24 May 14 12:52:06 PM PDT 24 755209870 ps
T444 /workspace/coverage/cover_reg_top/14.rom_ctrl_passthru_mem_tl_intg_err.3172223169 May 14 12:52:06 PM PDT 24 May 14 12:53:32 PM PDT 24 20685421317 ps
T445 /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_rw.909902859 May 14 12:51:58 PM PDT 24 May 14 12:52:14 PM PDT 24 2670175438 ps
T446 /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_mem_rw_with_rand_reset.2161219397 May 14 12:52:08 PM PDT 24 May 14 12:52:13 PM PDT 24 94195525 ps
T447 /workspace/coverage/cover_reg_top/3.rom_ctrl_same_csr_outstanding.2368679971 May 14 12:51:50 PM PDT 24 May 14 12:52:09 PM PDT 24 1253998249 ps
T448 /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_rw.1903689477 May 14 12:52:10 PM PDT 24 May 14 12:52:26 PM PDT 24 3221621514 ps
T449 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_rw.1742902660 May 14 12:51:39 PM PDT 24 May 14 12:51:45 PM PDT 24 165289521 ps
T450 /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_walk.3665729541 May 14 12:51:47 PM PDT 24 May 14 12:52:00 PM PDT 24 858352245 ps
T451 /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_rw.3069904855 May 14 12:52:00 PM PDT 24 May 14 12:52:15 PM PDT 24 2927236080 ps
T452 /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_errors.3915548212 May 14 12:52:10 PM PDT 24 May 14 12:52:32 PM PDT 24 8473677454 ps
T453 /workspace/coverage/cover_reg_top/7.rom_ctrl_same_csr_outstanding.3551604809 May 14 12:51:56 PM PDT 24 May 14 12:52:16 PM PDT 24 2006563140 ps
T454 /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_intg_err.852519867 May 14 12:52:04 PM PDT 24 May 14 12:52:42 PM PDT 24 195428699 ps
T455 /workspace/coverage/cover_reg_top/0.rom_ctrl_passthru_mem_tl_intg_err.2207172553 May 14 12:51:58 PM PDT 24 May 14 12:52:42 PM PDT 24 9271604798 ps
T456 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_rw.2599474521 May 14 12:51:49 PM PDT 24 May 14 12:52:08 PM PDT 24 2448276156 ps
T457 /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_mem_rw_with_rand_reset.315846153 May 14 12:51:57 PM PDT 24 May 14 12:52:06 PM PDT 24 103100752 ps
T458 /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_rw.757679545 May 14 12:52:11 PM PDT 24 May 14 12:52:17 PM PDT 24 85434080 ps
T459 /workspace/coverage/cover_reg_top/10.rom_ctrl_passthru_mem_tl_intg_err.1370068259 May 14 12:51:58 PM PDT 24 May 14 12:52:42 PM PDT 24 3362506075 ps
T460 /workspace/coverage/cover_reg_top/11.rom_ctrl_passthru_mem_tl_intg_err.1123086854 May 14 12:51:59 PM PDT 24 May 14 12:53:38 PM PDT 24 154785032407 ps
T461 /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_mem_rw_with_rand_reset.4146298062 May 14 12:52:09 PM PDT 24 May 14 12:52:20 PM PDT 24 4206976839 ps
T462 /workspace/coverage/cover_reg_top/15.rom_ctrl_same_csr_outstanding.1064729515 May 14 12:52:10 PM PDT 24 May 14 12:52:27 PM PDT 24 6781527786 ps

Test location /workspace/coverage/default/34.rom_ctrl_corrupt_sig_fatal_chk.3802619878
Short name T4
Test name
Test status
Simulation time 88330238743 ps
CPU time 227.13 seconds
Started May 14 12:51:45 PM PDT 24
Finished May 14 12:55:35 PM PDT 24
Peak memory 237932 kb
Host smart-d427675c-401b-45c1-84c0-ff0628b665a7
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3802619878 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_
corrupt_sig_fatal_chk.3802619878
Directory /workspace/34.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/30.rom_ctrl_stress_all_with_rand_reset.855576432
Short name T14
Test name
Test status
Simulation time 51553646367 ps
CPU time 1201.57 seconds
Started May 14 12:51:33 PM PDT 24
Finished May 14 01:11:36 PM PDT 24
Peak memory 227416 kb
Host smart-2b09a52d-7f83-4da7-a385-24adbf5c81bd
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=855576432 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_stress_all_with_rand_reset.855576432
Directory /workspace/30.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.rom_ctrl_corrupt_sig_fatal_chk.4064782936
Short name T27
Test name
Test status
Simulation time 2960333160 ps
CPU time 103.47 seconds
Started May 14 12:51:30 PM PDT 24
Finished May 14 12:53:16 PM PDT 24
Peak memory 236764 kb
Host smart-71757cde-09af-4154-803c-a4693898e1b8
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4064782936 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_
corrupt_sig_fatal_chk.4064782936
Directory /workspace/39.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/25.rom_ctrl_corrupt_sig_fatal_chk.96750765
Short name T21
Test name
Test status
Simulation time 61663607434 ps
CPU time 164.44 seconds
Started May 14 12:51:28 PM PDT 24
Finished May 14 12:54:15 PM PDT 24
Peak memory 229876 kb
Host smart-97419cd6-3edd-4098-9bec-1da6d73b6c14
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96750765 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_
sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_co
rrupt_sig_fatal_chk.96750765
Directory /workspace/25.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_intg_err.4029591603
Short name T50
Test name
Test status
Simulation time 5982854080 ps
CPU time 75.06 seconds
Started May 14 12:51:46 PM PDT 24
Finished May 14 12:53:04 PM PDT 24
Peak memory 212496 kb
Host smart-b1f597d9-bd40-4280-a8db-f40e955c847a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4029591603 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_tl_in
tg_err.4029591603
Directory /workspace/2.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/11.rom_ctrl_stress_all.153544162
Short name T11
Test name
Test status
Simulation time 26461767206 ps
CPU time 62.45 seconds
Started May 14 12:51:02 PM PDT 24
Finished May 14 12:52:05 PM PDT 24
Peak memory 214548 kb
Host smart-0bd8ad77-5309-4845-808b-cd3b4f428f7e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=153544162 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 11.rom_ctrl_stress_all.153544162
Directory /workspace/11.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/0.rom_ctrl_sec_cm.2256549111
Short name T29
Test name
Test status
Simulation time 693964357 ps
CPU time 99.69 seconds
Started May 14 12:50:58 PM PDT 24
Finished May 14 12:52:40 PM PDT 24
Peak memory 230632 kb
Host smart-11c46c6c-e415-4e6e-85cb-d5dc248b8cc8
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2256549111 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_sec_cm.2256549111
Directory /workspace/0.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_passthru_mem_tl_intg_err.3905331044
Short name T72
Test name
Test status
Simulation time 49635481410 ps
CPU time 56.66 seconds
Started May 14 12:52:09 PM PDT 24
Finished May 14 12:53:08 PM PDT 24
Peak memory 211372 kb
Host smart-c5996cb8-df54-4c11-83c8-1fe821c8fc31
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3905331044 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_p
assthru_mem_tl_intg_err.3905331044
Directory /workspace/19.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_intg_err.113221563
Short name T105
Test name
Test status
Simulation time 3345773853 ps
CPU time 41.47 seconds
Started May 14 12:51:55 PM PDT 24
Finished May 14 12:52:40 PM PDT 24
Peak memory 212232 kb
Host smart-e7c62fbf-de94-46fe-bb86-527dc348d9b4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=113221563 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_tl_int
g_err.113221563
Directory /workspace/4.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/47.rom_ctrl_alert_test.3415790223
Short name T31
Test name
Test status
Simulation time 85450880 ps
CPU time 4.35 seconds
Started May 14 12:51:49 PM PDT 24
Finished May 14 12:51:58 PM PDT 24
Peak memory 211208 kb
Host smart-5a60989e-8b66-407c-8214-babdc9d5b619
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3415790223 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_alert_test.3415790223
Directory /workspace/47.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/20.rom_ctrl_kmac_err_chk.156728874
Short name T132
Test name
Test status
Simulation time 7856852464 ps
CPU time 22.25 seconds
Started May 14 12:51:19 PM PDT 24
Finished May 14 12:51:44 PM PDT 24
Peak memory 211460 kb
Host smart-eb1e7c0a-7ef7-4539-a3d5-aff8a91bed78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=156728874 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_kmac_err_chk.156728874
Directory /workspace/20.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/1.rom_ctrl_kmac_err_chk.121349979
Short name T20
Test name
Test status
Simulation time 168782264 ps
CPU time 9.32 seconds
Started May 14 12:50:53 PM PDT 24
Finished May 14 12:51:04 PM PDT 24
Peak memory 211152 kb
Host smart-281337b9-b10e-4c56-b40e-c2ff4fc04963
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=121349979 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_kmac_err_chk.121349979
Directory /workspace/1.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_intg_err.2645694353
Short name T104
Test name
Test status
Simulation time 4340580643 ps
CPU time 47.42 seconds
Started May 14 12:51:51 PM PDT 24
Finished May 14 12:52:43 PM PDT 24
Peak memory 212344 kb
Host smart-7f2997ec-f4b6-41a3-9b8d-ea46c9d89b7c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2645694353 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_tl_i
ntg_err.2645694353
Directory /workspace/10.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_intg_err.2426729679
Short name T107
Test name
Test status
Simulation time 850322173 ps
CPU time 70.72 seconds
Started May 14 12:52:13 PM PDT 24
Finished May 14 12:53:25 PM PDT 24
Peak memory 212048 kb
Host smart-75287f21-e550-4b3a-8d9f-77a2cf19ff53
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2426729679 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_tl_i
ntg_err.2426729679
Directory /workspace/16.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_same_csr_outstanding.3524605109
Short name T52
Test name
Test status
Simulation time 16343531865 ps
CPU time 13.05 seconds
Started May 14 12:51:50 PM PDT 24
Finished May 14 12:52:08 PM PDT 24
Peak memory 211292 kb
Host smart-059873b9-cdc5-4bf0-9262-af36f94c1e9e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3524605109 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_c
trl_same_csr_outstanding.3524605109
Directory /workspace/0.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/default/29.rom_ctrl_stress_all_with_rand_reset.704817592
Short name T15
Test name
Test status
Simulation time 100751931377 ps
CPU time 942.97 seconds
Started May 14 12:51:19 PM PDT 24
Finished May 14 01:07:05 PM PDT 24
Peak memory 235836 kb
Host smart-9010e9b4-dc6a-4864-9f07-68359be8049b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=704817592 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_stress_all_with_rand_reset.704817592
Directory /workspace/29.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.rom_ctrl_max_throughput_chk.1304122293
Short name T83
Test name
Test status
Simulation time 367565304 ps
CPU time 5.57 seconds
Started May 14 12:51:49 PM PDT 24
Finished May 14 12:51:59 PM PDT 24
Peak memory 211044 kb
Host smart-27f0c771-7afd-488e-872d-5b42919416b8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1304122293 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_max_throughput_chk.1304122293
Directory /workspace/47.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/15.rom_ctrl_stress_all_with_rand_reset.2626431199
Short name T37
Test name
Test status
Simulation time 238507096117 ps
CPU time 3269.85 seconds
Started May 14 12:51:12 PM PDT 24
Finished May 14 01:45:45 PM PDT 24
Peak memory 244132 kb
Host smart-d101e366-d20c-430a-9cb7-70f1367da830
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2626431199 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_stress_all_with_rand_reset.2626431199
Directory /workspace/15.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_aliasing.1474312343
Short name T404
Test name
Test status
Simulation time 6024136757 ps
CPU time 13.32 seconds
Started May 14 12:51:49 PM PDT 24
Finished May 14 12:52:07 PM PDT 24
Peak memory 211200 kb
Host smart-152cc5c0-2e94-4f82-9fd0-d033c5273471
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1474312343 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_alia
sing.1474312343
Directory /workspace/0.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_bit_bash.4237496526
Short name T407
Test name
Test status
Simulation time 541356349 ps
CPU time 8.11 seconds
Started May 14 12:51:54 PM PDT 24
Finished May 14 12:52:06 PM PDT 24
Peak memory 211136 kb
Host smart-1677cf76-6de7-458f-8897-eb914a5041a3
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4237496526 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_bit_
bash.4237496526
Directory /workspace/0.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_hw_reset.3694362297
Short name T96
Test name
Test status
Simulation time 617427021 ps
CPU time 9.09 seconds
Started May 14 12:51:54 PM PDT 24
Finished May 14 12:52:07 PM PDT 24
Peak memory 211224 kb
Host smart-d99cc9a4-7dbc-4886-b588-c4e162399942
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3694362297 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_hw_r
eset.3694362297
Directory /workspace/0.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_mem_rw_with_rand_reset.3452610047
Short name T381
Test name
Test status
Simulation time 4885064870 ps
CPU time 13.28 seconds
Started May 14 12:51:47 PM PDT 24
Finished May 14 12:52:05 PM PDT 24
Peak memory 219556 kb
Host smart-065447b6-7595-41df-a096-e32f428e17a7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3452610047 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 0.rom_ctrl_csr_mem_rw_with_rand_reset.3452610047
Directory /workspace/0.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_rw.3741462917
Short name T70
Test name
Test status
Simulation time 289829884 ps
CPU time 5.96 seconds
Started May 14 12:51:56 PM PDT 24
Finished May 14 12:52:05 PM PDT 24
Peak memory 211192 kb
Host smart-94347b11-aec1-418a-b271-165955cbf27c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3741462917 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_rw.3741462917
Directory /workspace/0.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_partial_access.4067235222
Short name T401
Test name
Test status
Simulation time 5711597455 ps
CPU time 12.89 seconds
Started May 14 12:52:00 PM PDT 24
Finished May 14 12:52:16 PM PDT 24
Peak memory 211168 kb
Host smart-da431aa1-2417-4eed-9c2b-4da551644590
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4067235222 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctr
l_mem_partial_access.4067235222
Directory /workspace/0.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_walk.644599012
Short name T419
Test name
Test status
Simulation time 1651471469 ps
CPU time 3.95 seconds
Started May 14 12:51:49 PM PDT 24
Finished May 14 12:51:57 PM PDT 24
Peak memory 211184 kb
Host smart-3be40000-8781-4c8d-b77a-f80717e3c49e
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=644599012 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_mem_walk.
644599012
Directory /workspace/0.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_passthru_mem_tl_intg_err.2207172553
Short name T455
Test name
Test status
Simulation time 9271604798 ps
CPU time 40.31 seconds
Started May 14 12:51:58 PM PDT 24
Finished May 14 12:52:42 PM PDT 24
Peak memory 211344 kb
Host smart-adbbab44-142b-4c5a-a0d5-dc1634c161cc
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2207172553 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_pa
ssthru_mem_tl_intg_err.2207172553
Directory /workspace/0.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_errors.4108539517
Short name T380
Test name
Test status
Simulation time 1947555523 ps
CPU time 17.46 seconds
Started May 14 12:51:49 PM PDT 24
Finished May 14 12:52:10 PM PDT 24
Peak memory 219468 kb
Host smart-1c3505a9-a9c7-4d29-bafe-85f2a75be6e1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4108539517 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_tl_errors.4108539517
Directory /workspace/0.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_intg_err.2976449962
Short name T108
Test name
Test status
Simulation time 3306544702 ps
CPU time 44.61 seconds
Started May 14 12:51:44 PM PDT 24
Finished May 14 12:52:31 PM PDT 24
Peak memory 213188 kb
Host smart-fc7ac967-1b9b-41d5-a494-e6f2a05b0d13
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2976449962 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_tl_in
tg_err.2976449962
Directory /workspace/0.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_aliasing.3842861176
Short name T56
Test name
Test status
Simulation time 9685862130 ps
CPU time 12.36 seconds
Started May 14 12:51:52 PM PDT 24
Finished May 14 12:52:09 PM PDT 24
Peak memory 211380 kb
Host smart-d8cd4774-34e9-4c09-97de-9e41c85314d3
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3842861176 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_alia
sing.3842861176
Directory /workspace/1.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_bit_bash.56526187
Short name T371
Test name
Test status
Simulation time 1509871594 ps
CPU time 7.21 seconds
Started May 14 12:51:42 PM PDT 24
Finished May 14 12:51:51 PM PDT 24
Peak memory 211124 kb
Host smart-f55d5b92-c787-4a56-956b-c7857b739573
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=56526187 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_bit_ba
sh.56526187
Directory /workspace/1.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_hw_reset.82193384
Short name T75
Test name
Test status
Simulation time 2221352532 ps
CPU time 9.18 seconds
Started May 14 12:51:47 PM PDT 24
Finished May 14 12:52:01 PM PDT 24
Peak memory 211280 kb
Host smart-c69d98c2-388b-4063-9fcf-1a9df5c493bd
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82193384 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_hw_res
et.82193384
Directory /workspace/1.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_mem_rw_with_rand_reset.708844626
Short name T415
Test name
Test status
Simulation time 482968983 ps
CPU time 7.49 seconds
Started May 14 12:51:52 PM PDT 24
Finished May 14 12:52:04 PM PDT 24
Peak memory 219516 kb
Host smart-b9582a0e-4748-4053-b308-bcde2b1f9193
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=708844626 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 1.rom_ctrl_csr_mem_rw_with_rand_reset.708844626
Directory /workspace/1.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_rw.1742902660
Short name T449
Test name
Test status
Simulation time 165289521 ps
CPU time 4.24 seconds
Started May 14 12:51:39 PM PDT 24
Finished May 14 12:51:45 PM PDT 24
Peak memory 211188 kb
Host smart-66565b49-7e68-4f5d-bb7b-0e2fc372267e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1742902660 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_rw.1742902660
Directory /workspace/1.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_partial_access.3209850678
Short name T431
Test name
Test status
Simulation time 3804179104 ps
CPU time 10.37 seconds
Started May 14 12:51:46 PM PDT 24
Finished May 14 12:51:59 PM PDT 24
Peak memory 211240 kb
Host smart-60d936f6-d159-4387-ab24-473c2bdb7d78
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3209850678 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctr
l_mem_partial_access.3209850678
Directory /workspace/1.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_walk.3665729541
Short name T450
Test name
Test status
Simulation time 858352245 ps
CPU time 8.92 seconds
Started May 14 12:51:47 PM PDT 24
Finished May 14 12:52:00 PM PDT 24
Peak memory 211116 kb
Host smart-7aa8bbac-6e60-4d1c-8f4c-20bfa91a97f4
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3665729541 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_mem_walk
.3665729541
Directory /workspace/1.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_passthru_mem_tl_intg_err.1074067314
Short name T77
Test name
Test status
Simulation time 17300620812 ps
CPU time 78.42 seconds
Started May 14 12:51:50 PM PDT 24
Finished May 14 12:53:13 PM PDT 24
Peak memory 211312 kb
Host smart-3e46b4e3-a53d-4cb0-84b4-9bcc40b38264
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1074067314 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_pa
ssthru_mem_tl_intg_err.1074067314
Directory /workspace/1.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_same_csr_outstanding.2217734745
Short name T94
Test name
Test status
Simulation time 182848635 ps
CPU time 6.2 seconds
Started May 14 12:51:54 PM PDT 24
Finished May 14 12:52:04 PM PDT 24
Peak memory 211232 kb
Host smart-6c8182a4-7b98-4acf-8d24-6a29d0c65b49
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2217734745 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_c
trl_same_csr_outstanding.2217734745
Directory /workspace/1.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_errors.1374368599
Short name T370
Test name
Test status
Simulation time 1591475915 ps
CPU time 17.44 seconds
Started May 14 12:51:49 PM PDT 24
Finished May 14 12:52:11 PM PDT 24
Peak memory 219500 kb
Host smart-58398601-16b6-4fe7-a5e1-3c1f5f77090f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1374368599 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_tl_errors.1374368599
Directory /workspace/1.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_intg_err.4002945780
Short name T103
Test name
Test status
Simulation time 30530052348 ps
CPU time 47.3 seconds
Started May 14 12:51:47 PM PDT 24
Finished May 14 12:52:38 PM PDT 24
Peak memory 219508 kb
Host smart-73d1c409-67a0-4330-bed0-6e4333a8388e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4002945780 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_tl_in
tg_err.4002945780
Directory /workspace/1.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_mem_rw_with_rand_reset.751380615
Short name T409
Test name
Test status
Simulation time 1209102611 ps
CPU time 10.18 seconds
Started May 14 12:52:01 PM PDT 24
Finished May 14 12:52:14 PM PDT 24
Peak memory 212536 kb
Host smart-a59c0436-5553-43bc-abdb-c3d6f49743aa
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=751380615 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 10.rom_ctrl_csr_mem_rw_with_rand_reset.751380615
Directory /workspace/10.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_rw.917574832
Short name T388
Test name
Test status
Simulation time 22959639322 ps
CPU time 11.14 seconds
Started May 14 12:52:04 PM PDT 24
Finished May 14 12:52:17 PM PDT 24
Peak memory 211300 kb
Host smart-42f01554-0d6b-459c-8f14-f32db4b563f6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=917574832 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_csr_rw.917574832
Directory /workspace/10.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_passthru_mem_tl_intg_err.1370068259
Short name T459
Test name
Test status
Simulation time 3362506075 ps
CPU time 40.16 seconds
Started May 14 12:51:58 PM PDT 24
Finished May 14 12:52:42 PM PDT 24
Peak memory 211404 kb
Host smart-4c647f23-c39b-4e44-972d-500ca7f3b6e2
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1370068259 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_p
assthru_mem_tl_intg_err.1370068259
Directory /workspace/10.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_same_csr_outstanding.159959561
Short name T403
Test name
Test status
Simulation time 500897888 ps
CPU time 4.91 seconds
Started May 14 12:52:01 PM PDT 24
Finished May 14 12:52:09 PM PDT 24
Peak memory 211252 kb
Host smart-58aa2e06-6f45-4053-a6e6-6153720239df
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=159959561 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_c
trl_same_csr_outstanding.159959561
Directory /workspace/10.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_errors.1689588840
Short name T378
Test name
Test status
Simulation time 9821702097 ps
CPU time 14.28 seconds
Started May 14 12:52:04 PM PDT 24
Finished May 14 12:52:21 PM PDT 24
Peak memory 219540 kb
Host smart-5cba793d-f2b4-4433-b29c-a4fdf77da7ad
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1689588840 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_tl_errors.1689588840
Directory /workspace/10.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_mem_rw_with_rand_reset.610217744
Short name T410
Test name
Test status
Simulation time 2627250856 ps
CPU time 11.46 seconds
Started May 14 12:51:58 PM PDT 24
Finished May 14 12:52:13 PM PDT 24
Peak memory 219536 kb
Host smart-52f3d08e-0ca4-4675-b86b-f448f763bb4b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=610217744 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 11.rom_ctrl_csr_mem_rw_with_rand_reset.610217744
Directory /workspace/11.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_rw.1963993945
Short name T392
Test name
Test status
Simulation time 89157418 ps
CPU time 4.22 seconds
Started May 14 12:52:01 PM PDT 24
Finished May 14 12:52:08 PM PDT 24
Peak memory 211228 kb
Host smart-cc309ceb-52d6-4880-a948-a36dde8567a4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1963993945 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_csr_rw.1963993945
Directory /workspace/11.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_passthru_mem_tl_intg_err.1123086854
Short name T460
Test name
Test status
Simulation time 154785032407 ps
CPU time 94.94 seconds
Started May 14 12:51:59 PM PDT 24
Finished May 14 12:53:38 PM PDT 24
Peak memory 211336 kb
Host smart-2f97bad9-0902-4974-a908-d66bbbcae88a
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1123086854 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_p
assthru_mem_tl_intg_err.1123086854
Directory /workspace/11.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_same_csr_outstanding.2696358535
Short name T423
Test name
Test status
Simulation time 2142145361 ps
CPU time 16.92 seconds
Started May 14 12:52:07 PM PDT 24
Finished May 14 12:52:25 PM PDT 24
Peak memory 211232 kb
Host smart-d8485455-5242-4be3-928e-9adf35ebb9c4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2696358535 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_
ctrl_same_csr_outstanding.2696358535
Directory /workspace/11.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_errors.311114738
Short name T384
Test name
Test status
Simulation time 5978634607 ps
CPU time 12.79 seconds
Started May 14 12:52:05 PM PDT 24
Finished May 14 12:52:20 PM PDT 24
Peak memory 219592 kb
Host smart-4b9a04b0-58fc-4145-86d0-52fdad1834e5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=311114738 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_tl_errors.311114738
Directory /workspace/11.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_intg_err.2203535173
Short name T441
Test name
Test status
Simulation time 4505989836 ps
CPU time 47.44 seconds
Started May 14 12:52:06 PM PDT 24
Finished May 14 12:52:55 PM PDT 24
Peak memory 212388 kb
Host smart-a8619a5f-70b8-456e-b7c2-b26329b33e33
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2203535173 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_tl_i
ntg_err.2203535173
Directory /workspace/11.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_mem_rw_with_rand_reset.1141450675
Short name T365
Test name
Test status
Simulation time 105790694 ps
CPU time 4.97 seconds
Started May 14 12:51:58 PM PDT 24
Finished May 14 12:52:07 PM PDT 24
Peak memory 213644 kb
Host smart-3ac1759a-8629-4333-b84c-102b6ea35980
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1141450675 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 12.rom_ctrl_csr_mem_rw_with_rand_reset.1141450675
Directory /workspace/12.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_rw.3069904855
Short name T451
Test name
Test status
Simulation time 2927236080 ps
CPU time 12.45 seconds
Started May 14 12:52:00 PM PDT 24
Finished May 14 12:52:15 PM PDT 24
Peak memory 211296 kb
Host smart-0a11b637-40b4-4fc3-b177-dd3f73ed3133
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3069904855 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_csr_rw.3069904855
Directory /workspace/12.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_passthru_mem_tl_intg_err.1820791595
Short name T79
Test name
Test status
Simulation time 38076585875 ps
CPU time 63.92 seconds
Started May 14 12:52:06 PM PDT 24
Finished May 14 12:53:11 PM PDT 24
Peak memory 211400 kb
Host smart-21090aac-fef6-479f-a63c-0339aa394784
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1820791595 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_p
assthru_mem_tl_intg_err.1820791595
Directory /workspace/12.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_same_csr_outstanding.994324040
Short name T61
Test name
Test status
Simulation time 1941260010 ps
CPU time 17.17 seconds
Started May 14 12:52:01 PM PDT 24
Finished May 14 12:52:21 PM PDT 24
Peak memory 211232 kb
Host smart-925fe792-ad9f-4fe7-89c4-db95396614f0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=994324040 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_c
trl_same_csr_outstanding.994324040
Directory /workspace/12.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_errors.419828366
Short name T393
Test name
Test status
Simulation time 157094418 ps
CPU time 9.46 seconds
Started May 14 12:52:01 PM PDT 24
Finished May 14 12:52:13 PM PDT 24
Peak memory 219508 kb
Host smart-e2992c53-3ffa-4baa-bdd8-967e57a5b3f5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=419828366 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_tl_errors.419828366
Directory /workspace/12.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_intg_err.2390225882
Short name T113
Test name
Test status
Simulation time 250648720 ps
CPU time 68.81 seconds
Started May 14 12:51:59 PM PDT 24
Finished May 14 12:53:11 PM PDT 24
Peak memory 212324 kb
Host smart-36b3162b-a0b7-446c-b8c0-03c4abfa832a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2390225882 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_tl_i
ntg_err.2390225882
Directory /workspace/12.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_mem_rw_with_rand_reset.3125859073
Short name T418
Test name
Test status
Simulation time 9448705550 ps
CPU time 16.71 seconds
Started May 14 12:52:02 PM PDT 24
Finished May 14 12:52:21 PM PDT 24
Peak memory 219524 kb
Host smart-c1ae60d8-a1b9-404c-bff0-d958d27ce0f9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3125859073 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 13.rom_ctrl_csr_mem_rw_with_rand_reset.3125859073
Directory /workspace/13.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_rw.3746036540
Short name T59
Test name
Test status
Simulation time 332997820 ps
CPU time 4.2 seconds
Started May 14 12:52:05 PM PDT 24
Finished May 14 12:52:11 PM PDT 24
Peak memory 211232 kb
Host smart-5ae69831-541f-4fd9-ac41-7d73c4eb2678
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3746036540 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_csr_rw.3746036540
Directory /workspace/13.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_passthru_mem_tl_intg_err.1011395468
Short name T76
Test name
Test status
Simulation time 15318483736 ps
CPU time 75.37 seconds
Started May 14 12:52:00 PM PDT 24
Finished May 14 12:53:18 PM PDT 24
Peak memory 211300 kb
Host smart-885f1444-1b92-475f-9333-ab5f3944a472
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1011395468 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_p
assthru_mem_tl_intg_err.1011395468
Directory /workspace/13.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_same_csr_outstanding.1516577843
Short name T438
Test name
Test status
Simulation time 8757735943 ps
CPU time 14.95 seconds
Started May 14 12:52:04 PM PDT 24
Finished May 14 12:52:21 PM PDT 24
Peak memory 211304 kb
Host smart-963630fb-29c7-459f-9d9a-0aa6c98cc0b1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1516577843 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_
ctrl_same_csr_outstanding.1516577843
Directory /workspace/13.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_errors.4182483511
Short name T369
Test name
Test status
Simulation time 4221545884 ps
CPU time 17.19 seconds
Started May 14 12:52:04 PM PDT 24
Finished May 14 12:52:23 PM PDT 24
Peak memory 219564 kb
Host smart-a4c30324-1d5b-4d22-886a-ea1ac89e1cc2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4182483511 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_tl_errors.4182483511
Directory /workspace/13.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_intg_err.3323981609
Short name T111
Test name
Test status
Simulation time 488719413 ps
CPU time 70.61 seconds
Started May 14 12:52:06 PM PDT 24
Finished May 14 12:53:19 PM PDT 24
Peak memory 212088 kb
Host smart-90679d5e-8b23-43cf-92b2-8afe899e80f3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3323981609 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_tl_i
ntg_err.3323981609
Directory /workspace/13.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_mem_rw_with_rand_reset.3691626190
Short name T364
Test name
Test status
Simulation time 1785605155 ps
CPU time 8.24 seconds
Started May 14 12:52:01 PM PDT 24
Finished May 14 12:52:12 PM PDT 24
Peak memory 219460 kb
Host smart-4e25cc09-2eb5-4967-b2bb-798442c8ec1b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3691626190 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 14.rom_ctrl_csr_mem_rw_with_rand_reset.3691626190
Directory /workspace/14.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_rw.909902859
Short name T445
Test name
Test status
Simulation time 2670175438 ps
CPU time 12.09 seconds
Started May 14 12:51:58 PM PDT 24
Finished May 14 12:52:14 PM PDT 24
Peak memory 211248 kb
Host smart-41e45579-1029-4f49-b0b6-4a311cf0e9e2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=909902859 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_csr_rw.909902859
Directory /workspace/14.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_passthru_mem_tl_intg_err.3172223169
Short name T444
Test name
Test status
Simulation time 20685421317 ps
CPU time 84.55 seconds
Started May 14 12:52:06 PM PDT 24
Finished May 14 12:53:32 PM PDT 24
Peak memory 211284 kb
Host smart-6ae76ec9-ce3c-4f9e-81e8-61ef4317e1c9
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3172223169 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_p
assthru_mem_tl_intg_err.3172223169
Directory /workspace/14.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_same_csr_outstanding.2514510170
Short name T406
Test name
Test status
Simulation time 2828452161 ps
CPU time 8.64 seconds
Started May 14 12:51:59 PM PDT 24
Finished May 14 12:52:11 PM PDT 24
Peak memory 211348 kb
Host smart-3c398795-ee79-4dc5-87be-07f50bdb389d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2514510170 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_
ctrl_same_csr_outstanding.2514510170
Directory /workspace/14.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_errors.3307345462
Short name T396
Test name
Test status
Simulation time 250968594 ps
CPU time 8.37 seconds
Started May 14 12:52:06 PM PDT 24
Finished May 14 12:52:16 PM PDT 24
Peak memory 219504 kb
Host smart-8237f514-a3e5-4ee8-a9c4-cf55543791d8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3307345462 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_tl_errors.3307345462
Directory /workspace/14.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_intg_err.2425743193
Short name T48
Test name
Test status
Simulation time 368164267 ps
CPU time 37.19 seconds
Started May 14 12:52:05 PM PDT 24
Finished May 14 12:52:44 PM PDT 24
Peak memory 212220 kb
Host smart-6ceb7921-4968-4c39-bcf7-078e07fd54cf
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2425743193 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_tl_i
ntg_err.2425743193
Directory /workspace/14.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_mem_rw_with_rand_reset.628373113
Short name T413
Test name
Test status
Simulation time 99264878 ps
CPU time 4.69 seconds
Started May 14 12:52:14 PM PDT 24
Finished May 14 12:52:20 PM PDT 24
Peak memory 219508 kb
Host smart-393e3670-8b13-4c06-a3b4-7c32985aad44
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=628373113 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 15.rom_ctrl_csr_mem_rw_with_rand_reset.628373113
Directory /workspace/15.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_rw.334642239
Short name T57
Test name
Test status
Simulation time 830198851 ps
CPU time 8.7 seconds
Started May 14 12:52:04 PM PDT 24
Finished May 14 12:52:14 PM PDT 24
Peak memory 211256 kb
Host smart-df16c3c2-6dfa-4cb0-8028-68f3f39ff37d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=334642239 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_csr_rw.334642239
Directory /workspace/15.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_passthru_mem_tl_intg_err.1974552799
Short name T62
Test name
Test status
Simulation time 25812225257 ps
CPU time 65.15 seconds
Started May 14 12:52:00 PM PDT 24
Finished May 14 12:53:08 PM PDT 24
Peak memory 211596 kb
Host smart-9cb96ecd-ed7e-4517-87ea-d516faae2051
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1974552799 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_p
assthru_mem_tl_intg_err.1974552799
Directory /workspace/15.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_same_csr_outstanding.1064729515
Short name T462
Test name
Test status
Simulation time 6781527786 ps
CPU time 15.25 seconds
Started May 14 12:52:10 PM PDT 24
Finished May 14 12:52:27 PM PDT 24
Peak memory 211232 kb
Host smart-3ff9c1fd-8d58-4987-9dfa-2844a8bb0484
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1064729515 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_
ctrl_same_csr_outstanding.1064729515
Directory /workspace/15.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_errors.2712814441
Short name T427
Test name
Test status
Simulation time 2037172154 ps
CPU time 20.46 seconds
Started May 14 12:52:00 PM PDT 24
Finished May 14 12:52:23 PM PDT 24
Peak memory 219532 kb
Host smart-f789d705-f210-403b-8de2-8fa964507a3f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2712814441 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_tl_errors.2712814441
Directory /workspace/15.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_intg_err.3043087696
Short name T49
Test name
Test status
Simulation time 7384590215 ps
CPU time 46.71 seconds
Started May 14 12:51:59 PM PDT 24
Finished May 14 12:52:49 PM PDT 24
Peak memory 212156 kb
Host smart-f80fe9e8-96e4-4e98-94c0-eae2ad0c85ad
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3043087696 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_tl_i
ntg_err.3043087696
Directory /workspace/15.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_mem_rw_with_rand_reset.2161219397
Short name T446
Test name
Test status
Simulation time 94195525 ps
CPU time 4.48 seconds
Started May 14 12:52:08 PM PDT 24
Finished May 14 12:52:13 PM PDT 24
Peak memory 214004 kb
Host smart-27ddb269-f6ce-4c3a-9ef7-9dd3c32d4090
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2161219397 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 16.rom_ctrl_csr_mem_rw_with_rand_reset.2161219397
Directory /workspace/16.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_rw.949021399
Short name T60
Test name
Test status
Simulation time 851839190 ps
CPU time 9.27 seconds
Started May 14 12:52:12 PM PDT 24
Finished May 14 12:52:23 PM PDT 24
Peak memory 211196 kb
Host smart-d1896fd4-bb46-4470-b06c-09d3972646d6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=949021399 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_csr_rw.949021399
Directory /workspace/16.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_passthru_mem_tl_intg_err.1380732787
Short name T81
Test name
Test status
Simulation time 24783269834 ps
CPU time 50 seconds
Started May 14 12:52:09 PM PDT 24
Finished May 14 12:53:01 PM PDT 24
Peak memory 211356 kb
Host smart-50c488a6-3887-4928-996b-70970034df72
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1380732787 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_p
assthru_mem_tl_intg_err.1380732787
Directory /workspace/16.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_same_csr_outstanding.1748939297
Short name T399
Test name
Test status
Simulation time 94678659 ps
CPU time 6.04 seconds
Started May 14 12:52:12 PM PDT 24
Finished May 14 12:52:20 PM PDT 24
Peak memory 211108 kb
Host smart-4d0b0c73-8907-4f19-af6a-13d3db961158
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1748939297 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_
ctrl_same_csr_outstanding.1748939297
Directory /workspace/16.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_errors.1767633263
Short name T394
Test name
Test status
Simulation time 1116649263 ps
CPU time 13.31 seconds
Started May 14 12:52:09 PM PDT 24
Finished May 14 12:52:25 PM PDT 24
Peak memory 219752 kb
Host smart-f278d756-6a11-46d8-b87d-da1c5c9c8f69
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1767633263 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_tl_errors.1767633263
Directory /workspace/16.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_mem_rw_with_rand_reset.4146298062
Short name T461
Test name
Test status
Simulation time 4206976839 ps
CPU time 9.12 seconds
Started May 14 12:52:09 PM PDT 24
Finished May 14 12:52:20 PM PDT 24
Peak memory 219524 kb
Host smart-b427dfb2-3646-4f55-8733-ac10784f68c0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4146298062 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 17.rom_ctrl_csr_mem_rw_with_rand_reset.4146298062
Directory /workspace/17.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_rw.2795244945
Short name T395
Test name
Test status
Simulation time 332961807 ps
CPU time 4.19 seconds
Started May 14 12:52:10 PM PDT 24
Finished May 14 12:52:16 PM PDT 24
Peak memory 211156 kb
Host smart-8d7be571-1f37-48d5-8609-27cb0fbfa40c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2795244945 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_csr_rw.2795244945
Directory /workspace/17.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_passthru_mem_tl_intg_err.288226838
Short name T73
Test name
Test status
Simulation time 1043617479 ps
CPU time 27.91 seconds
Started May 14 12:52:09 PM PDT 24
Finished May 14 12:52:38 PM PDT 24
Peak memory 211280 kb
Host smart-c3f1fc5b-c77b-4160-8b60-345bb34028d5
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=288226838 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_pa
ssthru_mem_tl_intg_err.288226838
Directory /workspace/17.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_same_csr_outstanding.924907264
Short name T63
Test name
Test status
Simulation time 5270165737 ps
CPU time 12.44 seconds
Started May 14 12:52:09 PM PDT 24
Finished May 14 12:52:23 PM PDT 24
Peak memory 211328 kb
Host smart-5d86c164-6c90-463e-b67b-4efc4d5ec5fe
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=924907264 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_c
trl_same_csr_outstanding.924907264
Directory /workspace/17.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_errors.1235124008
Short name T376
Test name
Test status
Simulation time 858477451 ps
CPU time 10.27 seconds
Started May 14 12:52:09 PM PDT 24
Finished May 14 12:52:21 PM PDT 24
Peak memory 215608 kb
Host smart-c48de007-4fc4-4b97-ad79-4345730291bf
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1235124008 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_tl_errors.1235124008
Directory /workspace/17.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_intg_err.1950858464
Short name T429
Test name
Test status
Simulation time 7887493892 ps
CPU time 45.47 seconds
Started May 14 12:52:10 PM PDT 24
Finished May 14 12:52:57 PM PDT 24
Peak memory 212120 kb
Host smart-209e99d9-c5f1-4bd2-9627-1512f1b90260
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1950858464 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_tl_i
ntg_err.1950858464
Directory /workspace/17.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_mem_rw_with_rand_reset.3312872109
Short name T405
Test name
Test status
Simulation time 2406190669 ps
CPU time 7.93 seconds
Started May 14 12:52:11 PM PDT 24
Finished May 14 12:52:21 PM PDT 24
Peak memory 212156 kb
Host smart-cde9d923-b258-4bdc-a210-a392cd9c5476
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3312872109 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 18.rom_ctrl_csr_mem_rw_with_rand_reset.3312872109
Directory /workspace/18.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_rw.1903689477
Short name T448
Test name
Test status
Simulation time 3221621514 ps
CPU time 13.61 seconds
Started May 14 12:52:10 PM PDT 24
Finished May 14 12:52:26 PM PDT 24
Peak memory 211292 kb
Host smart-a6cfafe3-38b3-410d-88af-ea2df3c9c633
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1903689477 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_csr_rw.1903689477
Directory /workspace/18.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_passthru_mem_tl_intg_err.2875200605
Short name T383
Test name
Test status
Simulation time 95828645312 ps
CPU time 72.51 seconds
Started May 14 12:52:12 PM PDT 24
Finished May 14 12:53:26 PM PDT 24
Peak memory 211224 kb
Host smart-67a696bb-697d-43f4-8b3c-6ca368425e70
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2875200605 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_p
assthru_mem_tl_intg_err.2875200605
Directory /workspace/18.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_same_csr_outstanding.2530770825
Short name T408
Test name
Test status
Simulation time 2574936098 ps
CPU time 11.89 seconds
Started May 14 12:52:09 PM PDT 24
Finished May 14 12:52:23 PM PDT 24
Peak memory 211328 kb
Host smart-ff4998b0-e54c-409c-b35e-15b3ed51bec9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2530770825 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_
ctrl_same_csr_outstanding.2530770825
Directory /workspace/18.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_errors.3915548212
Short name T452
Test name
Test status
Simulation time 8473677454 ps
CPU time 19.19 seconds
Started May 14 12:52:10 PM PDT 24
Finished May 14 12:52:32 PM PDT 24
Peak memory 219532 kb
Host smart-6668cb37-0f11-48e4-aba2-8bc707aeb8bc
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3915548212 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_tl_errors.3915548212
Directory /workspace/18.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_intg_err.2904875677
Short name T442
Test name
Test status
Simulation time 2281255627 ps
CPU time 78.62 seconds
Started May 14 12:52:08 PM PDT 24
Finished May 14 12:53:27 PM PDT 24
Peak memory 212224 kb
Host smart-90a9597b-5266-470d-ab98-b8d21eb3d30e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2904875677 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_tl_i
ntg_err.2904875677
Directory /workspace/18.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_mem_rw_with_rand_reset.1243810275
Short name T373
Test name
Test status
Simulation time 2415819509 ps
CPU time 14.92 seconds
Started May 14 12:52:09 PM PDT 24
Finished May 14 12:52:26 PM PDT 24
Peak memory 219528 kb
Host smart-cfcdbe53-3472-48ab-9e12-bd3212dfc409
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1243810275 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 19.rom_ctrl_csr_mem_rw_with_rand_reset.1243810275
Directory /workspace/19.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_rw.757679545
Short name T458
Test name
Test status
Simulation time 85434080 ps
CPU time 4.25 seconds
Started May 14 12:52:11 PM PDT 24
Finished May 14 12:52:17 PM PDT 24
Peak memory 211192 kb
Host smart-abfc5bc7-b074-4fd5-a5de-98b1160d2748
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=757679545 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_csr_rw.757679545
Directory /workspace/19.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_same_csr_outstanding.1676450402
Short name T414
Test name
Test status
Simulation time 1910637211 ps
CPU time 8.61 seconds
Started May 14 12:52:10 PM PDT 24
Finished May 14 12:52:21 PM PDT 24
Peak memory 211132 kb
Host smart-5e5f064d-8d9a-4333-bae1-7b17ff35f1d7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1676450402 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_
ctrl_same_csr_outstanding.1676450402
Directory /workspace/19.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_errors.509429609
Short name T372
Test name
Test status
Simulation time 5074351107 ps
CPU time 11.33 seconds
Started May 14 12:52:12 PM PDT 24
Finished May 14 12:52:25 PM PDT 24
Peak memory 219604 kb
Host smart-aeca6d51-2894-4b58-a07b-08a1af19fad4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=509429609 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_tl_errors.509429609
Directory /workspace/19.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_intg_err.971345245
Short name T390
Test name
Test status
Simulation time 367891703 ps
CPU time 37.23 seconds
Started May 14 12:52:09 PM PDT 24
Finished May 14 12:52:48 PM PDT 24
Peak memory 212160 kb
Host smart-922ba946-5c0c-4674-b113-302d449b8990
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=971345245 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_tl_in
tg_err.971345245
Directory /workspace/19.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_aliasing.1676871416
Short name T80
Test name
Test status
Simulation time 348191909 ps
CPU time 4.32 seconds
Started May 14 12:51:50 PM PDT 24
Finished May 14 12:51:59 PM PDT 24
Peak memory 211308 kb
Host smart-ea2a1eba-f1d2-4c94-9506-98912f5d7205
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1676871416 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_alia
sing.1676871416
Directory /workspace/2.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_bit_bash.3225445710
Short name T400
Test name
Test status
Simulation time 2339460046 ps
CPU time 16.56 seconds
Started May 14 12:51:45 PM PDT 24
Finished May 14 12:52:04 PM PDT 24
Peak memory 211248 kb
Host smart-fa16ff17-fe8a-4894-a4b1-750d39398bc2
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3225445710 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_bit_
bash.3225445710
Directory /workspace/2.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_hw_reset.2412783104
Short name T55
Test name
Test status
Simulation time 639397090 ps
CPU time 9.99 seconds
Started May 14 12:52:02 PM PDT 24
Finished May 14 12:52:14 PM PDT 24
Peak memory 211264 kb
Host smart-eaac218a-ec62-4fd7-bdc3-480daabd0f1c
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2412783104 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_hw_r
eset.2412783104
Directory /workspace/2.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_mem_rw_with_rand_reset.3338431099
Short name T367
Test name
Test status
Simulation time 90925039 ps
CPU time 4.5 seconds
Started May 14 12:51:50 PM PDT 24
Finished May 14 12:51:59 PM PDT 24
Peak memory 213924 kb
Host smart-ccee1542-bebe-4d17-9efa-1c15f8219e54
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3338431099 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 2.rom_ctrl_csr_mem_rw_with_rand_reset.3338431099
Directory /workspace/2.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_rw.2599474521
Short name T456
Test name
Test status
Simulation time 2448276156 ps
CPU time 14.96 seconds
Started May 14 12:51:49 PM PDT 24
Finished May 14 12:52:08 PM PDT 24
Peak memory 211288 kb
Host smart-7f29d355-3b09-41fb-a283-8b9153d99ac0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2599474521 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_rw.2599474521
Directory /workspace/2.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_partial_access.2313860679
Short name T430
Test name
Test status
Simulation time 6159035846 ps
CPU time 13.34 seconds
Started May 14 12:51:46 PM PDT 24
Finished May 14 12:52:02 PM PDT 24
Peak memory 211176 kb
Host smart-372ae833-99f3-4f94-9161-475b8198134c
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2313860679 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctr
l_mem_partial_access.2313860679
Directory /workspace/2.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_walk.4285257234
Short name T382
Test name
Test status
Simulation time 3876999746 ps
CPU time 15.6 seconds
Started May 14 12:51:47 PM PDT 24
Finished May 14 12:52:07 PM PDT 24
Peak memory 211284 kb
Host smart-28427fcf-457a-4754-bb98-45ea17a71a98
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4285257234 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_mem_walk
.4285257234
Directory /workspace/2.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_passthru_mem_tl_intg_err.4020005002
Short name T101
Test name
Test status
Simulation time 4766181566 ps
CPU time 46.55 seconds
Started May 14 12:51:49 PM PDT 24
Finished May 14 12:52:40 PM PDT 24
Peak memory 211312 kb
Host smart-38ff448a-97e0-4dd9-a0d0-9e77ba2cff05
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4020005002 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_pa
ssthru_mem_tl_intg_err.4020005002
Directory /workspace/2.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_same_csr_outstanding.4075689840
Short name T439
Test name
Test status
Simulation time 3415042192 ps
CPU time 12.15 seconds
Started May 14 12:51:49 PM PDT 24
Finished May 14 12:52:06 PM PDT 24
Peak memory 211276 kb
Host smart-97eed577-015c-4482-a25a-71b5a33981f9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4075689840 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_c
trl_same_csr_outstanding.4075689840
Directory /workspace/2.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_errors.1520564025
Short name T417
Test name
Test status
Simulation time 3630980827 ps
CPU time 16.11 seconds
Started May 14 12:51:47 PM PDT 24
Finished May 14 12:52:07 PM PDT 24
Peak memory 219528 kb
Host smart-570edfc7-2229-4524-9467-d1e73dafd60a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1520564025 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_tl_errors.1520564025
Directory /workspace/2.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_aliasing.2056695327
Short name T51
Test name
Test status
Simulation time 7828503285 ps
CPU time 15.17 seconds
Started May 14 12:51:59 PM PDT 24
Finished May 14 12:52:17 PM PDT 24
Peak memory 211220 kb
Host smart-b4873378-5d70-40a2-8555-88919b2d9cac
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2056695327 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_alia
sing.2056695327
Directory /workspace/3.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_bit_bash.157582889
Short name T434
Test name
Test status
Simulation time 8486320675 ps
CPU time 17.57 seconds
Started May 14 12:51:51 PM PDT 24
Finished May 14 12:52:13 PM PDT 24
Peak memory 211340 kb
Host smart-6e4ad706-0d03-40ee-91ce-b29e46b655ce
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=157582889 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_bit_b
ash.157582889
Directory /workspace/3.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_hw_reset.2175899382
Short name T425
Test name
Test status
Simulation time 356482767 ps
CPU time 5.7 seconds
Started May 14 12:52:04 PM PDT 24
Finished May 14 12:52:12 PM PDT 24
Peak memory 211224 kb
Host smart-b9307403-d526-4ca2-8b09-d0e24c051c08
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2175899382 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_hw_r
eset.2175899382
Directory /workspace/3.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_mem_rw_with_rand_reset.2168706425
Short name T411
Test name
Test status
Simulation time 2887836994 ps
CPU time 12.56 seconds
Started May 14 12:51:48 PM PDT 24
Finished May 14 12:52:05 PM PDT 24
Peak memory 219584 kb
Host smart-3ace0bb5-db32-49eb-aef4-166ca361df20
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2168706425 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 3.rom_ctrl_csr_mem_rw_with_rand_reset.2168706425
Directory /workspace/3.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_rw.607451331
Short name T443
Test name
Test status
Simulation time 755209870 ps
CPU time 4.08 seconds
Started May 14 12:51:59 PM PDT 24
Finished May 14 12:52:06 PM PDT 24
Peak memory 211136 kb
Host smart-e055ff00-5797-432e-91d7-a840fbe3642a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=607451331 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_rw.607451331
Directory /workspace/3.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_partial_access.1095658634
Short name T385
Test name
Test status
Simulation time 691847802 ps
CPU time 8.27 seconds
Started May 14 12:51:44 PM PDT 24
Finished May 14 12:51:55 PM PDT 24
Peak memory 211056 kb
Host smart-ead0c246-46bc-40cd-9287-630bd2d9f587
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1095658634 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctr
l_mem_partial_access.1095658634
Directory /workspace/3.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_walk.2930604393
Short name T377
Test name
Test status
Simulation time 333606767 ps
CPU time 4 seconds
Started May 14 12:52:02 PM PDT 24
Finished May 14 12:52:08 PM PDT 24
Peak memory 211192 kb
Host smart-45b62709-0af0-452c-aad3-a08aed5fda3c
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2930604393 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_mem_walk
.2930604393
Directory /workspace/3.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_passthru_mem_tl_intg_err.884998709
Short name T379
Test name
Test status
Simulation time 383440426 ps
CPU time 19 seconds
Started May 14 12:51:51 PM PDT 24
Finished May 14 12:52:15 PM PDT 24
Peak memory 211280 kb
Host smart-4c01ad86-dd7b-48f1-a7f0-75eba3c40052
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=884998709 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_pas
sthru_mem_tl_intg_err.884998709
Directory /workspace/3.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_same_csr_outstanding.2368679971
Short name T447
Test name
Test status
Simulation time 1253998249 ps
CPU time 13.66 seconds
Started May 14 12:51:50 PM PDT 24
Finished May 14 12:52:09 PM PDT 24
Peak memory 211272 kb
Host smart-979a2657-14c3-435a-b087-73af29016b5b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2368679971 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_c
trl_same_csr_outstanding.2368679971
Directory /workspace/3.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_errors.843057415
Short name T437
Test name
Test status
Simulation time 1623911344 ps
CPU time 16.66 seconds
Started May 14 12:51:51 PM PDT 24
Finished May 14 12:52:12 PM PDT 24
Peak memory 219552 kb
Host smart-661ebec7-da6a-40a9-83c5-623467f29595
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=843057415 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_tl_errors.843057415
Directory /workspace/3.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_intg_err.439482226
Short name T109
Test name
Test status
Simulation time 1432025175 ps
CPU time 37.51 seconds
Started May 14 12:51:50 PM PDT 24
Finished May 14 12:52:32 PM PDT 24
Peak memory 211228 kb
Host smart-b6919431-4309-4f3c-96ae-f34f3c61aa31
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=439482226 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_tl_int
g_err.439482226
Directory /workspace/3.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_aliasing.2811601053
Short name T98
Test name
Test status
Simulation time 1881816400 ps
CPU time 10.02 seconds
Started May 14 12:51:55 PM PDT 24
Finished May 14 12:52:08 PM PDT 24
Peak memory 211288 kb
Host smart-a19f9e86-f697-4160-a598-6dee508af1cf
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2811601053 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_alia
sing.2811601053
Directory /workspace/4.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_bit_bash.1961660464
Short name T397
Test name
Test status
Simulation time 2171686663 ps
CPU time 16.12 seconds
Started May 14 12:51:46 PM PDT 24
Finished May 14 12:52:07 PM PDT 24
Peak memory 211344 kb
Host smart-b989fdaf-02bf-4dec-982e-ff001aef2419
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1961660464 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_bit_
bash.1961660464
Directory /workspace/4.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_hw_reset.4075324394
Short name T71
Test name
Test status
Simulation time 89553779 ps
CPU time 5.79 seconds
Started May 14 12:51:49 PM PDT 24
Finished May 14 12:51:59 PM PDT 24
Peak memory 211288 kb
Host smart-6a324e04-8f77-4cc8-9e78-46de61f1f5bc
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4075324394 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_hw_r
eset.4075324394
Directory /workspace/4.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_mem_rw_with_rand_reset.3448131571
Short name T366
Test name
Test status
Simulation time 445473508 ps
CPU time 7.32 seconds
Started May 14 12:52:03 PM PDT 24
Finished May 14 12:52:12 PM PDT 24
Peak memory 219452 kb
Host smart-c15f6724-4f4b-4967-a83d-197f0f5f1aa4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3448131571 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 4.rom_ctrl_csr_mem_rw_with_rand_reset.3448131571
Directory /workspace/4.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_rw.2607775849
Short name T58
Test name
Test status
Simulation time 3249235714 ps
CPU time 9.45 seconds
Started May 14 12:51:50 PM PDT 24
Finished May 14 12:52:04 PM PDT 24
Peak memory 211376 kb
Host smart-386d2c4e-c9aa-4bee-a2bf-ee82c133b114
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2607775849 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_rw.2607775849
Directory /workspace/4.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_partial_access.4148044062
Short name T375
Test name
Test status
Simulation time 2013253267 ps
CPU time 9.88 seconds
Started May 14 12:51:49 PM PDT 24
Finished May 14 12:52:04 PM PDT 24
Peak memory 210976 kb
Host smart-57fd2a47-64f4-4d4e-a64d-703009be2cf4
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4148044062 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctr
l_mem_partial_access.4148044062
Directory /workspace/4.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_walk.1501606815
Short name T389
Test name
Test status
Simulation time 2028089910 ps
CPU time 15.91 seconds
Started May 14 12:51:49 PM PDT 24
Finished May 14 12:52:09 PM PDT 24
Peak memory 211180 kb
Host smart-4953c8df-e4f9-42e0-8760-a339ed98eb77
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1501606815 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_mem_walk
.1501606815
Directory /workspace/4.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_passthru_mem_tl_intg_err.3360418538
Short name T95
Test name
Test status
Simulation time 378153142 ps
CPU time 18.55 seconds
Started May 14 12:51:53 PM PDT 24
Finished May 14 12:52:16 PM PDT 24
Peak memory 211248 kb
Host smart-e115d42e-cf17-49d9-9b3d-4ec018f3e5d7
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3360418538 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_pa
ssthru_mem_tl_intg_err.3360418538
Directory /workspace/4.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_same_csr_outstanding.2907117088
Short name T92
Test name
Test status
Simulation time 4781964824 ps
CPU time 11.58 seconds
Started May 14 12:51:52 PM PDT 24
Finished May 14 12:52:08 PM PDT 24
Peak memory 211308 kb
Host smart-f285a6ec-3fb1-41d8-99e6-d7097aaa8c91
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2907117088 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_c
trl_same_csr_outstanding.2907117088
Directory /workspace/4.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_errors.693439586
Short name T391
Test name
Test status
Simulation time 976986710 ps
CPU time 12.22 seconds
Started May 14 12:51:49 PM PDT 24
Finished May 14 12:52:05 PM PDT 24
Peak memory 219436 kb
Host smart-eee903ce-5d90-47d3-bdbf-322a2a3ef0e4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=693439586 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_tl_errors.693439586
Directory /workspace/4.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_mem_rw_with_rand_reset.2623815980
Short name T433
Test name
Test status
Simulation time 14194112844 ps
CPU time 12.58 seconds
Started May 14 12:51:56 PM PDT 24
Finished May 14 12:52:12 PM PDT 24
Peak memory 219604 kb
Host smart-63b8c401-b6e5-4fc0-af0e-adc11ab954f8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2623815980 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 5.rom_ctrl_csr_mem_rw_with_rand_reset.2623815980
Directory /workspace/5.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_rw.2354599052
Short name T97
Test name
Test status
Simulation time 4101910251 ps
CPU time 10.53 seconds
Started May 14 12:52:01 PM PDT 24
Finished May 14 12:52:15 PM PDT 24
Peak memory 211168 kb
Host smart-d3714aa0-97e7-4ae4-9481-561a9206a00d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2354599052 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_csr_rw.2354599052
Directory /workspace/5.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_passthru_mem_tl_intg_err.143099600
Short name T74
Test name
Test status
Simulation time 1017032711 ps
CPU time 25.27 seconds
Started May 14 12:51:58 PM PDT 24
Finished May 14 12:52:27 PM PDT 24
Peak memory 211288 kb
Host smart-e06ac9f3-2a8c-4203-ad1f-5625848a323a
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=143099600 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_pas
sthru_mem_tl_intg_err.143099600
Directory /workspace/5.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_same_csr_outstanding.3520597737
Short name T420
Test name
Test status
Simulation time 337898239 ps
CPU time 5.39 seconds
Started May 14 12:51:57 PM PDT 24
Finished May 14 12:52:06 PM PDT 24
Peak memory 211248 kb
Host smart-a95c2b2f-1957-4a27-953d-df2dec2a15ef
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3520597737 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_c
trl_same_csr_outstanding.3520597737
Directory /workspace/5.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_errors.1027025307
Short name T435
Test name
Test status
Simulation time 4974066686 ps
CPU time 14.55 seconds
Started May 14 12:51:52 PM PDT 24
Finished May 14 12:52:11 PM PDT 24
Peak memory 219548 kb
Host smart-1f087c7d-5fe1-4807-8b5d-0e065c3de24e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1027025307 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_tl_errors.1027025307
Directory /workspace/5.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_intg_err.1513267052
Short name T110
Test name
Test status
Simulation time 5766821511 ps
CPU time 43.57 seconds
Started May 14 12:51:55 PM PDT 24
Finished May 14 12:52:42 PM PDT 24
Peak memory 212488 kb
Host smart-e053d4b6-3a1d-4cd3-83fa-2e9df9c0fa84
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1513267052 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_tl_in
tg_err.1513267052
Directory /workspace/5.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_mem_rw_with_rand_reset.3051780580
Short name T426
Test name
Test status
Simulation time 1531187807 ps
CPU time 13.47 seconds
Started May 14 12:51:52 PM PDT 24
Finished May 14 12:52:10 PM PDT 24
Peak memory 219512 kb
Host smart-c1376552-5a38-4687-b955-d7a440fbe42d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3051780580 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 6.rom_ctrl_csr_mem_rw_with_rand_reset.3051780580
Directory /workspace/6.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_rw.4097100030
Short name T387
Test name
Test status
Simulation time 3277441790 ps
CPU time 8.79 seconds
Started May 14 12:51:57 PM PDT 24
Finished May 14 12:52:09 PM PDT 24
Peak memory 211280 kb
Host smart-f6ffd86c-d29e-43bd-9ac3-752574ef45b6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4097100030 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_csr_rw.4097100030
Directory /workspace/6.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_passthru_mem_tl_intg_err.3779738514
Short name T82
Test name
Test status
Simulation time 9426935206 ps
CPU time 78.5 seconds
Started May 14 12:52:08 PM PDT 24
Finished May 14 12:53:28 PM PDT 24
Peak memory 211344 kb
Host smart-04676d89-f9e3-489d-8585-fa4244332424
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3779738514 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_pa
ssthru_mem_tl_intg_err.3779738514
Directory /workspace/6.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_same_csr_outstanding.2610542297
Short name T93
Test name
Test status
Simulation time 9478610601 ps
CPU time 17.28 seconds
Started May 14 12:51:57 PM PDT 24
Finished May 14 12:52:18 PM PDT 24
Peak memory 211288 kb
Host smart-27d6c37a-b64d-4fa2-9558-b3af023d2e46
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2610542297 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_c
trl_same_csr_outstanding.2610542297
Directory /workspace/6.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_errors.2142630040
Short name T440
Test name
Test status
Simulation time 3220566450 ps
CPU time 13.04 seconds
Started May 14 12:51:55 PM PDT 24
Finished May 14 12:52:11 PM PDT 24
Peak memory 219524 kb
Host smart-de214541-ba2b-4211-a856-124f2d918dda
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2142630040 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_tl_errors.2142630040
Directory /workspace/6.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_intg_err.3491414607
Short name T106
Test name
Test status
Simulation time 9831773970 ps
CPU time 70.4 seconds
Started May 14 12:51:59 PM PDT 24
Finished May 14 12:53:13 PM PDT 24
Peak memory 219520 kb
Host smart-661604af-6021-422f-a7ee-16443354960f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3491414607 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_tl_in
tg_err.3491414607
Directory /workspace/6.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_mem_rw_with_rand_reset.3942939334
Short name T374
Test name
Test status
Simulation time 617637617 ps
CPU time 7.42 seconds
Started May 14 12:51:56 PM PDT 24
Finished May 14 12:52:07 PM PDT 24
Peak memory 219484 kb
Host smart-cc08e12a-b3ea-46f1-892e-dbb73216020a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3942939334 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 7.rom_ctrl_csr_mem_rw_with_rand_reset.3942939334
Directory /workspace/7.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_rw.225843748
Short name T386
Test name
Test status
Simulation time 13049858108 ps
CPU time 12.63 seconds
Started May 14 12:52:04 PM PDT 24
Finished May 14 12:52:19 PM PDT 24
Peak memory 211312 kb
Host smart-cace91ff-afd0-46f8-99fa-e3df6bc25695
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=225843748 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_csr_rw.225843748
Directory /workspace/7.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_passthru_mem_tl_intg_err.1886209140
Short name T412
Test name
Test status
Simulation time 15846833961 ps
CPU time 73.72 seconds
Started May 14 12:52:03 PM PDT 24
Finished May 14 12:53:19 PM PDT 24
Peak memory 211344 kb
Host smart-5cc0fc45-bbc6-4421-964a-08fbbe1eb1c9
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1886209140 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_pa
ssthru_mem_tl_intg_err.1886209140
Directory /workspace/7.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_same_csr_outstanding.3551604809
Short name T453
Test name
Test status
Simulation time 2006563140 ps
CPU time 16.59 seconds
Started May 14 12:51:56 PM PDT 24
Finished May 14 12:52:16 PM PDT 24
Peak memory 211264 kb
Host smart-4adfaac4-2ac5-4222-a584-8b9515377159
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3551604809 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_c
trl_same_csr_outstanding.3551604809
Directory /workspace/7.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_errors.2775260386
Short name T428
Test name
Test status
Simulation time 290476287 ps
CPU time 10.87 seconds
Started May 14 12:51:52 PM PDT 24
Finished May 14 12:52:07 PM PDT 24
Peak memory 219568 kb
Host smart-df7edeba-afb1-4ad6-9ec6-888652137b28
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2775260386 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_tl_errors.2775260386
Directory /workspace/7.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_intg_err.2895611521
Short name T112
Test name
Test status
Simulation time 1897598093 ps
CPU time 77.56 seconds
Started May 14 12:51:57 PM PDT 24
Finished May 14 12:53:19 PM PDT 24
Peak memory 212136 kb
Host smart-7ec2b348-7b2d-4cd5-80c1-3704b4dd1cbf
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2895611521 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_tl_in
tg_err.2895611521
Directory /workspace/7.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_mem_rw_with_rand_reset.315846153
Short name T457
Test name
Test status
Simulation time 103100752 ps
CPU time 5.32 seconds
Started May 14 12:51:57 PM PDT 24
Finished May 14 12:52:06 PM PDT 24
Peak memory 219484 kb
Host smart-f678b121-000e-4102-8176-0f8e85a146d6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=315846153 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 8.rom_ctrl_csr_mem_rw_with_rand_reset.315846153
Directory /workspace/8.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_rw.182309291
Short name T416
Test name
Test status
Simulation time 213780564 ps
CPU time 5.83 seconds
Started May 14 12:51:54 PM PDT 24
Finished May 14 12:52:04 PM PDT 24
Peak memory 211168 kb
Host smart-4ee9ee9f-35f1-4b48-ac98-e28b203e87a8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=182309291 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_csr_rw.182309291
Directory /workspace/8.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_passthru_mem_tl_intg_err.1387575697
Short name T78
Test name
Test status
Simulation time 12788020961 ps
CPU time 36.19 seconds
Started May 14 12:51:55 PM PDT 24
Finished May 14 12:52:35 PM PDT 24
Peak memory 211328 kb
Host smart-60e1aa30-02c6-4975-958d-996b7142941f
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1387575697 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_pa
ssthru_mem_tl_intg_err.1387575697
Directory /workspace/8.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_same_csr_outstanding.2613281120
Short name T402
Test name
Test status
Simulation time 2181694873 ps
CPU time 16.55 seconds
Started May 14 12:51:51 PM PDT 24
Finished May 14 12:52:12 PM PDT 24
Peak memory 211196 kb
Host smart-c8773d2e-fc5a-4942-b011-bbd1fe8f9d6f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2613281120 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_c
trl_same_csr_outstanding.2613281120
Directory /workspace/8.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_errors.906200007
Short name T398
Test name
Test status
Simulation time 687082486 ps
CPU time 11.04 seconds
Started May 14 12:51:52 PM PDT 24
Finished May 14 12:52:08 PM PDT 24
Peak memory 219392 kb
Host smart-b6e76ccf-f74a-45be-aef5-a6c51464966f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=906200007 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_tl_errors.906200007
Directory /workspace/8.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_intg_err.852519867
Short name T454
Test name
Test status
Simulation time 195428699 ps
CPU time 36.23 seconds
Started May 14 12:52:04 PM PDT 24
Finished May 14 12:52:42 PM PDT 24
Peak memory 211896 kb
Host smart-1d3f11c7-e127-4765-a80b-a6875d78e998
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=852519867 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_tl_int
g_err.852519867
Directory /workspace/8.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_mem_rw_with_rand_reset.3348359767
Short name T422
Test name
Test status
Simulation time 1706197867 ps
CPU time 7.65 seconds
Started May 14 12:51:52 PM PDT 24
Finished May 14 12:52:03 PM PDT 24
Peak memory 219484 kb
Host smart-352bd12c-1741-4424-aea3-cfce61bf730f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3348359767 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 9.rom_ctrl_csr_mem_rw_with_rand_reset.3348359767
Directory /workspace/9.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_rw.893331813
Short name T432
Test name
Test status
Simulation time 5448544618 ps
CPU time 12.46 seconds
Started May 14 12:51:54 PM PDT 24
Finished May 14 12:52:10 PM PDT 24
Peak memory 211288 kb
Host smart-c1fb258f-4093-4189-8de7-1a139c584a91
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=893331813 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_csr_rw.893331813
Directory /workspace/9.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_passthru_mem_tl_intg_err.1340056862
Short name T436
Test name
Test status
Simulation time 7383564569 ps
CPU time 61.85 seconds
Started May 14 12:51:59 PM PDT 24
Finished May 14 12:53:04 PM PDT 24
Peak memory 212320 kb
Host smart-cf405bbe-0838-448b-9fdb-151730eba33c
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1340056862 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_pa
ssthru_mem_tl_intg_err.1340056862
Directory /workspace/9.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_same_csr_outstanding.2706164084
Short name T424
Test name
Test status
Simulation time 2470367442 ps
CPU time 8.67 seconds
Started May 14 12:51:56 PM PDT 24
Finished May 14 12:52:09 PM PDT 24
Peak memory 211244 kb
Host smart-0771fce6-6cf9-4332-a3ab-fddce09c6b04
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2706164084 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_c
trl_same_csr_outstanding.2706164084
Directory /workspace/9.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_errors.2233363419
Short name T368
Test name
Test status
Simulation time 1677564993 ps
CPU time 17.91 seconds
Started May 14 12:51:55 PM PDT 24
Finished May 14 12:52:16 PM PDT 24
Peak memory 219516 kb
Host smart-a6391561-70b2-4573-a9d2-f4f4deba9bbc
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2233363419 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_tl_errors.2233363419
Directory /workspace/9.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_intg_err.1146484847
Short name T421
Test name
Test status
Simulation time 6284120156 ps
CPU time 43.46 seconds
Started May 14 12:51:53 PM PDT 24
Finished May 14 12:52:41 PM PDT 24
Peak memory 219368 kb
Host smart-57734516-2be9-4ae6-ac28-4a3d2f460b44
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1146484847 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_tl_in
tg_err.1146484847
Directory /workspace/9.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/0.rom_ctrl_alert_test.3862061563
Short name T315
Test name
Test status
Simulation time 554395722 ps
CPU time 4.21 seconds
Started May 14 12:50:51 PM PDT 24
Finished May 14 12:50:57 PM PDT 24
Peak memory 211252 kb
Host smart-9a719fef-a726-4350-b839-fe47bca01cdc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3862061563 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_alert_test.3862061563
Directory /workspace/0.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/0.rom_ctrl_corrupt_sig_fatal_chk.2397900638
Short name T23
Test name
Test status
Simulation time 70359948950 ps
CPU time 158.41 seconds
Started May 14 12:50:51 PM PDT 24
Finished May 14 12:53:31 PM PDT 24
Peak memory 218580 kb
Host smart-5251ae32-5bbe-4e13-8924-3ae61766fb0e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2397900638 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_c
orrupt_sig_fatal_chk.2397900638
Directory /workspace/0.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/0.rom_ctrl_kmac_err_chk.1697268500
Short name T189
Test name
Test status
Simulation time 3617042540 ps
CPU time 30.45 seconds
Started May 14 12:50:51 PM PDT 24
Finished May 14 12:51:23 PM PDT 24
Peak memory 211924 kb
Host smart-6f471150-32e2-4157-aea1-6b04b19962d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1697268500 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_kmac_err_chk.1697268500
Directory /workspace/0.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/0.rom_ctrl_max_throughput_chk.3011087224
Short name T337
Test name
Test status
Simulation time 707354993 ps
CPU time 9.57 seconds
Started May 14 12:50:49 PM PDT 24
Finished May 14 12:51:00 PM PDT 24
Peak memory 211004 kb
Host smart-bd2a15d9-1c92-400e-af9a-73aa87082d33
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3011087224 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_max_throughput_chk.3011087224
Directory /workspace/0.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/0.rom_ctrl_smoke.1052030534
Short name T171
Test name
Test status
Simulation time 4187093152 ps
CPU time 34.04 seconds
Started May 14 12:51:14 PM PDT 24
Finished May 14 12:51:50 PM PDT 24
Peak memory 219420 kb
Host smart-97f626f7-0152-40c0-ac06-9e444a603eeb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1052030534 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_smoke.1052030534
Directory /workspace/0.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/0.rom_ctrl_stress_all.72923896
Short name T329
Test name
Test status
Simulation time 5173584721 ps
CPU time 58.46 seconds
Started May 14 12:50:50 PM PDT 24
Finished May 14 12:51:50 PM PDT 24
Peak memory 215944 kb
Host smart-734fece3-c2fc-4106-97ee-72123b0535f9
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72923896 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +U
VM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n
ame 0.rom_ctrl_stress_all.72923896
Directory /workspace/0.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/0.rom_ctrl_stress_all_with_rand_reset.3613566332
Short name T42
Test name
Test status
Simulation time 20785418974 ps
CPU time 1262.14 seconds
Started May 14 12:50:52 PM PDT 24
Finished May 14 01:11:56 PM PDT 24
Peak memory 227760 kb
Host smart-2b175d59-f33f-436c-8bcd-f57f54815ae5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3613566332 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_stress_all_with_rand_reset.3613566332
Directory /workspace/0.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.rom_ctrl_alert_test.4053159684
Short name T207
Test name
Test status
Simulation time 5586827298 ps
CPU time 12.75 seconds
Started May 14 12:50:53 PM PDT 24
Finished May 14 12:51:07 PM PDT 24
Peak memory 211344 kb
Host smart-e2470274-d659-4bea-9f49-7a1964e61583
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4053159684 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_alert_test.4053159684
Directory /workspace/1.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/1.rom_ctrl_corrupt_sig_fatal_chk.1922178479
Short name T194
Test name
Test status
Simulation time 189113524277 ps
CPU time 465.18 seconds
Started May 14 12:51:10 PM PDT 24
Finished May 14 12:58:57 PM PDT 24
Peak memory 233812 kb
Host smart-33530c58-50ad-4de5-bfa7-2a87b4f88cd8
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1922178479 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_c
orrupt_sig_fatal_chk.1922178479
Directory /workspace/1.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/1.rom_ctrl_max_throughput_chk.3043918298
Short name T334
Test name
Test status
Simulation time 95211537 ps
CPU time 5.31 seconds
Started May 14 12:50:53 PM PDT 24
Finished May 14 12:51:01 PM PDT 24
Peak memory 210936 kb
Host smart-56791687-ac0d-47f2-b565-9eabee48a7b5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3043918298 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_max_throughput_chk.3043918298
Directory /workspace/1.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/1.rom_ctrl_sec_cm.3481524583
Short name T6
Test name
Test status
Simulation time 3688212072 ps
CPU time 61.2 seconds
Started May 14 12:51:05 PM PDT 24
Finished May 14 12:52:07 PM PDT 24
Peak memory 236844 kb
Host smart-9739786e-6270-4ca3-bbcb-296cb153d955
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3481524583 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_sec_cm.3481524583
Directory /workspace/1.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/1.rom_ctrl_smoke.3354140118
Short name T241
Test name
Test status
Simulation time 6939458471 ps
CPU time 22.12 seconds
Started May 14 12:51:19 PM PDT 24
Finished May 14 12:51:44 PM PDT 24
Peak memory 219380 kb
Host smart-28614b21-1a8d-47c3-b0ad-960dbddc3745
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3354140118 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_smoke.3354140118
Directory /workspace/1.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/1.rom_ctrl_stress_all.2217886007
Short name T235
Test name
Test status
Simulation time 1443996645 ps
CPU time 13.28 seconds
Started May 14 12:50:51 PM PDT 24
Finished May 14 12:51:06 PM PDT 24
Peak memory 210908 kb
Host smart-8585f943-a446-4b15-a277-cf7dc7cd0ab8
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2217886007 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 1.rom_ctrl_stress_all.2217886007
Directory /workspace/1.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/10.rom_ctrl_alert_test.2552793587
Short name T261
Test name
Test status
Simulation time 3776968721 ps
CPU time 15.71 seconds
Started May 14 12:51:05 PM PDT 24
Finished May 14 12:51:23 PM PDT 24
Peak memory 211420 kb
Host smart-fdec4ce8-57c6-4796-842d-740a0d6d10fd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2552793587 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_alert_test.2552793587
Directory /workspace/10.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/10.rom_ctrl_corrupt_sig_fatal_chk.1017932886
Short name T156
Test name
Test status
Simulation time 3592114348 ps
CPU time 152.78 seconds
Started May 14 12:50:59 PM PDT 24
Finished May 14 12:53:34 PM PDT 24
Peak memory 212896 kb
Host smart-23251643-a25d-4d40-9ea4-ce989b086b49
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1017932886 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_
corrupt_sig_fatal_chk.1017932886
Directory /workspace/10.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/10.rom_ctrl_kmac_err_chk.2434610381
Short name T265
Test name
Test status
Simulation time 831299491 ps
CPU time 9.61 seconds
Started May 14 12:51:03 PM PDT 24
Finished May 14 12:51:19 PM PDT 24
Peak memory 211824 kb
Host smart-46758aef-9feb-40cb-8ebf-4559cc0a29eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2434610381 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_kmac_err_chk.2434610381
Directory /workspace/10.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/10.rom_ctrl_max_throughput_chk.1376689009
Short name T251
Test name
Test status
Simulation time 2237665711 ps
CPU time 12.05 seconds
Started May 14 12:51:18 PM PDT 24
Finished May 14 12:51:32 PM PDT 24
Peak memory 211164 kb
Host smart-e40b4f06-8062-45d2-b2e7-dc186436c390
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1376689009 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_max_throughput_chk.1376689009
Directory /workspace/10.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/10.rom_ctrl_smoke.3430953535
Short name T311
Test name
Test status
Simulation time 7969712545 ps
CPU time 22.02 seconds
Started May 14 12:51:16 PM PDT 24
Finished May 14 12:51:40 PM PDT 24
Peak memory 214348 kb
Host smart-a8255fcf-24ce-457c-b9d1-ce40578eea26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3430953535 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_smoke.3430953535
Directory /workspace/10.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/10.rom_ctrl_stress_all.363814789
Short name T128
Test name
Test status
Simulation time 1554563395 ps
CPU time 22.27 seconds
Started May 14 12:50:56 PM PDT 24
Finished May 14 12:51:21 PM PDT 24
Peak memory 214212 kb
Host smart-f528c463-dc83-4c7e-9b57-e99466e9f43e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=363814789 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 10.rom_ctrl_stress_all.363814789
Directory /workspace/10.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/11.rom_ctrl_alert_test.1366125359
Short name T130
Test name
Test status
Simulation time 1531922239 ps
CPU time 6.94 seconds
Started May 14 12:51:14 PM PDT 24
Finished May 14 12:51:23 PM PDT 24
Peak memory 211456 kb
Host smart-18301593-9353-4a18-8bd7-afec92966da9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1366125359 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_alert_test.1366125359
Directory /workspace/11.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/11.rom_ctrl_corrupt_sig_fatal_chk.1104525896
Short name T206
Test name
Test status
Simulation time 3123925152 ps
CPU time 110.45 seconds
Started May 14 12:51:02 PM PDT 24
Finished May 14 12:52:53 PM PDT 24
Peak memory 238160 kb
Host smart-d1a5ff60-9f55-4892-8150-78fe34ffea41
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1104525896 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_
corrupt_sig_fatal_chk.1104525896
Directory /workspace/11.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/11.rom_ctrl_kmac_err_chk.2804959685
Short name T208
Test name
Test status
Simulation time 6446761039 ps
CPU time 19.46 seconds
Started May 14 12:51:01 PM PDT 24
Finished May 14 12:51:22 PM PDT 24
Peak memory 212528 kb
Host smart-af201843-ce23-403a-a5b1-65dafe457b02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2804959685 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_kmac_err_chk.2804959685
Directory /workspace/11.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/11.rom_ctrl_max_throughput_chk.888719068
Short name T320
Test name
Test status
Simulation time 2096684359 ps
CPU time 8.68 seconds
Started May 14 12:51:01 PM PDT 24
Finished May 14 12:51:11 PM PDT 24
Peak memory 211012 kb
Host smart-18213189-6e2a-4932-a977-658acd3cf77e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=888719068 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_max_throughput_chk.888719068
Directory /workspace/11.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/11.rom_ctrl_smoke.4045356310
Short name T146
Test name
Test status
Simulation time 7912903140 ps
CPU time 21.63 seconds
Started May 14 12:50:56 PM PDT 24
Finished May 14 12:51:19 PM PDT 24
Peak memory 214196 kb
Host smart-f6f8d075-8c53-4896-98c1-052f988a1b68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4045356310 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_smoke.4045356310
Directory /workspace/11.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/12.rom_ctrl_alert_test.2190698329
Short name T195
Test name
Test status
Simulation time 7020310150 ps
CPU time 15.03 seconds
Started May 14 12:50:59 PM PDT 24
Finished May 14 12:51:17 PM PDT 24
Peak memory 211284 kb
Host smart-f0bb7418-78cc-43f2-91fa-52712d1d4034
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2190698329 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_alert_test.2190698329
Directory /workspace/12.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/12.rom_ctrl_corrupt_sig_fatal_chk.2908665581
Short name T115
Test name
Test status
Simulation time 71685598234 ps
CPU time 196.99 seconds
Started May 14 12:51:04 PM PDT 24
Finished May 14 12:54:22 PM PDT 24
Peak memory 238024 kb
Host smart-aeb47c88-3e69-468f-92a3-c31ac19e2682
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2908665581 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_
corrupt_sig_fatal_chk.2908665581
Directory /workspace/12.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/12.rom_ctrl_kmac_err_chk.986575167
Short name T242
Test name
Test status
Simulation time 10732111193 ps
CPU time 25.93 seconds
Started May 14 12:50:59 PM PDT 24
Finished May 14 12:51:27 PM PDT 24
Peak memory 212260 kb
Host smart-db3c89e3-9899-4d09-8dbd-395396ef4247
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=986575167 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_kmac_err_chk.986575167
Directory /workspace/12.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/12.rom_ctrl_max_throughput_chk.1143724080
Short name T179
Test name
Test status
Simulation time 606907898 ps
CPU time 9.26 seconds
Started May 14 12:51:00 PM PDT 24
Finished May 14 12:51:12 PM PDT 24
Peak memory 211040 kb
Host smart-9d6a41b4-a90e-471d-abfe-b79341863102
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1143724080 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_max_throughput_chk.1143724080
Directory /workspace/12.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/12.rom_ctrl_smoke.3040306546
Short name T347
Test name
Test status
Simulation time 1898274872 ps
CPU time 21.36 seconds
Started May 14 12:51:10 PM PDT 24
Finished May 14 12:51:34 PM PDT 24
Peak memory 213352 kb
Host smart-b8712308-3c64-4bee-ad25-9d7daabccdea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3040306546 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_smoke.3040306546
Directory /workspace/12.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/12.rom_ctrl_stress_all.1783957980
Short name T68
Test name
Test status
Simulation time 1318254734 ps
CPU time 15.3 seconds
Started May 14 12:51:14 PM PDT 24
Finished May 14 12:51:31 PM PDT 24
Peak memory 216104 kb
Host smart-ea3d12f7-3bff-4623-9fb4-a3f88244a885
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1783957980 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 12.rom_ctrl_stress_all.1783957980
Directory /workspace/12.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/13.rom_ctrl_alert_test.774428417
Short name T352
Test name
Test status
Simulation time 396286101 ps
CPU time 4.21 seconds
Started May 14 12:51:20 PM PDT 24
Finished May 14 12:51:32 PM PDT 24
Peak memory 211232 kb
Host smart-ddf58725-04ae-4cbc-849a-d7d803c41da2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=774428417 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_alert_test.774428417
Directory /workspace/13.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/13.rom_ctrl_corrupt_sig_fatal_chk.327291191
Short name T228
Test name
Test status
Simulation time 27832328102 ps
CPU time 183.85 seconds
Started May 14 12:51:16 PM PDT 24
Finished May 14 12:54:21 PM PDT 24
Peak memory 237928 kb
Host smart-66f69d3f-dd8a-4d43-a943-9084f0f31664
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=327291191 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_c
orrupt_sig_fatal_chk.327291191
Directory /workspace/13.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/13.rom_ctrl_kmac_err_chk.156494260
Short name T324
Test name
Test status
Simulation time 16331190015 ps
CPU time 20.86 seconds
Started May 14 12:51:20 PM PDT 24
Finished May 14 12:51:44 PM PDT 24
Peak memory 212212 kb
Host smart-62371a46-9c1d-4c12-ad87-1732f04cf879
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=156494260 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_kmac_err_chk.156494260
Directory /workspace/13.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/13.rom_ctrl_max_throughput_chk.2983306980
Short name T345
Test name
Test status
Simulation time 1122757422 ps
CPU time 8.73 seconds
Started May 14 12:51:19 PM PDT 24
Finished May 14 12:51:30 PM PDT 24
Peak memory 211012 kb
Host smart-58d09272-3b2f-41d4-ab12-19f382f237c8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2983306980 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_max_throughput_chk.2983306980
Directory /workspace/13.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/13.rom_ctrl_smoke.217579939
Short name T310
Test name
Test status
Simulation time 181948572 ps
CPU time 10.11 seconds
Started May 14 12:51:16 PM PDT 24
Finished May 14 12:51:28 PM PDT 24
Peak memory 219320 kb
Host smart-3e3dd937-407d-485e-9cb3-fcc7f1c33af1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=217579939 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_smoke.217579939
Directory /workspace/13.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/13.rom_ctrl_stress_all.2128872886
Short name T321
Test name
Test status
Simulation time 10311503650 ps
CPU time 58.87 seconds
Started May 14 12:51:07 PM PDT 24
Finished May 14 12:52:08 PM PDT 24
Peak memory 219348 kb
Host smart-5168077a-88d6-41c0-9cf3-5f27c142948d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2128872886 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 13.rom_ctrl_stress_all.2128872886
Directory /workspace/13.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/13.rom_ctrl_stress_all_with_rand_reset.1644808906
Short name T323
Test name
Test status
Simulation time 21982279433 ps
CPU time 223.55 seconds
Started May 14 12:51:12 PM PDT 24
Finished May 14 12:54:58 PM PDT 24
Peak memory 222380 kb
Host smart-32ec5034-605b-4ccf-bf1b-618cfb3ad0d4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1644808906 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_stress_all_with_rand_reset.1644808906
Directory /workspace/13.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/14.rom_ctrl_alert_test.793854303
Short name T10
Test name
Test status
Simulation time 106106497 ps
CPU time 4.32 seconds
Started May 14 12:51:10 PM PDT 24
Finished May 14 12:51:16 PM PDT 24
Peak memory 211188 kb
Host smart-40d6ee27-cca9-4802-a37f-9da0f6a9687b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=793854303 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_alert_test.793854303
Directory /workspace/14.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/14.rom_ctrl_corrupt_sig_fatal_chk.619541003
Short name T28
Test name
Test status
Simulation time 2424902575 ps
CPU time 139.64 seconds
Started May 14 12:51:12 PM PDT 24
Finished May 14 12:53:34 PM PDT 24
Peak memory 228664 kb
Host smart-de2c07e7-bd41-49fc-9e22-d37c0d84ab79
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=619541003 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_c
orrupt_sig_fatal_chk.619541003
Directory /workspace/14.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/14.rom_ctrl_kmac_err_chk.3215738551
Short name T153
Test name
Test status
Simulation time 3004945459 ps
CPU time 26.18 seconds
Started May 14 12:51:17 PM PDT 24
Finished May 14 12:51:45 PM PDT 24
Peak memory 211236 kb
Host smart-61b08a87-fa4d-4d9a-ba41-21a6870fcd20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3215738551 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_kmac_err_chk.3215738551
Directory /workspace/14.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/14.rom_ctrl_max_throughput_chk.1659402350
Short name T138
Test name
Test status
Simulation time 2013865402 ps
CPU time 9.55 seconds
Started May 14 12:51:21 PM PDT 24
Finished May 14 12:51:33 PM PDT 24
Peak memory 211044 kb
Host smart-eebdb661-a182-451a-ac0c-b7f3739c72c4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1659402350 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_max_throughput_chk.1659402350
Directory /workspace/14.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/14.rom_ctrl_smoke.1774100426
Short name T142
Test name
Test status
Simulation time 3458037479 ps
CPU time 33.45 seconds
Started May 14 12:51:10 PM PDT 24
Finished May 14 12:51:46 PM PDT 24
Peak memory 213692 kb
Host smart-04f287a2-b119-41a2-9259-e80844d6029b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1774100426 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_smoke.1774100426
Directory /workspace/14.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/14.rom_ctrl_stress_all.2244331638
Short name T163
Test name
Test status
Simulation time 1412953352 ps
CPU time 20.2 seconds
Started May 14 12:51:24 PM PDT 24
Finished May 14 12:51:46 PM PDT 24
Peak memory 219276 kb
Host smart-045d89d4-0c4c-4648-bafd-13d1f3cdb314
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2244331638 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 14.rom_ctrl_stress_all.2244331638
Directory /workspace/14.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/15.rom_ctrl_alert_test.2846412839
Short name T339
Test name
Test status
Simulation time 4252871550 ps
CPU time 11.18 seconds
Started May 14 12:51:08 PM PDT 24
Finished May 14 12:51:21 PM PDT 24
Peak memory 211240 kb
Host smart-f0b021b9-5849-481f-858e-517ab765495b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2846412839 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_alert_test.2846412839
Directory /workspace/15.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/15.rom_ctrl_corrupt_sig_fatal_chk.864467277
Short name T279
Test name
Test status
Simulation time 20781541783 ps
CPU time 198.2 seconds
Started May 14 12:51:07 PM PDT 24
Finished May 14 12:54:27 PM PDT 24
Peak memory 237316 kb
Host smart-ad7fb1da-bd3d-4718-9dfa-213c2a1b1b8b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=864467277 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_c
orrupt_sig_fatal_chk.864467277
Directory /workspace/15.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/15.rom_ctrl_kmac_err_chk.840224966
Short name T8
Test name
Test status
Simulation time 14359071948 ps
CPU time 30.52 seconds
Started May 14 12:51:19 PM PDT 24
Finished May 14 12:51:52 PM PDT 24
Peak memory 212716 kb
Host smart-09a66582-5fbe-419b-8fdd-d0333799f1aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=840224966 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_kmac_err_chk.840224966
Directory /workspace/15.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/15.rom_ctrl_max_throughput_chk.4191497934
Short name T172
Test name
Test status
Simulation time 8594160547 ps
CPU time 17.18 seconds
Started May 14 12:51:13 PM PDT 24
Finished May 14 12:51:32 PM PDT 24
Peak memory 211232 kb
Host smart-f9bbb8d5-66d7-4290-b281-60e9a712b0d5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4191497934 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_max_throughput_chk.4191497934
Directory /workspace/15.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/15.rom_ctrl_smoke.888760038
Short name T164
Test name
Test status
Simulation time 6436746202 ps
CPU time 28.85 seconds
Started May 14 12:51:17 PM PDT 24
Finished May 14 12:51:48 PM PDT 24
Peak memory 214172 kb
Host smart-664094f7-9ec9-48a2-a4ea-1083e3fd6d37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=888760038 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_smoke.888760038
Directory /workspace/15.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/15.rom_ctrl_stress_all.2778711505
Short name T159
Test name
Test status
Simulation time 11885182912 ps
CPU time 11.43 seconds
Started May 14 12:51:09 PM PDT 24
Finished May 14 12:51:23 PM PDT 24
Peak memory 211112 kb
Host smart-bcada16e-8ea4-4d7e-94e1-99034966690e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2778711505 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 15.rom_ctrl_stress_all.2778711505
Directory /workspace/15.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/16.rom_ctrl_alert_test.1548498841
Short name T185
Test name
Test status
Simulation time 547128083 ps
CPU time 5.03 seconds
Started May 14 12:51:21 PM PDT 24
Finished May 14 12:51:29 PM PDT 24
Peak memory 211204 kb
Host smart-d32060ba-ed4a-4311-a7d6-985bd0924cf2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1548498841 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_alert_test.1548498841
Directory /workspace/16.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/16.rom_ctrl_corrupt_sig_fatal_chk.781414750
Short name T218
Test name
Test status
Simulation time 136100862542 ps
CPU time 308.69 seconds
Started May 14 12:51:26 PM PDT 24
Finished May 14 12:56:37 PM PDT 24
Peak memory 234064 kb
Host smart-359d2461-aa79-4145-a844-9cdd87605ef3
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=781414750 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_c
orrupt_sig_fatal_chk.781414750
Directory /workspace/16.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/16.rom_ctrl_kmac_err_chk.2528646463
Short name T160
Test name
Test status
Simulation time 3159155078 ps
CPU time 26.89 seconds
Started May 14 12:51:18 PM PDT 24
Finished May 14 12:51:48 PM PDT 24
Peak memory 212424 kb
Host smart-f902073c-2ea6-44f1-8df4-d8342797622c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2528646463 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_kmac_err_chk.2528646463
Directory /workspace/16.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/16.rom_ctrl_max_throughput_chk.3884300261
Short name T204
Test name
Test status
Simulation time 4117244981 ps
CPU time 11.39 seconds
Started May 14 12:51:13 PM PDT 24
Finished May 14 12:51:26 PM PDT 24
Peak memory 211200 kb
Host smart-f71cb86d-d1b0-48ee-8f05-b4eabd9336e8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3884300261 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_max_throughput_chk.3884300261
Directory /workspace/16.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/16.rom_ctrl_smoke.1822660416
Short name T45
Test name
Test status
Simulation time 4309621328 ps
CPU time 16.34 seconds
Started May 14 12:51:12 PM PDT 24
Finished May 14 12:51:30 PM PDT 24
Peak memory 219312 kb
Host smart-b91a9ebb-aa1a-4b95-8b2c-2e9879748256
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1822660416 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_smoke.1822660416
Directory /workspace/16.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/16.rom_ctrl_stress_all.2018377701
Short name T346
Test name
Test status
Simulation time 2050590294 ps
CPU time 23.73 seconds
Started May 14 12:51:20 PM PDT 24
Finished May 14 12:51:46 PM PDT 24
Peak memory 214904 kb
Host smart-0e033deb-9a7a-4344-ae2d-c3efc0949905
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2018377701 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 16.rom_ctrl_stress_all.2018377701
Directory /workspace/16.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/17.rom_ctrl_alert_test.2936100910
Short name T220
Test name
Test status
Simulation time 999461592 ps
CPU time 10.53 seconds
Started May 14 12:51:13 PM PDT 24
Finished May 14 12:51:26 PM PDT 24
Peak memory 211140 kb
Host smart-28c93429-d991-45f7-98ca-6a36df2169f1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2936100910 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_alert_test.2936100910
Directory /workspace/17.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/17.rom_ctrl_corrupt_sig_fatal_chk.3753021095
Short name T283
Test name
Test status
Simulation time 62610545928 ps
CPU time 291.97 seconds
Started May 14 12:51:17 PM PDT 24
Finished May 14 12:56:10 PM PDT 24
Peak memory 230596 kb
Host smart-384189a1-582c-43d1-8fa7-814dc3bbd603
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3753021095 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_
corrupt_sig_fatal_chk.3753021095
Directory /workspace/17.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/17.rom_ctrl_kmac_err_chk.747741403
Short name T327
Test name
Test status
Simulation time 1004517134 ps
CPU time 11.24 seconds
Started May 14 12:51:09 PM PDT 24
Finished May 14 12:51:23 PM PDT 24
Peak memory 219364 kb
Host smart-ffce641b-8035-4058-9b28-425e992b18e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=747741403 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_kmac_err_chk.747741403
Directory /workspace/17.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/17.rom_ctrl_max_throughput_chk.3868449788
Short name T232
Test name
Test status
Simulation time 1776019261 ps
CPU time 11.16 seconds
Started May 14 12:51:15 PM PDT 24
Finished May 14 12:51:27 PM PDT 24
Peak memory 211032 kb
Host smart-abd4de9b-a68f-46e7-a3e9-e069ffc40975
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3868449788 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_max_throughput_chk.3868449788
Directory /workspace/17.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/17.rom_ctrl_smoke.3815563669
Short name T263
Test name
Test status
Simulation time 1841197671 ps
CPU time 22.26 seconds
Started May 14 12:51:19 PM PDT 24
Finished May 14 12:51:44 PM PDT 24
Peak memory 213528 kb
Host smart-83680ae6-5f3c-4da9-ba9a-19850908ddad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3815563669 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_smoke.3815563669
Directory /workspace/17.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/17.rom_ctrl_stress_all.1221856196
Short name T225
Test name
Test status
Simulation time 4534987753 ps
CPU time 54.42 seconds
Started May 14 12:51:08 PM PDT 24
Finished May 14 12:52:04 PM PDT 24
Peak memory 214576 kb
Host smart-99851d60-3b03-4b61-bf07-fc46c67bbaed
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1221856196 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 17.rom_ctrl_stress_all.1221856196
Directory /workspace/17.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/17.rom_ctrl_stress_all_with_rand_reset.2402268836
Short name T38
Test name
Test status
Simulation time 93874531965 ps
CPU time 1897.01 seconds
Started May 14 12:51:18 PM PDT 24
Finished May 14 01:22:58 PM PDT 24
Peak memory 244568 kb
Host smart-9526fa05-63a3-4d79-bd39-b9ce880b64b0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2402268836 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_stress_all_with_rand_reset.2402268836
Directory /workspace/17.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/18.rom_ctrl_alert_test.3775734300
Short name T175
Test name
Test status
Simulation time 7000512634 ps
CPU time 9.99 seconds
Started May 14 12:51:18 PM PDT 24
Finished May 14 12:51:31 PM PDT 24
Peak memory 211316 kb
Host smart-5ad73a7a-9949-40a7-a900-d6e899861922
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3775734300 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_alert_test.3775734300
Directory /workspace/18.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/18.rom_ctrl_corrupt_sig_fatal_chk.1899387745
Short name T217
Test name
Test status
Simulation time 43382951629 ps
CPU time 167.74 seconds
Started May 14 12:51:10 PM PDT 24
Finished May 14 12:54:00 PM PDT 24
Peak memory 218596 kb
Host smart-9b7820ad-1d36-47ad-82ea-c38a612446f6
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1899387745 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_
corrupt_sig_fatal_chk.1899387745
Directory /workspace/18.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/18.rom_ctrl_kmac_err_chk.1538090912
Short name T288
Test name
Test status
Simulation time 1659257216 ps
CPU time 9.28 seconds
Started May 14 12:51:16 PM PDT 24
Finished May 14 12:51:26 PM PDT 24
Peak memory 211652 kb
Host smart-5cffe309-83b8-4d1d-98d9-ab89a975cf66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1538090912 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_kmac_err_chk.1538090912
Directory /workspace/18.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/18.rom_ctrl_max_throughput_chk.4239688299
Short name T246
Test name
Test status
Simulation time 343885273 ps
CPU time 5.67 seconds
Started May 14 12:51:07 PM PDT 24
Finished May 14 12:51:15 PM PDT 24
Peak memory 211032 kb
Host smart-896e2110-eb8e-4390-9558-949df9c336fb
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4239688299 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_max_throughput_chk.4239688299
Directory /workspace/18.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/18.rom_ctrl_smoke.638481893
Short name T134
Test name
Test status
Simulation time 187038216 ps
CPU time 10.05 seconds
Started May 14 12:51:19 PM PDT 24
Finished May 14 12:51:31 PM PDT 24
Peak memory 219208 kb
Host smart-4da83823-5e0a-4d0b-8c6e-b164790127bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=638481893 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_smoke.638481893
Directory /workspace/18.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/18.rom_ctrl_stress_all.2898663179
Short name T223
Test name
Test status
Simulation time 8669262334 ps
CPU time 64.39 seconds
Started May 14 12:51:22 PM PDT 24
Finished May 14 12:52:29 PM PDT 24
Peak memory 214244 kb
Host smart-c34e8aa0-25bb-4cf9-83e0-2797243d71a3
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2898663179 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 18.rom_ctrl_stress_all.2898663179
Directory /workspace/18.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/19.rom_ctrl_alert_test.2469695511
Short name T47
Test name
Test status
Simulation time 1632972207 ps
CPU time 14.31 seconds
Started May 14 12:51:14 PM PDT 24
Finished May 14 12:51:30 PM PDT 24
Peak memory 211068 kb
Host smart-a4308e7a-2e6c-4ec0-860f-94f67512a794
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2469695511 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_alert_test.2469695511
Directory /workspace/19.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/19.rom_ctrl_corrupt_sig_fatal_chk.3381183810
Short name T355
Test name
Test status
Simulation time 28700739054 ps
CPU time 253.32 seconds
Started May 14 12:51:01 PM PDT 24
Finished May 14 12:55:16 PM PDT 24
Peak memory 212480 kb
Host smart-dab0762d-3e23-4bbf-a55e-d98ebbdf28c6
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3381183810 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_
corrupt_sig_fatal_chk.3381183810
Directory /workspace/19.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/19.rom_ctrl_kmac_err_chk.3635497708
Short name T268
Test name
Test status
Simulation time 5709376999 ps
CPU time 31.23 seconds
Started May 14 12:51:18 PM PDT 24
Finished May 14 12:51:51 PM PDT 24
Peak memory 212236 kb
Host smart-218503e5-8b1a-4ae5-8ef1-4972c17f467e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3635497708 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_kmac_err_chk.3635497708
Directory /workspace/19.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/19.rom_ctrl_max_throughput_chk.3322674893
Short name T229
Test name
Test status
Simulation time 97092121 ps
CPU time 5.92 seconds
Started May 14 12:51:03 PM PDT 24
Finished May 14 12:51:10 PM PDT 24
Peak memory 210984 kb
Host smart-678935d6-8f6b-4f2a-8544-22cc376ec129
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3322674893 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_max_throughput_chk.3322674893
Directory /workspace/19.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/19.rom_ctrl_smoke.1633319111
Short name T247
Test name
Test status
Simulation time 3446109938 ps
CPU time 30.35 seconds
Started May 14 12:51:21 PM PDT 24
Finished May 14 12:51:54 PM PDT 24
Peak memory 219380 kb
Host smart-8a4a8ee5-62ce-413e-ada0-11819807e546
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1633319111 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_smoke.1633319111
Directory /workspace/19.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/19.rom_ctrl_stress_all.707920627
Short name T238
Test name
Test status
Simulation time 217417750 ps
CPU time 12.5 seconds
Started May 14 12:51:19 PM PDT 24
Finished May 14 12:51:34 PM PDT 24
Peak memory 212884 kb
Host smart-f24823d0-5d87-4113-a063-e15f31778574
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=707920627 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 19.rom_ctrl_stress_all.707920627
Directory /workspace/19.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/2.rom_ctrl_alert_test.1211586020
Short name T173
Test name
Test status
Simulation time 106249881 ps
CPU time 4.31 seconds
Started May 14 12:50:49 PM PDT 24
Finished May 14 12:50:55 PM PDT 24
Peak memory 211216 kb
Host smart-af5a3b57-8b12-46b2-8007-e8c6e859c239
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1211586020 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_alert_test.1211586020
Directory /workspace/2.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/2.rom_ctrl_corrupt_sig_fatal_chk.3723232047
Short name T318
Test name
Test status
Simulation time 18407897745 ps
CPU time 182.16 seconds
Started May 14 12:50:53 PM PDT 24
Finished May 14 12:53:57 PM PDT 24
Peak memory 228740 kb
Host smart-909598e2-0069-46b7-ae40-c3eeb420cad8
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3723232047 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_c
orrupt_sig_fatal_chk.3723232047
Directory /workspace/2.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/2.rom_ctrl_kmac_err_chk.868226736
Short name T19
Test name
Test status
Simulation time 2631082821 ps
CPU time 26.08 seconds
Started May 14 12:50:54 PM PDT 24
Finished May 14 12:51:22 PM PDT 24
Peak memory 211688 kb
Host smart-3a8d621b-a45e-4f4f-b639-05927c3df5d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=868226736 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_kmac_err_chk.868226736
Directory /workspace/2.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/2.rom_ctrl_max_throughput_chk.3933507511
Short name T224
Test name
Test status
Simulation time 197755839 ps
CPU time 5.81 seconds
Started May 14 12:51:09 PM PDT 24
Finished May 14 12:51:16 PM PDT 24
Peak memory 211040 kb
Host smart-539d1736-2fbf-4a0c-b4a0-93d067575916
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3933507511 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_max_throughput_chk.3933507511
Directory /workspace/2.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/2.rom_ctrl_sec_cm.2966635526
Short name T32
Test name
Test status
Simulation time 8351583945 ps
CPU time 63.59 seconds
Started May 14 12:51:01 PM PDT 24
Finished May 14 12:52:06 PM PDT 24
Peak memory 238676 kb
Host smart-79c40665-c66b-4bb6-a1dc-e04745373fd3
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2966635526 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_sec_cm.2966635526
Directory /workspace/2.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/2.rom_ctrl_smoke.2734671441
Short name T117
Test name
Test status
Simulation time 18915743864 ps
CPU time 22.13 seconds
Started May 14 12:50:51 PM PDT 24
Finished May 14 12:51:16 PM PDT 24
Peak memory 219328 kb
Host smart-ce8a467d-6057-47ee-a333-6cff25dafeba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2734671441 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_smoke.2734671441
Directory /workspace/2.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/2.rom_ctrl_stress_all.2331853543
Short name T203
Test name
Test status
Simulation time 16672303117 ps
CPU time 44.57 seconds
Started May 14 12:51:05 PM PDT 24
Finished May 14 12:51:50 PM PDT 24
Peak memory 219404 kb
Host smart-c9cc55d7-4167-402d-b946-e2eddf28e1cf
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2331853543 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 2.rom_ctrl_stress_all.2331853543
Directory /workspace/2.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/20.rom_ctrl_alert_test.1561487292
Short name T136
Test name
Test status
Simulation time 2574920028 ps
CPU time 12.76 seconds
Started May 14 12:51:24 PM PDT 24
Finished May 14 12:51:39 PM PDT 24
Peak memory 211256 kb
Host smart-dac767e2-d659-46f1-9dc9-6dc44084b316
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1561487292 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_alert_test.1561487292
Directory /workspace/20.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/20.rom_ctrl_corrupt_sig_fatal_chk.297694749
Short name T86
Test name
Test status
Simulation time 38363139831 ps
CPU time 114.87 seconds
Started May 14 12:51:15 PM PDT 24
Finished May 14 12:53:11 PM PDT 24
Peak memory 213516 kb
Host smart-0f116c84-fca9-4e2d-8a66-c37c64abdb7d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=297694749 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_c
orrupt_sig_fatal_chk.297694749
Directory /workspace/20.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/20.rom_ctrl_max_throughput_chk.491203772
Short name T306
Test name
Test status
Simulation time 2115248264 ps
CPU time 8.89 seconds
Started May 14 12:51:16 PM PDT 24
Finished May 14 12:51:27 PM PDT 24
Peak memory 211088 kb
Host smart-f28ba666-e316-4724-8542-519181a87edb
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=491203772 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_max_throughput_chk.491203772
Directory /workspace/20.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/20.rom_ctrl_smoke.1053826595
Short name T91
Test name
Test status
Simulation time 928418782 ps
CPU time 18.16 seconds
Started May 14 12:51:20 PM PDT 24
Finished May 14 12:51:41 PM PDT 24
Peak memory 213056 kb
Host smart-d5c3c5a2-6a42-4b89-8674-a0304763edfb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1053826595 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_smoke.1053826595
Directory /workspace/20.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/20.rom_ctrl_stress_all.3789956831
Short name T141
Test name
Test status
Simulation time 3326612052 ps
CPU time 43.52 seconds
Started May 14 12:51:17 PM PDT 24
Finished May 14 12:52:03 PM PDT 24
Peak memory 216408 kb
Host smart-56fed88a-c731-4598-8a2d-afe838e959ff
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3789956831 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 20.rom_ctrl_stress_all.3789956831
Directory /workspace/20.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/20.rom_ctrl_stress_all_with_rand_reset.3568666255
Short name T39
Test name
Test status
Simulation time 33986814684 ps
CPU time 1293.29 seconds
Started May 14 12:51:17 PM PDT 24
Finished May 14 01:12:52 PM PDT 24
Peak memory 229576 kb
Host smart-45188bd2-1060-4f22-82a6-11d5288c93b6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3568666255 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_stress_all_with_rand_reset.3568666255
Directory /workspace/20.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/21.rom_ctrl_alert_test.1144733920
Short name T43
Test name
Test status
Simulation time 89206706 ps
CPU time 4.3 seconds
Started May 14 12:51:23 PM PDT 24
Finished May 14 12:51:29 PM PDT 24
Peak memory 211208 kb
Host smart-c48cab6d-e0dd-476c-b8bd-3e0262cf739e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1144733920 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_alert_test.1144733920
Directory /workspace/21.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/21.rom_ctrl_corrupt_sig_fatal_chk.3157574267
Short name T150
Test name
Test status
Simulation time 7411932190 ps
CPU time 134.76 seconds
Started May 14 12:51:23 PM PDT 24
Finished May 14 12:53:40 PM PDT 24
Peak memory 237296 kb
Host smart-a07929a0-44b5-4875-9486-d6881f35498b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3157574267 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_
corrupt_sig_fatal_chk.3157574267
Directory /workspace/21.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/21.rom_ctrl_kmac_err_chk.2299830507
Short name T129
Test name
Test status
Simulation time 3412720779 ps
CPU time 20.28 seconds
Started May 14 12:51:20 PM PDT 24
Finished May 14 12:51:43 PM PDT 24
Peak memory 212028 kb
Host smart-3f734930-c901-43ce-8edc-fd19510ed225
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2299830507 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_kmac_err_chk.2299830507
Directory /workspace/21.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/21.rom_ctrl_max_throughput_chk.1794296624
Short name T322
Test name
Test status
Simulation time 3696066380 ps
CPU time 16.67 seconds
Started May 14 12:51:22 PM PDT 24
Finished May 14 12:51:41 PM PDT 24
Peak memory 211144 kb
Host smart-1490e60d-4bf5-4813-afc3-917dd8d986bc
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1794296624 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_max_throughput_chk.1794296624
Directory /workspace/21.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/21.rom_ctrl_smoke.1077778611
Short name T298
Test name
Test status
Simulation time 8209375968 ps
CPU time 34.96 seconds
Started May 14 12:51:18 PM PDT 24
Finished May 14 12:51:55 PM PDT 24
Peak memory 219448 kb
Host smart-105df50c-f6b7-44de-ab94-3600e3612ce2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1077778611 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_smoke.1077778611
Directory /workspace/21.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/21.rom_ctrl_stress_all.3272202196
Short name T200
Test name
Test status
Simulation time 947256369 ps
CPU time 12.56 seconds
Started May 14 12:51:22 PM PDT 24
Finished May 14 12:51:37 PM PDT 24
Peak memory 212008 kb
Host smart-002d82a6-4b89-4be3-ad70-41e2c73cea7f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3272202196 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 21.rom_ctrl_stress_all.3272202196
Directory /workspace/21.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/22.rom_ctrl_alert_test.863676189
Short name T252
Test name
Test status
Simulation time 1382087608 ps
CPU time 4.39 seconds
Started May 14 12:51:18 PM PDT 24
Finished May 14 12:51:25 PM PDT 24
Peak memory 211200 kb
Host smart-58dcf10a-a49a-4a6a-a987-a4ef0aea8001
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=863676189 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_alert_test.863676189
Directory /workspace/22.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/22.rom_ctrl_corrupt_sig_fatal_chk.910651188
Short name T350
Test name
Test status
Simulation time 12048861249 ps
CPU time 169.68 seconds
Started May 14 12:51:18 PM PDT 24
Finished May 14 12:54:11 PM PDT 24
Peak memory 235064 kb
Host smart-50f46904-470f-4cb4-8868-787e47b4a018
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=910651188 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_c
orrupt_sig_fatal_chk.910651188
Directory /workspace/22.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/22.rom_ctrl_kmac_err_chk.1911676597
Short name T167
Test name
Test status
Simulation time 3532699906 ps
CPU time 29.85 seconds
Started May 14 12:51:28 PM PDT 24
Finished May 14 12:52:00 PM PDT 24
Peak memory 212624 kb
Host smart-96da8135-75f3-4288-ac07-14827cd23007
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1911676597 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_kmac_err_chk.1911676597
Directory /workspace/22.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/22.rom_ctrl_max_throughput_chk.2865727503
Short name T209
Test name
Test status
Simulation time 1285724107 ps
CPU time 13.22 seconds
Started May 14 12:51:23 PM PDT 24
Finished May 14 12:51:38 PM PDT 24
Peak memory 210992 kb
Host smart-895537bf-1043-440d-bf58-e5ef28c74e49
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2865727503 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_max_throughput_chk.2865727503
Directory /workspace/22.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/22.rom_ctrl_smoke.1993509813
Short name T122
Test name
Test status
Simulation time 1029550125 ps
CPU time 17.35 seconds
Started May 14 12:51:29 PM PDT 24
Finished May 14 12:51:48 PM PDT 24
Peak memory 219228 kb
Host smart-6a51b642-7185-4c57-b458-7d10e099689f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1993509813 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_smoke.1993509813
Directory /workspace/22.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/22.rom_ctrl_stress_all.1605853005
Short name T67
Test name
Test status
Simulation time 15162370413 ps
CPU time 44.24 seconds
Started May 14 12:51:26 PM PDT 24
Finished May 14 12:52:13 PM PDT 24
Peak memory 219360 kb
Host smart-ab72d946-3528-45ae-aef0-dd5001925077
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1605853005 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 22.rom_ctrl_stress_all.1605853005
Directory /workspace/22.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/23.rom_ctrl_alert_test.1665463416
Short name T300
Test name
Test status
Simulation time 171445584 ps
CPU time 4.28 seconds
Started May 14 12:51:24 PM PDT 24
Finished May 14 12:51:30 PM PDT 24
Peak memory 211212 kb
Host smart-5d9a18b1-2835-4b51-9cda-7e91f4a7002b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1665463416 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_alert_test.1665463416
Directory /workspace/23.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/23.rom_ctrl_corrupt_sig_fatal_chk.1403478387
Short name T258
Test name
Test status
Simulation time 4475933787 ps
CPU time 63.42 seconds
Started May 14 12:51:24 PM PDT 24
Finished May 14 12:52:30 PM PDT 24
Peak memory 213408 kb
Host smart-65af0531-e179-407f-a2de-e334f4778053
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1403478387 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_
corrupt_sig_fatal_chk.1403478387
Directory /workspace/23.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/23.rom_ctrl_kmac_err_chk.542706971
Short name T127
Test name
Test status
Simulation time 4258716365 ps
CPU time 33.02 seconds
Started May 14 12:51:22 PM PDT 24
Finished May 14 12:51:57 PM PDT 24
Peak memory 212824 kb
Host smart-fc05d611-8e63-44be-a2a6-da58bd96c843
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=542706971 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_kmac_err_chk.542706971
Directory /workspace/23.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/23.rom_ctrl_max_throughput_chk.51499884
Short name T169
Test name
Test status
Simulation time 1944959735 ps
CPU time 16.41 seconds
Started May 14 12:51:21 PM PDT 24
Finished May 14 12:51:40 PM PDT 24
Peak memory 211276 kb
Host smart-a749d93e-489d-40df-abe5-81f4db56b040
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=51499884 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_max_throughput_chk.51499884
Directory /workspace/23.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/23.rom_ctrl_smoke.1342422113
Short name T125
Test name
Test status
Simulation time 2397558593 ps
CPU time 24.79 seconds
Started May 14 12:51:22 PM PDT 24
Finished May 14 12:51:49 PM PDT 24
Peak memory 213144 kb
Host smart-51032c53-adbd-4838-8442-de3203766455
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1342422113 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_smoke.1342422113
Directory /workspace/23.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/23.rom_ctrl_stress_all.2380912595
Short name T174
Test name
Test status
Simulation time 1789642809 ps
CPU time 17.95 seconds
Started May 14 12:51:21 PM PDT 24
Finished May 14 12:51:41 PM PDT 24
Peak memory 211448 kb
Host smart-9453cdf8-db89-452c-b503-ae20651e8994
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2380912595 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 23.rom_ctrl_stress_all.2380912595
Directory /workspace/23.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/24.rom_ctrl_alert_test.2096222561
Short name T243
Test name
Test status
Simulation time 7620032583 ps
CPU time 14.82 seconds
Started May 14 12:51:17 PM PDT 24
Finished May 14 12:51:33 PM PDT 24
Peak memory 211256 kb
Host smart-90d044a4-ebe2-42ec-af59-89962720bf3c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2096222561 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_alert_test.2096222561
Directory /workspace/24.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/24.rom_ctrl_corrupt_sig_fatal_chk.1722980640
Short name T36
Test name
Test status
Simulation time 33442934861 ps
CPU time 242.76 seconds
Started May 14 12:51:29 PM PDT 24
Finished May 14 12:55:34 PM PDT 24
Peak memory 239832 kb
Host smart-dbe1c104-d1c2-4fc3-959c-1c4a250624b8
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1722980640 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_
corrupt_sig_fatal_chk.1722980640
Directory /workspace/24.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/24.rom_ctrl_kmac_err_chk.1737492817
Short name T187
Test name
Test status
Simulation time 3285473026 ps
CPU time 28.97 seconds
Started May 14 12:51:26 PM PDT 24
Finished May 14 12:51:58 PM PDT 24
Peak memory 211828 kb
Host smart-83f5109f-b2ce-4c64-adb9-fe0af786290d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1737492817 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_kmac_err_chk.1737492817
Directory /workspace/24.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/24.rom_ctrl_max_throughput_chk.3049906900
Short name T85
Test name
Test status
Simulation time 3038092719 ps
CPU time 14.05 seconds
Started May 14 12:51:17 PM PDT 24
Finished May 14 12:51:33 PM PDT 24
Peak memory 211068 kb
Host smart-7f36cf57-f8f0-4739-bf15-e03bce9908f6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3049906900 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_max_throughput_chk.3049906900
Directory /workspace/24.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/24.rom_ctrl_smoke.768768703
Short name T280
Test name
Test status
Simulation time 8591796825 ps
CPU time 23.09 seconds
Started May 14 12:51:25 PM PDT 24
Finished May 14 12:51:50 PM PDT 24
Peak memory 214484 kb
Host smart-5c6079d4-8bcb-46f1-af2b-65a83cdf037d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=768768703 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_smoke.768768703
Directory /workspace/24.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/24.rom_ctrl_stress_all.2160779483
Short name T354
Test name
Test status
Simulation time 9941347165 ps
CPU time 51.98 seconds
Started May 14 12:51:21 PM PDT 24
Finished May 14 12:52:16 PM PDT 24
Peak memory 219328 kb
Host smart-f5e99255-598e-410c-8ce5-76ea23ab5626
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2160779483 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 24.rom_ctrl_stress_all.2160779483
Directory /workspace/24.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/25.rom_ctrl_alert_test.3770481853
Short name T147
Test name
Test status
Simulation time 8534944489 ps
CPU time 16.98 seconds
Started May 14 12:51:17 PM PDT 24
Finished May 14 12:51:36 PM PDT 24
Peak memory 211228 kb
Host smart-06153c7f-6e48-4158-912d-02ea4ced69be
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3770481853 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_alert_test.3770481853
Directory /workspace/25.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/25.rom_ctrl_kmac_err_chk.2671496566
Short name T341
Test name
Test status
Simulation time 6089570869 ps
CPU time 28.07 seconds
Started May 14 12:51:17 PM PDT 24
Finished May 14 12:51:47 PM PDT 24
Peak memory 212304 kb
Host smart-8645c6a3-a359-4f53-b420-d2ecd2cfa7a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2671496566 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_kmac_err_chk.2671496566
Directory /workspace/25.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/25.rom_ctrl_max_throughput_chk.2433382990
Short name T253
Test name
Test status
Simulation time 380592011 ps
CPU time 5.67 seconds
Started May 14 12:51:26 PM PDT 24
Finished May 14 12:51:34 PM PDT 24
Peak memory 211000 kb
Host smart-13426b55-2d5f-4599-b0af-83ee129c26ea
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2433382990 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_max_throughput_chk.2433382990
Directory /workspace/25.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/25.rom_ctrl_smoke.2453771863
Short name T118
Test name
Test status
Simulation time 2825385702 ps
CPU time 18.82 seconds
Started May 14 12:51:19 PM PDT 24
Finished May 14 12:51:41 PM PDT 24
Peak memory 213388 kb
Host smart-856c6753-6b49-49ad-98a4-fd65e6216fc3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2453771863 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_smoke.2453771863
Directory /workspace/25.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/25.rom_ctrl_stress_all.3176977971
Short name T276
Test name
Test status
Simulation time 43110256422 ps
CPU time 109.91 seconds
Started May 14 12:51:27 PM PDT 24
Finished May 14 12:53:19 PM PDT 24
Peak memory 219384 kb
Host smart-6d26423f-8865-4473-ac4a-537e4cf2d5d1
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3176977971 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 25.rom_ctrl_stress_all.3176977971
Directory /workspace/25.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/26.rom_ctrl_alert_test.2772200434
Short name T360
Test name
Test status
Simulation time 85467553 ps
CPU time 4.34 seconds
Started May 14 12:51:23 PM PDT 24
Finished May 14 12:51:29 PM PDT 24
Peak memory 211200 kb
Host smart-342c9e60-f219-48a7-a13e-de6bbe3ed385
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2772200434 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_alert_test.2772200434
Directory /workspace/26.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/26.rom_ctrl_corrupt_sig_fatal_chk.627710245
Short name T363
Test name
Test status
Simulation time 12028209291 ps
CPU time 164.43 seconds
Started May 14 12:51:22 PM PDT 24
Finished May 14 12:54:09 PM PDT 24
Peak memory 237896 kb
Host smart-57ea7ece-9a85-4cca-8c32-0e70f4472b65
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=627710245 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_c
orrupt_sig_fatal_chk.627710245
Directory /workspace/26.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/26.rom_ctrl_kmac_err_chk.843453036
Short name T144
Test name
Test status
Simulation time 601050275 ps
CPU time 13.78 seconds
Started May 14 12:51:18 PM PDT 24
Finished May 14 12:51:34 PM PDT 24
Peak memory 211860 kb
Host smart-7044883e-833f-4d2f-ba9d-8cb8e57867c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=843453036 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_kmac_err_chk.843453036
Directory /workspace/26.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/26.rom_ctrl_max_throughput_chk.3480880472
Short name T230
Test name
Test status
Simulation time 664764908 ps
CPU time 8.46 seconds
Started May 14 12:51:28 PM PDT 24
Finished May 14 12:51:39 PM PDT 24
Peak memory 211056 kb
Host smart-b203ce86-1eb8-4bcc-bef8-5f6b89968b62
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3480880472 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_max_throughput_chk.3480880472
Directory /workspace/26.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/26.rom_ctrl_smoke.751142385
Short name T145
Test name
Test status
Simulation time 2664976982 ps
CPU time 18.69 seconds
Started May 14 12:51:19 PM PDT 24
Finished May 14 12:51:40 PM PDT 24
Peak memory 219352 kb
Host smart-1b49778f-9cfc-4488-a947-5a0ebcf6bae5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=751142385 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_smoke.751142385
Directory /workspace/26.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/26.rom_ctrl_stress_all.3641144891
Short name T274
Test name
Test status
Simulation time 220213195 ps
CPU time 11.09 seconds
Started May 14 12:51:26 PM PDT 24
Finished May 14 12:51:40 PM PDT 24
Peak memory 212308 kb
Host smart-cebf28fb-f450-4ba5-a076-022756ef11cb
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3641144891 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 26.rom_ctrl_stress_all.3641144891
Directory /workspace/26.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/27.rom_ctrl_alert_test.1860696651
Short name T264
Test name
Test status
Simulation time 2192696134 ps
CPU time 8.41 seconds
Started May 14 12:51:23 PM PDT 24
Finished May 14 12:51:34 PM PDT 24
Peak memory 211224 kb
Host smart-cbcb4c48-ff54-442a-9dd3-31db78841e56
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1860696651 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_alert_test.1860696651
Directory /workspace/27.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/27.rom_ctrl_corrupt_sig_fatal_chk.3725595268
Short name T325
Test name
Test status
Simulation time 2860614106 ps
CPU time 92.63 seconds
Started May 14 12:51:19 PM PDT 24
Finished May 14 12:52:55 PM PDT 24
Peak memory 220732 kb
Host smart-ce1b632d-da4a-44d5-9b79-7adfc90fc65e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3725595268 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_
corrupt_sig_fatal_chk.3725595268
Directory /workspace/27.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/27.rom_ctrl_kmac_err_chk.1590091671
Short name T255
Test name
Test status
Simulation time 172048198 ps
CPU time 9.81 seconds
Started May 14 12:51:22 PM PDT 24
Finished May 14 12:51:34 PM PDT 24
Peak memory 211732 kb
Host smart-60f5b6aa-c8c2-467a-8996-32867a726da3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1590091671 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_kmac_err_chk.1590091671
Directory /workspace/27.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/27.rom_ctrl_max_throughput_chk.216568158
Short name T257
Test name
Test status
Simulation time 4987219220 ps
CPU time 12.56 seconds
Started May 14 12:51:20 PM PDT 24
Finished May 14 12:51:35 PM PDT 24
Peak memory 211112 kb
Host smart-81f606dc-ca6a-468c-9601-cbff5c69b593
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=216568158 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_max_throughput_chk.216568158
Directory /workspace/27.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/27.rom_ctrl_smoke.2468258678
Short name T239
Test name
Test status
Simulation time 9009283854 ps
CPU time 17.79 seconds
Started May 14 12:51:26 PM PDT 24
Finished May 14 12:51:46 PM PDT 24
Peak memory 213896 kb
Host smart-7f39044d-a905-4adb-ac61-9dfa8f18bd96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2468258678 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_smoke.2468258678
Directory /workspace/27.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/27.rom_ctrl_stress_all.95215625
Short name T335
Test name
Test status
Simulation time 12950992398 ps
CPU time 42.33 seconds
Started May 14 12:51:28 PM PDT 24
Finished May 14 12:52:12 PM PDT 24
Peak memory 219332 kb
Host smart-7676c9cb-cc94-4bcb-a6f4-717188c12e4d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=95215625 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +U
VM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n
ame 27.rom_ctrl_stress_all.95215625
Directory /workspace/27.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/28.rom_ctrl_alert_test.846236113
Short name T124
Test name
Test status
Simulation time 3446342609 ps
CPU time 12.66 seconds
Started May 14 12:51:26 PM PDT 24
Finished May 14 12:51:42 PM PDT 24
Peak memory 211192 kb
Host smart-b4508bfc-f665-425b-a084-14459280b4ac
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=846236113 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_alert_test.846236113
Directory /workspace/28.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/28.rom_ctrl_corrupt_sig_fatal_chk.1000266472
Short name T161
Test name
Test status
Simulation time 2230712409 ps
CPU time 133.52 seconds
Started May 14 12:51:23 PM PDT 24
Finished May 14 12:53:39 PM PDT 24
Peak memory 228156 kb
Host smart-32ff5dbd-e675-4bae-800d-677773ce414b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1000266472 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_
corrupt_sig_fatal_chk.1000266472
Directory /workspace/28.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/28.rom_ctrl_kmac_err_chk.3189066511
Short name T186
Test name
Test status
Simulation time 2137736346 ps
CPU time 22.64 seconds
Started May 14 12:51:20 PM PDT 24
Finished May 14 12:51:45 PM PDT 24
Peak memory 211908 kb
Host smart-fce8ba87-d82c-4997-b536-db87a68cb21d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3189066511 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_kmac_err_chk.3189066511
Directory /workspace/28.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/28.rom_ctrl_max_throughput_chk.1252436384
Short name T212
Test name
Test status
Simulation time 2916487089 ps
CPU time 9.59 seconds
Started May 14 12:51:24 PM PDT 24
Finished May 14 12:51:36 PM PDT 24
Peak memory 211204 kb
Host smart-5941f91c-d680-4c53-8563-101d2a6eeb88
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1252436384 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_max_throughput_chk.1252436384
Directory /workspace/28.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/28.rom_ctrl_smoke.843649814
Short name T343
Test name
Test status
Simulation time 10378636212 ps
CPU time 41.84 seconds
Started May 14 12:51:26 PM PDT 24
Finished May 14 12:52:11 PM PDT 24
Peak memory 213828 kb
Host smart-cb2612a0-b21d-4285-92c5-11d71be3d026
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=843649814 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_smoke.843649814
Directory /workspace/28.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/28.rom_ctrl_stress_all.1251003118
Short name T291
Test name
Test status
Simulation time 4579617677 ps
CPU time 32.28 seconds
Started May 14 12:51:15 PM PDT 24
Finished May 14 12:51:49 PM PDT 24
Peak memory 215908 kb
Host smart-fd644ef8-3e25-45b7-b135-f3ad8781f9f7
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1251003118 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 28.rom_ctrl_stress_all.1251003118
Directory /workspace/28.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/28.rom_ctrl_stress_all_with_rand_reset.2986729530
Short name T333
Test name
Test status
Simulation time 74224366305 ps
CPU time 680.33 seconds
Started May 14 12:51:20 PM PDT 24
Finished May 14 01:02:43 PM PDT 24
Peak memory 235868 kb
Host smart-39cfe9a6-4d9c-4452-b3ed-d0a50777a26f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2986729530 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_stress_all_with_rand_reset.2986729530
Directory /workspace/28.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/29.rom_ctrl_alert_test.4266223626
Short name T180
Test name
Test status
Simulation time 616494274 ps
CPU time 8.44 seconds
Started May 14 12:51:26 PM PDT 24
Finished May 14 12:51:37 PM PDT 24
Peak memory 211216 kb
Host smart-26913b83-d8b4-4ebc-a012-fddbd53ff9a5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4266223626 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_alert_test.4266223626
Directory /workspace/29.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/29.rom_ctrl_corrupt_sig_fatal_chk.1637653901
Short name T114
Test name
Test status
Simulation time 9897086437 ps
CPU time 112.68 seconds
Started May 14 12:51:28 PM PDT 24
Finished May 14 12:53:23 PM PDT 24
Peak memory 228396 kb
Host smart-065379d6-8092-402e-90c0-50294562565c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1637653901 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_
corrupt_sig_fatal_chk.1637653901
Directory /workspace/29.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/29.rom_ctrl_kmac_err_chk.3944240031
Short name T87
Test name
Test status
Simulation time 43357588049 ps
CPU time 29.54 seconds
Started May 14 12:51:30 PM PDT 24
Finished May 14 12:52:02 PM PDT 24
Peak memory 212344 kb
Host smart-41aa8a5c-de91-4e8f-927b-58e2c081b55e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3944240031 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_kmac_err_chk.3944240031
Directory /workspace/29.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/29.rom_ctrl_max_throughput_chk.451137934
Short name T9
Test name
Test status
Simulation time 3535724170 ps
CPU time 15.5 seconds
Started May 14 12:51:31 PM PDT 24
Finished May 14 12:51:48 PM PDT 24
Peak memory 211176 kb
Host smart-267e7017-741a-473a-8dfb-1342c36e176b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=451137934 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_max_throughput_chk.451137934
Directory /workspace/29.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/29.rom_ctrl_smoke.1675085412
Short name T236
Test name
Test status
Simulation time 16336394926 ps
CPU time 27.39 seconds
Started May 14 12:51:28 PM PDT 24
Finished May 14 12:51:57 PM PDT 24
Peak memory 214444 kb
Host smart-5cc4c65e-9dad-4d79-8470-68020d141d79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1675085412 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_smoke.1675085412
Directory /workspace/29.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/29.rom_ctrl_stress_all.3660262376
Short name T269
Test name
Test status
Simulation time 2983082707 ps
CPU time 41.93 seconds
Started May 14 12:51:29 PM PDT 24
Finished May 14 12:52:13 PM PDT 24
Peak memory 213740 kb
Host smart-057e7906-41ba-44db-b4b2-283a0340ce77
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3660262376 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 29.rom_ctrl_stress_all.3660262376
Directory /workspace/29.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/3.rom_ctrl_alert_test.3080642799
Short name T267
Test name
Test status
Simulation time 4447994776 ps
CPU time 10.71 seconds
Started May 14 12:51:11 PM PDT 24
Finished May 14 12:51:24 PM PDT 24
Peak memory 211320 kb
Host smart-3a9ac86a-8b9b-4507-a887-6e834f270c04
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3080642799 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_alert_test.3080642799
Directory /workspace/3.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/3.rom_ctrl_corrupt_sig_fatal_chk.3499717156
Short name T149
Test name
Test status
Simulation time 9577916663 ps
CPU time 129.51 seconds
Started May 14 12:50:50 PM PDT 24
Finished May 14 12:53:02 PM PDT 24
Peak memory 218484 kb
Host smart-b6a9e206-c3ad-4ae4-96e8-38496f886d33
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3499717156 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_c
orrupt_sig_fatal_chk.3499717156
Directory /workspace/3.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/3.rom_ctrl_kmac_err_chk.417559093
Short name T362
Test name
Test status
Simulation time 168933210 ps
CPU time 9.64 seconds
Started May 14 12:50:56 PM PDT 24
Finished May 14 12:51:08 PM PDT 24
Peak memory 211228 kb
Host smart-11596dae-8a7d-4d7a-9d85-7b40d7f5448b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=417559093 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_kmac_err_chk.417559093
Directory /workspace/3.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/3.rom_ctrl_max_throughput_chk.829753708
Short name T234
Test name
Test status
Simulation time 7791410034 ps
CPU time 17.38 seconds
Started May 14 12:50:53 PM PDT 24
Finished May 14 12:51:12 PM PDT 24
Peak memory 211156 kb
Host smart-a5369fef-60d8-40d9-ab76-357233767268
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=829753708 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_max_throughput_chk.829753708
Directory /workspace/3.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/3.rom_ctrl_sec_cm.3898605253
Short name T30
Test name
Test status
Simulation time 8809382849 ps
CPU time 110.45 seconds
Started May 14 12:50:59 PM PDT 24
Finished May 14 12:52:57 PM PDT 24
Peak memory 236808 kb
Host smart-b061a19e-b4ef-4957-8791-bc2cfc991433
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3898605253 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_sec_cm.3898605253
Directory /workspace/3.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/3.rom_ctrl_smoke.522894813
Short name T65
Test name
Test status
Simulation time 379605962 ps
CPU time 10.19 seconds
Started May 14 12:50:51 PM PDT 24
Finished May 14 12:51:04 PM PDT 24
Peak memory 219236 kb
Host smart-0fcd5330-239d-4ca4-b91c-552a3cb0eaa7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=522894813 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_smoke.522894813
Directory /workspace/3.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/3.rom_ctrl_stress_all.1853547790
Short name T331
Test name
Test status
Simulation time 8215775214 ps
CPU time 72.25 seconds
Started May 14 12:50:51 PM PDT 24
Finished May 14 12:52:06 PM PDT 24
Peak memory 219456 kb
Host smart-e7c20d26-a19f-4cbe-b88f-fc66785992c6
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1853547790 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 3.rom_ctrl_stress_all.1853547790
Directory /workspace/3.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/30.rom_ctrl_alert_test.2811583597
Short name T182
Test name
Test status
Simulation time 4099722304 ps
CPU time 10.61 seconds
Started May 14 12:51:36 PM PDT 24
Finished May 14 12:51:48 PM PDT 24
Peak memory 211296 kb
Host smart-6a9dd8ee-38a3-4edb-bbde-2014c58db65f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2811583597 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_alert_test.2811583597
Directory /workspace/30.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/30.rom_ctrl_corrupt_sig_fatal_chk.3742161494
Short name T183
Test name
Test status
Simulation time 1125766274 ps
CPU time 72.97 seconds
Started May 14 12:51:31 PM PDT 24
Finished May 14 12:52:46 PM PDT 24
Peak memory 235860 kb
Host smart-d198ee46-76a8-4920-ba64-9998a39bc1f2
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3742161494 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_
corrupt_sig_fatal_chk.3742161494
Directory /workspace/30.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/30.rom_ctrl_kmac_err_chk.2601304490
Short name T214
Test name
Test status
Simulation time 3933188532 ps
CPU time 32.83 seconds
Started May 14 12:51:41 PM PDT 24
Finished May 14 12:52:15 PM PDT 24
Peak memory 211896 kb
Host smart-bbbf8198-ba7d-4a7c-a7f2-b927eb733a94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2601304490 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_kmac_err_chk.2601304490
Directory /workspace/30.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/30.rom_ctrl_max_throughput_chk.3575355183
Short name T133
Test name
Test status
Simulation time 1310244132 ps
CPU time 9.8 seconds
Started May 14 12:51:31 PM PDT 24
Finished May 14 12:51:43 PM PDT 24
Peak memory 211272 kb
Host smart-3a2b2e3f-a77d-4976-b67b-f14710fa82af
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3575355183 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_max_throughput_chk.3575355183
Directory /workspace/30.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/30.rom_ctrl_smoke.1369319055
Short name T69
Test name
Test status
Simulation time 1497599089 ps
CPU time 10.28 seconds
Started May 14 12:51:30 PM PDT 24
Finished May 14 12:51:43 PM PDT 24
Peak memory 219340 kb
Host smart-1f752a57-e51c-4c5e-901c-c0f7ef4a2e09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1369319055 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_smoke.1369319055
Directory /workspace/30.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/30.rom_ctrl_stress_all.423658644
Short name T285
Test name
Test status
Simulation time 2244892009 ps
CPU time 18.03 seconds
Started May 14 12:51:30 PM PDT 24
Finished May 14 12:51:50 PM PDT 24
Peak memory 211832 kb
Host smart-ec497b90-498b-4597-b4cd-0b836d29c1a9
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=423658644 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 30.rom_ctrl_stress_all.423658644
Directory /workspace/30.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/31.rom_ctrl_alert_test.1559248144
Short name T302
Test name
Test status
Simulation time 5524685796 ps
CPU time 12.54 seconds
Started May 14 12:51:33 PM PDT 24
Finished May 14 12:51:48 PM PDT 24
Peak memory 211268 kb
Host smart-ca09e4d2-924f-4b3d-882d-1e8e8a40754e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1559248144 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_alert_test.1559248144
Directory /workspace/31.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/31.rom_ctrl_corrupt_sig_fatal_chk.2040205566
Short name T271
Test name
Test status
Simulation time 83684810672 ps
CPU time 432.41 seconds
Started May 14 12:51:31 PM PDT 24
Finished May 14 12:58:46 PM PDT 24
Peak memory 228588 kb
Host smart-111501d8-5afc-4c0e-ad2f-190de156b33b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2040205566 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_
corrupt_sig_fatal_chk.2040205566
Directory /workspace/31.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/31.rom_ctrl_kmac_err_chk.2131697188
Short name T295
Test name
Test status
Simulation time 17708809341 ps
CPU time 30.05 seconds
Started May 14 12:51:24 PM PDT 24
Finished May 14 12:51:56 PM PDT 24
Peak memory 212080 kb
Host smart-00e2fd96-e25e-41c3-b656-6531477d5c80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2131697188 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_kmac_err_chk.2131697188
Directory /workspace/31.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/31.rom_ctrl_max_throughput_chk.1219630452
Short name T297
Test name
Test status
Simulation time 2159129064 ps
CPU time 17.4 seconds
Started May 14 12:51:29 PM PDT 24
Finished May 14 12:51:49 PM PDT 24
Peak memory 211396 kb
Host smart-31212f8d-2fab-477b-acad-9a5d8cd031d4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1219630452 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_max_throughput_chk.1219630452
Directory /workspace/31.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/31.rom_ctrl_smoke.1842069291
Short name T342
Test name
Test status
Simulation time 190217549 ps
CPU time 9.97 seconds
Started May 14 12:51:31 PM PDT 24
Finished May 14 12:51:43 PM PDT 24
Peak memory 213144 kb
Host smart-9c758945-f4ce-44ef-8ed5-f526f39e7e72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1842069291 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_smoke.1842069291
Directory /workspace/31.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/31.rom_ctrl_stress_all.2992273404
Short name T140
Test name
Test status
Simulation time 5662868304 ps
CPU time 86.12 seconds
Started May 14 12:51:26 PM PDT 24
Finished May 14 12:52:55 PM PDT 24
Peak memory 216424 kb
Host smart-75f34ab1-113b-48c2-b0cf-2358ec4f7234
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2992273404 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 31.rom_ctrl_stress_all.2992273404
Directory /workspace/31.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/32.rom_ctrl_alert_test.416369327
Short name T301
Test name
Test status
Simulation time 172006867 ps
CPU time 4.21 seconds
Started May 14 12:51:25 PM PDT 24
Finished May 14 12:51:31 PM PDT 24
Peak memory 211132 kb
Host smart-4d4a4f91-20ec-49c5-9cb6-612f513601a6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=416369327 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_alert_test.416369327
Directory /workspace/32.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/32.rom_ctrl_corrupt_sig_fatal_chk.411520301
Short name T213
Test name
Test status
Simulation time 6776995029 ps
CPU time 134.62 seconds
Started May 14 12:51:25 PM PDT 24
Finished May 14 12:53:42 PM PDT 24
Peak memory 228688 kb
Host smart-ae54a6e1-ecd5-4598-8de1-2ce852945384
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=411520301 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_c
orrupt_sig_fatal_chk.411520301
Directory /workspace/32.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/32.rom_ctrl_kmac_err_chk.800162002
Short name T299
Test name
Test status
Simulation time 4029714373 ps
CPU time 32.38 seconds
Started May 14 12:51:43 PM PDT 24
Finished May 14 12:52:18 PM PDT 24
Peak memory 219568 kb
Host smart-eb0893bc-e3f8-45b0-a008-1525151b4885
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=800162002 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_kmac_err_chk.800162002
Directory /workspace/32.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/32.rom_ctrl_max_throughput_chk.2408784829
Short name T317
Test name
Test status
Simulation time 102644465 ps
CPU time 5.89 seconds
Started May 14 12:51:26 PM PDT 24
Finished May 14 12:51:34 PM PDT 24
Peak memory 211064 kb
Host smart-adeea98c-1595-4638-a818-e76684c08219
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2408784829 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_max_throughput_chk.2408784829
Directory /workspace/32.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/32.rom_ctrl_smoke.2693046528
Short name T270
Test name
Test status
Simulation time 1799943929 ps
CPU time 10.28 seconds
Started May 14 12:51:27 PM PDT 24
Finished May 14 12:51:40 PM PDT 24
Peak memory 219308 kb
Host smart-06336d4b-a4b0-4f5c-a6d0-38e164d0ffce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2693046528 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_smoke.2693046528
Directory /workspace/32.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/32.rom_ctrl_stress_all.2934152354
Short name T197
Test name
Test status
Simulation time 25614543863 ps
CPU time 73.22 seconds
Started May 14 12:51:20 PM PDT 24
Finished May 14 12:52:36 PM PDT 24
Peak memory 219372 kb
Host smart-6bd4bf02-b347-4468-8b51-4da908a06761
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2934152354 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 32.rom_ctrl_stress_all.2934152354
Directory /workspace/32.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/33.rom_ctrl_alert_test.617447824
Short name T196
Test name
Test status
Simulation time 1985000935 ps
CPU time 15.55 seconds
Started May 14 12:51:43 PM PDT 24
Finished May 14 12:52:01 PM PDT 24
Peak memory 211296 kb
Host smart-0ff63258-9a6e-4806-9e68-e412aff91f6c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=617447824 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_alert_test.617447824
Directory /workspace/33.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/33.rom_ctrl_corrupt_sig_fatal_chk.1747623485
Short name T176
Test name
Test status
Simulation time 9202402357 ps
CPU time 213.48 seconds
Started May 14 12:51:38 PM PDT 24
Finished May 14 12:55:13 PM PDT 24
Peak memory 224996 kb
Host smart-38c3f6c5-cc19-4cc8-86a1-c83f158119cf
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1747623485 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_
corrupt_sig_fatal_chk.1747623485
Directory /workspace/33.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/33.rom_ctrl_kmac_err_chk.1971562880
Short name T348
Test name
Test status
Simulation time 2967667792 ps
CPU time 27.65 seconds
Started May 14 12:51:26 PM PDT 24
Finished May 14 12:51:56 PM PDT 24
Peak memory 211784 kb
Host smart-683eda13-f851-4e7e-b4d4-b1368488a933
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1971562880 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_kmac_err_chk.1971562880
Directory /workspace/33.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/33.rom_ctrl_max_throughput_chk.1473708589
Short name T219
Test name
Test status
Simulation time 879059473 ps
CPU time 11.1 seconds
Started May 14 12:51:26 PM PDT 24
Finished May 14 12:51:40 PM PDT 24
Peak memory 211016 kb
Host smart-278cd140-e377-4c5f-9170-2d65d46b9113
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1473708589 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_max_throughput_chk.1473708589
Directory /workspace/33.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/33.rom_ctrl_smoke.346171502
Short name T277
Test name
Test status
Simulation time 10326951778 ps
CPU time 32.65 seconds
Started May 14 12:51:30 PM PDT 24
Finished May 14 12:52:04 PM PDT 24
Peak memory 213812 kb
Host smart-a36b7b09-248f-4588-b711-dc8e1bba14e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=346171502 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_smoke.346171502
Directory /workspace/33.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/33.rom_ctrl_stress_all.2681852991
Short name T221
Test name
Test status
Simulation time 1252420622 ps
CPU time 32.97 seconds
Started May 14 12:51:44 PM PDT 24
Finished May 14 12:52:20 PM PDT 24
Peak memory 219272 kb
Host smart-80c0fbfd-4f7c-4de2-998a-c68d75eded5f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2681852991 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 33.rom_ctrl_stress_all.2681852991
Directory /workspace/33.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/34.rom_ctrl_alert_test.4131697191
Short name T54
Test name
Test status
Simulation time 3330525430 ps
CPU time 14.22 seconds
Started May 14 12:51:30 PM PDT 24
Finished May 14 12:51:47 PM PDT 24
Peak memory 211376 kb
Host smart-b639b72a-fb86-4025-9638-01946b4c1553
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4131697191 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_alert_test.4131697191
Directory /workspace/34.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/34.rom_ctrl_kmac_err_chk.1597231659
Short name T24
Test name
Test status
Simulation time 1486857746 ps
CPU time 14.48 seconds
Started May 14 12:51:26 PM PDT 24
Finished May 14 12:51:43 PM PDT 24
Peak memory 212124 kb
Host smart-5228a038-8e8e-4496-b9b2-305260f44fd1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1597231659 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_kmac_err_chk.1597231659
Directory /workspace/34.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/34.rom_ctrl_max_throughput_chk.722729874
Short name T100
Test name
Test status
Simulation time 3367067900 ps
CPU time 14.79 seconds
Started May 14 12:51:20 PM PDT 24
Finished May 14 12:51:37 PM PDT 24
Peak memory 211156 kb
Host smart-6c5f561d-74c9-410d-99c4-adef6f1f9f07
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=722729874 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_max_throughput_chk.722729874
Directory /workspace/34.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/34.rom_ctrl_smoke.241218671
Short name T66
Test name
Test status
Simulation time 1975596347 ps
CPU time 23.1 seconds
Started May 14 12:51:32 PM PDT 24
Finished May 14 12:51:57 PM PDT 24
Peak memory 212996 kb
Host smart-32feade5-f764-4946-abdd-889c83085345
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=241218671 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_smoke.241218671
Directory /workspace/34.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/34.rom_ctrl_stress_all.253228341
Short name T166
Test name
Test status
Simulation time 1626571620 ps
CPU time 16.77 seconds
Started May 14 12:51:36 PM PDT 24
Finished May 14 12:51:54 PM PDT 24
Peak memory 213556 kb
Host smart-54f3f757-fbae-45c1-9e06-0a94dc48130d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=253228341 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 34.rom_ctrl_stress_all.253228341
Directory /workspace/34.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/35.rom_ctrl_alert_test.1444563829
Short name T336
Test name
Test status
Simulation time 517891735 ps
CPU time 4.23 seconds
Started May 14 12:51:34 PM PDT 24
Finished May 14 12:51:40 PM PDT 24
Peak memory 211144 kb
Host smart-d74d06be-d645-4de9-9371-f2122c0c7334
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1444563829 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_alert_test.1444563829
Directory /workspace/35.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/35.rom_ctrl_corrupt_sig_fatal_chk.4106923992
Short name T34
Test name
Test status
Simulation time 373558760955 ps
CPU time 244.43 seconds
Started May 14 12:51:25 PM PDT 24
Finished May 14 12:55:32 PM PDT 24
Peak memory 224964 kb
Host smart-f02bafa6-c955-40f8-88a9-1253eeff6b7c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4106923992 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_
corrupt_sig_fatal_chk.4106923992
Directory /workspace/35.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/35.rom_ctrl_kmac_err_chk.2017196792
Short name T358
Test name
Test status
Simulation time 6944243218 ps
CPU time 15.83 seconds
Started May 14 12:51:38 PM PDT 24
Finished May 14 12:51:55 PM PDT 24
Peak memory 211480 kb
Host smart-42133176-442e-4f5d-b0a2-2034b1cff95f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2017196792 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_kmac_err_chk.2017196792
Directory /workspace/35.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/35.rom_ctrl_max_throughput_chk.2264023612
Short name T201
Test name
Test status
Simulation time 7564798559 ps
CPU time 16.32 seconds
Started May 14 12:51:27 PM PDT 24
Finished May 14 12:51:46 PM PDT 24
Peak memory 211200 kb
Host smart-ad128df6-323a-44b8-adda-11d11c507f25
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2264023612 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_max_throughput_chk.2264023612
Directory /workspace/35.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/35.rom_ctrl_smoke.811614307
Short name T309
Test name
Test status
Simulation time 5631729600 ps
CPU time 21.09 seconds
Started May 14 12:51:41 PM PDT 24
Finished May 14 12:52:03 PM PDT 24
Peak memory 214132 kb
Host smart-06c1d20b-2ae6-4e42-9324-88acad8f83d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=811614307 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_smoke.811614307
Directory /workspace/35.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/35.rom_ctrl_stress_all.4248070685
Short name T292
Test name
Test status
Simulation time 16045862388 ps
CPU time 28.67 seconds
Started May 14 12:51:29 PM PDT 24
Finished May 14 12:52:00 PM PDT 24
Peak memory 219436 kb
Host smart-a37464b4-c5ba-4f6b-ac37-d0a91e4d708c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4248070685 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 35.rom_ctrl_stress_all.4248070685
Directory /workspace/35.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/36.rom_ctrl_alert_test.1288698601
Short name T193
Test name
Test status
Simulation time 1212638818 ps
CPU time 11.16 seconds
Started May 14 12:51:47 PM PDT 24
Finished May 14 12:52:02 PM PDT 24
Peak memory 211132 kb
Host smart-a5a34eac-d6b7-45fe-ab3b-b221d2cd420f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1288698601 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_alert_test.1288698601
Directory /workspace/36.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/36.rom_ctrl_corrupt_sig_fatal_chk.261226836
Short name T188
Test name
Test status
Simulation time 6184786806 ps
CPU time 95.56 seconds
Started May 14 12:51:31 PM PDT 24
Finished May 14 12:53:09 PM PDT 24
Peak memory 231864 kb
Host smart-cf5a027f-ff04-42fb-afe3-6e8035de4cea
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=261226836 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_c
orrupt_sig_fatal_chk.261226836
Directory /workspace/36.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/36.rom_ctrl_kmac_err_chk.3755895283
Short name T25
Test name
Test status
Simulation time 6653961096 ps
CPU time 18.99 seconds
Started May 14 12:51:39 PM PDT 24
Finished May 14 12:51:59 PM PDT 24
Peak memory 212196 kb
Host smart-05ba43fe-bdd5-4481-b871-c01f02fba873
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3755895283 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_kmac_err_chk.3755895283
Directory /workspace/36.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/36.rom_ctrl_max_throughput_chk.1063514416
Short name T120
Test name
Test status
Simulation time 5817578768 ps
CPU time 9.7 seconds
Started May 14 12:51:33 PM PDT 24
Finished May 14 12:51:45 PM PDT 24
Peak memory 211164 kb
Host smart-8c87d4a8-43c9-458a-9695-d6a8a21d8797
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1063514416 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_max_throughput_chk.1063514416
Directory /workspace/36.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/36.rom_ctrl_smoke.3240654019
Short name T313
Test name
Test status
Simulation time 2435267628 ps
CPU time 14.57 seconds
Started May 14 12:51:25 PM PDT 24
Finished May 14 12:51:42 PM PDT 24
Peak memory 219360 kb
Host smart-9b3e90ef-cf7a-496c-a4c4-b040dddd9c46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3240654019 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_smoke.3240654019
Directory /workspace/36.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/36.rom_ctrl_stress_all.2703837499
Short name T170
Test name
Test status
Simulation time 1123529677 ps
CPU time 13.46 seconds
Started May 14 12:51:42 PM PDT 24
Finished May 14 12:51:57 PM PDT 24
Peak memory 211044 kb
Host smart-d04d8d9c-00e3-4968-88f1-2a41614c356f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2703837499 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 36.rom_ctrl_stress_all.2703837499
Directory /workspace/36.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/37.rom_ctrl_alert_test.2017053168
Short name T53
Test name
Test status
Simulation time 348211790 ps
CPU time 4.17 seconds
Started May 14 12:51:44 PM PDT 24
Finished May 14 12:51:50 PM PDT 24
Peak memory 211200 kb
Host smart-90a0d0e4-0f4a-4edc-9a1b-f40064e6d403
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2017053168 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_alert_test.2017053168
Directory /workspace/37.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/37.rom_ctrl_corrupt_sig_fatal_chk.3266605588
Short name T158
Test name
Test status
Simulation time 1550277096 ps
CPU time 62.71 seconds
Started May 14 12:51:40 PM PDT 24
Finished May 14 12:52:44 PM PDT 24
Peak memory 232624 kb
Host smart-0a9cb88d-35f3-4c66-869e-e914acb416b1
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3266605588 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_
corrupt_sig_fatal_chk.3266605588
Directory /workspace/37.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/37.rom_ctrl_kmac_err_chk.782729523
Short name T137
Test name
Test status
Simulation time 7897346252 ps
CPU time 21.37 seconds
Started May 14 12:51:49 PM PDT 24
Finished May 14 12:52:15 PM PDT 24
Peak memory 212160 kb
Host smart-e2d52170-f1e8-4d8f-b8d2-cf1d28d488bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=782729523 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_kmac_err_chk.782729523
Directory /workspace/37.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/37.rom_ctrl_max_throughput_chk.512062887
Short name T319
Test name
Test status
Simulation time 10506771742 ps
CPU time 12.67 seconds
Started May 14 12:51:46 PM PDT 24
Finished May 14 12:52:03 PM PDT 24
Peak memory 211232 kb
Host smart-565e73a2-363d-4958-9589-9afc32f17c5f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=512062887 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_max_throughput_chk.512062887
Directory /workspace/37.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/37.rom_ctrl_smoke.1739929402
Short name T227
Test name
Test status
Simulation time 7232061960 ps
CPU time 21.27 seconds
Started May 14 12:51:45 PM PDT 24
Finished May 14 12:52:09 PM PDT 24
Peak memory 219364 kb
Host smart-5843cf1d-db33-4aac-a854-6ac1d21345ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1739929402 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_smoke.1739929402
Directory /workspace/37.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/37.rom_ctrl_stress_all.4129231420
Short name T240
Test name
Test status
Simulation time 11930186796 ps
CPU time 11.72 seconds
Started May 14 12:51:43 PM PDT 24
Finished May 14 12:51:57 PM PDT 24
Peak memory 212352 kb
Host smart-faa4fd17-ad1c-4dde-944d-644e735ffb04
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4129231420 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 37.rom_ctrl_stress_all.4129231420
Directory /workspace/37.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/38.rom_ctrl_alert_test.2333411671
Short name T178
Test name
Test status
Simulation time 8547658311 ps
CPU time 17.49 seconds
Started May 14 12:51:45 PM PDT 24
Finished May 14 12:52:06 PM PDT 24
Peak memory 211408 kb
Host smart-a60727e7-57d0-42cf-a53a-8603909fb764
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2333411671 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_alert_test.2333411671
Directory /workspace/38.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/38.rom_ctrl_corrupt_sig_fatal_chk.2831216354
Short name T26
Test name
Test status
Simulation time 13244931486 ps
CPU time 189.02 seconds
Started May 14 12:51:46 PM PDT 24
Finished May 14 12:54:59 PM PDT 24
Peak memory 227800 kb
Host smart-b6558e76-f04a-409a-bd37-c0e3bf9b4ced
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2831216354 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_
corrupt_sig_fatal_chk.2831216354
Directory /workspace/38.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/38.rom_ctrl_kmac_err_chk.4195915609
Short name T344
Test name
Test status
Simulation time 4260765499 ps
CPU time 26.11 seconds
Started May 14 12:51:35 PM PDT 24
Finished May 14 12:52:02 PM PDT 24
Peak memory 212204 kb
Host smart-99e3854b-c05c-40f3-a599-b1ca61842d32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4195915609 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_kmac_err_chk.4195915609
Directory /workspace/38.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/38.rom_ctrl_max_throughput_chk.3689696967
Short name T281
Test name
Test status
Simulation time 1985238845 ps
CPU time 8.78 seconds
Started May 14 12:51:49 PM PDT 24
Finished May 14 12:52:02 PM PDT 24
Peak memory 211076 kb
Host smart-041d6c76-115f-4f6f-9d41-5783e224d712
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3689696967 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_max_throughput_chk.3689696967
Directory /workspace/38.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/38.rom_ctrl_smoke.4045421569
Short name T46
Test name
Test status
Simulation time 8610305359 ps
CPU time 38.59 seconds
Started May 14 12:51:31 PM PDT 24
Finished May 14 12:52:12 PM PDT 24
Peak memory 219392 kb
Host smart-0145bbac-68f4-4749-922b-cca3a1fbd96d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4045421569 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_smoke.4045421569
Directory /workspace/38.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/38.rom_ctrl_stress_all.2714125094
Short name T250
Test name
Test status
Simulation time 5012512310 ps
CPU time 31.96 seconds
Started May 14 12:51:45 PM PDT 24
Finished May 14 12:52:20 PM PDT 24
Peak memory 219380 kb
Host smart-0193c079-9733-45b2-a3db-1ed934cd2c9d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2714125094 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 38.rom_ctrl_stress_all.2714125094
Directory /workspace/38.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/39.rom_ctrl_alert_test.1455710881
Short name T148
Test name
Test status
Simulation time 2216380764 ps
CPU time 11.14 seconds
Started May 14 12:51:43 PM PDT 24
Finished May 14 12:51:56 PM PDT 24
Peak memory 211284 kb
Host smart-185adbb1-5d12-4131-a452-9d73b603be8e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1455710881 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_alert_test.1455710881
Directory /workspace/39.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/39.rom_ctrl_kmac_err_chk.1391227917
Short name T303
Test name
Test status
Simulation time 7883173394 ps
CPU time 32.62 seconds
Started May 14 12:51:42 PM PDT 24
Finished May 14 12:52:16 PM PDT 24
Peak memory 212212 kb
Host smart-a7670330-2dfc-4f7e-a3da-5dfec0cf9f5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1391227917 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_kmac_err_chk.1391227917
Directory /workspace/39.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/39.rom_ctrl_max_throughput_chk.2916505121
Short name T294
Test name
Test status
Simulation time 6375532683 ps
CPU time 14.44 seconds
Started May 14 12:51:37 PM PDT 24
Finished May 14 12:51:53 PM PDT 24
Peak memory 211084 kb
Host smart-32bc0f48-ea17-4a6d-9df0-8b8fbbf2c9fc
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2916505121 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_max_throughput_chk.2916505121
Directory /workspace/39.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/39.rom_ctrl_smoke.2281311291
Short name T305
Test name
Test status
Simulation time 1081016740 ps
CPU time 10.3 seconds
Started May 14 12:51:29 PM PDT 24
Finished May 14 12:51:42 PM PDT 24
Peak memory 213628 kb
Host smart-c2f82042-63f5-4706-aae1-ede26e19e694
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2281311291 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_smoke.2281311291
Directory /workspace/39.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/39.rom_ctrl_stress_all.1588459329
Short name T256
Test name
Test status
Simulation time 4223452325 ps
CPU time 46.08 seconds
Started May 14 12:51:46 PM PDT 24
Finished May 14 12:52:37 PM PDT 24
Peak memory 219384 kb
Host smart-d437dfd4-996f-48a7-b1f1-18028867bb24
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1588459329 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 39.rom_ctrl_stress_all.1588459329
Directory /workspace/39.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/39.rom_ctrl_stress_all_with_rand_reset.1106308358
Short name T102
Test name
Test status
Simulation time 83387528988 ps
CPU time 3275.69 seconds
Started May 14 12:51:38 PM PDT 24
Finished May 14 01:46:16 PM PDT 24
Peak memory 230440 kb
Host smart-9743e7fe-f880-49e2-b2dc-1d7a9e4d3def
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1106308358 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_stress_all_with_rand_reset.1106308358
Directory /workspace/39.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.rom_ctrl_alert_test.195901501
Short name T278
Test name
Test status
Simulation time 1881541418 ps
CPU time 15.1 seconds
Started May 14 12:50:57 PM PDT 24
Finished May 14 12:51:15 PM PDT 24
Peak memory 211132 kb
Host smart-9ba97a35-6e32-448e-a535-4ef5d2d7abb2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=195901501 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_alert_test.195901501
Directory /workspace/4.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/4.rom_ctrl_corrupt_sig_fatal_chk.469902806
Short name T249
Test name
Test status
Simulation time 2988645544 ps
CPU time 89.25 seconds
Started May 14 12:50:55 PM PDT 24
Finished May 14 12:52:26 PM PDT 24
Peak memory 228572 kb
Host smart-23164410-8899-45c4-8d41-be8b849232d6
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=469902806 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_co
rrupt_sig_fatal_chk.469902806
Directory /workspace/4.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/4.rom_ctrl_kmac_err_chk.3881819397
Short name T262
Test name
Test status
Simulation time 9612791152 ps
CPU time 23.14 seconds
Started May 14 12:51:12 PM PDT 24
Finished May 14 12:51:38 PM PDT 24
Peak memory 211348 kb
Host smart-a7a0e3a0-462e-493c-8931-19dccf013b02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3881819397 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_kmac_err_chk.3881819397
Directory /workspace/4.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/4.rom_ctrl_max_throughput_chk.1801344867
Short name T233
Test name
Test status
Simulation time 1643267911 ps
CPU time 14.47 seconds
Started May 14 12:51:14 PM PDT 24
Finished May 14 12:51:30 PM PDT 24
Peak memory 210992 kb
Host smart-fc161793-058d-43e1-8239-2afd511958c9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1801344867 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_max_throughput_chk.1801344867
Directory /workspace/4.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/4.rom_ctrl_sec_cm.1341046846
Short name T33
Test name
Test status
Simulation time 1466910131 ps
CPU time 106.64 seconds
Started May 14 12:50:58 PM PDT 24
Finished May 14 12:52:47 PM PDT 24
Peak memory 237908 kb
Host smart-179af301-3239-476f-a52e-74ee2e59a19f
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1341046846 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_sec_cm.1341046846
Directory /workspace/4.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/4.rom_ctrl_smoke.3951343180
Short name T215
Test name
Test status
Simulation time 21482825316 ps
CPU time 25.78 seconds
Started May 14 12:50:58 PM PDT 24
Finished May 14 12:51:27 PM PDT 24
Peak memory 219380 kb
Host smart-791bcfb1-82cf-4d9f-a9fc-71ebd50b80f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3951343180 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_smoke.3951343180
Directory /workspace/4.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/4.rom_ctrl_stress_all.1193675749
Short name T184
Test name
Test status
Simulation time 3671564375 ps
CPU time 20.19 seconds
Started May 14 12:51:06 PM PDT 24
Finished May 14 12:51:28 PM PDT 24
Peak memory 213188 kb
Host smart-b7983e47-ec02-4eed-9a53-800291fcf54d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1193675749 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 4.rom_ctrl_stress_all.1193675749
Directory /workspace/4.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/4.rom_ctrl_stress_all_with_rand_reset.2341824103
Short name T40
Test name
Test status
Simulation time 554718759353 ps
CPU time 2261.32 seconds
Started May 14 12:51:16 PM PDT 24
Finished May 14 01:29:00 PM PDT 24
Peak memory 237936 kb
Host smart-dfe56eb6-4966-4773-b837-cac31e831469
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2341824103 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_stress_all_with_rand_reset.2341824103
Directory /workspace/4.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.rom_ctrl_alert_test.4042169986
Short name T307
Test name
Test status
Simulation time 171528013 ps
CPU time 4.27 seconds
Started May 14 12:51:31 PM PDT 24
Finished May 14 12:51:38 PM PDT 24
Peak memory 211144 kb
Host smart-30d57e67-876d-45c0-ac52-a585110e8a38
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4042169986 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_alert_test.4042169986
Directory /workspace/40.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/40.rom_ctrl_corrupt_sig_fatal_chk.67735979
Short name T290
Test name
Test status
Simulation time 19717658552 ps
CPU time 241.07 seconds
Started May 14 12:51:48 PM PDT 24
Finished May 14 12:55:54 PM PDT 24
Peak memory 237864 kb
Host smart-9185273e-3266-4334-9003-917920ec22a0
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=67735979 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_
sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_co
rrupt_sig_fatal_chk.67735979
Directory /workspace/40.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/40.rom_ctrl_kmac_err_chk.2827035375
Short name T191
Test name
Test status
Simulation time 8498625043 ps
CPU time 22.28 seconds
Started May 14 12:51:43 PM PDT 24
Finished May 14 12:52:07 PM PDT 24
Peak memory 212428 kb
Host smart-a6f3f324-a27b-4e32-b670-04c9a1eca595
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2827035375 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_kmac_err_chk.2827035375
Directory /workspace/40.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/40.rom_ctrl_max_throughput_chk.2850995741
Short name T139
Test name
Test status
Simulation time 8469592462 ps
CPU time 17.48 seconds
Started May 14 12:51:29 PM PDT 24
Finished May 14 12:51:48 PM PDT 24
Peak memory 211072 kb
Host smart-66eac034-7757-42e6-b547-50fcbb857359
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2850995741 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_max_throughput_chk.2850995741
Directory /workspace/40.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/40.rom_ctrl_smoke.171764410
Short name T64
Test name
Test status
Simulation time 3239304520 ps
CPU time 16.11 seconds
Started May 14 12:51:42 PM PDT 24
Finished May 14 12:51:59 PM PDT 24
Peak memory 219356 kb
Host smart-fb337ecb-6736-4255-8059-68cf575a2e28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=171764410 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_smoke.171764410
Directory /workspace/40.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/40.rom_ctrl_stress_all.94662752
Short name T119
Test name
Test status
Simulation time 5338255159 ps
CPU time 51.98 seconds
Started May 14 12:51:33 PM PDT 24
Finished May 14 12:52:27 PM PDT 24
Peak memory 219440 kb
Host smart-ea5bea3d-c8df-4fc2-9405-4c14a9c171f2
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=94662752 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +U
VM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n
ame 40.rom_ctrl_stress_all.94662752
Directory /workspace/40.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/41.rom_ctrl_alert_test.3018660549
Short name T308
Test name
Test status
Simulation time 5854856753 ps
CPU time 13.06 seconds
Started May 14 12:51:44 PM PDT 24
Finished May 14 12:52:00 PM PDT 24
Peak memory 211308 kb
Host smart-1a1a8aa6-f4d0-4add-a8fd-1f235d57f4a5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3018660549 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_alert_test.3018660549
Directory /workspace/41.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/41.rom_ctrl_corrupt_sig_fatal_chk.256823166
Short name T84
Test name
Test status
Simulation time 36339465452 ps
CPU time 358.76 seconds
Started May 14 12:51:46 PM PDT 24
Finished May 14 12:57:48 PM PDT 24
Peak memory 228476 kb
Host smart-fbd057d1-f36a-4600-873b-5fcc349dc9bb
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=256823166 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_c
orrupt_sig_fatal_chk.256823166
Directory /workspace/41.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/41.rom_ctrl_kmac_err_chk.1594990237
Short name T338
Test name
Test status
Simulation time 1970896142 ps
CPU time 21.93 seconds
Started May 14 12:51:45 PM PDT 24
Finished May 14 12:52:10 PM PDT 24
Peak memory 211692 kb
Host smart-74a7d58a-d21e-4093-ab81-7135913aa448
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1594990237 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_kmac_err_chk.1594990237
Directory /workspace/41.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/41.rom_ctrl_max_throughput_chk.2017563856
Short name T116
Test name
Test status
Simulation time 94373959 ps
CPU time 5.53 seconds
Started May 14 12:51:45 PM PDT 24
Finished May 14 12:51:53 PM PDT 24
Peak memory 211072 kb
Host smart-f0493d2f-fdd5-4084-a42d-1813029dfba6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2017563856 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_max_throughput_chk.2017563856
Directory /workspace/41.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/41.rom_ctrl_smoke.3753676711
Short name T154
Test name
Test status
Simulation time 3182121913 ps
CPU time 15.36 seconds
Started May 14 12:51:30 PM PDT 24
Finished May 14 12:51:47 PM PDT 24
Peak memory 213624 kb
Host smart-bf8714ab-7050-44b0-8fdc-fa8c179ab8d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3753676711 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_smoke.3753676711
Directory /workspace/41.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/41.rom_ctrl_stress_all.2854269127
Short name T90
Test name
Test status
Simulation time 813203213 ps
CPU time 17.01 seconds
Started May 14 12:51:35 PM PDT 24
Finished May 14 12:51:53 PM PDT 24
Peak memory 219320 kb
Host smart-a628ffa3-1200-4f03-922f-eb77781f32a7
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2854269127 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 41.rom_ctrl_stress_all.2854269127
Directory /workspace/41.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/42.rom_ctrl_alert_test.301357129
Short name T231
Test name
Test status
Simulation time 1561800861 ps
CPU time 12.55 seconds
Started May 14 12:51:46 PM PDT 24
Finished May 14 12:52:01 PM PDT 24
Peak memory 211132 kb
Host smart-0a14531c-a79a-4994-a40b-a98faa6db685
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=301357129 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_alert_test.301357129
Directory /workspace/42.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/42.rom_ctrl_corrupt_sig_fatal_chk.3599803682
Short name T237
Test name
Test status
Simulation time 136973413527 ps
CPU time 401.69 seconds
Started May 14 12:51:41 PM PDT 24
Finished May 14 12:58:23 PM PDT 24
Peak memory 234068 kb
Host smart-e9299d18-5f15-46f7-8ec0-4d23fca8dfd2
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3599803682 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_
corrupt_sig_fatal_chk.3599803682
Directory /workspace/42.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/42.rom_ctrl_kmac_err_chk.2470018916
Short name T190
Test name
Test status
Simulation time 5927946952 ps
CPU time 18.5 seconds
Started May 14 12:51:30 PM PDT 24
Finished May 14 12:51:50 PM PDT 24
Peak memory 212572 kb
Host smart-8b9c696e-6bec-41b1-8af1-355fb6403977
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2470018916 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_kmac_err_chk.2470018916
Directory /workspace/42.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/42.rom_ctrl_max_throughput_chk.3605361225
Short name T155
Test name
Test status
Simulation time 3691172119 ps
CPU time 15.65 seconds
Started May 14 12:51:44 PM PDT 24
Finished May 14 12:52:01 PM PDT 24
Peak memory 211100 kb
Host smart-2ffecff7-e39e-46d5-90b3-18032bb7d99a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3605361225 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_max_throughput_chk.3605361225
Directory /workspace/42.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/42.rom_ctrl_smoke.1521465753
Short name T143
Test name
Test status
Simulation time 11820159341 ps
CPU time 30.49 seconds
Started May 14 12:51:46 PM PDT 24
Finished May 14 12:52:19 PM PDT 24
Peak memory 219288 kb
Host smart-022fc173-1424-4be0-8b75-8930f0088258
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1521465753 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_smoke.1521465753
Directory /workspace/42.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/42.rom_ctrl_stress_all.2612077453
Short name T286
Test name
Test status
Simulation time 7891290214 ps
CPU time 87.73 seconds
Started May 14 12:51:29 PM PDT 24
Finished May 14 12:52:59 PM PDT 24
Peak memory 219396 kb
Host smart-9a90625c-3c50-499e-99ef-5ad52618128d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2612077453 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 42.rom_ctrl_stress_all.2612077453
Directory /workspace/42.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/43.rom_ctrl_alert_test.3777230755
Short name T44
Test name
Test status
Simulation time 4949370175 ps
CPU time 11.53 seconds
Started May 14 12:51:45 PM PDT 24
Finished May 14 12:51:59 PM PDT 24
Peak memory 211288 kb
Host smart-4d32ff22-51bc-432b-808b-fa991f728210
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3777230755 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_alert_test.3777230755
Directory /workspace/43.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/43.rom_ctrl_corrupt_sig_fatal_chk.1542487864
Short name T272
Test name
Test status
Simulation time 51238571575 ps
CPU time 509.1 seconds
Started May 14 12:51:29 PM PDT 24
Finished May 14 01:00:00 PM PDT 24
Peak memory 228668 kb
Host smart-29e42041-019e-4cf7-99bd-1ea1d3ca6373
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1542487864 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_
corrupt_sig_fatal_chk.1542487864
Directory /workspace/43.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/43.rom_ctrl_kmac_err_chk.2652066962
Short name T248
Test name
Test status
Simulation time 2144765683 ps
CPU time 21.8 seconds
Started May 14 12:51:42 PM PDT 24
Finished May 14 12:52:05 PM PDT 24
Peak memory 211712 kb
Host smart-b400f043-8f1e-4956-9fe8-9528c454ebd9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2652066962 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_kmac_err_chk.2652066962
Directory /workspace/43.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/43.rom_ctrl_max_throughput_chk.736150507
Short name T99
Test name
Test status
Simulation time 1047956510 ps
CPU time 11.43 seconds
Started May 14 12:51:36 PM PDT 24
Finished May 14 12:51:49 PM PDT 24
Peak memory 210996 kb
Host smart-c6cb0072-acbf-4bae-b07a-a1996d466911
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=736150507 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_max_throughput_chk.736150507
Directory /workspace/43.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/43.rom_ctrl_smoke.769529558
Short name T296
Test name
Test status
Simulation time 1693948848 ps
CPU time 22.07 seconds
Started May 14 12:51:36 PM PDT 24
Finished May 14 12:51:59 PM PDT 24
Peak memory 212728 kb
Host smart-df7c7287-14d6-4c49-a607-6af70fca009a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=769529558 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_smoke.769529558
Directory /workspace/43.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/43.rom_ctrl_stress_all.413798318
Short name T359
Test name
Test status
Simulation time 547835259 ps
CPU time 26.32 seconds
Started May 14 12:51:30 PM PDT 24
Finished May 14 12:51:59 PM PDT 24
Peak memory 219300 kb
Host smart-8dd137aa-8b62-4d4d-a122-7bb78f04c1e2
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=413798318 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 43.rom_ctrl_stress_all.413798318
Directory /workspace/43.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/43.rom_ctrl_stress_all_with_rand_reset.1112510586
Short name T41
Test name
Test status
Simulation time 47825365915 ps
CPU time 5111.5 seconds
Started May 14 12:51:47 PM PDT 24
Finished May 14 02:17:03 PM PDT 24
Peak memory 235880 kb
Host smart-4d5c30c4-5156-4f6a-8144-ef8c2b9e0356
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1112510586 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_stress_all_with_rand_reset.1112510586
Directory /workspace/43.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.rom_ctrl_alert_test.3704587641
Short name T351
Test name
Test status
Simulation time 7332659818 ps
CPU time 15.2 seconds
Started May 14 12:51:43 PM PDT 24
Finished May 14 12:51:59 PM PDT 24
Peak memory 211304 kb
Host smart-0a40c080-2087-4f82-a5e5-7659489a55a7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3704587641 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_alert_test.3704587641
Directory /workspace/44.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/44.rom_ctrl_corrupt_sig_fatal_chk.2396150122
Short name T35
Test name
Test status
Simulation time 8388629603 ps
CPU time 123.86 seconds
Started May 14 12:51:48 PM PDT 24
Finished May 14 12:53:56 PM PDT 24
Peak memory 225136 kb
Host smart-f21bd362-f8ab-4c4f-8e18-b5c7d2f78e72
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2396150122 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_
corrupt_sig_fatal_chk.2396150122
Directory /workspace/44.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/44.rom_ctrl_kmac_err_chk.712292931
Short name T289
Test name
Test status
Simulation time 1035980168 ps
CPU time 9.56 seconds
Started May 14 12:51:48 PM PDT 24
Finished May 14 12:52:02 PM PDT 24
Peak memory 211168 kb
Host smart-916f755e-cd2d-4609-92ed-4244d025e712
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=712292931 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_kmac_err_chk.712292931
Directory /workspace/44.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/44.rom_ctrl_max_throughput_chk.483182345
Short name T202
Test name
Test status
Simulation time 1014724845 ps
CPU time 7.28 seconds
Started May 14 12:51:41 PM PDT 24
Finished May 14 12:51:49 PM PDT 24
Peak memory 211044 kb
Host smart-b84f6e25-58fd-4184-a552-e805e1e616ed
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=483182345 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_max_throughput_chk.483182345
Directory /workspace/44.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/44.rom_ctrl_smoke.3482403684
Short name T7
Test name
Test status
Simulation time 4265790568 ps
CPU time 39.78 seconds
Started May 14 12:51:41 PM PDT 24
Finished May 14 12:52:21 PM PDT 24
Peak memory 219460 kb
Host smart-32cc2abf-d94f-46c8-881d-ae180d3d9d8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3482403684 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_smoke.3482403684
Directory /workspace/44.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/44.rom_ctrl_stress_all.3512388299
Short name T12
Test name
Test status
Simulation time 9866645473 ps
CPU time 26.6 seconds
Started May 14 12:51:33 PM PDT 24
Finished May 14 12:52:02 PM PDT 24
Peak memory 213676 kb
Host smart-d80b8ece-609d-41ba-9741-0fc9fe2f0ee8
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3512388299 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 44.rom_ctrl_stress_all.3512388299
Directory /workspace/44.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/44.rom_ctrl_stress_all_with_rand_reset.3409247250
Short name T16
Test name
Test status
Simulation time 46508042928 ps
CPU time 4763 seconds
Started May 14 12:51:34 PM PDT 24
Finished May 14 02:10:59 PM PDT 24
Peak memory 235964 kb
Host smart-04df3cf6-d30e-43d2-8486-0277bc20c324
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3409247250 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_stress_all_with_rand_reset.3409247250
Directory /workspace/44.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.rom_ctrl_alert_test.230329683
Short name T349
Test name
Test status
Simulation time 1371829295 ps
CPU time 6.61 seconds
Started May 14 12:51:46 PM PDT 24
Finished May 14 12:51:56 PM PDT 24
Peak memory 211208 kb
Host smart-422ab27f-2495-44d9-88f9-3d35f075470b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=230329683 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_alert_test.230329683
Directory /workspace/45.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/45.rom_ctrl_corrupt_sig_fatal_chk.4120561101
Short name T88
Test name
Test status
Simulation time 2409157224 ps
CPU time 150.72 seconds
Started May 14 12:51:52 PM PDT 24
Finished May 14 12:54:27 PM PDT 24
Peak memory 224760 kb
Host smart-da2e7b0e-a20a-4002-91a5-aee01aa36d02
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4120561101 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_
corrupt_sig_fatal_chk.4120561101
Directory /workspace/45.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/45.rom_ctrl_kmac_err_chk.2076904489
Short name T332
Test name
Test status
Simulation time 3543446499 ps
CPU time 29.61 seconds
Started May 14 12:51:42 PM PDT 24
Finished May 14 12:52:13 PM PDT 24
Peak memory 211884 kb
Host smart-a007a1d9-fd2d-49b8-9642-500c0078e953
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2076904489 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_kmac_err_chk.2076904489
Directory /workspace/45.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/45.rom_ctrl_max_throughput_chk.2763261741
Short name T22
Test name
Test status
Simulation time 1756389672 ps
CPU time 15.4 seconds
Started May 14 12:51:51 PM PDT 24
Finished May 14 12:52:11 PM PDT 24
Peak memory 211072 kb
Host smart-30bf0cb2-53fb-45c9-befd-4214b730b201
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2763261741 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_max_throughput_chk.2763261741
Directory /workspace/45.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/45.rom_ctrl_smoke.2886333014
Short name T353
Test name
Test status
Simulation time 24770605693 ps
CPU time 23.16 seconds
Started May 14 12:51:49 PM PDT 24
Finished May 14 12:52:16 PM PDT 24
Peak memory 219460 kb
Host smart-453e8390-1e51-4aaf-a978-7c475b5dd850
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2886333014 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_smoke.2886333014
Directory /workspace/45.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/45.rom_ctrl_stress_all.2218905754
Short name T340
Test name
Test status
Simulation time 275319172 ps
CPU time 14.97 seconds
Started May 14 12:51:47 PM PDT 24
Finished May 14 12:52:07 PM PDT 24
Peak memory 214756 kb
Host smart-c587a2f1-3b2c-4633-8698-2fad28d4ec6b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2218905754 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 45.rom_ctrl_stress_all.2218905754
Directory /workspace/45.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/46.rom_ctrl_alert_test.2323825301
Short name T152
Test name
Test status
Simulation time 4598182054 ps
CPU time 11.78 seconds
Started May 14 12:51:49 PM PDT 24
Finished May 14 12:52:05 PM PDT 24
Peak memory 211356 kb
Host smart-4ae3f7cf-e9e1-4e49-979e-258219de3c60
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2323825301 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_alert_test.2323825301
Directory /workspace/46.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/46.rom_ctrl_corrupt_sig_fatal_chk.1245284431
Short name T254
Test name
Test status
Simulation time 95298319890 ps
CPU time 253.71 seconds
Started May 14 12:51:47 PM PDT 24
Finished May 14 12:56:05 PM PDT 24
Peak memory 236752 kb
Host smart-38460e5a-b5dd-4caa-87ea-298db274b605
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1245284431 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_
corrupt_sig_fatal_chk.1245284431
Directory /workspace/46.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/46.rom_ctrl_kmac_err_chk.614819001
Short name T168
Test name
Test status
Simulation time 4351557800 ps
CPU time 34.69 seconds
Started May 14 12:51:48 PM PDT 24
Finished May 14 12:52:27 PM PDT 24
Peak memory 212020 kb
Host smart-69114cb3-ebee-4378-8e05-f97ca3a6b063
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=614819001 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_kmac_err_chk.614819001
Directory /workspace/46.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/46.rom_ctrl_max_throughput_chk.3856209025
Short name T151
Test name
Test status
Simulation time 8414382312 ps
CPU time 16.54 seconds
Started May 14 12:51:49 PM PDT 24
Finished May 14 12:52:09 PM PDT 24
Peak memory 211156 kb
Host smart-eda6cdbd-8bf8-496e-8d00-8ec664199c22
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3856209025 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_max_throughput_chk.3856209025
Directory /workspace/46.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/46.rom_ctrl_smoke.1742283416
Short name T314
Test name
Test status
Simulation time 185645340 ps
CPU time 10.16 seconds
Started May 14 12:51:46 PM PDT 24
Finished May 14 12:51:59 PM PDT 24
Peak memory 213100 kb
Host smart-d1bc97c9-ba2e-48a2-9055-9637db56bd69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1742283416 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_smoke.1742283416
Directory /workspace/46.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/46.rom_ctrl_stress_all.2715340308
Short name T13
Test name
Test status
Simulation time 1403700139 ps
CPU time 23.3 seconds
Started May 14 12:51:48 PM PDT 24
Finished May 14 12:52:16 PM PDT 24
Peak memory 212836 kb
Host smart-4141340e-dd9a-4e05-8c25-592d416d2566
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2715340308 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 46.rom_ctrl_stress_all.2715340308
Directory /workspace/46.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/47.rom_ctrl_corrupt_sig_fatal_chk.1757072934
Short name T356
Test name
Test status
Simulation time 65906925807 ps
CPU time 176.4 seconds
Started May 14 12:51:43 PM PDT 24
Finished May 14 12:54:41 PM PDT 24
Peak memory 237928 kb
Host smart-52568f1a-3cbf-48ab-9ddb-6fbbcf07e762
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1757072934 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_
corrupt_sig_fatal_chk.1757072934
Directory /workspace/47.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/47.rom_ctrl_kmac_err_chk.4253689217
Short name T357
Test name
Test status
Simulation time 1384103768 ps
CPU time 9.01 seconds
Started May 14 12:51:49 PM PDT 24
Finished May 14 12:52:03 PM PDT 24
Peak memory 211868 kb
Host smart-30304df6-f152-4686-8bad-a378f3388eef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4253689217 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_kmac_err_chk.4253689217
Directory /workspace/47.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/47.rom_ctrl_smoke.667476790
Short name T5
Test name
Test status
Simulation time 1854871255 ps
CPU time 21.25 seconds
Started May 14 12:51:50 PM PDT 24
Finished May 14 12:52:16 PM PDT 24
Peak memory 213264 kb
Host smart-619f4b7f-5865-4c46-99b9-381f89179a6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=667476790 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_smoke.667476790
Directory /workspace/47.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/47.rom_ctrl_stress_all.1484357589
Short name T287
Test name
Test status
Simulation time 4040419505 ps
CPU time 18.01 seconds
Started May 14 12:51:43 PM PDT 24
Finished May 14 12:52:04 PM PDT 24
Peak memory 211120 kb
Host smart-9f95dd10-b41a-4f31-9e1d-397e6acbdc87
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1484357589 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 47.rom_ctrl_stress_all.1484357589
Directory /workspace/47.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/48.rom_ctrl_alert_test.3179909887
Short name T2
Test name
Test status
Simulation time 2959067798 ps
CPU time 12.66 seconds
Started May 14 12:51:42 PM PDT 24
Finished May 14 12:51:56 PM PDT 24
Peak memory 211244 kb
Host smart-93e8e071-3723-4b03-8928-1dc46f9b1fb9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3179909887 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_alert_test.3179909887
Directory /workspace/48.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/48.rom_ctrl_corrupt_sig_fatal_chk.1081214880
Short name T304
Test name
Test status
Simulation time 21658933421 ps
CPU time 192.68 seconds
Started May 14 12:51:47 PM PDT 24
Finished May 14 12:55:04 PM PDT 24
Peak memory 229312 kb
Host smart-3d890315-ad4d-4d43-bdef-a8288449a9da
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1081214880 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_
corrupt_sig_fatal_chk.1081214880
Directory /workspace/48.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/48.rom_ctrl_kmac_err_chk.3833749854
Short name T18
Test name
Test status
Simulation time 333554606 ps
CPU time 10.06 seconds
Started May 14 12:51:47 PM PDT 24
Finished May 14 12:52:01 PM PDT 24
Peak memory 211920 kb
Host smart-98dc05b6-ba1e-43f7-83ba-31cbc716db62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3833749854 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_kmac_err_chk.3833749854
Directory /workspace/48.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/48.rom_ctrl_max_throughput_chk.3524749237
Short name T199
Test name
Test status
Simulation time 15111732563 ps
CPU time 14.04 seconds
Started May 14 12:51:50 PM PDT 24
Finished May 14 12:52:09 PM PDT 24
Peak memory 211116 kb
Host smart-24b3ff0d-81ea-40ba-8ec8-655b9cb43d03
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3524749237 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_max_throughput_chk.3524749237
Directory /workspace/48.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/48.rom_ctrl_smoke.479307056
Short name T157
Test name
Test status
Simulation time 665556704 ps
CPU time 10.22 seconds
Started May 14 12:51:46 PM PDT 24
Finished May 14 12:52:00 PM PDT 24
Peak memory 219344 kb
Host smart-77f49015-bcb6-442d-a7c0-978077f2c0ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=479307056 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_smoke.479307056
Directory /workspace/48.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/48.rom_ctrl_stress_all.1264433801
Short name T326
Test name
Test status
Simulation time 847119927 ps
CPU time 13.71 seconds
Started May 14 12:51:55 PM PDT 24
Finished May 14 12:52:12 PM PDT 24
Peak memory 213072 kb
Host smart-78a41e88-718d-4a75-a198-0dc7e33e647b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1264433801 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 48.rom_ctrl_stress_all.1264433801
Directory /workspace/48.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/49.rom_ctrl_alert_test.253477897
Short name T330
Test name
Test status
Simulation time 89128172 ps
CPU time 4.31 seconds
Started May 14 12:51:47 PM PDT 24
Finished May 14 12:51:56 PM PDT 24
Peak memory 211148 kb
Host smart-1c003020-c002-4ae5-8a11-953dbfe4e2c9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=253477897 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_alert_test.253477897
Directory /workspace/49.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/49.rom_ctrl_corrupt_sig_fatal_chk.1131721411
Short name T3
Test name
Test status
Simulation time 4832085538 ps
CPU time 72.69 seconds
Started May 14 12:51:48 PM PDT 24
Finished May 14 12:53:05 PM PDT 24
Peak memory 212288 kb
Host smart-dcf578ee-2f1e-46d3-8cba-c00085eabad4
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1131721411 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_
corrupt_sig_fatal_chk.1131721411
Directory /workspace/49.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/49.rom_ctrl_kmac_err_chk.509564314
Short name T135
Test name
Test status
Simulation time 7217081750 ps
CPU time 20.73 seconds
Started May 14 12:51:48 PM PDT 24
Finished May 14 12:52:13 PM PDT 24
Peak memory 213264 kb
Host smart-19c21f56-d5af-42fc-a0f3-21e5f6077160
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=509564314 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_kmac_err_chk.509564314
Directory /workspace/49.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/49.rom_ctrl_max_throughput_chk.537880124
Short name T259
Test name
Test status
Simulation time 1580504672 ps
CPU time 14.68 seconds
Started May 14 12:51:59 PM PDT 24
Finished May 14 12:52:17 PM PDT 24
Peak memory 211012 kb
Host smart-6c3aadd2-01de-4032-8a08-c930afa58f3d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=537880124 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_max_throughput_chk.537880124
Directory /workspace/49.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/49.rom_ctrl_smoke.1547377665
Short name T316
Test name
Test status
Simulation time 6904145839 ps
CPU time 21.04 seconds
Started May 14 12:51:43 PM PDT 24
Finished May 14 12:52:05 PM PDT 24
Peak memory 214460 kb
Host smart-d2f70265-8a77-4881-b20b-8cc4108adb64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1547377665 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_smoke.1547377665
Directory /workspace/49.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/49.rom_ctrl_stress_all.3264682158
Short name T216
Test name
Test status
Simulation time 6812372051 ps
CPU time 27.64 seconds
Started May 14 12:51:48 PM PDT 24
Finished May 14 12:52:20 PM PDT 24
Peak memory 214612 kb
Host smart-f7ff18b5-b7a8-4aa2-998b-660c9d23639c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3264682158 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 49.rom_ctrl_stress_all.3264682158
Directory /workspace/49.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/49.rom_ctrl_stress_all_with_rand_reset.1209825738
Short name T17
Test name
Test status
Simulation time 118249078740 ps
CPU time 2070.51 seconds
Started May 14 12:51:44 PM PDT 24
Finished May 14 01:26:17 PM PDT 24
Peak memory 236444 kb
Host smart-e90b07b2-6749-48e2-b0f1-742c68ea5995
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1209825738 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_stress_all_with_rand_reset.1209825738
Directory /workspace/49.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.rom_ctrl_alert_test.3029580213
Short name T165
Test name
Test status
Simulation time 499297406 ps
CPU time 5.08 seconds
Started May 14 12:51:06 PM PDT 24
Finished May 14 12:51:13 PM PDT 24
Peak memory 211184 kb
Host smart-a3e3d329-c5e0-4d3c-8202-efdcd4485774
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3029580213 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_alert_test.3029580213
Directory /workspace/5.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/5.rom_ctrl_corrupt_sig_fatal_chk.1401236834
Short name T293
Test name
Test status
Simulation time 20042819974 ps
CPU time 210.72 seconds
Started May 14 12:50:59 PM PDT 24
Finished May 14 12:54:32 PM PDT 24
Peak memory 228356 kb
Host smart-1d482d0d-b147-4107-8129-e4e76b14acc3
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1401236834 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_c
orrupt_sig_fatal_chk.1401236834
Directory /workspace/5.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/5.rom_ctrl_kmac_err_chk.3004064874
Short name T126
Test name
Test status
Simulation time 4088993318 ps
CPU time 33.72 seconds
Started May 14 12:50:58 PM PDT 24
Finished May 14 12:51:34 PM PDT 24
Peak memory 212072 kb
Host smart-f6f9bd01-b8e5-4537-ab2d-881bba6c5881
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3004064874 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_kmac_err_chk.3004064874
Directory /workspace/5.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/5.rom_ctrl_max_throughput_chk.2628858099
Short name T312
Test name
Test status
Simulation time 372939260 ps
CPU time 5.79 seconds
Started May 14 12:51:19 PM PDT 24
Finished May 14 12:51:27 PM PDT 24
Peak memory 211116 kb
Host smart-14e92b13-b886-4a92-8280-12adbb34b668
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2628858099 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_max_throughput_chk.2628858099
Directory /workspace/5.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/5.rom_ctrl_smoke.469684218
Short name T210
Test name
Test status
Simulation time 184537420 ps
CPU time 10.32 seconds
Started May 14 12:50:58 PM PDT 24
Finished May 14 12:51:11 PM PDT 24
Peak memory 213536 kb
Host smart-ba05d42b-f7b1-4457-a7fe-b61137b8ed56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=469684218 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_smoke.469684218
Directory /workspace/5.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/5.rom_ctrl_stress_all.86584203
Short name T361
Test name
Test status
Simulation time 1191416019 ps
CPU time 17.44 seconds
Started May 14 12:51:16 PM PDT 24
Finished May 14 12:51:35 PM PDT 24
Peak memory 216172 kb
Host smart-4c415d06-89b9-4c05-9cd1-6c2fb1fe43dd
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86584203 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +U
VM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n
ame 5.rom_ctrl_stress_all.86584203
Directory /workspace/5.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/6.rom_ctrl_alert_test.1913651562
Short name T211
Test name
Test status
Simulation time 320181151 ps
CPU time 4.5 seconds
Started May 14 12:50:57 PM PDT 24
Finished May 14 12:51:03 PM PDT 24
Peak memory 211156 kb
Host smart-5b15c2b0-bcec-47ef-8bda-f67cce0a3dc2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1913651562 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_alert_test.1913651562
Directory /workspace/6.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/6.rom_ctrl_kmac_err_chk.786801295
Short name T181
Test name
Test status
Simulation time 332424739 ps
CPU time 12.04 seconds
Started May 14 12:50:57 PM PDT 24
Finished May 14 12:51:11 PM PDT 24
Peak memory 211784 kb
Host smart-ceb2331f-5d7b-4e56-bb31-30276b1e3687
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=786801295 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_kmac_err_chk.786801295
Directory /workspace/6.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/6.rom_ctrl_max_throughput_chk.2667695526
Short name T177
Test name
Test status
Simulation time 1677302765 ps
CPU time 8.09 seconds
Started May 14 12:50:58 PM PDT 24
Finished May 14 12:51:09 PM PDT 24
Peak memory 210936 kb
Host smart-5976c24f-b92a-4e8f-9885-662c2a0783fa
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2667695526 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_max_throughput_chk.2667695526
Directory /workspace/6.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/6.rom_ctrl_smoke.1658992804
Short name T198
Test name
Test status
Simulation time 378075624 ps
CPU time 10.15 seconds
Started May 14 12:50:58 PM PDT 24
Finished May 14 12:51:11 PM PDT 24
Peak memory 219260 kb
Host smart-122882dc-0998-4096-8626-c5fe125d1e45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1658992804 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_smoke.1658992804
Directory /workspace/6.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/6.rom_ctrl_stress_all.2028444606
Short name T121
Test name
Test status
Simulation time 11242446898 ps
CPU time 28.14 seconds
Started May 14 12:51:08 PM PDT 24
Finished May 14 12:51:38 PM PDT 24
Peak memory 219416 kb
Host smart-884712f5-7170-4405-9718-2c2dc417e5f0
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2028444606 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 6.rom_ctrl_stress_all.2028444606
Directory /workspace/6.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/7.rom_ctrl_alert_test.3827940781
Short name T266
Test name
Test status
Simulation time 1961927868 ps
CPU time 7.19 seconds
Started May 14 12:51:05 PM PDT 24
Finished May 14 12:51:13 PM PDT 24
Peak memory 211212 kb
Host smart-9717d950-3dc2-4173-9ce9-02dcf5e93153
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3827940781 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_alert_test.3827940781
Directory /workspace/7.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/7.rom_ctrl_corrupt_sig_fatal_chk.822001960
Short name T275
Test name
Test status
Simulation time 12551237630 ps
CPU time 65.55 seconds
Started May 14 12:50:59 PM PDT 24
Finished May 14 12:52:07 PM PDT 24
Peak memory 219624 kb
Host smart-73e566e2-9f23-4ec0-8d97-f9c74d3739fa
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=822001960 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_co
rrupt_sig_fatal_chk.822001960
Directory /workspace/7.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/7.rom_ctrl_kmac_err_chk.640688032
Short name T131
Test name
Test status
Simulation time 19506560703 ps
CPU time 19.98 seconds
Started May 14 12:50:57 PM PDT 24
Finished May 14 12:51:19 PM PDT 24
Peak memory 212288 kb
Host smart-59409bb0-e6e4-4999-866b-f05048a74a7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=640688032 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_kmac_err_chk.640688032
Directory /workspace/7.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/7.rom_ctrl_max_throughput_chk.482819927
Short name T284
Test name
Test status
Simulation time 1237036524 ps
CPU time 12.76 seconds
Started May 14 12:50:58 PM PDT 24
Finished May 14 12:51:13 PM PDT 24
Peak memory 211064 kb
Host smart-4c0c8cae-e466-4b72-b310-5ef58a45d1c0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=482819927 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_max_throughput_chk.482819927
Directory /workspace/7.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/7.rom_ctrl_smoke.3640813689
Short name T226
Test name
Test status
Simulation time 5772470717 ps
CPU time 19.48 seconds
Started May 14 12:51:07 PM PDT 24
Finished May 14 12:51:28 PM PDT 24
Peak memory 219420 kb
Host smart-29f3338d-7bb5-48a4-8e28-d35e7d21cf22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3640813689 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_smoke.3640813689
Directory /workspace/7.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/7.rom_ctrl_stress_all.183580982
Short name T192
Test name
Test status
Simulation time 9219346509 ps
CPU time 30.09 seconds
Started May 14 12:50:57 PM PDT 24
Finished May 14 12:51:29 PM PDT 24
Peak memory 219408 kb
Host smart-ce08cddc-2ec6-466f-bfc1-5e59b315eb69
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=183580982 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 7.rom_ctrl_stress_all.183580982
Directory /workspace/7.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/8.rom_ctrl_alert_test.2566018788
Short name T89
Test name
Test status
Simulation time 171980102 ps
CPU time 4.55 seconds
Started May 14 12:51:14 PM PDT 24
Finished May 14 12:51:20 PM PDT 24
Peak memory 211300 kb
Host smart-dd9c15cf-c878-40d6-9622-6f14797cc115
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2566018788 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_alert_test.2566018788
Directory /workspace/8.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/8.rom_ctrl_corrupt_sig_fatal_chk.4024804394
Short name T162
Test name
Test status
Simulation time 64322336516 ps
CPU time 334.11 seconds
Started May 14 12:51:04 PM PDT 24
Finished May 14 12:56:39 PM PDT 24
Peak memory 225044 kb
Host smart-7027368f-8d20-4c35-9cc9-cd256460beab
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4024804394 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_c
orrupt_sig_fatal_chk.4024804394
Directory /workspace/8.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/8.rom_ctrl_kmac_err_chk.3207151072
Short name T205
Test name
Test status
Simulation time 1201666206 ps
CPU time 16.74 seconds
Started May 14 12:51:18 PM PDT 24
Finished May 14 12:51:37 PM PDT 24
Peak memory 212112 kb
Host smart-ce68f7bd-6555-46cb-a9f2-953c75dc0916
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3207151072 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_kmac_err_chk.3207151072
Directory /workspace/8.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/8.rom_ctrl_max_throughput_chk.2386277183
Short name T244
Test name
Test status
Simulation time 14583900051 ps
CPU time 15.39 seconds
Started May 14 12:50:56 PM PDT 24
Finished May 14 12:51:14 PM PDT 24
Peak memory 211164 kb
Host smart-55618000-9550-49e4-bdf8-a1266e7d200d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2386277183 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_max_throughput_chk.2386277183
Directory /workspace/8.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/8.rom_ctrl_smoke.2076766770
Short name T282
Test name
Test status
Simulation time 4279866365 ps
CPU time 17.1 seconds
Started May 14 12:51:01 PM PDT 24
Finished May 14 12:51:19 PM PDT 24
Peak memory 219368 kb
Host smart-f2a1f7b0-c20d-4d22-9367-cf601b364ee7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2076766770 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_smoke.2076766770
Directory /workspace/8.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/8.rom_ctrl_stress_all.2686590244
Short name T260
Test name
Test status
Simulation time 50140928307 ps
CPU time 71.29 seconds
Started May 14 12:50:56 PM PDT 24
Finished May 14 12:52:10 PM PDT 24
Peak memory 217360 kb
Host smart-4d7ecb33-7cfc-4960-a8ce-18e3f1991339
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2686590244 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 8.rom_ctrl_stress_all.2686590244
Directory /workspace/8.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/9.rom_ctrl_alert_test.743704912
Short name T123
Test name
Test status
Simulation time 694253785 ps
CPU time 8.37 seconds
Started May 14 12:51:01 PM PDT 24
Finished May 14 12:51:11 PM PDT 24
Peak memory 211228 kb
Host smart-0ff7720d-9510-45d4-a5a0-a048550f2e25
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=743704912 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_alert_test.743704912
Directory /workspace/9.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/9.rom_ctrl_corrupt_sig_fatal_chk.3486052648
Short name T328
Test name
Test status
Simulation time 39759223534 ps
CPU time 107.66 seconds
Started May 14 12:51:13 PM PDT 24
Finished May 14 12:53:03 PM PDT 24
Peak memory 212436 kb
Host smart-4f12d978-ea07-4c40-afdf-c7cc0de09ede
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3486052648 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_c
orrupt_sig_fatal_chk.3486052648
Directory /workspace/9.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/9.rom_ctrl_kmac_err_chk.2523353041
Short name T273
Test name
Test status
Simulation time 3168232118 ps
CPU time 20.31 seconds
Started May 14 12:51:15 PM PDT 24
Finished May 14 12:51:37 PM PDT 24
Peak memory 211692 kb
Host smart-bb955d67-7b23-42e5-be06-d12510c9b69d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2523353041 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_kmac_err_chk.2523353041
Directory /workspace/9.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/9.rom_ctrl_max_throughput_chk.924567453
Short name T1
Test name
Test status
Simulation time 3112752786 ps
CPU time 14.48 seconds
Started May 14 12:51:01 PM PDT 24
Finished May 14 12:51:17 PM PDT 24
Peak memory 211172 kb
Host smart-6041f008-3910-49ed-91e8-54a7f602aee0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=924567453 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_max_throughput_chk.924567453
Directory /workspace/9.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/9.rom_ctrl_smoke.392793262
Short name T222
Test name
Test status
Simulation time 1116340684 ps
CPU time 18.36 seconds
Started May 14 12:50:58 PM PDT 24
Finished May 14 12:51:19 PM PDT 24
Peak memory 219196 kb
Host smart-4f0f2544-b634-4304-8f65-a999501331b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=392793262 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_smoke.392793262
Directory /workspace/9.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/9.rom_ctrl_stress_all.2126163569
Short name T245
Test name
Test status
Simulation time 15186448749 ps
CPU time 48.32 seconds
Started May 14 12:51:16 PM PDT 24
Finished May 14 12:52:06 PM PDT 24
Peak memory 216952 kb
Host smart-1140620f-d03d-4a1d-86d8-110c174686e3
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2126163569 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 9.rom_ctrl_stress_all.2126163569
Directory /workspace/9.rom_ctrl_stress_all/latest
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