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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
97.62 96.97 93.01 97.88 100.00 98.37 98.03 99.07


Total test records in report: 468
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T308 /workspace/coverage/default/18.rom_ctrl_smoke.279863664 May 16 12:53:10 PM PDT 24 May 16 12:53:51 PM PDT 24 4291139549 ps
T309 /workspace/coverage/default/37.rom_ctrl_stress_all.2389949035 May 16 12:53:27 PM PDT 24 May 16 12:55:06 PM PDT 24 15863949399 ps
T310 /workspace/coverage/default/46.rom_ctrl_max_throughput_chk.3332505646 May 16 12:53:36 PM PDT 24 May 16 12:54:11 PM PDT 24 3543232290 ps
T311 /workspace/coverage/default/8.rom_ctrl_max_throughput_chk.3952861187 May 16 12:52:56 PM PDT 24 May 16 12:53:16 PM PDT 24 1010130772 ps
T312 /workspace/coverage/default/2.rom_ctrl_smoke.3819155814 May 16 12:52:51 PM PDT 24 May 16 12:53:12 PM PDT 24 189773096 ps
T313 /workspace/coverage/default/41.rom_ctrl_kmac_err_chk.2317459897 May 16 12:53:43 PM PDT 24 May 16 12:54:21 PM PDT 24 774525437 ps
T314 /workspace/coverage/default/34.rom_ctrl_corrupt_sig_fatal_chk.1238028109 May 16 12:53:31 PM PDT 24 May 16 01:00:00 PM PDT 24 126969552663 ps
T315 /workspace/coverage/default/10.rom_ctrl_corrupt_sig_fatal_chk.300902453 May 16 12:53:09 PM PDT 24 May 16 12:55:15 PM PDT 24 17731779082 ps
T316 /workspace/coverage/default/38.rom_ctrl_stress_all.893987504 May 16 12:53:40 PM PDT 24 May 16 12:54:55 PM PDT 24 4865494680 ps
T317 /workspace/coverage/default/39.rom_ctrl_smoke.1946749075 May 16 12:53:32 PM PDT 24 May 16 12:54:10 PM PDT 24 4839350751 ps
T318 /workspace/coverage/default/9.rom_ctrl_corrupt_sig_fatal_chk.2308907508 May 16 12:53:11 PM PDT 24 May 16 12:56:23 PM PDT 24 15772913599 ps
T319 /workspace/coverage/default/4.rom_ctrl_kmac_err_chk.586759566 May 16 12:52:54 PM PDT 24 May 16 12:53:20 PM PDT 24 12805309128 ps
T320 /workspace/coverage/default/35.rom_ctrl_stress_all_with_rand_reset.1931426778 May 16 12:53:30 PM PDT 24 May 16 01:12:11 PM PDT 24 410003988522 ps
T321 /workspace/coverage/default/5.rom_ctrl_corrupt_sig_fatal_chk.980142948 May 16 12:52:54 PM PDT 24 May 16 12:57:20 PM PDT 24 41423518873 ps
T322 /workspace/coverage/default/1.rom_ctrl_max_throughput_chk.1392946223 May 16 12:52:53 PM PDT 24 May 16 12:53:18 PM PDT 24 3267988939 ps
T323 /workspace/coverage/default/11.rom_ctrl_stress_all.1006010865 May 16 12:53:09 PM PDT 24 May 16 12:54:04 PM PDT 24 17929234785 ps
T324 /workspace/coverage/default/3.rom_ctrl_kmac_err_chk.1049911094 May 16 12:52:52 PM PDT 24 May 16 12:53:36 PM PDT 24 17432244441 ps
T325 /workspace/coverage/default/40.rom_ctrl_stress_all.1616005430 May 16 12:53:36 PM PDT 24 May 16 12:55:20 PM PDT 24 33262717044 ps
T326 /workspace/coverage/default/3.rom_ctrl_smoke.2367104868 May 16 12:52:55 PM PDT 24 May 16 12:53:15 PM PDT 24 179494487 ps
T327 /workspace/coverage/default/17.rom_ctrl_alert_test.1140633770 May 16 12:53:12 PM PDT 24 May 16 12:53:32 PM PDT 24 1236589173 ps
T328 /workspace/coverage/default/11.rom_ctrl_stress_all_with_rand_reset.1757290308 May 16 12:53:06 PM PDT 24 May 16 01:29:40 PM PDT 24 141789743128 ps
T329 /workspace/coverage/default/16.rom_ctrl_smoke.1182421419 May 16 12:53:11 PM PDT 24 May 16 12:53:43 PM PDT 24 9327582009 ps
T330 /workspace/coverage/default/45.rom_ctrl_kmac_err_chk.4164414367 May 16 12:53:37 PM PDT 24 May 16 12:54:10 PM PDT 24 825484833 ps
T331 /workspace/coverage/default/42.rom_ctrl_smoke.3557021554 May 16 12:53:39 PM PDT 24 May 16 12:54:20 PM PDT 24 3103095711 ps
T332 /workspace/coverage/default/14.rom_ctrl_alert_test.1976872515 May 16 12:53:12 PM PDT 24 May 16 12:53:25 PM PDT 24 89089426 ps
T333 /workspace/coverage/default/5.rom_ctrl_stress_all.1482486641 May 16 12:52:52 PM PDT 24 May 16 12:53:24 PM PDT 24 2239999799 ps
T334 /workspace/coverage/default/6.rom_ctrl_alert_test.4238462507 May 16 12:52:56 PM PDT 24 May 16 12:53:09 PM PDT 24 103579881 ps
T335 /workspace/coverage/default/41.rom_ctrl_corrupt_sig_fatal_chk.2723162501 May 16 12:53:45 PM PDT 24 May 16 12:56:31 PM PDT 24 5608418112 ps
T336 /workspace/coverage/default/23.rom_ctrl_corrupt_sig_fatal_chk.3120051518 May 16 12:53:28 PM PDT 24 May 16 12:55:36 PM PDT 24 7527626612 ps
T337 /workspace/coverage/default/24.rom_ctrl_corrupt_sig_fatal_chk.374924633 May 16 12:53:25 PM PDT 24 May 16 12:57:16 PM PDT 24 45986286532 ps
T338 /workspace/coverage/default/45.rom_ctrl_smoke.264439569 May 16 12:53:47 PM PDT 24 May 16 12:54:36 PM PDT 24 9467584939 ps
T339 /workspace/coverage/default/0.rom_ctrl_corrupt_sig_fatal_chk.2562921923 May 16 12:52:54 PM PDT 24 May 16 12:55:18 PM PDT 24 7679061473 ps
T340 /workspace/coverage/default/10.rom_ctrl_alert_test.3743989729 May 16 12:53:09 PM PDT 24 May 16 12:53:32 PM PDT 24 6738600908 ps
T37 /workspace/coverage/default/4.rom_ctrl_sec_cm.3099447395 May 16 12:52:55 PM PDT 24 May 16 12:54:51 PM PDT 24 1476513555 ps
T341 /workspace/coverage/default/35.rom_ctrl_max_throughput_chk.4280290163 May 16 12:53:34 PM PDT 24 May 16 12:54:06 PM PDT 24 6514964060 ps
T342 /workspace/coverage/default/15.rom_ctrl_alert_test.3352348276 May 16 12:53:09 PM PDT 24 May 16 12:53:31 PM PDT 24 1750089938 ps
T343 /workspace/coverage/default/28.rom_ctrl_kmac_err_chk.6194263 May 16 12:53:31 PM PDT 24 May 16 12:54:05 PM PDT 24 8825428630 ps
T344 /workspace/coverage/default/40.rom_ctrl_kmac_err_chk.1267044502 May 16 12:53:39 PM PDT 24 May 16 12:54:29 PM PDT 24 3151355404 ps
T345 /workspace/coverage/default/39.rom_ctrl_max_throughput_chk.2969850283 May 16 12:53:38 PM PDT 24 May 16 12:54:06 PM PDT 24 137117075 ps
T346 /workspace/coverage/default/11.rom_ctrl_kmac_err_chk.255037027 May 16 12:53:06 PM PDT 24 May 16 12:53:29 PM PDT 24 1330451512 ps
T347 /workspace/coverage/default/27.rom_ctrl_alert_test.4178409113 May 16 12:53:27 PM PDT 24 May 16 12:53:55 PM PDT 24 7300529559 ps
T348 /workspace/coverage/default/44.rom_ctrl_alert_test.3130178802 May 16 12:53:42 PM PDT 24 May 16 12:54:11 PM PDT 24 85562968 ps
T349 /workspace/coverage/default/48.rom_ctrl_smoke.2100370077 May 16 12:53:39 PM PDT 24 May 16 12:54:23 PM PDT 24 20949803079 ps
T350 /workspace/coverage/default/3.rom_ctrl_stress_all_with_rand_reset.358521002 May 16 12:52:52 PM PDT 24 May 16 01:22:20 PM PDT 24 610183389723 ps
T106 /workspace/coverage/default/46.rom_ctrl_stress_all_with_rand_reset.1126181472 May 16 12:53:38 PM PDT 24 May 16 01:05:23 PM PDT 24 68968869288 ps
T351 /workspace/coverage/default/14.rom_ctrl_corrupt_sig_fatal_chk.3554370785 May 16 12:53:05 PM PDT 24 May 16 12:55:52 PM PDT 24 11101002640 ps
T352 /workspace/coverage/default/22.rom_ctrl_stress_all_with_rand_reset.2645595614 May 16 12:53:08 PM PDT 24 May 16 01:11:18 PM PDT 24 347632528463 ps
T353 /workspace/coverage/default/23.rom_ctrl_kmac_err_chk.1597675475 May 16 12:53:28 PM PDT 24 May 16 12:54:06 PM PDT 24 2548132257 ps
T354 /workspace/coverage/default/32.rom_ctrl_kmac_err_chk.2502222043 May 16 12:53:32 PM PDT 24 May 16 12:54:24 PM PDT 24 4200675450 ps
T355 /workspace/coverage/default/39.rom_ctrl_corrupt_sig_fatal_chk.2312400621 May 16 12:53:42 PM PDT 24 May 16 12:55:26 PM PDT 24 3312102056 ps
T356 /workspace/coverage/default/44.rom_ctrl_max_throughput_chk.923968098 May 16 12:53:48 PM PDT 24 May 16 12:54:22 PM PDT 24 8822015147 ps
T357 /workspace/coverage/default/14.rom_ctrl_smoke.452679976 May 16 12:53:13 PM PDT 24 May 16 12:53:52 PM PDT 24 11016505816 ps
T358 /workspace/coverage/default/17.rom_ctrl_smoke.1995711496 May 16 12:53:10 PM PDT 24 May 16 12:53:29 PM PDT 24 380603643 ps
T359 /workspace/coverage/default/13.rom_ctrl_stress_all.3209608625 May 16 12:53:08 PM PDT 24 May 16 12:53:35 PM PDT 24 2198168233 ps
T360 /workspace/coverage/default/31.rom_ctrl_corrupt_sig_fatal_chk.2035394570 May 16 12:53:29 PM PDT 24 May 16 12:55:45 PM PDT 24 8408560620 ps
T361 /workspace/coverage/default/35.rom_ctrl_alert_test.819091499 May 16 12:53:30 PM PDT 24 May 16 12:53:55 PM PDT 24 868360366 ps
T362 /workspace/coverage/default/11.rom_ctrl_max_throughput_chk.2129557801 May 16 12:53:14 PM PDT 24 May 16 12:53:32 PM PDT 24 1813406740 ps
T363 /workspace/coverage/default/1.rom_ctrl_kmac_err_chk.797521631 May 16 12:52:52 PM PDT 24 May 16 12:53:19 PM PDT 24 4295297274 ps
T364 /workspace/coverage/default/18.rom_ctrl_corrupt_sig_fatal_chk.2043564214 May 16 12:53:16 PM PDT 24 May 16 12:56:20 PM PDT 24 21422923618 ps
T365 /workspace/coverage/default/21.rom_ctrl_max_throughput_chk.860462316 May 16 12:53:09 PM PDT 24 May 16 12:53:28 PM PDT 24 788148220 ps
T366 /workspace/coverage/default/13.rom_ctrl_alert_test.3097304828 May 16 12:53:13 PM PDT 24 May 16 12:53:35 PM PDT 24 5883392958 ps
T367 /workspace/coverage/default/25.rom_ctrl_smoke.2001035751 May 16 12:53:28 PM PDT 24 May 16 12:53:53 PM PDT 24 1604889290 ps
T368 /workspace/coverage/default/17.rom_ctrl_stress_all_with_rand_reset.1872412522 May 16 12:53:10 PM PDT 24 May 16 01:01:53 PM PDT 24 13432627361 ps
T369 /workspace/coverage/default/25.rom_ctrl_max_throughput_chk.1239412783 May 16 12:53:27 PM PDT 24 May 16 12:53:46 PM PDT 24 379421483 ps
T66 /workspace/coverage/default/41.rom_ctrl_stress_all_with_rand_reset.2355414985 May 16 12:53:42 PM PDT 24 May 16 01:12:51 PM PDT 24 28445485238 ps
T67 /workspace/coverage/default/7.rom_ctrl_max_throughput_chk.3815178821 May 16 12:52:59 PM PDT 24 May 16 12:53:22 PM PDT 24 4241591680 ps
T68 /workspace/coverage/default/8.rom_ctrl_alert_test.2388707938 May 16 12:53:06 PM PDT 24 May 16 12:53:23 PM PDT 24 2215321955 ps
T69 /workspace/coverage/default/7.rom_ctrl_alert_test.280496614 May 16 12:53:01 PM PDT 24 May 16 12:53:22 PM PDT 24 1783003246 ps
T70 /workspace/coverage/default/0.rom_ctrl_max_throughput_chk.1685830426 May 16 12:52:50 PM PDT 24 May 16 12:53:14 PM PDT 24 1206691523 ps
T71 /workspace/coverage/default/32.rom_ctrl_stress_all.4185693454 May 16 12:53:31 PM PDT 24 May 16 12:54:09 PM PDT 24 19402597774 ps
T72 /workspace/coverage/default/14.rom_ctrl_max_throughput_chk.2220870964 May 16 12:53:10 PM PDT 24 May 16 12:53:26 PM PDT 24 1235545219 ps
T73 /workspace/coverage/default/15.rom_ctrl_corrupt_sig_fatal_chk.742421878 May 16 12:53:07 PM PDT 24 May 16 12:56:54 PM PDT 24 62278375472 ps
T74 /workspace/coverage/default/33.rom_ctrl_stress_all.635481443 May 16 12:53:28 PM PDT 24 May 16 12:54:03 PM PDT 24 1935920545 ps
T61 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_hw_reset.3665818345 May 16 12:50:06 PM PDT 24 May 16 12:50:32 PM PDT 24 4920751450 ps
T62 /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_mem_rw_with_rand_reset.881147448 May 16 12:50:36 PM PDT 24 May 16 12:51:02 PM PDT 24 3620558374 ps
T58 /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_intg_err.3904714289 May 16 12:50:48 PM PDT 24 May 16 12:51:48 PM PDT 24 10696442801 ps
T75 /workspace/coverage/cover_reg_top/16.rom_ctrl_passthru_mem_tl_intg_err.1941259583 May 16 12:50:59 PM PDT 24 May 16 12:52:39 PM PDT 24 23634899764 ps
T370 /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_walk.3216931108 May 16 12:50:24 PM PDT 24 May 16 12:50:49 PM PDT 24 619024560 ps
T79 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_aliasing.2393936275 May 16 12:50:17 PM PDT 24 May 16 12:50:48 PM PDT 24 4503178043 ps
T80 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_rw.721510709 May 16 12:50:06 PM PDT 24 May 16 12:50:28 PM PDT 24 3933235357 ps
T81 /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_rw.271133372 May 16 12:51:06 PM PDT 24 May 16 12:51:24 PM PDT 24 8533692267 ps
T103 /workspace/coverage/cover_reg_top/6.rom_ctrl_passthru_mem_tl_intg_err.1366076339 May 16 12:50:24 PM PDT 24 May 16 12:51:30 PM PDT 24 98849650809 ps
T82 /workspace/coverage/cover_reg_top/19.rom_ctrl_passthru_mem_tl_intg_err.3967818757 May 16 12:51:10 PM PDT 24 May 16 12:52:11 PM PDT 24 11184075478 ps
T371 /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_errors.1410055552 May 16 12:50:23 PM PDT 24 May 16 12:50:49 PM PDT 24 430304879 ps
T372 /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_errors.3385497718 May 16 12:51:02 PM PDT 24 May 16 12:51:29 PM PDT 24 3758256054 ps
T104 /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_rw.1141897576 May 16 12:50:48 PM PDT 24 May 16 12:51:12 PM PDT 24 2443191304 ps
T105 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_bit_bash.4156366074 May 16 12:50:03 PM PDT 24 May 16 12:50:19 PM PDT 24 85540407 ps
T83 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_hw_reset.1061385616 May 16 12:50:14 PM PDT 24 May 16 12:50:35 PM PDT 24 594269785 ps
T373 /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_mem_rw_with_rand_reset.2462152749 May 16 12:50:47 PM PDT 24 May 16 12:51:13 PM PDT 24 6227591789 ps
T374 /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_rw.3817354267 May 16 12:50:25 PM PDT 24 May 16 12:50:57 PM PDT 24 6744262122 ps
T375 /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_errors.3630918968 May 16 12:50:46 PM PDT 24 May 16 12:51:15 PM PDT 24 1760300212 ps
T84 /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_rw.684460462 May 16 12:50:34 PM PDT 24 May 16 12:51:00 PM PDT 24 979720156 ps
T85 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_rw.1743442083 May 16 12:49:56 PM PDT 24 May 16 12:50:25 PM PDT 24 34172793014 ps
T376 /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_errors.3399336383 May 16 12:50:07 PM PDT 24 May 16 12:50:35 PM PDT 24 7004069665 ps
T377 /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_walk.4094907357 May 16 12:49:54 PM PDT 24 May 16 12:50:21 PM PDT 24 3699683906 ps
T59 /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_intg_err.879437953 May 16 12:50:27 PM PDT 24 May 16 12:51:32 PM PDT 24 1925945351 ps
T378 /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_mem_rw_with_rand_reset.67721032 May 16 12:51:00 PM PDT 24 May 16 12:51:18 PM PDT 24 2647044438 ps
T379 /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_errors.3958336022 May 16 12:50:14 PM PDT 24 May 16 12:50:33 PM PDT 24 348338633 ps
T86 /workspace/coverage/cover_reg_top/2.rom_ctrl_passthru_mem_tl_intg_err.517493047 May 16 12:50:07 PM PDT 24 May 16 12:50:38 PM PDT 24 2218092089 ps
T95 /workspace/coverage/cover_reg_top/12.rom_ctrl_passthru_mem_tl_intg_err.742630725 May 16 12:50:47 PM PDT 24 May 16 12:52:09 PM PDT 24 8587988238 ps
T380 /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_errors.1515411725 May 16 12:49:59 PM PDT 24 May 16 12:50:31 PM PDT 24 8859988779 ps
T381 /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_errors.934293124 May 16 12:50:36 PM PDT 24 May 16 12:51:09 PM PDT 24 6371202384 ps
T96 /workspace/coverage/cover_reg_top/7.rom_ctrl_same_csr_outstanding.2378234090 May 16 12:50:32 PM PDT 24 May 16 12:51:00 PM PDT 24 12678683918 ps
T97 /workspace/coverage/cover_reg_top/13.rom_ctrl_same_csr_outstanding.324414753 May 16 12:50:59 PM PDT 24 May 16 12:51:24 PM PDT 24 8706000177 ps
T382 /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_walk.1682697941 May 16 12:50:20 PM PDT 24 May 16 12:50:46 PM PDT 24 1955921964 ps
T87 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_aliasing.1846360134 May 16 12:50:24 PM PDT 24 May 16 12:50:44 PM PDT 24 168531616 ps
T383 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_bit_bash.914617320 May 16 12:50:16 PM PDT 24 May 16 12:50:38 PM PDT 24 2237376166 ps
T384 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_bit_bash.3901417022 May 16 12:50:17 PM PDT 24 May 16 12:50:39 PM PDT 24 2188897422 ps
T385 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_mem_rw_with_rand_reset.4112268743 May 16 12:50:23 PM PDT 24 May 16 12:50:57 PM PDT 24 4385225829 ps
T60 /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_intg_err.2324827466 May 16 12:50:16 PM PDT 24 May 16 12:51:09 PM PDT 24 601970224 ps
T88 /workspace/coverage/cover_reg_top/0.rom_ctrl_passthru_mem_tl_intg_err.3103499622 May 16 12:49:55 PM PDT 24 May 16 12:51:38 PM PDT 24 46074397915 ps
T386 /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_rw.618415513 May 16 12:50:35 PM PDT 24 May 16 12:51:06 PM PDT 24 9039318632 ps
T89 /workspace/coverage/cover_reg_top/11.rom_ctrl_passthru_mem_tl_intg_err.1538123805 May 16 12:50:45 PM PDT 24 May 16 12:51:26 PM PDT 24 543558383 ps
T107 /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_intg_err.2823230527 May 16 12:50:25 PM PDT 24 May 16 12:51:53 PM PDT 24 1012047208 ps
T387 /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_errors.244575971 May 16 12:50:47 PM PDT 24 May 16 12:51:18 PM PDT 24 1689032064 ps
T388 /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_mem_rw_with_rand_reset.4146190346 May 16 12:50:47 PM PDT 24 May 16 12:51:17 PM PDT 24 4404815765 ps
T389 /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_errors.1335567842 May 16 12:50:58 PM PDT 24 May 16 12:51:22 PM PDT 24 2562265000 ps
T115 /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_intg_err.2513196376 May 16 12:51:02 PM PDT 24 May 16 12:51:58 PM PDT 24 5082955883 ps
T94 /workspace/coverage/cover_reg_top/3.rom_ctrl_passthru_mem_tl_intg_err.2039309707 May 16 12:50:13 PM PDT 24 May 16 12:51:44 PM PDT 24 8632868106 ps
T390 /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_mem_rw_with_rand_reset.3186014441 May 16 12:50:28 PM PDT 24 May 16 12:50:52 PM PDT 24 1836063882 ps
T391 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_bit_bash.945504725 May 16 12:50:22 PM PDT 24 May 16 12:50:50 PM PDT 24 1314539282 ps
T98 /workspace/coverage/cover_reg_top/15.rom_ctrl_same_csr_outstanding.1296941028 May 16 12:50:59 PM PDT 24 May 16 12:51:18 PM PDT 24 858321485 ps
T113 /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_intg_err.581267076 May 16 12:50:59 PM PDT 24 May 16 12:51:52 PM PDT 24 2810698974 ps
T99 /workspace/coverage/cover_reg_top/8.rom_ctrl_same_csr_outstanding.1669958623 May 16 12:50:34 PM PDT 24 May 16 12:51:00 PM PDT 24 1767616756 ps
T90 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_aliasing.3714919821 May 16 12:50:06 PM PDT 24 May 16 12:50:31 PM PDT 24 3034619615 ps
T392 /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_errors.4253568842 May 16 12:50:48 PM PDT 24 May 16 12:51:12 PM PDT 24 793550922 ps
T100 /workspace/coverage/cover_reg_top/4.rom_ctrl_same_csr_outstanding.146298110 May 16 12:50:22 PM PDT 24 May 16 12:50:48 PM PDT 24 3404520036 ps
T393 /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_rw.963279272 May 16 12:51:00 PM PDT 24 May 16 12:51:25 PM PDT 24 2133939499 ps
T91 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_aliasing.1046492947 May 16 12:50:08 PM PDT 24 May 16 12:50:25 PM PDT 24 348257904 ps
T108 /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_intg_err.530134382 May 16 12:50:58 PM PDT 24 May 16 12:52:21 PM PDT 24 1609372441 ps
T394 /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_errors.814600851 May 16 12:50:14 PM PDT 24 May 16 12:50:47 PM PDT 24 7183081146 ps
T395 /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_partial_access.3915439877 May 16 12:50:27 PM PDT 24 May 16 12:51:00 PM PDT 24 8058914055 ps
T111 /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_intg_err.1098953915 May 16 12:50:11 PM PDT 24 May 16 12:51:09 PM PDT 24 1867367847 ps
T101 /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_rw.324297191 May 16 12:50:23 PM PDT 24 May 16 12:50:48 PM PDT 24 2855649373 ps
T396 /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_rw.3630173620 May 16 12:51:18 PM PDT 24 May 16 12:51:29 PM PDT 24 168143366 ps
T92 /workspace/coverage/cover_reg_top/7.rom_ctrl_passthru_mem_tl_intg_err.2182195325 May 16 12:50:35 PM PDT 24 May 16 12:51:34 PM PDT 24 3837430372 ps
T397 /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_errors.3578697793 May 16 12:51:04 PM PDT 24 May 16 12:51:24 PM PDT 24 23493909143 ps
T398 /workspace/coverage/cover_reg_top/10.rom_ctrl_same_csr_outstanding.4025876634 May 16 12:50:46 PM PDT 24 May 16 12:51:03 PM PDT 24 168367666 ps
T399 /workspace/coverage/cover_reg_top/9.rom_ctrl_same_csr_outstanding.384571066 May 16 12:50:34 PM PDT 24 May 16 12:50:54 PM PDT 24 88959241 ps
T400 /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_mem_rw_with_rand_reset.67270943 May 16 12:51:01 PM PDT 24 May 16 12:51:21 PM PDT 24 1144769355 ps
T401 /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_mem_rw_with_rand_reset.2030904319 May 16 12:51:14 PM PDT 24 May 16 12:51:27 PM PDT 24 1539490338 ps
T402 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_hw_reset.1375854435 May 16 12:50:17 PM PDT 24 May 16 12:50:39 PM PDT 24 250723159 ps
T403 /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_rw.2374049045 May 16 12:50:58 PM PDT 24 May 16 12:51:13 PM PDT 24 830864776 ps
T404 /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_rw.2063927688 May 16 12:51:02 PM PDT 24 May 16 12:51:21 PM PDT 24 2409717704 ps
T405 /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_walk.353249350 May 16 12:50:06 PM PDT 24 May 16 12:50:28 PM PDT 24 3404787651 ps
T406 /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_partial_access.1522716909 May 16 12:49:54 PM PDT 24 May 16 12:50:18 PM PDT 24 1285480258 ps
T407 /workspace/coverage/cover_reg_top/19.rom_ctrl_same_csr_outstanding.885439449 May 16 12:51:10 PM PDT 24 May 16 12:51:25 PM PDT 24 2400643926 ps
T408 /workspace/coverage/cover_reg_top/17.rom_ctrl_same_csr_outstanding.2464394720 May 16 12:50:59 PM PDT 24 May 16 12:51:22 PM PDT 24 8879776114 ps
T112 /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_intg_err.289690601 May 16 12:50:17 PM PDT 24 May 16 12:51:49 PM PDT 24 1945704285 ps
T409 /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_errors.2732336940 May 16 12:50:29 PM PDT 24 May 16 12:50:52 PM PDT 24 91218402 ps
T119 /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_intg_err.3691763540 May 16 12:50:36 PM PDT 24 May 16 12:51:40 PM PDT 24 4110322607 ps
T410 /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_mem_rw_with_rand_reset.3761575701 May 16 12:51:04 PM PDT 24 May 16 12:51:16 PM PDT 24 99344773 ps
T411 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_mem_rw_with_rand_reset.2379381162 May 16 12:50:14 PM PDT 24 May 16 12:50:44 PM PDT 24 2151675543 ps
T412 /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_rw.3426360565 May 16 12:50:44 PM PDT 24 May 16 12:51:11 PM PDT 24 1448046663 ps
T413 /workspace/coverage/cover_reg_top/8.rom_ctrl_passthru_mem_tl_intg_err.708546159 May 16 12:50:34 PM PDT 24 May 16 12:52:29 PM PDT 24 50266347986 ps
T414 /workspace/coverage/cover_reg_top/13.rom_ctrl_passthru_mem_tl_intg_err.2591740625 May 16 12:50:47 PM PDT 24 May 16 12:52:36 PM PDT 24 47479462292 ps
T415 /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_mem_rw_with_rand_reset.3422993389 May 16 12:50:32 PM PDT 24 May 16 12:50:52 PM PDT 24 97592414 ps
T416 /workspace/coverage/cover_reg_top/2.rom_ctrl_same_csr_outstanding.4031111443 May 16 12:50:06 PM PDT 24 May 16 12:50:31 PM PDT 24 1372536616 ps
T417 /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_errors.4042057965 May 16 12:50:57 PM PDT 24 May 16 12:51:14 PM PDT 24 347361708 ps
T418 /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_mem_rw_with_rand_reset.3106724392 May 16 12:50:34 PM PDT 24 May 16 12:51:04 PM PDT 24 10535396803 ps
T419 /workspace/coverage/cover_reg_top/5.rom_ctrl_same_csr_outstanding.3914453093 May 16 12:50:26 PM PDT 24 May 16 12:50:47 PM PDT 24 333988966 ps
T420 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_mem_rw_with_rand_reset.1239066651 May 16 12:50:08 PM PDT 24 May 16 12:50:37 PM PDT 24 2613408056 ps
T421 /workspace/coverage/cover_reg_top/3.rom_ctrl_same_csr_outstanding.1102939334 May 16 12:50:14 PM PDT 24 May 16 12:50:33 PM PDT 24 98083883 ps
T422 /workspace/coverage/cover_reg_top/5.rom_ctrl_passthru_mem_tl_intg_err.3191721071 May 16 12:50:27 PM PDT 24 May 16 12:52:12 PM PDT 24 39276525253 ps
T423 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_bit_bash.3575974859 May 16 12:49:59 PM PDT 24 May 16 12:50:23 PM PDT 24 5316740271 ps
T117 /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_intg_err.2880326499 May 16 12:50:46 PM PDT 24 May 16 12:52:12 PM PDT 24 1173546760 ps
T116 /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_intg_err.2018806089 May 16 12:51:06 PM PDT 24 May 16 12:52:00 PM PDT 24 4178181553 ps
T120 /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_intg_err.687230585 May 16 12:50:35 PM PDT 24 May 16 12:51:30 PM PDT 24 4170932024 ps
T118 /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_intg_err.1720597951 May 16 12:51:10 PM PDT 24 May 16 12:51:56 PM PDT 24 688974038 ps
T424 /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_errors.2979852297 May 16 12:50:48 PM PDT 24 May 16 12:51:17 PM PDT 24 1332618768 ps
T425 /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_mem_rw_with_rand_reset.355260146 May 16 12:51:02 PM PDT 24 May 16 12:51:25 PM PDT 24 7095569291 ps
T426 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_aliasing.2581615977 May 16 12:50:05 PM PDT 24 May 16 12:50:21 PM PDT 24 333622374 ps
T427 /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_rw.1249602072 May 16 12:50:46 PM PDT 24 May 16 12:51:03 PM PDT 24 639549451 ps
T428 /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_partial_access.4146276445 May 16 12:50:18 PM PDT 24 May 16 12:50:43 PM PDT 24 1026154984 ps
T429 /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_intg_err.2384378685 May 16 12:50:07 PM PDT 24 May 16 12:51:06 PM PDT 24 9555852879 ps
T430 /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_partial_access.2955122376 May 16 12:50:13 PM PDT 24 May 16 12:50:30 PM PDT 24 89956750 ps
T431 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_mem_rw_with_rand_reset.3432122535 May 16 12:50:04 PM PDT 24 May 16 12:50:25 PM PDT 24 691772979 ps
T432 /workspace/coverage/cover_reg_top/0.rom_ctrl_same_csr_outstanding.2446145554 May 16 12:50:05 PM PDT 24 May 16 12:50:26 PM PDT 24 1584156517 ps
T433 /workspace/coverage/cover_reg_top/12.rom_ctrl_same_csr_outstanding.317375783 May 16 12:50:47 PM PDT 24 May 16 12:51:16 PM PDT 24 1623675951 ps
T434 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_hw_reset.1485262604 May 16 12:50:00 PM PDT 24 May 16 12:50:24 PM PDT 24 3622587712 ps
T435 /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_errors.1246607043 May 16 12:50:05 PM PDT 24 May 16 12:50:24 PM PDT 24 89159636 ps
T436 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_rw.58758705 May 16 12:50:05 PM PDT 24 May 16 12:50:34 PM PDT 24 8686440111 ps
T437 /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_mem_rw_with_rand_reset.4204161630 May 16 12:51:00 PM PDT 24 May 16 12:51:20 PM PDT 24 1156874176 ps
T438 /workspace/coverage/cover_reg_top/11.rom_ctrl_same_csr_outstanding.2186614385 May 16 12:50:46 PM PDT 24 May 16 12:51:04 PM PDT 24 85643635 ps
T109 /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_intg_err.632505473 May 16 12:49:59 PM PDT 24 May 16 12:51:30 PM PDT 24 1848140872 ps
T439 /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_errors.3721090876 May 16 12:51:02 PM PDT 24 May 16 12:51:21 PM PDT 24 1124002196 ps
T440 /workspace/coverage/cover_reg_top/18.rom_ctrl_same_csr_outstanding.810620713 May 16 12:51:06 PM PDT 24 May 16 12:51:25 PM PDT 24 1181241330 ps
T441 /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_intg_err.4222737650 May 16 12:50:46 PM PDT 24 May 16 12:52:13 PM PDT 24 5114779446 ps
T93 /workspace/coverage/cover_reg_top/14.rom_ctrl_passthru_mem_tl_intg_err.3798124473 May 16 12:51:00 PM PDT 24 May 16 12:51:45 PM PDT 24 5307084758 ps
T442 /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_walk.2523450822 May 16 12:50:08 PM PDT 24 May 16 12:50:25 PM PDT 24 88035347 ps
T443 /workspace/coverage/cover_reg_top/4.rom_ctrl_passthru_mem_tl_intg_err.1270362988 May 16 12:50:14 PM PDT 24 May 16 12:50:47 PM PDT 24 364008410 ps
T444 /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_errors.2755281502 May 16 12:51:12 PM PDT 24 May 16 12:51:35 PM PDT 24 16263738081 ps
T445 /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_partial_access.3135464046 May 16 12:50:03 PM PDT 24 May 16 12:50:19 PM PDT 24 130560192 ps
T446 /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_mem_rw_with_rand_reset.868440261 May 16 12:51:04 PM PDT 24 May 16 12:51:24 PM PDT 24 5324753067 ps
T447 /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_mem_rw_with_rand_reset.3623826127 May 16 12:50:34 PM PDT 24 May 16 12:51:01 PM PDT 24 11209506927 ps
T448 /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_rw.2295149546 May 16 12:50:49 PM PDT 24 May 16 12:51:12 PM PDT 24 6630905915 ps
T449 /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_mem_rw_with_rand_reset.2436019313 May 16 12:50:47 PM PDT 24 May 16 12:51:13 PM PDT 24 1262144056 ps
T450 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_hw_reset.2868069845 May 16 12:50:28 PM PDT 24 May 16 12:50:54 PM PDT 24 296290241 ps
T451 /workspace/coverage/cover_reg_top/14.rom_ctrl_same_csr_outstanding.1439939356 May 16 12:50:58 PM PDT 24 May 16 12:51:12 PM PDT 24 347251984 ps
T452 /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_rw.3039419045 May 16 12:51:00 PM PDT 24 May 16 12:51:24 PM PDT 24 4560509677 ps
T453 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_rw.1198624391 May 16 12:50:14 PM PDT 24 May 16 12:50:43 PM PDT 24 8025289583 ps
T454 /workspace/coverage/cover_reg_top/1.rom_ctrl_same_csr_outstanding.575904445 May 16 12:50:04 PM PDT 24 May 16 12:50:33 PM PDT 24 2107255014 ps
T455 /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_intg_err.1252493151 May 16 12:50:36 PM PDT 24 May 16 12:51:31 PM PDT 24 971700891 ps
T456 /workspace/coverage/cover_reg_top/18.rom_ctrl_passthru_mem_tl_intg_err.2418395439 May 16 12:51:03 PM PDT 24 May 16 12:52:46 PM PDT 24 11854645548 ps
T457 /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_errors.1128553677 May 16 12:50:33 PM PDT 24 May 16 12:51:03 PM PDT 24 1362864909 ps
T458 /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_rw.245790914 May 16 12:50:34 PM PDT 24 May 16 12:50:54 PM PDT 24 320786716 ps
T459 /workspace/coverage/cover_reg_top/9.rom_ctrl_passthru_mem_tl_intg_err.3838653717 May 16 12:50:35 PM PDT 24 May 16 12:52:19 PM PDT 24 26056673343 ps
T460 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_mem_rw_with_rand_reset.1461047476 May 16 12:50:08 PM PDT 24 May 16 12:50:25 PM PDT 24 1255662158 ps
T461 /workspace/coverage/cover_reg_top/6.rom_ctrl_same_csr_outstanding.2511298470 May 16 12:50:29 PM PDT 24 May 16 12:51:02 PM PDT 24 1665856753 ps
T110 /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_intg_err.2731852660 May 16 12:51:00 PM PDT 24 May 16 12:52:19 PM PDT 24 1576671740 ps
T462 /workspace/coverage/cover_reg_top/1.rom_ctrl_passthru_mem_tl_intg_err.109585688 May 16 12:50:12 PM PDT 24 May 16 12:50:42 PM PDT 24 749699197 ps
T463 /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_errors.1859447269 May 16 12:50:35 PM PDT 24 May 16 12:51:06 PM PDT 24 3592893591 ps
T114 /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_intg_err.3576378524 May 16 12:50:47 PM PDT 24 May 16 12:52:17 PM PDT 24 9333854867 ps
T464 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_rw.2150306396 May 16 12:50:24 PM PDT 24 May 16 12:50:51 PM PDT 24 8517614325 ps
T465 /workspace/coverage/cover_reg_top/16.rom_ctrl_same_csr_outstanding.902383650 May 16 12:51:02 PM PDT 24 May 16 12:51:23 PM PDT 24 1256451221 ps
T466 /workspace/coverage/cover_reg_top/15.rom_ctrl_passthru_mem_tl_intg_err.766823741 May 16 12:51:02 PM PDT 24 May 16 12:52:21 PM PDT 24 14591825892 ps
T467 /workspace/coverage/cover_reg_top/17.rom_ctrl_passthru_mem_tl_intg_err.1544701149 May 16 12:51:02 PM PDT 24 May 16 12:51:53 PM PDT 24 3794205491 ps
T468 /workspace/coverage/cover_reg_top/10.rom_ctrl_passthru_mem_tl_intg_err.3403939862 May 16 12:50:46 PM PDT 24 May 16 12:51:27 PM PDT 24 567929562 ps

Test location /workspace/coverage/default/49.rom_ctrl_corrupt_sig_fatal_chk.1880182474
Short name T4
Test name
Test status
Simulation time 22110323372 ps
CPU time 269.64 seconds
Started May 16 12:53:47 PM PDT 24
Finished May 16 12:58:41 PM PDT 24
Peak memory 230792 kb
Host smart-60a8ebcc-3a19-4201-bb6f-6e366c5b964d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1880182474 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_
corrupt_sig_fatal_chk.1880182474
Directory /workspace/49.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/24.rom_ctrl_stress_all_with_rand_reset.422986155
Short name T11
Test name
Test status
Simulation time 394472895300 ps
CPU time 1958.23 seconds
Started May 16 12:53:29 PM PDT 24
Finished May 16 01:26:22 PM PDT 24
Peak memory 236264 kb
Host smart-b191ea92-9c87-48d0-a523-13a9cde9a0a7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=422986155 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_stress_all_with_rand_reset.422986155
Directory /workspace/24.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.rom_ctrl_corrupt_sig_fatal_chk.1575875923
Short name T275
Test name
Test status
Simulation time 30986331784 ps
CPU time 290.43 seconds
Started May 16 12:53:39 PM PDT 24
Finished May 16 12:58:52 PM PDT 24
Peak memory 212556 kb
Host smart-96ca3e05-2996-41cd-8b3e-153d788feb75
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1575875923 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_
corrupt_sig_fatal_chk.1575875923
Directory /workspace/40.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_intg_err.2823230527
Short name T107
Test name
Test status
Simulation time 1012047208 ps
CPU time 71.2 seconds
Started May 16 12:50:25 PM PDT 24
Finished May 16 12:51:53 PM PDT 24
Peak memory 212236 kb
Host smart-44a42934-dfab-44f1-8f55-be5d32be6379
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2823230527 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_tl_in
tg_err.2823230527
Directory /workspace/6.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/29.rom_ctrl_smoke.1784360129
Short name T2
Test name
Test status
Simulation time 3494220655 ps
CPU time 17.28 seconds
Started May 16 12:53:24 PM PDT 24
Finished May 16 12:53:44 PM PDT 24
Peak memory 213820 kb
Host smart-aeb80338-e310-4917-b845-9cf44ea34f4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1784360129 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_smoke.1784360129
Directory /workspace/29.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/1.rom_ctrl_sec_cm.3822112786
Short name T32
Test name
Test status
Simulation time 239989619 ps
CPU time 100.7 seconds
Started May 16 12:52:52 PM PDT 24
Finished May 16 12:54:43 PM PDT 24
Peak memory 232812 kb
Host smart-5570b8ff-8f6e-49e4-8814-925385062c38
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3822112786 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_sec_cm.3822112786
Directory /workspace/1.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/16.rom_ctrl_alert_test.3252019311
Short name T3
Test name
Test status
Simulation time 1679518465 ps
CPU time 13.91 seconds
Started May 16 12:53:10 PM PDT 24
Finished May 16 12:53:32 PM PDT 24
Peak memory 211240 kb
Host smart-57e080c0-ed02-431f-b96c-0822ad7cbf8f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3252019311 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_alert_test.3252019311
Directory /workspace/16.rom_ctrl_alert_test/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_passthru_mem_tl_intg_err.1941259583
Short name T75
Test name
Test status
Simulation time 23634899764 ps
CPU time 90.42 seconds
Started May 16 12:50:59 PM PDT 24
Finished May 16 12:52:39 PM PDT 24
Peak memory 211336 kb
Host smart-1c28a885-8f6a-48c7-9235-71be05618e24
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1941259583 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_p
assthru_mem_tl_intg_err.1941259583
Directory /workspace/16.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/default/29.rom_ctrl_stress_all_with_rand_reset.2595649013
Short name T49
Test name
Test status
Simulation time 18642433450 ps
CPU time 4852.47 seconds
Started May 16 12:53:27 PM PDT 24
Finished May 16 02:14:33 PM PDT 24
Peak memory 233688 kb
Host smart-0af4ffc2-920d-491e-8685-6726e47cecb2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2595649013 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_stress_all_with_rand_reset.2595649013
Directory /workspace/29.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.rom_ctrl_stress_all.3585134668
Short name T12
Test name
Test status
Simulation time 6791925003 ps
CPU time 77.93 seconds
Started May 16 12:53:10 PM PDT 24
Finished May 16 12:54:36 PM PDT 24
Peak memory 219452 kb
Host smart-ddf52611-1a0a-446c-82c3-4d3d712d5081
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3585134668 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 9.rom_ctrl_stress_all.3585134668
Directory /workspace/9.rom_ctrl_stress_all/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_intg_err.632505473
Short name T109
Test name
Test status
Simulation time 1848140872 ps
CPU time 79.37 seconds
Started May 16 12:49:59 PM PDT 24
Finished May 16 12:51:30 PM PDT 24
Peak memory 213088 kb
Host smart-7e8f10cb-5bfc-4688-ae4d-e28efe389016
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=632505473 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_tl_int
g_err.632505473
Directory /workspace/0.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/5.rom_ctrl_smoke.2733869728
Short name T122
Test name
Test status
Simulation time 1390002566 ps
CPU time 10.33 seconds
Started May 16 12:53:00 PM PDT 24
Finished May 16 12:53:18 PM PDT 24
Peak memory 219208 kb
Host smart-38d42870-3408-4236-a59d-b0ce4026b0aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2733869728 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_smoke.2733869728
Directory /workspace/5.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/0.rom_ctrl_kmac_err_chk.3438227722
Short name T7
Test name
Test status
Simulation time 7845835990 ps
CPU time 33.09 seconds
Started May 16 12:52:52 PM PDT 24
Finished May 16 12:53:36 PM PDT 24
Peak memory 212524 kb
Host smart-2e0641cf-d5ed-48ef-a899-347ad1ede757
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3438227722 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_kmac_err_chk.3438227722
Directory /workspace/0.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/13.rom_ctrl_kmac_err_chk.2137788790
Short name T22
Test name
Test status
Simulation time 173535401 ps
CPU time 9.26 seconds
Started May 16 12:53:06 PM PDT 24
Finished May 16 12:53:20 PM PDT 24
Peak memory 211832 kb
Host smart-61054b77-36a2-4916-8c5a-eaaceb35eac8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2137788790 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_kmac_err_chk.2137788790
Directory /workspace/13.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/1.rom_ctrl_corrupt_sig_fatal_chk.38254053
Short name T24
Test name
Test status
Simulation time 24638859099 ps
CPU time 279.34 seconds
Started May 16 12:52:51 PM PDT 24
Finished May 16 12:57:42 PM PDT 24
Peak memory 219568 kb
Host smart-ac2e595a-23b4-47fa-b23e-ffee349196c2
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38254053 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_
sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_cor
rupt_sig_fatal_chk.38254053
Directory /workspace/1.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_intg_err.3576378524
Short name T114
Test name
Test status
Simulation time 9333854867 ps
CPU time 77.6 seconds
Started May 16 12:50:47 PM PDT 24
Finished May 16 12:52:17 PM PDT 24
Peak memory 219480 kb
Host smart-b60b2465-016e-495b-b7fb-a00dcb442d28
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3576378524 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_tl_i
ntg_err.3576378524
Directory /workspace/10.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_intg_err.530134382
Short name T108
Test name
Test status
Simulation time 1609372441 ps
CPU time 73.71 seconds
Started May 16 12:50:58 PM PDT 24
Finished May 16 12:52:21 PM PDT 24
Peak memory 211296 kb
Host smart-4f216617-f60b-47fd-95d7-f731d716dc0c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=530134382 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_tl_in
tg_err.530134382
Directory /workspace/14.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_passthru_mem_tl_intg_err.1538123805
Short name T89
Test name
Test status
Simulation time 543558383 ps
CPU time 27.97 seconds
Started May 16 12:50:45 PM PDT 24
Finished May 16 12:51:26 PM PDT 24
Peak memory 211276 kb
Host smart-33c4aaa3-177d-45a5-aa5d-6198aa13e918
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1538123805 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_p
assthru_mem_tl_intg_err.1538123805
Directory /workspace/11.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/default/13.rom_ctrl_max_throughput_chk.2027315356
Short name T1
Test name
Test status
Simulation time 7518465491 ps
CPU time 15.76 seconds
Started May 16 12:53:06 PM PDT 24
Finished May 16 12:53:27 PM PDT 24
Peak memory 211184 kb
Host smart-493fb1ce-6059-4547-95d2-54a810617be8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2027315356 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_max_throughput_chk.2027315356
Directory /workspace/13.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_aliasing.2581615977
Short name T426
Test name
Test status
Simulation time 333622374 ps
CPU time 4.32 seconds
Started May 16 12:50:05 PM PDT 24
Finished May 16 12:50:21 PM PDT 24
Peak memory 211204 kb
Host smart-17c1c6fa-ee03-4125-97be-f733196c7335
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2581615977 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_alia
sing.2581615977
Directory /workspace/0.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_bit_bash.3575974859
Short name T423
Test name
Test status
Simulation time 5316740271 ps
CPU time 12.12 seconds
Started May 16 12:49:59 PM PDT 24
Finished May 16 12:50:23 PM PDT 24
Peak memory 211228 kb
Host smart-c9f06f9c-3039-4d49-8d90-1ee6b8737e8f
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3575974859 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_bit_
bash.3575974859
Directory /workspace/0.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_hw_reset.1485262604
Short name T434
Test name
Test status
Simulation time 3622587712 ps
CPU time 12.66 seconds
Started May 16 12:50:00 PM PDT 24
Finished May 16 12:50:24 PM PDT 24
Peak memory 211220 kb
Host smart-c1ece321-4c57-4b0b-b7c2-de392f8ac591
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1485262604 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_hw_r
eset.1485262604
Directory /workspace/0.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_mem_rw_with_rand_reset.3432122535
Short name T431
Test name
Test status
Simulation time 691772979 ps
CPU time 8.93 seconds
Started May 16 12:50:04 PM PDT 24
Finished May 16 12:50:25 PM PDT 24
Peak memory 219524 kb
Host smart-e31e77fc-9ab8-49a2-a065-9cf67a64603a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3432122535 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 0.rom_ctrl_csr_mem_rw_with_rand_reset.3432122535
Directory /workspace/0.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_rw.1743442083
Short name T85
Test name
Test status
Simulation time 34172793014 ps
CPU time 16.42 seconds
Started May 16 12:49:56 PM PDT 24
Finished May 16 12:50:25 PM PDT 24
Peak memory 211324 kb
Host smart-dc35f20a-74a8-463f-b75d-73630f6a40d5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1743442083 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_rw.1743442083
Directory /workspace/0.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_partial_access.1522716909
Short name T406
Test name
Test status
Simulation time 1285480258 ps
CPU time 11.7 seconds
Started May 16 12:49:54 PM PDT 24
Finished May 16 12:50:18 PM PDT 24
Peak memory 211136 kb
Host smart-84aa9a06-5905-4dd2-be10-f167b1cf50d4
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1522716909 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctr
l_mem_partial_access.1522716909
Directory /workspace/0.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_walk.4094907357
Short name T377
Test name
Test status
Simulation time 3699683906 ps
CPU time 14.91 seconds
Started May 16 12:49:54 PM PDT 24
Finished May 16 12:50:21 PM PDT 24
Peak memory 211236 kb
Host smart-bdb9e8f9-9964-4ec6-84cc-d8b40f1c4431
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4094907357 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_mem_walk
.4094907357
Directory /workspace/0.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_passthru_mem_tl_intg_err.3103499622
Short name T88
Test name
Test status
Simulation time 46074397915 ps
CPU time 91.46 seconds
Started May 16 12:49:55 PM PDT 24
Finished May 16 12:51:38 PM PDT 24
Peak memory 211360 kb
Host smart-182089f7-8229-4344-8b62-c4e202ab9826
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3103499622 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_pa
ssthru_mem_tl_intg_err.3103499622
Directory /workspace/0.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_same_csr_outstanding.2446145554
Short name T432
Test name
Test status
Simulation time 1584156517 ps
CPU time 8.54 seconds
Started May 16 12:50:05 PM PDT 24
Finished May 16 12:50:26 PM PDT 24
Peak memory 211144 kb
Host smart-68088391-9028-48bf-bb37-f26c90bdcc07
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2446145554 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_c
trl_same_csr_outstanding.2446145554
Directory /workspace/0.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_errors.1515411725
Short name T380
Test name
Test status
Simulation time 8859988779 ps
CPU time 19.75 seconds
Started May 16 12:49:59 PM PDT 24
Finished May 16 12:50:31 PM PDT 24
Peak memory 219604 kb
Host smart-b007116c-c94d-41fc-95b2-525c940d0224
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1515411725 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_tl_errors.1515411725
Directory /workspace/0.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_aliasing.1046492947
Short name T91
Test name
Test status
Simulation time 348257904 ps
CPU time 4.33 seconds
Started May 16 12:50:08 PM PDT 24
Finished May 16 12:50:25 PM PDT 24
Peak memory 211136 kb
Host smart-4de66200-7090-4cc0-8a94-5e306b6ee27e
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1046492947 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_alia
sing.1046492947
Directory /workspace/1.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_bit_bash.4156366074
Short name T105
Test name
Test status
Simulation time 85540407 ps
CPU time 4.45 seconds
Started May 16 12:50:03 PM PDT 24
Finished May 16 12:50:19 PM PDT 24
Peak memory 211244 kb
Host smart-63652b22-45a3-4523-be00-d6c4b1c3e717
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4156366074 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_bit_
bash.4156366074
Directory /workspace/1.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_hw_reset.3665818345
Short name T61
Test name
Test status
Simulation time 4920751450 ps
CPU time 12.74 seconds
Started May 16 12:50:06 PM PDT 24
Finished May 16 12:50:32 PM PDT 24
Peak memory 211356 kb
Host smart-6ed0330a-6b18-4d5e-87b0-0fe13b43cce9
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3665818345 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_hw_r
eset.3665818345
Directory /workspace/1.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_mem_rw_with_rand_reset.1461047476
Short name T460
Test name
Test status
Simulation time 1255662158 ps
CPU time 5.19 seconds
Started May 16 12:50:08 PM PDT 24
Finished May 16 12:50:25 PM PDT 24
Peak memory 219452 kb
Host smart-febe491f-01de-497f-bfbe-73e2500766b6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1461047476 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 1.rom_ctrl_csr_mem_rw_with_rand_reset.1461047476
Directory /workspace/1.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_rw.58758705
Short name T436
Test name
Test status
Simulation time 8686440111 ps
CPU time 16.29 seconds
Started May 16 12:50:05 PM PDT 24
Finished May 16 12:50:34 PM PDT 24
Peak memory 211256 kb
Host smart-11b93a71-369b-4153-8640-11fe645fbc56
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58758705 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_rw.58758705
Directory /workspace/1.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_partial_access.3135464046
Short name T445
Test name
Test status
Simulation time 130560192 ps
CPU time 5.06 seconds
Started May 16 12:50:03 PM PDT 24
Finished May 16 12:50:19 PM PDT 24
Peak memory 211044 kb
Host smart-030c52dc-3f68-4378-813b-5aa3a718b363
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3135464046 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctr
l_mem_partial_access.3135464046
Directory /workspace/1.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_walk.353249350
Short name T405
Test name
Test status
Simulation time 3404787651 ps
CPU time 9.02 seconds
Started May 16 12:50:06 PM PDT 24
Finished May 16 12:50:28 PM PDT 24
Peak memory 211304 kb
Host smart-8acc3064-f637-42c4-817f-cce609a3a1d6
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=353249350 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_mem_walk.
353249350
Directory /workspace/1.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_passthru_mem_tl_intg_err.109585688
Short name T462
Test name
Test status
Simulation time 749699197 ps
CPU time 18.48 seconds
Started May 16 12:50:12 PM PDT 24
Finished May 16 12:50:42 PM PDT 24
Peak memory 211292 kb
Host smart-dfe9a46b-1399-4f44-9d5b-a58fea910789
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=109585688 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_pas
sthru_mem_tl_intg_err.109585688
Directory /workspace/1.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_same_csr_outstanding.575904445
Short name T454
Test name
Test status
Simulation time 2107255014 ps
CPU time 17.81 seconds
Started May 16 12:50:04 PM PDT 24
Finished May 16 12:50:33 PM PDT 24
Peak memory 211272 kb
Host smart-1b8421b0-711d-47aa-9537-552faea84b4e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=575904445 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ct
rl_same_csr_outstanding.575904445
Directory /workspace/1.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_errors.1246607043
Short name T435
Test name
Test status
Simulation time 89159636 ps
CPU time 7.87 seconds
Started May 16 12:50:05 PM PDT 24
Finished May 16 12:50:24 PM PDT 24
Peak memory 219532 kb
Host smart-cf282bcc-5054-4a42-97a3-c031e9fde876
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1246607043 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_tl_errors.1246607043
Directory /workspace/1.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_intg_err.2384378685
Short name T429
Test name
Test status
Simulation time 9555852879 ps
CPU time 47.13 seconds
Started May 16 12:50:07 PM PDT 24
Finished May 16 12:51:06 PM PDT 24
Peak memory 212392 kb
Host smart-36d8bd92-a4e4-4265-905c-06f764a680f4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2384378685 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_tl_in
tg_err.2384378685
Directory /workspace/1.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_mem_rw_with_rand_reset.2436019313
Short name T449
Test name
Test status
Simulation time 1262144056 ps
CPU time 12.18 seconds
Started May 16 12:50:47 PM PDT 24
Finished May 16 12:51:13 PM PDT 24
Peak memory 219388 kb
Host smart-5a37827d-9717-4a13-b1dd-3ca7f82d2a16
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2436019313 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 10.rom_ctrl_csr_mem_rw_with_rand_reset.2436019313
Directory /workspace/10.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_rw.1249602072
Short name T427
Test name
Test status
Simulation time 639549451 ps
CPU time 4.18 seconds
Started May 16 12:50:46 PM PDT 24
Finished May 16 12:51:03 PM PDT 24
Peak memory 211108 kb
Host smart-325e4461-7155-4dbf-bea1-78919ad2a1ec
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1249602072 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_csr_rw.1249602072
Directory /workspace/10.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_passthru_mem_tl_intg_err.3403939862
Short name T468
Test name
Test status
Simulation time 567929562 ps
CPU time 27.55 seconds
Started May 16 12:50:46 PM PDT 24
Finished May 16 12:51:27 PM PDT 24
Peak memory 211252 kb
Host smart-08b5b3c2-bba4-47b3-9c4d-d064bb05a8c4
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3403939862 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_p
assthru_mem_tl_intg_err.3403939862
Directory /workspace/10.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_same_csr_outstanding.4025876634
Short name T398
Test name
Test status
Simulation time 168367666 ps
CPU time 4.21 seconds
Started May 16 12:50:46 PM PDT 24
Finished May 16 12:51:03 PM PDT 24
Peak memory 211240 kb
Host smart-d9eefccf-3957-411d-b8ac-f328bd25e212
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4025876634 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_
ctrl_same_csr_outstanding.4025876634
Directory /workspace/10.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_errors.244575971
Short name T387
Test name
Test status
Simulation time 1689032064 ps
CPU time 16.54 seconds
Started May 16 12:50:47 PM PDT 24
Finished May 16 12:51:18 PM PDT 24
Peak memory 219544 kb
Host smart-a15c5a00-0dd5-4024-b191-cccab170428a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=244575971 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_tl_errors.244575971
Directory /workspace/10.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_mem_rw_with_rand_reset.2462152749
Short name T373
Test name
Test status
Simulation time 6227591789 ps
CPU time 12.58 seconds
Started May 16 12:50:47 PM PDT 24
Finished May 16 12:51:13 PM PDT 24
Peak memory 213560 kb
Host smart-f8efc9f4-432a-4abc-8a36-46d8d9b4066a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2462152749 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 11.rom_ctrl_csr_mem_rw_with_rand_reset.2462152749
Directory /workspace/11.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_rw.2295149546
Short name T448
Test name
Test status
Simulation time 6630905915 ps
CPU time 9.77 seconds
Started May 16 12:50:49 PM PDT 24
Finished May 16 12:51:12 PM PDT 24
Peak memory 211328 kb
Host smart-904cb533-e674-448d-9558-cac60335da69
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2295149546 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_csr_rw.2295149546
Directory /workspace/11.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_same_csr_outstanding.2186614385
Short name T438
Test name
Test status
Simulation time 85643635 ps
CPU time 4.36 seconds
Started May 16 12:50:46 PM PDT 24
Finished May 16 12:51:04 PM PDT 24
Peak memory 211132 kb
Host smart-4f4676f5-41a9-4eec-9f83-56552a122189
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2186614385 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_
ctrl_same_csr_outstanding.2186614385
Directory /workspace/11.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_errors.4253568842
Short name T392
Test name
Test status
Simulation time 793550922 ps
CPU time 10.64 seconds
Started May 16 12:50:48 PM PDT 24
Finished May 16 12:51:12 PM PDT 24
Peak memory 219512 kb
Host smart-31ab5a63-1edb-4992-83eb-970e3c5c5bb4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4253568842 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_tl_errors.4253568842
Directory /workspace/11.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_intg_err.2880326499
Short name T117
Test name
Test status
Simulation time 1173546760 ps
CPU time 72.06 seconds
Started May 16 12:50:46 PM PDT 24
Finished May 16 12:52:12 PM PDT 24
Peak memory 212144 kb
Host smart-bc883aff-868f-4bfa-8626-7084930a3413
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2880326499 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_tl_i
ntg_err.2880326499
Directory /workspace/11.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_mem_rw_with_rand_reset.4146190346
Short name T388
Test name
Test status
Simulation time 4404815765 ps
CPU time 16.43 seconds
Started May 16 12:50:47 PM PDT 24
Finished May 16 12:51:17 PM PDT 24
Peak memory 219440 kb
Host smart-8f8eaf25-436e-43a3-b413-260459480089
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4146190346 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 12.rom_ctrl_csr_mem_rw_with_rand_reset.4146190346
Directory /workspace/12.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_rw.3426360565
Short name T412
Test name
Test status
Simulation time 1448046663 ps
CPU time 12.86 seconds
Started May 16 12:50:44 PM PDT 24
Finished May 16 12:51:11 PM PDT 24
Peak memory 211216 kb
Host smart-69540afe-2ec4-49fa-a16c-9e09a19d2800
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3426360565 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_csr_rw.3426360565
Directory /workspace/12.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_passthru_mem_tl_intg_err.742630725
Short name T95
Test name
Test status
Simulation time 8587988238 ps
CPU time 67.61 seconds
Started May 16 12:50:47 PM PDT 24
Finished May 16 12:52:09 PM PDT 24
Peak memory 211332 kb
Host smart-013c28b3-6216-4eba-aa8b-e8fcd35d3151
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=742630725 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_pa
ssthru_mem_tl_intg_err.742630725
Directory /workspace/12.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_same_csr_outstanding.317375783
Short name T433
Test name
Test status
Simulation time 1623675951 ps
CPU time 15.86 seconds
Started May 16 12:50:47 PM PDT 24
Finished May 16 12:51:16 PM PDT 24
Peak memory 211144 kb
Host smart-0137fc12-a842-4c74-a37e-b4f6a7d304a8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=317375783 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_c
trl_same_csr_outstanding.317375783
Directory /workspace/12.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_errors.3630918968
Short name T375
Test name
Test status
Simulation time 1760300212 ps
CPU time 15.9 seconds
Started May 16 12:50:46 PM PDT 24
Finished May 16 12:51:15 PM PDT 24
Peak memory 219440 kb
Host smart-c19ad2f2-bf0b-430f-a44b-05e67cae6f4d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3630918968 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_tl_errors.3630918968
Directory /workspace/12.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_intg_err.3904714289
Short name T58
Test name
Test status
Simulation time 10696442801 ps
CPU time 46.71 seconds
Started May 16 12:50:48 PM PDT 24
Finished May 16 12:51:48 PM PDT 24
Peak memory 219528 kb
Host smart-ead903b4-c651-47fc-9c1e-35ad00ec6a82
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3904714289 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_tl_i
ntg_err.3904714289
Directory /workspace/12.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_mem_rw_with_rand_reset.355260146
Short name T425
Test name
Test status
Simulation time 7095569291 ps
CPU time 15.02 seconds
Started May 16 12:51:02 PM PDT 24
Finished May 16 12:51:25 PM PDT 24
Peak memory 219588 kb
Host smart-9ae9a82b-80eb-46ac-a881-28513b9c505d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=355260146 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 13.rom_ctrl_csr_mem_rw_with_rand_reset.355260146
Directory /workspace/13.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_rw.1141897576
Short name T104
Test name
Test status
Simulation time 2443191304 ps
CPU time 11.03 seconds
Started May 16 12:50:48 PM PDT 24
Finished May 16 12:51:12 PM PDT 24
Peak memory 211200 kb
Host smart-09fd1821-c591-42c3-bc14-6c3896d753c8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1141897576 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_csr_rw.1141897576
Directory /workspace/13.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_passthru_mem_tl_intg_err.2591740625
Short name T414
Test name
Test status
Simulation time 47479462292 ps
CPU time 96.19 seconds
Started May 16 12:50:47 PM PDT 24
Finished May 16 12:52:36 PM PDT 24
Peak memory 211384 kb
Host smart-1eade1ce-c2eb-44c8-affe-58de282f6ebb
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2591740625 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_p
assthru_mem_tl_intg_err.2591740625
Directory /workspace/13.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_same_csr_outstanding.324414753
Short name T97
Test name
Test status
Simulation time 8706000177 ps
CPU time 15.78 seconds
Started May 16 12:50:59 PM PDT 24
Finished May 16 12:51:24 PM PDT 24
Peak memory 211136 kb
Host smart-3e4abca3-e3d3-4e7b-ba63-435c03023fab
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=324414753 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_c
trl_same_csr_outstanding.324414753
Directory /workspace/13.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_errors.2979852297
Short name T424
Test name
Test status
Simulation time 1332618768 ps
CPU time 15.42 seconds
Started May 16 12:50:48 PM PDT 24
Finished May 16 12:51:17 PM PDT 24
Peak memory 219416 kb
Host smart-4d27450a-eb71-4518-9d86-66dbde2ea870
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2979852297 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_tl_errors.2979852297
Directory /workspace/13.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_intg_err.4222737650
Short name T441
Test name
Test status
Simulation time 5114779446 ps
CPU time 74.68 seconds
Started May 16 12:50:46 PM PDT 24
Finished May 16 12:52:13 PM PDT 24
Peak memory 212480 kb
Host smart-f3e8bc83-3357-4ccc-9e47-ccb277fbce2b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4222737650 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_tl_i
ntg_err.4222737650
Directory /workspace/13.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_mem_rw_with_rand_reset.4204161630
Short name T437
Test name
Test status
Simulation time 1156874176 ps
CPU time 10.73 seconds
Started May 16 12:51:00 PM PDT 24
Finished May 16 12:51:20 PM PDT 24
Peak memory 219480 kb
Host smart-185bb44e-b240-4422-8c7d-83ff1f587582
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4204161630 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 14.rom_ctrl_csr_mem_rw_with_rand_reset.4204161630
Directory /workspace/14.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_rw.3039419045
Short name T452
Test name
Test status
Simulation time 4560509677 ps
CPU time 14.67 seconds
Started May 16 12:51:00 PM PDT 24
Finished May 16 12:51:24 PM PDT 24
Peak memory 211276 kb
Host smart-22c802f0-ccfe-40a4-8967-be95f929cc3b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3039419045 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_csr_rw.3039419045
Directory /workspace/14.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_passthru_mem_tl_intg_err.3798124473
Short name T93
Test name
Test status
Simulation time 5307084758 ps
CPU time 36.11 seconds
Started May 16 12:51:00 PM PDT 24
Finished May 16 12:51:45 PM PDT 24
Peak memory 211360 kb
Host smart-ce50cc01-fb24-441a-885d-5db56731d658
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3798124473 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_p
assthru_mem_tl_intg_err.3798124473
Directory /workspace/14.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_same_csr_outstanding.1439939356
Short name T451
Test name
Test status
Simulation time 347251984 ps
CPU time 4.35 seconds
Started May 16 12:50:58 PM PDT 24
Finished May 16 12:51:12 PM PDT 24
Peak memory 211112 kb
Host smart-b8315fa8-85f3-4007-b043-dba9c3404e54
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1439939356 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_
ctrl_same_csr_outstanding.1439939356
Directory /workspace/14.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_errors.4042057965
Short name T417
Test name
Test status
Simulation time 347361708 ps
CPU time 6.57 seconds
Started May 16 12:50:57 PM PDT 24
Finished May 16 12:51:14 PM PDT 24
Peak memory 219484 kb
Host smart-938313ad-cf28-4929-9c5d-d782a091d336
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4042057965 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_tl_errors.4042057965
Directory /workspace/14.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_mem_rw_with_rand_reset.67721032
Short name T378
Test name
Test status
Simulation time 2647044438 ps
CPU time 8.65 seconds
Started May 16 12:51:00 PM PDT 24
Finished May 16 12:51:18 PM PDT 24
Peak memory 213012 kb
Host smart-c2002450-8dbc-43cc-92f3-6e2bd572793f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=67721032 -assert nopostproc +UVM_TESTNAME=r
om_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 15.rom_ctrl_csr_mem_rw_with_rand_reset.67721032
Directory /workspace/15.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_rw.2374049045
Short name T403
Test name
Test status
Simulation time 830864776 ps
CPU time 4.94 seconds
Started May 16 12:50:58 PM PDT 24
Finished May 16 12:51:13 PM PDT 24
Peak memory 211220 kb
Host smart-71812eb2-8125-4c46-8416-7b52c2bc3a0b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2374049045 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_csr_rw.2374049045
Directory /workspace/15.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_passthru_mem_tl_intg_err.766823741
Short name T466
Test name
Test status
Simulation time 14591825892 ps
CPU time 70.95 seconds
Started May 16 12:51:02 PM PDT 24
Finished May 16 12:52:21 PM PDT 24
Peak memory 211240 kb
Host smart-b3442781-cc0f-43fe-93e6-de89dd3dce57
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=766823741 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_pa
ssthru_mem_tl_intg_err.766823741
Directory /workspace/15.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_same_csr_outstanding.1296941028
Short name T98
Test name
Test status
Simulation time 858321485 ps
CPU time 9.42 seconds
Started May 16 12:50:59 PM PDT 24
Finished May 16 12:51:18 PM PDT 24
Peak memory 211108 kb
Host smart-99a4672e-624d-456c-91a5-dae30d1445ee
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1296941028 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_
ctrl_same_csr_outstanding.1296941028
Directory /workspace/15.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_errors.3721090876
Short name T439
Test name
Test status
Simulation time 1124002196 ps
CPU time 11.44 seconds
Started May 16 12:51:02 PM PDT 24
Finished May 16 12:51:21 PM PDT 24
Peak memory 219548 kb
Host smart-36d46305-b94f-40dd-960f-4bd0ae7ec61f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3721090876 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_tl_errors.3721090876
Directory /workspace/15.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_intg_err.581267076
Short name T113
Test name
Test status
Simulation time 2810698974 ps
CPU time 44.01 seconds
Started May 16 12:50:59 PM PDT 24
Finished May 16 12:51:52 PM PDT 24
Peak memory 211280 kb
Host smart-12e0cd82-2081-4f6a-8c98-80997fb35b2c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=581267076 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_tl_in
tg_err.581267076
Directory /workspace/15.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_mem_rw_with_rand_reset.67270943
Short name T400
Test name
Test status
Simulation time 1144769355 ps
CPU time 11.37 seconds
Started May 16 12:51:01 PM PDT 24
Finished May 16 12:51:21 PM PDT 24
Peak memory 213292 kb
Host smart-bb728370-ea92-4f83-bfd5-f1147f03a38f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=67270943 -assert nopostproc +UVM_TESTNAME=r
om_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 16.rom_ctrl_csr_mem_rw_with_rand_reset.67270943
Directory /workspace/16.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_rw.963279272
Short name T393
Test name
Test status
Simulation time 2133939499 ps
CPU time 16.45 seconds
Started May 16 12:51:00 PM PDT 24
Finished May 16 12:51:25 PM PDT 24
Peak memory 211264 kb
Host smart-fbcb2f8a-eb54-40cb-b960-ddffe4b7d5aa
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=963279272 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_csr_rw.963279272
Directory /workspace/16.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_same_csr_outstanding.902383650
Short name T465
Test name
Test status
Simulation time 1256451221 ps
CPU time 13.45 seconds
Started May 16 12:51:02 PM PDT 24
Finished May 16 12:51:23 PM PDT 24
Peak memory 211512 kb
Host smart-9796d9ad-a101-4f89-ad21-2f41cfd7c69b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=902383650 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_c
trl_same_csr_outstanding.902383650
Directory /workspace/16.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_errors.1335567842
Short name T389
Test name
Test status
Simulation time 2562265000 ps
CPU time 13.89 seconds
Started May 16 12:50:58 PM PDT 24
Finished May 16 12:51:22 PM PDT 24
Peak memory 219596 kb
Host smart-e55954a1-6c7d-4e4f-9dea-442819e5244c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1335567842 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_tl_errors.1335567842
Directory /workspace/16.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_intg_err.2731852660
Short name T110
Test name
Test status
Simulation time 1576671740 ps
CPU time 69.92 seconds
Started May 16 12:51:00 PM PDT 24
Finished May 16 12:52:19 PM PDT 24
Peak memory 211236 kb
Host smart-b5d5147e-1aca-4fca-9fb2-b70948995fc9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2731852660 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_tl_i
ntg_err.2731852660
Directory /workspace/16.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_mem_rw_with_rand_reset.3761575701
Short name T410
Test name
Test status
Simulation time 99344773 ps
CPU time 4.84 seconds
Started May 16 12:51:04 PM PDT 24
Finished May 16 12:51:16 PM PDT 24
Peak memory 214068 kb
Host smart-15c2eb39-e089-4e16-991e-a6ecafe5dea1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3761575701 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 17.rom_ctrl_csr_mem_rw_with_rand_reset.3761575701
Directory /workspace/17.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_rw.2063927688
Short name T404
Test name
Test status
Simulation time 2409717704 ps
CPU time 11.06 seconds
Started May 16 12:51:02 PM PDT 24
Finished May 16 12:51:21 PM PDT 24
Peak memory 211308 kb
Host smart-7c4fe4bb-86ff-462f-a992-20386c84738b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2063927688 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_csr_rw.2063927688
Directory /workspace/17.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_passthru_mem_tl_intg_err.1544701149
Short name T467
Test name
Test status
Simulation time 3794205491 ps
CPU time 43.07 seconds
Started May 16 12:51:02 PM PDT 24
Finished May 16 12:51:53 PM PDT 24
Peak memory 211380 kb
Host smart-debd5dfe-14a3-4fd9-98b1-786bb0f6e9a9
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1544701149 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_p
assthru_mem_tl_intg_err.1544701149
Directory /workspace/17.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_same_csr_outstanding.2464394720
Short name T408
Test name
Test status
Simulation time 8879776114 ps
CPU time 13.53 seconds
Started May 16 12:50:59 PM PDT 24
Finished May 16 12:51:22 PM PDT 24
Peak memory 211324 kb
Host smart-eda793f3-e7b5-40ac-b21a-76d3e99475f0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2464394720 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_
ctrl_same_csr_outstanding.2464394720
Directory /workspace/17.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_errors.3385497718
Short name T372
Test name
Test status
Simulation time 3758256054 ps
CPU time 19.2 seconds
Started May 16 12:51:02 PM PDT 24
Finished May 16 12:51:29 PM PDT 24
Peak memory 219480 kb
Host smart-86922ac9-48bb-467f-8b65-522123906221
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3385497718 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_tl_errors.3385497718
Directory /workspace/17.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_intg_err.2513196376
Short name T115
Test name
Test status
Simulation time 5082955883 ps
CPU time 48.24 seconds
Started May 16 12:51:02 PM PDT 24
Finished May 16 12:51:58 PM PDT 24
Peak memory 212060 kb
Host smart-428dd307-75ed-4c7f-bb32-ff14863b090f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2513196376 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_tl_i
ntg_err.2513196376
Directory /workspace/17.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_mem_rw_with_rand_reset.868440261
Short name T446
Test name
Test status
Simulation time 5324753067 ps
CPU time 12.79 seconds
Started May 16 12:51:04 PM PDT 24
Finished May 16 12:51:24 PM PDT 24
Peak memory 219424 kb
Host smart-9d46c729-70fe-42cf-a08f-5121e933e098
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=868440261 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 18.rom_ctrl_csr_mem_rw_with_rand_reset.868440261
Directory /workspace/18.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_rw.271133372
Short name T81
Test name
Test status
Simulation time 8533692267 ps
CPU time 10.32 seconds
Started May 16 12:51:06 PM PDT 24
Finished May 16 12:51:24 PM PDT 24
Peak memory 211212 kb
Host smart-de03e96c-7242-4120-9e76-7f5776ff52ef
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=271133372 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_csr_rw.271133372
Directory /workspace/18.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_passthru_mem_tl_intg_err.2418395439
Short name T456
Test name
Test status
Simulation time 11854645548 ps
CPU time 94.98 seconds
Started May 16 12:51:03 PM PDT 24
Finished May 16 12:52:46 PM PDT 24
Peak memory 211364 kb
Host smart-c347914d-a09d-4e88-b3ef-47879bcbb7dc
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2418395439 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_p
assthru_mem_tl_intg_err.2418395439
Directory /workspace/18.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_same_csr_outstanding.810620713
Short name T440
Test name
Test status
Simulation time 1181241330 ps
CPU time 11.56 seconds
Started May 16 12:51:06 PM PDT 24
Finished May 16 12:51:25 PM PDT 24
Peak memory 211144 kb
Host smart-7fd58964-7225-4dfe-8b67-11457d542f45
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=810620713 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_c
trl_same_csr_outstanding.810620713
Directory /workspace/18.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_errors.3578697793
Short name T397
Test name
Test status
Simulation time 23493909143 ps
CPU time 12.95 seconds
Started May 16 12:51:04 PM PDT 24
Finished May 16 12:51:24 PM PDT 24
Peak memory 219572 kb
Host smart-dc6a4b20-5618-4d72-b64d-281ee7a2686a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3578697793 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_tl_errors.3578697793
Directory /workspace/18.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_intg_err.2018806089
Short name T116
Test name
Test status
Simulation time 4178181553 ps
CPU time 46.58 seconds
Started May 16 12:51:06 PM PDT 24
Finished May 16 12:52:00 PM PDT 24
Peak memory 212068 kb
Host smart-1648da47-4d1e-40d0-b445-324b65cda01a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2018806089 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_tl_i
ntg_err.2018806089
Directory /workspace/18.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_mem_rw_with_rand_reset.2030904319
Short name T401
Test name
Test status
Simulation time 1539490338 ps
CPU time 6.9 seconds
Started May 16 12:51:14 PM PDT 24
Finished May 16 12:51:27 PM PDT 24
Peak memory 219464 kb
Host smart-35011c04-87e3-4b7d-9af3-8c7ca7b57b03
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2030904319 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 19.rom_ctrl_csr_mem_rw_with_rand_reset.2030904319
Directory /workspace/19.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_rw.3630173620
Short name T396
Test name
Test status
Simulation time 168143366 ps
CPU time 4.32 seconds
Started May 16 12:51:18 PM PDT 24
Finished May 16 12:51:29 PM PDT 24
Peak memory 211136 kb
Host smart-8fc5e661-1cdf-4b6e-a665-2dd7c27aff39
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3630173620 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_csr_rw.3630173620
Directory /workspace/19.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_passthru_mem_tl_intg_err.3967818757
Short name T82
Test name
Test status
Simulation time 11184075478 ps
CPU time 54.22 seconds
Started May 16 12:51:10 PM PDT 24
Finished May 16 12:52:11 PM PDT 24
Peak memory 211264 kb
Host smart-9142f8cb-8b72-4ef2-8fe1-6a09206cd0c5
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3967818757 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_p
assthru_mem_tl_intg_err.3967818757
Directory /workspace/19.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_same_csr_outstanding.885439449
Short name T407
Test name
Test status
Simulation time 2400643926 ps
CPU time 7.96 seconds
Started May 16 12:51:10 PM PDT 24
Finished May 16 12:51:25 PM PDT 24
Peak memory 211204 kb
Host smart-478d6998-5d12-4023-b3a3-f799d67d3e6b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=885439449 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_c
trl_same_csr_outstanding.885439449
Directory /workspace/19.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_errors.2755281502
Short name T444
Test name
Test status
Simulation time 16263738081 ps
CPU time 16.75 seconds
Started May 16 12:51:12 PM PDT 24
Finished May 16 12:51:35 PM PDT 24
Peak memory 219204 kb
Host smart-7692d3e6-3758-4040-9844-3cb89ff01fcf
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2755281502 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_tl_errors.2755281502
Directory /workspace/19.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_intg_err.1720597951
Short name T118
Test name
Test status
Simulation time 688974038 ps
CPU time 39.08 seconds
Started May 16 12:51:10 PM PDT 24
Finished May 16 12:51:56 PM PDT 24
Peak memory 211284 kb
Host smart-8ab399b8-938f-4821-8285-d7c314370740
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1720597951 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_tl_i
ntg_err.1720597951
Directory /workspace/19.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_aliasing.3714919821
Short name T90
Test name
Test status
Simulation time 3034619615 ps
CPU time 13.01 seconds
Started May 16 12:50:06 PM PDT 24
Finished May 16 12:50:31 PM PDT 24
Peak memory 211304 kb
Host smart-fe020f7b-ef7b-4f1c-b929-83fd88597d4a
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3714919821 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_alia
sing.3714919821
Directory /workspace/2.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_bit_bash.3901417022
Short name T384
Test name
Test status
Simulation time 2188897422 ps
CPU time 6.58 seconds
Started May 16 12:50:17 PM PDT 24
Finished May 16 12:50:39 PM PDT 24
Peak memory 211236 kb
Host smart-daff499e-ea35-4afb-8a26-92550979a03a
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3901417022 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_bit_
bash.3901417022
Directory /workspace/2.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_hw_reset.1061385616
Short name T83
Test name
Test status
Simulation time 594269785 ps
CPU time 7.8 seconds
Started May 16 12:50:14 PM PDT 24
Finished May 16 12:50:35 PM PDT 24
Peak memory 211180 kb
Host smart-2411e8a2-0805-4c14-adad-fe40e2f60fd9
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1061385616 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_hw_r
eset.1061385616
Directory /workspace/2.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_mem_rw_with_rand_reset.1239066651
Short name T420
Test name
Test status
Simulation time 2613408056 ps
CPU time 16.41 seconds
Started May 16 12:50:08 PM PDT 24
Finished May 16 12:50:37 PM PDT 24
Peak memory 213632 kb
Host smart-3d6056f1-5c9e-4467-81d9-68e79c753142
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1239066651 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 2.rom_ctrl_csr_mem_rw_with_rand_reset.1239066651
Directory /workspace/2.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_rw.721510709
Short name T80
Test name
Test status
Simulation time 3933235357 ps
CPU time 9.71 seconds
Started May 16 12:50:06 PM PDT 24
Finished May 16 12:50:28 PM PDT 24
Peak memory 211280 kb
Host smart-69002972-3c6f-4b63-888b-39d4fcb89e37
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=721510709 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_rw.721510709
Directory /workspace/2.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_partial_access.2955122376
Short name T430
Test name
Test status
Simulation time 89956750 ps
CPU time 4.13 seconds
Started May 16 12:50:13 PM PDT 24
Finished May 16 12:50:30 PM PDT 24
Peak memory 211012 kb
Host smart-39bbe1c2-6184-4a09-a6ea-5b928ac4f1d2
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2955122376 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctr
l_mem_partial_access.2955122376
Directory /workspace/2.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_walk.2523450822
Short name T442
Test name
Test status
Simulation time 88035347 ps
CPU time 4.21 seconds
Started May 16 12:50:08 PM PDT 24
Finished May 16 12:50:25 PM PDT 24
Peak memory 211204 kb
Host smart-0d644a7e-d349-4e4a-8ead-2ac1e18d3253
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2523450822 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_mem_walk
.2523450822
Directory /workspace/2.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_passthru_mem_tl_intg_err.517493047
Short name T86
Test name
Test status
Simulation time 2218092089 ps
CPU time 18.2 seconds
Started May 16 12:50:07 PM PDT 24
Finished May 16 12:50:38 PM PDT 24
Peak memory 211360 kb
Host smart-8b43536b-e9ec-434e-bb48-44a0521344ce
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=517493047 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_pas
sthru_mem_tl_intg_err.517493047
Directory /workspace/2.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_same_csr_outstanding.4031111443
Short name T416
Test name
Test status
Simulation time 1372536616 ps
CPU time 12.57 seconds
Started May 16 12:50:06 PM PDT 24
Finished May 16 12:50:31 PM PDT 24
Peak memory 211172 kb
Host smart-c510eb4f-3781-41dc-92fc-eb355ad4dc20
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4031111443 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_c
trl_same_csr_outstanding.4031111443
Directory /workspace/2.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_errors.3399336383
Short name T376
Test name
Test status
Simulation time 7004069665 ps
CPU time 15.05 seconds
Started May 16 12:50:07 PM PDT 24
Finished May 16 12:50:35 PM PDT 24
Peak memory 219556 kb
Host smart-a9d2071c-a254-47ac-9f4f-a3d519398616
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3399336383 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_tl_errors.3399336383
Directory /workspace/2.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_intg_err.1098953915
Short name T111
Test name
Test status
Simulation time 1867367847 ps
CPU time 45.99 seconds
Started May 16 12:50:11 PM PDT 24
Finished May 16 12:51:09 PM PDT 24
Peak memory 212708 kb
Host smart-1c6962c0-0a45-47b1-acab-5fabab5df083
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1098953915 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_tl_in
tg_err.1098953915
Directory /workspace/2.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_aliasing.2393936275
Short name T79
Test name
Test status
Simulation time 4503178043 ps
CPU time 16.94 seconds
Started May 16 12:50:17 PM PDT 24
Finished May 16 12:50:48 PM PDT 24
Peak memory 211300 kb
Host smart-71bacb5a-b92d-4395-a79b-56ebba273435
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2393936275 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_alia
sing.2393936275
Directory /workspace/3.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_bit_bash.914617320
Short name T383
Test name
Test status
Simulation time 2237376166 ps
CPU time 7.61 seconds
Started May 16 12:50:16 PM PDT 24
Finished May 16 12:50:38 PM PDT 24
Peak memory 211208 kb
Host smart-299ebc1d-1eba-436b-ac93-dab1f4bd9567
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=914617320 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_bit_b
ash.914617320
Directory /workspace/3.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_hw_reset.1375854435
Short name T402
Test name
Test status
Simulation time 250723159 ps
CPU time 7.37 seconds
Started May 16 12:50:17 PM PDT 24
Finished May 16 12:50:39 PM PDT 24
Peak memory 211240 kb
Host smart-35869934-c812-45df-a4f7-4d44f373a91c
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1375854435 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_hw_r
eset.1375854435
Directory /workspace/3.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_mem_rw_with_rand_reset.2379381162
Short name T411
Test name
Test status
Simulation time 2151675543 ps
CPU time 17.03 seconds
Started May 16 12:50:14 PM PDT 24
Finished May 16 12:50:44 PM PDT 24
Peak memory 219548 kb
Host smart-32aff528-ca42-49e1-9167-2a221ed44b51
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2379381162 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 3.rom_ctrl_csr_mem_rw_with_rand_reset.2379381162
Directory /workspace/3.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_rw.1198624391
Short name T453
Test name
Test status
Simulation time 8025289583 ps
CPU time 15.77 seconds
Started May 16 12:50:14 PM PDT 24
Finished May 16 12:50:43 PM PDT 24
Peak memory 211356 kb
Host smart-68f0619c-1d7b-4ab3-881f-ef170f2867cb
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1198624391 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_rw.1198624391
Directory /workspace/3.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_partial_access.4146276445
Short name T428
Test name
Test status
Simulation time 1026154984 ps
CPU time 9.94 seconds
Started May 16 12:50:18 PM PDT 24
Finished May 16 12:50:43 PM PDT 24
Peak memory 211076 kb
Host smart-7597fadc-9b45-4ba1-b0c9-0ea2a05c3c02
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4146276445 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctr
l_mem_partial_access.4146276445
Directory /workspace/3.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_walk.1682697941
Short name T382
Test name
Test status
Simulation time 1955921964 ps
CPU time 11.49 seconds
Started May 16 12:50:20 PM PDT 24
Finished May 16 12:50:46 PM PDT 24
Peak memory 211132 kb
Host smart-cff6d12c-83d8-4b4d-8b36-71829396e89b
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1682697941 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_mem_walk
.1682697941
Directory /workspace/3.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_passthru_mem_tl_intg_err.2039309707
Short name T94
Test name
Test status
Simulation time 8632868106 ps
CPU time 78.71 seconds
Started May 16 12:50:13 PM PDT 24
Finished May 16 12:51:44 PM PDT 24
Peak memory 212332 kb
Host smart-c77c039c-7120-45bb-aa0f-686b09a7d081
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2039309707 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_pa
ssthru_mem_tl_intg_err.2039309707
Directory /workspace/3.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_same_csr_outstanding.1102939334
Short name T421
Test name
Test status
Simulation time 98083883 ps
CPU time 6.01 seconds
Started May 16 12:50:14 PM PDT 24
Finished May 16 12:50:33 PM PDT 24
Peak memory 211236 kb
Host smart-9a835992-7289-46ec-8d0a-0a4661a166e4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1102939334 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_c
trl_same_csr_outstanding.1102939334
Directory /workspace/3.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_errors.814600851
Short name T394
Test name
Test status
Simulation time 7183081146 ps
CPU time 18.81 seconds
Started May 16 12:50:14 PM PDT 24
Finished May 16 12:50:47 PM PDT 24
Peak memory 219576 kb
Host smart-e7817ebd-32fa-4ea9-867f-e99aa003039a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=814600851 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_tl_errors.814600851
Directory /workspace/3.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_intg_err.289690601
Short name T112
Test name
Test status
Simulation time 1945704285 ps
CPU time 77.33 seconds
Started May 16 12:50:17 PM PDT 24
Finished May 16 12:51:49 PM PDT 24
Peak memory 211236 kb
Host smart-56d65530-b2fa-4c25-bfd5-39f25d72bbe2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=289690601 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_tl_int
g_err.289690601
Directory /workspace/3.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_aliasing.1846360134
Short name T87
Test name
Test status
Simulation time 168531616 ps
CPU time 4.15 seconds
Started May 16 12:50:24 PM PDT 24
Finished May 16 12:50:44 PM PDT 24
Peak memory 211180 kb
Host smart-81833011-69a0-4e91-966c-a60a29f071ff
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1846360134 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_alia
sing.1846360134
Directory /workspace/4.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_bit_bash.945504725
Short name T391
Test name
Test status
Simulation time 1314539282 ps
CPU time 12.79 seconds
Started May 16 12:50:22 PM PDT 24
Finished May 16 12:50:50 PM PDT 24
Peak memory 211168 kb
Host smart-78748a22-bc3a-410f-89f0-6aacffef7d0b
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=945504725 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_bit_b
ash.945504725
Directory /workspace/4.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_hw_reset.2868069845
Short name T450
Test name
Test status
Simulation time 296290241 ps
CPU time 9.31 seconds
Started May 16 12:50:28 PM PDT 24
Finished May 16 12:50:54 PM PDT 24
Peak memory 211244 kb
Host smart-3a8fd1c5-26f8-4c55-92da-40f06814354f
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2868069845 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_hw_r
eset.2868069845
Directory /workspace/4.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_mem_rw_with_rand_reset.4112268743
Short name T385
Test name
Test status
Simulation time 4385225829 ps
CPU time 17.66 seconds
Started May 16 12:50:23 PM PDT 24
Finished May 16 12:50:57 PM PDT 24
Peak memory 219548 kb
Host smart-df3d3c41-4282-466b-a775-027079703b3d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4112268743 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 4.rom_ctrl_csr_mem_rw_with_rand_reset.4112268743
Directory /workspace/4.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_rw.2150306396
Short name T464
Test name
Test status
Simulation time 8517614325 ps
CPU time 9.46 seconds
Started May 16 12:50:24 PM PDT 24
Finished May 16 12:50:51 PM PDT 24
Peak memory 211208 kb
Host smart-97dd893b-4c2f-4a27-9359-0171508b0682
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2150306396 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_rw.2150306396
Directory /workspace/4.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_partial_access.3915439877
Short name T395
Test name
Test status
Simulation time 8058914055 ps
CPU time 15.66 seconds
Started May 16 12:50:27 PM PDT 24
Finished May 16 12:51:00 PM PDT 24
Peak memory 211180 kb
Host smart-da24a846-9d89-479a-9b78-cf0a53e97d4d
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3915439877 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctr
l_mem_partial_access.3915439877
Directory /workspace/4.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_walk.3216931108
Short name T370
Test name
Test status
Simulation time 619024560 ps
CPU time 8.04 seconds
Started May 16 12:50:24 PM PDT 24
Finished May 16 12:50:49 PM PDT 24
Peak memory 211148 kb
Host smart-460d4cfc-04a5-4571-8f4d-6a21daf1899a
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3216931108 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_mem_walk
.3216931108
Directory /workspace/4.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_passthru_mem_tl_intg_err.1270362988
Short name T443
Test name
Test status
Simulation time 364008410 ps
CPU time 18.6 seconds
Started May 16 12:50:14 PM PDT 24
Finished May 16 12:50:47 PM PDT 24
Peak memory 211216 kb
Host smart-96f5ddae-0e77-4f6c-8d96-8e9e33a4ff3d
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1270362988 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_pa
ssthru_mem_tl_intg_err.1270362988
Directory /workspace/4.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_same_csr_outstanding.146298110
Short name T100
Test name
Test status
Simulation time 3404520036 ps
CPU time 10.31 seconds
Started May 16 12:50:22 PM PDT 24
Finished May 16 12:50:48 PM PDT 24
Peak memory 211228 kb
Host smart-ade2d884-5be5-4536-8252-cf43a9e7fbd1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=146298110 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ct
rl_same_csr_outstanding.146298110
Directory /workspace/4.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_errors.3958336022
Short name T379
Test name
Test status
Simulation time 348338633 ps
CPU time 6.7 seconds
Started May 16 12:50:14 PM PDT 24
Finished May 16 12:50:33 PM PDT 24
Peak memory 219536 kb
Host smart-eb3e15d0-46ba-4a95-938d-01e2e2bc7c0f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3958336022 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_tl_errors.3958336022
Directory /workspace/4.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_intg_err.2324827466
Short name T60
Test name
Test status
Simulation time 601970224 ps
CPU time 39.39 seconds
Started May 16 12:50:16 PM PDT 24
Finished May 16 12:51:09 PM PDT 24
Peak memory 211292 kb
Host smart-930d8e76-081e-4bd1-8282-a6e5ac2f1b3c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2324827466 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_tl_in
tg_err.2324827466
Directory /workspace/4.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_mem_rw_with_rand_reset.3186014441
Short name T390
Test name
Test status
Simulation time 1836063882 ps
CPU time 7.18 seconds
Started May 16 12:50:28 PM PDT 24
Finished May 16 12:50:52 PM PDT 24
Peak memory 212156 kb
Host smart-f4050711-8bdc-4acc-9d1f-4a742f25e971
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3186014441 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 5.rom_ctrl_csr_mem_rw_with_rand_reset.3186014441
Directory /workspace/5.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_rw.3817354267
Short name T374
Test name
Test status
Simulation time 6744262122 ps
CPU time 14.79 seconds
Started May 16 12:50:25 PM PDT 24
Finished May 16 12:50:57 PM PDT 24
Peak memory 211256 kb
Host smart-5fa1b83b-9cf7-4874-8196-8738520fdcb1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3817354267 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_csr_rw.3817354267
Directory /workspace/5.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_passthru_mem_tl_intg_err.3191721071
Short name T422
Test name
Test status
Simulation time 39276525253 ps
CPU time 87.61 seconds
Started May 16 12:50:27 PM PDT 24
Finished May 16 12:52:12 PM PDT 24
Peak memory 211332 kb
Host smart-313fd6d4-9f54-4862-9d46-40de382bf3c8
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3191721071 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_pa
ssthru_mem_tl_intg_err.3191721071
Directory /workspace/5.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_same_csr_outstanding.3914453093
Short name T419
Test name
Test status
Simulation time 333988966 ps
CPU time 4.38 seconds
Started May 16 12:50:26 PM PDT 24
Finished May 16 12:50:47 PM PDT 24
Peak memory 211192 kb
Host smart-af4959d7-4759-4184-8cd1-44f499211a9e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3914453093 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_c
trl_same_csr_outstanding.3914453093
Directory /workspace/5.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_errors.2732336940
Short name T409
Test name
Test status
Simulation time 91218402 ps
CPU time 6.37 seconds
Started May 16 12:50:29 PM PDT 24
Finished May 16 12:50:52 PM PDT 24
Peak memory 219504 kb
Host smart-63cfcc03-a7b2-4ead-b83b-9282d592a63a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2732336940 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_tl_errors.2732336940
Directory /workspace/5.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_intg_err.879437953
Short name T59
Test name
Test status
Simulation time 1925945351 ps
CPU time 47.7 seconds
Started May 16 12:50:27 PM PDT 24
Finished May 16 12:51:32 PM PDT 24
Peak memory 211284 kb
Host smart-e46e943f-3e62-4867-bc55-e54597213929
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=879437953 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_tl_int
g_err.879437953
Directory /workspace/5.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_mem_rw_with_rand_reset.3422993389
Short name T415
Test name
Test status
Simulation time 97592414 ps
CPU time 4.76 seconds
Started May 16 12:50:32 PM PDT 24
Finished May 16 12:50:52 PM PDT 24
Peak memory 214092 kb
Host smart-52e0e81f-a02b-414d-83e9-1f1dc6498680
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3422993389 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 6.rom_ctrl_csr_mem_rw_with_rand_reset.3422993389
Directory /workspace/6.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_rw.324297191
Short name T101
Test name
Test status
Simulation time 2855649373 ps
CPU time 8.47 seconds
Started May 16 12:50:23 PM PDT 24
Finished May 16 12:50:48 PM PDT 24
Peak memory 211316 kb
Host smart-97499c82-eb46-44eb-8e56-672c741afa32
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=324297191 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_csr_rw.324297191
Directory /workspace/6.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_passthru_mem_tl_intg_err.1366076339
Short name T103
Test name
Test status
Simulation time 98849650809 ps
CPU time 49.5 seconds
Started May 16 12:50:24 PM PDT 24
Finished May 16 12:51:30 PM PDT 24
Peak memory 211240 kb
Host smart-74f0bb23-0aed-4bf8-beed-25b13d1ad3e7
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1366076339 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_pa
ssthru_mem_tl_intg_err.1366076339
Directory /workspace/6.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_same_csr_outstanding.2511298470
Short name T461
Test name
Test status
Simulation time 1665856753 ps
CPU time 16.01 seconds
Started May 16 12:50:29 PM PDT 24
Finished May 16 12:51:02 PM PDT 24
Peak memory 211224 kb
Host smart-3b588216-bddb-4390-8384-03edca4c21ce
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2511298470 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_c
trl_same_csr_outstanding.2511298470
Directory /workspace/6.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_errors.1410055552
Short name T371
Test name
Test status
Simulation time 430304879 ps
CPU time 10.83 seconds
Started May 16 12:50:23 PM PDT 24
Finished May 16 12:50:49 PM PDT 24
Peak memory 219424 kb
Host smart-89e9f7ac-34c1-4295-962c-c01182424797
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1410055552 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_tl_errors.1410055552
Directory /workspace/6.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_mem_rw_with_rand_reset.3106724392
Short name T418
Test name
Test status
Simulation time 10535396803 ps
CPU time 14.87 seconds
Started May 16 12:50:34 PM PDT 24
Finished May 16 12:51:04 PM PDT 24
Peak memory 219560 kb
Host smart-8ec09890-c663-4e36-836e-8762abd93d8d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3106724392 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 7.rom_ctrl_csr_mem_rw_with_rand_reset.3106724392
Directory /workspace/7.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_rw.684460462
Short name T84
Test name
Test status
Simulation time 979720156 ps
CPU time 10.03 seconds
Started May 16 12:50:34 PM PDT 24
Finished May 16 12:51:00 PM PDT 24
Peak memory 211216 kb
Host smart-5382dbee-a688-4ddf-afce-ca7d700f0fe6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=684460462 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_csr_rw.684460462
Directory /workspace/7.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_passthru_mem_tl_intg_err.2182195325
Short name T92
Test name
Test status
Simulation time 3837430372 ps
CPU time 44 seconds
Started May 16 12:50:35 PM PDT 24
Finished May 16 12:51:34 PM PDT 24
Peak memory 211332 kb
Host smart-5b2791bf-6b52-4c5f-8aad-db38d962c9c3
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2182195325 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_pa
ssthru_mem_tl_intg_err.2182195325
Directory /workspace/7.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_same_csr_outstanding.2378234090
Short name T96
Test name
Test status
Simulation time 12678683918 ps
CPU time 12.5 seconds
Started May 16 12:50:32 PM PDT 24
Finished May 16 12:51:00 PM PDT 24
Peak memory 211312 kb
Host smart-ba96ecf7-7d90-4831-a4aa-6121f261b18d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2378234090 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_c
trl_same_csr_outstanding.2378234090
Directory /workspace/7.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_errors.1859447269
Short name T463
Test name
Test status
Simulation time 3592893591 ps
CPU time 16.01 seconds
Started May 16 12:50:35 PM PDT 24
Finished May 16 12:51:06 PM PDT 24
Peak memory 219552 kb
Host smart-acbd7c88-ff05-4da4-a5ed-da2f644b510b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1859447269 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_tl_errors.1859447269
Directory /workspace/7.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_intg_err.3691763540
Short name T119
Test name
Test status
Simulation time 4110322607 ps
CPU time 46.26 seconds
Started May 16 12:50:36 PM PDT 24
Finished May 16 12:51:40 PM PDT 24
Peak memory 212132 kb
Host smart-d1547cca-77fc-4de8-8992-830336c3e9ab
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3691763540 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_tl_in
tg_err.3691763540
Directory /workspace/7.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_mem_rw_with_rand_reset.3623826127
Short name T447
Test name
Test status
Simulation time 11209506927 ps
CPU time 11.54 seconds
Started May 16 12:50:34 PM PDT 24
Finished May 16 12:51:01 PM PDT 24
Peak memory 219548 kb
Host smart-df3f6541-0135-4ba4-9856-bb88a4d8484e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3623826127 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 8.rom_ctrl_csr_mem_rw_with_rand_reset.3623826127
Directory /workspace/8.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_rw.618415513
Short name T386
Test name
Test status
Simulation time 9039318632 ps
CPU time 15.5 seconds
Started May 16 12:50:35 PM PDT 24
Finished May 16 12:51:06 PM PDT 24
Peak memory 211236 kb
Host smart-2d4a841b-f4b7-429f-a6fb-0781e8f6d18c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=618415513 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_csr_rw.618415513
Directory /workspace/8.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_passthru_mem_tl_intg_err.708546159
Short name T413
Test name
Test status
Simulation time 50266347986 ps
CPU time 99.29 seconds
Started May 16 12:50:34 PM PDT 24
Finished May 16 12:52:29 PM PDT 24
Peak memory 211304 kb
Host smart-07e918c1-8d20-4602-a70e-fe628df6c376
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=708546159 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_pas
sthru_mem_tl_intg_err.708546159
Directory /workspace/8.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_same_csr_outstanding.1669958623
Short name T99
Test name
Test status
Simulation time 1767616756 ps
CPU time 10.81 seconds
Started May 16 12:50:34 PM PDT 24
Finished May 16 12:51:00 PM PDT 24
Peak memory 211188 kb
Host smart-c8bd882d-2aa0-4eb9-a095-4c9949ee31e2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1669958623 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_c
trl_same_csr_outstanding.1669958623
Directory /workspace/8.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_errors.1128553677
Short name T457
Test name
Test status
Simulation time 1362864909 ps
CPU time 15.45 seconds
Started May 16 12:50:33 PM PDT 24
Finished May 16 12:51:03 PM PDT 24
Peak memory 219516 kb
Host smart-31947b52-2172-47ff-8285-76559c089e0e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1128553677 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_tl_errors.1128553677
Directory /workspace/8.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_intg_err.1252493151
Short name T455
Test name
Test status
Simulation time 971700891 ps
CPU time 38.44 seconds
Started May 16 12:50:36 PM PDT 24
Finished May 16 12:51:31 PM PDT 24
Peak memory 219440 kb
Host smart-2659f4ef-8150-435b-b936-cc1b5c81953a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1252493151 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_tl_in
tg_err.1252493151
Directory /workspace/8.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_mem_rw_with_rand_reset.881147448
Short name T62
Test name
Test status
Simulation time 3620558374 ps
CPU time 9.39 seconds
Started May 16 12:50:36 PM PDT 24
Finished May 16 12:51:02 PM PDT 24
Peak memory 213188 kb
Host smart-98980941-0fa1-43d3-a5ec-380405da330a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=881147448 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 9.rom_ctrl_csr_mem_rw_with_rand_reset.881147448
Directory /workspace/9.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_rw.245790914
Short name T458
Test name
Test status
Simulation time 320786716 ps
CPU time 4.14 seconds
Started May 16 12:50:34 PM PDT 24
Finished May 16 12:50:54 PM PDT 24
Peak memory 211224 kb
Host smart-9a71d024-6912-4477-904c-bace54d399f6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=245790914 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_csr_rw.245790914
Directory /workspace/9.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_passthru_mem_tl_intg_err.3838653717
Short name T459
Test name
Test status
Simulation time 26056673343 ps
CPU time 89.07 seconds
Started May 16 12:50:35 PM PDT 24
Finished May 16 12:52:19 PM PDT 24
Peak memory 211260 kb
Host smart-4f608aa1-4975-46ef-ad58-f888632be56d
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3838653717 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_pa
ssthru_mem_tl_intg_err.3838653717
Directory /workspace/9.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_same_csr_outstanding.384571066
Short name T399
Test name
Test status
Simulation time 88959241 ps
CPU time 4.16 seconds
Started May 16 12:50:34 PM PDT 24
Finished May 16 12:50:54 PM PDT 24
Peak memory 211260 kb
Host smart-d81e01a3-b4f4-4f3a-8a34-b587fdcbb6f8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=384571066 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ct
rl_same_csr_outstanding.384571066
Directory /workspace/9.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_errors.934293124
Short name T381
Test name
Test status
Simulation time 6371202384 ps
CPU time 15.71 seconds
Started May 16 12:50:36 PM PDT 24
Finished May 16 12:51:09 PM PDT 24
Peak memory 219624 kb
Host smart-b28248e4-6144-462f-b060-61edcfda5b43
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=934293124 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_tl_errors.934293124
Directory /workspace/9.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_intg_err.687230585
Short name T120
Test name
Test status
Simulation time 4170932024 ps
CPU time 39.39 seconds
Started May 16 12:50:35 PM PDT 24
Finished May 16 12:51:30 PM PDT 24
Peak memory 211796 kb
Host smart-5b591340-cb21-406f-8a7d-07fa2e4c25ee
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=687230585 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_tl_int
g_err.687230585
Directory /workspace/9.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/0.rom_ctrl_alert_test.4076415200
Short name T276
Test name
Test status
Simulation time 731135269 ps
CPU time 8.73 seconds
Started May 16 12:52:50 PM PDT 24
Finished May 16 12:53:09 PM PDT 24
Peak memory 211212 kb
Host smart-4eb2f398-b228-4a56-9c21-d36002c29ab2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4076415200 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_alert_test.4076415200
Directory /workspace/0.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/0.rom_ctrl_corrupt_sig_fatal_chk.2562921923
Short name T339
Test name
Test status
Simulation time 7679061473 ps
CPU time 134.06 seconds
Started May 16 12:52:54 PM PDT 24
Finished May 16 12:55:18 PM PDT 24
Peak memory 233896 kb
Host smart-aa626ea2-94b2-4b58-aef7-adca5cb1bcae
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2562921923 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_c
orrupt_sig_fatal_chk.2562921923
Directory /workspace/0.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/0.rom_ctrl_max_throughput_chk.1685830426
Short name T70
Test name
Test status
Simulation time 1206691523 ps
CPU time 12.79 seconds
Started May 16 12:52:50 PM PDT 24
Finished May 16 12:53:14 PM PDT 24
Peak memory 210984 kb
Host smart-df999934-ab4d-4e50-b054-930d473a39c1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1685830426 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_max_throughput_chk.1685830426
Directory /workspace/0.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/0.rom_ctrl_sec_cm.3350952909
Short name T36
Test name
Test status
Simulation time 8871833665 ps
CPU time 63.86 seconds
Started May 16 12:52:55 PM PDT 24
Finished May 16 12:54:09 PM PDT 24
Peak memory 236680 kb
Host smart-ffab6a47-bd6c-4e6c-abc2-fc1ff96d4b6f
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3350952909 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_sec_cm.3350952909
Directory /workspace/0.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/0.rom_ctrl_smoke.3623583802
Short name T272
Test name
Test status
Simulation time 2370000413 ps
CPU time 25.44 seconds
Started May 16 12:52:51 PM PDT 24
Finished May 16 12:53:27 PM PDT 24
Peak memory 219332 kb
Host smart-b7fb397d-7e98-4ebc-ab3d-b34b36de195e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3623583802 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_smoke.3623583802
Directory /workspace/0.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/0.rom_ctrl_stress_all.1471611749
Short name T43
Test name
Test status
Simulation time 3493779236 ps
CPU time 13.08 seconds
Started May 16 12:52:52 PM PDT 24
Finished May 16 12:53:16 PM PDT 24
Peak memory 211840 kb
Host smart-8eeb06f3-4d2c-4a5f-995c-3546497648da
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1471611749 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 0.rom_ctrl_stress_all.1471611749
Directory /workspace/0.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/1.rom_ctrl_alert_test.2899702137
Short name T39
Test name
Test status
Simulation time 2299914688 ps
CPU time 15.7 seconds
Started May 16 12:52:54 PM PDT 24
Finished May 16 12:53:19 PM PDT 24
Peak memory 211276 kb
Host smart-6c99b1c8-4b33-414a-874f-0774058063a2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2899702137 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_alert_test.2899702137
Directory /workspace/1.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/1.rom_ctrl_kmac_err_chk.797521631
Short name T363
Test name
Test status
Simulation time 4295297274 ps
CPU time 16.49 seconds
Started May 16 12:52:52 PM PDT 24
Finished May 16 12:53:19 PM PDT 24
Peak memory 212276 kb
Host smart-0f0267dc-a04a-4078-8463-22a05fdded39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=797521631 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_kmac_err_chk.797521631
Directory /workspace/1.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/1.rom_ctrl_max_throughput_chk.1392946223
Short name T322
Test name
Test status
Simulation time 3267988939 ps
CPU time 14.93 seconds
Started May 16 12:52:53 PM PDT 24
Finished May 16 12:53:18 PM PDT 24
Peak memory 211184 kb
Host smart-8a7afcd7-7886-4ba3-8d67-93ad854abce0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1392946223 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_max_throughput_chk.1392946223
Directory /workspace/1.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/1.rom_ctrl_smoke.940162998
Short name T252
Test name
Test status
Simulation time 7425727088 ps
CPU time 20.72 seconds
Started May 16 12:53:07 PM PDT 24
Finished May 16 12:53:33 PM PDT 24
Peak memory 219408 kb
Host smart-d8ecbc0b-4779-4586-8a5d-559eda0b240f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=940162998 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_smoke.940162998
Directory /workspace/1.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/1.rom_ctrl_stress_all.2002617567
Short name T198
Test name
Test status
Simulation time 648232716 ps
CPU time 37.51 seconds
Started May 16 12:52:52 PM PDT 24
Finished May 16 12:53:40 PM PDT 24
Peak memory 219284 kb
Host smart-cbd40c8b-fd61-45a9-888e-f90f1a795be8
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2002617567 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 1.rom_ctrl_stress_all.2002617567
Directory /workspace/1.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/10.rom_ctrl_alert_test.3743989729
Short name T340
Test name
Test status
Simulation time 6738600908 ps
CPU time 14.09 seconds
Started May 16 12:53:09 PM PDT 24
Finished May 16 12:53:32 PM PDT 24
Peak memory 211300 kb
Host smart-ddc4243d-013b-42ce-9faa-9575f1d3e8f3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3743989729 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_alert_test.3743989729
Directory /workspace/10.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/10.rom_ctrl_corrupt_sig_fatal_chk.300902453
Short name T315
Test name
Test status
Simulation time 17731779082 ps
CPU time 118.53 seconds
Started May 16 12:53:09 PM PDT 24
Finished May 16 12:55:15 PM PDT 24
Peak memory 228724 kb
Host smart-9fcb0c06-d1ac-4f14-a87c-c48d1ebc9410
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=300902453 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_c
orrupt_sig_fatal_chk.300902453
Directory /workspace/10.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/10.rom_ctrl_kmac_err_chk.904680965
Short name T246
Test name
Test status
Simulation time 5337302786 ps
CPU time 24.79 seconds
Started May 16 12:53:04 PM PDT 24
Finished May 16 12:53:34 PM PDT 24
Peak memory 212956 kb
Host smart-d723fdbd-048c-4325-aba9-7bf389db9bce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=904680965 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_kmac_err_chk.904680965
Directory /workspace/10.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/10.rom_ctrl_max_throughput_chk.2118256182
Short name T56
Test name
Test status
Simulation time 1030190595 ps
CPU time 11.67 seconds
Started May 16 12:53:04 PM PDT 24
Finished May 16 12:53:21 PM PDT 24
Peak memory 211028 kb
Host smart-c62fd561-7545-4512-9220-e8659b45fc3e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2118256182 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_max_throughput_chk.2118256182
Directory /workspace/10.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/10.rom_ctrl_smoke.2737469945
Short name T209
Test name
Test status
Simulation time 4284772999 ps
CPU time 21.77 seconds
Started May 16 12:53:08 PM PDT 24
Finished May 16 12:53:35 PM PDT 24
Peak memory 213132 kb
Host smart-2b514412-809c-498f-89be-24dd968dbf4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2737469945 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_smoke.2737469945
Directory /workspace/10.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/10.rom_ctrl_stress_all.4004588219
Short name T5
Test name
Test status
Simulation time 8568206610 ps
CPU time 67.44 seconds
Started May 16 12:53:04 PM PDT 24
Finished May 16 12:54:17 PM PDT 24
Peak memory 219380 kb
Host smart-7fa9d0c8-dec2-46cf-a537-42931d0574f3
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4004588219 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 10.rom_ctrl_stress_all.4004588219
Directory /workspace/10.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/10.rom_ctrl_stress_all_with_rand_reset.3201033072
Short name T50
Test name
Test status
Simulation time 21180202113 ps
CPU time 7439.97 seconds
Started May 16 12:53:08 PM PDT 24
Finished May 16 02:57:16 PM PDT 24
Peak memory 227004 kb
Host smart-66529244-52d3-4272-9261-cea38e8441a7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3201033072 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_stress_all_with_rand_reset.3201033072
Directory /workspace/10.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/11.rom_ctrl_alert_test.1229098579
Short name T307
Test name
Test status
Simulation time 7369125078 ps
CPU time 16.08 seconds
Started May 16 12:53:09 PM PDT 24
Finished May 16 12:53:33 PM PDT 24
Peak memory 211316 kb
Host smart-36663362-1baf-4aca-9412-c4232ecdfadd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1229098579 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_alert_test.1229098579
Directory /workspace/11.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/11.rom_ctrl_corrupt_sig_fatal_chk.1065171054
Short name T45
Test name
Test status
Simulation time 105780504947 ps
CPU time 255.37 seconds
Started May 16 12:53:09 PM PDT 24
Finished May 16 12:57:33 PM PDT 24
Peak memory 224716 kb
Host smart-fd31bd77-d60c-4117-84e3-2da95bf4e250
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1065171054 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_
corrupt_sig_fatal_chk.1065171054
Directory /workspace/11.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/11.rom_ctrl_kmac_err_chk.255037027
Short name T346
Test name
Test status
Simulation time 1330451512 ps
CPU time 18.04 seconds
Started May 16 12:53:06 PM PDT 24
Finished May 16 12:53:29 PM PDT 24
Peak memory 211984 kb
Host smart-02cf57dc-bdcf-4310-a242-d6eb91b81ca1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=255037027 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_kmac_err_chk.255037027
Directory /workspace/11.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/11.rom_ctrl_max_throughput_chk.2129557801
Short name T362
Test name
Test status
Simulation time 1813406740 ps
CPU time 10.51 seconds
Started May 16 12:53:14 PM PDT 24
Finished May 16 12:53:32 PM PDT 24
Peak memory 211008 kb
Host smart-ce6df3c5-5aa5-45ec-9a8e-b351914d6ec6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2129557801 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_max_throughput_chk.2129557801
Directory /workspace/11.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/11.rom_ctrl_smoke.3927832119
Short name T219
Test name
Test status
Simulation time 3378065867 ps
CPU time 29.95 seconds
Started May 16 12:53:08 PM PDT 24
Finished May 16 12:53:45 PM PDT 24
Peak memory 219276 kb
Host smart-3f7f3c40-f5cf-4525-b6ef-84d06b0f70e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3927832119 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_smoke.3927832119
Directory /workspace/11.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/11.rom_ctrl_stress_all.1006010865
Short name T323
Test name
Test status
Simulation time 17929234785 ps
CPU time 47.99 seconds
Started May 16 12:53:09 PM PDT 24
Finished May 16 12:54:04 PM PDT 24
Peak memory 216816 kb
Host smart-a35c5315-3015-403b-b068-020f2f8b9737
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1006010865 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 11.rom_ctrl_stress_all.1006010865
Directory /workspace/11.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/11.rom_ctrl_stress_all_with_rand_reset.1757290308
Short name T328
Test name
Test status
Simulation time 141789743128 ps
CPU time 2188.5 seconds
Started May 16 12:53:06 PM PDT 24
Finished May 16 01:29:40 PM PDT 24
Peak memory 235924 kb
Host smart-5be8fb8d-bf3a-460b-93f4-865437a5132a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1757290308 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_stress_all_with_rand_reset.1757290308
Directory /workspace/11.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/12.rom_ctrl_alert_test.3409295497
Short name T238
Test name
Test status
Simulation time 23646276558 ps
CPU time 17.21 seconds
Started May 16 12:53:07 PM PDT 24
Finished May 16 12:53:30 PM PDT 24
Peak memory 211328 kb
Host smart-7c54db9a-59c2-4375-8444-3071db731d64
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3409295497 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_alert_test.3409295497
Directory /workspace/12.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/12.rom_ctrl_corrupt_sig_fatal_chk.3398193048
Short name T30
Test name
Test status
Simulation time 2673172312 ps
CPU time 163.12 seconds
Started May 16 12:53:08 PM PDT 24
Finished May 16 12:55:58 PM PDT 24
Peak memory 237892 kb
Host smart-c978a764-75c6-494f-a9ad-78d1eff4eb70
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3398193048 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_
corrupt_sig_fatal_chk.3398193048
Directory /workspace/12.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/12.rom_ctrl_kmac_err_chk.1827422121
Short name T176
Test name
Test status
Simulation time 3840577830 ps
CPU time 21.61 seconds
Started May 16 12:53:06 PM PDT 24
Finished May 16 12:53:32 PM PDT 24
Peak memory 211768 kb
Host smart-26cb306f-a2ae-4508-82d2-30f5bbf6dc4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1827422121 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_kmac_err_chk.1827422121
Directory /workspace/12.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/12.rom_ctrl_max_throughput_chk.1371635667
Short name T234
Test name
Test status
Simulation time 2081672813 ps
CPU time 11.52 seconds
Started May 16 12:53:06 PM PDT 24
Finished May 16 12:53:22 PM PDT 24
Peak memory 211076 kb
Host smart-97851c02-8320-4c4b-87b5-2bef641d1dfd
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1371635667 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_max_throughput_chk.1371635667
Directory /workspace/12.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/12.rom_ctrl_smoke.45605066
Short name T172
Test name
Test status
Simulation time 35499196055 ps
CPU time 22.02 seconds
Started May 16 12:53:07 PM PDT 24
Finished May 16 12:53:35 PM PDT 24
Peak memory 219420 kb
Host smart-b3956eec-6ec9-4d44-b875-b27404b29a83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=45605066 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_smoke.45605066
Directory /workspace/12.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/12.rom_ctrl_stress_all.2108588540
Short name T10
Test name
Test status
Simulation time 5952162830 ps
CPU time 36.75 seconds
Started May 16 12:53:03 PM PDT 24
Finished May 16 12:53:45 PM PDT 24
Peak memory 219392 kb
Host smart-bd450ed3-b978-46e0-b771-fea01a3388c0
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2108588540 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 12.rom_ctrl_stress_all.2108588540
Directory /workspace/12.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/13.rom_ctrl_alert_test.3097304828
Short name T366
Test name
Test status
Simulation time 5883392958 ps
CPU time 14.04 seconds
Started May 16 12:53:13 PM PDT 24
Finished May 16 12:53:35 PM PDT 24
Peak memory 211284 kb
Host smart-9c437b31-824f-4375-aa08-1bf8ccc696d4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3097304828 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_alert_test.3097304828
Directory /workspace/13.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/13.rom_ctrl_corrupt_sig_fatal_chk.3058961617
Short name T169
Test name
Test status
Simulation time 36025479333 ps
CPU time 171.64 seconds
Started May 16 12:53:05 PM PDT 24
Finished May 16 12:56:01 PM PDT 24
Peak memory 218492 kb
Host smart-5432ddb2-b07b-4fbb-b7ff-2e2c8f7760bd
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3058961617 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_
corrupt_sig_fatal_chk.3058961617
Directory /workspace/13.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/13.rom_ctrl_smoke.2993542459
Short name T298
Test name
Test status
Simulation time 21365679647 ps
CPU time 23.59 seconds
Started May 16 12:53:08 PM PDT 24
Finished May 16 12:53:38 PM PDT 24
Peak memory 219392 kb
Host smart-00121f4b-a494-4e32-8f30-c0ce1c154a32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2993542459 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_smoke.2993542459
Directory /workspace/13.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/13.rom_ctrl_stress_all.3209608625
Short name T359
Test name
Test status
Simulation time 2198168233 ps
CPU time 21.58 seconds
Started May 16 12:53:08 PM PDT 24
Finished May 16 12:53:35 PM PDT 24
Peak memory 213772 kb
Host smart-0907bf44-1114-4e36-9ade-b3aac3d8fcd7
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3209608625 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 13.rom_ctrl_stress_all.3209608625
Directory /workspace/13.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/13.rom_ctrl_stress_all_with_rand_reset.126113358
Short name T19
Test name
Test status
Simulation time 300208200675 ps
CPU time 9412.5 seconds
Started May 16 12:53:06 PM PDT 24
Finished May 16 03:30:06 PM PDT 24
Peak memory 238448 kb
Host smart-145c9121-826a-4d7c-bf10-4a1cd4a9ca00
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=126113358 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_stress_all_with_rand_reset.126113358
Directory /workspace/13.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/14.rom_ctrl_alert_test.1976872515
Short name T332
Test name
Test status
Simulation time 89089426 ps
CPU time 4.26 seconds
Started May 16 12:53:12 PM PDT 24
Finished May 16 12:53:25 PM PDT 24
Peak memory 211096 kb
Host smart-0eb8ad43-54c9-402e-9cbe-10c1ccc63bcd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1976872515 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_alert_test.1976872515
Directory /workspace/14.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/14.rom_ctrl_corrupt_sig_fatal_chk.3554370785
Short name T351
Test name
Test status
Simulation time 11101002640 ps
CPU time 162.53 seconds
Started May 16 12:53:05 PM PDT 24
Finished May 16 12:55:52 PM PDT 24
Peak memory 234816 kb
Host smart-ee85646b-cf37-4275-8547-45a6ca004baf
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3554370785 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_
corrupt_sig_fatal_chk.3554370785
Directory /workspace/14.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/14.rom_ctrl_kmac_err_chk.3283483872
Short name T229
Test name
Test status
Simulation time 181690210 ps
CPU time 9.43 seconds
Started May 16 12:53:04 PM PDT 24
Finished May 16 12:53:18 PM PDT 24
Peak memory 212336 kb
Host smart-3b307a27-7fa8-47ed-9a3d-dbba6ff05626
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3283483872 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_kmac_err_chk.3283483872
Directory /workspace/14.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/14.rom_ctrl_max_throughput_chk.2220870964
Short name T72
Test name
Test status
Simulation time 1235545219 ps
CPU time 7.48 seconds
Started May 16 12:53:10 PM PDT 24
Finished May 16 12:53:26 PM PDT 24
Peak memory 211076 kb
Host smart-fb5aa774-aba8-4531-a4a2-807f06310a33
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2220870964 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_max_throughput_chk.2220870964
Directory /workspace/14.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/14.rom_ctrl_smoke.452679976
Short name T357
Test name
Test status
Simulation time 11016505816 ps
CPU time 30.87 seconds
Started May 16 12:53:13 PM PDT 24
Finished May 16 12:53:52 PM PDT 24
Peak memory 213824 kb
Host smart-63169230-4d86-45c9-a976-a15d9254ca5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=452679976 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_smoke.452679976
Directory /workspace/14.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/14.rom_ctrl_stress_all.2260560938
Short name T25
Test name
Test status
Simulation time 4729616019 ps
CPU time 27.66 seconds
Started May 16 12:53:07 PM PDT 24
Finished May 16 12:53:40 PM PDT 24
Peak memory 219396 kb
Host smart-6ddab812-80c6-4112-81b2-3d314013607a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2260560938 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 14.rom_ctrl_stress_all.2260560938
Directory /workspace/14.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/14.rom_ctrl_stress_all_with_rand_reset.1512793995
Short name T51
Test name
Test status
Simulation time 19540502720 ps
CPU time 805.1 seconds
Started May 16 12:53:09 PM PDT 24
Finished May 16 01:06:42 PM PDT 24
Peak memory 235896 kb
Host smart-ec65a926-ca1d-4c3d-a41b-e07be7f8f910
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1512793995 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_stress_all_with_rand_reset.1512793995
Directory /workspace/14.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/15.rom_ctrl_alert_test.3352348276
Short name T342
Test name
Test status
Simulation time 1750089938 ps
CPU time 13.56 seconds
Started May 16 12:53:09 PM PDT 24
Finished May 16 12:53:31 PM PDT 24
Peak memory 211236 kb
Host smart-6f542362-5a85-4e39-ab7c-4266ff7cbfb7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3352348276 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_alert_test.3352348276
Directory /workspace/15.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/15.rom_ctrl_corrupt_sig_fatal_chk.742421878
Short name T73
Test name
Test status
Simulation time 62278375472 ps
CPU time 221.11 seconds
Started May 16 12:53:07 PM PDT 24
Finished May 16 12:56:54 PM PDT 24
Peak memory 218600 kb
Host smart-cf8c9434-0e21-4c1c-84f5-e7b9f168a9d3
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=742421878 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_c
orrupt_sig_fatal_chk.742421878
Directory /workspace/15.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/15.rom_ctrl_kmac_err_chk.898243505
Short name T254
Test name
Test status
Simulation time 6939197217 ps
CPU time 28.08 seconds
Started May 16 12:53:08 PM PDT 24
Finished May 16 12:53:44 PM PDT 24
Peak memory 212240 kb
Host smart-3d93b04c-9849-4d06-b434-81ab80993552
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=898243505 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_kmac_err_chk.898243505
Directory /workspace/15.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/15.rom_ctrl_max_throughput_chk.3852756000
Short name T237
Test name
Test status
Simulation time 3084632186 ps
CPU time 14.59 seconds
Started May 16 12:53:09 PM PDT 24
Finished May 16 12:53:31 PM PDT 24
Peak memory 211156 kb
Host smart-3b402e34-0594-43e0-830e-8bc17ed30aff
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3852756000 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_max_throughput_chk.3852756000
Directory /workspace/15.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/15.rom_ctrl_smoke.323027254
Short name T215
Test name
Test status
Simulation time 11554798909 ps
CPU time 28.72 seconds
Started May 16 12:53:08 PM PDT 24
Finished May 16 12:53:44 PM PDT 24
Peak memory 219392 kb
Host smart-746b43f1-808c-42ab-ad54-d676ec5a8840
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=323027254 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_smoke.323027254
Directory /workspace/15.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/15.rom_ctrl_stress_all.1861322251
Short name T76
Test name
Test status
Simulation time 15533227809 ps
CPU time 43.21 seconds
Started May 16 12:53:05 PM PDT 24
Finished May 16 12:53:53 PM PDT 24
Peak memory 214360 kb
Host smart-749cca7f-fc93-40d6-baf3-8a96339a6862
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1861322251 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 15.rom_ctrl_stress_all.1861322251
Directory /workspace/15.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/15.rom_ctrl_stress_all_with_rand_reset.4100566515
Short name T17
Test name
Test status
Simulation time 39892135574 ps
CPU time 4665.16 seconds
Started May 16 12:53:09 PM PDT 24
Finished May 16 02:11:02 PM PDT 24
Peak memory 235900 kb
Host smart-9c68a478-4cc2-4e76-bf62-a220425e7b16
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4100566515 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_stress_all_with_rand_reset.4100566515
Directory /workspace/15.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/16.rom_ctrl_corrupt_sig_fatal_chk.607243357
Short name T192
Test name
Test status
Simulation time 64930337331 ps
CPU time 172.77 seconds
Started May 16 12:53:11 PM PDT 24
Finished May 16 12:56:12 PM PDT 24
Peak memory 228880 kb
Host smart-a03a6e7a-8e67-4fed-8abd-3e1ba1be5bf9
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=607243357 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_c
orrupt_sig_fatal_chk.607243357
Directory /workspace/16.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/16.rom_ctrl_kmac_err_chk.617917465
Short name T27
Test name
Test status
Simulation time 5071596609 ps
CPU time 24.37 seconds
Started May 16 12:53:09 PM PDT 24
Finished May 16 12:53:42 PM PDT 24
Peak memory 212308 kb
Host smart-222b35af-17a2-4e4b-a917-d72494e3ad4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=617917465 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_kmac_err_chk.617917465
Directory /workspace/16.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/16.rom_ctrl_max_throughput_chk.1604575302
Short name T216
Test name
Test status
Simulation time 992233749 ps
CPU time 11.56 seconds
Started May 16 12:53:07 PM PDT 24
Finished May 16 12:53:25 PM PDT 24
Peak memory 211000 kb
Host smart-373a489d-e91f-4cbf-8634-029238c08025
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1604575302 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_max_throughput_chk.1604575302
Directory /workspace/16.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/16.rom_ctrl_smoke.1182421419
Short name T329
Test name
Test status
Simulation time 9327582009 ps
CPU time 23.54 seconds
Started May 16 12:53:11 PM PDT 24
Finished May 16 12:53:43 PM PDT 24
Peak memory 219424 kb
Host smart-515075d0-5c67-4665-b4f1-65d101da9bc4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1182421419 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_smoke.1182421419
Directory /workspace/16.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/16.rom_ctrl_stress_all.3844026793
Short name T293
Test name
Test status
Simulation time 389887829 ps
CPU time 12.08 seconds
Started May 16 12:53:05 PM PDT 24
Finished May 16 12:53:21 PM PDT 24
Peak memory 219268 kb
Host smart-77d953a1-1cd8-4770-a2df-0f0e2ab1f46b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3844026793 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 16.rom_ctrl_stress_all.3844026793
Directory /workspace/16.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/17.rom_ctrl_alert_test.1140633770
Short name T327
Test name
Test status
Simulation time 1236589173 ps
CPU time 11.79 seconds
Started May 16 12:53:12 PM PDT 24
Finished May 16 12:53:32 PM PDT 24
Peak memory 211240 kb
Host smart-04f35248-a234-4adc-9823-df4a133393b2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1140633770 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_alert_test.1140633770
Directory /workspace/17.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/17.rom_ctrl_corrupt_sig_fatal_chk.425821536
Short name T206
Test name
Test status
Simulation time 19955495890 ps
CPU time 128.46 seconds
Started May 16 12:53:05 PM PDT 24
Finished May 16 12:55:19 PM PDT 24
Peak memory 229012 kb
Host smart-998cb519-633a-49f9-92dc-8f207455ef43
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=425821536 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_c
orrupt_sig_fatal_chk.425821536
Directory /workspace/17.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/17.rom_ctrl_kmac_err_chk.869877613
Short name T220
Test name
Test status
Simulation time 33587573352 ps
CPU time 32.49 seconds
Started May 16 12:53:10 PM PDT 24
Finished May 16 12:53:51 PM PDT 24
Peak memory 212216 kb
Host smart-ea0c247e-c668-425e-97e6-2dcae38eff4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=869877613 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_kmac_err_chk.869877613
Directory /workspace/17.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/17.rom_ctrl_max_throughput_chk.2467989919
Short name T282
Test name
Test status
Simulation time 7054418805 ps
CPU time 16.4 seconds
Started May 16 12:53:09 PM PDT 24
Finished May 16 12:53:32 PM PDT 24
Peak memory 211176 kb
Host smart-eb99ff6d-617e-4696-98c5-81b43440e173
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2467989919 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_max_throughput_chk.2467989919
Directory /workspace/17.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/17.rom_ctrl_smoke.1995711496
Short name T358
Test name
Test status
Simulation time 380603643 ps
CPU time 9.89 seconds
Started May 16 12:53:10 PM PDT 24
Finished May 16 12:53:29 PM PDT 24
Peak memory 213256 kb
Host smart-0148903f-3cc6-4514-9983-a359c705f63e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1995711496 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_smoke.1995711496
Directory /workspace/17.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/17.rom_ctrl_stress_all.2882748704
Short name T284
Test name
Test status
Simulation time 1029055820 ps
CPU time 23.56 seconds
Started May 16 12:53:11 PM PDT 24
Finished May 16 12:53:43 PM PDT 24
Peak memory 219264 kb
Host smart-985ad54d-5d2e-4e00-a0e2-c855df9ec2de
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2882748704 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 17.rom_ctrl_stress_all.2882748704
Directory /workspace/17.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/17.rom_ctrl_stress_all_with_rand_reset.1872412522
Short name T368
Test name
Test status
Simulation time 13432627361 ps
CPU time 513.94 seconds
Started May 16 12:53:10 PM PDT 24
Finished May 16 01:01:53 PM PDT 24
Peak memory 232792 kb
Host smart-8e27d947-e5fe-4d87-a112-51748d8ca430
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1872412522 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_stress_all_with_rand_reset.1872412522
Directory /workspace/17.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/18.rom_ctrl_alert_test.3997015237
Short name T281
Test name
Test status
Simulation time 520536562 ps
CPU time 4.16 seconds
Started May 16 12:53:08 PM PDT 24
Finished May 16 12:53:19 PM PDT 24
Peak memory 211048 kb
Host smart-df124d3a-1a79-4907-b198-0d4bd0de49cc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3997015237 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_alert_test.3997015237
Directory /workspace/18.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/18.rom_ctrl_corrupt_sig_fatal_chk.2043564214
Short name T364
Test name
Test status
Simulation time 21422923618 ps
CPU time 177.39 seconds
Started May 16 12:53:16 PM PDT 24
Finished May 16 12:56:20 PM PDT 24
Peak memory 233740 kb
Host smart-121ef5d6-0fed-44bd-b70b-0f81b59e6994
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2043564214 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_
corrupt_sig_fatal_chk.2043564214
Directory /workspace/18.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/18.rom_ctrl_kmac_err_chk.3043481790
Short name T182
Test name
Test status
Simulation time 3451818637 ps
CPU time 29.55 seconds
Started May 16 12:53:15 PM PDT 24
Finished May 16 12:53:51 PM PDT 24
Peak memory 211892 kb
Host smart-a1b0bc4f-14ac-4497-942a-ac73fac13734
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3043481790 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_kmac_err_chk.3043481790
Directory /workspace/18.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/18.rom_ctrl_max_throughput_chk.1613926988
Short name T148
Test name
Test status
Simulation time 1663108984 ps
CPU time 15.11 seconds
Started May 16 12:53:11 PM PDT 24
Finished May 16 12:53:34 PM PDT 24
Peak memory 211056 kb
Host smart-f7592c87-1d89-4f7a-a6b5-1c8d9d95205d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1613926988 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_max_throughput_chk.1613926988
Directory /workspace/18.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/18.rom_ctrl_smoke.279863664
Short name T308
Test name
Test status
Simulation time 4291139549 ps
CPU time 32.85 seconds
Started May 16 12:53:10 PM PDT 24
Finished May 16 12:53:51 PM PDT 24
Peak memory 219408 kb
Host smart-97d92518-ad39-4ddc-9d52-e8e7f492a7c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=279863664 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_smoke.279863664
Directory /workspace/18.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/18.rom_ctrl_stress_all.3424593146
Short name T261
Test name
Test status
Simulation time 5809317349 ps
CPU time 52.61 seconds
Started May 16 12:53:14 PM PDT 24
Finished May 16 12:54:14 PM PDT 24
Peak memory 216456 kb
Host smart-b062d0f7-8dd3-4178-ae98-97b019e9c968
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3424593146 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 18.rom_ctrl_stress_all.3424593146
Directory /workspace/18.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/19.rom_ctrl_alert_test.2499772760
Short name T259
Test name
Test status
Simulation time 24248561262 ps
CPU time 16.46 seconds
Started May 16 12:53:10 PM PDT 24
Finished May 16 12:53:35 PM PDT 24
Peak memory 211328 kb
Host smart-55e04690-5ba8-403b-b184-5e2b5bc900f1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2499772760 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_alert_test.2499772760
Directory /workspace/19.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/19.rom_ctrl_corrupt_sig_fatal_chk.1052395364
Short name T23
Test name
Test status
Simulation time 96458114960 ps
CPU time 251.43 seconds
Started May 16 12:53:09 PM PDT 24
Finished May 16 12:57:29 PM PDT 24
Peak memory 237908 kb
Host smart-9e7155a5-3ccb-49e0-bcbf-278c534e6ffb
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1052395364 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_
corrupt_sig_fatal_chk.1052395364
Directory /workspace/19.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/19.rom_ctrl_kmac_err_chk.475338392
Short name T232
Test name
Test status
Simulation time 168682982 ps
CPU time 9.64 seconds
Started May 16 12:53:10 PM PDT 24
Finished May 16 12:53:28 PM PDT 24
Peak memory 211724 kb
Host smart-9dd4020a-f108-47be-90c7-f29f70f02acb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=475338392 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_kmac_err_chk.475338392
Directory /workspace/19.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/19.rom_ctrl_max_throughput_chk.1239050864
Short name T132
Test name
Test status
Simulation time 4168119506 ps
CPU time 15.99 seconds
Started May 16 12:53:07 PM PDT 24
Finished May 16 12:53:29 PM PDT 24
Peak memory 211112 kb
Host smart-fec0bb26-2d2b-4ff8-9d69-24f8ea6136ba
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1239050864 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_max_throughput_chk.1239050864
Directory /workspace/19.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/19.rom_ctrl_smoke.2349530474
Short name T186
Test name
Test status
Simulation time 2926502869 ps
CPU time 26.95 seconds
Started May 16 12:53:08 PM PDT 24
Finished May 16 12:53:42 PM PDT 24
Peak memory 213292 kb
Host smart-a8112a57-f540-495c-af3e-906863803685
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2349530474 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_smoke.2349530474
Directory /workspace/19.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/19.rom_ctrl_stress_all.2195382606
Short name T250
Test name
Test status
Simulation time 24500432867 ps
CPU time 66.83 seconds
Started May 16 12:53:08 PM PDT 24
Finished May 16 12:54:20 PM PDT 24
Peak memory 219380 kb
Host smart-68747239-3563-436e-8719-ed89b238ec0e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2195382606 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 19.rom_ctrl_stress_all.2195382606
Directory /workspace/19.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/2.rom_ctrl_alert_test.4151554439
Short name T179
Test name
Test status
Simulation time 9623859012 ps
CPU time 8.51 seconds
Started May 16 12:52:52 PM PDT 24
Finished May 16 12:53:11 PM PDT 24
Peak memory 211344 kb
Host smart-3303de31-2bb9-4fd9-ae0b-653b4ae4afe7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4151554439 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_alert_test.4151554439
Directory /workspace/2.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/2.rom_ctrl_corrupt_sig_fatal_chk.4210847203
Short name T187
Test name
Test status
Simulation time 11485961411 ps
CPU time 98.89 seconds
Started May 16 12:52:51 PM PDT 24
Finished May 16 12:54:41 PM PDT 24
Peak memory 224744 kb
Host smart-e7ff0b2d-de69-486d-a197-35e5da95aa9a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4210847203 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_c
orrupt_sig_fatal_chk.4210847203
Directory /workspace/2.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/2.rom_ctrl_kmac_err_chk.2539068754
Short name T20
Test name
Test status
Simulation time 168466727 ps
CPU time 9.56 seconds
Started May 16 12:52:53 PM PDT 24
Finished May 16 12:53:12 PM PDT 24
Peak memory 211880 kb
Host smart-305eeaa6-657e-42f2-b5f0-fe5503ee6456
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2539068754 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_kmac_err_chk.2539068754
Directory /workspace/2.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/2.rom_ctrl_max_throughput_chk.2245372981
Short name T16
Test name
Test status
Simulation time 383509935 ps
CPU time 5.5 seconds
Started May 16 12:52:53 PM PDT 24
Finished May 16 12:53:09 PM PDT 24
Peak memory 211040 kb
Host smart-34376d04-e2d3-4220-954c-c17f66cbae05
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2245372981 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_max_throughput_chk.2245372981
Directory /workspace/2.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/2.rom_ctrl_sec_cm.678928535
Short name T33
Test name
Test status
Simulation time 2222732927 ps
CPU time 57.78 seconds
Started May 16 12:52:51 PM PDT 24
Finished May 16 12:54:00 PM PDT 24
Peak memory 233648 kb
Host smart-e5c5f8db-27b8-46c0-924d-42a8e986a799
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=678928535 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_sec_cm.678928535
Directory /workspace/2.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/2.rom_ctrl_smoke.3819155814
Short name T312
Test name
Test status
Simulation time 189773096 ps
CPU time 10.3 seconds
Started May 16 12:52:51 PM PDT 24
Finished May 16 12:53:12 PM PDT 24
Peak memory 213440 kb
Host smart-0c65a7c4-3657-41d3-859d-880f109feb7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3819155814 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_smoke.3819155814
Directory /workspace/2.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/2.rom_ctrl_stress_all.4026315258
Short name T181
Test name
Test status
Simulation time 2125904366 ps
CPU time 16.94 seconds
Started May 16 12:52:55 PM PDT 24
Finished May 16 12:53:21 PM PDT 24
Peak memory 211948 kb
Host smart-8c9ca162-d4ac-424a-82dd-25b510908ea0
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4026315258 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 2.rom_ctrl_stress_all.4026315258
Directory /workspace/2.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/20.rom_ctrl_alert_test.2465522000
Short name T279
Test name
Test status
Simulation time 213624730 ps
CPU time 5.81 seconds
Started May 16 12:53:09 PM PDT 24
Finished May 16 12:53:23 PM PDT 24
Peak memory 211192 kb
Host smart-a7f16dc7-3a9c-4c8f-9784-ddb70e07794c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2465522000 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_alert_test.2465522000
Directory /workspace/20.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/20.rom_ctrl_corrupt_sig_fatal_chk.2366343579
Short name T28
Test name
Test status
Simulation time 62892395894 ps
CPU time 173.35 seconds
Started May 16 12:53:15 PM PDT 24
Finished May 16 12:56:15 PM PDT 24
Peak memory 232900 kb
Host smart-bad47a4b-f9c8-426a-a5c7-9f90d27a0368
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2366343579 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_
corrupt_sig_fatal_chk.2366343579
Directory /workspace/20.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/20.rom_ctrl_kmac_err_chk.1992793729
Short name T129
Test name
Test status
Simulation time 2119582101 ps
CPU time 21.77 seconds
Started May 16 12:53:09 PM PDT 24
Finished May 16 12:53:38 PM PDT 24
Peak memory 211616 kb
Host smart-cfa9f84a-4466-4d77-a65b-47e904fb8327
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1992793729 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_kmac_err_chk.1992793729
Directory /workspace/20.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/20.rom_ctrl_max_throughput_chk.851009972
Short name T126
Test name
Test status
Simulation time 429340739 ps
CPU time 5.83 seconds
Started May 16 12:53:10 PM PDT 24
Finished May 16 12:53:24 PM PDT 24
Peak memory 211072 kb
Host smart-eb932a3f-9f4d-4ca1-8be5-8775383b84f8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=851009972 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_max_throughput_chk.851009972
Directory /workspace/20.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/20.rom_ctrl_smoke.4072377939
Short name T40
Test name
Test status
Simulation time 12630664835 ps
CPU time 23.2 seconds
Started May 16 12:53:09 PM PDT 24
Finished May 16 12:53:41 PM PDT 24
Peak memory 214060 kb
Host smart-7db29cda-427f-4a6f-a1eb-a62d2ff43872
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4072377939 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_smoke.4072377939
Directory /workspace/20.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/20.rom_ctrl_stress_all.2892643568
Short name T189
Test name
Test status
Simulation time 108403160 ps
CPU time 7.1 seconds
Started May 16 12:53:10 PM PDT 24
Finished May 16 12:53:26 PM PDT 24
Peak memory 210992 kb
Host smart-3c31f131-abdc-493f-aebe-ee6e084463a2
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2892643568 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 20.rom_ctrl_stress_all.2892643568
Directory /workspace/20.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/21.rom_ctrl_alert_test.3025704945
Short name T217
Test name
Test status
Simulation time 1857101801 ps
CPU time 15 seconds
Started May 16 12:53:13 PM PDT 24
Finished May 16 12:53:36 PM PDT 24
Peak memory 211196 kb
Host smart-e383ad1f-13b0-447d-afa1-10275be76942
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3025704945 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_alert_test.3025704945
Directory /workspace/21.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/21.rom_ctrl_corrupt_sig_fatal_chk.1856809396
Short name T230
Test name
Test status
Simulation time 7755314675 ps
CPU time 152.84 seconds
Started May 16 12:53:13 PM PDT 24
Finished May 16 12:55:54 PM PDT 24
Peak memory 228816 kb
Host smart-b1188d18-a5a7-4d04-b639-22c22145a217
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1856809396 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_
corrupt_sig_fatal_chk.1856809396
Directory /workspace/21.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/21.rom_ctrl_kmac_err_chk.1525930023
Short name T160
Test name
Test status
Simulation time 1201111921 ps
CPU time 13.1 seconds
Started May 16 12:53:14 PM PDT 24
Finished May 16 12:53:35 PM PDT 24
Peak memory 211784 kb
Host smart-42324f1f-ca12-49c6-a68b-ee49ef1e926c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1525930023 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_kmac_err_chk.1525930023
Directory /workspace/21.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/21.rom_ctrl_max_throughput_chk.860462316
Short name T365
Test name
Test status
Simulation time 788148220 ps
CPU time 10.12 seconds
Started May 16 12:53:09 PM PDT 24
Finished May 16 12:53:28 PM PDT 24
Peak memory 210940 kb
Host smart-335f4139-8d5a-4c62-b861-e3aa4d371fd2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=860462316 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_max_throughput_chk.860462316
Directory /workspace/21.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/21.rom_ctrl_smoke.2992823416
Short name T262
Test name
Test status
Simulation time 758377058 ps
CPU time 10.13 seconds
Started May 16 12:53:09 PM PDT 24
Finished May 16 12:53:26 PM PDT 24
Peak memory 219172 kb
Host smart-35e4f6a6-9b71-4834-b5a4-ba3f00bb55ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2992823416 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_smoke.2992823416
Directory /workspace/21.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/21.rom_ctrl_stress_all.2540802380
Short name T249
Test name
Test status
Simulation time 10360167328 ps
CPU time 54.43 seconds
Started May 16 12:53:07 PM PDT 24
Finished May 16 12:54:07 PM PDT 24
Peak memory 219464 kb
Host smart-889c39c2-4148-458a-b489-314414d55ca7
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2540802380 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 21.rom_ctrl_stress_all.2540802380
Directory /workspace/21.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/22.rom_ctrl_alert_test.1660228872
Short name T269
Test name
Test status
Simulation time 6662738619 ps
CPU time 14.19 seconds
Started May 16 12:53:12 PM PDT 24
Finished May 16 12:53:34 PM PDT 24
Peak memory 211320 kb
Host smart-6b915327-10ed-4b4e-b00b-473bb2b3ab2f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1660228872 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_alert_test.1660228872
Directory /workspace/22.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/22.rom_ctrl_corrupt_sig_fatal_chk.604023491
Short name T299
Test name
Test status
Simulation time 14988859336 ps
CPU time 210.51 seconds
Started May 16 12:53:12 PM PDT 24
Finished May 16 12:56:51 PM PDT 24
Peak memory 237840 kb
Host smart-0d8d2ae4-df14-4bad-9281-592754677c09
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=604023491 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_c
orrupt_sig_fatal_chk.604023491
Directory /workspace/22.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/22.rom_ctrl_kmac_err_chk.4186093802
Short name T253
Test name
Test status
Simulation time 9906428274 ps
CPU time 23.8 seconds
Started May 16 12:53:00 PM PDT 24
Finished May 16 12:53:31 PM PDT 24
Peak memory 212396 kb
Host smart-bbdccd3f-3d08-469c-97e5-97c87c7ab2f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4186093802 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_kmac_err_chk.4186093802
Directory /workspace/22.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/22.rom_ctrl_max_throughput_chk.3639794751
Short name T247
Test name
Test status
Simulation time 100077458 ps
CPU time 5.42 seconds
Started May 16 12:53:13 PM PDT 24
Finished May 16 12:53:27 PM PDT 24
Peak memory 211036 kb
Host smart-6ad9c745-ddc1-452a-a8e5-0517198f3c54
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3639794751 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_max_throughput_chk.3639794751
Directory /workspace/22.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/22.rom_ctrl_smoke.3300396635
Short name T162
Test name
Test status
Simulation time 3001963191 ps
CPU time 29.5 seconds
Started May 16 12:53:16 PM PDT 24
Finished May 16 12:53:52 PM PDT 24
Peak memory 219348 kb
Host smart-50f8aaa6-a623-4194-9277-6bcb5fbc12cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3300396635 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_smoke.3300396635
Directory /workspace/22.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/22.rom_ctrl_stress_all.1390754741
Short name T260
Test name
Test status
Simulation time 2050622571 ps
CPU time 19.25 seconds
Started May 16 12:53:09 PM PDT 24
Finished May 16 12:53:37 PM PDT 24
Peak memory 210992 kb
Host smart-c4c12437-b01a-4234-949a-a97bac090414
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1390754741 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 22.rom_ctrl_stress_all.1390754741
Directory /workspace/22.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/22.rom_ctrl_stress_all_with_rand_reset.2645595614
Short name T352
Test name
Test status
Simulation time 347632528463 ps
CPU time 1082.35 seconds
Started May 16 12:53:08 PM PDT 24
Finished May 16 01:11:18 PM PDT 24
Peak memory 231800 kb
Host smart-4465d859-2a70-4c57-8ee9-ef937e969e74
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2645595614 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_stress_all_with_rand_reset.2645595614
Directory /workspace/22.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/23.rom_ctrl_alert_test.505123510
Short name T42
Test name
Test status
Simulation time 369639310 ps
CPU time 6.86 seconds
Started May 16 12:53:28 PM PDT 24
Finished May 16 12:53:48 PM PDT 24
Peak memory 211200 kb
Host smart-5f1011b7-98c3-4398-8a5b-05f266283c37
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=505123510 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_alert_test.505123510
Directory /workspace/23.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/23.rom_ctrl_corrupt_sig_fatal_chk.3120051518
Short name T336
Test name
Test status
Simulation time 7527626612 ps
CPU time 114.88 seconds
Started May 16 12:53:28 PM PDT 24
Finished May 16 12:55:36 PM PDT 24
Peak memory 237908 kb
Host smart-bdca68af-b42f-45f1-a0b9-0e6f67bd370a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3120051518 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_
corrupt_sig_fatal_chk.3120051518
Directory /workspace/23.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/23.rom_ctrl_kmac_err_chk.1597675475
Short name T353
Test name
Test status
Simulation time 2548132257 ps
CPU time 24.35 seconds
Started May 16 12:53:28 PM PDT 24
Finished May 16 12:54:06 PM PDT 24
Peak memory 212064 kb
Host smart-b76a6069-f2c7-40a2-9baf-944122ca606a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1597675475 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_kmac_err_chk.1597675475
Directory /workspace/23.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/23.rom_ctrl_max_throughput_chk.2395474799
Short name T154
Test name
Test status
Simulation time 94695253 ps
CPU time 5.08 seconds
Started May 16 12:53:30 PM PDT 24
Finished May 16 12:53:51 PM PDT 24
Peak memory 211068 kb
Host smart-5bbf94b1-aacb-4d06-b04f-fa62a332b5bd
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2395474799 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_max_throughput_chk.2395474799
Directory /workspace/23.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/23.rom_ctrl_smoke.2855548513
Short name T221
Test name
Test status
Simulation time 14107425429 ps
CPU time 32.69 seconds
Started May 16 12:53:08 PM PDT 24
Finished May 16 12:53:47 PM PDT 24
Peak memory 219412 kb
Host smart-89a60641-a56c-4f2c-928f-1f31cd6cce33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2855548513 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_smoke.2855548513
Directory /workspace/23.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/23.rom_ctrl_stress_all.465343761
Short name T224
Test name
Test status
Simulation time 12133656848 ps
CPU time 57.1 seconds
Started May 16 12:53:34 PM PDT 24
Finished May 16 12:54:49 PM PDT 24
Peak memory 217044 kb
Host smart-4ec1c7db-bd46-4271-a942-3ab8a6ef2e78
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=465343761 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 23.rom_ctrl_stress_all.465343761
Directory /workspace/23.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/24.rom_ctrl_alert_test.3183383005
Short name T164
Test name
Test status
Simulation time 525527745 ps
CPU time 7.24 seconds
Started May 16 12:53:25 PM PDT 24
Finished May 16 12:53:38 PM PDT 24
Peak memory 211200 kb
Host smart-c2e87777-c58b-4a23-bd6f-eb3f056f8a26
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3183383005 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_alert_test.3183383005
Directory /workspace/24.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/24.rom_ctrl_corrupt_sig_fatal_chk.374924633
Short name T337
Test name
Test status
Simulation time 45986286532 ps
CPU time 224.5 seconds
Started May 16 12:53:25 PM PDT 24
Finished May 16 12:57:16 PM PDT 24
Peak memory 224844 kb
Host smart-16861c76-82bc-4b66-8a4f-3342392f1b30
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=374924633 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_c
orrupt_sig_fatal_chk.374924633
Directory /workspace/24.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/24.rom_ctrl_kmac_err_chk.3889439111
Short name T127
Test name
Test status
Simulation time 881114956 ps
CPU time 15.08 seconds
Started May 16 12:53:26 PM PDT 24
Finished May 16 12:53:50 PM PDT 24
Peak memory 211872 kb
Host smart-81021007-9a52-4da1-a4c3-5390aac84d03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3889439111 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_kmac_err_chk.3889439111
Directory /workspace/24.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/24.rom_ctrl_max_throughput_chk.1384955392
Short name T251
Test name
Test status
Simulation time 715383637 ps
CPU time 9.79 seconds
Started May 16 12:53:31 PM PDT 24
Finished May 16 12:53:56 PM PDT 24
Peak memory 211056 kb
Host smart-b3917e90-eb31-4e82-b50d-14d1efffc63c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1384955392 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_max_throughput_chk.1384955392
Directory /workspace/24.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/24.rom_ctrl_smoke.90871526
Short name T134
Test name
Test status
Simulation time 2921984637 ps
CPU time 26.4 seconds
Started May 16 12:53:29 PM PDT 24
Finished May 16 12:54:11 PM PDT 24
Peak memory 213628 kb
Host smart-f6eeb211-eac4-4a17-8800-f32227874992
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=90871526 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_smoke.90871526
Directory /workspace/24.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/24.rom_ctrl_stress_all.4056425058
Short name T292
Test name
Test status
Simulation time 27809318262 ps
CPU time 78.93 seconds
Started May 16 12:53:26 PM PDT 24
Finished May 16 12:54:54 PM PDT 24
Peak memory 219360 kb
Host smart-1efa8871-a803-45f0-bf31-78642de16fa6
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4056425058 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 24.rom_ctrl_stress_all.4056425058
Directory /workspace/24.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/25.rom_ctrl_alert_test.1895189358
Short name T161
Test name
Test status
Simulation time 906151466 ps
CPU time 7.02 seconds
Started May 16 12:53:29 PM PDT 24
Finished May 16 12:53:52 PM PDT 24
Peak memory 211236 kb
Host smart-f564b6a7-1a6c-4659-ab72-8c6fbc35ac96
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1895189358 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_alert_test.1895189358
Directory /workspace/25.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/25.rom_ctrl_corrupt_sig_fatal_chk.3448371407
Short name T188
Test name
Test status
Simulation time 1292367136 ps
CPU time 80.45 seconds
Started May 16 12:53:31 PM PDT 24
Finished May 16 12:55:08 PM PDT 24
Peak memory 237852 kb
Host smart-baf26519-592e-4048-889e-0589d1e38d89
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3448371407 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_
corrupt_sig_fatal_chk.3448371407
Directory /workspace/25.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/25.rom_ctrl_kmac_err_chk.154697651
Short name T146
Test name
Test status
Simulation time 1373610680 ps
CPU time 14.09 seconds
Started May 16 12:53:29 PM PDT 24
Finished May 16 12:53:59 PM PDT 24
Peak memory 211888 kb
Host smart-96ee421e-342d-4276-8ea4-e34086d777f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=154697651 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_kmac_err_chk.154697651
Directory /workspace/25.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/25.rom_ctrl_max_throughput_chk.1239412783
Short name T369
Test name
Test status
Simulation time 379421483 ps
CPU time 5.5 seconds
Started May 16 12:53:27 PM PDT 24
Finished May 16 12:53:46 PM PDT 24
Peak memory 211044 kb
Host smart-86505d97-e5bd-4bc6-bd1f-4e45e89c5322
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1239412783 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_max_throughput_chk.1239412783
Directory /workspace/25.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/25.rom_ctrl_smoke.2001035751
Short name T367
Test name
Test status
Simulation time 1604889290 ps
CPU time 10.22 seconds
Started May 16 12:53:28 PM PDT 24
Finished May 16 12:53:53 PM PDT 24
Peak memory 213808 kb
Host smart-065848b3-1323-4d75-a2a6-fd08bf9ea6ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2001035751 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_smoke.2001035751
Directory /workspace/25.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/25.rom_ctrl_stress_all.2128348382
Short name T257
Test name
Test status
Simulation time 10043888828 ps
CPU time 42.05 seconds
Started May 16 12:53:28 PM PDT 24
Finished May 16 12:54:24 PM PDT 24
Peak memory 219356 kb
Host smart-0034b270-9c51-43ce-9736-6b0a5c1d36be
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2128348382 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 25.rom_ctrl_stress_all.2128348382
Directory /workspace/25.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/26.rom_ctrl_alert_test.717946574
Short name T63
Test name
Test status
Simulation time 7839325878 ps
CPU time 12.7 seconds
Started May 16 12:53:24 PM PDT 24
Finished May 16 12:53:41 PM PDT 24
Peak memory 211328 kb
Host smart-8c764a01-7b60-49b2-97b5-65a2013198aa
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=717946574 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_alert_test.717946574
Directory /workspace/26.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/26.rom_ctrl_corrupt_sig_fatal_chk.4146793209
Short name T184
Test name
Test status
Simulation time 209171796821 ps
CPU time 228.8 seconds
Started May 16 12:53:30 PM PDT 24
Finished May 16 12:57:35 PM PDT 24
Peak memory 230988 kb
Host smart-b325785f-1bf8-4d1b-9a71-52d3e1d56e76
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4146793209 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_
corrupt_sig_fatal_chk.4146793209
Directory /workspace/26.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/26.rom_ctrl_kmac_err_chk.2865894519
Short name T255
Test name
Test status
Simulation time 1036941847 ps
CPU time 11.01 seconds
Started May 16 12:53:27 PM PDT 24
Finished May 16 12:53:51 PM PDT 24
Peak memory 211752 kb
Host smart-8e3899d0-d202-4941-b14c-d96a6e0f697f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2865894519 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_kmac_err_chk.2865894519
Directory /workspace/26.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/26.rom_ctrl_max_throughput_chk.126432172
Short name T223
Test name
Test status
Simulation time 7609818260 ps
CPU time 13.22 seconds
Started May 16 12:53:28 PM PDT 24
Finished May 16 12:53:54 PM PDT 24
Peak memory 211196 kb
Host smart-5dce85a6-f37d-415c-b46d-a622c28eed75
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=126432172 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_max_throughput_chk.126432172
Directory /workspace/26.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/26.rom_ctrl_smoke.4126264382
Short name T202
Test name
Test status
Simulation time 182481208 ps
CPU time 10.25 seconds
Started May 16 12:53:26 PM PDT 24
Finished May 16 12:53:45 PM PDT 24
Peak memory 219280 kb
Host smart-894a510c-6415-4ffe-8070-37b85adae78d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4126264382 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_smoke.4126264382
Directory /workspace/26.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/26.rom_ctrl_stress_all.2851944231
Short name T55
Test name
Test status
Simulation time 698380262 ps
CPU time 14.6 seconds
Started May 16 12:53:27 PM PDT 24
Finished May 16 12:53:53 PM PDT 24
Peak memory 219280 kb
Host smart-e46715ae-4828-41a4-a987-cc6c6fd3de08
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2851944231 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 26.rom_ctrl_stress_all.2851944231
Directory /workspace/26.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/27.rom_ctrl_alert_test.4178409113
Short name T347
Test name
Test status
Simulation time 7300529559 ps
CPU time 14.55 seconds
Started May 16 12:53:27 PM PDT 24
Finished May 16 12:53:55 PM PDT 24
Peak memory 211360 kb
Host smart-f816c343-17b4-4d0f-bc37-7ce0a01e477e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4178409113 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_alert_test.4178409113
Directory /workspace/27.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/27.rom_ctrl_corrupt_sig_fatal_chk.883370332
Short name T268
Test name
Test status
Simulation time 142386265038 ps
CPU time 365.21 seconds
Started May 16 12:53:25 PM PDT 24
Finished May 16 12:59:37 PM PDT 24
Peak memory 219624 kb
Host smart-bc558cab-5871-43b3-a90d-cdbc6a225647
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=883370332 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_c
orrupt_sig_fatal_chk.883370332
Directory /workspace/27.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/27.rom_ctrl_kmac_err_chk.3097647599
Short name T294
Test name
Test status
Simulation time 9889978654 ps
CPU time 26.74 seconds
Started May 16 12:53:25 PM PDT 24
Finished May 16 12:54:00 PM PDT 24
Peak memory 212348 kb
Host smart-a3935728-310c-4118-ae00-502c65918c40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3097647599 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_kmac_err_chk.3097647599
Directory /workspace/27.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/27.rom_ctrl_max_throughput_chk.2284876166
Short name T145
Test name
Test status
Simulation time 1151682909 ps
CPU time 11.3 seconds
Started May 16 12:53:27 PM PDT 24
Finished May 16 12:53:51 PM PDT 24
Peak memory 211060 kb
Host smart-648c8c3e-4449-4cea-938c-431576a870ae
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2284876166 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_max_throughput_chk.2284876166
Directory /workspace/27.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/27.rom_ctrl_smoke.853834734
Short name T78
Test name
Test status
Simulation time 7896141384 ps
CPU time 25.12 seconds
Started May 16 12:53:30 PM PDT 24
Finished May 16 12:54:11 PM PDT 24
Peak memory 219452 kb
Host smart-51967bad-7ae7-4cd8-81cb-1b79da3ac5d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=853834734 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_smoke.853834734
Directory /workspace/27.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/27.rom_ctrl_stress_all.1974805265
Short name T266
Test name
Test status
Simulation time 1398937410 ps
CPU time 32.07 seconds
Started May 16 12:53:26 PM PDT 24
Finished May 16 12:54:07 PM PDT 24
Peak memory 219312 kb
Host smart-6ec202d3-8a80-466a-b131-a52eadcaebee
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1974805265 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 27.rom_ctrl_stress_all.1974805265
Directory /workspace/27.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/28.rom_ctrl_alert_test.1474747001
Short name T175
Test name
Test status
Simulation time 969504946 ps
CPU time 9.94 seconds
Started May 16 12:53:27 PM PDT 24
Finished May 16 12:53:48 PM PDT 24
Peak memory 211212 kb
Host smart-694401e7-5429-45bf-a54d-8ab7c2392a13
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1474747001 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_alert_test.1474747001
Directory /workspace/28.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/28.rom_ctrl_corrupt_sig_fatal_chk.3427710292
Short name T280
Test name
Test status
Simulation time 7558369426 ps
CPU time 125.56 seconds
Started May 16 12:53:28 PM PDT 24
Finished May 16 12:55:46 PM PDT 24
Peak memory 230324 kb
Host smart-a6fce399-04ed-41f6-abb4-ce2848661cdb
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3427710292 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_
corrupt_sig_fatal_chk.3427710292
Directory /workspace/28.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/28.rom_ctrl_kmac_err_chk.6194263
Short name T343
Test name
Test status
Simulation time 8825428630 ps
CPU time 17.56 seconds
Started May 16 12:53:31 PM PDT 24
Finished May 16 12:54:05 PM PDT 24
Peak memory 212076 kb
Host smart-123c0775-b23f-47e7-8664-d2c94c57aa9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=6194263 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_kmac_err_chk.6194263
Directory /workspace/28.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/28.rom_ctrl_max_throughput_chk.141918615
Short name T285
Test name
Test status
Simulation time 1928029389 ps
CPU time 16.48 seconds
Started May 16 12:53:28 PM PDT 24
Finished May 16 12:53:59 PM PDT 24
Peak memory 211036 kb
Host smart-460c6f7a-0ddf-4010-8666-13aa30825005
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=141918615 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_max_throughput_chk.141918615
Directory /workspace/28.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/28.rom_ctrl_smoke.2098723053
Short name T177
Test name
Test status
Simulation time 347877805 ps
CPU time 12.61 seconds
Started May 16 12:53:26 PM PDT 24
Finished May 16 12:53:49 PM PDT 24
Peak memory 219320 kb
Host smart-2bfded10-026c-480d-b8d7-58b8706ec506
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2098723053 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_smoke.2098723053
Directory /workspace/28.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/28.rom_ctrl_stress_all.4146376006
Short name T41
Test name
Test status
Simulation time 15570692725 ps
CPU time 69.01 seconds
Started May 16 12:53:29 PM PDT 24
Finished May 16 12:54:52 PM PDT 24
Peak memory 219356 kb
Host smart-bcfaac37-226e-42a8-8d0e-b0aa4cc997f3
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4146376006 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 28.rom_ctrl_stress_all.4146376006
Directory /workspace/28.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/29.rom_ctrl_alert_test.569945650
Short name T6
Test name
Test status
Simulation time 212874598 ps
CPU time 5.9 seconds
Started May 16 12:53:27 PM PDT 24
Finished May 16 12:53:45 PM PDT 24
Peak memory 211200 kb
Host smart-7a07ac08-0e38-4113-80c2-58624fc776a5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=569945650 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_alert_test.569945650
Directory /workspace/29.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/29.rom_ctrl_corrupt_sig_fatal_chk.1827041767
Short name T152
Test name
Test status
Simulation time 8254687166 ps
CPU time 85.25 seconds
Started May 16 12:53:26 PM PDT 24
Finished May 16 12:55:02 PM PDT 24
Peak memory 228604 kb
Host smart-3d08a6f1-4aa1-416c-a711-c01404d2a9b6
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1827041767 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_
corrupt_sig_fatal_chk.1827041767
Directory /workspace/29.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/29.rom_ctrl_kmac_err_chk.2870772250
Short name T218
Test name
Test status
Simulation time 5905262134 ps
CPU time 18.62 seconds
Started May 16 12:53:30 PM PDT 24
Finished May 16 12:54:04 PM PDT 24
Peak memory 212472 kb
Host smart-fb5e2908-859e-4964-bb62-cc5308a16fa5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2870772250 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_kmac_err_chk.2870772250
Directory /workspace/29.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/29.rom_ctrl_max_throughput_chk.1100205486
Short name T289
Test name
Test status
Simulation time 8052197424 ps
CPU time 16.24 seconds
Started May 16 12:53:27 PM PDT 24
Finished May 16 12:53:55 PM PDT 24
Peak memory 211164 kb
Host smart-8481b416-48ca-4bde-b5d1-0ed714c5427f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1100205486 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_max_throughput_chk.1100205486
Directory /workspace/29.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/29.rom_ctrl_stress_all.1130444996
Short name T153
Test name
Test status
Simulation time 6970724155 ps
CPU time 37.84 seconds
Started May 16 12:53:25 PM PDT 24
Finished May 16 12:54:12 PM PDT 24
Peak memory 213920 kb
Host smart-14b3d39d-03ed-4785-a086-667c1017e219
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1130444996 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 29.rom_ctrl_stress_all.1130444996
Directory /workspace/29.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/3.rom_ctrl_alert_test.1682843009
Short name T149
Test name
Test status
Simulation time 7471932408 ps
CPU time 15.45 seconds
Started May 16 12:52:50 PM PDT 24
Finished May 16 12:53:17 PM PDT 24
Peak memory 211268 kb
Host smart-f9d6f904-425b-4cb7-8bd9-222be9d75291
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1682843009 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_alert_test.1682843009
Directory /workspace/3.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/3.rom_ctrl_corrupt_sig_fatal_chk.399573107
Short name T199
Test name
Test status
Simulation time 21352910436 ps
CPU time 257.79 seconds
Started May 16 12:52:54 PM PDT 24
Finished May 16 12:57:22 PM PDT 24
Peak memory 218600 kb
Host smart-4dc1b14d-2f83-45bd-94d4-797e7bc6a3cd
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=399573107 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_co
rrupt_sig_fatal_chk.399573107
Directory /workspace/3.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/3.rom_ctrl_kmac_err_chk.1049911094
Short name T324
Test name
Test status
Simulation time 17432244441 ps
CPU time 33.77 seconds
Started May 16 12:52:52 PM PDT 24
Finished May 16 12:53:36 PM PDT 24
Peak memory 212256 kb
Host smart-f618c155-7a8c-4ac5-bc0e-536c36c346bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1049911094 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_kmac_err_chk.1049911094
Directory /workspace/3.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/3.rom_ctrl_max_throughput_chk.1795829776
Short name T286
Test name
Test status
Simulation time 2941263616 ps
CPU time 10.12 seconds
Started May 16 12:52:54 PM PDT 24
Finished May 16 12:53:14 PM PDT 24
Peak memory 211156 kb
Host smart-cd3c28e4-ba2f-4b0f-86ee-1b38dc0f73b1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1795829776 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_max_throughput_chk.1795829776
Directory /workspace/3.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/3.rom_ctrl_sec_cm.1939597609
Short name T34
Test name
Test status
Simulation time 2123051319 ps
CPU time 63.92 seconds
Started May 16 12:52:50 PM PDT 24
Finished May 16 12:54:05 PM PDT 24
Peak memory 230104 kb
Host smart-9f1225f1-d2d6-4045-ab11-bdf4bd5d8539
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1939597609 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_sec_cm.1939597609
Directory /workspace/3.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/3.rom_ctrl_smoke.2367104868
Short name T326
Test name
Test status
Simulation time 179494487 ps
CPU time 10.32 seconds
Started May 16 12:52:55 PM PDT 24
Finished May 16 12:53:15 PM PDT 24
Peak memory 219336 kb
Host smart-4dc56d0c-157b-4530-99aa-486384275e7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2367104868 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_smoke.2367104868
Directory /workspace/3.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/3.rom_ctrl_stress_all.2804413422
Short name T38
Test name
Test status
Simulation time 12674846038 ps
CPU time 65.15 seconds
Started May 16 12:52:53 PM PDT 24
Finished May 16 12:54:08 PM PDT 24
Peak memory 214444 kb
Host smart-9c4c546d-c414-46a4-95e6-c1b0c0a795b0
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2804413422 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 3.rom_ctrl_stress_all.2804413422
Directory /workspace/3.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/3.rom_ctrl_stress_all_with_rand_reset.358521002
Short name T350
Test name
Test status
Simulation time 610183389723 ps
CPU time 1757.36 seconds
Started May 16 12:52:52 PM PDT 24
Finished May 16 01:22:20 PM PDT 24
Peak memory 235644 kb
Host smart-17a2f0bd-456a-4f56-9733-9a6e209849bc
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=358521002 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_stress_all_with_rand_reset.358521002
Directory /workspace/3.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.rom_ctrl_alert_test.1607331487
Short name T166
Test name
Test status
Simulation time 3291217701 ps
CPU time 9.19 seconds
Started May 16 12:53:29 PM PDT 24
Finished May 16 12:53:53 PM PDT 24
Peak memory 211316 kb
Host smart-95cf6719-67f3-4fae-8551-40d938a5d250
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1607331487 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_alert_test.1607331487
Directory /workspace/30.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/30.rom_ctrl_corrupt_sig_fatal_chk.3774679568
Short name T203
Test name
Test status
Simulation time 1225616202 ps
CPU time 81.39 seconds
Started May 16 12:53:26 PM PDT 24
Finished May 16 12:54:56 PM PDT 24
Peak memory 228400 kb
Host smart-f560bd6f-346d-4b57-b3a7-4da13da4b085
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3774679568 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_
corrupt_sig_fatal_chk.3774679568
Directory /workspace/30.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/30.rom_ctrl_kmac_err_chk.24475168
Short name T150
Test name
Test status
Simulation time 13367228086 ps
CPU time 32.58 seconds
Started May 16 12:53:27 PM PDT 24
Finished May 16 12:54:11 PM PDT 24
Peak memory 212164 kb
Host smart-92cefd97-7bcb-457d-a467-b3be6f12ea7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=24475168 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_kmac_err_chk.24475168
Directory /workspace/30.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/30.rom_ctrl_max_throughput_chk.1617754950
Short name T273
Test name
Test status
Simulation time 950869927 ps
CPU time 10.85 seconds
Started May 16 12:53:25 PM PDT 24
Finished May 16 12:53:41 PM PDT 24
Peak memory 211000 kb
Host smart-cb9d123b-3cca-46f0-812a-5863fc69b887
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1617754950 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_max_throughput_chk.1617754950
Directory /workspace/30.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/30.rom_ctrl_smoke.2215529
Short name T13
Test name
Test status
Simulation time 4062891257 ps
CPU time 28.58 seconds
Started May 16 12:53:25 PM PDT 24
Finished May 16 12:53:58 PM PDT 24
Peak memory 213648 kb
Host smart-2c9f9d28-69bb-4c44-9ff0-76f6b44dca62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2215529 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_smoke.2215529
Directory /workspace/30.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/30.rom_ctrl_stress_all.1683821792
Short name T185
Test name
Test status
Simulation time 11506558089 ps
CPU time 35.2 seconds
Started May 16 12:53:27 PM PDT 24
Finished May 16 12:54:14 PM PDT 24
Peak memory 213824 kb
Host smart-e24f485d-f7fd-45c1-8f5a-5a626fe4c763
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1683821792 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 30.rom_ctrl_stress_all.1683821792
Directory /workspace/30.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/31.rom_ctrl_alert_test.3660110572
Short name T291
Test name
Test status
Simulation time 3762542343 ps
CPU time 7.25 seconds
Started May 16 12:53:31 PM PDT 24
Finished May 16 12:53:55 PM PDT 24
Peak memory 211328 kb
Host smart-efe217eb-2c86-4c26-b111-8a73f5252517
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3660110572 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_alert_test.3660110572
Directory /workspace/31.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/31.rom_ctrl_corrupt_sig_fatal_chk.2035394570
Short name T360
Test name
Test status
Simulation time 8408560620 ps
CPU time 120.94 seconds
Started May 16 12:53:29 PM PDT 24
Finished May 16 12:55:45 PM PDT 24
Peak memory 212524 kb
Host smart-5bd88d04-649a-4fe0-add5-3c56a43248e0
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2035394570 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_
corrupt_sig_fatal_chk.2035394570
Directory /workspace/31.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/31.rom_ctrl_kmac_err_chk.2154916417
Short name T243
Test name
Test status
Simulation time 3081329577 ps
CPU time 28.04 seconds
Started May 16 12:53:27 PM PDT 24
Finished May 16 12:54:07 PM PDT 24
Peak memory 211964 kb
Host smart-a44184e0-d234-4517-be4e-ac6bed695eb0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2154916417 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_kmac_err_chk.2154916417
Directory /workspace/31.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/31.rom_ctrl_max_throughput_chk.1285286997
Short name T231
Test name
Test status
Simulation time 1933146320 ps
CPU time 8.42 seconds
Started May 16 12:53:27 PM PDT 24
Finished May 16 12:53:48 PM PDT 24
Peak memory 211072 kb
Host smart-98ce0096-bac5-4d16-a31b-929986a7f3d9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1285286997 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_max_throughput_chk.1285286997
Directory /workspace/31.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/31.rom_ctrl_smoke.33119030
Short name T77
Test name
Test status
Simulation time 4425365022 ps
CPU time 24.79 seconds
Started May 16 12:53:29 PM PDT 24
Finished May 16 12:54:08 PM PDT 24
Peak memory 219400 kb
Host smart-a78896d4-61af-420b-8458-e48e35766d32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=33119030 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_smoke.33119030
Directory /workspace/31.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/31.rom_ctrl_stress_all.2475312641
Short name T283
Test name
Test status
Simulation time 26639824924 ps
CPU time 48.38 seconds
Started May 16 12:53:28 PM PDT 24
Finished May 16 12:54:29 PM PDT 24
Peak memory 217008 kb
Host smart-d2d3f1d9-b6bb-4084-9df3-5ca123e3f986
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2475312641 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 31.rom_ctrl_stress_all.2475312641
Directory /workspace/31.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/32.rom_ctrl_alert_test.4070529704
Short name T228
Test name
Test status
Simulation time 2590935615 ps
CPU time 8.35 seconds
Started May 16 12:53:42 PM PDT 24
Finished May 16 12:54:15 PM PDT 24
Peak memory 211360 kb
Host smart-2c2e5c9c-7567-42be-afc8-f97780022234
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4070529704 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_alert_test.4070529704
Directory /workspace/32.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/32.rom_ctrl_corrupt_sig_fatal_chk.1525812212
Short name T121
Test name
Test status
Simulation time 53509648453 ps
CPU time 197.82 seconds
Started May 16 12:53:27 PM PDT 24
Finished May 16 12:56:56 PM PDT 24
Peak memory 237900 kb
Host smart-dd25ca38-23cb-41ed-9381-27a934107582
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1525812212 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_
corrupt_sig_fatal_chk.1525812212
Directory /workspace/32.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/32.rom_ctrl_kmac_err_chk.2502222043
Short name T354
Test name
Test status
Simulation time 4200675450 ps
CPU time 34.72 seconds
Started May 16 12:53:32 PM PDT 24
Finished May 16 12:54:24 PM PDT 24
Peak memory 211700 kb
Host smart-f2b69589-3988-47e5-a885-c27490c15968
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2502222043 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_kmac_err_chk.2502222043
Directory /workspace/32.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/32.rom_ctrl_max_throughput_chk.2972436404
Short name T239
Test name
Test status
Simulation time 1324191327 ps
CPU time 12.91 seconds
Started May 16 12:53:33 PM PDT 24
Finished May 16 12:54:03 PM PDT 24
Peak memory 210972 kb
Host smart-12eb34d5-e53a-4d57-9b06-6d85056bfd8d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2972436404 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_max_throughput_chk.2972436404
Directory /workspace/32.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/32.rom_ctrl_smoke.3387351884
Short name T304
Test name
Test status
Simulation time 4143480758 ps
CPU time 24.67 seconds
Started May 16 12:53:27 PM PDT 24
Finished May 16 12:54:04 PM PDT 24
Peak memory 212960 kb
Host smart-76ce6452-d22a-4c60-ab34-c75fc688a14b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3387351884 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_smoke.3387351884
Directory /workspace/32.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/32.rom_ctrl_stress_all.4185693454
Short name T71
Test name
Test status
Simulation time 19402597774 ps
CPU time 21.87 seconds
Started May 16 12:53:31 PM PDT 24
Finished May 16 12:54:09 PM PDT 24
Peak memory 211088 kb
Host smart-9197d090-51b5-4e1f-8076-1595d2d2c695
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4185693454 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 32.rom_ctrl_stress_all.4185693454
Directory /workspace/32.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/33.rom_ctrl_alert_test.3917268962
Short name T64
Test name
Test status
Simulation time 499657099 ps
CPU time 7.36 seconds
Started May 16 12:53:27 PM PDT 24
Finished May 16 12:53:48 PM PDT 24
Peak memory 211092 kb
Host smart-6ee11f38-469d-4b6a-97ff-e23b2541f4a6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3917268962 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_alert_test.3917268962
Directory /workspace/33.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/33.rom_ctrl_corrupt_sig_fatal_chk.3737395614
Short name T9
Test name
Test status
Simulation time 63857025640 ps
CPU time 143.63 seconds
Started May 16 12:53:33 PM PDT 24
Finished May 16 12:56:14 PM PDT 24
Peak memory 233564 kb
Host smart-5894f25d-8a45-4bf8-a91d-832dff51f491
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3737395614 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_
corrupt_sig_fatal_chk.3737395614
Directory /workspace/33.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/33.rom_ctrl_kmac_err_chk.2887352071
Short name T305
Test name
Test status
Simulation time 5230139830 ps
CPU time 18.02 seconds
Started May 16 12:53:31 PM PDT 24
Finished May 16 12:54:05 PM PDT 24
Peak memory 211404 kb
Host smart-a4bf57bc-3d81-4979-8226-46c9f38aa9b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2887352071 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_kmac_err_chk.2887352071
Directory /workspace/33.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/33.rom_ctrl_max_throughput_chk.727740754
Short name T264
Test name
Test status
Simulation time 829348422 ps
CPU time 10.51 seconds
Started May 16 12:53:31 PM PDT 24
Finished May 16 12:53:58 PM PDT 24
Peak memory 210976 kb
Host smart-63c8ec0e-2923-4574-8839-5c0cc7fd1d15
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=727740754 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_max_throughput_chk.727740754
Directory /workspace/33.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/33.rom_ctrl_smoke.4025927399
Short name T210
Test name
Test status
Simulation time 383598458 ps
CPU time 10.22 seconds
Started May 16 12:53:29 PM PDT 24
Finished May 16 12:53:53 PM PDT 24
Peak memory 213928 kb
Host smart-b79a9b22-1932-4887-a519-144f60da2982
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4025927399 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_smoke.4025927399
Directory /workspace/33.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/33.rom_ctrl_stress_all.635481443
Short name T74
Test name
Test status
Simulation time 1935920545 ps
CPU time 22.34 seconds
Started May 16 12:53:28 PM PDT 24
Finished May 16 12:54:03 PM PDT 24
Peak memory 214436 kb
Host smart-de422db1-ed5a-4839-83f8-4f7a1bf0bcea
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=635481443 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 33.rom_ctrl_stress_all.635481443
Directory /workspace/33.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/34.rom_ctrl_alert_test.2529741731
Short name T267
Test name
Test status
Simulation time 4264308811 ps
CPU time 10.73 seconds
Started May 16 12:53:33 PM PDT 24
Finished May 16 12:54:02 PM PDT 24
Peak memory 211184 kb
Host smart-3417591c-25fa-489d-9f87-d90e304f713e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2529741731 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_alert_test.2529741731
Directory /workspace/34.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/34.rom_ctrl_corrupt_sig_fatal_chk.1238028109
Short name T314
Test name
Test status
Simulation time 126969552663 ps
CPU time 372.5 seconds
Started May 16 12:53:31 PM PDT 24
Finished May 16 01:00:00 PM PDT 24
Peak memory 230480 kb
Host smart-a1bb6960-4201-486e-9855-b3312eb202c5
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1238028109 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_
corrupt_sig_fatal_chk.1238028109
Directory /workspace/34.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/34.rom_ctrl_kmac_err_chk.2918029238
Short name T178
Test name
Test status
Simulation time 2580425269 ps
CPU time 23.85 seconds
Started May 16 12:53:34 PM PDT 24
Finished May 16 12:54:17 PM PDT 24
Peak memory 211780 kb
Host smart-123b5834-d2e5-4583-abfe-4d130fca3163
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2918029238 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_kmac_err_chk.2918029238
Directory /workspace/34.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/34.rom_ctrl_max_throughput_chk.3131631552
Short name T158
Test name
Test status
Simulation time 516898800 ps
CPU time 8.23 seconds
Started May 16 12:53:33 PM PDT 24
Finished May 16 12:53:58 PM PDT 24
Peak memory 211080 kb
Host smart-1ea86f73-8a04-496e-ad9b-9bb4834a3094
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3131631552 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_max_throughput_chk.3131631552
Directory /workspace/34.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/34.rom_ctrl_smoke.127553113
Short name T151
Test name
Test status
Simulation time 2500639254 ps
CPU time 26.52 seconds
Started May 16 12:53:29 PM PDT 24
Finished May 16 12:54:11 PM PDT 24
Peak memory 212868 kb
Host smart-000a0bb9-ff3c-4716-95ed-a5dfc56f770c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=127553113 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_smoke.127553113
Directory /workspace/34.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/34.rom_ctrl_stress_all.2449844283
Short name T133
Test name
Test status
Simulation time 15039331858 ps
CPU time 20.25 seconds
Started May 16 12:53:33 PM PDT 24
Finished May 16 12:54:11 PM PDT 24
Peak memory 219444 kb
Host smart-e65a4b79-4871-4cf0-9242-4554667fc214
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2449844283 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 34.rom_ctrl_stress_all.2449844283
Directory /workspace/34.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/35.rom_ctrl_alert_test.819091499
Short name T361
Test name
Test status
Simulation time 868360366 ps
CPU time 9.71 seconds
Started May 16 12:53:30 PM PDT 24
Finished May 16 12:53:55 PM PDT 24
Peak memory 211156 kb
Host smart-d08788f2-6047-48e5-b05b-ed5c1afecd8e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=819091499 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_alert_test.819091499
Directory /workspace/35.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/35.rom_ctrl_corrupt_sig_fatal_chk.2792553421
Short name T207
Test name
Test status
Simulation time 1181305326 ps
CPU time 83.56 seconds
Started May 16 12:53:30 PM PDT 24
Finished May 16 12:55:09 PM PDT 24
Peak memory 237616 kb
Host smart-44c70bad-9c29-439f-8133-e4dbb6661e89
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2792553421 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_
corrupt_sig_fatal_chk.2792553421
Directory /workspace/35.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/35.rom_ctrl_kmac_err_chk.3762768264
Short name T225
Test name
Test status
Simulation time 6180519601 ps
CPU time 18.59 seconds
Started May 16 12:53:28 PM PDT 24
Finished May 16 12:54:01 PM PDT 24
Peak memory 212584 kb
Host smart-787683bb-bd73-4ba3-9249-8b66af3f6cf0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3762768264 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_kmac_err_chk.3762768264
Directory /workspace/35.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/35.rom_ctrl_max_throughput_chk.4280290163
Short name T341
Test name
Test status
Simulation time 6514964060 ps
CPU time 14.33 seconds
Started May 16 12:53:34 PM PDT 24
Finished May 16 12:54:06 PM PDT 24
Peak memory 211008 kb
Host smart-19dbea3f-879c-4853-945e-4b12326d9098
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4280290163 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_max_throughput_chk.4280290163
Directory /workspace/35.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/35.rom_ctrl_smoke.29123617
Short name T123
Test name
Test status
Simulation time 2527440587 ps
CPU time 18.24 seconds
Started May 16 12:53:29 PM PDT 24
Finished May 16 12:54:03 PM PDT 24
Peak memory 213488 kb
Host smart-0a1971c4-8164-4bc7-b1fc-ea4fdc30b891
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=29123617 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_smoke.29123617
Directory /workspace/35.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/35.rom_ctrl_stress_all.1646510396
Short name T196
Test name
Test status
Simulation time 31020048499 ps
CPU time 50.23 seconds
Started May 16 12:53:29 PM PDT 24
Finished May 16 12:54:35 PM PDT 24
Peak memory 217228 kb
Host smart-1bf22ac7-c390-470c-b1df-799248842faa
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1646510396 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 35.rom_ctrl_stress_all.1646510396
Directory /workspace/35.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/35.rom_ctrl_stress_all_with_rand_reset.1931426778
Short name T320
Test name
Test status
Simulation time 410003988522 ps
CPU time 1104.15 seconds
Started May 16 12:53:30 PM PDT 24
Finished May 16 01:12:11 PM PDT 24
Peak memory 230500 kb
Host smart-8a5ef022-7e33-4da9-8dc5-e69fa4ab19ac
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1931426778 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_stress_all_with_rand_reset.1931426778
Directory /workspace/35.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.rom_ctrl_alert_test.4242203100
Short name T194
Test name
Test status
Simulation time 4787677426 ps
CPU time 10.97 seconds
Started May 16 12:53:27 PM PDT 24
Finished May 16 12:53:51 PM PDT 24
Peak memory 211360 kb
Host smart-68ed2ac2-eb47-4c68-ab16-df133ab3fc98
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4242203100 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_alert_test.4242203100
Directory /workspace/36.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/36.rom_ctrl_corrupt_sig_fatal_chk.1671741452
Short name T212
Test name
Test status
Simulation time 4041211244 ps
CPU time 132.84 seconds
Started May 16 12:53:28 PM PDT 24
Finished May 16 12:55:54 PM PDT 24
Peak memory 234364 kb
Host smart-b39ade86-0d87-4389-ade7-d02dd376635a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1671741452 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_
corrupt_sig_fatal_chk.1671741452
Directory /workspace/36.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/36.rom_ctrl_kmac_err_chk.2470804856
Short name T140
Test name
Test status
Simulation time 1969828273 ps
CPU time 20.44 seconds
Started May 16 12:53:26 PM PDT 24
Finished May 16 12:53:57 PM PDT 24
Peak memory 211800 kb
Host smart-7eddcc4b-e7e0-4879-b5bf-cd8c87db9756
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2470804856 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_kmac_err_chk.2470804856
Directory /workspace/36.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/36.rom_ctrl_max_throughput_chk.1052356266
Short name T193
Test name
Test status
Simulation time 3627993861 ps
CPU time 12.33 seconds
Started May 16 12:53:27 PM PDT 24
Finished May 16 12:53:52 PM PDT 24
Peak memory 211180 kb
Host smart-52d8c2c7-41df-4e26-a6c3-6c2357805406
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1052356266 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_max_throughput_chk.1052356266
Directory /workspace/36.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/36.rom_ctrl_smoke.2005746871
Short name T135
Test name
Test status
Simulation time 716234025 ps
CPU time 9.89 seconds
Started May 16 12:53:31 PM PDT 24
Finished May 16 12:53:56 PM PDT 24
Peak memory 213292 kb
Host smart-917f7ca1-ca7d-4ce7-8f50-b9b6d8793925
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2005746871 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_smoke.2005746871
Directory /workspace/36.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/36.rom_ctrl_stress_all.1550553332
Short name T256
Test name
Test status
Simulation time 646670310 ps
CPU time 37.78 seconds
Started May 16 12:53:30 PM PDT 24
Finished May 16 12:54:24 PM PDT 24
Peak memory 215120 kb
Host smart-f3ec3b17-ae27-46ed-b09c-1ba2b410f950
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1550553332 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 36.rom_ctrl_stress_all.1550553332
Directory /workspace/36.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/36.rom_ctrl_stress_all_with_rand_reset.4119475702
Short name T53
Test name
Test status
Simulation time 409931982223 ps
CPU time 1543.7 seconds
Started May 16 12:53:33 PM PDT 24
Finished May 16 01:19:35 PM PDT 24
Peak memory 235924 kb
Host smart-dd90223e-6e63-4e4c-ba6b-a8b3f3dd027d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4119475702 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_stress_all_with_rand_reset.4119475702
Directory /workspace/36.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.rom_ctrl_alert_test.2722570480
Short name T124
Test name
Test status
Simulation time 88060358 ps
CPU time 4.17 seconds
Started May 16 12:53:27 PM PDT 24
Finished May 16 12:53:43 PM PDT 24
Peak memory 211120 kb
Host smart-319f4dc2-99e4-4ae6-bfed-e9a1c4ab94cf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2722570480 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_alert_test.2722570480
Directory /workspace/37.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/37.rom_ctrl_corrupt_sig_fatal_chk.1120524309
Short name T29
Test name
Test status
Simulation time 10119774016 ps
CPU time 171.18 seconds
Started May 16 12:53:25 PM PDT 24
Finished May 16 12:56:24 PM PDT 24
Peak memory 233756 kb
Host smart-ddf1a9d5-f3e5-410e-97b6-4a7b957755ea
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1120524309 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_
corrupt_sig_fatal_chk.1120524309
Directory /workspace/37.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/37.rom_ctrl_kmac_err_chk.3649685698
Short name T296
Test name
Test status
Simulation time 168875779 ps
CPU time 9.42 seconds
Started May 16 12:53:25 PM PDT 24
Finished May 16 12:53:43 PM PDT 24
Peak memory 211216 kb
Host smart-93a6503b-6388-4955-9c43-382d080b3403
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3649685698 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_kmac_err_chk.3649685698
Directory /workspace/37.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/37.rom_ctrl_max_throughput_chk.820668966
Short name T142
Test name
Test status
Simulation time 879789957 ps
CPU time 10.76 seconds
Started May 16 12:53:31 PM PDT 24
Finished May 16 12:53:59 PM PDT 24
Peak memory 210992 kb
Host smart-766133ee-a6ab-4b65-8701-bcfc8f233319
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=820668966 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_max_throughput_chk.820668966
Directory /workspace/37.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/37.rom_ctrl_smoke.4160403645
Short name T167
Test name
Test status
Simulation time 11223828262 ps
CPU time 19.95 seconds
Started May 16 12:53:27 PM PDT 24
Finished May 16 12:53:59 PM PDT 24
Peak memory 214284 kb
Host smart-4b617ea5-05af-4910-8159-ae9f47450ef4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4160403645 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_smoke.4160403645
Directory /workspace/37.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/37.rom_ctrl_stress_all.2389949035
Short name T309
Test name
Test status
Simulation time 15863949399 ps
CPU time 86.69 seconds
Started May 16 12:53:27 PM PDT 24
Finished May 16 12:55:06 PM PDT 24
Peak memory 219328 kb
Host smart-a055026d-6671-484b-ae22-ee8fd7b9d9d6
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2389949035 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 37.rom_ctrl_stress_all.2389949035
Directory /workspace/37.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/37.rom_ctrl_stress_all_with_rand_reset.1676597654
Short name T54
Test name
Test status
Simulation time 92591623492 ps
CPU time 2615.72 seconds
Started May 16 12:53:27 PM PDT 24
Finished May 16 01:37:15 PM PDT 24
Peak memory 235832 kb
Host smart-3a7c5c15-fa2a-4eb8-ba31-5577fb07cc0a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1676597654 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_stress_all_with_rand_reset.1676597654
Directory /workspace/37.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.rom_ctrl_alert_test.2344357645
Short name T300
Test name
Test status
Simulation time 476667594 ps
CPU time 5.43 seconds
Started May 16 12:53:39 PM PDT 24
Finished May 16 12:54:07 PM PDT 24
Peak memory 211124 kb
Host smart-1b32a0c3-db2a-437c-833d-c22794d112dc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2344357645 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_alert_test.2344357645
Directory /workspace/38.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/38.rom_ctrl_corrupt_sig_fatal_chk.1963968578
Short name T227
Test name
Test status
Simulation time 149861127794 ps
CPU time 254.51 seconds
Started May 16 12:53:38 PM PDT 24
Finished May 16 12:58:14 PM PDT 24
Peak memory 220992 kb
Host smart-f2d5d5da-1ab0-4602-b343-429578f29d93
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1963968578 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_
corrupt_sig_fatal_chk.1963968578
Directory /workspace/38.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/38.rom_ctrl_kmac_err_chk.3718720277
Short name T278
Test name
Test status
Simulation time 5829967847 ps
CPU time 25.32 seconds
Started May 16 12:53:36 PM PDT 24
Finished May 16 12:54:21 PM PDT 24
Peak memory 212516 kb
Host smart-cd8bc615-fb8a-4b0c-86d7-4d1059d312de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3718720277 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_kmac_err_chk.3718720277
Directory /workspace/38.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/38.rom_ctrl_max_throughput_chk.2440058094
Short name T226
Test name
Test status
Simulation time 1106154729 ps
CPU time 12.08 seconds
Started May 16 12:53:36 PM PDT 24
Finished May 16 12:54:07 PM PDT 24
Peak memory 211044 kb
Host smart-0a53dd70-c317-4c18-92ee-1eedbf53696b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2440058094 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_max_throughput_chk.2440058094
Directory /workspace/38.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/38.rom_ctrl_smoke.23084573
Short name T287
Test name
Test status
Simulation time 190564384 ps
CPU time 10.35 seconds
Started May 16 12:53:38 PM PDT 24
Finished May 16 12:54:09 PM PDT 24
Peak memory 213776 kb
Host smart-1d66ef2f-5317-479f-a3e6-de5b530904c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=23084573 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_smoke.23084573
Directory /workspace/38.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/38.rom_ctrl_stress_all.893987504
Short name T316
Test name
Test status
Simulation time 4865494680 ps
CPU time 52.82 seconds
Started May 16 12:53:40 PM PDT 24
Finished May 16 12:54:55 PM PDT 24
Peak memory 215616 kb
Host smart-3d44dd7e-34d4-4f44-9a4a-7515847bf2a2
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=893987504 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 38.rom_ctrl_stress_all.893987504
Directory /workspace/38.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/38.rom_ctrl_stress_all_with_rand_reset.3761519072
Short name T48
Test name
Test status
Simulation time 412610621389 ps
CPU time 2997.78 seconds
Started May 16 12:53:37 PM PDT 24
Finished May 16 01:43:56 PM PDT 24
Peak memory 247644 kb
Host smart-1526fd6c-d020-4ce1-9b4a-3de7b9fc7f56
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3761519072 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_stress_all_with_rand_reset.3761519072
Directory /workspace/38.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.rom_ctrl_alert_test.1729456790
Short name T171
Test name
Test status
Simulation time 2028203087 ps
CPU time 15.67 seconds
Started May 16 12:53:38 PM PDT 24
Finished May 16 12:54:14 PM PDT 24
Peak memory 211208 kb
Host smart-05a14e82-c09e-4263-88f5-67d6680ba4ca
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1729456790 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_alert_test.1729456790
Directory /workspace/39.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/39.rom_ctrl_corrupt_sig_fatal_chk.2312400621
Short name T355
Test name
Test status
Simulation time 3312102056 ps
CPU time 79.75 seconds
Started May 16 12:53:42 PM PDT 24
Finished May 16 12:55:26 PM PDT 24
Peak memory 236896 kb
Host smart-b66170e0-19ed-4ed9-8f71-7e503d61bb9b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2312400621 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_
corrupt_sig_fatal_chk.2312400621
Directory /workspace/39.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/39.rom_ctrl_kmac_err_chk.459743657
Short name T168
Test name
Test status
Simulation time 2550970221 ps
CPU time 17.4 seconds
Started May 16 12:53:42 PM PDT 24
Finished May 16 12:54:23 PM PDT 24
Peak memory 212060 kb
Host smart-43ad2ac5-c48b-4aa9-937a-e54e589517d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=459743657 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_kmac_err_chk.459743657
Directory /workspace/39.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/39.rom_ctrl_max_throughput_chk.2969850283
Short name T345
Test name
Test status
Simulation time 137117075 ps
CPU time 6.56 seconds
Started May 16 12:53:38 PM PDT 24
Finished May 16 12:54:06 PM PDT 24
Peak memory 210868 kb
Host smart-324b1885-3bbf-4c45-be1f-5c926015e75d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2969850283 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_max_throughput_chk.2969850283
Directory /workspace/39.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/39.rom_ctrl_smoke.1946749075
Short name T317
Test name
Test status
Simulation time 4839350751 ps
CPU time 21.01 seconds
Started May 16 12:53:32 PM PDT 24
Finished May 16 12:54:10 PM PDT 24
Peak memory 214008 kb
Host smart-3d2720ef-f756-49ee-9d06-cae88473311a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1946749075 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_smoke.1946749075
Directory /workspace/39.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/39.rom_ctrl_stress_all.2300770464
Short name T163
Test name
Test status
Simulation time 48573834760 ps
CPU time 33.96 seconds
Started May 16 12:53:38 PM PDT 24
Finished May 16 12:54:34 PM PDT 24
Peak memory 219260 kb
Host smart-08c115a1-ac60-4359-8ce7-cca9943f3d0d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2300770464 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 39.rom_ctrl_stress_all.2300770464
Directory /workspace/39.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/4.rom_ctrl_alert_test.1658581500
Short name T204
Test name
Test status
Simulation time 1168854258 ps
CPU time 11.69 seconds
Started May 16 12:52:50 PM PDT 24
Finished May 16 12:53:12 PM PDT 24
Peak memory 211124 kb
Host smart-3d9820ad-ee80-4f93-bfea-bfe6097342ba
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1658581500 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_alert_test.1658581500
Directory /workspace/4.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/4.rom_ctrl_corrupt_sig_fatal_chk.913509411
Short name T258
Test name
Test status
Simulation time 7417088971 ps
CPU time 117.76 seconds
Started May 16 12:52:54 PM PDT 24
Finished May 16 12:55:01 PM PDT 24
Peak memory 231392 kb
Host smart-ab6f301d-a509-4135-942f-7b8b3e90bb6e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=913509411 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_co
rrupt_sig_fatal_chk.913509411
Directory /workspace/4.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/4.rom_ctrl_kmac_err_chk.586759566
Short name T319
Test name
Test status
Simulation time 12805309128 ps
CPU time 16.58 seconds
Started May 16 12:52:54 PM PDT 24
Finished May 16 12:53:20 PM PDT 24
Peak memory 212940 kb
Host smart-bc47504f-1c4d-4b17-a156-2b7e6beb7580
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=586759566 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_kmac_err_chk.586759566
Directory /workspace/4.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/4.rom_ctrl_max_throughput_chk.4172395205
Short name T102
Test name
Test status
Simulation time 13533181715 ps
CPU time 13.48 seconds
Started May 16 12:52:52 PM PDT 24
Finished May 16 12:53:16 PM PDT 24
Peak memory 211172 kb
Host smart-f19a60c7-ae78-4f60-bafa-c47115944f3b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4172395205 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_max_throughput_chk.4172395205
Directory /workspace/4.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/4.rom_ctrl_sec_cm.3099447395
Short name T37
Test name
Test status
Simulation time 1476513555 ps
CPU time 105.89 seconds
Started May 16 12:52:55 PM PDT 24
Finished May 16 12:54:51 PM PDT 24
Peak memory 230728 kb
Host smart-684dea3c-ea2d-4c78-a97a-8e1421454ff0
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3099447395 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_sec_cm.3099447395
Directory /workspace/4.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/4.rom_ctrl_smoke.1298560541
Short name T155
Test name
Test status
Simulation time 8211809483 ps
CPU time 32.96 seconds
Started May 16 12:52:55 PM PDT 24
Finished May 16 12:53:38 PM PDT 24
Peak memory 219460 kb
Host smart-7b35a01b-55f6-41bc-afa0-621588fb6e7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1298560541 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_smoke.1298560541
Directory /workspace/4.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/4.rom_ctrl_stress_all.3937997416
Short name T15
Test name
Test status
Simulation time 1599142838 ps
CPU time 6.04 seconds
Started May 16 12:52:52 PM PDT 24
Finished May 16 12:53:08 PM PDT 24
Peak memory 211060 kb
Host smart-e2d35f43-daac-42d5-9cc1-c3c92eed11eb
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3937997416 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 4.rom_ctrl_stress_all.3937997416
Directory /workspace/4.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/40.rom_ctrl_alert_test.2791756823
Short name T244
Test name
Test status
Simulation time 922191321 ps
CPU time 9.58 seconds
Started May 16 12:53:38 PM PDT 24
Finished May 16 12:54:09 PM PDT 24
Peak memory 211220 kb
Host smart-13e70ba2-12e0-4e62-ac26-65b8abd2ec34
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2791756823 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_alert_test.2791756823
Directory /workspace/40.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/40.rom_ctrl_kmac_err_chk.1267044502
Short name T344
Test name
Test status
Simulation time 3151355404 ps
CPU time 27.61 seconds
Started May 16 12:53:39 PM PDT 24
Finished May 16 12:54:29 PM PDT 24
Peak memory 211980 kb
Host smart-9a996058-61e9-448e-a805-cb59ed6cdd82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1267044502 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_kmac_err_chk.1267044502
Directory /workspace/40.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/40.rom_ctrl_max_throughput_chk.1515472380
Short name T8
Test name
Test status
Simulation time 1420927145 ps
CPU time 13.51 seconds
Started May 16 12:53:38 PM PDT 24
Finished May 16 12:54:12 PM PDT 24
Peak memory 211060 kb
Host smart-54abfbae-df4d-463e-821a-7ab58c4147d2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1515472380 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_max_throughput_chk.1515472380
Directory /workspace/40.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/40.rom_ctrl_smoke.2127905580
Short name T240
Test name
Test status
Simulation time 361233243 ps
CPU time 9.96 seconds
Started May 16 12:53:38 PM PDT 24
Finished May 16 12:54:09 PM PDT 24
Peak memory 219232 kb
Host smart-53309ef3-ae91-47c8-8fc1-a651745d9a67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2127905580 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_smoke.2127905580
Directory /workspace/40.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/40.rom_ctrl_stress_all.1616005430
Short name T325
Test name
Test status
Simulation time 33262717044 ps
CPU time 83.55 seconds
Started May 16 12:53:36 PM PDT 24
Finished May 16 12:55:20 PM PDT 24
Peak memory 219388 kb
Host smart-c355a090-a6c0-4457-b232-e988f08d9ebc
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1616005430 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 40.rom_ctrl_stress_all.1616005430
Directory /workspace/40.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/41.rom_ctrl_alert_test.3714873590
Short name T180
Test name
Test status
Simulation time 6707095213 ps
CPU time 13.74 seconds
Started May 16 12:53:43 PM PDT 24
Finished May 16 12:54:20 PM PDT 24
Peak memory 211376 kb
Host smart-eefaf771-f5d2-497a-b86d-cf02c3c8b85f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3714873590 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_alert_test.3714873590
Directory /workspace/41.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/41.rom_ctrl_corrupt_sig_fatal_chk.2723162501
Short name T335
Test name
Test status
Simulation time 5608418112 ps
CPU time 142.06 seconds
Started May 16 12:53:45 PM PDT 24
Finished May 16 12:56:31 PM PDT 24
Peak memory 234308 kb
Host smart-cdad0754-cee6-404e-9dbe-3086596868be
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2723162501 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_
corrupt_sig_fatal_chk.2723162501
Directory /workspace/41.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/41.rom_ctrl_kmac_err_chk.2317459897
Short name T313
Test name
Test status
Simulation time 774525437 ps
CPU time 14.39 seconds
Started May 16 12:53:43 PM PDT 24
Finished May 16 12:54:21 PM PDT 24
Peak memory 211736 kb
Host smart-aa34e1cf-1ffb-4c46-85e0-b034406f4350
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2317459897 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_kmac_err_chk.2317459897
Directory /workspace/41.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/41.rom_ctrl_max_throughput_chk.4046549275
Short name T195
Test name
Test status
Simulation time 1390127489 ps
CPU time 11.58 seconds
Started May 16 12:53:38 PM PDT 24
Finished May 16 12:54:11 PM PDT 24
Peak memory 210964 kb
Host smart-e7e2cf34-d976-49e9-af22-d380adb7fa09
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4046549275 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_max_throughput_chk.4046549275
Directory /workspace/41.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/41.rom_ctrl_smoke.3557616631
Short name T147
Test name
Test status
Simulation time 8213275859 ps
CPU time 31.47 seconds
Started May 16 12:53:39 PM PDT 24
Finished May 16 12:54:32 PM PDT 24
Peak memory 213796 kb
Host smart-41d4fc19-b9e3-426b-9109-e598cf0ee875
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3557616631 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_smoke.3557616631
Directory /workspace/41.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/41.rom_ctrl_stress_all.1541027542
Short name T174
Test name
Test status
Simulation time 13271706092 ps
CPU time 101.04 seconds
Started May 16 12:53:39 PM PDT 24
Finished May 16 12:55:42 PM PDT 24
Peak memory 217108 kb
Host smart-452324ee-a6b8-43d7-9172-c263a93db990
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1541027542 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 41.rom_ctrl_stress_all.1541027542
Directory /workspace/41.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/41.rom_ctrl_stress_all_with_rand_reset.2355414985
Short name T66
Test name
Test status
Simulation time 28445485238 ps
CPU time 1124.97 seconds
Started May 16 12:53:42 PM PDT 24
Finished May 16 01:12:51 PM PDT 24
Peak memory 235864 kb
Host smart-58a02fba-24e6-4bcc-a610-6dbfaa33eac4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2355414985 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_stress_all_with_rand_reset.2355414985
Directory /workspace/41.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.rom_ctrl_alert_test.3461660176
Short name T35
Test name
Test status
Simulation time 1082073800 ps
CPU time 10.29 seconds
Started May 16 12:53:44 PM PDT 24
Finished May 16 12:54:18 PM PDT 24
Peak memory 211224 kb
Host smart-6653fbbe-a133-417e-a933-e0af50d78371
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3461660176 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_alert_test.3461660176
Directory /workspace/42.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/42.rom_ctrl_corrupt_sig_fatal_chk.2113424451
Short name T47
Test name
Test status
Simulation time 4061062850 ps
CPU time 56.55 seconds
Started May 16 12:53:43 PM PDT 24
Finished May 16 12:55:03 PM PDT 24
Peak memory 232856 kb
Host smart-bfca72dc-f1f7-41a0-bda4-06cd5e6d8881
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2113424451 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_
corrupt_sig_fatal_chk.2113424451
Directory /workspace/42.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/42.rom_ctrl_kmac_err_chk.2274064894
Short name T297
Test name
Test status
Simulation time 505620836 ps
CPU time 12.65 seconds
Started May 16 12:53:47 PM PDT 24
Finished May 16 12:54:24 PM PDT 24
Peak memory 211852 kb
Host smart-88a19803-dfdf-42d6-8578-3d834f679ec3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2274064894 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_kmac_err_chk.2274064894
Directory /workspace/42.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/42.rom_ctrl_max_throughput_chk.3754956847
Short name T14
Test name
Test status
Simulation time 1822435524 ps
CPU time 6.89 seconds
Started May 16 12:53:42 PM PDT 24
Finished May 16 12:54:12 PM PDT 24
Peak memory 210992 kb
Host smart-e7b28164-bee4-4854-aafe-d0040fc57c45
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3754956847 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_max_throughput_chk.3754956847
Directory /workspace/42.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/42.rom_ctrl_smoke.3557021554
Short name T331
Test name
Test status
Simulation time 3103095711 ps
CPU time 19.12 seconds
Started May 16 12:53:39 PM PDT 24
Finished May 16 12:54:20 PM PDT 24
Peak memory 219332 kb
Host smart-4d4b99ef-0c06-4d27-9beb-014955cf197a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3557021554 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_smoke.3557021554
Directory /workspace/42.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/42.rom_ctrl_stress_all.4260220562
Short name T157
Test name
Test status
Simulation time 704865444 ps
CPU time 20.12 seconds
Started May 16 12:53:42 PM PDT 24
Finished May 16 12:54:25 PM PDT 24
Peak memory 216228 kb
Host smart-d778dd7d-d682-4bb9-81b0-29c48256e4db
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4260220562 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 42.rom_ctrl_stress_all.4260220562
Directory /workspace/42.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/43.rom_ctrl_alert_test.2499665846
Short name T170
Test name
Test status
Simulation time 6608320351 ps
CPU time 14.15 seconds
Started May 16 12:53:46 PM PDT 24
Finished May 16 12:54:25 PM PDT 24
Peak memory 211324 kb
Host smart-b288cdb1-6b5f-4876-852b-71e98e4d8129
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2499665846 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_alert_test.2499665846
Directory /workspace/43.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/43.rom_ctrl_corrupt_sig_fatal_chk.4075827839
Short name T271
Test name
Test status
Simulation time 84014347312 ps
CPU time 245.56 seconds
Started May 16 12:53:37 PM PDT 24
Finished May 16 12:58:04 PM PDT 24
Peak memory 229240 kb
Host smart-4292528e-7673-444b-b4e8-e431c2a7f16a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4075827839 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_
corrupt_sig_fatal_chk.4075827839
Directory /workspace/43.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/43.rom_ctrl_kmac_err_chk.978205427
Short name T144
Test name
Test status
Simulation time 32868915594 ps
CPU time 25.76 seconds
Started May 16 12:53:47 PM PDT 24
Finished May 16 12:54:38 PM PDT 24
Peak memory 212324 kb
Host smart-5baa7c18-f968-4c3c-bf3e-6180b29b43ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=978205427 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_kmac_err_chk.978205427
Directory /workspace/43.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/43.rom_ctrl_max_throughput_chk.1031187266
Short name T245
Test name
Test status
Simulation time 185158248 ps
CPU time 6.73 seconds
Started May 16 12:53:48 PM PDT 24
Finished May 16 12:54:19 PM PDT 24
Peak memory 211084 kb
Host smart-643c4d39-87b9-48d0-aa1e-d1fddf61c3d1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1031187266 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_max_throughput_chk.1031187266
Directory /workspace/43.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/43.rom_ctrl_smoke.4133416389
Short name T270
Test name
Test status
Simulation time 193501977 ps
CPU time 10.09 seconds
Started May 16 12:53:46 PM PDT 24
Finished May 16 12:54:21 PM PDT 24
Peak memory 213844 kb
Host smart-289dccc9-bdfd-4eee-b42a-9281e1dfd5fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4133416389 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_smoke.4133416389
Directory /workspace/43.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/43.rom_ctrl_stress_all.1426651751
Short name T263
Test name
Test status
Simulation time 917967798 ps
CPU time 12.62 seconds
Started May 16 12:53:46 PM PDT 24
Finished May 16 12:54:23 PM PDT 24
Peak memory 211132 kb
Host smart-140d79db-72c4-4039-b05b-242796ec5075
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1426651751 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 43.rom_ctrl_stress_all.1426651751
Directory /workspace/43.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/44.rom_ctrl_alert_test.3130178802
Short name T348
Test name
Test status
Simulation time 85562968 ps
CPU time 4.29 seconds
Started May 16 12:53:42 PM PDT 24
Finished May 16 12:54:11 PM PDT 24
Peak memory 211276 kb
Host smart-c7a6b07d-5e84-497d-b92f-da7c31bfcd11
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3130178802 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_alert_test.3130178802
Directory /workspace/44.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/44.rom_ctrl_corrupt_sig_fatal_chk.3906420223
Short name T44
Test name
Test status
Simulation time 9602152142 ps
CPU time 160.33 seconds
Started May 16 12:53:47 PM PDT 24
Finished May 16 12:56:52 PM PDT 24
Peak memory 212784 kb
Host smart-23930d66-f1e1-4884-9650-5eb029d5d150
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3906420223 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_
corrupt_sig_fatal_chk.3906420223
Directory /workspace/44.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/44.rom_ctrl_kmac_err_chk.913663515
Short name T277
Test name
Test status
Simulation time 1842732144 ps
CPU time 9.56 seconds
Started May 16 12:53:43 PM PDT 24
Finished May 16 12:54:16 PM PDT 24
Peak memory 211948 kb
Host smart-0bb55082-c234-4e1d-8957-a393127ea9a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=913663515 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_kmac_err_chk.913663515
Directory /workspace/44.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/44.rom_ctrl_max_throughput_chk.923968098
Short name T356
Test name
Test status
Simulation time 8822015147 ps
CPU time 10.06 seconds
Started May 16 12:53:48 PM PDT 24
Finished May 16 12:54:22 PM PDT 24
Peak memory 211176 kb
Host smart-3370dbab-9b2c-497a-8308-725f28528eba
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=923968098 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_max_throughput_chk.923968098
Directory /workspace/44.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/44.rom_ctrl_smoke.1795874729
Short name T288
Test name
Test status
Simulation time 3020480364 ps
CPU time 17.61 seconds
Started May 16 12:53:48 PM PDT 24
Finished May 16 12:54:30 PM PDT 24
Peak memory 213792 kb
Host smart-67aa9852-be6d-4aa2-86aa-44b228c8bb9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1795874729 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_smoke.1795874729
Directory /workspace/44.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/44.rom_ctrl_stress_all.4049960111
Short name T233
Test name
Test status
Simulation time 1108304813 ps
CPU time 12.14 seconds
Started May 16 12:53:48 PM PDT 24
Finished May 16 12:54:25 PM PDT 24
Peak memory 213720 kb
Host smart-8b8a00ce-d756-46e1-b240-7e1c21bd2ed2
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4049960111 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 44.rom_ctrl_stress_all.4049960111
Directory /workspace/44.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/45.rom_ctrl_alert_test.1170896243
Short name T136
Test name
Test status
Simulation time 348739692 ps
CPU time 5.54 seconds
Started May 16 12:53:36 PM PDT 24
Finished May 16 12:54:01 PM PDT 24
Peak memory 211236 kb
Host smart-7c82b03f-f939-46b6-a32b-507e698f3a55
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1170896243 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_alert_test.1170896243
Directory /workspace/45.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/45.rom_ctrl_corrupt_sig_fatal_chk.1526859154
Short name T274
Test name
Test status
Simulation time 111883166844 ps
CPU time 273.64 seconds
Started May 16 12:53:38 PM PDT 24
Finished May 16 12:58:32 PM PDT 24
Peak memory 231512 kb
Host smart-39ca13ec-f297-411f-a09c-7f3d991566a9
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1526859154 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_
corrupt_sig_fatal_chk.1526859154
Directory /workspace/45.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/45.rom_ctrl_kmac_err_chk.4164414367
Short name T330
Test name
Test status
Simulation time 825484833 ps
CPU time 12.45 seconds
Started May 16 12:53:37 PM PDT 24
Finished May 16 12:54:10 PM PDT 24
Peak memory 212000 kb
Host smart-e3a57078-4ade-459a-9c2f-43af7a9a45d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4164414367 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_kmac_err_chk.4164414367
Directory /workspace/45.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/45.rom_ctrl_max_throughput_chk.256737264
Short name T201
Test name
Test status
Simulation time 4048905702 ps
CPU time 17.58 seconds
Started May 16 12:53:38 PM PDT 24
Finished May 16 12:54:17 PM PDT 24
Peak memory 211168 kb
Host smart-eb06e4c8-45d7-4111-ae18-eb991e00279f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=256737264 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_max_throughput_chk.256737264
Directory /workspace/45.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/45.rom_ctrl_smoke.264439569
Short name T338
Test name
Test status
Simulation time 9467584939 ps
CPU time 24.65 seconds
Started May 16 12:53:47 PM PDT 24
Finished May 16 12:54:36 PM PDT 24
Peak memory 219408 kb
Host smart-af993048-0bfe-4d7d-bf32-8168abba1769
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=264439569 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_smoke.264439569
Directory /workspace/45.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/45.rom_ctrl_stress_all.2485033733
Short name T211
Test name
Test status
Simulation time 3139437226 ps
CPU time 14.68 seconds
Started May 16 12:53:38 PM PDT 24
Finished May 16 12:54:14 PM PDT 24
Peak memory 211220 kb
Host smart-7a2bf0d9-6ab4-4d45-85c3-9a4be187259e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2485033733 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 45.rom_ctrl_stress_all.2485033733
Directory /workspace/45.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/46.rom_ctrl_alert_test.308879568
Short name T290
Test name
Test status
Simulation time 2510907131 ps
CPU time 11.91 seconds
Started May 16 12:53:38 PM PDT 24
Finished May 16 12:54:12 PM PDT 24
Peak memory 211272 kb
Host smart-eff68274-819b-4ef5-a761-266773d407f6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=308879568 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_alert_test.308879568
Directory /workspace/46.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/46.rom_ctrl_corrupt_sig_fatal_chk.29946046
Short name T31
Test name
Test status
Simulation time 6881676675 ps
CPU time 109.12 seconds
Started May 16 12:53:33 PM PDT 24
Finished May 16 12:55:39 PM PDT 24
Peak memory 234980 kb
Host smart-c1769fd6-94c8-4023-a205-37524b972df4
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29946046 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_
sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_co
rrupt_sig_fatal_chk.29946046
Directory /workspace/46.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/46.rom_ctrl_kmac_err_chk.1851367860
Short name T190
Test name
Test status
Simulation time 47010178549 ps
CPU time 31.64 seconds
Started May 16 12:53:38 PM PDT 24
Finished May 16 12:54:31 PM PDT 24
Peak memory 211376 kb
Host smart-8e85153c-e5c5-416e-97a4-00519d3ec352
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1851367860 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_kmac_err_chk.1851367860
Directory /workspace/46.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/46.rom_ctrl_max_throughput_chk.3332505646
Short name T310
Test name
Test status
Simulation time 3543232290 ps
CPU time 15.9 seconds
Started May 16 12:53:36 PM PDT 24
Finished May 16 12:54:11 PM PDT 24
Peak memory 211200 kb
Host smart-a2526b34-b801-4a7c-91d1-3615c82f2ad2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3332505646 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_max_throughput_chk.3332505646
Directory /workspace/46.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/46.rom_ctrl_smoke.200025384
Short name T303
Test name
Test status
Simulation time 4392891842 ps
CPU time 26.78 seconds
Started May 16 12:53:34 PM PDT 24
Finished May 16 12:54:18 PM PDT 24
Peak memory 213620 kb
Host smart-9cc11b09-cd09-4ac9-a1d4-ea9a884d9e74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=200025384 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_smoke.200025384
Directory /workspace/46.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/46.rom_ctrl_stress_all.2006611613
Short name T197
Test name
Test status
Simulation time 4466492205 ps
CPU time 10.89 seconds
Started May 16 12:53:36 PM PDT 24
Finished May 16 12:54:06 PM PDT 24
Peak memory 211252 kb
Host smart-a92a254d-ccd1-45e0-8825-0896a0ec8c98
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2006611613 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 46.rom_ctrl_stress_all.2006611613
Directory /workspace/46.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/46.rom_ctrl_stress_all_with_rand_reset.1126181472
Short name T106
Test name
Test status
Simulation time 68968869288 ps
CPU time 683.14 seconds
Started May 16 12:53:38 PM PDT 24
Finished May 16 01:05:23 PM PDT 24
Peak memory 235284 kb
Host smart-2d9aa946-ee1f-46a3-945a-fa7651b93b90
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1126181472 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_stress_all_with_rand_reset.1126181472
Directory /workspace/46.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.rom_ctrl_alert_test.2104621727
Short name T137
Test name
Test status
Simulation time 536307089 ps
CPU time 7.67 seconds
Started May 16 12:53:44 PM PDT 24
Finished May 16 12:54:16 PM PDT 24
Peak memory 211188 kb
Host smart-de6d971c-4d0f-41b6-87b3-efca765f25e9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2104621727 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_alert_test.2104621727
Directory /workspace/47.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/47.rom_ctrl_corrupt_sig_fatal_chk.2641904408
Short name T295
Test name
Test status
Simulation time 543088805692 ps
CPU time 385.93 seconds
Started May 16 12:53:35 PM PDT 24
Finished May 16 01:00:20 PM PDT 24
Peak memory 239216 kb
Host smart-30dc228b-0c97-4ae6-89b7-ff02f5917e47
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2641904408 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_
corrupt_sig_fatal_chk.2641904408
Directory /workspace/47.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/47.rom_ctrl_kmac_err_chk.1859287229
Short name T159
Test name
Test status
Simulation time 456314121 ps
CPU time 11.26 seconds
Started May 16 12:53:39 PM PDT 24
Finished May 16 12:54:13 PM PDT 24
Peak memory 212960 kb
Host smart-912c6515-d928-42c2-a63b-943f3a188313
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1859287229 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_kmac_err_chk.1859287229
Directory /workspace/47.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/47.rom_ctrl_max_throughput_chk.3194405281
Short name T208
Test name
Test status
Simulation time 363043109 ps
CPU time 5.48 seconds
Started May 16 12:53:42 PM PDT 24
Finished May 16 12:54:11 PM PDT 24
Peak memory 211060 kb
Host smart-cab5400d-e3fb-45bf-95c6-c943938d27ce
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3194405281 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_max_throughput_chk.3194405281
Directory /workspace/47.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/47.rom_ctrl_smoke.4164743924
Short name T222
Test name
Test status
Simulation time 8557850637 ps
CPU time 34.24 seconds
Started May 16 12:53:42 PM PDT 24
Finished May 16 12:54:41 PM PDT 24
Peak memory 219428 kb
Host smart-3f023443-c689-4ae8-9f61-0703e685ed42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4164743924 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_smoke.4164743924
Directory /workspace/47.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/47.rom_ctrl_stress_all.3351797666
Short name T200
Test name
Test status
Simulation time 11232995266 ps
CPU time 47.16 seconds
Started May 16 12:53:39 PM PDT 24
Finished May 16 12:54:49 PM PDT 24
Peak memory 219332 kb
Host smart-5928cdb4-878b-4853-b41b-9eead400d6ae
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3351797666 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 47.rom_ctrl_stress_all.3351797666
Directory /workspace/47.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/47.rom_ctrl_stress_all_with_rand_reset.1172944225
Short name T18
Test name
Test status
Simulation time 49153552405 ps
CPU time 885.75 seconds
Started May 16 12:53:38 PM PDT 24
Finished May 16 01:08:45 PM PDT 24
Peak memory 228656 kb
Host smart-f31a9639-9f03-4e3d-8fc1-534fc2e10f5b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1172944225 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_stress_all_with_rand_reset.1172944225
Directory /workspace/47.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.rom_ctrl_alert_test.2254557031
Short name T302
Test name
Test status
Simulation time 3349879638 ps
CPU time 13.19 seconds
Started May 16 12:53:41 PM PDT 24
Finished May 16 12:54:18 PM PDT 24
Peak memory 211276 kb
Host smart-cae8116e-8725-49f8-90f5-91e456d1f502
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2254557031 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_alert_test.2254557031
Directory /workspace/48.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/48.rom_ctrl_corrupt_sig_fatal_chk.3905221760
Short name T242
Test name
Test status
Simulation time 217855921730 ps
CPU time 243.99 seconds
Started May 16 12:53:45 PM PDT 24
Finished May 16 12:58:13 PM PDT 24
Peak memory 240932 kb
Host smart-460e5ace-3604-4e6a-8f85-38c5ffccf880
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3905221760 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_
corrupt_sig_fatal_chk.3905221760
Directory /workspace/48.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/48.rom_ctrl_kmac_err_chk.3457359953
Short name T26
Test name
Test status
Simulation time 26408092788 ps
CPU time 24.48 seconds
Started May 16 12:53:45 PM PDT 24
Finished May 16 12:54:34 PM PDT 24
Peak memory 212060 kb
Host smart-a0c04882-6092-4f1e-b6e0-a8dc1de8ebca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3457359953 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_kmac_err_chk.3457359953
Directory /workspace/48.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/48.rom_ctrl_max_throughput_chk.2906804805
Short name T130
Test name
Test status
Simulation time 1850145107 ps
CPU time 8.35 seconds
Started May 16 12:53:41 PM PDT 24
Finished May 16 12:54:13 PM PDT 24
Peak memory 210992 kb
Host smart-306cc236-770a-42b2-9450-5d62e7df8bc5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2906804805 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_max_throughput_chk.2906804805
Directory /workspace/48.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/48.rom_ctrl_smoke.2100370077
Short name T349
Test name
Test status
Simulation time 20949803079 ps
CPU time 21.25 seconds
Started May 16 12:53:39 PM PDT 24
Finished May 16 12:54:23 PM PDT 24
Peak memory 213732 kb
Host smart-1ab91285-8cd8-4bc6-8ebc-fbd30ab0311e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2100370077 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_smoke.2100370077
Directory /workspace/48.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/48.rom_ctrl_stress_all.1947077758
Short name T57
Test name
Test status
Simulation time 8628161880 ps
CPU time 20.84 seconds
Started May 16 12:53:46 PM PDT 24
Finished May 16 12:54:31 PM PDT 24
Peak memory 213492 kb
Host smart-f41a9f9a-dff8-411c-a4ac-891dc894133c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1947077758 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 48.rom_ctrl_stress_all.1947077758
Directory /workspace/48.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/49.rom_ctrl_alert_test.913591314
Short name T65
Test name
Test status
Simulation time 2446329006 ps
CPU time 11.7 seconds
Started May 16 12:53:43 PM PDT 24
Finished May 16 12:54:19 PM PDT 24
Peak memory 211348 kb
Host smart-55d986f8-a60d-431c-a07d-e1cd8c86247a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=913591314 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_alert_test.913591314
Directory /workspace/49.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/49.rom_ctrl_kmac_err_chk.3005768029
Short name T173
Test name
Test status
Simulation time 2193183341 ps
CPU time 22.56 seconds
Started May 16 12:53:42 PM PDT 24
Finished May 16 12:54:28 PM PDT 24
Peak memory 212012 kb
Host smart-571fbbe2-f9d4-41c6-9019-96573f8b8b6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3005768029 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_kmac_err_chk.3005768029
Directory /workspace/49.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/49.rom_ctrl_max_throughput_chk.1027795986
Short name T191
Test name
Test status
Simulation time 95194650 ps
CPU time 5.46 seconds
Started May 16 12:53:41 PM PDT 24
Finished May 16 12:54:10 PM PDT 24
Peak memory 210992 kb
Host smart-ce8ea03f-d42e-4fc3-888e-eae1182dc984
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1027795986 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_max_throughput_chk.1027795986
Directory /workspace/49.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/49.rom_ctrl_smoke.2369769559
Short name T131
Test name
Test status
Simulation time 4045390923 ps
CPU time 22.54 seconds
Started May 16 12:53:41 PM PDT 24
Finished May 16 12:54:27 PM PDT 24
Peak memory 213508 kb
Host smart-c95b2f85-3f4b-4e6a-a3ca-da7ac4f70d30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2369769559 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_smoke.2369769559
Directory /workspace/49.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/49.rom_ctrl_stress_all.4124295138
Short name T214
Test name
Test status
Simulation time 8000672001 ps
CPU time 46.2 seconds
Started May 16 12:53:43 PM PDT 24
Finished May 16 12:54:53 PM PDT 24
Peak memory 219436 kb
Host smart-a871d766-fd45-4df0-ac6d-ba3670ae1d32
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4124295138 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 49.rom_ctrl_stress_all.4124295138
Directory /workspace/49.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/5.rom_ctrl_alert_test.3044801276
Short name T156
Test name
Test status
Simulation time 1773093472 ps
CPU time 5.1 seconds
Started May 16 12:52:55 PM PDT 24
Finished May 16 12:53:10 PM PDT 24
Peak memory 211204 kb
Host smart-662ed8ed-4c16-4e04-ba0b-822b6837a204
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3044801276 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_alert_test.3044801276
Directory /workspace/5.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/5.rom_ctrl_corrupt_sig_fatal_chk.980142948
Short name T321
Test name
Test status
Simulation time 41423518873 ps
CPU time 256.15 seconds
Started May 16 12:52:54 PM PDT 24
Finished May 16 12:57:20 PM PDT 24
Peak memory 212612 kb
Host smart-dd0f859d-3ae5-4f2c-9a59-4b5cea8ab0b0
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=980142948 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_co
rrupt_sig_fatal_chk.980142948
Directory /workspace/5.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/5.rom_ctrl_kmac_err_chk.3314938708
Short name T21
Test name
Test status
Simulation time 665913779 ps
CPU time 9.29 seconds
Started May 16 12:53:00 PM PDT 24
Finished May 16 12:53:16 PM PDT 24
Peak memory 211764 kb
Host smart-3fce7392-f09c-494d-91ba-7e84187081df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3314938708 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_kmac_err_chk.3314938708
Directory /workspace/5.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/5.rom_ctrl_max_throughput_chk.1826199123
Short name T139
Test name
Test status
Simulation time 3640671558 ps
CPU time 10.9 seconds
Started May 16 12:52:55 PM PDT 24
Finished May 16 12:53:16 PM PDT 24
Peak memory 211052 kb
Host smart-d986b7a8-df39-4ad7-b51e-135fdd91bfcc
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1826199123 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_max_throughput_chk.1826199123
Directory /workspace/5.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/5.rom_ctrl_stress_all.1482486641
Short name T333
Test name
Test status
Simulation time 2239999799 ps
CPU time 21.03 seconds
Started May 16 12:52:52 PM PDT 24
Finished May 16 12:53:24 PM PDT 24
Peak memory 214876 kb
Host smart-1e7bebde-2181-40b2-adc4-659ff97b3e57
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1482486641 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 5.rom_ctrl_stress_all.1482486641
Directory /workspace/5.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/6.rom_ctrl_alert_test.4238462507
Short name T334
Test name
Test status
Simulation time 103579881 ps
CPU time 4.3 seconds
Started May 16 12:52:56 PM PDT 24
Finished May 16 12:53:09 PM PDT 24
Peak memory 211204 kb
Host smart-c012cab7-dfd8-4151-9fca-4e24ad74ed87
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4238462507 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_alert_test.4238462507
Directory /workspace/6.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/6.rom_ctrl_corrupt_sig_fatal_chk.796654970
Short name T128
Test name
Test status
Simulation time 15835302918 ps
CPU time 135.74 seconds
Started May 16 12:53:00 PM PDT 24
Finished May 16 12:55:22 PM PDT 24
Peak memory 236824 kb
Host smart-e328d686-7f78-4f90-bc90-d6be0744d2ec
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=796654970 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_co
rrupt_sig_fatal_chk.796654970
Directory /workspace/6.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/6.rom_ctrl_kmac_err_chk.1991219016
Short name T205
Test name
Test status
Simulation time 5983559660 ps
CPU time 28.71 seconds
Started May 16 12:52:55 PM PDT 24
Finished May 16 12:53:33 PM PDT 24
Peak memory 212256 kb
Host smart-fc27a868-8196-4250-976a-8277ca4fac63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1991219016 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_kmac_err_chk.1991219016
Directory /workspace/6.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/6.rom_ctrl_max_throughput_chk.998505706
Short name T125
Test name
Test status
Simulation time 1516629707 ps
CPU time 14.05 seconds
Started May 16 12:52:54 PM PDT 24
Finished May 16 12:53:18 PM PDT 24
Peak memory 211052 kb
Host smart-8d0cbf0e-b0a5-4390-aee1-9e81cdfc4dc0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=998505706 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_max_throughput_chk.998505706
Directory /workspace/6.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/6.rom_ctrl_smoke.354059439
Short name T236
Test name
Test status
Simulation time 3063142476 ps
CPU time 18.1 seconds
Started May 16 12:53:02 PM PDT 24
Finished May 16 12:53:26 PM PDT 24
Peak memory 211832 kb
Host smart-9b53ce55-58d7-4da6-a4e2-e957d66a86c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=354059439 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_smoke.354059439
Directory /workspace/6.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/6.rom_ctrl_stress_all.3768278185
Short name T183
Test name
Test status
Simulation time 2387015772 ps
CPU time 30.17 seconds
Started May 16 12:52:52 PM PDT 24
Finished May 16 12:53:33 PM PDT 24
Peak memory 219308 kb
Host smart-83658d93-3dd8-4e28-8491-b90d62f4aa53
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3768278185 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 6.rom_ctrl_stress_all.3768278185
Directory /workspace/6.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/7.rom_ctrl_alert_test.280496614
Short name T69
Test name
Test status
Simulation time 1783003246 ps
CPU time 14.9 seconds
Started May 16 12:53:01 PM PDT 24
Finished May 16 12:53:22 PM PDT 24
Peak memory 211128 kb
Host smart-76312e88-f675-4ca8-a924-39dfc358ecd6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=280496614 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_alert_test.280496614
Directory /workspace/7.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/7.rom_ctrl_corrupt_sig_fatal_chk.1914658860
Short name T46
Test name
Test status
Simulation time 25734245160 ps
CPU time 290.95 seconds
Started May 16 12:52:56 PM PDT 24
Finished May 16 12:57:56 PM PDT 24
Peak memory 228476 kb
Host smart-2d5b39cb-5812-424c-a1df-68fc53370a7a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1914658860 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_c
orrupt_sig_fatal_chk.1914658860
Directory /workspace/7.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/7.rom_ctrl_kmac_err_chk.2349612432
Short name T213
Test name
Test status
Simulation time 4118714788 ps
CPU time 12.77 seconds
Started May 16 12:53:00 PM PDT 24
Finished May 16 12:53:19 PM PDT 24
Peak memory 212016 kb
Host smart-7b57f7ce-b2e9-49a1-be78-275d9cbaef05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2349612432 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_kmac_err_chk.2349612432
Directory /workspace/7.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/7.rom_ctrl_max_throughput_chk.3815178821
Short name T67
Test name
Test status
Simulation time 4241591680 ps
CPU time 16.43 seconds
Started May 16 12:52:59 PM PDT 24
Finished May 16 12:53:22 PM PDT 24
Peak memory 210840 kb
Host smart-d060e633-64ad-4347-a07a-2de75e15b30c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3815178821 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_max_throughput_chk.3815178821
Directory /workspace/7.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/7.rom_ctrl_smoke.919697796
Short name T301
Test name
Test status
Simulation time 8337344026 ps
CPU time 33.15 seconds
Started May 16 12:52:56 PM PDT 24
Finished May 16 12:53:38 PM PDT 24
Peak memory 214044 kb
Host smart-ca886ca3-717a-430d-8c1f-38ad90f47ab4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=919697796 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_smoke.919697796
Directory /workspace/7.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/7.rom_ctrl_stress_all.2845449850
Short name T235
Test name
Test status
Simulation time 302328797 ps
CPU time 15.54 seconds
Started May 16 12:52:55 PM PDT 24
Finished May 16 12:53:20 PM PDT 24
Peak memory 219316 kb
Host smart-d98a6df7-c389-44e0-a547-3508c0f1f8c8
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2845449850 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 7.rom_ctrl_stress_all.2845449850
Directory /workspace/7.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/8.rom_ctrl_alert_test.2388707938
Short name T68
Test name
Test status
Simulation time 2215321955 ps
CPU time 10.95 seconds
Started May 16 12:53:06 PM PDT 24
Finished May 16 12:53:23 PM PDT 24
Peak memory 211268 kb
Host smart-81ef9f13-fb09-4c9e-a47c-3b3f44b4e80a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2388707938 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_alert_test.2388707938
Directory /workspace/8.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/8.rom_ctrl_corrupt_sig_fatal_chk.2839433735
Short name T248
Test name
Test status
Simulation time 11766057072 ps
CPU time 79.82 seconds
Started May 16 12:53:10 PM PDT 24
Finished May 16 12:54:38 PM PDT 24
Peak memory 228900 kb
Host smart-99911212-1bb0-4cf8-bde2-cad45d3ceda2
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2839433735 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_c
orrupt_sig_fatal_chk.2839433735
Directory /workspace/8.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/8.rom_ctrl_kmac_err_chk.548285624
Short name T241
Test name
Test status
Simulation time 168639246 ps
CPU time 9.7 seconds
Started May 16 12:53:08 PM PDT 24
Finished May 16 12:53:23 PM PDT 24
Peak memory 211680 kb
Host smart-c4c27c08-5820-4441-a913-d71e6e6e5ce6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=548285624 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_kmac_err_chk.548285624
Directory /workspace/8.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/8.rom_ctrl_max_throughput_chk.3952861187
Short name T311
Test name
Test status
Simulation time 1010130772 ps
CPU time 11.45 seconds
Started May 16 12:52:56 PM PDT 24
Finished May 16 12:53:16 PM PDT 24
Peak memory 211076 kb
Host smart-1239ed50-b108-4c40-837e-fcbc8ade8177
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3952861187 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_max_throughput_chk.3952861187
Directory /workspace/8.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/8.rom_ctrl_smoke.4058112318
Short name T165
Test name
Test status
Simulation time 1487165106 ps
CPU time 19.3 seconds
Started May 16 12:52:55 PM PDT 24
Finished May 16 12:53:24 PM PDT 24
Peak memory 219328 kb
Host smart-c0c71128-e0b1-4700-964b-922b22314e15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4058112318 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_smoke.4058112318
Directory /workspace/8.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/8.rom_ctrl_stress_all.4166906251
Short name T141
Test name
Test status
Simulation time 4868596630 ps
CPU time 28.08 seconds
Started May 16 12:52:59 PM PDT 24
Finished May 16 12:53:34 PM PDT 24
Peak memory 216780 kb
Host smart-6ee059cd-dfb0-4af4-a64d-74e3216c26f0
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4166906251 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 8.rom_ctrl_stress_all.4166906251
Directory /workspace/8.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/9.rom_ctrl_alert_test.2559171962
Short name T138
Test name
Test status
Simulation time 1684818142 ps
CPU time 14.17 seconds
Started May 16 12:53:03 PM PDT 24
Finished May 16 12:53:23 PM PDT 24
Peak memory 211212 kb
Host smart-319d5fbf-750e-42b2-8dda-00471cbf5527
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2559171962 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_alert_test.2559171962
Directory /workspace/9.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/9.rom_ctrl_corrupt_sig_fatal_chk.2308907508
Short name T318
Test name
Test status
Simulation time 15772913599 ps
CPU time 183.68 seconds
Started May 16 12:53:11 PM PDT 24
Finished May 16 12:56:23 PM PDT 24
Peak memory 237836 kb
Host smart-704dc9a1-9633-4126-bfc4-4514e5dbd194
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2308907508 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_c
orrupt_sig_fatal_chk.2308907508
Directory /workspace/9.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/9.rom_ctrl_kmac_err_chk.1655532729
Short name T265
Test name
Test status
Simulation time 1413615694 ps
CPU time 18.93 seconds
Started May 16 12:53:06 PM PDT 24
Finished May 16 12:53:30 PM PDT 24
Peak memory 211640 kb
Host smart-95e66bdf-71d0-4586-aa6e-e1221542adf2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1655532729 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_kmac_err_chk.1655532729
Directory /workspace/9.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/9.rom_ctrl_max_throughput_chk.3066770221
Short name T306
Test name
Test status
Simulation time 4482328241 ps
CPU time 12.54 seconds
Started May 16 12:53:09 PM PDT 24
Finished May 16 12:53:30 PM PDT 24
Peak memory 211128 kb
Host smart-bb0d4299-1a35-4aa2-86f3-141b5ca5fe0a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3066770221 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_max_throughput_chk.3066770221
Directory /workspace/9.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/9.rom_ctrl_smoke.1462912966
Short name T143
Test name
Test status
Simulation time 183014665 ps
CPU time 10.04 seconds
Started May 16 12:53:09 PM PDT 24
Finished May 16 12:53:27 PM PDT 24
Peak memory 212632 kb
Host smart-bc32e9b6-4b8c-4317-b040-9b3dda204b9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1462912966 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_smoke.1462912966
Directory /workspace/9.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/9.rom_ctrl_stress_all_with_rand_reset.1551177198
Short name T52
Test name
Test status
Simulation time 20705688652 ps
CPU time 764.2 seconds
Started May 16 12:53:08 PM PDT 24
Finished May 16 01:05:58 PM PDT 24
Peak memory 226824 kb
Host smart-1e32a838-8b21-4188-947c-bed09724ad58
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1551177198 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_stress_all_with_rand_reset.1551177198
Directory /workspace/9.rom_ctrl_stress_all_with_rand_reset/latest
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