Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
97.69 96.97 93.58 97.88 100.00 99.02 98.03 98.37


Total test records in report: 464
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T308 /workspace/coverage/default/36.rom_ctrl_kmac_err_chk.3036422277 May 19 12:54:05 PM PDT 24 May 19 12:54:34 PM PDT 24 13412061765 ps
T309 /workspace/coverage/default/14.rom_ctrl_smoke.1204956927 May 19 12:53:46 PM PDT 24 May 19 12:54:13 PM PDT 24 5454165873 ps
T310 /workspace/coverage/default/16.rom_ctrl_smoke.3793076920 May 19 12:53:48 PM PDT 24 May 19 12:54:00 PM PDT 24 358703254 ps
T311 /workspace/coverage/default/22.rom_ctrl_kmac_err_chk.1246759998 May 19 12:54:04 PM PDT 24 May 19 12:54:18 PM PDT 24 331351088 ps
T312 /workspace/coverage/default/44.rom_ctrl_kmac_err_chk.1564867304 May 19 12:54:05 PM PDT 24 May 19 12:54:21 PM PDT 24 2614041733 ps
T313 /workspace/coverage/default/23.rom_ctrl_smoke.1919810417 May 19 12:53:54 PM PDT 24 May 19 12:54:26 PM PDT 24 36278337987 ps
T314 /workspace/coverage/default/32.rom_ctrl_alert_test.3569696435 May 19 12:53:56 PM PDT 24 May 19 12:54:10 PM PDT 24 3811000243 ps
T315 /workspace/coverage/default/37.rom_ctrl_smoke.3284156448 May 19 12:54:05 PM PDT 24 May 19 12:54:33 PM PDT 24 18750095409 ps
T316 /workspace/coverage/default/40.rom_ctrl_smoke.3110438237 May 19 12:54:10 PM PDT 24 May 19 12:54:41 PM PDT 24 2982326274 ps
T317 /workspace/coverage/default/10.rom_ctrl_smoke.6406076 May 19 12:53:44 PM PDT 24 May 19 12:54:15 PM PDT 24 14483536757 ps
T318 /workspace/coverage/default/20.rom_ctrl_smoke.2451600966 May 19 12:53:56 PM PDT 24 May 19 12:54:26 PM PDT 24 3153352255 ps
T319 /workspace/coverage/default/45.rom_ctrl_max_throughput_chk.1294830651 May 19 12:54:08 PM PDT 24 May 19 12:54:15 PM PDT 24 370211357 ps
T320 /workspace/coverage/default/2.rom_ctrl_max_throughput_chk.2021887797 May 19 12:53:38 PM PDT 24 May 19 12:53:55 PM PDT 24 1738752213 ps
T321 /workspace/coverage/default/32.rom_ctrl_smoke.3529722325 May 19 12:53:56 PM PDT 24 May 19 12:54:28 PM PDT 24 3747261371 ps
T322 /workspace/coverage/default/31.rom_ctrl_alert_test.347358166 May 19 12:53:52 PM PDT 24 May 19 12:54:05 PM PDT 24 1787018018 ps
T323 /workspace/coverage/default/49.rom_ctrl_stress_all.420225720 May 19 12:54:10 PM PDT 24 May 19 12:54:51 PM PDT 24 32488226145 ps
T324 /workspace/coverage/default/7.rom_ctrl_stress_all.2374063190 May 19 12:53:43 PM PDT 24 May 19 12:54:04 PM PDT 24 7689543972 ps
T325 /workspace/coverage/default/6.rom_ctrl_corrupt_sig_fatal_chk.2679296914 May 19 12:53:55 PM PDT 24 May 19 12:55:05 PM PDT 24 3982640521 ps
T326 /workspace/coverage/default/25.rom_ctrl_corrupt_sig_fatal_chk.1781363106 May 19 12:54:04 PM PDT 24 May 19 12:56:14 PM PDT 24 5805788757 ps
T327 /workspace/coverage/default/6.rom_ctrl_alert_test.3901171524 May 19 12:53:50 PM PDT 24 May 19 12:53:59 PM PDT 24 371518151 ps
T328 /workspace/coverage/default/8.rom_ctrl_stress_all.522068488 May 19 12:53:46 PM PDT 24 May 19 12:54:09 PM PDT 24 778460519 ps
T329 /workspace/coverage/default/31.rom_ctrl_corrupt_sig_fatal_chk.2932074948 May 19 12:54:01 PM PDT 24 May 19 12:59:44 PM PDT 24 40831023094 ps
T330 /workspace/coverage/default/24.rom_ctrl_alert_test.481534739 May 19 12:53:54 PM PDT 24 May 19 12:54:14 PM PDT 24 2751484765 ps
T331 /workspace/coverage/default/40.rom_ctrl_stress_all.3862727049 May 19 12:54:08 PM PDT 24 May 19 12:54:25 PM PDT 24 16320654238 ps
T332 /workspace/coverage/default/34.rom_ctrl_stress_all.3210703846 May 19 12:54:02 PM PDT 24 May 19 12:54:31 PM PDT 24 1189905555 ps
T333 /workspace/coverage/default/28.rom_ctrl_stress_all.1552688739 May 19 12:53:57 PM PDT 24 May 19 12:54:27 PM PDT 24 1924052346 ps
T334 /workspace/coverage/default/2.rom_ctrl_corrupt_sig_fatal_chk.277110002 May 19 12:53:29 PM PDT 24 May 19 12:55:39 PM PDT 24 10936060030 ps
T335 /workspace/coverage/default/49.rom_ctrl_alert_test.291200919 May 19 12:54:10 PM PDT 24 May 19 12:54:22 PM PDT 24 721213875 ps
T336 /workspace/coverage/default/27.rom_ctrl_smoke.468487877 May 19 12:53:54 PM PDT 24 May 19 12:54:16 PM PDT 24 3235185313 ps
T337 /workspace/coverage/default/47.rom_ctrl_alert_test.3147287979 May 19 12:54:15 PM PDT 24 May 19 12:54:32 PM PDT 24 1178367214 ps
T338 /workspace/coverage/default/4.rom_ctrl_kmac_err_chk.2904830024 May 19 12:53:33 PM PDT 24 May 19 12:54:07 PM PDT 24 16469894668 ps
T339 /workspace/coverage/default/11.rom_ctrl_corrupt_sig_fatal_chk.2491033210 May 19 12:53:52 PM PDT 24 May 19 12:56:29 PM PDT 24 11392745972 ps
T340 /workspace/coverage/default/32.rom_ctrl_corrupt_sig_fatal_chk.201259241 May 19 12:54:03 PM PDT 24 May 19 12:55:51 PM PDT 24 1606725535 ps
T341 /workspace/coverage/default/38.rom_ctrl_kmac_err_chk.236811741 May 19 12:54:00 PM PDT 24 May 19 12:54:38 PM PDT 24 9486544383 ps
T342 /workspace/coverage/default/38.rom_ctrl_stress_all.712705247 May 19 12:54:11 PM PDT 24 May 19 12:54:53 PM PDT 24 19614118119 ps
T343 /workspace/coverage/default/5.rom_ctrl_max_throughput_chk.200467784 May 19 12:53:28 PM PDT 24 May 19 12:53:47 PM PDT 24 9315527734 ps
T344 /workspace/coverage/default/21.rom_ctrl_smoke.815408756 May 19 12:53:58 PM PDT 24 May 19 12:54:21 PM PDT 24 1968749390 ps
T345 /workspace/coverage/default/19.rom_ctrl_alert_test.3818396634 May 19 12:53:47 PM PDT 24 May 19 12:54:01 PM PDT 24 1388581297 ps
T346 /workspace/coverage/default/12.rom_ctrl_alert_test.2103432736 May 19 12:53:50 PM PDT 24 May 19 12:53:58 PM PDT 24 1147039987 ps
T347 /workspace/coverage/default/13.rom_ctrl_corrupt_sig_fatal_chk.2707827336 May 19 12:53:50 PM PDT 24 May 19 12:57:52 PM PDT 24 44681929958 ps
T348 /workspace/coverage/default/38.rom_ctrl_alert_test.3465330661 May 19 12:54:11 PM PDT 24 May 19 12:54:20 PM PDT 24 87980015 ps
T349 /workspace/coverage/default/6.rom_ctrl_kmac_err_chk.3313215757 May 19 12:53:35 PM PDT 24 May 19 12:54:08 PM PDT 24 15359112478 ps
T350 /workspace/coverage/default/43.rom_ctrl_stress_all.2535767944 May 19 12:54:11 PM PDT 24 May 19 12:54:40 PM PDT 24 9458705486 ps
T351 /workspace/coverage/default/16.rom_ctrl_corrupt_sig_fatal_chk.68928235 May 19 12:53:48 PM PDT 24 May 19 12:57:02 PM PDT 24 41679156167 ps
T352 /workspace/coverage/default/49.rom_ctrl_max_throughput_chk.431628138 May 19 12:54:16 PM PDT 24 May 19 12:54:29 PM PDT 24 567162871 ps
T353 /workspace/coverage/default/8.rom_ctrl_alert_test.4239479773 May 19 12:53:37 PM PDT 24 May 19 12:53:49 PM PDT 24 23681811100 ps
T354 /workspace/coverage/default/49.rom_ctrl_smoke.2645836906 May 19 12:54:18 PM PDT 24 May 19 12:54:51 PM PDT 24 3218310421 ps
T355 /workspace/coverage/default/21.rom_ctrl_max_throughput_chk.3273908844 May 19 12:53:58 PM PDT 24 May 19 12:54:07 PM PDT 24 137046137 ps
T356 /workspace/coverage/default/14.rom_ctrl_max_throughput_chk.137166741 May 19 12:53:51 PM PDT 24 May 19 12:54:10 PM PDT 24 1819008641 ps
T357 /workspace/coverage/default/9.rom_ctrl_max_throughput_chk.3354016489 May 19 12:53:45 PM PDT 24 May 19 12:53:57 PM PDT 24 16436476532 ps
T358 /workspace/coverage/default/3.rom_ctrl_corrupt_sig_fatal_chk.122748357 May 19 12:53:47 PM PDT 24 May 19 12:59:41 PM PDT 24 111073347241 ps
T359 /workspace/coverage/default/44.rom_ctrl_smoke.4140464872 May 19 12:54:10 PM PDT 24 May 19 12:54:25 PM PDT 24 205762484 ps
T360 /workspace/coverage/default/5.rom_ctrl_stress_all.3522428061 May 19 12:53:35 PM PDT 24 May 19 12:54:32 PM PDT 24 5664528603 ps
T96 /workspace/coverage/default/29.rom_ctrl_max_throughput_chk.1922060878 May 19 12:54:09 PM PDT 24 May 19 12:54:18 PM PDT 24 98439793 ps
T97 /workspace/coverage/default/24.rom_ctrl_max_throughput_chk.3220813410 May 19 12:54:00 PM PDT 24 May 19 12:54:11 PM PDT 24 518212522 ps
T98 /workspace/coverage/default/46.rom_ctrl_kmac_err_chk.3074313207 May 19 12:54:10 PM PDT 24 May 19 12:54:24 PM PDT 24 340518465 ps
T99 /workspace/coverage/default/14.rom_ctrl_kmac_err_chk.3147980134 May 19 12:53:50 PM PDT 24 May 19 12:54:18 PM PDT 24 14681923455 ps
T100 /workspace/coverage/default/32.rom_ctrl_kmac_err_chk.1458791136 May 19 12:53:54 PM PDT 24 May 19 12:54:07 PM PDT 24 693163886 ps
T101 /workspace/coverage/default/43.rom_ctrl_kmac_err_chk.3450050293 May 19 12:54:16 PM PDT 24 May 19 12:54:38 PM PDT 24 1281711815 ps
T102 /workspace/coverage/default/27.rom_ctrl_stress_all.1448482033 May 19 12:53:57 PM PDT 24 May 19 12:54:20 PM PDT 24 1698167026 ps
T103 /workspace/coverage/default/3.rom_ctrl_stress_all.2580293012 May 19 12:53:53 PM PDT 24 May 19 12:54:13 PM PDT 24 2722727126 ps
T104 /workspace/coverage/default/31.rom_ctrl_kmac_err_chk.935567064 May 19 12:54:10 PM PDT 24 May 19 12:54:39 PM PDT 24 9949654415 ps
T105 /workspace/coverage/default/0.rom_ctrl_max_throughput_chk.2274620268 May 19 12:53:25 PM PDT 24 May 19 12:53:35 PM PDT 24 476317688 ps
T361 /workspace/coverage/default/22.rom_ctrl_corrupt_sig_fatal_chk.2921802850 May 19 12:54:15 PM PDT 24 May 19 12:58:48 PM PDT 24 45611965509 ps
T362 /workspace/coverage/default/38.rom_ctrl_max_throughput_chk.143830031 May 19 12:54:05 PM PDT 24 May 19 12:54:13 PM PDT 24 98415685 ps
T363 /workspace/coverage/default/21.rom_ctrl_alert_test.1871743012 May 19 12:54:00 PM PDT 24 May 19 12:54:19 PM PDT 24 23378137023 ps
T364 /workspace/coverage/default/12.rom_ctrl_smoke.1495285094 May 19 12:53:52 PM PDT 24 May 19 12:54:19 PM PDT 24 3150215748 ps
T365 /workspace/coverage/default/39.rom_ctrl_corrupt_sig_fatal_chk.4201946191 May 19 12:54:13 PM PDT 24 May 19 12:56:50 PM PDT 24 28980497132 ps
T366 /workspace/coverage/default/28.rom_ctrl_smoke.3196430069 May 19 12:54:05 PM PDT 24 May 19 12:54:18 PM PDT 24 378857174 ps
T60 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_mem_rw_with_rand_reset.2269350367 May 19 12:53:13 PM PDT 24 May 19 12:53:26 PM PDT 24 2452385320 ps
T57 /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_intg_err.108365772 May 19 12:53:10 PM PDT 24 May 19 12:53:59 PM PDT 24 4436010874 ps
T61 /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_rw.3274195039 May 19 12:53:39 PM PDT 24 May 19 12:53:49 PM PDT 24 743067548 ps
T66 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_hw_reset.663655792 May 19 12:53:08 PM PDT 24 May 19 12:53:25 PM PDT 24 6409713261 ps
T67 /workspace/coverage/cover_reg_top/11.rom_ctrl_same_csr_outstanding.1302670481 May 19 12:53:25 PM PDT 24 May 19 12:53:44 PM PDT 24 2083990837 ps
T106 /workspace/coverage/cover_reg_top/0.rom_ctrl_same_csr_outstanding.2766810186 May 19 12:53:12 PM PDT 24 May 19 12:53:32 PM PDT 24 19499473809 ps
T68 /workspace/coverage/cover_reg_top/11.rom_ctrl_passthru_mem_tl_intg_err.2535378424 May 19 12:53:17 PM PDT 24 May 19 12:54:18 PM PDT 24 24726292563 ps
T58 /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_intg_err.962143226 May 19 12:53:19 PM PDT 24 May 19 12:54:38 PM PDT 24 1343223020 ps
T69 /workspace/coverage/cover_reg_top/8.rom_ctrl_passthru_mem_tl_intg_err.3883312749 May 19 12:53:20 PM PDT 24 May 19 12:54:24 PM PDT 24 25456966432 ps
T70 /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_rw.2173295883 May 19 12:53:24 PM PDT 24 May 19 12:53:33 PM PDT 24 2554663899 ps
T71 /workspace/coverage/cover_reg_top/15.rom_ctrl_passthru_mem_tl_intg_err.3036069486 May 19 12:53:13 PM PDT 24 May 19 12:54:52 PM PDT 24 24107856633 ps
T367 /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_mem_rw_with_rand_reset.1576021142 May 19 12:53:39 PM PDT 24 May 19 12:53:44 PM PDT 24 254963312 ps
T72 /workspace/coverage/cover_reg_top/13.rom_ctrl_passthru_mem_tl_intg_err.3297841739 May 19 12:53:20 PM PDT 24 May 19 12:53:51 PM PDT 24 4491057798 ps
T59 /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_intg_err.1563994591 May 19 12:53:11 PM PDT 24 May 19 12:54:32 PM PDT 24 1579869978 ps
T73 /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_rw.2373705719 May 19 12:53:24 PM PDT 24 May 19 12:53:39 PM PDT 24 7567327161 ps
T368 /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_errors.1635513225 May 19 12:53:29 PM PDT 24 May 19 12:53:43 PM PDT 24 4718398952 ps
T369 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_rw.3304841432 May 19 12:53:18 PM PDT 24 May 19 12:53:35 PM PDT 24 6693307106 ps
T74 /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_rw.3279671121 May 19 12:53:26 PM PDT 24 May 19 12:53:39 PM PDT 24 2316118111 ps
T370 /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_errors.286142181 May 19 12:53:14 PM PDT 24 May 19 12:53:26 PM PDT 24 87079427 ps
T75 /workspace/coverage/cover_reg_top/5.rom_ctrl_passthru_mem_tl_intg_err.3684985274 May 19 12:53:10 PM PDT 24 May 19 12:54:10 PM PDT 24 6246173687 ps
T371 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_mem_rw_with_rand_reset.3683991746 May 19 12:53:12 PM PDT 24 May 19 12:53:25 PM PDT 24 3362794893 ps
T112 /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_intg_err.2114573701 May 19 12:53:17 PM PDT 24 May 19 12:54:35 PM PDT 24 2302798962 ps
T372 /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_mem_rw_with_rand_reset.3543786360 May 19 12:53:18 PM PDT 24 May 19 12:53:29 PM PDT 24 451267646 ps
T373 /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_mem_rw_with_rand_reset.2062473589 May 19 12:53:21 PM PDT 24 May 19 12:53:40 PM PDT 24 2074171644 ps
T374 /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_rw.590514319 May 19 12:53:22 PM PDT 24 May 19 12:53:29 PM PDT 24 308624272 ps
T375 /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_rw.3233322539 May 19 12:53:41 PM PDT 24 May 19 12:53:59 PM PDT 24 4263422131 ps
T376 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_mem_rw_with_rand_reset.308052923 May 19 12:53:15 PM PDT 24 May 19 12:53:32 PM PDT 24 4216471328 ps
T377 /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_errors.1225677361 May 19 12:53:14 PM PDT 24 May 19 12:53:28 PM PDT 24 175566369 ps
T83 /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_rw.643549267 May 19 12:53:18 PM PDT 24 May 19 12:53:33 PM PDT 24 1097189635 ps
T107 /workspace/coverage/cover_reg_top/15.rom_ctrl_same_csr_outstanding.1172745790 May 19 12:53:30 PM PDT 24 May 19 12:53:47 PM PDT 24 19742604100 ps
T378 /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_mem_rw_with_rand_reset.4232373482 May 19 12:53:40 PM PDT 24 May 19 12:53:57 PM PDT 24 2000200703 ps
T84 /workspace/coverage/cover_reg_top/0.rom_ctrl_passthru_mem_tl_intg_err.2271547456 May 19 12:53:04 PM PDT 24 May 19 12:54:02 PM PDT 24 7773299692 ps
T379 /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_mem_rw_with_rand_reset.2237048841 May 19 12:53:40 PM PDT 24 May 19 12:53:55 PM PDT 24 3178046363 ps
T380 /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_partial_access.1018802137 May 19 12:53:09 PM PDT 24 May 19 12:53:21 PM PDT 24 296778595 ps
T115 /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_intg_err.2043664061 May 19 12:53:04 PM PDT 24 May 19 12:54:18 PM PDT 24 801508003 ps
T381 /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_walk.1877881933 May 19 12:53:09 PM PDT 24 May 19 12:53:27 PM PDT 24 3035461328 ps
T382 /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_errors.398667056 May 19 12:53:09 PM PDT 24 May 19 12:53:27 PM PDT 24 2630475488 ps
T383 /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_mem_rw_with_rand_reset.2017804248 May 19 12:53:25 PM PDT 24 May 19 12:53:34 PM PDT 24 1299655851 ps
T118 /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_intg_err.1913229873 May 19 12:53:41 PM PDT 24 May 19 12:54:25 PM PDT 24 5214764518 ps
T123 /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_intg_err.56994414 May 19 12:53:19 PM PDT 24 May 19 12:54:38 PM PDT 24 1294059783 ps
T121 /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_intg_err.2706093443 May 19 12:53:14 PM PDT 24 May 19 12:54:31 PM PDT 24 3251510441 ps
T116 /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_intg_err.700912774 May 19 12:53:13 PM PDT 24 May 19 12:54:27 PM PDT 24 434996179 ps
T384 /workspace/coverage/cover_reg_top/2.rom_ctrl_passthru_mem_tl_intg_err.1467427221 May 19 12:53:20 PM PDT 24 May 19 12:54:57 PM PDT 24 11817747797 ps
T108 /workspace/coverage/cover_reg_top/4.rom_ctrl_same_csr_outstanding.747927836 May 19 12:53:13 PM PDT 24 May 19 12:53:25 PM PDT 24 561281352 ps
T109 /workspace/coverage/cover_reg_top/10.rom_ctrl_same_csr_outstanding.1357306870 May 19 12:53:17 PM PDT 24 May 19 12:53:33 PM PDT 24 1190054998 ps
T385 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_aliasing.977372877 May 19 12:53:11 PM PDT 24 May 19 12:53:33 PM PDT 24 4092528954 ps
T85 /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_rw.2876627081 May 19 12:53:14 PM PDT 24 May 19 12:53:24 PM PDT 24 831097528 ps
T386 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_mem_rw_with_rand_reset.1532005172 May 19 12:53:31 PM PDT 24 May 19 12:53:40 PM PDT 24 821651776 ps
T387 /workspace/coverage/cover_reg_top/4.rom_ctrl_passthru_mem_tl_intg_err.1399528727 May 19 12:53:09 PM PDT 24 May 19 12:53:55 PM PDT 24 3631115737 ps
T110 /workspace/coverage/cover_reg_top/19.rom_ctrl_same_csr_outstanding.3698372244 May 19 12:53:35 PM PDT 24 May 19 12:53:43 PM PDT 24 97927393 ps
T388 /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_errors.3233040175 May 19 12:53:39 PM PDT 24 May 19 12:53:57 PM PDT 24 1694355291 ps
T86 /workspace/coverage/cover_reg_top/7.rom_ctrl_passthru_mem_tl_intg_err.4175829951 May 19 12:53:13 PM PDT 24 May 19 12:54:54 PM PDT 24 47524307622 ps
T87 /workspace/coverage/cover_reg_top/1.rom_ctrl_passthru_mem_tl_intg_err.1892082486 May 19 12:53:12 PM PDT 24 May 19 12:53:56 PM PDT 24 13762193729 ps
T389 /workspace/coverage/cover_reg_top/13.rom_ctrl_same_csr_outstanding.1435761895 May 19 12:53:17 PM PDT 24 May 19 12:53:37 PM PDT 24 1860465917 ps
T390 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_hw_reset.3302723965 May 19 12:53:20 PM PDT 24 May 19 12:53:42 PM PDT 24 4253148725 ps
T93 /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_rw.3699719482 May 19 12:53:30 PM PDT 24 May 19 12:53:38 PM PDT 24 1365206151 ps
T88 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_aliasing.1019889276 May 19 12:53:12 PM PDT 24 May 19 12:53:31 PM PDT 24 6403224619 ps
T391 /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_errors.3366117124 May 19 12:53:25 PM PDT 24 May 19 12:53:43 PM PDT 24 1450709471 ps
T89 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_aliasing.303402198 May 19 12:53:27 PM PDT 24 May 19 12:53:36 PM PDT 24 1449970035 ps
T392 /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_mem_rw_with_rand_reset.2498246191 May 19 12:53:19 PM PDT 24 May 19 12:53:28 PM PDT 24 391440211 ps
T94 /workspace/coverage/cover_reg_top/10.rom_ctrl_passthru_mem_tl_intg_err.1556262750 May 19 12:53:13 PM PDT 24 May 19 12:53:37 PM PDT 24 5112838391 ps
T393 /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_errors.4025146951 May 19 12:53:38 PM PDT 24 May 19 12:53:54 PM PDT 24 6876379776 ps
T117 /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_intg_err.1279436062 May 19 12:53:18 PM PDT 24 May 19 12:54:10 PM PDT 24 2026799369 ps
T394 /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_mem_rw_with_rand_reset.3661301944 May 19 12:53:43 PM PDT 24 May 19 12:53:54 PM PDT 24 2521876382 ps
T395 /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_rw.2285946213 May 19 12:53:10 PM PDT 24 May 19 12:53:20 PM PDT 24 333425416 ps
T396 /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_errors.2993700559 May 19 12:53:25 PM PDT 24 May 19 12:53:39 PM PDT 24 1159579657 ps
T90 /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_rw.474909318 May 19 12:53:19 PM PDT 24 May 19 12:53:31 PM PDT 24 621778758 ps
T91 /workspace/coverage/cover_reg_top/14.rom_ctrl_passthru_mem_tl_intg_err.2723588916 May 19 12:53:18 PM PDT 24 May 19 12:54:28 PM PDT 24 17464107777 ps
T397 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_rw.528452469 May 19 12:53:14 PM PDT 24 May 19 12:53:34 PM PDT 24 1733737054 ps
T398 /workspace/coverage/cover_reg_top/18.rom_ctrl_passthru_mem_tl_intg_err.1123521347 May 19 12:53:42 PM PDT 24 May 19 12:55:04 PM PDT 24 65261378000 ps
T399 /workspace/coverage/cover_reg_top/12.rom_ctrl_same_csr_outstanding.1093782348 May 19 12:53:14 PM PDT 24 May 19 12:53:36 PM PDT 24 1836874083 ps
T113 /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_intg_err.1697041961 May 19 12:53:22 PM PDT 24 May 19 12:54:38 PM PDT 24 5301170149 ps
T400 /workspace/coverage/cover_reg_top/8.rom_ctrl_same_csr_outstanding.1135536074 May 19 12:53:18 PM PDT 24 May 19 12:53:35 PM PDT 24 6716068068 ps
T401 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_bit_bash.1820872684 May 19 12:53:13 PM PDT 24 May 19 12:53:32 PM PDT 24 6031373757 ps
T402 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_bit_bash.1962322949 May 19 12:53:13 PM PDT 24 May 19 12:53:23 PM PDT 24 347831244 ps
T403 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_aliasing.1829360718 May 19 12:53:10 PM PDT 24 May 19 12:53:20 PM PDT 24 168679999 ps
T92 /workspace/coverage/cover_reg_top/17.rom_ctrl_passthru_mem_tl_intg_err.2472792483 May 19 12:53:15 PM PDT 24 May 19 12:54:11 PM PDT 24 9144930265 ps
T404 /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_errors.3977077041 May 19 12:53:02 PM PDT 24 May 19 12:53:21 PM PDT 24 955021725 ps
T405 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_bit_bash.3083111723 May 19 12:53:17 PM PDT 24 May 19 12:53:31 PM PDT 24 1625669742 ps
T406 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_rw.1176095908 May 19 12:53:17 PM PDT 24 May 19 12:53:39 PM PDT 24 2132561004 ps
T407 /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_mem_rw_with_rand_reset.1482620602 May 19 12:53:29 PM PDT 24 May 19 12:53:40 PM PDT 24 2336640264 ps
T95 /workspace/coverage/cover_reg_top/3.rom_ctrl_passthru_mem_tl_intg_err.1721505260 May 19 12:53:06 PM PDT 24 May 19 12:53:59 PM PDT 24 18520943120 ps
T408 /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_mem_rw_with_rand_reset.415068848 May 19 12:53:14 PM PDT 24 May 19 12:53:28 PM PDT 24 737977879 ps
T409 /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_errors.3335265180 May 19 12:53:21 PM PDT 24 May 19 12:53:40 PM PDT 24 1461411274 ps
T114 /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_intg_err.536942888 May 19 12:53:41 PM PDT 24 May 19 12:54:53 PM PDT 24 233936706 ps
T410 /workspace/coverage/cover_reg_top/19.rom_ctrl_passthru_mem_tl_intg_err.2426749105 May 19 12:53:19 PM PDT 24 May 19 12:53:58 PM PDT 24 4314612969 ps
T411 /workspace/coverage/cover_reg_top/9.rom_ctrl_passthru_mem_tl_intg_err.3787307956 May 19 12:53:14 PM PDT 24 May 19 12:54:23 PM PDT 24 7986364308 ps
T412 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_hw_reset.3796604770 May 19 12:53:14 PM PDT 24 May 19 12:53:30 PM PDT 24 4539403541 ps
T124 /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_intg_err.1025002779 May 19 12:53:14 PM PDT 24 May 19 12:54:31 PM PDT 24 3566152917 ps
T413 /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_rw.1589807346 May 19 12:53:22 PM PDT 24 May 19 12:53:35 PM PDT 24 2174453213 ps
T414 /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_errors.3420137425 May 19 12:53:13 PM PDT 24 May 19 12:53:27 PM PDT 24 248051268 ps
T415 /workspace/coverage/cover_reg_top/12.rom_ctrl_passthru_mem_tl_intg_err.3146392900 May 19 12:53:21 PM PDT 24 May 19 12:53:52 PM PDT 24 2163735892 ps
T416 /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_rw.3477637263 May 19 12:53:19 PM PDT 24 May 19 12:53:36 PM PDT 24 12995914902 ps
T417 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_bit_bash.1737254076 May 19 12:53:12 PM PDT 24 May 19 12:53:32 PM PDT 24 7236849730 ps
T418 /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_walk.2168865269 May 19 12:53:14 PM PDT 24 May 19 12:53:25 PM PDT 24 223477915 ps
T419 /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_errors.2638181882 May 19 12:53:13 PM PDT 24 May 19 12:53:36 PM PDT 24 23698770191 ps
T420 /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_errors.3878513513 May 19 12:53:19 PM PDT 24 May 19 12:53:41 PM PDT 24 22227845132 ps
T122 /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_intg_err.2725177552 May 19 12:53:25 PM PDT 24 May 19 12:54:39 PM PDT 24 2386121161 ps
T421 /workspace/coverage/cover_reg_top/18.rom_ctrl_same_csr_outstanding.502534030 May 19 12:53:29 PM PDT 24 May 19 12:53:43 PM PDT 24 1506090056 ps
T422 /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_intg_err.3831283444 May 19 12:53:19 PM PDT 24 May 19 12:54:40 PM PDT 24 1725678011 ps
T423 /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_rw.1331947135 May 19 12:53:37 PM PDT 24 May 19 12:53:42 PM PDT 24 334454385 ps
T424 /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_walk.4171734329 May 19 12:53:17 PM PDT 24 May 19 12:53:36 PM PDT 24 3569802972 ps
T425 /workspace/coverage/cover_reg_top/1.rom_ctrl_same_csr_outstanding.172892925 May 19 12:53:17 PM PDT 24 May 19 12:53:32 PM PDT 24 21366951670 ps
T426 /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_mem_rw_with_rand_reset.1196803257 May 19 12:53:27 PM PDT 24 May 19 12:53:33 PM PDT 24 92244199 ps
T427 /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_partial_access.1634159460 May 19 12:53:12 PM PDT 24 May 19 12:53:26 PM PDT 24 1287754834 ps
T428 /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_errors.3473541433 May 19 12:53:13 PM PDT 24 May 19 12:53:36 PM PDT 24 5241824385 ps
T429 /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_errors.306861605 May 19 12:53:19 PM PDT 24 May 19 12:53:39 PM PDT 24 1632574149 ps
T430 /workspace/coverage/cover_reg_top/7.rom_ctrl_same_csr_outstanding.1686659555 May 19 12:53:30 PM PDT 24 May 19 12:53:47 PM PDT 24 8006109755 ps
T119 /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_intg_err.1165360293 May 19 12:53:19 PM PDT 24 May 19 12:54:09 PM PDT 24 7535652774 ps
T431 /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_errors.1844484841 May 19 12:53:19 PM PDT 24 May 19 12:53:36 PM PDT 24 2212603221 ps
T432 /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_partial_access.1333100628 May 19 12:53:18 PM PDT 24 May 19 12:53:31 PM PDT 24 9217025484 ps
T433 /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_intg_err.3349615535 May 19 12:53:22 PM PDT 24 May 19 12:54:35 PM PDT 24 10140964046 ps
T434 /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_errors.2507843749 May 19 12:53:19 PM PDT 24 May 19 12:53:32 PM PDT 24 536454185 ps
T435 /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_walk.4019865211 May 19 12:53:14 PM PDT 24 May 19 12:53:23 PM PDT 24 171754916 ps
T436 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_hw_reset.1391617477 May 19 12:53:19 PM PDT 24 May 19 12:53:30 PM PDT 24 352166851 ps
T437 /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_mem_rw_with_rand_reset.896483941 May 19 12:53:21 PM PDT 24 May 19 12:53:38 PM PDT 24 6738145191 ps
T438 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_aliasing.413820174 May 19 12:53:03 PM PDT 24 May 19 12:53:14 PM PDT 24 779126765 ps
T439 /workspace/coverage/cover_reg_top/5.rom_ctrl_same_csr_outstanding.4117494311 May 19 12:53:19 PM PDT 24 May 19 12:53:27 PM PDT 24 89070684 ps
T440 /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_errors.2680324755 May 19 12:53:33 PM PDT 24 May 19 12:53:47 PM PDT 24 2291441364 ps
T441 /workspace/coverage/cover_reg_top/16.rom_ctrl_passthru_mem_tl_intg_err.1311134892 May 19 12:53:32 PM PDT 24 May 19 12:54:47 PM PDT 24 16461114704 ps
T442 /workspace/coverage/cover_reg_top/6.rom_ctrl_passthru_mem_tl_intg_err.665922313 May 19 12:53:22 PM PDT 24 May 19 12:54:52 PM PDT 24 10842929731 ps
T443 /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_errors.3508812403 May 19 12:53:34 PM PDT 24 May 19 12:53:54 PM PDT 24 10778453640 ps
T444 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_rw.1753748256 May 19 12:53:05 PM PDT 24 May 19 12:53:20 PM PDT 24 1167758350 ps
T445 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_hw_reset.935367720 May 19 12:53:12 PM PDT 24 May 19 12:53:23 PM PDT 24 341101250 ps
T446 /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_rw.907451209 May 19 12:53:25 PM PDT 24 May 19 12:53:32 PM PDT 24 211951774 ps
T447 /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_walk.397515418 May 19 12:53:05 PM PDT 24 May 19 12:53:13 PM PDT 24 232241202 ps
T448 /workspace/coverage/cover_reg_top/17.rom_ctrl_same_csr_outstanding.4043105961 May 19 12:53:30 PM PDT 24 May 19 12:53:35 PM PDT 24 1181587182 ps
T449 /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_partial_access.2603031024 May 19 12:53:09 PM PDT 24 May 19 12:53:25 PM PDT 24 4119330260 ps
T450 /workspace/coverage/cover_reg_top/9.rom_ctrl_same_csr_outstanding.577831129 May 19 12:53:24 PM PDT 24 May 19 12:53:31 PM PDT 24 552994828 ps
T451 /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_errors.1753389083 May 19 12:53:22 PM PDT 24 May 19 12:53:39 PM PDT 24 4590195546 ps
T452 /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_mem_rw_with_rand_reset.2192740104 May 19 12:53:22 PM PDT 24 May 19 12:53:29 PM PDT 24 345247941 ps
T453 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_rw.1198701708 May 19 12:53:16 PM PDT 24 May 19 12:53:28 PM PDT 24 1208209064 ps
T454 /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_partial_access.2790771908 May 19 12:53:01 PM PDT 24 May 19 12:53:09 PM PDT 24 103655854 ps
T120 /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_intg_err.3022875535 May 19 12:53:19 PM PDT 24 May 19 12:54:36 PM PDT 24 1093353791 ps
T455 /workspace/coverage/cover_reg_top/6.rom_ctrl_same_csr_outstanding.1713890906 May 19 12:53:13 PM PDT 24 May 19 12:53:32 PM PDT 24 1432698931 ps
T456 /workspace/coverage/cover_reg_top/2.rom_ctrl_same_csr_outstanding.866289056 May 19 12:53:10 PM PDT 24 May 19 12:53:33 PM PDT 24 8761562709 ps
T457 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_mem_rw_with_rand_reset.1283542627 May 19 12:53:15 PM PDT 24 May 19 12:53:34 PM PDT 24 1508133364 ps
T458 /workspace/coverage/cover_reg_top/14.rom_ctrl_same_csr_outstanding.1038834871 May 19 12:53:26 PM PDT 24 May 19 12:53:32 PM PDT 24 87520041 ps
T459 /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_intg_err.2393492017 May 19 12:53:11 PM PDT 24 May 19 12:53:53 PM PDT 24 884155683 ps
T460 /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_mem_rw_with_rand_reset.3584593373 May 19 12:53:13 PM PDT 24 May 19 12:53:24 PM PDT 24 198876970 ps
T461 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_bit_bash.3754802153 May 19 12:53:17 PM PDT 24 May 19 12:53:32 PM PDT 24 11266631358 ps
T462 /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_mem_rw_with_rand_reset.3026379874 May 19 12:53:19 PM PDT 24 May 19 12:53:28 PM PDT 24 374878310 ps
T463 /workspace/coverage/cover_reg_top/3.rom_ctrl_same_csr_outstanding.1165775012 May 19 12:53:19 PM PDT 24 May 19 12:53:27 PM PDT 24 174763108 ps
T125 /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_intg_err.1430214874 May 19 12:53:18 PM PDT 24 May 19 12:54:01 PM PDT 24 223293743 ps
T464 /workspace/coverage/cover_reg_top/16.rom_ctrl_same_csr_outstanding.1925518410 May 19 12:53:28 PM PDT 24 May 19 12:53:34 PM PDT 24 333752168 ps

Test location /workspace/coverage/default/40.rom_ctrl_corrupt_sig_fatal_chk.2413682749
Short name T3
Test name
Test status
Simulation time 115416346813 ps
CPU time 233.76 seconds
Started May 19 12:54:09 PM PDT 24
Finished May 19 12:58:06 PM PDT 24
Peak memory 213456 kb
Host smart-c31d4384-abec-4e97-9402-2d28edb03206
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2413682749 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_
corrupt_sig_fatal_chk.2413682749
Directory /workspace/40.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/24.rom_ctrl_stress_all_with_rand_reset.3500327138
Short name T17
Test name
Test status
Simulation time 95104077253 ps
CPU time 1779.77 seconds
Started May 19 12:54:00 PM PDT 24
Finished May 19 01:23:42 PM PDT 24
Peak memory 235148 kb
Host smart-dfd001e2-1d63-4fcd-9ee3-470aee693456
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3500327138 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_stress_all_with_rand_reset.3500327138
Directory /workspace/24.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/17.rom_ctrl_corrupt_sig_fatal_chk.2308124062
Short name T25
Test name
Test status
Simulation time 29221992331 ps
CPU time 343.26 seconds
Started May 19 12:53:53 PM PDT 24
Finished May 19 12:59:40 PM PDT 24
Peak memory 224756 kb
Host smart-dc980578-09a5-4c67-814a-c84a41b56c09
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2308124062 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_
corrupt_sig_fatal_chk.2308124062
Directory /workspace/17.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/5.rom_ctrl_smoke.1231315649
Short name T6
Test name
Test status
Simulation time 10290095241 ps
CPU time 25.85 seconds
Started May 19 12:53:39 PM PDT 24
Finished May 19 12:54:06 PM PDT 24
Peak memory 214116 kb
Host smart-9424ad18-1feb-495d-98fa-b10c8e0f98b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1231315649 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_smoke.1231315649
Directory /workspace/5.rom_ctrl_smoke/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_intg_err.962143226
Short name T58
Test name
Test status
Simulation time 1343223020 ps
CPU time 75.59 seconds
Started May 19 12:53:19 PM PDT 24
Finished May 19 12:54:38 PM PDT 24
Peak memory 212164 kb
Host smart-910e4a78-f9c6-4e8b-9e65-fb2e0aadcd22
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=962143226 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_tl_in
tg_err.962143226
Directory /workspace/11.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/3.rom_ctrl_sec_cm.3664095193
Short name T32
Test name
Test status
Simulation time 298163840 ps
CPU time 60.08 seconds
Started May 19 12:53:43 PM PDT 24
Finished May 19 12:54:45 PM PDT 24
Peak memory 240592 kb
Host smart-2e324053-d4de-4136-80ac-cb3c83f55a5b
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3664095193 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_sec_cm.3664095193
Directory /workspace/3.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_passthru_mem_tl_intg_err.3036069486
Short name T71
Test name
Test status
Simulation time 24107856633 ps
CPU time 93.16 seconds
Started May 19 12:53:13 PM PDT 24
Finished May 19 12:54:52 PM PDT 24
Peak memory 211308 kb
Host smart-3b75840d-ba6a-4d1c-8cfb-1deb49bfaa50
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3036069486 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_p
assthru_mem_tl_intg_err.3036069486
Directory /workspace/15.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_intg_err.1165360293
Short name T119
Test name
Test status
Simulation time 7535652774 ps
CPU time 46.43 seconds
Started May 19 12:53:19 PM PDT 24
Finished May 19 12:54:09 PM PDT 24
Peak memory 212340 kb
Host smart-276dd8a5-f8c6-4d8b-b389-b91d45b60c4b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1165360293 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_tl_i
ntg_err.1165360293
Directory /workspace/15.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/30.rom_ctrl_alert_test.2488480074
Short name T36
Test name
Test status
Simulation time 11333017598 ps
CPU time 16.27 seconds
Started May 19 12:53:59 PM PDT 24
Finished May 19 12:54:18 PM PDT 24
Peak memory 211584 kb
Host smart-2fc19c3d-99de-48f1-8b6a-b102d908bea1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2488480074 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_alert_test.2488480074
Directory /workspace/30.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/29.rom_ctrl_kmac_err_chk.1193503377
Short name T2
Test name
Test status
Simulation time 4500455233 ps
CPU time 24.22 seconds
Started May 19 12:53:56 PM PDT 24
Finished May 19 12:54:24 PM PDT 24
Peak memory 212264 kb
Host smart-5ae72bcc-ec11-4e08-9e89-2575999c718e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1193503377 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_kmac_err_chk.1193503377
Directory /workspace/29.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/10.rom_ctrl_kmac_err_chk.2107891163
Short name T179
Test name
Test status
Simulation time 175650458 ps
CPU time 9.77 seconds
Started May 19 12:53:48 PM PDT 24
Finished May 19 12:53:59 PM PDT 24
Peak memory 211976 kb
Host smart-d774137d-7251-4501-80a5-eb2c39b9b6e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2107891163 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_kmac_err_chk.2107891163
Directory /workspace/10.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/47.rom_ctrl_stress_all_with_rand_reset.561336690
Short name T19
Test name
Test status
Simulation time 147670274599 ps
CPU time 911.05 seconds
Started May 19 12:54:13 PM PDT 24
Finished May 19 01:09:30 PM PDT 24
Peak memory 235872 kb
Host smart-14051f2d-4c2e-4078-ae11-541b99bce02a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=561336690 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_stress_all_with_rand_reset.561336690
Directory /workspace/47.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.rom_ctrl_kmac_err_chk.205144300
Short name T10
Test name
Test status
Simulation time 1570811888 ps
CPU time 14.66 seconds
Started May 19 12:54:12 PM PDT 24
Finished May 19 12:54:32 PM PDT 24
Peak memory 211244 kb
Host smart-a21a79f5-9b0c-453d-9a75-1a08db00aa7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=205144300 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_kmac_err_chk.205144300
Directory /workspace/33.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_intg_err.2114573701
Short name T112
Test name
Test status
Simulation time 2302798962 ps
CPU time 73.06 seconds
Started May 19 12:53:17 PM PDT 24
Finished May 19 12:54:35 PM PDT 24
Peak memory 219376 kb
Host smart-ef37276d-8846-4433-aa67-b052baa45b0c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2114573701 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_tl_i
ntg_err.2114573701
Directory /workspace/10.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/19.rom_ctrl_corrupt_sig_fatal_chk.4198108246
Short name T39
Test name
Test status
Simulation time 19461280961 ps
CPU time 224.15 seconds
Started May 19 12:53:53 PM PDT 24
Finished May 19 12:57:41 PM PDT 24
Peak memory 237920 kb
Host smart-8b9eb8f7-61d6-4e1a-8741-8a00f52937d0
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4198108246 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_
corrupt_sig_fatal_chk.4198108246
Directory /workspace/19.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/16.rom_ctrl_max_throughput_chk.2559916811
Short name T13
Test name
Test status
Simulation time 6646644710 ps
CPU time 14.97 seconds
Started May 19 12:53:50 PM PDT 24
Finished May 19 12:54:07 PM PDT 24
Peak memory 211048 kb
Host smart-bf6cad0f-29f9-469b-9465-229b6efdfcd3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2559916811 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_max_throughput_chk.2559916811
Directory /workspace/16.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_passthru_mem_tl_intg_err.2271547456
Short name T84
Test name
Test status
Simulation time 7773299692 ps
CPU time 53.11 seconds
Started May 19 12:53:04 PM PDT 24
Finished May 19 12:54:02 PM PDT 24
Peak memory 211304 kb
Host smart-dd5ddbba-b8d7-49d8-bc38-db5b11713fa7
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2271547456 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_pa
ssthru_mem_tl_intg_err.2271547456
Directory /workspace/0.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_intg_err.2706093443
Short name T121
Test name
Test status
Simulation time 3251510441 ps
CPU time 71.24 seconds
Started May 19 12:53:14 PM PDT 24
Finished May 19 12:54:31 PM PDT 24
Peak memory 219508 kb
Host smart-e9a3a7cc-91d7-42d7-9564-2cc9d720a8a6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2706093443 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_tl_i
ntg_err.2706093443
Directory /workspace/13.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/1.rom_ctrl_smoke.1413508576
Short name T12
Test name
Test status
Simulation time 2703238976 ps
CPU time 28.47 seconds
Started May 19 12:53:24 PM PDT 24
Finished May 19 12:53:54 PM PDT 24
Peak memory 212904 kb
Host smart-45016ac5-6d48-4cc5-9a8c-d10600e60cd3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1413508576 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_smoke.1413508576
Directory /workspace/1.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/29.rom_ctrl_max_throughput_chk.1922060878
Short name T96
Test name
Test status
Simulation time 98439793 ps
CPU time 5.48 seconds
Started May 19 12:54:09 PM PDT 24
Finished May 19 12:54:18 PM PDT 24
Peak memory 210948 kb
Host smart-f31e2211-a021-4435-b0df-2c0fa9b80cb5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1922060878 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_max_throughput_chk.1922060878
Directory /workspace/29.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_aliasing.413820174
Short name T438
Test name
Test status
Simulation time 779126765 ps
CPU time 6.73 seconds
Started May 19 12:53:03 PM PDT 24
Finished May 19 12:53:14 PM PDT 24
Peak memory 211132 kb
Host smart-0f7abda3-91f9-49fc-a9f3-899bfde38376
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=413820174 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_alias
ing.413820174
Directory /workspace/0.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_bit_bash.1820872684
Short name T401
Test name
Test status
Simulation time 6031373757 ps
CPU time 12.84 seconds
Started May 19 12:53:13 PM PDT 24
Finished May 19 12:53:32 PM PDT 24
Peak memory 211232 kb
Host smart-ef76ca38-e482-4b58-93b6-4cac29f6a1d0
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1820872684 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_bit_
bash.1820872684
Directory /workspace/0.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_hw_reset.935367720
Short name T445
Test name
Test status
Simulation time 341101250 ps
CPU time 5.67 seconds
Started May 19 12:53:12 PM PDT 24
Finished May 19 12:53:23 PM PDT 24
Peak memory 211160 kb
Host smart-0a4f101f-eb01-41ba-b3e4-5566e90a6f5a
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=935367720 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_hw_re
set.935367720
Directory /workspace/0.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_mem_rw_with_rand_reset.2269350367
Short name T60
Test name
Test status
Simulation time 2452385320 ps
CPU time 7.05 seconds
Started May 19 12:53:13 PM PDT 24
Finished May 19 12:53:26 PM PDT 24
Peak memory 219428 kb
Host smart-648ea8cc-b300-480e-bbcc-c243033f575c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2269350367 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 0.rom_ctrl_csr_mem_rw_with_rand_reset.2269350367
Directory /workspace/0.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_rw.1753748256
Short name T444
Test name
Test status
Simulation time 1167758350 ps
CPU time 11.06 seconds
Started May 19 12:53:05 PM PDT 24
Finished May 19 12:53:20 PM PDT 24
Peak memory 211244 kb
Host smart-b6d559a6-fde6-4881-9455-e6862854484b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1753748256 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_rw.1753748256
Directory /workspace/0.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_partial_access.2790771908
Short name T454
Test name
Test status
Simulation time 103655854 ps
CPU time 4.07 seconds
Started May 19 12:53:01 PM PDT 24
Finished May 19 12:53:09 PM PDT 24
Peak memory 211020 kb
Host smart-148ebc5d-706c-4ce2-8ec2-22a9c27d40b9
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2790771908 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctr
l_mem_partial_access.2790771908
Directory /workspace/0.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_walk.4171734329
Short name T424
Test name
Test status
Simulation time 3569802972 ps
CPU time 14.59 seconds
Started May 19 12:53:17 PM PDT 24
Finished May 19 12:53:36 PM PDT 24
Peak memory 211228 kb
Host smart-1ce91d12-b43b-4961-9f9d-f45736fdaccf
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4171734329 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_mem_walk
.4171734329
Directory /workspace/0.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_same_csr_outstanding.2766810186
Short name T106
Test name
Test status
Simulation time 19499473809 ps
CPU time 14.46 seconds
Started May 19 12:53:12 PM PDT 24
Finished May 19 12:53:32 PM PDT 24
Peak memory 211188 kb
Host smart-a64a3143-3bb7-4b59-b766-278fcb4a02e2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2766810186 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_c
trl_same_csr_outstanding.2766810186
Directory /workspace/0.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_errors.3977077041
Short name T404
Test name
Test status
Simulation time 955021725 ps
CPU time 14.64 seconds
Started May 19 12:53:02 PM PDT 24
Finished May 19 12:53:21 PM PDT 24
Peak memory 219524 kb
Host smart-d036adc8-1a3a-4623-ba4a-ea22aec54c34
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3977077041 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_tl_errors.3977077041
Directory /workspace/0.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_intg_err.2393492017
Short name T459
Test name
Test status
Simulation time 884155683 ps
CPU time 36.69 seconds
Started May 19 12:53:11 PM PDT 24
Finished May 19 12:53:53 PM PDT 24
Peak memory 212152 kb
Host smart-648ccecc-ea25-4508-a3d2-6aac87c8fb17
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2393492017 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_tl_in
tg_err.2393492017
Directory /workspace/0.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_aliasing.1019889276
Short name T88
Test name
Test status
Simulation time 6403224619 ps
CPU time 13.35 seconds
Started May 19 12:53:12 PM PDT 24
Finished May 19 12:53:31 PM PDT 24
Peak memory 211324 kb
Host smart-8a5ad510-0385-4e34-b0e9-8bcd1fb60128
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1019889276 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_alia
sing.1019889276
Directory /workspace/1.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_bit_bash.3754802153
Short name T461
Test name
Test status
Simulation time 11266631358 ps
CPU time 10.37 seconds
Started May 19 12:53:17 PM PDT 24
Finished May 19 12:53:32 PM PDT 24
Peak memory 211240 kb
Host smart-06f66253-a4ce-49e8-b31c-7e98f70c3f4f
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3754802153 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_bit_
bash.3754802153
Directory /workspace/1.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_hw_reset.663655792
Short name T66
Test name
Test status
Simulation time 6409713261 ps
CPU time 12.33 seconds
Started May 19 12:53:08 PM PDT 24
Finished May 19 12:53:25 PM PDT 24
Peak memory 211180 kb
Host smart-d94381e5-62e8-473c-abc8-e3a501e91a3c
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=663655792 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_hw_re
set.663655792
Directory /workspace/1.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_mem_rw_with_rand_reset.1532005172
Short name T386
Test name
Test status
Simulation time 821651776 ps
CPU time 8.08 seconds
Started May 19 12:53:31 PM PDT 24
Finished May 19 12:53:40 PM PDT 24
Peak memory 219372 kb
Host smart-6914b407-f3a6-4037-a5bb-2dd3fad0b84d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1532005172 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 1.rom_ctrl_csr_mem_rw_with_rand_reset.1532005172
Directory /workspace/1.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_rw.1176095908
Short name T406
Test name
Test status
Simulation time 2132561004 ps
CPU time 16.96 seconds
Started May 19 12:53:17 PM PDT 24
Finished May 19 12:53:39 PM PDT 24
Peak memory 211112 kb
Host smart-e5e5e0c5-38b9-43e5-907a-5a4b60e6adf0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1176095908 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_rw.1176095908
Directory /workspace/1.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_partial_access.1634159460
Short name T427
Test name
Test status
Simulation time 1287754834 ps
CPU time 8.31 seconds
Started May 19 12:53:12 PM PDT 24
Finished May 19 12:53:26 PM PDT 24
Peak memory 211052 kb
Host smart-9abb334f-8691-4ee5-86fc-2d83c03be7ae
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1634159460 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctr
l_mem_partial_access.1634159460
Directory /workspace/1.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_walk.397515418
Short name T447
Test name
Test status
Simulation time 232241202 ps
CPU time 4.05 seconds
Started May 19 12:53:05 PM PDT 24
Finished May 19 12:53:13 PM PDT 24
Peak memory 211204 kb
Host smart-a5b5bbc6-03c3-4615-a63f-62e627af6f1e
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=397515418 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_mem_walk.
397515418
Directory /workspace/1.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_passthru_mem_tl_intg_err.1892082486
Short name T87
Test name
Test status
Simulation time 13762193729 ps
CPU time 38.58 seconds
Started May 19 12:53:12 PM PDT 24
Finished May 19 12:53:56 PM PDT 24
Peak memory 211264 kb
Host smart-b682b578-a529-4ec1-8fca-9f5091c5aa3a
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1892082486 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_pa
ssthru_mem_tl_intg_err.1892082486
Directory /workspace/1.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_same_csr_outstanding.172892925
Short name T425
Test name
Test status
Simulation time 21366951670 ps
CPU time 10.61 seconds
Started May 19 12:53:17 PM PDT 24
Finished May 19 12:53:32 PM PDT 24
Peak memory 211296 kb
Host smart-86ed948c-dc1d-44f3-9022-d590b6d3cf9b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=172892925 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ct
rl_same_csr_outstanding.172892925
Directory /workspace/1.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_errors.398667056
Short name T382
Test name
Test status
Simulation time 2630475488 ps
CPU time 12.82 seconds
Started May 19 12:53:09 PM PDT 24
Finished May 19 12:53:27 PM PDT 24
Peak memory 219484 kb
Host smart-1e7310d0-74d3-462e-8262-dacb5f7acca3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=398667056 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_tl_errors.398667056
Directory /workspace/1.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_intg_err.2043664061
Short name T115
Test name
Test status
Simulation time 801508003 ps
CPU time 68.51 seconds
Started May 19 12:53:04 PM PDT 24
Finished May 19 12:54:18 PM PDT 24
Peak memory 211304 kb
Host smart-0ea0a80d-66e3-4583-9c83-ffca87a6a3f4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2043664061 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_tl_in
tg_err.2043664061
Directory /workspace/1.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_mem_rw_with_rand_reset.3584593373
Short name T460
Test name
Test status
Simulation time 198876970 ps
CPU time 4.93 seconds
Started May 19 12:53:13 PM PDT 24
Finished May 19 12:53:24 PM PDT 24
Peak memory 214296 kb
Host smart-4d2e3fcd-ee0a-41c9-bc49-bf06227c6913
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3584593373 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 10.rom_ctrl_csr_mem_rw_with_rand_reset.3584593373
Directory /workspace/10.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_rw.907451209
Short name T446
Test name
Test status
Simulation time 211951774 ps
CPU time 5.75 seconds
Started May 19 12:53:25 PM PDT 24
Finished May 19 12:53:32 PM PDT 24
Peak memory 211212 kb
Host smart-9beaad9b-3c2c-43b0-ba0c-7e9343395f2d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=907451209 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_csr_rw.907451209
Directory /workspace/10.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_passthru_mem_tl_intg_err.1556262750
Short name T94
Test name
Test status
Simulation time 5112838391 ps
CPU time 18.42 seconds
Started May 19 12:53:13 PM PDT 24
Finished May 19 12:53:37 PM PDT 24
Peak memory 211276 kb
Host smart-ca498ce7-f0e9-405b-9f69-6386c07be7b6
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1556262750 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_p
assthru_mem_tl_intg_err.1556262750
Directory /workspace/10.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_same_csr_outstanding.1357306870
Short name T109
Test name
Test status
Simulation time 1190054998 ps
CPU time 11.93 seconds
Started May 19 12:53:17 PM PDT 24
Finished May 19 12:53:33 PM PDT 24
Peak memory 211260 kb
Host smart-d4ab07f9-069e-4ce3-b147-9b97030c1614
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1357306870 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_
ctrl_same_csr_outstanding.1357306870
Directory /workspace/10.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_errors.1844484841
Short name T431
Test name
Test status
Simulation time 2212603221 ps
CPU time 13.05 seconds
Started May 19 12:53:19 PM PDT 24
Finished May 19 12:53:36 PM PDT 24
Peak memory 219836 kb
Host smart-f0397f26-7c33-4bfb-9e6e-542f92eadd54
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1844484841 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_tl_errors.1844484841
Directory /workspace/10.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_mem_rw_with_rand_reset.2498246191
Short name T392
Test name
Test status
Simulation time 391440211 ps
CPU time 4.83 seconds
Started May 19 12:53:19 PM PDT 24
Finished May 19 12:53:28 PM PDT 24
Peak memory 214360 kb
Host smart-44998389-08ac-4da5-a931-383533750922
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2498246191 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 11.rom_ctrl_csr_mem_rw_with_rand_reset.2498246191
Directory /workspace/11.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_rw.3477637263
Short name T416
Test name
Test status
Simulation time 12995914902 ps
CPU time 12.96 seconds
Started May 19 12:53:19 PM PDT 24
Finished May 19 12:53:36 PM PDT 24
Peak memory 211268 kb
Host smart-79885a05-ca1f-4f92-8c49-8e14e9e770e5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3477637263 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_csr_rw.3477637263
Directory /workspace/11.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_passthru_mem_tl_intg_err.2535378424
Short name T68
Test name
Test status
Simulation time 24726292563 ps
CPU time 52.51 seconds
Started May 19 12:53:17 PM PDT 24
Finished May 19 12:54:18 PM PDT 24
Peak memory 211364 kb
Host smart-69a9bd57-2304-45c5-8214-cbdf5c6a109a
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2535378424 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_p
assthru_mem_tl_intg_err.2535378424
Directory /workspace/11.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_same_csr_outstanding.1302670481
Short name T67
Test name
Test status
Simulation time 2083990837 ps
CPU time 17.05 seconds
Started May 19 12:53:25 PM PDT 24
Finished May 19 12:53:44 PM PDT 24
Peak memory 211244 kb
Host smart-0fd20cdb-47ae-4d27-b411-2112131289ab
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1302670481 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_
ctrl_same_csr_outstanding.1302670481
Directory /workspace/11.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_errors.4025146951
Short name T393
Test name
Test status
Simulation time 6876379776 ps
CPU time 16.01 seconds
Started May 19 12:53:38 PM PDT 24
Finished May 19 12:53:54 PM PDT 24
Peak memory 219420 kb
Host smart-6b243c15-d37f-4ca3-aee7-f85214217525
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4025146951 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_tl_errors.4025146951
Directory /workspace/11.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_mem_rw_with_rand_reset.415068848
Short name T408
Test name
Test status
Simulation time 737977879 ps
CPU time 8.97 seconds
Started May 19 12:53:14 PM PDT 24
Finished May 19 12:53:28 PM PDT 24
Peak memory 219488 kb
Host smart-a16a9984-56a9-4b4f-8a75-c4dc6d7d7f8d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=415068848 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 12.rom_ctrl_csr_mem_rw_with_rand_reset.415068848
Directory /workspace/12.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_rw.643549267
Short name T83
Test name
Test status
Simulation time 1097189635 ps
CPU time 10.9 seconds
Started May 19 12:53:18 PM PDT 24
Finished May 19 12:53:33 PM PDT 24
Peak memory 211112 kb
Host smart-25bd59f5-32fd-484f-8809-80cd444524ee
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=643549267 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_csr_rw.643549267
Directory /workspace/12.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_passthru_mem_tl_intg_err.3146392900
Short name T415
Test name
Test status
Simulation time 2163735892 ps
CPU time 28.08 seconds
Started May 19 12:53:21 PM PDT 24
Finished May 19 12:53:52 PM PDT 24
Peak memory 211332 kb
Host smart-3f7025f3-faa7-4dfd-a4ec-ad8f87586daf
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3146392900 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_p
assthru_mem_tl_intg_err.3146392900
Directory /workspace/12.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_same_csr_outstanding.1093782348
Short name T399
Test name
Test status
Simulation time 1836874083 ps
CPU time 16.53 seconds
Started May 19 12:53:14 PM PDT 24
Finished May 19 12:53:36 PM PDT 24
Peak memory 211164 kb
Host smart-5e37ea04-eed3-4339-aeec-8c8fc5ab5403
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1093782348 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_
ctrl_same_csr_outstanding.1093782348
Directory /workspace/12.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_errors.3878513513
Short name T420
Test name
Test status
Simulation time 22227845132 ps
CPU time 18.19 seconds
Started May 19 12:53:19 PM PDT 24
Finished May 19 12:53:41 PM PDT 24
Peak memory 215880 kb
Host smart-f3a15021-8cc5-4a2b-bdd2-940d18f8531c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3878513513 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_tl_errors.3878513513
Directory /workspace/12.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_intg_err.3022875535
Short name T120
Test name
Test status
Simulation time 1093353791 ps
CPU time 73.53 seconds
Started May 19 12:53:19 PM PDT 24
Finished May 19 12:54:36 PM PDT 24
Peak memory 213276 kb
Host smart-3d14b917-f2d7-4db1-a199-415dd8d25cac
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3022875535 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_tl_i
ntg_err.3022875535
Directory /workspace/12.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_mem_rw_with_rand_reset.1482620602
Short name T407
Test name
Test status
Simulation time 2336640264 ps
CPU time 9.42 seconds
Started May 19 12:53:29 PM PDT 24
Finished May 19 12:53:40 PM PDT 24
Peak memory 213412 kb
Host smart-6b8af645-3e6a-4c20-945c-a13327dfc97d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1482620602 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 13.rom_ctrl_csr_mem_rw_with_rand_reset.1482620602
Directory /workspace/13.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_rw.3233322539
Short name T375
Test name
Test status
Simulation time 4263422131 ps
CPU time 16.26 seconds
Started May 19 12:53:41 PM PDT 24
Finished May 19 12:53:59 PM PDT 24
Peak memory 211196 kb
Host smart-437f0307-edd6-4870-8022-059d012ddb17
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3233322539 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_csr_rw.3233322539
Directory /workspace/13.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_passthru_mem_tl_intg_err.3297841739
Short name T72
Test name
Test status
Simulation time 4491057798 ps
CPU time 27.97 seconds
Started May 19 12:53:20 PM PDT 24
Finished May 19 12:53:51 PM PDT 24
Peak memory 211252 kb
Host smart-acb22dca-a835-4e8c-bc2e-4413a4502a9a
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3297841739 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_p
assthru_mem_tl_intg_err.3297841739
Directory /workspace/13.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_same_csr_outstanding.1435761895
Short name T389
Test name
Test status
Simulation time 1860465917 ps
CPU time 14.98 seconds
Started May 19 12:53:17 PM PDT 24
Finished May 19 12:53:37 PM PDT 24
Peak memory 211144 kb
Host smart-259803f0-378a-44f2-8f53-ef1f7e47d95b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1435761895 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_
ctrl_same_csr_outstanding.1435761895
Directory /workspace/13.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_errors.2638181882
Short name T419
Test name
Test status
Simulation time 23698770191 ps
CPU time 17.6 seconds
Started May 19 12:53:13 PM PDT 24
Finished May 19 12:53:36 PM PDT 24
Peak memory 219608 kb
Host smart-397c510a-ee9c-482f-bf73-d541886a1be5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2638181882 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_tl_errors.2638181882
Directory /workspace/13.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_mem_rw_with_rand_reset.3026379874
Short name T462
Test name
Test status
Simulation time 374878310 ps
CPU time 4.6 seconds
Started May 19 12:53:19 PM PDT 24
Finished May 19 12:53:28 PM PDT 24
Peak memory 213312 kb
Host smart-029d0dea-0d85-451c-9041-953a8ed7e2fb
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3026379874 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 14.rom_ctrl_csr_mem_rw_with_rand_reset.3026379874
Directory /workspace/14.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_rw.2373705719
Short name T73
Test name
Test status
Simulation time 7567327161 ps
CPU time 13.73 seconds
Started May 19 12:53:24 PM PDT 24
Finished May 19 12:53:39 PM PDT 24
Peak memory 211312 kb
Host smart-a6edd26d-6ff8-4a2a-9aa2-6985064036cf
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2373705719 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_csr_rw.2373705719
Directory /workspace/14.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_passthru_mem_tl_intg_err.2723588916
Short name T91
Test name
Test status
Simulation time 17464107777 ps
CPU time 65.77 seconds
Started May 19 12:53:18 PM PDT 24
Finished May 19 12:54:28 PM PDT 24
Peak memory 211324 kb
Host smart-074a9a34-1645-4758-a831-de679586608d
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2723588916 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_p
assthru_mem_tl_intg_err.2723588916
Directory /workspace/14.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_same_csr_outstanding.1038834871
Short name T458
Test name
Test status
Simulation time 87520041 ps
CPU time 4.46 seconds
Started May 19 12:53:26 PM PDT 24
Finished May 19 12:53:32 PM PDT 24
Peak memory 211180 kb
Host smart-64687430-4cb7-4ad4-b156-d9fa0e449423
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1038834871 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_
ctrl_same_csr_outstanding.1038834871
Directory /workspace/14.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_errors.306861605
Short name T429
Test name
Test status
Simulation time 1632574149 ps
CPU time 16.72 seconds
Started May 19 12:53:19 PM PDT 24
Finished May 19 12:53:39 PM PDT 24
Peak memory 219776 kb
Host smart-c2c561f3-a92b-4ad0-a377-928648232f37
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=306861605 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_tl_errors.306861605
Directory /workspace/14.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_intg_err.1279436062
Short name T117
Test name
Test status
Simulation time 2026799369 ps
CPU time 47.77 seconds
Started May 19 12:53:18 PM PDT 24
Finished May 19 12:54:10 PM PDT 24
Peak memory 212960 kb
Host smart-07d42008-7dcd-4278-b3bc-435b180c8968
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1279436062 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_tl_i
ntg_err.1279436062
Directory /workspace/14.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_mem_rw_with_rand_reset.1196803257
Short name T426
Test name
Test status
Simulation time 92244199 ps
CPU time 4.57 seconds
Started May 19 12:53:27 PM PDT 24
Finished May 19 12:53:33 PM PDT 24
Peak memory 212044 kb
Host smart-12ef3c9e-c32b-4dc9-b925-572ecf4cc30c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1196803257 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 15.rom_ctrl_csr_mem_rw_with_rand_reset.1196803257
Directory /workspace/15.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_rw.590514319
Short name T374
Test name
Test status
Simulation time 308624272 ps
CPU time 4.13 seconds
Started May 19 12:53:22 PM PDT 24
Finished May 19 12:53:29 PM PDT 24
Peak memory 211204 kb
Host smart-74cd8b56-dd6c-433a-9076-19e3a2acccda
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=590514319 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_csr_rw.590514319
Directory /workspace/15.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_same_csr_outstanding.1172745790
Short name T107
Test name
Test status
Simulation time 19742604100 ps
CPU time 15.82 seconds
Started May 19 12:53:30 PM PDT 24
Finished May 19 12:53:47 PM PDT 24
Peak memory 210656 kb
Host smart-5fa40885-06a8-47c1-bcef-93e89e763eb9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1172745790 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_
ctrl_same_csr_outstanding.1172745790
Directory /workspace/15.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_errors.3366117124
Short name T391
Test name
Test status
Simulation time 1450709471 ps
CPU time 16.88 seconds
Started May 19 12:53:25 PM PDT 24
Finished May 19 12:53:43 PM PDT 24
Peak memory 219496 kb
Host smart-64c0d1cb-066f-4f80-9065-ac109e130782
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3366117124 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_tl_errors.3366117124
Directory /workspace/15.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_mem_rw_with_rand_reset.896483941
Short name T437
Test name
Test status
Simulation time 6738145191 ps
CPU time 13.99 seconds
Started May 19 12:53:21 PM PDT 24
Finished May 19 12:53:38 PM PDT 24
Peak memory 219464 kb
Host smart-606d74c3-11bb-43d7-b01d-bf50c4704a4f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=896483941 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 16.rom_ctrl_csr_mem_rw_with_rand_reset.896483941
Directory /workspace/16.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_rw.1589807346
Short name T413
Test name
Test status
Simulation time 2174453213 ps
CPU time 10.93 seconds
Started May 19 12:53:22 PM PDT 24
Finished May 19 12:53:35 PM PDT 24
Peak memory 211172 kb
Host smart-fdf0e808-49ab-496a-af27-c28f932d45a9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1589807346 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_csr_rw.1589807346
Directory /workspace/16.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_passthru_mem_tl_intg_err.1311134892
Short name T441
Test name
Test status
Simulation time 16461114704 ps
CPU time 74.5 seconds
Started May 19 12:53:32 PM PDT 24
Finished May 19 12:54:47 PM PDT 24
Peak memory 211340 kb
Host smart-96d1e60c-5ced-458c-96bb-1e5e36cf6b32
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1311134892 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_p
assthru_mem_tl_intg_err.1311134892
Directory /workspace/16.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_same_csr_outstanding.1925518410
Short name T464
Test name
Test status
Simulation time 333752168 ps
CPU time 4.4 seconds
Started May 19 12:53:28 PM PDT 24
Finished May 19 12:53:34 PM PDT 24
Peak memory 211104 kb
Host smart-4be17894-6720-4ad3-8548-ca77832941bd
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1925518410 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_
ctrl_same_csr_outstanding.1925518410
Directory /workspace/16.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_errors.1225677361
Short name T377
Test name
Test status
Simulation time 175566369 ps
CPU time 8.05 seconds
Started May 19 12:53:14 PM PDT 24
Finished May 19 12:53:28 PM PDT 24
Peak memory 219416 kb
Host smart-d259add6-23fc-4de4-a253-fb4994640522
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1225677361 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_tl_errors.1225677361
Directory /workspace/16.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_intg_err.3831283444
Short name T422
Test name
Test status
Simulation time 1725678011 ps
CPU time 76.98 seconds
Started May 19 12:53:19 PM PDT 24
Finished May 19 12:54:40 PM PDT 24
Peak memory 212484 kb
Host smart-de7369bc-ccd3-4881-ad36-100ccc39ec13
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3831283444 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_tl_i
ntg_err.3831283444
Directory /workspace/16.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_mem_rw_with_rand_reset.1576021142
Short name T367
Test name
Test status
Simulation time 254963312 ps
CPU time 4.68 seconds
Started May 19 12:53:39 PM PDT 24
Finished May 19 12:53:44 PM PDT 24
Peak memory 213296 kb
Host smart-694bc4df-d998-4a2a-ba9f-dc1160896810
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1576021142 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 17.rom_ctrl_csr_mem_rw_with_rand_reset.1576021142
Directory /workspace/17.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_rw.3274195039
Short name T61
Test name
Test status
Simulation time 743067548 ps
CPU time 8.75 seconds
Started May 19 12:53:39 PM PDT 24
Finished May 19 12:53:49 PM PDT 24
Peak memory 211224 kb
Host smart-65b8f1ee-5930-49f6-aab0-180fd20dd5b2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3274195039 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_csr_rw.3274195039
Directory /workspace/17.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_passthru_mem_tl_intg_err.2472792483
Short name T92
Test name
Test status
Simulation time 9144930265 ps
CPU time 50.64 seconds
Started May 19 12:53:15 PM PDT 24
Finished May 19 12:54:11 PM PDT 24
Peak memory 211248 kb
Host smart-07f500a3-07c9-4bcd-8628-49d21f1f7acc
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2472792483 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_p
assthru_mem_tl_intg_err.2472792483
Directory /workspace/17.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_same_csr_outstanding.4043105961
Short name T448
Test name
Test status
Simulation time 1181587182 ps
CPU time 4.34 seconds
Started May 19 12:53:30 PM PDT 24
Finished May 19 12:53:35 PM PDT 24
Peak memory 211100 kb
Host smart-b30873e3-30cb-4400-9afb-9ea7e16f408b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4043105961 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_
ctrl_same_csr_outstanding.4043105961
Directory /workspace/17.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_errors.3508812403
Short name T443
Test name
Test status
Simulation time 10778453640 ps
CPU time 18.97 seconds
Started May 19 12:53:34 PM PDT 24
Finished May 19 12:53:54 PM PDT 24
Peak memory 219480 kb
Host smart-6b50ff3b-f339-4970-a462-f29ccd1f125b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3508812403 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_tl_errors.3508812403
Directory /workspace/17.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_intg_err.1913229873
Short name T118
Test name
Test status
Simulation time 5214764518 ps
CPU time 42.57 seconds
Started May 19 12:53:41 PM PDT 24
Finished May 19 12:54:25 PM PDT 24
Peak memory 212356 kb
Host smart-a924bb88-0a12-44de-9ec8-1f697c6946dd
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1913229873 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_tl_i
ntg_err.1913229873
Directory /workspace/17.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_mem_rw_with_rand_reset.3661301944
Short name T394
Test name
Test status
Simulation time 2521876382 ps
CPU time 8.85 seconds
Started May 19 12:53:43 PM PDT 24
Finished May 19 12:53:54 PM PDT 24
Peak memory 219432 kb
Host smart-b63b8ab8-eecb-450e-bc1a-6a5fd400d12b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3661301944 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 18.rom_ctrl_csr_mem_rw_with_rand_reset.3661301944
Directory /workspace/18.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_rw.2173295883
Short name T70
Test name
Test status
Simulation time 2554663899 ps
CPU time 8.05 seconds
Started May 19 12:53:24 PM PDT 24
Finished May 19 12:53:33 PM PDT 24
Peak memory 211268 kb
Host smart-c919f867-05c4-44c9-b472-0b576d1e742c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2173295883 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_csr_rw.2173295883
Directory /workspace/18.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_passthru_mem_tl_intg_err.1123521347
Short name T398
Test name
Test status
Simulation time 65261378000 ps
CPU time 80.13 seconds
Started May 19 12:53:42 PM PDT 24
Finished May 19 12:55:04 PM PDT 24
Peak memory 211356 kb
Host smart-36f3f49b-754f-48a2-9c36-06cdfe9692fe
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1123521347 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_p
assthru_mem_tl_intg_err.1123521347
Directory /workspace/18.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_same_csr_outstanding.502534030
Short name T421
Test name
Test status
Simulation time 1506090056 ps
CPU time 13.31 seconds
Started May 19 12:53:29 PM PDT 24
Finished May 19 12:53:43 PM PDT 24
Peak memory 211492 kb
Host smart-0b1ddc31-cb76-4064-aee7-9aeed399a87e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=502534030 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_c
trl_same_csr_outstanding.502534030
Directory /workspace/18.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_errors.3233040175
Short name T388
Test name
Test status
Simulation time 1694355291 ps
CPU time 16.57 seconds
Started May 19 12:53:39 PM PDT 24
Finished May 19 12:53:57 PM PDT 24
Peak memory 219488 kb
Host smart-7bc1e458-54bb-41aa-9559-73cb68ddf686
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3233040175 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_tl_errors.3233040175
Directory /workspace/18.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_intg_err.536942888
Short name T114
Test name
Test status
Simulation time 233936706 ps
CPU time 69.29 seconds
Started May 19 12:53:41 PM PDT 24
Finished May 19 12:54:53 PM PDT 24
Peak memory 212248 kb
Host smart-3d2ee07e-ace2-45b1-8cff-933fcbe28b74
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=536942888 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_tl_in
tg_err.536942888
Directory /workspace/18.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_mem_rw_with_rand_reset.2017804248
Short name T383
Test name
Test status
Simulation time 1299655851 ps
CPU time 7.29 seconds
Started May 19 12:53:25 PM PDT 24
Finished May 19 12:53:34 PM PDT 24
Peak memory 212360 kb
Host smart-466e22b2-4236-471e-ae90-bd63d4a718d9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2017804248 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 19.rom_ctrl_csr_mem_rw_with_rand_reset.2017804248
Directory /workspace/19.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_rw.3279671121
Short name T74
Test name
Test status
Simulation time 2316118111 ps
CPU time 11.1 seconds
Started May 19 12:53:26 PM PDT 24
Finished May 19 12:53:39 PM PDT 24
Peak memory 211272 kb
Host smart-8e33c725-679c-47f0-ac2c-16d6321f914f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3279671121 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_csr_rw.3279671121
Directory /workspace/19.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_passthru_mem_tl_intg_err.2426749105
Short name T410
Test name
Test status
Simulation time 4314612969 ps
CPU time 34.54 seconds
Started May 19 12:53:19 PM PDT 24
Finished May 19 12:53:58 PM PDT 24
Peak memory 211256 kb
Host smart-5407c948-3f8e-40f5-841b-2feeec0de6f5
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2426749105 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_p
assthru_mem_tl_intg_err.2426749105
Directory /workspace/19.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_same_csr_outstanding.3698372244
Short name T110
Test name
Test status
Simulation time 97927393 ps
CPU time 5.9 seconds
Started May 19 12:53:35 PM PDT 24
Finished May 19 12:53:43 PM PDT 24
Peak memory 211200 kb
Host smart-9f92afbd-6d8f-4d8c-8134-737d71e688b2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3698372244 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_
ctrl_same_csr_outstanding.3698372244
Directory /workspace/19.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_errors.2993700559
Short name T396
Test name
Test status
Simulation time 1159579657 ps
CPU time 11.97 seconds
Started May 19 12:53:25 PM PDT 24
Finished May 19 12:53:39 PM PDT 24
Peak memory 214744 kb
Host smart-7638de12-5b46-4586-a9af-2c2727bfcb97
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2993700559 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_tl_errors.2993700559
Directory /workspace/19.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_intg_err.1430214874
Short name T125
Test name
Test status
Simulation time 223293743 ps
CPU time 39.1 seconds
Started May 19 12:53:18 PM PDT 24
Finished May 19 12:54:01 PM PDT 24
Peak memory 212556 kb
Host smart-6d6e97b4-ddcf-41f8-a102-7d8deaca73ab
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1430214874 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_tl_i
ntg_err.1430214874
Directory /workspace/19.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_aliasing.1829360718
Short name T403
Test name
Test status
Simulation time 168679999 ps
CPU time 4.16 seconds
Started May 19 12:53:10 PM PDT 24
Finished May 19 12:53:20 PM PDT 24
Peak memory 211104 kb
Host smart-273ee2a7-6aec-46e3-83b4-4f7eb0274591
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1829360718 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_alia
sing.1829360718
Directory /workspace/2.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_bit_bash.1737254076
Short name T417
Test name
Test status
Simulation time 7236849730 ps
CPU time 14.9 seconds
Started May 19 12:53:12 PM PDT 24
Finished May 19 12:53:32 PM PDT 24
Peak memory 211204 kb
Host smart-a2994c78-bd66-43a0-aa56-74938ffa34e6
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1737254076 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_bit_
bash.1737254076
Directory /workspace/2.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_hw_reset.3302723965
Short name T390
Test name
Test status
Simulation time 4253148725 ps
CPU time 18.94 seconds
Started May 19 12:53:20 PM PDT 24
Finished May 19 12:53:42 PM PDT 24
Peak memory 211296 kb
Host smart-e101796a-c5d7-4678-a5db-88ec51fba1b6
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3302723965 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_hw_r
eset.3302723965
Directory /workspace/2.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_mem_rw_with_rand_reset.1283542627
Short name T457
Test name
Test status
Simulation time 1508133364 ps
CPU time 13.11 seconds
Started May 19 12:53:15 PM PDT 24
Finished May 19 12:53:34 PM PDT 24
Peak memory 219384 kb
Host smart-0ebed4f2-1841-47db-a61d-a8830b88ebe5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1283542627 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 2.rom_ctrl_csr_mem_rw_with_rand_reset.1283542627
Directory /workspace/2.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_rw.3304841432
Short name T369
Test name
Test status
Simulation time 6693307106 ps
CPU time 13.28 seconds
Started May 19 12:53:18 PM PDT 24
Finished May 19 12:53:35 PM PDT 24
Peak memory 211580 kb
Host smart-3c3f5179-35f6-4c10-b044-a51acaeb659b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3304841432 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_rw.3304841432
Directory /workspace/2.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_partial_access.1018802137
Short name T380
Test name
Test status
Simulation time 296778595 ps
CPU time 6.17 seconds
Started May 19 12:53:09 PM PDT 24
Finished May 19 12:53:21 PM PDT 24
Peak memory 211132 kb
Host smart-e4df1ee7-e20a-447c-80d2-e989a6aa7c59
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1018802137 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctr
l_mem_partial_access.1018802137
Directory /workspace/2.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_walk.2168865269
Short name T418
Test name
Test status
Simulation time 223477915 ps
CPU time 5.65 seconds
Started May 19 12:53:14 PM PDT 24
Finished May 19 12:53:25 PM PDT 24
Peak memory 211180 kb
Host smart-d878f53f-49ba-4f99-9d8d-d1cc88a4bc13
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2168865269 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_mem_walk
.2168865269
Directory /workspace/2.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_passthru_mem_tl_intg_err.1467427221
Short name T384
Test name
Test status
Simulation time 11817747797 ps
CPU time 93.45 seconds
Started May 19 12:53:20 PM PDT 24
Finished May 19 12:54:57 PM PDT 24
Peak memory 211340 kb
Host smart-c7d9a5a1-3ccf-4a58-ae05-19473bdfdfb9
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1467427221 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_pa
ssthru_mem_tl_intg_err.1467427221
Directory /workspace/2.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_same_csr_outstanding.866289056
Short name T456
Test name
Test status
Simulation time 8761562709 ps
CPU time 17.45 seconds
Started May 19 12:53:10 PM PDT 24
Finished May 19 12:53:33 PM PDT 24
Peak memory 211212 kb
Host smart-c8b9f648-fc5c-4066-9b50-97b87f5d9384
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=866289056 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ct
rl_same_csr_outstanding.866289056
Directory /workspace/2.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_errors.3420137425
Short name T414
Test name
Test status
Simulation time 248051268 ps
CPU time 8.79 seconds
Started May 19 12:53:13 PM PDT 24
Finished May 19 12:53:27 PM PDT 24
Peak memory 219428 kb
Host smart-a0cf4431-19fa-4aa5-8072-ced58d5c2a6e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3420137425 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_tl_errors.3420137425
Directory /workspace/2.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_intg_err.1697041961
Short name T113
Test name
Test status
Simulation time 5301170149 ps
CPU time 73.43 seconds
Started May 19 12:53:22 PM PDT 24
Finished May 19 12:54:38 PM PDT 24
Peak memory 219472 kb
Host smart-3c6b97d7-e945-46a9-a418-b357b11ad308
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1697041961 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_tl_in
tg_err.1697041961
Directory /workspace/2.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_aliasing.977372877
Short name T385
Test name
Test status
Simulation time 4092528954 ps
CPU time 16.44 seconds
Started May 19 12:53:11 PM PDT 24
Finished May 19 12:53:33 PM PDT 24
Peak memory 211216 kb
Host smart-ac58fa39-bbaa-4249-9a3e-79c3dbe1227a
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=977372877 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_alias
ing.977372877
Directory /workspace/3.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_bit_bash.3083111723
Short name T405
Test name
Test status
Simulation time 1625669742 ps
CPU time 9.71 seconds
Started May 19 12:53:17 PM PDT 24
Finished May 19 12:53:31 PM PDT 24
Peak memory 211164 kb
Host smart-26ab8aa2-8992-4ceb-8413-decc7706f398
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3083111723 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_bit_
bash.3083111723
Directory /workspace/3.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_hw_reset.1391617477
Short name T436
Test name
Test status
Simulation time 352166851 ps
CPU time 7.4 seconds
Started May 19 12:53:19 PM PDT 24
Finished May 19 12:53:30 PM PDT 24
Peak memory 211536 kb
Host smart-cdeb3654-9d7b-4a82-8e35-adeea7d9e79b
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1391617477 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_hw_r
eset.1391617477
Directory /workspace/3.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_mem_rw_with_rand_reset.3683991746
Short name T371
Test name
Test status
Simulation time 3362794893 ps
CPU time 6.84 seconds
Started May 19 12:53:12 PM PDT 24
Finished May 19 12:53:25 PM PDT 24
Peak memory 214576 kb
Host smart-edf6ba66-2a7c-43f2-bf20-660f704172e1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3683991746 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 3.rom_ctrl_csr_mem_rw_with_rand_reset.3683991746
Directory /workspace/3.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_rw.528452469
Short name T397
Test name
Test status
Simulation time 1733737054 ps
CPU time 14.53 seconds
Started May 19 12:53:14 PM PDT 24
Finished May 19 12:53:34 PM PDT 24
Peak memory 211224 kb
Host smart-4de596b2-b20a-4645-bc7b-7aeee7ad0c82
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=528452469 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_rw.528452469
Directory /workspace/3.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_partial_access.2603031024
Short name T449
Test name
Test status
Simulation time 4119330260 ps
CPU time 10.56 seconds
Started May 19 12:53:09 PM PDT 24
Finished May 19 12:53:25 PM PDT 24
Peak memory 211212 kb
Host smart-4e0cb68d-017c-474c-8e0e-4889130862e7
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2603031024 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctr
l_mem_partial_access.2603031024
Directory /workspace/3.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_walk.4019865211
Short name T435
Test name
Test status
Simulation time 171754916 ps
CPU time 4.07 seconds
Started May 19 12:53:14 PM PDT 24
Finished May 19 12:53:23 PM PDT 24
Peak memory 211076 kb
Host smart-4a008794-fc9f-4ae1-a125-3bc085e9889a
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4019865211 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_mem_walk
.4019865211
Directory /workspace/3.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_passthru_mem_tl_intg_err.1721505260
Short name T95
Test name
Test status
Simulation time 18520943120 ps
CPU time 47.19 seconds
Started May 19 12:53:06 PM PDT 24
Finished May 19 12:53:59 PM PDT 24
Peak memory 211228 kb
Host smart-9acfb7cf-cdf9-494b-b2a1-684c2d32c636
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1721505260 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_pa
ssthru_mem_tl_intg_err.1721505260
Directory /workspace/3.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_same_csr_outstanding.1165775012
Short name T463
Test name
Test status
Simulation time 174763108 ps
CPU time 4.2 seconds
Started May 19 12:53:19 PM PDT 24
Finished May 19 12:53:27 PM PDT 24
Peak memory 211192 kb
Host smart-1f06c62c-0f6a-4fea-803e-7387ffc43c6c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1165775012 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_c
trl_same_csr_outstanding.1165775012
Directory /workspace/3.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_errors.2507843749
Short name T434
Test name
Test status
Simulation time 536454185 ps
CPU time 9.44 seconds
Started May 19 12:53:19 PM PDT 24
Finished May 19 12:53:32 PM PDT 24
Peak memory 219340 kb
Host smart-ac85f100-c821-4002-b010-e0d797e71cef
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2507843749 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_tl_errors.2507843749
Directory /workspace/3.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_intg_err.1563994591
Short name T59
Test name
Test status
Simulation time 1579869978 ps
CPU time 75.26 seconds
Started May 19 12:53:11 PM PDT 24
Finished May 19 12:54:32 PM PDT 24
Peak memory 219476 kb
Host smart-be243b6f-3319-430e-bef1-9c41ac2890ac
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1563994591 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_tl_in
tg_err.1563994591
Directory /workspace/3.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_aliasing.303402198
Short name T89
Test name
Test status
Simulation time 1449970035 ps
CPU time 8.32 seconds
Started May 19 12:53:27 PM PDT 24
Finished May 19 12:53:36 PM PDT 24
Peak memory 211136 kb
Host smart-56b8205e-9893-469c-a0eb-1f377eb0b8ea
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=303402198 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_alias
ing.303402198
Directory /workspace/4.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_bit_bash.1962322949
Short name T402
Test name
Test status
Simulation time 347831244 ps
CPU time 4.52 seconds
Started May 19 12:53:13 PM PDT 24
Finished May 19 12:53:23 PM PDT 24
Peak memory 211120 kb
Host smart-d1d92397-2475-43c8-83c4-fd7b382987d2
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1962322949 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_bit_
bash.1962322949
Directory /workspace/4.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_hw_reset.3796604770
Short name T412
Test name
Test status
Simulation time 4539403541 ps
CPU time 10.24 seconds
Started May 19 12:53:14 PM PDT 24
Finished May 19 12:53:30 PM PDT 24
Peak memory 211256 kb
Host smart-9c0f39fb-f4b3-4e91-b686-fd08fe29f09e
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3796604770 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_hw_r
eset.3796604770
Directory /workspace/4.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_mem_rw_with_rand_reset.308052923
Short name T376
Test name
Test status
Simulation time 4216471328 ps
CPU time 11.94 seconds
Started May 19 12:53:15 PM PDT 24
Finished May 19 12:53:32 PM PDT 24
Peak memory 216668 kb
Host smart-f3f276cd-bacc-47b8-a8c9-8926430ca9e5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=308052923 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 4.rom_ctrl_csr_mem_rw_with_rand_reset.308052923
Directory /workspace/4.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_rw.1198701708
Short name T453
Test name
Test status
Simulation time 1208209064 ps
CPU time 6.19 seconds
Started May 19 12:53:16 PM PDT 24
Finished May 19 12:53:28 PM PDT 24
Peak memory 211104 kb
Host smart-82922df3-f602-4a54-8813-b77f99434af4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1198701708 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_rw.1198701708
Directory /workspace/4.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_partial_access.1333100628
Short name T432
Test name
Test status
Simulation time 9217025484 ps
CPU time 8.94 seconds
Started May 19 12:53:18 PM PDT 24
Finished May 19 12:53:31 PM PDT 24
Peak memory 211168 kb
Host smart-8e9a28a7-1c20-41d1-ac99-a2baa40c3b81
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1333100628 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctr
l_mem_partial_access.1333100628
Directory /workspace/4.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_walk.1877881933
Short name T381
Test name
Test status
Simulation time 3035461328 ps
CPU time 12.8 seconds
Started May 19 12:53:09 PM PDT 24
Finished May 19 12:53:27 PM PDT 24
Peak memory 211180 kb
Host smart-ae9432d4-b3c1-4cb8-9709-46c7b6d0c2b7
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1877881933 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_mem_walk
.1877881933
Directory /workspace/4.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_passthru_mem_tl_intg_err.1399528727
Short name T387
Test name
Test status
Simulation time 3631115737 ps
CPU time 41.42 seconds
Started May 19 12:53:09 PM PDT 24
Finished May 19 12:53:55 PM PDT 24
Peak memory 211568 kb
Host smart-4cfdaa84-85e6-419a-9aab-1292cb298398
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1399528727 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_pa
ssthru_mem_tl_intg_err.1399528727
Directory /workspace/4.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_same_csr_outstanding.747927836
Short name T108
Test name
Test status
Simulation time 561281352 ps
CPU time 5.97 seconds
Started May 19 12:53:13 PM PDT 24
Finished May 19 12:53:25 PM PDT 24
Peak memory 211224 kb
Host smart-a418ba83-5b79-4663-a3a8-df8ae6330ca6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=747927836 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ct
rl_same_csr_outstanding.747927836
Directory /workspace/4.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_errors.3335265180
Short name T409
Test name
Test status
Simulation time 1461411274 ps
CPU time 16.56 seconds
Started May 19 12:53:21 PM PDT 24
Finished May 19 12:53:40 PM PDT 24
Peak memory 219392 kb
Host smart-e978036c-8bea-4968-9931-634df7ebc432
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3335265180 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_tl_errors.3335265180
Directory /workspace/4.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_intg_err.108365772
Short name T57
Test name
Test status
Simulation time 4436010874 ps
CPU time 43.03 seconds
Started May 19 12:53:10 PM PDT 24
Finished May 19 12:53:59 PM PDT 24
Peak memory 212156 kb
Host smart-35f815db-0092-4b9d-a343-76199300628a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=108365772 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_tl_int
g_err.108365772
Directory /workspace/4.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_mem_rw_with_rand_reset.2237048841
Short name T379
Test name
Test status
Simulation time 3178046363 ps
CPU time 14.1 seconds
Started May 19 12:53:40 PM PDT 24
Finished May 19 12:53:55 PM PDT 24
Peak memory 219572 kb
Host smart-38c028eb-91ee-4ce0-974d-02e66e1a80cc
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2237048841 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 5.rom_ctrl_csr_mem_rw_with_rand_reset.2237048841
Directory /workspace/5.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_rw.2876627081
Short name T85
Test name
Test status
Simulation time 831097528 ps
CPU time 4.25 seconds
Started May 19 12:53:14 PM PDT 24
Finished May 19 12:53:24 PM PDT 24
Peak memory 211204 kb
Host smart-95ea26f7-0536-469e-90bb-dbcd9fc4ca27
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2876627081 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_csr_rw.2876627081
Directory /workspace/5.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_passthru_mem_tl_intg_err.3684985274
Short name T75
Test name
Test status
Simulation time 6246173687 ps
CPU time 54.09 seconds
Started May 19 12:53:10 PM PDT 24
Finished May 19 12:54:10 PM PDT 24
Peak memory 211268 kb
Host smart-d347f8db-0015-475e-8829-009eb50a3414
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3684985274 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_pa
ssthru_mem_tl_intg_err.3684985274
Directory /workspace/5.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_same_csr_outstanding.4117494311
Short name T439
Test name
Test status
Simulation time 89070684 ps
CPU time 4.37 seconds
Started May 19 12:53:19 PM PDT 24
Finished May 19 12:53:27 PM PDT 24
Peak memory 211236 kb
Host smart-f97e9c9f-acb4-4f9c-b56c-f84508f26339
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4117494311 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_c
trl_same_csr_outstanding.4117494311
Directory /workspace/5.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_errors.1753389083
Short name T451
Test name
Test status
Simulation time 4590195546 ps
CPU time 14.64 seconds
Started May 19 12:53:22 PM PDT 24
Finished May 19 12:53:39 PM PDT 24
Peak memory 219464 kb
Host smart-b92a1011-b087-4f31-9563-5a1dc570326a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1753389083 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_tl_errors.1753389083
Directory /workspace/5.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_intg_err.2725177552
Short name T122
Test name
Test status
Simulation time 2386121161 ps
CPU time 72.43 seconds
Started May 19 12:53:25 PM PDT 24
Finished May 19 12:54:39 PM PDT 24
Peak memory 212048 kb
Host smart-c602c88b-f852-40ef-9245-d525d92cbc1c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2725177552 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_tl_in
tg_err.2725177552
Directory /workspace/5.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_mem_rw_with_rand_reset.2192740104
Short name T452
Test name
Test status
Simulation time 345247941 ps
CPU time 4.56 seconds
Started May 19 12:53:22 PM PDT 24
Finished May 19 12:53:29 PM PDT 24
Peak memory 213816 kb
Host smart-cd593070-0e77-4788-8c49-1e008afc4559
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2192740104 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 6.rom_ctrl_csr_mem_rw_with_rand_reset.2192740104
Directory /workspace/6.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_rw.2285946213
Short name T395
Test name
Test status
Simulation time 333425416 ps
CPU time 4.12 seconds
Started May 19 12:53:10 PM PDT 24
Finished May 19 12:53:20 PM PDT 24
Peak memory 211120 kb
Host smart-b0853073-a6af-41a9-ab21-b02cf67f2c7e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2285946213 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_csr_rw.2285946213
Directory /workspace/6.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_passthru_mem_tl_intg_err.665922313
Short name T442
Test name
Test status
Simulation time 10842929731 ps
CPU time 87.52 seconds
Started May 19 12:53:22 PM PDT 24
Finished May 19 12:54:52 PM PDT 24
Peak memory 211224 kb
Host smart-ac52e9db-6eb4-4e53-a211-6a60a63b8b5a
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=665922313 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_pas
sthru_mem_tl_intg_err.665922313
Directory /workspace/6.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_same_csr_outstanding.1713890906
Short name T455
Test name
Test status
Simulation time 1432698931 ps
CPU time 12.92 seconds
Started May 19 12:53:13 PM PDT 24
Finished May 19 12:53:32 PM PDT 24
Peak memory 211280 kb
Host smart-6cfeda9f-dc78-4753-8ede-d6d6b9b322ac
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1713890906 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_c
trl_same_csr_outstanding.1713890906
Directory /workspace/6.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_errors.2680324755
Short name T440
Test name
Test status
Simulation time 2291441364 ps
CPU time 13.33 seconds
Started May 19 12:53:33 PM PDT 24
Finished May 19 12:53:47 PM PDT 24
Peak memory 219584 kb
Host smart-d6d72941-d0e0-4f42-a25c-207c518a7510
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2680324755 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_tl_errors.2680324755
Directory /workspace/6.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_intg_err.700912774
Short name T116
Test name
Test status
Simulation time 434996179 ps
CPU time 68.66 seconds
Started May 19 12:53:13 PM PDT 24
Finished May 19 12:54:27 PM PDT 24
Peak memory 212204 kb
Host smart-c8384ef3-da8b-4e86-bfb6-8f67d4dfedbf
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=700912774 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_tl_int
g_err.700912774
Directory /workspace/6.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_mem_rw_with_rand_reset.4232373482
Short name T378
Test name
Test status
Simulation time 2000200703 ps
CPU time 16.28 seconds
Started May 19 12:53:40 PM PDT 24
Finished May 19 12:53:57 PM PDT 24
Peak memory 219340 kb
Host smart-ba6bad54-1e15-4f4a-b89a-109130f8fd74
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4232373482 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 7.rom_ctrl_csr_mem_rw_with_rand_reset.4232373482
Directory /workspace/7.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_rw.1331947135
Short name T423
Test name
Test status
Simulation time 334454385 ps
CPU time 4.24 seconds
Started May 19 12:53:37 PM PDT 24
Finished May 19 12:53:42 PM PDT 24
Peak memory 211228 kb
Host smart-97c6fc03-234e-4591-b18a-3bc1de2c913d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1331947135 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_csr_rw.1331947135
Directory /workspace/7.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_passthru_mem_tl_intg_err.4175829951
Short name T86
Test name
Test status
Simulation time 47524307622 ps
CPU time 95.19 seconds
Started May 19 12:53:13 PM PDT 24
Finished May 19 12:54:54 PM PDT 24
Peak memory 211280 kb
Host smart-c29e681a-fefb-43ed-894b-600e338a3267
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4175829951 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_pa
ssthru_mem_tl_intg_err.4175829951
Directory /workspace/7.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_same_csr_outstanding.1686659555
Short name T430
Test name
Test status
Simulation time 8006109755 ps
CPU time 15.75 seconds
Started May 19 12:53:30 PM PDT 24
Finished May 19 12:53:47 PM PDT 24
Peak memory 211176 kb
Host smart-6aebee58-3c8c-44fb-b9e4-d8f653db281a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1686659555 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_c
trl_same_csr_outstanding.1686659555
Directory /workspace/7.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_errors.286142181
Short name T370
Test name
Test status
Simulation time 87079427 ps
CPU time 6.52 seconds
Started May 19 12:53:14 PM PDT 24
Finished May 19 12:53:26 PM PDT 24
Peak memory 219536 kb
Host smart-e97485cb-30ed-4e68-9379-ec3af4bf72f2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=286142181 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_tl_errors.286142181
Directory /workspace/7.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_intg_err.56994414
Short name T123
Test name
Test status
Simulation time 1294059783 ps
CPU time 74.53 seconds
Started May 19 12:53:19 PM PDT 24
Finished May 19 12:54:38 PM PDT 24
Peak memory 211248 kb
Host smart-aa21070c-04b6-4f94-8cfd-a68581e6f7f3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=56994414 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_tl_intg
_err.56994414
Directory /workspace/7.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_mem_rw_with_rand_reset.2062473589
Short name T373
Test name
Test status
Simulation time 2074171644 ps
CPU time 15.89 seconds
Started May 19 12:53:21 PM PDT 24
Finished May 19 12:53:40 PM PDT 24
Peak memory 213044 kb
Host smart-3fdddd66-b701-4130-b3ff-648aa4eea674
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2062473589 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 8.rom_ctrl_csr_mem_rw_with_rand_reset.2062473589
Directory /workspace/8.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_rw.474909318
Short name T90
Test name
Test status
Simulation time 621778758 ps
CPU time 8.08 seconds
Started May 19 12:53:19 PM PDT 24
Finished May 19 12:53:31 PM PDT 24
Peak memory 211152 kb
Host smart-63bae2cd-b6fa-4731-a529-81f43b83af75
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=474909318 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_csr_rw.474909318
Directory /workspace/8.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_passthru_mem_tl_intg_err.3883312749
Short name T69
Test name
Test status
Simulation time 25456966432 ps
CPU time 60.81 seconds
Started May 19 12:53:20 PM PDT 24
Finished May 19 12:54:24 PM PDT 24
Peak memory 211248 kb
Host smart-bdefcda1-af97-4705-8ad0-e57c91c638b8
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3883312749 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_pa
ssthru_mem_tl_intg_err.3883312749
Directory /workspace/8.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_same_csr_outstanding.1135536074
Short name T400
Test name
Test status
Simulation time 6716068068 ps
CPU time 13.35 seconds
Started May 19 12:53:18 PM PDT 24
Finished May 19 12:53:35 PM PDT 24
Peak memory 211252 kb
Host smart-431f7342-2560-46a8-91e5-5c9b46b553af
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1135536074 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_c
trl_same_csr_outstanding.1135536074
Directory /workspace/8.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_errors.3473541433
Short name T428
Test name
Test status
Simulation time 5241824385 ps
CPU time 17.53 seconds
Started May 19 12:53:13 PM PDT 24
Finished May 19 12:53:36 PM PDT 24
Peak memory 219452 kb
Host smart-c393c1be-a69e-4993-8a7e-a078a7042e6d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3473541433 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_tl_errors.3473541433
Directory /workspace/8.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_intg_err.1025002779
Short name T124
Test name
Test status
Simulation time 3566152917 ps
CPU time 71.1 seconds
Started May 19 12:53:14 PM PDT 24
Finished May 19 12:54:31 PM PDT 24
Peak memory 213256 kb
Host smart-d8b5e47e-dae1-4269-ac8d-720ea3ed8b0d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1025002779 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_tl_in
tg_err.1025002779
Directory /workspace/8.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_mem_rw_with_rand_reset.3543786360
Short name T372
Test name
Test status
Simulation time 451267646 ps
CPU time 6.71 seconds
Started May 19 12:53:18 PM PDT 24
Finished May 19 12:53:29 PM PDT 24
Peak memory 219392 kb
Host smart-3368b829-44a3-4fd5-96d0-f960bbb9ab21
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3543786360 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 9.rom_ctrl_csr_mem_rw_with_rand_reset.3543786360
Directory /workspace/9.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_rw.3699719482
Short name T93
Test name
Test status
Simulation time 1365206151 ps
CPU time 6.64 seconds
Started May 19 12:53:30 PM PDT 24
Finished May 19 12:53:38 PM PDT 24
Peak memory 210468 kb
Host smart-077df8d4-2806-4728-b2bb-e27b5c8f6458
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3699719482 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_csr_rw.3699719482
Directory /workspace/9.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_passthru_mem_tl_intg_err.3787307956
Short name T411
Test name
Test status
Simulation time 7986364308 ps
CPU time 63.36 seconds
Started May 19 12:53:14 PM PDT 24
Finished May 19 12:54:23 PM PDT 24
Peak memory 211360 kb
Host smart-cb71749b-f0cf-4733-944f-20b7a998073e
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3787307956 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_pa
ssthru_mem_tl_intg_err.3787307956
Directory /workspace/9.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_same_csr_outstanding.577831129
Short name T450
Test name
Test status
Simulation time 552994828 ps
CPU time 6.03 seconds
Started May 19 12:53:24 PM PDT 24
Finished May 19 12:53:31 PM PDT 24
Peak memory 211132 kb
Host smart-8b76427e-9bb0-44fe-af6a-f153f30b05a5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=577831129 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ct
rl_same_csr_outstanding.577831129
Directory /workspace/9.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_errors.1635513225
Short name T368
Test name
Test status
Simulation time 4718398952 ps
CPU time 12.29 seconds
Started May 19 12:53:29 PM PDT 24
Finished May 19 12:53:43 PM PDT 24
Peak memory 219576 kb
Host smart-524947e5-1bd2-41cc-9535-eadd8e2ece16
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1635513225 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_tl_errors.1635513225
Directory /workspace/9.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_intg_err.3349615535
Short name T433
Test name
Test status
Simulation time 10140964046 ps
CPU time 71.03 seconds
Started May 19 12:53:22 PM PDT 24
Finished May 19 12:54:35 PM PDT 24
Peak memory 219476 kb
Host smart-5abdf1fa-fa18-4fa1-92c4-270e68b36669
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3349615535 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_tl_in
tg_err.3349615535
Directory /workspace/9.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/0.rom_ctrl_alert_test.2032671554
Short name T273
Test name
Test status
Simulation time 474631402 ps
CPU time 7.3 seconds
Started May 19 12:53:27 PM PDT 24
Finished May 19 12:53:35 PM PDT 24
Peak memory 211416 kb
Host smart-6e2507e5-bb3d-43c7-9bee-4d760bf8e5c2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2032671554 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_alert_test.2032671554
Directory /workspace/0.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/0.rom_ctrl_corrupt_sig_fatal_chk.3720546530
Short name T1
Test name
Test status
Simulation time 8232548376 ps
CPU time 210.19 seconds
Started May 19 12:53:25 PM PDT 24
Finished May 19 12:56:57 PM PDT 24
Peak memory 220320 kb
Host smart-03bc5f1f-bbe1-4b0d-8c48-a5581848f677
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3720546530 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_c
orrupt_sig_fatal_chk.3720546530
Directory /workspace/0.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/0.rom_ctrl_kmac_err_chk.43071972
Short name T22
Test name
Test status
Simulation time 14026579320 ps
CPU time 29.87 seconds
Started May 19 12:53:38 PM PDT 24
Finished May 19 12:54:09 PM PDT 24
Peak memory 212000 kb
Host smart-59ca1f58-832d-4c40-a8fe-0653cf201267
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=43071972 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_kmac_err_chk.43071972
Directory /workspace/0.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/0.rom_ctrl_max_throughput_chk.2274620268
Short name T105
Test name
Test status
Simulation time 476317688 ps
CPU time 8.16 seconds
Started May 19 12:53:25 PM PDT 24
Finished May 19 12:53:35 PM PDT 24
Peak memory 210928 kb
Host smart-7b91d707-fc4f-4328-9594-9116e1cbf8be
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2274620268 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_max_throughput_chk.2274620268
Directory /workspace/0.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/0.rom_ctrl_sec_cm.1438282338
Short name T7
Test name
Test status
Simulation time 577931524 ps
CPU time 50.92 seconds
Started May 19 12:53:41 PM PDT 24
Finished May 19 12:54:34 PM PDT 24
Peak memory 233444 kb
Host smart-13d42c6b-04a9-4c5b-b1e3-cf90cd8483f8
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1438282338 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_sec_cm.1438282338
Directory /workspace/0.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/0.rom_ctrl_smoke.3009195511
Short name T153
Test name
Test status
Simulation time 671554665 ps
CPU time 9.62 seconds
Started May 19 12:53:25 PM PDT 24
Finished May 19 12:53:36 PM PDT 24
Peak memory 219184 kb
Host smart-f2143ccd-6a22-48b2-8563-47586c6c1a82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3009195511 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_smoke.3009195511
Directory /workspace/0.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/0.rom_ctrl_stress_all.1564091672
Short name T274
Test name
Test status
Simulation time 6842304536 ps
CPU time 27.44 seconds
Started May 19 12:53:26 PM PDT 24
Finished May 19 12:53:55 PM PDT 24
Peak memory 219372 kb
Host smart-0a9c5ad9-562e-41dc-b744-91d6ea2fc5e7
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1564091672 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 0.rom_ctrl_stress_all.1564091672
Directory /workspace/0.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/1.rom_ctrl_alert_test.992964554
Short name T150
Test name
Test status
Simulation time 336411714 ps
CPU time 6.86 seconds
Started May 19 12:53:49 PM PDT 24
Finished May 19 12:53:58 PM PDT 24
Peak memory 211204 kb
Host smart-62c201c3-602b-49d6-b4f0-9cbf80e18d1d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=992964554 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_alert_test.992964554
Directory /workspace/1.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/1.rom_ctrl_corrupt_sig_fatal_chk.1394861747
Short name T16
Test name
Test status
Simulation time 1879878100 ps
CPU time 83.46 seconds
Started May 19 12:53:31 PM PDT 24
Finished May 19 12:54:56 PM PDT 24
Peak memory 233336 kb
Host smart-1a05cf73-19e8-4032-9abc-a23bb94028be
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1394861747 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_c
orrupt_sig_fatal_chk.1394861747
Directory /workspace/1.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/1.rom_ctrl_kmac_err_chk.760939938
Short name T27
Test name
Test status
Simulation time 3588976362 ps
CPU time 29.27 seconds
Started May 19 12:53:28 PM PDT 24
Finished May 19 12:53:59 PM PDT 24
Peak memory 211924 kb
Host smart-3cc2da5a-3c5f-4206-b193-9b8f341feeda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=760939938 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_kmac_err_chk.760939938
Directory /workspace/1.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/1.rom_ctrl_max_throughput_chk.2822063528
Short name T228
Test name
Test status
Simulation time 3769762851 ps
CPU time 16.48 seconds
Started May 19 12:53:31 PM PDT 24
Finished May 19 12:53:49 PM PDT 24
Peak memory 211116 kb
Host smart-4fda57a9-58f3-452c-9888-55dd30d1da6d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2822063528 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_max_throughput_chk.2822063528
Directory /workspace/1.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/1.rom_ctrl_sec_cm.4146578450
Short name T38
Test name
Test status
Simulation time 9197202983 ps
CPU time 127.18 seconds
Started May 19 12:53:29 PM PDT 24
Finished May 19 12:55:37 PM PDT 24
Peak memory 239268 kb
Host smart-42046231-c4ae-4905-9e09-b0135c20cf64
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4146578450 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_sec_cm.4146578450
Directory /workspace/1.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/1.rom_ctrl_stress_all.2220798218
Short name T248
Test name
Test status
Simulation time 2134748729 ps
CPU time 20.46 seconds
Started May 19 12:53:35 PM PDT 24
Finished May 19 12:53:57 PM PDT 24
Peak memory 219276 kb
Host smart-92f50e59-95d0-413f-944f-a277e1dace89
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2220798218 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 1.rom_ctrl_stress_all.2220798218
Directory /workspace/1.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/10.rom_ctrl_alert_test.1903729547
Short name T181
Test name
Test status
Simulation time 378782158 ps
CPU time 4.16 seconds
Started May 19 12:53:42 PM PDT 24
Finished May 19 12:53:49 PM PDT 24
Peak memory 211132 kb
Host smart-9a675c71-7aaa-4c40-92b3-e5b84e1b572d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1903729547 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_alert_test.1903729547
Directory /workspace/10.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/10.rom_ctrl_corrupt_sig_fatal_chk.547363244
Short name T29
Test name
Test status
Simulation time 54844025716 ps
CPU time 206.24 seconds
Started May 19 12:53:44 PM PDT 24
Finished May 19 12:57:12 PM PDT 24
Peak memory 237800 kb
Host smart-e819c548-1a3a-485f-a768-323fe3f2dd78
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=547363244 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_c
orrupt_sig_fatal_chk.547363244
Directory /workspace/10.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/10.rom_ctrl_max_throughput_chk.1174289027
Short name T227
Test name
Test status
Simulation time 4161861495 ps
CPU time 10.7 seconds
Started May 19 12:53:49 PM PDT 24
Finished May 19 12:54:01 PM PDT 24
Peak memory 211068 kb
Host smart-3e45c218-6860-4cb2-9486-f1fd8323261c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1174289027 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_max_throughput_chk.1174289027
Directory /workspace/10.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/10.rom_ctrl_smoke.6406076
Short name T317
Test name
Test status
Simulation time 14483536757 ps
CPU time 29.47 seconds
Started May 19 12:53:44 PM PDT 24
Finished May 19 12:54:15 PM PDT 24
Peak memory 219340 kb
Host smart-808ee43e-ee48-474f-b188-4f2f3e77ee9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=6406076 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_smoke.6406076
Directory /workspace/10.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/10.rom_ctrl_stress_all.3292621643
Short name T214
Test name
Test status
Simulation time 29764983601 ps
CPU time 87.53 seconds
Started May 19 12:53:46 PM PDT 24
Finished May 19 12:55:15 PM PDT 24
Peak memory 219592 kb
Host smart-2855b88d-2347-43bf-b408-e2c3ce3b3297
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3292621643 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 10.rom_ctrl_stress_all.3292621643
Directory /workspace/10.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/11.rom_ctrl_alert_test.1869759117
Short name T139
Test name
Test status
Simulation time 7766169837 ps
CPU time 16.22 seconds
Started May 19 12:53:49 PM PDT 24
Finished May 19 12:54:07 PM PDT 24
Peak memory 211328 kb
Host smart-d04c50ac-01af-4e97-bdde-ac2e197117d9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1869759117 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_alert_test.1869759117
Directory /workspace/11.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/11.rom_ctrl_corrupt_sig_fatal_chk.2491033210
Short name T339
Test name
Test status
Simulation time 11392745972 ps
CPU time 153.73 seconds
Started May 19 12:53:52 PM PDT 24
Finished May 19 12:56:29 PM PDT 24
Peak memory 233692 kb
Host smart-976e8a98-a7d8-46e4-bfa9-d215e0180f8b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2491033210 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_
corrupt_sig_fatal_chk.2491033210
Directory /workspace/11.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/11.rom_ctrl_kmac_err_chk.3363277194
Short name T225
Test name
Test status
Simulation time 5896658396 ps
CPU time 18.9 seconds
Started May 19 12:53:50 PM PDT 24
Finished May 19 12:54:11 PM PDT 24
Peak memory 212128 kb
Host smart-0ca1d1c5-7976-4645-b66c-7f9be967e6f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3363277194 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_kmac_err_chk.3363277194
Directory /workspace/11.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/11.rom_ctrl_max_throughput_chk.2347415294
Short name T281
Test name
Test status
Simulation time 1833106935 ps
CPU time 16.18 seconds
Started May 19 12:53:47 PM PDT 24
Finished May 19 12:54:05 PM PDT 24
Peak memory 210988 kb
Host smart-286ac3b1-7285-4bd0-bb21-e7db915487de
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2347415294 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_max_throughput_chk.2347415294
Directory /workspace/11.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/11.rom_ctrl_smoke.1480410399
Short name T50
Test name
Test status
Simulation time 13144164822 ps
CPU time 27.77 seconds
Started May 19 12:53:53 PM PDT 24
Finished May 19 12:54:24 PM PDT 24
Peak memory 213656 kb
Host smart-f47f2a72-6fa4-4b1b-88cc-a49ec2606c69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1480410399 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_smoke.1480410399
Directory /workspace/11.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/11.rom_ctrl_stress_all.1258606433
Short name T180
Test name
Test status
Simulation time 7658522934 ps
CPU time 31.15 seconds
Started May 19 12:53:48 PM PDT 24
Finished May 19 12:54:21 PM PDT 24
Peak memory 214048 kb
Host smart-d48fd926-1189-4ff9-a64c-397ccf760934
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1258606433 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 11.rom_ctrl_stress_all.1258606433
Directory /workspace/11.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/12.rom_ctrl_alert_test.2103432736
Short name T346
Test name
Test status
Simulation time 1147039987 ps
CPU time 5.73 seconds
Started May 19 12:53:50 PM PDT 24
Finished May 19 12:53:58 PM PDT 24
Peak memory 211216 kb
Host smart-a89a93bd-c181-4178-9f4b-e9c40522dc9e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2103432736 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_alert_test.2103432736
Directory /workspace/12.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/12.rom_ctrl_corrupt_sig_fatal_chk.2820702741
Short name T26
Test name
Test status
Simulation time 115705216105 ps
CPU time 317.46 seconds
Started May 19 12:53:45 PM PDT 24
Finished May 19 12:59:04 PM PDT 24
Peak memory 237832 kb
Host smart-5018553c-8734-4896-baa8-b37ec68aab6c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2820702741 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_
corrupt_sig_fatal_chk.2820702741
Directory /workspace/12.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/12.rom_ctrl_kmac_err_chk.1481368501
Short name T165
Test name
Test status
Simulation time 429104127 ps
CPU time 12.43 seconds
Started May 19 12:53:53 PM PDT 24
Finished May 19 12:54:09 PM PDT 24
Peak memory 211820 kb
Host smart-5f1ed195-db77-4018-aa37-8462ccab5318
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1481368501 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_kmac_err_chk.1481368501
Directory /workspace/12.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/12.rom_ctrl_max_throughput_chk.2249237922
Short name T15
Test name
Test status
Simulation time 589115531 ps
CPU time 9.27 seconds
Started May 19 12:53:45 PM PDT 24
Finished May 19 12:53:56 PM PDT 24
Peak memory 211064 kb
Host smart-6035481d-8959-4efa-9dec-46c83348f746
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2249237922 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_max_throughput_chk.2249237922
Directory /workspace/12.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/12.rom_ctrl_smoke.1495285094
Short name T364
Test name
Test status
Simulation time 3150215748 ps
CPU time 23.5 seconds
Started May 19 12:53:52 PM PDT 24
Finished May 19 12:54:19 PM PDT 24
Peak memory 213288 kb
Host smart-d5dab432-ffb9-42b1-a9ba-da0e7904a505
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1495285094 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_smoke.1495285094
Directory /workspace/12.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/12.rom_ctrl_stress_all.3608029664
Short name T188
Test name
Test status
Simulation time 2044779834 ps
CPU time 34 seconds
Started May 19 12:53:51 PM PDT 24
Finished May 19 12:54:27 PM PDT 24
Peak memory 215576 kb
Host smart-24f2a6b6-b93f-459b-8c4b-98968dc6412e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3608029664 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 12.rom_ctrl_stress_all.3608029664
Directory /workspace/12.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/12.rom_ctrl_stress_all_with_rand_reset.3776641048
Short name T42
Test name
Test status
Simulation time 410514973380 ps
CPU time 1090.16 seconds
Started May 19 12:53:47 PM PDT 24
Finished May 19 01:11:59 PM PDT 24
Peak memory 232616 kb
Host smart-86a96830-f512-4a85-b30d-facd6bf23c5d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3776641048 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_stress_all_with_rand_reset.3776641048
Directory /workspace/12.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/13.rom_ctrl_alert_test.2702609559
Short name T212
Test name
Test status
Simulation time 5023412481 ps
CPU time 11.36 seconds
Started May 19 12:53:46 PM PDT 24
Finished May 19 12:53:59 PM PDT 24
Peak memory 211220 kb
Host smart-43815fe4-3351-4c25-933c-4b7a49f150af
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2702609559 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_alert_test.2702609559
Directory /workspace/13.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/13.rom_ctrl_corrupt_sig_fatal_chk.2707827336
Short name T347
Test name
Test status
Simulation time 44681929958 ps
CPU time 240.12 seconds
Started May 19 12:53:50 PM PDT 24
Finished May 19 12:57:52 PM PDT 24
Peak memory 242096 kb
Host smart-31b1822e-8abe-4f56-b32b-35ceb5ae6e84
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2707827336 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_
corrupt_sig_fatal_chk.2707827336
Directory /workspace/13.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/13.rom_ctrl_kmac_err_chk.3234085798
Short name T163
Test name
Test status
Simulation time 757087679 ps
CPU time 9.74 seconds
Started May 19 12:53:42 PM PDT 24
Finished May 19 12:53:54 PM PDT 24
Peak memory 211956 kb
Host smart-e231216c-6bf0-47c0-96bf-f379bf35e071
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3234085798 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_kmac_err_chk.3234085798
Directory /workspace/13.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/13.rom_ctrl_max_throughput_chk.1345615175
Short name T253
Test name
Test status
Simulation time 530134576 ps
CPU time 6.06 seconds
Started May 19 12:53:51 PM PDT 24
Finished May 19 12:53:59 PM PDT 24
Peak memory 210960 kb
Host smart-7ff46d5e-52c3-4685-aa42-bc1c74a174f6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1345615175 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_max_throughput_chk.1345615175
Directory /workspace/13.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/13.rom_ctrl_smoke.3876162607
Short name T260
Test name
Test status
Simulation time 2233043573 ps
CPU time 23.53 seconds
Started May 19 12:53:54 PM PDT 24
Finished May 19 12:54:21 PM PDT 24
Peak memory 213696 kb
Host smart-1b63586a-ac1c-480b-9a8e-c9185bdfb4a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3876162607 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_smoke.3876162607
Directory /workspace/13.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/13.rom_ctrl_stress_all.3456722162
Short name T81
Test name
Test status
Simulation time 11055048627 ps
CPU time 18.98 seconds
Started May 19 12:53:43 PM PDT 24
Finished May 19 12:54:04 PM PDT 24
Peak memory 212064 kb
Host smart-43cf0d50-fd21-42b9-9753-f2ac81c2db95
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3456722162 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 13.rom_ctrl_stress_all.3456722162
Directory /workspace/13.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/13.rom_ctrl_stress_all_with_rand_reset.27422106
Short name T47
Test name
Test status
Simulation time 145318311107 ps
CPU time 2387.9 seconds
Started May 19 12:53:54 PM PDT 24
Finished May 19 01:33:46 PM PDT 24
Peak memory 229664 kb
Host smart-3fa5e553-0b26-47bf-9204-4b3f2157f8c4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27422106 -assert nopos
tproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_stress_all_with_rand_reset.27422106
Directory /workspace/13.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/14.rom_ctrl_alert_test.3930574492
Short name T143
Test name
Test status
Simulation time 3835884982 ps
CPU time 15.83 seconds
Started May 19 12:54:00 PM PDT 24
Finished May 19 12:54:19 PM PDT 24
Peak memory 211324 kb
Host smart-58cd6f6d-9610-4495-b1f3-bf8845700ce1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3930574492 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_alert_test.3930574492
Directory /workspace/14.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/14.rom_ctrl_corrupt_sig_fatal_chk.3429669244
Short name T213
Test name
Test status
Simulation time 72980654616 ps
CPU time 269.33 seconds
Started May 19 12:53:44 PM PDT 24
Finished May 19 12:58:15 PM PDT 24
Peak memory 236936 kb
Host smart-f519ec85-26ee-4b66-8a36-0dec4ea3fa45
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3429669244 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_
corrupt_sig_fatal_chk.3429669244
Directory /workspace/14.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/14.rom_ctrl_kmac_err_chk.3147980134
Short name T99
Test name
Test status
Simulation time 14681923455 ps
CPU time 26.15 seconds
Started May 19 12:53:50 PM PDT 24
Finished May 19 12:54:18 PM PDT 24
Peak memory 212832 kb
Host smart-553b16dc-77ab-4950-b61c-663c3be0e680
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3147980134 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_kmac_err_chk.3147980134
Directory /workspace/14.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/14.rom_ctrl_max_throughput_chk.137166741
Short name T356
Test name
Test status
Simulation time 1819008641 ps
CPU time 16.09 seconds
Started May 19 12:53:51 PM PDT 24
Finished May 19 12:54:10 PM PDT 24
Peak memory 211072 kb
Host smart-1b1ed7e9-cf70-448c-b008-02356c784ccc
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=137166741 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_max_throughput_chk.137166741
Directory /workspace/14.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/14.rom_ctrl_smoke.1204956927
Short name T309
Test name
Test status
Simulation time 5454165873 ps
CPU time 24.59 seconds
Started May 19 12:53:46 PM PDT 24
Finished May 19 12:54:13 PM PDT 24
Peak memory 213424 kb
Host smart-39b4d1fe-247d-42d1-a7ee-3b5353f2f97e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1204956927 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_smoke.1204956927
Directory /workspace/14.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/14.rom_ctrl_stress_all.13829205
Short name T304
Test name
Test status
Simulation time 5188193822 ps
CPU time 49.43 seconds
Started May 19 12:53:52 PM PDT 24
Finished May 19 12:54:45 PM PDT 24
Peak memory 216980 kb
Host smart-ebb9ff5a-be06-4d57-8dcd-73588becac55
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13829205 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +U
VM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n
ame 14.rom_ctrl_stress_all.13829205
Directory /workspace/14.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/15.rom_ctrl_alert_test.2963282359
Short name T34
Test name
Test status
Simulation time 1188146914 ps
CPU time 8.41 seconds
Started May 19 12:53:49 PM PDT 24
Finished May 19 12:54:06 PM PDT 24
Peak memory 211160 kb
Host smart-eef8e7f8-b7a7-4344-acca-e471d1931e00
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2963282359 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_alert_test.2963282359
Directory /workspace/15.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/15.rom_ctrl_corrupt_sig_fatal_chk.1562952742
Short name T220
Test name
Test status
Simulation time 28589783691 ps
CPU time 243.95 seconds
Started May 19 12:53:52 PM PDT 24
Finished May 19 12:57:59 PM PDT 24
Peak memory 228592 kb
Host smart-71f839b1-09f4-4de2-add5-da428ffdf36c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1562952742 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_
corrupt_sig_fatal_chk.1562952742
Directory /workspace/15.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/15.rom_ctrl_kmac_err_chk.364377409
Short name T254
Test name
Test status
Simulation time 1882443295 ps
CPU time 21.22 seconds
Started May 19 12:53:52 PM PDT 24
Finished May 19 12:54:17 PM PDT 24
Peak memory 211264 kb
Host smart-8806a833-2621-48b4-9a9a-432294c5b544
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=364377409 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_kmac_err_chk.364377409
Directory /workspace/15.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/15.rom_ctrl_max_throughput_chk.675679970
Short name T285
Test name
Test status
Simulation time 20769451601 ps
CPU time 13.19 seconds
Started May 19 12:53:51 PM PDT 24
Finished May 19 12:54:06 PM PDT 24
Peak memory 211124 kb
Host smart-9cb6db5d-4d08-476d-8e2c-534c3e75346c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=675679970 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_max_throughput_chk.675679970
Directory /workspace/15.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/15.rom_ctrl_smoke.1882565240
Short name T282
Test name
Test status
Simulation time 1117244517 ps
CPU time 10.13 seconds
Started May 19 12:53:44 PM PDT 24
Finished May 19 12:53:55 PM PDT 24
Peak memory 219300 kb
Host smart-0751a2b4-37ca-4b6e-81ea-d4168804f81a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1882565240 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_smoke.1882565240
Directory /workspace/15.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/15.rom_ctrl_stress_all.1376164648
Short name T49
Test name
Test status
Simulation time 3269621436 ps
CPU time 18.23 seconds
Started May 19 12:53:51 PM PDT 24
Finished May 19 12:54:11 PM PDT 24
Peak memory 211864 kb
Host smart-54693dc6-4ba3-410c-beac-68d4af3477b1
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1376164648 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 15.rom_ctrl_stress_all.1376164648
Directory /workspace/15.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/15.rom_ctrl_stress_all_with_rand_reset.323144455
Short name T193
Test name
Test status
Simulation time 85632937232 ps
CPU time 2836.55 seconds
Started May 19 12:53:52 PM PDT 24
Finished May 19 01:41:12 PM PDT 24
Peak memory 235864 kb
Host smart-f9511033-4ef3-425d-9e89-8a82503c6eee
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=323144455 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_stress_all_with_rand_reset.323144455
Directory /workspace/15.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/16.rom_ctrl_alert_test.3474539541
Short name T175
Test name
Test status
Simulation time 2748481537 ps
CPU time 14.99 seconds
Started May 19 12:53:47 PM PDT 24
Finished May 19 12:54:03 PM PDT 24
Peak memory 211268 kb
Host smart-78ad6c17-977e-4def-9fa2-4e4fae3e4f01
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3474539541 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_alert_test.3474539541
Directory /workspace/16.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/16.rom_ctrl_corrupt_sig_fatal_chk.68928235
Short name T351
Test name
Test status
Simulation time 41679156167 ps
CPU time 192.88 seconds
Started May 19 12:53:48 PM PDT 24
Finished May 19 12:57:02 PM PDT 24
Peak memory 221484 kb
Host smart-46d1abcd-a48b-4215-a137-d93b947fa35d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=68928235 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_
sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_co
rrupt_sig_fatal_chk.68928235
Directory /workspace/16.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/16.rom_ctrl_kmac_err_chk.3359895290
Short name T203
Test name
Test status
Simulation time 2469948078 ps
CPU time 23.62 seconds
Started May 19 12:53:57 PM PDT 24
Finished May 19 12:54:24 PM PDT 24
Peak memory 211232 kb
Host smart-64c6f2e6-fca4-4ca2-bbf4-b8f1b1ac05be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3359895290 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_kmac_err_chk.3359895290
Directory /workspace/16.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/16.rom_ctrl_smoke.3793076920
Short name T310
Test name
Test status
Simulation time 358703254 ps
CPU time 10.49 seconds
Started May 19 12:53:48 PM PDT 24
Finished May 19 12:54:00 PM PDT 24
Peak memory 219264 kb
Host smart-4ddc96ad-b1dd-4a21-bc0e-a8bb663847da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3793076920 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_smoke.3793076920
Directory /workspace/16.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/16.rom_ctrl_stress_all.3828827120
Short name T129
Test name
Test status
Simulation time 36789922175 ps
CPU time 51.23 seconds
Started May 19 12:53:52 PM PDT 24
Finished May 19 12:54:47 PM PDT 24
Peak memory 216428 kb
Host smart-6c178da6-11a2-4eff-92d7-3b18d0fc99d4
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3828827120 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 16.rom_ctrl_stress_all.3828827120
Directory /workspace/16.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/17.rom_ctrl_alert_test.3707296404
Short name T161
Test name
Test status
Simulation time 553222008 ps
CPU time 4.39 seconds
Started May 19 12:53:53 PM PDT 24
Finished May 19 12:54:01 PM PDT 24
Peak memory 211160 kb
Host smart-4b9ed98b-5373-46a7-837c-fcae45b46422
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3707296404 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_alert_test.3707296404
Directory /workspace/17.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/17.rom_ctrl_kmac_err_chk.839635420
Short name T144
Test name
Test status
Simulation time 22108144479 ps
CPU time 23.27 seconds
Started May 19 12:53:51 PM PDT 24
Finished May 19 12:54:16 PM PDT 24
Peak memory 211764 kb
Host smart-b1278c72-4b4a-4c0c-afd7-cffaee88e2ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=839635420 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_kmac_err_chk.839635420
Directory /workspace/17.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/17.rom_ctrl_max_throughput_chk.456502262
Short name T128
Test name
Test status
Simulation time 99543629 ps
CPU time 5.67 seconds
Started May 19 12:53:57 PM PDT 24
Finished May 19 12:54:06 PM PDT 24
Peak memory 210972 kb
Host smart-d2a5b98a-fe22-4d53-bf11-b80e6924fc5b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=456502262 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_max_throughput_chk.456502262
Directory /workspace/17.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/17.rom_ctrl_smoke.1589406562
Short name T160
Test name
Test status
Simulation time 2729927534 ps
CPU time 27.77 seconds
Started May 19 12:53:53 PM PDT 24
Finished May 19 12:54:24 PM PDT 24
Peak memory 213028 kb
Host smart-84a455c6-948e-4c4f-aace-ad900a70f1df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1589406562 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_smoke.1589406562
Directory /workspace/17.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/17.rom_ctrl_stress_all.471600168
Short name T276
Test name
Test status
Simulation time 12520522198 ps
CPU time 34.5 seconds
Started May 19 12:53:45 PM PDT 24
Finished May 19 12:54:21 PM PDT 24
Peak memory 216032 kb
Host smart-3eb6e7d8-4720-4f5c-b52f-796690b8f31d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=471600168 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 17.rom_ctrl_stress_all.471600168
Directory /workspace/17.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/17.rom_ctrl_stress_all_with_rand_reset.3851804054
Short name T48
Test name
Test status
Simulation time 14595198609 ps
CPU time 261.47 seconds
Started May 19 12:53:45 PM PDT 24
Finished May 19 12:58:08 PM PDT 24
Peak memory 221368 kb
Host smart-92006df6-b94a-4175-a546-d4b8e4a656d1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3851804054 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_stress_all_with_rand_reset.3851804054
Directory /workspace/17.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/18.rom_ctrl_alert_test.3663338967
Short name T147
Test name
Test status
Simulation time 85567446 ps
CPU time 4.19 seconds
Started May 19 12:53:47 PM PDT 24
Finished May 19 12:53:53 PM PDT 24
Peak memory 211192 kb
Host smart-6c7676d5-606a-4a5c-8b54-a8d0ac035788
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3663338967 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_alert_test.3663338967
Directory /workspace/18.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/18.rom_ctrl_corrupt_sig_fatal_chk.3916529010
Short name T41
Test name
Test status
Simulation time 45528567284 ps
CPU time 229.02 seconds
Started May 19 12:53:45 PM PDT 24
Finished May 19 12:57:35 PM PDT 24
Peak memory 233008 kb
Host smart-23cc4c96-5ba4-418b-9989-cfacfa7e4dac
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3916529010 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_
corrupt_sig_fatal_chk.3916529010
Directory /workspace/18.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/18.rom_ctrl_kmac_err_chk.2513046315
Short name T28
Test name
Test status
Simulation time 2733686372 ps
CPU time 26.02 seconds
Started May 19 12:53:59 PM PDT 24
Finished May 19 12:54:28 PM PDT 24
Peak memory 211744 kb
Host smart-2b108bf5-e4b7-4c98-a7b2-808cda96cb24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2513046315 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_kmac_err_chk.2513046315
Directory /workspace/18.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/18.rom_ctrl_max_throughput_chk.1819227500
Short name T297
Test name
Test status
Simulation time 336556932 ps
CPU time 5.68 seconds
Started May 19 12:53:46 PM PDT 24
Finished May 19 12:53:53 PM PDT 24
Peak memory 210904 kb
Host smart-b1442d8f-3f7e-447b-8ad2-dbd00fdd862e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1819227500 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_max_throughput_chk.1819227500
Directory /workspace/18.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/18.rom_ctrl_smoke.1181364950
Short name T287
Test name
Test status
Simulation time 10344944789 ps
CPU time 27.17 seconds
Started May 19 12:53:51 PM PDT 24
Finished May 19 12:54:21 PM PDT 24
Peak memory 219376 kb
Host smart-125b1477-0a46-40fd-b689-454448971b88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1181364950 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_smoke.1181364950
Directory /workspace/18.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/18.rom_ctrl_stress_all.3138232897
Short name T158
Test name
Test status
Simulation time 809249554 ps
CPU time 34.25 seconds
Started May 19 12:53:50 PM PDT 24
Finished May 19 12:54:26 PM PDT 24
Peak memory 216232 kb
Host smart-8264021e-fdf9-46dd-8d62-3fd6038bd44b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3138232897 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 18.rom_ctrl_stress_all.3138232897
Directory /workspace/18.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/18.rom_ctrl_stress_all_with_rand_reset.223611949
Short name T43
Test name
Test status
Simulation time 77448444270 ps
CPU time 515.8 seconds
Started May 19 12:53:50 PM PDT 24
Finished May 19 01:02:27 PM PDT 24
Peak memory 228428 kb
Host smart-e77b18e5-661c-4025-832d-8d8ac488a090
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=223611949 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_stress_all_with_rand_reset.223611949
Directory /workspace/18.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/19.rom_ctrl_alert_test.3818396634
Short name T345
Test name
Test status
Simulation time 1388581297 ps
CPU time 12.25 seconds
Started May 19 12:53:47 PM PDT 24
Finished May 19 12:54:01 PM PDT 24
Peak memory 211120 kb
Host smart-04b759ba-4deb-4399-839b-9f283557fa24
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3818396634 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_alert_test.3818396634
Directory /workspace/19.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/19.rom_ctrl_kmac_err_chk.4268021575
Short name T301
Test name
Test status
Simulation time 3702006978 ps
CPU time 31.11 seconds
Started May 19 12:53:58 PM PDT 24
Finished May 19 12:54:32 PM PDT 24
Peak memory 211776 kb
Host smart-ddac394e-c9d5-48bc-8bb8-a48c350bb57f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4268021575 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_kmac_err_chk.4268021575
Directory /workspace/19.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/19.rom_ctrl_max_throughput_chk.2196676008
Short name T138
Test name
Test status
Simulation time 1788667076 ps
CPU time 15.87 seconds
Started May 19 12:53:48 PM PDT 24
Finished May 19 12:54:06 PM PDT 24
Peak memory 211064 kb
Host smart-af4aec89-83ef-4e06-85aa-454d48112126
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2196676008 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_max_throughput_chk.2196676008
Directory /workspace/19.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/19.rom_ctrl_smoke.2830319395
Short name T302
Test name
Test status
Simulation time 689055902 ps
CPU time 10.08 seconds
Started May 19 12:53:46 PM PDT 24
Finished May 19 12:53:58 PM PDT 24
Peak memory 219204 kb
Host smart-0126c982-4bcb-4d79-bccd-d158adc49cce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2830319395 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_smoke.2830319395
Directory /workspace/19.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/19.rom_ctrl_stress_all.1062865717
Short name T239
Test name
Test status
Simulation time 595774531 ps
CPU time 17.38 seconds
Started May 19 12:53:46 PM PDT 24
Finished May 19 12:54:05 PM PDT 24
Peak memory 219224 kb
Host smart-4065c685-998a-4f27-867c-c9b21e3a03b1
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1062865717 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 19.rom_ctrl_stress_all.1062865717
Directory /workspace/19.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/2.rom_ctrl_alert_test.1415306673
Short name T204
Test name
Test status
Simulation time 3624877015 ps
CPU time 12.02 seconds
Started May 19 12:53:41 PM PDT 24
Finished May 19 12:53:55 PM PDT 24
Peak memory 211308 kb
Host smart-48c0bf73-7853-4c4e-9630-09d363e5e29c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1415306673 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_alert_test.1415306673
Directory /workspace/2.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/2.rom_ctrl_corrupt_sig_fatal_chk.277110002
Short name T334
Test name
Test status
Simulation time 10936060030 ps
CPU time 129.28 seconds
Started May 19 12:53:29 PM PDT 24
Finished May 19 12:55:39 PM PDT 24
Peak memory 236752 kb
Host smart-5eba544e-37ad-48a1-9d8f-4a5a8d900bd2
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=277110002 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_co
rrupt_sig_fatal_chk.277110002
Directory /workspace/2.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/2.rom_ctrl_kmac_err_chk.3471453591
Short name T245
Test name
Test status
Simulation time 3795993121 ps
CPU time 31.48 seconds
Started May 19 12:53:42 PM PDT 24
Finished May 19 12:54:15 PM PDT 24
Peak memory 211788 kb
Host smart-9f395c55-64f6-41e3-a5bd-08300d007d52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3471453591 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_kmac_err_chk.3471453591
Directory /workspace/2.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/2.rom_ctrl_max_throughput_chk.2021887797
Short name T320
Test name
Test status
Simulation time 1738752213 ps
CPU time 15.53 seconds
Started May 19 12:53:38 PM PDT 24
Finished May 19 12:53:55 PM PDT 24
Peak memory 210988 kb
Host smart-90aef445-e9b6-4328-9226-6de5fa67372d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2021887797 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_max_throughput_chk.2021887797
Directory /workspace/2.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/2.rom_ctrl_sec_cm.538244204
Short name T37
Test name
Test status
Simulation time 207407115 ps
CPU time 54.56 seconds
Started May 19 12:53:38 PM PDT 24
Finished May 19 12:54:34 PM PDT 24
Peak memory 229132 kb
Host smart-ab805c05-332f-4609-94ea-029b5048699b
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=538244204 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_sec_cm.538244204
Directory /workspace/2.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/2.rom_ctrl_smoke.1296440383
Short name T300
Test name
Test status
Simulation time 183641449 ps
CPU time 10.1 seconds
Started May 19 12:53:42 PM PDT 24
Finished May 19 12:53:54 PM PDT 24
Peak memory 219180 kb
Host smart-08c10447-72d4-42fb-8b58-4e214b5d71aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1296440383 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_smoke.1296440383
Directory /workspace/2.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/2.rom_ctrl_stress_all.1533376626
Short name T170
Test name
Test status
Simulation time 9508007567 ps
CPU time 66.81 seconds
Started May 19 12:53:42 PM PDT 24
Finished May 19 12:54:51 PM PDT 24
Peak memory 217184 kb
Host smart-b37df0ba-43e7-49d5-ad28-131ebf5fc48c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1533376626 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 2.rom_ctrl_stress_all.1533376626
Directory /workspace/2.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/20.rom_ctrl_alert_test.3142032746
Short name T237
Test name
Test status
Simulation time 5835714098 ps
CPU time 14.19 seconds
Started May 19 12:53:42 PM PDT 24
Finished May 19 12:53:58 PM PDT 24
Peak memory 211328 kb
Host smart-fa387fd0-1197-453f-8b02-6abcce31f055
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3142032746 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_alert_test.3142032746
Directory /workspace/20.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/20.rom_ctrl_corrupt_sig_fatal_chk.3081503815
Short name T264
Test name
Test status
Simulation time 196200892487 ps
CPU time 443.17 seconds
Started May 19 12:53:57 PM PDT 24
Finished May 19 01:01:24 PM PDT 24
Peak memory 233860 kb
Host smart-eec4fd36-a7ae-4248-8cea-db5be659e003
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3081503815 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_
corrupt_sig_fatal_chk.3081503815
Directory /workspace/20.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/20.rom_ctrl_kmac_err_chk.2305563826
Short name T178
Test name
Test status
Simulation time 173610133 ps
CPU time 9.52 seconds
Started May 19 12:53:48 PM PDT 24
Finished May 19 12:53:59 PM PDT 24
Peak memory 211764 kb
Host smart-3da7154e-a700-4e2e-8fff-7485f3bb9eb7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2305563826 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_kmac_err_chk.2305563826
Directory /workspace/20.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/20.rom_ctrl_max_throughput_chk.1219393566
Short name T202
Test name
Test status
Simulation time 5466569736 ps
CPU time 12.51 seconds
Started May 19 12:53:52 PM PDT 24
Finished May 19 12:54:08 PM PDT 24
Peak memory 211084 kb
Host smart-6f7de979-d27e-45cd-8d6a-35cf6fc4fddc
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1219393566 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_max_throughput_chk.1219393566
Directory /workspace/20.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/20.rom_ctrl_smoke.2451600966
Short name T318
Test name
Test status
Simulation time 3153352255 ps
CPU time 26.61 seconds
Started May 19 12:53:56 PM PDT 24
Finished May 19 12:54:26 PM PDT 24
Peak memory 219272 kb
Host smart-7d19a1aa-c8aa-4268-b968-be267859881b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2451600966 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_smoke.2451600966
Directory /workspace/20.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/20.rom_ctrl_stress_all.4173951416
Short name T215
Test name
Test status
Simulation time 6191597072 ps
CPU time 64.12 seconds
Started May 19 12:53:52 PM PDT 24
Finished May 19 12:55:01 PM PDT 24
Peak memory 219412 kb
Host smart-cdcf3f03-a56d-4393-848e-e6f1b5686541
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4173951416 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 20.rom_ctrl_stress_all.4173951416
Directory /workspace/20.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/21.rom_ctrl_alert_test.1871743012
Short name T363
Test name
Test status
Simulation time 23378137023 ps
CPU time 16.08 seconds
Started May 19 12:54:00 PM PDT 24
Finished May 19 12:54:19 PM PDT 24
Peak memory 211216 kb
Host smart-32e887c6-2fd1-40a8-bdaf-2773f35b654d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1871743012 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_alert_test.1871743012
Directory /workspace/21.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/21.rom_ctrl_corrupt_sig_fatal_chk.1935052500
Short name T31
Test name
Test status
Simulation time 11218542911 ps
CPU time 214.7 seconds
Started May 19 12:53:58 PM PDT 24
Finished May 19 12:57:36 PM PDT 24
Peak memory 228688 kb
Host smart-3ad3e2eb-47f8-4cd5-9d19-e4bbca160c0d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1935052500 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_
corrupt_sig_fatal_chk.1935052500
Directory /workspace/21.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/21.rom_ctrl_kmac_err_chk.4079852871
Short name T53
Test name
Test status
Simulation time 2270126455 ps
CPU time 23.22 seconds
Started May 19 12:53:53 PM PDT 24
Finished May 19 12:54:21 PM PDT 24
Peak memory 211984 kb
Host smart-0474561c-5a8d-4b59-9757-561268745f8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4079852871 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_kmac_err_chk.4079852871
Directory /workspace/21.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/21.rom_ctrl_max_throughput_chk.3273908844
Short name T355
Test name
Test status
Simulation time 137046137 ps
CPU time 6.33 seconds
Started May 19 12:53:58 PM PDT 24
Finished May 19 12:54:07 PM PDT 24
Peak memory 211228 kb
Host smart-259c21c1-ab46-461c-8a6d-475c96a2d8b9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3273908844 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_max_throughput_chk.3273908844
Directory /workspace/21.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/21.rom_ctrl_smoke.815408756
Short name T344
Test name
Test status
Simulation time 1968749390 ps
CPU time 20.52 seconds
Started May 19 12:53:58 PM PDT 24
Finished May 19 12:54:21 PM PDT 24
Peak memory 213152 kb
Host smart-3c448737-1d37-499a-ac5a-a6b93d9fb6d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=815408756 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_smoke.815408756
Directory /workspace/21.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/21.rom_ctrl_stress_all.496031385
Short name T299
Test name
Test status
Simulation time 4219293703 ps
CPU time 41.42 seconds
Started May 19 12:53:58 PM PDT 24
Finished May 19 12:54:43 PM PDT 24
Peak memory 216136 kb
Host smart-51bbcfb8-9fce-4b05-a2d4-ac8a7122a7ff
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=496031385 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 21.rom_ctrl_stress_all.496031385
Directory /workspace/21.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/21.rom_ctrl_stress_all_with_rand_reset.1225781991
Short name T45
Test name
Test status
Simulation time 96965922021 ps
CPU time 1226.04 seconds
Started May 19 12:53:53 PM PDT 24
Finished May 19 01:14:23 PM PDT 24
Peak memory 230156 kb
Host smart-3eacafb2-1825-4f74-9ce7-f36336f57ba5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1225781991 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_stress_all_with_rand_reset.1225781991
Directory /workspace/21.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/22.rom_ctrl_alert_test.1800857445
Short name T55
Test name
Test status
Simulation time 2574863282 ps
CPU time 9.99 seconds
Started May 19 12:53:55 PM PDT 24
Finished May 19 12:54:09 PM PDT 24
Peak memory 211256 kb
Host smart-ae5e1fda-59f7-4357-9130-186dfdefe8c4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1800857445 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_alert_test.1800857445
Directory /workspace/22.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/22.rom_ctrl_corrupt_sig_fatal_chk.2921802850
Short name T361
Test name
Test status
Simulation time 45611965509 ps
CPU time 267.46 seconds
Started May 19 12:54:15 PM PDT 24
Finished May 19 12:58:48 PM PDT 24
Peak memory 230712 kb
Host smart-aa59c213-67bd-4c68-8f0b-fc8cf76d589a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2921802850 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_
corrupt_sig_fatal_chk.2921802850
Directory /workspace/22.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/22.rom_ctrl_kmac_err_chk.1246759998
Short name T311
Test name
Test status
Simulation time 331351088 ps
CPU time 12.16 seconds
Started May 19 12:54:04 PM PDT 24
Finished May 19 12:54:18 PM PDT 24
Peak memory 211708 kb
Host smart-6690544f-e608-4cea-a1bf-62be9334d124
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1246759998 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_kmac_err_chk.1246759998
Directory /workspace/22.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/22.rom_ctrl_max_throughput_chk.3012021707
Short name T199
Test name
Test status
Simulation time 395829380 ps
CPU time 5.56 seconds
Started May 19 12:53:55 PM PDT 24
Finished May 19 12:54:04 PM PDT 24
Peak memory 211064 kb
Host smart-78a07b44-4581-457b-a0ea-33252832df99
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3012021707 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_max_throughput_chk.3012021707
Directory /workspace/22.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/22.rom_ctrl_smoke.409352134
Short name T56
Test name
Test status
Simulation time 11188747932 ps
CPU time 27.5 seconds
Started May 19 12:54:03 PM PDT 24
Finished May 19 12:54:33 PM PDT 24
Peak memory 214016 kb
Host smart-e8bc0c51-4379-46c0-b17b-3741d57e4258
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=409352134 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_smoke.409352134
Directory /workspace/22.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/22.rom_ctrl_stress_all.2769402445
Short name T233
Test name
Test status
Simulation time 754260441 ps
CPU time 19.42 seconds
Started May 19 12:53:53 PM PDT 24
Finished May 19 12:54:16 PM PDT 24
Peak memory 219296 kb
Host smart-87bd51cb-3afb-4b9e-b3c5-b883d91f58fb
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2769402445 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 22.rom_ctrl_stress_all.2769402445
Directory /workspace/22.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/23.rom_ctrl_alert_test.1705699127
Short name T54
Test name
Test status
Simulation time 4613681188 ps
CPU time 9.17 seconds
Started May 19 12:53:54 PM PDT 24
Finished May 19 12:54:08 PM PDT 24
Peak memory 211244 kb
Host smart-3e53091c-426b-4eda-937a-481054943713
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1705699127 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_alert_test.1705699127
Directory /workspace/23.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/23.rom_ctrl_corrupt_sig_fatal_chk.1345605107
Short name T24
Test name
Test status
Simulation time 106685432637 ps
CPU time 453.95 seconds
Started May 19 12:53:59 PM PDT 24
Finished May 19 01:01:36 PM PDT 24
Peak memory 239028 kb
Host smart-d4d66bed-148b-49bc-b26a-ced0e3b244bc
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1345605107 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_
corrupt_sig_fatal_chk.1345605107
Directory /workspace/23.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/23.rom_ctrl_kmac_err_chk.238946982
Short name T223
Test name
Test status
Simulation time 197933540 ps
CPU time 9.6 seconds
Started May 19 12:53:53 PM PDT 24
Finished May 19 12:54:06 PM PDT 24
Peak memory 211256 kb
Host smart-f6ae136b-259e-4c2d-9708-e923f1ef41c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=238946982 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_kmac_err_chk.238946982
Directory /workspace/23.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/23.rom_ctrl_max_throughput_chk.2298520273
Short name T14
Test name
Test status
Simulation time 7923192873 ps
CPU time 16.61 seconds
Started May 19 12:53:56 PM PDT 24
Finished May 19 12:54:16 PM PDT 24
Peak memory 211084 kb
Host smart-85f018f7-9c9a-4da0-b114-3f2cf1d2166c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2298520273 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_max_throughput_chk.2298520273
Directory /workspace/23.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/23.rom_ctrl_smoke.1919810417
Short name T313
Test name
Test status
Simulation time 36278337987 ps
CPU time 27.84 seconds
Started May 19 12:53:54 PM PDT 24
Finished May 19 12:54:26 PM PDT 24
Peak memory 219428 kb
Host smart-462b49d1-b49d-4b9e-936f-05181ed30eca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1919810417 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_smoke.1919810417
Directory /workspace/23.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/23.rom_ctrl_stress_all.3511374193
Short name T82
Test name
Test status
Simulation time 578854933 ps
CPU time 9.66 seconds
Started May 19 12:54:02 PM PDT 24
Finished May 19 12:54:13 PM PDT 24
Peak memory 211108 kb
Host smart-9269a584-b0a3-4946-8b1e-561fa9970226
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3511374193 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 23.rom_ctrl_stress_all.3511374193
Directory /workspace/23.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/24.rom_ctrl_alert_test.481534739
Short name T330
Test name
Test status
Simulation time 2751484765 ps
CPU time 12.62 seconds
Started May 19 12:53:54 PM PDT 24
Finished May 19 12:54:14 PM PDT 24
Peak memory 211224 kb
Host smart-74113577-accc-45a4-a93f-c58c855abe61
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=481534739 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_alert_test.481534739
Directory /workspace/24.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/24.rom_ctrl_corrupt_sig_fatal_chk.3227352127
Short name T173
Test name
Test status
Simulation time 70278821444 ps
CPU time 341.16 seconds
Started May 19 12:53:57 PM PDT 24
Finished May 19 12:59:42 PM PDT 24
Peak memory 228508 kb
Host smart-e21531dc-c116-41df-b53c-2e964b2674cb
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3227352127 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_
corrupt_sig_fatal_chk.3227352127
Directory /workspace/24.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/24.rom_ctrl_kmac_err_chk.3097564533
Short name T197
Test name
Test status
Simulation time 2914291474 ps
CPU time 18.33 seconds
Started May 19 12:54:00 PM PDT 24
Finished May 19 12:54:21 PM PDT 24
Peak memory 211816 kb
Host smart-23fdec96-581a-4155-8943-f7c82327b385
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3097564533 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_kmac_err_chk.3097564533
Directory /workspace/24.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/24.rom_ctrl_max_throughput_chk.3220813410
Short name T97
Test name
Test status
Simulation time 518212522 ps
CPU time 8.59 seconds
Started May 19 12:54:00 PM PDT 24
Finished May 19 12:54:11 PM PDT 24
Peak memory 211032 kb
Host smart-a9812665-184a-4523-ae0f-d3ee92c46180
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3220813410 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_max_throughput_chk.3220813410
Directory /workspace/24.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/24.rom_ctrl_smoke.3459873340
Short name T127
Test name
Test status
Simulation time 5283038612 ps
CPU time 25.07 seconds
Started May 19 12:53:50 PM PDT 24
Finished May 19 12:54:16 PM PDT 24
Peak memory 213896 kb
Host smart-e116ed1a-6de0-4af4-b347-f2dfb2dbc660
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3459873340 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_smoke.3459873340
Directory /workspace/24.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/24.rom_ctrl_stress_all.1012568572
Short name T11
Test name
Test status
Simulation time 2036867838 ps
CPU time 19.68 seconds
Started May 19 12:54:04 PM PDT 24
Finished May 19 12:54:26 PM PDT 24
Peak memory 215012 kb
Host smart-7695bb56-36a3-4521-930a-85fca8e1eb04
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1012568572 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 24.rom_ctrl_stress_all.1012568572
Directory /workspace/24.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/25.rom_ctrl_alert_test.1972672580
Short name T185
Test name
Test status
Simulation time 416327607 ps
CPU time 4.28 seconds
Started May 19 12:54:00 PM PDT 24
Finished May 19 12:54:07 PM PDT 24
Peak memory 211132 kb
Host smart-e61f4168-3127-4e70-a001-44455ecb7de0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1972672580 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_alert_test.1972672580
Directory /workspace/25.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/25.rom_ctrl_corrupt_sig_fatal_chk.1781363106
Short name T326
Test name
Test status
Simulation time 5805788757 ps
CPU time 127.38 seconds
Started May 19 12:54:04 PM PDT 24
Finished May 19 12:56:14 PM PDT 24
Peak memory 225068 kb
Host smart-7c917318-01bf-42c9-8cf7-48b7e7f982ed
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1781363106 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_
corrupt_sig_fatal_chk.1781363106
Directory /workspace/25.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/25.rom_ctrl_kmac_err_chk.3897266961
Short name T168
Test name
Test status
Simulation time 725816304 ps
CPU time 9.4 seconds
Started May 19 12:53:52 PM PDT 24
Finished May 19 12:54:05 PM PDT 24
Peak memory 211208 kb
Host smart-92e6e910-dfd0-40b4-b441-688b0a5dcaab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3897266961 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_kmac_err_chk.3897266961
Directory /workspace/25.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/25.rom_ctrl_max_throughput_chk.1600604351
Short name T307
Test name
Test status
Simulation time 1446686284 ps
CPU time 13.73 seconds
Started May 19 12:54:03 PM PDT 24
Finished May 19 12:54:18 PM PDT 24
Peak memory 211300 kb
Host smart-389093a0-748b-457b-a19b-f289ae936f91
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1600604351 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_max_throughput_chk.1600604351
Directory /workspace/25.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/25.rom_ctrl_smoke.2967096295
Short name T192
Test name
Test status
Simulation time 8954095184 ps
CPU time 26.95 seconds
Started May 19 12:54:01 PM PDT 24
Finished May 19 12:54:30 PM PDT 24
Peak memory 214152 kb
Host smart-9cd4cb1d-122d-432e-840a-13b7ec9f62ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2967096295 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_smoke.2967096295
Directory /workspace/25.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/25.rom_ctrl_stress_all.2564399908
Short name T238
Test name
Test status
Simulation time 12249838601 ps
CPU time 38.15 seconds
Started May 19 12:53:54 PM PDT 24
Finished May 19 12:54:37 PM PDT 24
Peak memory 219340 kb
Host smart-f495a627-81fc-4f46-80b4-7c2581efe225
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2564399908 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 25.rom_ctrl_stress_all.2564399908
Directory /workspace/25.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/26.rom_ctrl_alert_test.2371267462
Short name T133
Test name
Test status
Simulation time 332743493 ps
CPU time 4.48 seconds
Started May 19 12:53:55 PM PDT 24
Finished May 19 12:54:03 PM PDT 24
Peak memory 211212 kb
Host smart-0769b53c-1632-417a-9935-14fd475a1e63
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2371267462 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_alert_test.2371267462
Directory /workspace/26.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/26.rom_ctrl_corrupt_sig_fatal_chk.4002486394
Short name T219
Test name
Test status
Simulation time 19751454143 ps
CPU time 104.27 seconds
Started May 19 12:54:04 PM PDT 24
Finished May 19 12:55:51 PM PDT 24
Peak memory 236860 kb
Host smart-5cabfee2-2058-4be3-8451-9c8b8784094c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4002486394 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_
corrupt_sig_fatal_chk.4002486394
Directory /workspace/26.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/26.rom_ctrl_kmac_err_chk.4216016720
Short name T210
Test name
Test status
Simulation time 170523971 ps
CPU time 9.61 seconds
Started May 19 12:53:51 PM PDT 24
Finished May 19 12:54:04 PM PDT 24
Peak memory 211816 kb
Host smart-ad06838b-45a8-4b79-8d6c-bfd158203cd8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4216016720 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_kmac_err_chk.4216016720
Directory /workspace/26.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/26.rom_ctrl_max_throughput_chk.1149897240
Short name T134
Test name
Test status
Simulation time 1588278299 ps
CPU time 12.48 seconds
Started May 19 12:53:52 PM PDT 24
Finished May 19 12:54:08 PM PDT 24
Peak memory 211060 kb
Host smart-79102ce0-2f6c-4124-8740-01d1fba62ee0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1149897240 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_max_throughput_chk.1149897240
Directory /workspace/26.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/26.rom_ctrl_smoke.1463424700
Short name T176
Test name
Test status
Simulation time 8615823955 ps
CPU time 27.42 seconds
Started May 19 12:53:48 PM PDT 24
Finished May 19 12:54:17 PM PDT 24
Peak memory 213760 kb
Host smart-b5b1c1b4-3b47-4cef-a1e2-abaeefb9e7c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1463424700 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_smoke.1463424700
Directory /workspace/26.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/26.rom_ctrl_stress_all.178189434
Short name T157
Test name
Test status
Simulation time 1169475764 ps
CPU time 19.39 seconds
Started May 19 12:53:53 PM PDT 24
Finished May 19 12:54:16 PM PDT 24
Peak memory 210944 kb
Host smart-be0070a1-9b10-410a-ba3f-dacbc02ad22e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=178189434 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 26.rom_ctrl_stress_all.178189434
Directory /workspace/26.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/27.rom_ctrl_alert_test.488980630
Short name T205
Test name
Test status
Simulation time 5097452614 ps
CPU time 12.48 seconds
Started May 19 12:54:02 PM PDT 24
Finished May 19 12:54:16 PM PDT 24
Peak memory 211308 kb
Host smart-bf20276b-2b94-49e0-9ed8-da6b5f50c764
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=488980630 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_alert_test.488980630
Directory /workspace/27.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/27.rom_ctrl_corrupt_sig_fatal_chk.3575177162
Short name T272
Test name
Test status
Simulation time 8175334249 ps
CPU time 137.26 seconds
Started May 19 12:54:07 PM PDT 24
Finished May 19 12:56:27 PM PDT 24
Peak memory 236776 kb
Host smart-c856f7e8-7a46-4f8f-aff5-3df09fe820dd
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3575177162 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_
corrupt_sig_fatal_chk.3575177162
Directory /workspace/27.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/27.rom_ctrl_kmac_err_chk.376609403
Short name T155
Test name
Test status
Simulation time 175490701 ps
CPU time 9.77 seconds
Started May 19 12:53:57 PM PDT 24
Finished May 19 12:54:10 PM PDT 24
Peak memory 211924 kb
Host smart-bf7ddce0-ed8a-4f43-9078-ff90442d2916
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=376609403 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_kmac_err_chk.376609403
Directory /workspace/27.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/27.rom_ctrl_max_throughput_chk.453625316
Short name T191
Test name
Test status
Simulation time 710115896 ps
CPU time 9.9 seconds
Started May 19 12:54:01 PM PDT 24
Finished May 19 12:54:13 PM PDT 24
Peak memory 211088 kb
Host smart-fd516084-c59c-4367-971e-6b61468512a8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=453625316 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_max_throughput_chk.453625316
Directory /workspace/27.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/27.rom_ctrl_smoke.468487877
Short name T336
Test name
Test status
Simulation time 3235185313 ps
CPU time 18.55 seconds
Started May 19 12:53:54 PM PDT 24
Finished May 19 12:54:16 PM PDT 24
Peak memory 213672 kb
Host smart-29c61f8c-818d-4e24-a270-b71ccc3d9d35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=468487877 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_smoke.468487877
Directory /workspace/27.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/27.rom_ctrl_stress_all.1448482033
Short name T102
Test name
Test status
Simulation time 1698167026 ps
CPU time 19.55 seconds
Started May 19 12:53:57 PM PDT 24
Finished May 19 12:54:20 PM PDT 24
Peak memory 219264 kb
Host smart-ace03443-d5f5-4ce4-99f1-3ea9b0b2a86f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1448482033 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 27.rom_ctrl_stress_all.1448482033
Directory /workspace/27.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/28.rom_ctrl_alert_test.3788350968
Short name T295
Test name
Test status
Simulation time 4122573496 ps
CPU time 10.67 seconds
Started May 19 12:54:03 PM PDT 24
Finished May 19 12:54:16 PM PDT 24
Peak memory 211252 kb
Host smart-4c6f36da-fd69-4ee4-8cc6-c8cdd6f99895
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3788350968 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_alert_test.3788350968
Directory /workspace/28.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/28.rom_ctrl_corrupt_sig_fatal_chk.2089503194
Short name T206
Test name
Test status
Simulation time 80669081012 ps
CPU time 611.96 seconds
Started May 19 12:53:55 PM PDT 24
Finished May 19 01:04:11 PM PDT 24
Peak memory 224924 kb
Host smart-c51e34b6-6d65-4676-8c02-22e4acf1c9d0
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2089503194 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_
corrupt_sig_fatal_chk.2089503194
Directory /workspace/28.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/28.rom_ctrl_kmac_err_chk.661579428
Short name T208
Test name
Test status
Simulation time 6228069248 ps
CPU time 28.42 seconds
Started May 19 12:54:01 PM PDT 24
Finished May 19 12:54:32 PM PDT 24
Peak memory 212416 kb
Host smart-d68f801f-ca54-44c4-a59b-a7f40e025235
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=661579428 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_kmac_err_chk.661579428
Directory /workspace/28.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/28.rom_ctrl_max_throughput_chk.1028894260
Short name T290
Test name
Test status
Simulation time 602661793 ps
CPU time 5.36 seconds
Started May 19 12:53:59 PM PDT 24
Finished May 19 12:54:07 PM PDT 24
Peak memory 211032 kb
Host smart-e6ddfdd2-5caf-4df0-80a0-ffb95ff9f834
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1028894260 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_max_throughput_chk.1028894260
Directory /workspace/28.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/28.rom_ctrl_smoke.3196430069
Short name T366
Test name
Test status
Simulation time 378857174 ps
CPU time 10.1 seconds
Started May 19 12:54:05 PM PDT 24
Finished May 19 12:54:18 PM PDT 24
Peak memory 219264 kb
Host smart-f6fb45c4-c059-4620-9eab-a50056510f34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3196430069 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_smoke.3196430069
Directory /workspace/28.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/28.rom_ctrl_stress_all.1552688739
Short name T333
Test name
Test status
Simulation time 1924052346 ps
CPU time 26.95 seconds
Started May 19 12:53:57 PM PDT 24
Finished May 19 12:54:27 PM PDT 24
Peak memory 214316 kb
Host smart-b10cd2f4-6452-4e79-8938-735a49743b47
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1552688739 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 28.rom_ctrl_stress_all.1552688739
Directory /workspace/28.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/29.rom_ctrl_alert_test.4276942688
Short name T306
Test name
Test status
Simulation time 1378824635 ps
CPU time 6.64 seconds
Started May 19 12:53:58 PM PDT 24
Finished May 19 12:54:07 PM PDT 24
Peak memory 211192 kb
Host smart-461f922c-8298-4a91-a0d9-40dbeab6684f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4276942688 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_alert_test.4276942688
Directory /workspace/29.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/29.rom_ctrl_corrupt_sig_fatal_chk.1229310568
Short name T275
Test name
Test status
Simulation time 14902147479 ps
CPU time 175.8 seconds
Started May 19 12:53:53 PM PDT 24
Finished May 19 12:56:52 PM PDT 24
Peak memory 228372 kb
Host smart-44357067-ca86-442e-bcb8-8d567b8807d5
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1229310568 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_
corrupt_sig_fatal_chk.1229310568
Directory /workspace/29.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/29.rom_ctrl_smoke.2268716048
Short name T78
Test name
Test status
Simulation time 14688605456 ps
CPU time 38.73 seconds
Started May 19 12:54:10 PM PDT 24
Finished May 19 12:54:53 PM PDT 24
Peak memory 219408 kb
Host smart-012bfe28-0004-4e21-8437-734baf10cdde
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2268716048 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_smoke.2268716048
Directory /workspace/29.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/29.rom_ctrl_stress_all.1333024857
Short name T226
Test name
Test status
Simulation time 49925201045 ps
CPU time 68.46 seconds
Started May 19 12:54:02 PM PDT 24
Finished May 19 12:55:13 PM PDT 24
Peak memory 219388 kb
Host smart-fc6cb5a9-25a6-4c3e-8892-2be689797d16
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1333024857 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 29.rom_ctrl_stress_all.1333024857
Directory /workspace/29.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/3.rom_ctrl_alert_test.875660067
Short name T288
Test name
Test status
Simulation time 1354093847 ps
CPU time 12.46 seconds
Started May 19 12:53:30 PM PDT 24
Finished May 19 12:53:44 PM PDT 24
Peak memory 211208 kb
Host smart-219d09eb-4eb7-42e6-8c25-2647eb68dd3c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=875660067 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_alert_test.875660067
Directory /workspace/3.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/3.rom_ctrl_corrupt_sig_fatal_chk.122748357
Short name T358
Test name
Test status
Simulation time 111073347241 ps
CPU time 352.72 seconds
Started May 19 12:53:47 PM PDT 24
Finished May 19 12:59:41 PM PDT 24
Peak memory 230756 kb
Host smart-1afb6073-8120-4299-99e2-ade3c826291a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=122748357 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_co
rrupt_sig_fatal_chk.122748357
Directory /workspace/3.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/3.rom_ctrl_kmac_err_chk.661738044
Short name T65
Test name
Test status
Simulation time 2756995076 ps
CPU time 11.88 seconds
Started May 19 12:53:40 PM PDT 24
Finished May 19 12:53:54 PM PDT 24
Peak memory 211868 kb
Host smart-1008a01a-c086-4fe6-b7f2-4b22d08b95ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=661738044 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_kmac_err_chk.661738044
Directory /workspace/3.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/3.rom_ctrl_max_throughput_chk.3362442460
Short name T256
Test name
Test status
Simulation time 203745754 ps
CPU time 5.51 seconds
Started May 19 12:53:37 PM PDT 24
Finished May 19 12:53:43 PM PDT 24
Peak memory 210932 kb
Host smart-68b7f6f6-b239-4607-a235-d774a8dd9011
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3362442460 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_max_throughput_chk.3362442460
Directory /workspace/3.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/3.rom_ctrl_smoke.3866761031
Short name T182
Test name
Test status
Simulation time 3361774589 ps
CPU time 29.83 seconds
Started May 19 12:53:31 PM PDT 24
Finished May 19 12:54:02 PM PDT 24
Peak memory 219352 kb
Host smart-63b2b889-531d-43e3-a1c9-1c51697a013c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3866761031 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_smoke.3866761031
Directory /workspace/3.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/3.rom_ctrl_stress_all.2580293012
Short name T103
Test name
Test status
Simulation time 2722727126 ps
CPU time 16.74 seconds
Started May 19 12:53:53 PM PDT 24
Finished May 19 12:54:13 PM PDT 24
Peak memory 210968 kb
Host smart-711092b7-e354-4715-8498-9c3f16212f3e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2580293012 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 3.rom_ctrl_stress_all.2580293012
Directory /workspace/3.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/30.rom_ctrl_corrupt_sig_fatal_chk.1869724164
Short name T40
Test name
Test status
Simulation time 71036147010 ps
CPU time 232.84 seconds
Started May 19 12:53:54 PM PDT 24
Finished May 19 12:57:50 PM PDT 24
Peak memory 229500 kb
Host smart-9fc5346d-f7b1-4bd7-beaa-806a8d16996c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1869724164 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_
corrupt_sig_fatal_chk.1869724164
Directory /workspace/30.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/30.rom_ctrl_kmac_err_chk.3207661571
Short name T222
Test name
Test status
Simulation time 9484693347 ps
CPU time 27.75 seconds
Started May 19 12:54:02 PM PDT 24
Finished May 19 12:54:32 PM PDT 24
Peak memory 212204 kb
Host smart-73cf02d7-70e8-4d42-a4f2-ffe5ef1c425d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3207661571 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_kmac_err_chk.3207661571
Directory /workspace/30.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/30.rom_ctrl_max_throughput_chk.3469876661
Short name T145
Test name
Test status
Simulation time 3530571173 ps
CPU time 13.78 seconds
Started May 19 12:53:53 PM PDT 24
Finished May 19 12:54:10 PM PDT 24
Peak memory 211152 kb
Host smart-9d42b600-64bf-485d-aacb-cdebce5b2f0e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3469876661 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_max_throughput_chk.3469876661
Directory /workspace/30.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/30.rom_ctrl_smoke.1866613379
Short name T77
Test name
Test status
Simulation time 8237315760 ps
CPU time 25.38 seconds
Started May 19 12:53:59 PM PDT 24
Finished May 19 12:54:27 PM PDT 24
Peak memory 219380 kb
Host smart-cf0f7500-edd7-4e59-85fa-fffb44bcde5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1866613379 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_smoke.1866613379
Directory /workspace/30.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/30.rom_ctrl_stress_all.235976410
Short name T9
Test name
Test status
Simulation time 2182949553 ps
CPU time 20.56 seconds
Started May 19 12:53:54 PM PDT 24
Finished May 19 12:54:19 PM PDT 24
Peak memory 211068 kb
Host smart-e5debff9-c890-46a4-a827-9ef8bc4ba568
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=235976410 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 30.rom_ctrl_stress_all.235976410
Directory /workspace/30.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/30.rom_ctrl_stress_all_with_rand_reset.2128847472
Short name T46
Test name
Test status
Simulation time 32221730294 ps
CPU time 2964.46 seconds
Started May 19 12:53:55 PM PDT 24
Finished May 19 01:43:24 PM PDT 24
Peak memory 236156 kb
Host smart-abe8bb87-db42-4361-bdcf-69d0d1d28cbf
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2128847472 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_stress_all_with_rand_reset.2128847472
Directory /workspace/30.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.rom_ctrl_alert_test.347358166
Short name T322
Test name
Test status
Simulation time 1787018018 ps
CPU time 10.11 seconds
Started May 19 12:53:52 PM PDT 24
Finished May 19 12:54:05 PM PDT 24
Peak memory 211100 kb
Host smart-3f06276a-a331-42a2-a92e-ee0e15970099
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=347358166 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_alert_test.347358166
Directory /workspace/31.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/31.rom_ctrl_corrupt_sig_fatal_chk.2932074948
Short name T329
Test name
Test status
Simulation time 40831023094 ps
CPU time 340.22 seconds
Started May 19 12:54:01 PM PDT 24
Finished May 19 12:59:44 PM PDT 24
Peak memory 237120 kb
Host smart-44471c08-289b-4d89-b22d-8b4d8965dc40
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2932074948 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_
corrupt_sig_fatal_chk.2932074948
Directory /workspace/31.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/31.rom_ctrl_kmac_err_chk.935567064
Short name T104
Test name
Test status
Simulation time 9949654415 ps
CPU time 24.09 seconds
Started May 19 12:54:10 PM PDT 24
Finished May 19 12:54:39 PM PDT 24
Peak memory 212252 kb
Host smart-32ca1d4d-eb51-46f0-b386-c2352663ed2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=935567064 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_kmac_err_chk.935567064
Directory /workspace/31.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/31.rom_ctrl_max_throughput_chk.1513857301
Short name T236
Test name
Test status
Simulation time 1605570229 ps
CPU time 14.46 seconds
Started May 19 12:53:59 PM PDT 24
Finished May 19 12:54:16 PM PDT 24
Peak memory 210972 kb
Host smart-241c2eb5-352f-415f-b16f-4e1959ccfafc
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1513857301 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_max_throughput_chk.1513857301
Directory /workspace/31.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/31.rom_ctrl_smoke.2279471004
Short name T267
Test name
Test status
Simulation time 3979222698 ps
CPU time 15.37 seconds
Started May 19 12:53:58 PM PDT 24
Finished May 19 12:54:17 PM PDT 24
Peak memory 213744 kb
Host smart-8aaabaea-fe2c-4753-8236-4d28ba699964
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2279471004 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_smoke.2279471004
Directory /workspace/31.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/31.rom_ctrl_stress_all.1472693532
Short name T263
Test name
Test status
Simulation time 3753447557 ps
CPU time 14.2 seconds
Started May 19 12:53:56 PM PDT 24
Finished May 19 12:54:14 PM PDT 24
Peak memory 211808 kb
Host smart-584995f2-12e3-4033-92e9-165560713969
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1472693532 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 31.rom_ctrl_stress_all.1472693532
Directory /workspace/31.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/31.rom_ctrl_stress_all_with_rand_reset.854237641
Short name T44
Test name
Test status
Simulation time 64794610740 ps
CPU time 625.36 seconds
Started May 19 12:53:54 PM PDT 24
Finished May 19 01:04:23 PM PDT 24
Peak memory 227712 kb
Host smart-ba5d29b9-51f3-4038-aa28-e2eb6d32e923
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=854237641 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_stress_all_with_rand_reset.854237641
Directory /workspace/31.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.rom_ctrl_alert_test.3569696435
Short name T314
Test name
Test status
Simulation time 3811000243 ps
CPU time 10.43 seconds
Started May 19 12:53:56 PM PDT 24
Finished May 19 12:54:10 PM PDT 24
Peak memory 211336 kb
Host smart-bac22f46-ab17-42be-aff9-569a224cb6b2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3569696435 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_alert_test.3569696435
Directory /workspace/32.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/32.rom_ctrl_corrupt_sig_fatal_chk.201259241
Short name T340
Test name
Test status
Simulation time 1606725535 ps
CPU time 106.06 seconds
Started May 19 12:54:03 PM PDT 24
Finished May 19 12:55:51 PM PDT 24
Peak memory 228492 kb
Host smart-be85b8ac-e64e-43d6-8887-a79dd44c1f9b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=201259241 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_c
orrupt_sig_fatal_chk.201259241
Directory /workspace/32.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/32.rom_ctrl_kmac_err_chk.1458791136
Short name T100
Test name
Test status
Simulation time 693163886 ps
CPU time 9.59 seconds
Started May 19 12:53:54 PM PDT 24
Finished May 19 12:54:07 PM PDT 24
Peak memory 211924 kb
Host smart-146393f7-0cf1-47b3-866f-159428b9dd01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1458791136 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_kmac_err_chk.1458791136
Directory /workspace/32.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/32.rom_ctrl_max_throughput_chk.1578859702
Short name T187
Test name
Test status
Simulation time 5243300319 ps
CPU time 12.76 seconds
Started May 19 12:54:12 PM PDT 24
Finished May 19 12:54:30 PM PDT 24
Peak memory 211164 kb
Host smart-a0006d6a-f2d7-43a3-af54-1810cd345bc0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1578859702 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_max_throughput_chk.1578859702
Directory /workspace/32.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/32.rom_ctrl_smoke.3529722325
Short name T321
Test name
Test status
Simulation time 3747261371 ps
CPU time 28.92 seconds
Started May 19 12:53:56 PM PDT 24
Finished May 19 12:54:28 PM PDT 24
Peak memory 219636 kb
Host smart-e8a9726f-2dda-45e6-abdf-2d6d9d430bfe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3529722325 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_smoke.3529722325
Directory /workspace/32.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/32.rom_ctrl_stress_all.2259862373
Short name T242
Test name
Test status
Simulation time 4908807797 ps
CPU time 28.35 seconds
Started May 19 12:53:57 PM PDT 24
Finished May 19 12:54:29 PM PDT 24
Peak memory 219276 kb
Host smart-75149d16-34cc-4b06-8414-4de91e5f08fe
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2259862373 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 32.rom_ctrl_stress_all.2259862373
Directory /workspace/32.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/32.rom_ctrl_stress_all_with_rand_reset.356491463
Short name T111
Test name
Test status
Simulation time 7980358513 ps
CPU time 1042.98 seconds
Started May 19 12:54:00 PM PDT 24
Finished May 19 01:11:25 PM PDT 24
Peak memory 222724 kb
Host smart-d9f19c3c-7bae-4bd5-befc-55913a8f1c17
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=356491463 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_stress_all_with_rand_reset.356491463
Directory /workspace/32.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.rom_ctrl_alert_test.3318899051
Short name T250
Test name
Test status
Simulation time 5508687702 ps
CPU time 12.36 seconds
Started May 19 12:54:06 PM PDT 24
Finished May 19 12:54:21 PM PDT 24
Peak memory 211228 kb
Host smart-c8cf9bee-b956-42f5-b5da-92b79c0881b1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3318899051 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_alert_test.3318899051
Directory /workspace/33.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/33.rom_ctrl_corrupt_sig_fatal_chk.1044606854
Short name T230
Test name
Test status
Simulation time 75285691408 ps
CPU time 190.09 seconds
Started May 19 12:54:08 PM PDT 24
Finished May 19 12:57:20 PM PDT 24
Peak memory 218572 kb
Host smart-bf98a0a0-602d-4ce6-8d74-898794d7dbbd
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1044606854 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_
corrupt_sig_fatal_chk.1044606854
Directory /workspace/33.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/33.rom_ctrl_max_throughput_chk.1850650323
Short name T257
Test name
Test status
Simulation time 4864144083 ps
CPU time 12.67 seconds
Started May 19 12:53:59 PM PDT 24
Finished May 19 12:54:15 PM PDT 24
Peak memory 211060 kb
Host smart-c3013129-fdf8-4eba-b193-ff0d3172662f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1850650323 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_max_throughput_chk.1850650323
Directory /workspace/33.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/33.rom_ctrl_smoke.4026806165
Short name T80
Test name
Test status
Simulation time 1138819304 ps
CPU time 15.24 seconds
Started May 19 12:53:53 PM PDT 24
Finished May 19 12:54:13 PM PDT 24
Peak memory 211724 kb
Host smart-c223fc72-1097-4d1d-8664-59693438b261
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4026806165 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_smoke.4026806165
Directory /workspace/33.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/33.rom_ctrl_stress_all.1689938708
Short name T162
Test name
Test status
Simulation time 493500925 ps
CPU time 26.44 seconds
Started May 19 12:54:00 PM PDT 24
Finished May 19 12:54:29 PM PDT 24
Peak memory 219260 kb
Host smart-e25fd488-f05a-40ca-929d-34ad83cb3850
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1689938708 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 33.rom_ctrl_stress_all.1689938708
Directory /workspace/33.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/34.rom_ctrl_alert_test.3243482778
Short name T62
Test name
Test status
Simulation time 3663930297 ps
CPU time 9.33 seconds
Started May 19 12:54:06 PM PDT 24
Finished May 19 12:54:18 PM PDT 24
Peak memory 211308 kb
Host smart-3036d073-4957-4787-a959-6aed3ac16c7e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3243482778 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_alert_test.3243482778
Directory /workspace/34.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/34.rom_ctrl_corrupt_sig_fatal_chk.3309149805
Short name T262
Test name
Test status
Simulation time 43345911608 ps
CPU time 438.19 seconds
Started May 19 12:54:05 PM PDT 24
Finished May 19 01:01:26 PM PDT 24
Peak memory 229100 kb
Host smart-e752f0ea-314e-4eff-b2ae-cfbaf8b007bb
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3309149805 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_
corrupt_sig_fatal_chk.3309149805
Directory /workspace/34.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/34.rom_ctrl_kmac_err_chk.2456607982
Short name T137
Test name
Test status
Simulation time 4166215851 ps
CPU time 32.28 seconds
Started May 19 12:54:10 PM PDT 24
Finished May 19 12:54:46 PM PDT 24
Peak memory 211384 kb
Host smart-10560033-5a26-4236-88f4-2105e3f298e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2456607982 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_kmac_err_chk.2456607982
Directory /workspace/34.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/34.rom_ctrl_max_throughput_chk.458040240
Short name T200
Test name
Test status
Simulation time 97039929 ps
CPU time 5.29 seconds
Started May 19 12:54:09 PM PDT 24
Finished May 19 12:54:18 PM PDT 24
Peak memory 210952 kb
Host smart-0124fa20-10bd-4fa0-9ad5-9313728267df
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=458040240 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_max_throughput_chk.458040240
Directory /workspace/34.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/34.rom_ctrl_smoke.1818770105
Short name T234
Test name
Test status
Simulation time 367093481 ps
CPU time 13.08 seconds
Started May 19 12:54:10 PM PDT 24
Finished May 19 12:54:28 PM PDT 24
Peak memory 213692 kb
Host smart-e89a7ca5-0108-45cb-aa46-fde314901c65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1818770105 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_smoke.1818770105
Directory /workspace/34.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/34.rom_ctrl_stress_all.3210703846
Short name T332
Test name
Test status
Simulation time 1189905555 ps
CPU time 26.35 seconds
Started May 19 12:54:02 PM PDT 24
Finished May 19 12:54:31 PM PDT 24
Peak memory 214284 kb
Host smart-74e2fc79-5d17-4ed2-a67d-677660741d48
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3210703846 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 34.rom_ctrl_stress_all.3210703846
Directory /workspace/34.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/34.rom_ctrl_stress_all_with_rand_reset.209859318
Short name T18
Test name
Test status
Simulation time 35867946485 ps
CPU time 2158.36 seconds
Started May 19 12:54:02 PM PDT 24
Finished May 19 01:30:03 PM PDT 24
Peak memory 235840 kb
Host smart-1ab78ec2-1dd9-4403-8adf-cd8c527ac399
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=209859318 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_stress_all_with_rand_reset.209859318
Directory /workspace/34.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.rom_ctrl_alert_test.3843776940
Short name T183
Test name
Test status
Simulation time 1923452568 ps
CPU time 14.46 seconds
Started May 19 12:54:10 PM PDT 24
Finished May 19 12:54:29 PM PDT 24
Peak memory 211192 kb
Host smart-4a33c573-95a4-4f44-a22b-7453adf9918e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3843776940 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_alert_test.3843776940
Directory /workspace/35.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/35.rom_ctrl_corrupt_sig_fatal_chk.752030680
Short name T268
Test name
Test status
Simulation time 3397735259 ps
CPU time 102.32 seconds
Started May 19 12:54:05 PM PDT 24
Finished May 19 12:55:49 PM PDT 24
Peak memory 237888 kb
Host smart-47868625-148f-469e-819a-3554c23dca0e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=752030680 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_c
orrupt_sig_fatal_chk.752030680
Directory /workspace/35.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/35.rom_ctrl_kmac_err_chk.674098001
Short name T207
Test name
Test status
Simulation time 663487425 ps
CPU time 14.36 seconds
Started May 19 12:54:02 PM PDT 24
Finished May 19 12:54:19 PM PDT 24
Peak memory 211836 kb
Host smart-00cce427-749f-4028-ac7c-e0bcfa9211dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=674098001 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_kmac_err_chk.674098001
Directory /workspace/35.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/35.rom_ctrl_max_throughput_chk.2586555290
Short name T229
Test name
Test status
Simulation time 867087128 ps
CPU time 6.82 seconds
Started May 19 12:54:05 PM PDT 24
Finished May 19 12:54:14 PM PDT 24
Peak memory 211024 kb
Host smart-39fde0f1-0046-4b4e-9199-953dcfcbb8bd
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2586555290 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_max_throughput_chk.2586555290
Directory /workspace/35.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/35.rom_ctrl_smoke.4159872482
Short name T247
Test name
Test status
Simulation time 4044031996 ps
CPU time 37.34 seconds
Started May 19 12:54:06 PM PDT 24
Finished May 19 12:54:46 PM PDT 24
Peak memory 219368 kb
Host smart-55ea8034-cae8-493c-9668-9db5b7a414c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4159872482 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_smoke.4159872482
Directory /workspace/35.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/35.rom_ctrl_stress_all.2679731647
Short name T252
Test name
Test status
Simulation time 6612721314 ps
CPU time 17.77 seconds
Started May 19 12:54:02 PM PDT 24
Finished May 19 12:54:22 PM PDT 24
Peak memory 210948 kb
Host smart-33000c4b-e72c-4beb-80c1-34dd9ab63f9b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2679731647 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 35.rom_ctrl_stress_all.2679731647
Directory /workspace/35.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/36.rom_ctrl_alert_test.3632018288
Short name T64
Test name
Test status
Simulation time 215423410 ps
CPU time 4.17 seconds
Started May 19 12:54:14 PM PDT 24
Finished May 19 12:54:24 PM PDT 24
Peak memory 211100 kb
Host smart-28c6e35e-c09d-46ed-a645-41422670db0d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3632018288 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_alert_test.3632018288
Directory /workspace/36.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/36.rom_ctrl_corrupt_sig_fatal_chk.2147702898
Short name T172
Test name
Test status
Simulation time 18389258423 ps
CPU time 217 seconds
Started May 19 12:54:04 PM PDT 24
Finished May 19 12:57:43 PM PDT 24
Peak memory 229656 kb
Host smart-89bd0ff5-5940-4585-aafb-6f0c5a2c8d83
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2147702898 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_
corrupt_sig_fatal_chk.2147702898
Directory /workspace/36.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/36.rom_ctrl_kmac_err_chk.3036422277
Short name T308
Test name
Test status
Simulation time 13412061765 ps
CPU time 27.64 seconds
Started May 19 12:54:05 PM PDT 24
Finished May 19 12:54:34 PM PDT 24
Peak memory 212132 kb
Host smart-d0a67b2c-b893-4fca-a801-ea875084e988
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3036422277 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_kmac_err_chk.3036422277
Directory /workspace/36.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/36.rom_ctrl_max_throughput_chk.1619135329
Short name T51
Test name
Test status
Simulation time 2623105045 ps
CPU time 12.64 seconds
Started May 19 12:54:05 PM PDT 24
Finished May 19 12:54:20 PM PDT 24
Peak memory 211108 kb
Host smart-9a7c3c67-6031-4687-8ecd-5357f193481f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1619135329 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_max_throughput_chk.1619135329
Directory /workspace/36.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/36.rom_ctrl_smoke.3215611142
Short name T189
Test name
Test status
Simulation time 700331518 ps
CPU time 14.5 seconds
Started May 19 12:54:08 PM PDT 24
Finished May 19 12:54:25 PM PDT 24
Peak memory 213352 kb
Host smart-93c02181-181e-48ed-b076-16c166e25202
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3215611142 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_smoke.3215611142
Directory /workspace/36.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/36.rom_ctrl_stress_all.3298611200
Short name T8
Test name
Test status
Simulation time 12903724913 ps
CPU time 26.86 seconds
Started May 19 12:54:07 PM PDT 24
Finished May 19 12:54:37 PM PDT 24
Peak memory 214432 kb
Host smart-58324a24-e040-4a74-8bd1-61b2024b423f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3298611200 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 36.rom_ctrl_stress_all.3298611200
Directory /workspace/36.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/37.rom_ctrl_alert_test.3486408807
Short name T146
Test name
Test status
Simulation time 7495113338 ps
CPU time 15.21 seconds
Started May 19 12:54:05 PM PDT 24
Finished May 19 12:54:22 PM PDT 24
Peak memory 211340 kb
Host smart-03066b78-eb7b-487f-b9fb-135bac0afeae
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3486408807 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_alert_test.3486408807
Directory /workspace/37.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/37.rom_ctrl_corrupt_sig_fatal_chk.1076790892
Short name T198
Test name
Test status
Simulation time 6154719370 ps
CPU time 107.97 seconds
Started May 19 12:54:03 PM PDT 24
Finished May 19 12:55:53 PM PDT 24
Peak memory 236816 kb
Host smart-0b84f032-20ff-4756-897f-c2c1e0e99159
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1076790892 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_
corrupt_sig_fatal_chk.1076790892
Directory /workspace/37.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/37.rom_ctrl_kmac_err_chk.338153136
Short name T259
Test name
Test status
Simulation time 8477170771 ps
CPU time 35.9 seconds
Started May 19 12:54:06 PM PDT 24
Finished May 19 12:54:44 PM PDT 24
Peak memory 212548 kb
Host smart-57eb91e9-0155-4ee4-a031-9fad8b2e0d57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=338153136 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_kmac_err_chk.338153136
Directory /workspace/37.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/37.rom_ctrl_max_throughput_chk.125530403
Short name T177
Test name
Test status
Simulation time 522919216 ps
CPU time 5.23 seconds
Started May 19 12:54:04 PM PDT 24
Finished May 19 12:54:11 PM PDT 24
Peak memory 211020 kb
Host smart-28545e15-98ae-4180-840f-9faa9de2855b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=125530403 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_max_throughput_chk.125530403
Directory /workspace/37.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/37.rom_ctrl_smoke.3284156448
Short name T315
Test name
Test status
Simulation time 18750095409 ps
CPU time 26.69 seconds
Started May 19 12:54:05 PM PDT 24
Finished May 19 12:54:33 PM PDT 24
Peak memory 214288 kb
Host smart-75412085-5aa8-4cf1-9c0c-6d1a42adcfce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3284156448 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_smoke.3284156448
Directory /workspace/37.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/37.rom_ctrl_stress_all.3796427077
Short name T76
Test name
Test status
Simulation time 2330492193 ps
CPU time 11.21 seconds
Started May 19 12:53:59 PM PDT 24
Finished May 19 12:54:13 PM PDT 24
Peak memory 211160 kb
Host smart-8829ddd8-2bbc-4566-8741-5747b7eec9d3
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3796427077 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 37.rom_ctrl_stress_all.3796427077
Directory /workspace/37.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/38.rom_ctrl_alert_test.3465330661
Short name T348
Test name
Test status
Simulation time 87980015 ps
CPU time 4.28 seconds
Started May 19 12:54:11 PM PDT 24
Finished May 19 12:54:20 PM PDT 24
Peak memory 211184 kb
Host smart-6bddb1aa-ed18-4225-8b0a-cba9435342a5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3465330661 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_alert_test.3465330661
Directory /workspace/38.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/38.rom_ctrl_corrupt_sig_fatal_chk.1599435815
Short name T169
Test name
Test status
Simulation time 96819609697 ps
CPU time 252.06 seconds
Started May 19 12:54:10 PM PDT 24
Finished May 19 12:58:27 PM PDT 24
Peak memory 233772 kb
Host smart-36de1e97-0de2-4942-99bd-7ff0dd89bffd
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1599435815 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_
corrupt_sig_fatal_chk.1599435815
Directory /workspace/38.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/38.rom_ctrl_kmac_err_chk.236811741
Short name T341
Test name
Test status
Simulation time 9486544383 ps
CPU time 35.37 seconds
Started May 19 12:54:00 PM PDT 24
Finished May 19 12:54:38 PM PDT 24
Peak memory 212208 kb
Host smart-c4680612-3644-4f00-a495-ade2c2d762b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=236811741 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_kmac_err_chk.236811741
Directory /workspace/38.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/38.rom_ctrl_max_throughput_chk.143830031
Short name T362
Test name
Test status
Simulation time 98415685 ps
CPU time 5.3 seconds
Started May 19 12:54:05 PM PDT 24
Finished May 19 12:54:13 PM PDT 24
Peak memory 210948 kb
Host smart-f4e37ac9-5562-410c-8d5f-727b0908f309
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=143830031 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_max_throughput_chk.143830031
Directory /workspace/38.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/38.rom_ctrl_smoke.775001515
Short name T270
Test name
Test status
Simulation time 8065881337 ps
CPU time 33.06 seconds
Started May 19 12:54:02 PM PDT 24
Finished May 19 12:54:37 PM PDT 24
Peak memory 213724 kb
Host smart-4c2cfaf7-9dfe-4545-af54-e7ab67ef153e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=775001515 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_smoke.775001515
Directory /workspace/38.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/38.rom_ctrl_stress_all.712705247
Short name T342
Test name
Test status
Simulation time 19614118119 ps
CPU time 35.64 seconds
Started May 19 12:54:11 PM PDT 24
Finished May 19 12:54:53 PM PDT 24
Peak memory 219292 kb
Host smart-579573cb-bdf6-483c-8ed2-9a5bc02174c1
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=712705247 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 38.rom_ctrl_stress_all.712705247
Directory /workspace/38.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/39.rom_ctrl_alert_test.63640108
Short name T266
Test name
Test status
Simulation time 377554170 ps
CPU time 4.27 seconds
Started May 19 12:54:12 PM PDT 24
Finished May 19 12:54:22 PM PDT 24
Peak memory 211184 kb
Host smart-d23a501d-2cce-4a3a-a5ef-18632ce408d1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=63640108 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_alert_test.63640108
Directory /workspace/39.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/39.rom_ctrl_corrupt_sig_fatal_chk.4201946191
Short name T365
Test name
Test status
Simulation time 28980497132 ps
CPU time 151.5 seconds
Started May 19 12:54:13 PM PDT 24
Finished May 19 12:56:50 PM PDT 24
Peak memory 233732 kb
Host smart-fd798228-0e40-489e-8d88-517088be04e1
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4201946191 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_
corrupt_sig_fatal_chk.4201946191
Directory /workspace/39.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/39.rom_ctrl_kmac_err_chk.3089351166
Short name T294
Test name
Test status
Simulation time 4906613201 ps
CPU time 25.32 seconds
Started May 19 12:54:10 PM PDT 24
Finished May 19 12:54:40 PM PDT 24
Peak memory 212264 kb
Host smart-2d93a8f9-4efd-4809-8e9a-ab788c8f93d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3089351166 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_kmac_err_chk.3089351166
Directory /workspace/39.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/39.rom_ctrl_max_throughput_chk.3657557875
Short name T167
Test name
Test status
Simulation time 1249191005 ps
CPU time 12.53 seconds
Started May 19 12:54:10 PM PDT 24
Finished May 19 12:54:26 PM PDT 24
Peak memory 210940 kb
Host smart-026a6adb-66f6-4d30-a863-aceee1ded43a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3657557875 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_max_throughput_chk.3657557875
Directory /workspace/39.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/39.rom_ctrl_smoke.3508002592
Short name T141
Test name
Test status
Simulation time 6050657426 ps
CPU time 28.86 seconds
Started May 19 12:54:08 PM PDT 24
Finished May 19 12:54:39 PM PDT 24
Peak memory 219420 kb
Host smart-df46ca69-7385-470d-a6a4-dd476cf37545
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3508002592 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_smoke.3508002592
Directory /workspace/39.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/39.rom_ctrl_stress_all.865810644
Short name T221
Test name
Test status
Simulation time 21174905868 ps
CPU time 28.5 seconds
Started May 19 12:54:08 PM PDT 24
Finished May 19 12:54:40 PM PDT 24
Peak memory 214724 kb
Host smart-8b7cf9aa-d10e-409e-9b5b-38cddf67b917
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=865810644 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 39.rom_ctrl_stress_all.865810644
Directory /workspace/39.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/4.rom_ctrl_alert_test.1217317367
Short name T52
Test name
Test status
Simulation time 2630471398 ps
CPU time 12.34 seconds
Started May 19 12:53:34 PM PDT 24
Finished May 19 12:53:48 PM PDT 24
Peak memory 211248 kb
Host smart-136556f6-5891-4063-bb68-ffb6cd5d64f9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1217317367 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_alert_test.1217317367
Directory /workspace/4.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/4.rom_ctrl_corrupt_sig_fatal_chk.48213628
Short name T30
Test name
Test status
Simulation time 2727522525 ps
CPU time 86.33 seconds
Started May 19 12:53:33 PM PDT 24
Finished May 19 12:55:00 PM PDT 24
Peak memory 230136 kb
Host smart-f827407b-f0e4-415c-a9f6-5f162d423feb
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=48213628 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_
sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_cor
rupt_sig_fatal_chk.48213628
Directory /workspace/4.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/4.rom_ctrl_kmac_err_chk.2904830024
Short name T338
Test name
Test status
Simulation time 16469894668 ps
CPU time 33.93 seconds
Started May 19 12:53:33 PM PDT 24
Finished May 19 12:54:07 PM PDT 24
Peak memory 212272 kb
Host smart-b578ca81-c7d7-4a38-8f26-7497a6cfd640
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2904830024 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_kmac_err_chk.2904830024
Directory /workspace/4.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/4.rom_ctrl_max_throughput_chk.3416735071
Short name T246
Test name
Test status
Simulation time 102213258 ps
CPU time 5.67 seconds
Started May 19 12:53:42 PM PDT 24
Finished May 19 12:53:50 PM PDT 24
Peak memory 210912 kb
Host smart-bb20d610-f4f1-4049-b282-9460636a5589
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3416735071 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_max_throughput_chk.3416735071
Directory /workspace/4.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/4.rom_ctrl_sec_cm.3767689836
Short name T33
Test name
Test status
Simulation time 3058772878 ps
CPU time 58.54 seconds
Started May 19 12:53:30 PM PDT 24
Finished May 19 12:54:30 PM PDT 24
Peak memory 239524 kb
Host smart-fcc484d1-430c-4782-aac4-7c7f3a11f0ed
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3767689836 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_sec_cm.3767689836
Directory /workspace/4.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/4.rom_ctrl_smoke.2697205086
Short name T154
Test name
Test status
Simulation time 897784482 ps
CPU time 9.97 seconds
Started May 19 12:53:41 PM PDT 24
Finished May 19 12:53:53 PM PDT 24
Peak memory 219212 kb
Host smart-81640874-0b4c-4b58-926c-229e9decd324
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2697205086 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_smoke.2697205086
Directory /workspace/4.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/4.rom_ctrl_stress_all.691345088
Short name T244
Test name
Test status
Simulation time 1068801829 ps
CPU time 24.04 seconds
Started May 19 12:53:44 PM PDT 24
Finished May 19 12:54:10 PM PDT 24
Peak memory 216128 kb
Host smart-9524492b-306c-4562-ac15-28141cbc7d56
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=691345088 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 4.rom_ctrl_stress_all.691345088
Directory /workspace/4.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/4.rom_ctrl_stress_all_with_rand_reset.1285158999
Short name T269
Test name
Test status
Simulation time 31597585635 ps
CPU time 1223.91 seconds
Started May 19 12:53:44 PM PDT 24
Finished May 19 01:14:09 PM PDT 24
Peak memory 235892 kb
Host smart-3203e284-065f-4760-bfb0-06e6c258a3b3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1285158999 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_stress_all_with_rand_reset.1285158999
Directory /workspace/4.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.rom_ctrl_alert_test.611593243
Short name T217
Test name
Test status
Simulation time 89124407 ps
CPU time 4.32 seconds
Started May 19 12:54:13 PM PDT 24
Finished May 19 12:54:24 PM PDT 24
Peak memory 211212 kb
Host smart-0e880268-bfa3-462e-8cb9-022b6e679319
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=611593243 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_alert_test.611593243
Directory /workspace/40.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/40.rom_ctrl_kmac_err_chk.344089894
Short name T292
Test name
Test status
Simulation time 186882550 ps
CPU time 9.28 seconds
Started May 19 12:54:06 PM PDT 24
Finished May 19 12:54:18 PM PDT 24
Peak memory 211164 kb
Host smart-a1a9af70-c07d-4ee5-8276-053488bf6e32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=344089894 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_kmac_err_chk.344089894
Directory /workspace/40.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/40.rom_ctrl_max_throughput_chk.356788711
Short name T289
Test name
Test status
Simulation time 7141942143 ps
CPU time 15.95 seconds
Started May 19 12:54:07 PM PDT 24
Finished May 19 12:54:25 PM PDT 24
Peak memory 211188 kb
Host smart-4a8ebfa0-51c4-42c5-9b5b-57e757c7bcf2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=356788711 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_max_throughput_chk.356788711
Directory /workspace/40.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/40.rom_ctrl_smoke.3110438237
Short name T316
Test name
Test status
Simulation time 2982326274 ps
CPU time 27.4 seconds
Started May 19 12:54:10 PM PDT 24
Finished May 19 12:54:41 PM PDT 24
Peak memory 212892 kb
Host smart-09a0f43b-5b61-4d72-b10e-1a34d6f25b49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3110438237 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_smoke.3110438237
Directory /workspace/40.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/40.rom_ctrl_stress_all.3862727049
Short name T331
Test name
Test status
Simulation time 16320654238 ps
CPU time 13.35 seconds
Started May 19 12:54:08 PM PDT 24
Finished May 19 12:54:25 PM PDT 24
Peak memory 211132 kb
Host smart-0a3d6c64-4dd1-4754-83ff-87749655f582
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3862727049 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 40.rom_ctrl_stress_all.3862727049
Directory /workspace/40.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/41.rom_ctrl_alert_test.656972850
Short name T35
Test name
Test status
Simulation time 2070806240 ps
CPU time 16.52 seconds
Started May 19 12:54:06 PM PDT 24
Finished May 19 12:54:25 PM PDT 24
Peak memory 211120 kb
Host smart-78fabf7a-f8bb-4bb6-93e4-bb0ed18ea5d8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=656972850 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_alert_test.656972850
Directory /workspace/41.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/41.rom_ctrl_corrupt_sig_fatal_chk.1310097730
Short name T278
Test name
Test status
Simulation time 41868466199 ps
CPU time 239.9 seconds
Started May 19 12:54:10 PM PDT 24
Finished May 19 12:58:16 PM PDT 24
Peak memory 236816 kb
Host smart-7bcbef06-ab1b-4f5e-b27a-6ea6427ba59e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1310097730 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_
corrupt_sig_fatal_chk.1310097730
Directory /workspace/41.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/41.rom_ctrl_kmac_err_chk.1628700650
Short name T156
Test name
Test status
Simulation time 2394049068 ps
CPU time 24.06 seconds
Started May 19 12:54:09 PM PDT 24
Finished May 19 12:54:36 PM PDT 24
Peak memory 211924 kb
Host smart-84763bc0-4d74-410e-bc4a-74ad485b7100
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1628700650 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_kmac_err_chk.1628700650
Directory /workspace/41.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/41.rom_ctrl_max_throughput_chk.74921804
Short name T151
Test name
Test status
Simulation time 8722274165 ps
CPU time 11.44 seconds
Started May 19 12:54:15 PM PDT 24
Finished May 19 12:54:32 PM PDT 24
Peak memory 211160 kb
Host smart-7d351904-f7f9-44ee-b086-add6d594bad1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=74921804 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_max_throughput_chk.74921804
Directory /workspace/41.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/41.rom_ctrl_smoke.4038580389
Short name T218
Test name
Test status
Simulation time 7743875317 ps
CPU time 31.51 seconds
Started May 19 12:54:14 PM PDT 24
Finished May 19 12:54:52 PM PDT 24
Peak memory 219396 kb
Host smart-ed229173-36ce-4e59-828e-0ba702f4d3db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4038580389 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_smoke.4038580389
Directory /workspace/41.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/41.rom_ctrl_stress_all.1694092513
Short name T126
Test name
Test status
Simulation time 14985365301 ps
CPU time 50.89 seconds
Started May 19 12:54:05 PM PDT 24
Finished May 19 12:54:59 PM PDT 24
Peak memory 219312 kb
Host smart-eba2e3b8-919d-4915-a2c7-a18f7b950625
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1694092513 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 41.rom_ctrl_stress_all.1694092513
Directory /workspace/41.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/41.rom_ctrl_stress_all_with_rand_reset.420105050
Short name T232
Test name
Test status
Simulation time 10404735737 ps
CPU time 401.31 seconds
Started May 19 12:54:06 PM PDT 24
Finished May 19 01:00:50 PM PDT 24
Peak memory 227704 kb
Host smart-c608c14e-0695-4c0e-b387-f7fbd36c8df7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=420105050 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_stress_all_with_rand_reset.420105050
Directory /workspace/41.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.rom_ctrl_alert_test.2958883505
Short name T135
Test name
Test status
Simulation time 994719837 ps
CPU time 10.18 seconds
Started May 19 12:54:10 PM PDT 24
Finished May 19 12:54:26 PM PDT 24
Peak memory 211132 kb
Host smart-d659b661-8a05-470c-a557-deebc8a85195
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2958883505 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_alert_test.2958883505
Directory /workspace/42.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/42.rom_ctrl_corrupt_sig_fatal_chk.1653629974
Short name T249
Test name
Test status
Simulation time 33542138236 ps
CPU time 192.78 seconds
Started May 19 12:54:13 PM PDT 24
Finished May 19 12:57:32 PM PDT 24
Peak memory 234916 kb
Host smart-52472a29-2adb-4bd9-8719-33d08787f072
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1653629974 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_
corrupt_sig_fatal_chk.1653629974
Directory /workspace/42.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/42.rom_ctrl_kmac_err_chk.371164993
Short name T149
Test name
Test status
Simulation time 664714554 ps
CPU time 9.54 seconds
Started May 19 12:54:11 PM PDT 24
Finished May 19 12:54:31 PM PDT 24
Peak memory 211736 kb
Host smart-79ee6f71-e01f-44f9-9ee8-e113be2c2dc5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=371164993 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_kmac_err_chk.371164993
Directory /workspace/42.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/42.rom_ctrl_max_throughput_chk.1152357633
Short name T131
Test name
Test status
Simulation time 11052991904 ps
CPU time 9.77 seconds
Started May 19 12:54:07 PM PDT 24
Finished May 19 12:54:20 PM PDT 24
Peak memory 211076 kb
Host smart-b7ed0cc8-722e-4d8b-a730-c6ffe54e8dd7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1152357633 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_max_throughput_chk.1152357633
Directory /workspace/42.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/42.rom_ctrl_smoke.2802765588
Short name T243
Test name
Test status
Simulation time 903473623 ps
CPU time 10.57 seconds
Started May 19 12:54:11 PM PDT 24
Finished May 19 12:54:27 PM PDT 24
Peak memory 219268 kb
Host smart-80467ac6-4313-4786-bbfe-b7b9dcd7a0c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2802765588 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_smoke.2802765588
Directory /workspace/42.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/42.rom_ctrl_stress_all.3709966257
Short name T286
Test name
Test status
Simulation time 22728490732 ps
CPU time 54.12 seconds
Started May 19 12:54:14 PM PDT 24
Finished May 19 12:55:14 PM PDT 24
Peak memory 216336 kb
Host smart-26de67f5-ac4a-4994-be54-2484c3a8741d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3709966257 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 42.rom_ctrl_stress_all.3709966257
Directory /workspace/42.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/43.rom_ctrl_alert_test.3701216386
Short name T271
Test name
Test status
Simulation time 1944065107 ps
CPU time 14.97 seconds
Started May 19 12:54:09 PM PDT 24
Finished May 19 12:54:27 PM PDT 24
Peak memory 211144 kb
Host smart-f7b522c7-cf63-4e97-b907-ba1f6f899b65
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3701216386 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_alert_test.3701216386
Directory /workspace/43.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/43.rom_ctrl_corrupt_sig_fatal_chk.1185529768
Short name T305
Test name
Test status
Simulation time 139061699396 ps
CPU time 307.72 seconds
Started May 19 12:54:11 PM PDT 24
Finished May 19 12:59:24 PM PDT 24
Peak memory 229800 kb
Host smart-d8b76bd1-73c5-4072-bebc-15c13b143a1f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1185529768 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_
corrupt_sig_fatal_chk.1185529768
Directory /workspace/43.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/43.rom_ctrl_kmac_err_chk.3450050293
Short name T101
Test name
Test status
Simulation time 1281711815 ps
CPU time 17.38 seconds
Started May 19 12:54:16 PM PDT 24
Finished May 19 12:54:38 PM PDT 24
Peak memory 211724 kb
Host smart-68bd5347-61b3-4515-b8b2-74a096a98b8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3450050293 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_kmac_err_chk.3450050293
Directory /workspace/43.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/43.rom_ctrl_max_throughput_chk.3386767922
Short name T196
Test name
Test status
Simulation time 1277565719 ps
CPU time 12.98 seconds
Started May 19 12:54:12 PM PDT 24
Finished May 19 12:54:30 PM PDT 24
Peak memory 210972 kb
Host smart-23a8400d-64f1-4a8a-9916-893eb101d077
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3386767922 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_max_throughput_chk.3386767922
Directory /workspace/43.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/43.rom_ctrl_smoke.3565815813
Short name T258
Test name
Test status
Simulation time 2585602610 ps
CPU time 13.94 seconds
Started May 19 12:54:21 PM PDT 24
Finished May 19 12:54:38 PM PDT 24
Peak memory 219300 kb
Host smart-ca5facb8-1773-4c6c-a0fe-9eb1b19d3a31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3565815813 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_smoke.3565815813
Directory /workspace/43.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/43.rom_ctrl_stress_all.2535767944
Short name T350
Test name
Test status
Simulation time 9458705486 ps
CPU time 24.26 seconds
Started May 19 12:54:11 PM PDT 24
Finished May 19 12:54:40 PM PDT 24
Peak memory 212524 kb
Host smart-70e69371-0142-41d3-b05d-99ee36d9b71b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2535767944 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 43.rom_ctrl_stress_all.2535767944
Directory /workspace/43.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/44.rom_ctrl_alert_test.4231834595
Short name T63
Test name
Test status
Simulation time 2963185157 ps
CPU time 7.94 seconds
Started May 19 12:54:21 PM PDT 24
Finished May 19 12:54:32 PM PDT 24
Peak memory 211108 kb
Host smart-f99211d3-b295-4e8d-ad40-9059ae3236b5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4231834595 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_alert_test.4231834595
Directory /workspace/44.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/44.rom_ctrl_corrupt_sig_fatal_chk.1785363881
Short name T159
Test name
Test status
Simulation time 6755268386 ps
CPU time 93.49 seconds
Started May 19 12:54:13 PM PDT 24
Finished May 19 12:55:53 PM PDT 24
Peak memory 212468 kb
Host smart-17b392bb-b11c-47a1-a268-e252676dda76
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1785363881 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_
corrupt_sig_fatal_chk.1785363881
Directory /workspace/44.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/44.rom_ctrl_kmac_err_chk.1564867304
Short name T312
Test name
Test status
Simulation time 2614041733 ps
CPU time 13.74 seconds
Started May 19 12:54:05 PM PDT 24
Finished May 19 12:54:21 PM PDT 24
Peak memory 212208 kb
Host smart-c0dc2b7a-b306-4869-a4ed-fc233ebf4612
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1564867304 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_kmac_err_chk.1564867304
Directory /workspace/44.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/44.rom_ctrl_max_throughput_chk.3253121946
Short name T130
Test name
Test status
Simulation time 1606503204 ps
CPU time 14.94 seconds
Started May 19 12:54:14 PM PDT 24
Finished May 19 12:54:34 PM PDT 24
Peak memory 211028 kb
Host smart-5fa82c76-2522-4420-a086-d7e145f41045
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3253121946 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_max_throughput_chk.3253121946
Directory /workspace/44.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/44.rom_ctrl_smoke.4140464872
Short name T359
Test name
Test status
Simulation time 205762484 ps
CPU time 10.36 seconds
Started May 19 12:54:10 PM PDT 24
Finished May 19 12:54:25 PM PDT 24
Peak memory 213756 kb
Host smart-92b6d752-d9af-46f1-b52b-b3e0c529b57d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4140464872 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_smoke.4140464872
Directory /workspace/44.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/44.rom_ctrl_stress_all.4163312518
Short name T293
Test name
Test status
Simulation time 30534880607 ps
CPU time 68.35 seconds
Started May 19 12:54:06 PM PDT 24
Finished May 19 12:55:17 PM PDT 24
Peak memory 219344 kb
Host smart-dc18a528-b65d-4d3f-9efe-057b4764ef97
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4163312518 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 44.rom_ctrl_stress_all.4163312518
Directory /workspace/44.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/45.rom_ctrl_alert_test.2600817447
Short name T235
Test name
Test status
Simulation time 7431521221 ps
CPU time 13.66 seconds
Started May 19 12:54:08 PM PDT 24
Finished May 19 12:54:24 PM PDT 24
Peak memory 211308 kb
Host smart-c88ff529-2480-4606-929a-418ff49b59a3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2600817447 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_alert_test.2600817447
Directory /workspace/45.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/45.rom_ctrl_corrupt_sig_fatal_chk.2223261210
Short name T280
Test name
Test status
Simulation time 68340532364 ps
CPU time 212.71 seconds
Started May 19 12:54:04 PM PDT 24
Finished May 19 12:57:39 PM PDT 24
Peak memory 219520 kb
Host smart-2d2a78ec-eca6-4b5c-9e9a-b4d6ac7aa213
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2223261210 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_
corrupt_sig_fatal_chk.2223261210
Directory /workspace/45.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/45.rom_ctrl_kmac_err_chk.1951561347
Short name T23
Test name
Test status
Simulation time 170552009 ps
CPU time 9.5 seconds
Started May 19 12:54:10 PM PDT 24
Finished May 19 12:54:25 PM PDT 24
Peak memory 211176 kb
Host smart-9917451f-a87d-4e7c-a5c5-885307fea3d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1951561347 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_kmac_err_chk.1951561347
Directory /workspace/45.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/45.rom_ctrl_max_throughput_chk.1294830651
Short name T319
Test name
Test status
Simulation time 370211357 ps
CPU time 5.27 seconds
Started May 19 12:54:08 PM PDT 24
Finished May 19 12:54:15 PM PDT 24
Peak memory 210984 kb
Host smart-6679a426-0c37-4c60-b2a7-ad77c2f1e580
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1294830651 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_max_throughput_chk.1294830651
Directory /workspace/45.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/45.rom_ctrl_smoke.1831803822
Short name T184
Test name
Test status
Simulation time 17671492989 ps
CPU time 27.24 seconds
Started May 19 12:54:06 PM PDT 24
Finished May 19 12:54:36 PM PDT 24
Peak memory 219328 kb
Host smart-c2d5955c-9f23-43bd-bf62-c91e44b44954
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1831803822 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_smoke.1831803822
Directory /workspace/45.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/45.rom_ctrl_stress_all.2652187617
Short name T296
Test name
Test status
Simulation time 16198506191 ps
CPU time 82.05 seconds
Started May 19 12:54:10 PM PDT 24
Finished May 19 12:55:36 PM PDT 24
Peak memory 219400 kb
Host smart-69e879e9-00c7-4ddf-8901-52cd0f2bc3b6
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2652187617 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 45.rom_ctrl_stress_all.2652187617
Directory /workspace/45.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/46.rom_ctrl_alert_test.3083857299
Short name T209
Test name
Test status
Simulation time 168128820 ps
CPU time 4.41 seconds
Started May 19 12:54:12 PM PDT 24
Finished May 19 12:54:22 PM PDT 24
Peak memory 211412 kb
Host smart-14efd9d9-91b0-4d4e-bdb0-3da77b1bdd78
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3083857299 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_alert_test.3083857299
Directory /workspace/46.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/46.rom_ctrl_corrupt_sig_fatal_chk.1725963867
Short name T277
Test name
Test status
Simulation time 53994931479 ps
CPU time 280.99 seconds
Started May 19 12:54:18 PM PDT 24
Finished May 19 12:59:03 PM PDT 24
Peak memory 218872 kb
Host smart-30466e56-80b5-4235-ab39-3aa6c7310800
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1725963867 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_
corrupt_sig_fatal_chk.1725963867
Directory /workspace/46.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/46.rom_ctrl_kmac_err_chk.3074313207
Short name T98
Test name
Test status
Simulation time 340518465 ps
CPU time 9.46 seconds
Started May 19 12:54:10 PM PDT 24
Finished May 19 12:54:24 PM PDT 24
Peak memory 211772 kb
Host smart-e7f25845-7ff2-4668-8802-bf18af4aec34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3074313207 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_kmac_err_chk.3074313207
Directory /workspace/46.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/46.rom_ctrl_max_throughput_chk.3263284734
Short name T171
Test name
Test status
Simulation time 193856798 ps
CPU time 5.43 seconds
Started May 19 12:54:13 PM PDT 24
Finished May 19 12:54:24 PM PDT 24
Peak memory 211052 kb
Host smart-267e6169-7226-4ede-ab1f-22bc4b55d4d3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3263284734 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_max_throughput_chk.3263284734
Directory /workspace/46.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/46.rom_ctrl_smoke.2554266022
Short name T201
Test name
Test status
Simulation time 1291437650 ps
CPU time 19.29 seconds
Started May 19 12:54:13 PM PDT 24
Finished May 19 12:54:39 PM PDT 24
Peak memory 219212 kb
Host smart-f2a40b92-221c-48af-808b-1d88ddbf0375
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2554266022 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_smoke.2554266022
Directory /workspace/46.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/46.rom_ctrl_stress_all.3263660799
Short name T136
Test name
Test status
Simulation time 2589518892 ps
CPU time 29.78 seconds
Started May 19 12:54:04 PM PDT 24
Finished May 19 12:54:35 PM PDT 24
Peak memory 215560 kb
Host smart-e54069d0-ae08-4a14-9387-6a07b45860bf
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3263660799 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 46.rom_ctrl_stress_all.3263660799
Directory /workspace/46.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/47.rom_ctrl_alert_test.3147287979
Short name T337
Test name
Test status
Simulation time 1178367214 ps
CPU time 11.69 seconds
Started May 19 12:54:15 PM PDT 24
Finished May 19 12:54:32 PM PDT 24
Peak memory 211180 kb
Host smart-d9bfb58d-fb71-499a-85ef-7ebd83320f1f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3147287979 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_alert_test.3147287979
Directory /workspace/47.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/47.rom_ctrl_corrupt_sig_fatal_chk.3568093107
Short name T224
Test name
Test status
Simulation time 96534315595 ps
CPU time 232.03 seconds
Started May 19 12:54:15 PM PDT 24
Finished May 19 12:58:12 PM PDT 24
Peak memory 236588 kb
Host smart-ebe8c616-43ab-4255-9c6a-624663c3798c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3568093107 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_
corrupt_sig_fatal_chk.3568093107
Directory /workspace/47.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/47.rom_ctrl_kmac_err_chk.3710762442
Short name T174
Test name
Test status
Simulation time 8492348327 ps
CPU time 21.98 seconds
Started May 19 12:54:09 PM PDT 24
Finished May 19 12:54:35 PM PDT 24
Peak memory 213320 kb
Host smart-34e7da1c-c63e-4da2-aa55-58051807a8ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3710762442 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_kmac_err_chk.3710762442
Directory /workspace/47.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/47.rom_ctrl_max_throughput_chk.3064125659
Short name T303
Test name
Test status
Simulation time 1043320248 ps
CPU time 11.68 seconds
Started May 19 12:54:12 PM PDT 24
Finished May 19 12:54:29 PM PDT 24
Peak memory 211228 kb
Host smart-56c6c57c-fb1b-4105-a177-224447716e92
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3064125659 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_max_throughput_chk.3064125659
Directory /workspace/47.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/47.rom_ctrl_smoke.3445556557
Short name T241
Test name
Test status
Simulation time 6236473620 ps
CPU time 19.45 seconds
Started May 19 12:54:11 PM PDT 24
Finished May 19 12:54:35 PM PDT 24
Peak memory 214420 kb
Host smart-ae4be525-41a7-419b-aac6-4024f43fe943
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3445556557 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_smoke.3445556557
Directory /workspace/47.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/47.rom_ctrl_stress_all.2854920828
Short name T152
Test name
Test status
Simulation time 191116088 ps
CPU time 10.59 seconds
Started May 19 12:54:10 PM PDT 24
Finished May 19 12:54:25 PM PDT 24
Peak memory 214544 kb
Host smart-c6a488c5-1195-486c-9ad0-132d3d7ad010
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2854920828 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 47.rom_ctrl_stress_all.2854920828
Directory /workspace/47.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/48.rom_ctrl_alert_test.3048697114
Short name T284
Test name
Test status
Simulation time 8238412355 ps
CPU time 17.11 seconds
Started May 19 12:54:14 PM PDT 24
Finished May 19 12:54:37 PM PDT 24
Peak memory 211324 kb
Host smart-b1f67244-f22a-4dea-8ec9-f248c7a0cbcf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3048697114 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_alert_test.3048697114
Directory /workspace/48.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/48.rom_ctrl_corrupt_sig_fatal_chk.4120160871
Short name T148
Test name
Test status
Simulation time 9240200589 ps
CPU time 146.1 seconds
Started May 19 12:54:15 PM PDT 24
Finished May 19 12:56:46 PM PDT 24
Peak memory 236848 kb
Host smart-5ae5963e-e605-4e3b-9a0a-2c24e4b84008
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4120160871 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_
corrupt_sig_fatal_chk.4120160871
Directory /workspace/48.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/48.rom_ctrl_kmac_err_chk.3666000560
Short name T216
Test name
Test status
Simulation time 691618560 ps
CPU time 9.66 seconds
Started May 19 12:54:14 PM PDT 24
Finished May 19 12:54:29 PM PDT 24
Peak memory 211636 kb
Host smart-7b5e1c5a-9c5a-48bc-8f84-b1b7a36b5057
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3666000560 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_kmac_err_chk.3666000560
Directory /workspace/48.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/48.rom_ctrl_max_throughput_chk.2889995106
Short name T4
Test name
Test status
Simulation time 1323248953 ps
CPU time 9.12 seconds
Started May 19 12:54:10 PM PDT 24
Finished May 19 12:54:25 PM PDT 24
Peak memory 211280 kb
Host smart-0763572b-83c3-4d97-b8cc-9bae3028d9fb
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2889995106 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_max_throughput_chk.2889995106
Directory /workspace/48.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/48.rom_ctrl_smoke.840239065
Short name T261
Test name
Test status
Simulation time 375986744 ps
CPU time 10.35 seconds
Started May 19 12:54:17 PM PDT 24
Finished May 19 12:54:32 PM PDT 24
Peak memory 219184 kb
Host smart-b8c89113-9840-4585-9126-d79a2222ed81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=840239065 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_smoke.840239065
Directory /workspace/48.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/48.rom_ctrl_stress_all.1599415493
Short name T166
Test name
Test status
Simulation time 1597181398 ps
CPU time 21.39 seconds
Started May 19 12:54:16 PM PDT 24
Finished May 19 12:54:42 PM PDT 24
Peak memory 216108 kb
Host smart-8257c5ea-5dee-4673-8fb4-28fa06382915
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1599415493 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 48.rom_ctrl_stress_all.1599415493
Directory /workspace/48.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/49.rom_ctrl_alert_test.291200919
Short name T335
Test name
Test status
Simulation time 721213875 ps
CPU time 5.98 seconds
Started May 19 12:54:10 PM PDT 24
Finished May 19 12:54:22 PM PDT 24
Peak memory 211124 kb
Host smart-734c9c6c-1251-425b-b0b2-c4f75b14caea
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=291200919 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_alert_test.291200919
Directory /workspace/49.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/49.rom_ctrl_corrupt_sig_fatal_chk.3844498913
Short name T255
Test name
Test status
Simulation time 144159283070 ps
CPU time 365.39 seconds
Started May 19 12:54:10 PM PDT 24
Finished May 19 01:00:19 PM PDT 24
Peak memory 233788 kb
Host smart-d14d12ba-75b2-4ae6-91e5-97dd4a68b888
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3844498913 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_
corrupt_sig_fatal_chk.3844498913
Directory /workspace/49.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/49.rom_ctrl_kmac_err_chk.351381116
Short name T186
Test name
Test status
Simulation time 812574426 ps
CPU time 12.32 seconds
Started May 19 12:54:14 PM PDT 24
Finished May 19 12:54:32 PM PDT 24
Peak memory 211900 kb
Host smart-490066c6-3661-4af1-8b6c-3987d52af3f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=351381116 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_kmac_err_chk.351381116
Directory /workspace/49.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/49.rom_ctrl_max_throughput_chk.431628138
Short name T352
Test name
Test status
Simulation time 567162871 ps
CPU time 8.55 seconds
Started May 19 12:54:16 PM PDT 24
Finished May 19 12:54:29 PM PDT 24
Peak memory 210964 kb
Host smart-7309e738-7c6f-4ea9-9c56-7e0e94e298c0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=431628138 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_max_throughput_chk.431628138
Directory /workspace/49.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/49.rom_ctrl_smoke.2645836906
Short name T354
Test name
Test status
Simulation time 3218310421 ps
CPU time 28.66 seconds
Started May 19 12:54:18 PM PDT 24
Finished May 19 12:54:51 PM PDT 24
Peak memory 213108 kb
Host smart-ae962c41-bb4a-460d-b9bf-3460bbf20855
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2645836906 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_smoke.2645836906
Directory /workspace/49.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/49.rom_ctrl_stress_all.420225720
Short name T323
Test name
Test status
Simulation time 32488226145 ps
CPU time 35.34 seconds
Started May 19 12:54:10 PM PDT 24
Finished May 19 12:54:51 PM PDT 24
Peak memory 219276 kb
Host smart-2fdc8fb0-978d-4cd9-9e61-cb31246b76c3
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=420225720 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 49.rom_ctrl_stress_all.420225720
Directory /workspace/49.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/5.rom_ctrl_alert_test.1220892831
Short name T231
Test name
Test status
Simulation time 187002141 ps
CPU time 4.33 seconds
Started May 19 12:53:31 PM PDT 24
Finished May 19 12:53:36 PM PDT 24
Peak memory 211120 kb
Host smart-1eb0b371-a772-4e3d-8f38-06b30819cf78
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1220892831 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_alert_test.1220892831
Directory /workspace/5.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/5.rom_ctrl_corrupt_sig_fatal_chk.4178047507
Short name T142
Test name
Test status
Simulation time 146951092426 ps
CPU time 392.34 seconds
Started May 19 12:53:33 PM PDT 24
Finished May 19 01:00:06 PM PDT 24
Peak memory 229684 kb
Host smart-2b32fb13-3cdf-4f98-98d7-8465e1e7ceab
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4178047507 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_c
orrupt_sig_fatal_chk.4178047507
Directory /workspace/5.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/5.rom_ctrl_kmac_err_chk.2401289071
Short name T190
Test name
Test status
Simulation time 171909453 ps
CPU time 9.37 seconds
Started May 19 12:53:31 PM PDT 24
Finished May 19 12:53:41 PM PDT 24
Peak memory 211776 kb
Host smart-2bd3293e-80fa-4e15-98ac-167999b7c027
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2401289071 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_kmac_err_chk.2401289071
Directory /workspace/5.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/5.rom_ctrl_max_throughput_chk.200467784
Short name T343
Test name
Test status
Simulation time 9315527734 ps
CPU time 17.6 seconds
Started May 19 12:53:28 PM PDT 24
Finished May 19 12:53:47 PM PDT 24
Peak memory 211352 kb
Host smart-c3b1ff6b-e39b-4f94-a58b-e3e69f3a76c9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=200467784 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_max_throughput_chk.200467784
Directory /workspace/5.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/5.rom_ctrl_stress_all.3522428061
Short name T360
Test name
Test status
Simulation time 5664528603 ps
CPU time 55.91 seconds
Started May 19 12:53:35 PM PDT 24
Finished May 19 12:54:32 PM PDT 24
Peak memory 216524 kb
Host smart-db185415-7f85-41a1-ae9e-400838fd4433
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3522428061 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 5.rom_ctrl_stress_all.3522428061
Directory /workspace/5.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/6.rom_ctrl_alert_test.3901171524
Short name T327
Test name
Test status
Simulation time 371518151 ps
CPU time 7.08 seconds
Started May 19 12:53:50 PM PDT 24
Finished May 19 12:53:59 PM PDT 24
Peak memory 211080 kb
Host smart-c0b0b7bf-6a36-4043-918e-f026c8c8f1d1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3901171524 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_alert_test.3901171524
Directory /workspace/6.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/6.rom_ctrl_corrupt_sig_fatal_chk.2679296914
Short name T325
Test name
Test status
Simulation time 3982640521 ps
CPU time 66.57 seconds
Started May 19 12:53:55 PM PDT 24
Finished May 19 12:55:05 PM PDT 24
Peak memory 230792 kb
Host smart-6f2059be-461e-4419-a0a1-d5943019390c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2679296914 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_c
orrupt_sig_fatal_chk.2679296914
Directory /workspace/6.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/6.rom_ctrl_kmac_err_chk.3313215757
Short name T349
Test name
Test status
Simulation time 15359112478 ps
CPU time 32.37 seconds
Started May 19 12:53:35 PM PDT 24
Finished May 19 12:54:08 PM PDT 24
Peak memory 212132 kb
Host smart-5e3154b2-7c44-4864-aaab-b70c52728167
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3313215757 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_kmac_err_chk.3313215757
Directory /workspace/6.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/6.rom_ctrl_max_throughput_chk.3951494986
Short name T5
Test name
Test status
Simulation time 7746197493 ps
CPU time 16.99 seconds
Started May 19 12:53:30 PM PDT 24
Finished May 19 12:53:48 PM PDT 24
Peak memory 211052 kb
Host smart-76103fda-5384-4506-8f7e-9997db8f1688
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3951494986 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_max_throughput_chk.3951494986
Directory /workspace/6.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/6.rom_ctrl_smoke.2185639733
Short name T195
Test name
Test status
Simulation time 1898934144 ps
CPU time 22.05 seconds
Started May 19 12:53:36 PM PDT 24
Finished May 19 12:53:59 PM PDT 24
Peak memory 212292 kb
Host smart-5a181ea9-78b1-4536-821f-9882d4d9d3ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2185639733 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_smoke.2185639733
Directory /workspace/6.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/6.rom_ctrl_stress_all.4035167358
Short name T140
Test name
Test status
Simulation time 13660679988 ps
CPU time 36.96 seconds
Started May 19 12:53:47 PM PDT 24
Finished May 19 12:54:26 PM PDT 24
Peak memory 219360 kb
Host smart-5e6e0287-9899-4cc8-9eb7-0f932672073f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4035167358 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 6.rom_ctrl_stress_all.4035167358
Directory /workspace/6.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/7.rom_ctrl_alert_test.1606538588
Short name T265
Test name
Test status
Simulation time 2053967410 ps
CPU time 15.83 seconds
Started May 19 12:53:34 PM PDT 24
Finished May 19 12:53:51 PM PDT 24
Peak memory 211060 kb
Host smart-65d2bb15-9dcb-4390-aa88-3224dd55f7bf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1606538588 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_alert_test.1606538588
Directory /workspace/7.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/7.rom_ctrl_corrupt_sig_fatal_chk.3881557776
Short name T20
Test name
Test status
Simulation time 18289139721 ps
CPU time 211.02 seconds
Started May 19 12:53:42 PM PDT 24
Finished May 19 12:57:15 PM PDT 24
Peak memory 212364 kb
Host smart-f5bfcfdf-af74-432b-8e55-a95fc75d6646
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3881557776 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_c
orrupt_sig_fatal_chk.3881557776
Directory /workspace/7.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/7.rom_ctrl_kmac_err_chk.1017555341
Short name T21
Test name
Test status
Simulation time 722250052 ps
CPU time 9.31 seconds
Started May 19 12:53:38 PM PDT 24
Finished May 19 12:53:48 PM PDT 24
Peak memory 211744 kb
Host smart-9c04c4a9-2f69-4009-8960-d9cda21b86a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1017555341 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_kmac_err_chk.1017555341
Directory /workspace/7.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/7.rom_ctrl_max_throughput_chk.4056559162
Short name T251
Test name
Test status
Simulation time 2451013802 ps
CPU time 9.49 seconds
Started May 19 12:53:41 PM PDT 24
Finished May 19 12:53:53 PM PDT 24
Peak memory 211020 kb
Host smart-ad341d05-c7fc-4212-8485-264050438941
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4056559162 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_max_throughput_chk.4056559162
Directory /workspace/7.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/7.rom_ctrl_smoke.1317265695
Short name T291
Test name
Test status
Simulation time 13455766095 ps
CPU time 29.04 seconds
Started May 19 12:53:45 PM PDT 24
Finished May 19 12:54:15 PM PDT 24
Peak memory 219380 kb
Host smart-51db1e27-62c3-4370-9d94-208682fda4b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1317265695 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_smoke.1317265695
Directory /workspace/7.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/7.rom_ctrl_stress_all.2374063190
Short name T324
Test name
Test status
Simulation time 7689543972 ps
CPU time 18.96 seconds
Started May 19 12:53:43 PM PDT 24
Finished May 19 12:54:04 PM PDT 24
Peak memory 212204 kb
Host smart-99f49186-588e-4928-9b82-b20fd1fd4541
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2374063190 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 7.rom_ctrl_stress_all.2374063190
Directory /workspace/7.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/8.rom_ctrl_alert_test.4239479773
Short name T353
Test name
Test status
Simulation time 23681811100 ps
CPU time 11.17 seconds
Started May 19 12:53:37 PM PDT 24
Finished May 19 12:53:49 PM PDT 24
Peak memory 211292 kb
Host smart-3834486a-b0c1-4d71-b940-caa421dfeaf0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4239479773 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_alert_test.4239479773
Directory /workspace/8.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/8.rom_ctrl_corrupt_sig_fatal_chk.1822700232
Short name T283
Test name
Test status
Simulation time 7836276686 ps
CPU time 97.61 seconds
Started May 19 12:53:54 PM PDT 24
Finished May 19 12:55:35 PM PDT 24
Peak memory 228640 kb
Host smart-32280cd3-c8b5-44df-985d-f4462dcfc9be
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1822700232 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_c
orrupt_sig_fatal_chk.1822700232
Directory /workspace/8.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/8.rom_ctrl_kmac_err_chk.2698060595
Short name T298
Test name
Test status
Simulation time 11676585089 ps
CPU time 24.83 seconds
Started May 19 12:53:51 PM PDT 24
Finished May 19 12:54:18 PM PDT 24
Peak memory 212264 kb
Host smart-b18855ec-5387-4b26-8ffe-d17959162a2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2698060595 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_kmac_err_chk.2698060595
Directory /workspace/8.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/8.rom_ctrl_max_throughput_chk.4259996645
Short name T240
Test name
Test status
Simulation time 1989776071 ps
CPU time 11.27 seconds
Started May 19 12:53:40 PM PDT 24
Finished May 19 12:53:53 PM PDT 24
Peak memory 210948 kb
Host smart-bc608d4d-3aa3-4af2-b717-88bb27f5abff
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4259996645 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_max_throughput_chk.4259996645
Directory /workspace/8.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/8.rom_ctrl_smoke.3348346206
Short name T79
Test name
Test status
Simulation time 4483692051 ps
CPU time 26.13 seconds
Started May 19 12:53:42 PM PDT 24
Finished May 19 12:54:10 PM PDT 24
Peak memory 213152 kb
Host smart-3bfd8847-d468-4053-b919-f22af9e84164
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3348346206 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_smoke.3348346206
Directory /workspace/8.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/8.rom_ctrl_stress_all.522068488
Short name T328
Test name
Test status
Simulation time 778460519 ps
CPU time 21.3 seconds
Started May 19 12:53:46 PM PDT 24
Finished May 19 12:54:09 PM PDT 24
Peak memory 219264 kb
Host smart-1a4d7128-5767-46f0-b070-70afae396b74
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=522068488 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 8.rom_ctrl_stress_all.522068488
Directory /workspace/8.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/9.rom_ctrl_alert_test.3285401827
Short name T194
Test name
Test status
Simulation time 1995612568 ps
CPU time 15.1 seconds
Started May 19 12:53:40 PM PDT 24
Finished May 19 12:53:57 PM PDT 24
Peak memory 211216 kb
Host smart-15432918-9951-4e86-acf1-c1569a7e096f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3285401827 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_alert_test.3285401827
Directory /workspace/9.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/9.rom_ctrl_corrupt_sig_fatal_chk.1215168982
Short name T211
Test name
Test status
Simulation time 20451316625 ps
CPU time 238.2 seconds
Started May 19 12:53:49 PM PDT 24
Finished May 19 12:57:49 PM PDT 24
Peak memory 231820 kb
Host smart-f0be277d-e43f-477f-93ca-33de5aa60244
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1215168982 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_c
orrupt_sig_fatal_chk.1215168982
Directory /workspace/9.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/9.rom_ctrl_kmac_err_chk.1333882575
Short name T132
Test name
Test status
Simulation time 32699424565 ps
CPU time 28.65 seconds
Started May 19 12:53:50 PM PDT 24
Finished May 19 12:54:21 PM PDT 24
Peak memory 212400 kb
Host smart-48d7759a-dfda-4cd4-8b09-cb29c762c806
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1333882575 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_kmac_err_chk.1333882575
Directory /workspace/9.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/9.rom_ctrl_max_throughput_chk.3354016489
Short name T357
Test name
Test status
Simulation time 16436476532 ps
CPU time 10.54 seconds
Started May 19 12:53:45 PM PDT 24
Finished May 19 12:53:57 PM PDT 24
Peak memory 211124 kb
Host smart-bb2b8d21-14ab-4b7c-b713-978af97d2951
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3354016489 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_max_throughput_chk.3354016489
Directory /workspace/9.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/9.rom_ctrl_smoke.4000870923
Short name T164
Test name
Test status
Simulation time 28304819197 ps
CPU time 24.82 seconds
Started May 19 12:53:39 PM PDT 24
Finished May 19 12:54:05 PM PDT 24
Peak memory 219304 kb
Host smart-49b0afea-dc23-4051-96d1-013f79905fb7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4000870923 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_smoke.4000870923
Directory /workspace/9.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/9.rom_ctrl_stress_all.1936045608
Short name T279
Test name
Test status
Simulation time 41048631531 ps
CPU time 106 seconds
Started May 19 12:53:47 PM PDT 24
Finished May 19 12:55:35 PM PDT 24
Peak memory 219428 kb
Host smart-4c44dbc0-becd-4c42-94d0-473aab061a03
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1936045608 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 9.rom_ctrl_stress_all.1936045608
Directory /workspace/9.rom_ctrl_stress_all/latest
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