Tests
dashboard | hierarchy | modlist | groups | tests | asserts
Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
97.58 96.97 92.87 97.88 100.00 98.37 97.88 99.07


Total test records in report: 462
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html
T297 /workspace/coverage/default/17.rom_ctrl_stress_all.3338409100 May 23 01:42:42 PM PDT 24 May 23 01:43:04 PM PDT 24 1517492348 ps
T298 /workspace/coverage/default/33.rom_ctrl_corrupt_sig_fatal_chk.676273661 May 23 01:43:14 PM PDT 24 May 23 01:46:34 PM PDT 24 98922371400 ps
T299 /workspace/coverage/default/28.rom_ctrl_stress_all_with_rand_reset.1468064567 May 23 01:43:14 PM PDT 24 May 23 02:00:49 PM PDT 24 102727162170 ps
T300 /workspace/coverage/default/46.rom_ctrl_stress_all.932037906 May 23 01:43:29 PM PDT 24 May 23 01:44:29 PM PDT 24 6976688665 ps
T301 /workspace/coverage/default/25.rom_ctrl_max_throughput_chk.881239043 May 23 01:42:56 PM PDT 24 May 23 01:43:11 PM PDT 24 2381526714 ps
T302 /workspace/coverage/default/35.rom_ctrl_max_throughput_chk.1806040387 May 23 01:43:14 PM PDT 24 May 23 01:43:36 PM PDT 24 2060087089 ps
T303 /workspace/coverage/default/10.rom_ctrl_alert_test.3608090913 May 23 01:42:29 PM PDT 24 May 23 01:42:35 PM PDT 24 347353978 ps
T304 /workspace/coverage/default/18.rom_ctrl_stress_all.1839703942 May 23 01:42:41 PM PDT 24 May 23 01:42:50 PM PDT 24 2258850372 ps
T305 /workspace/coverage/default/14.rom_ctrl_max_throughput_chk.1029783382 May 23 01:42:42 PM PDT 24 May 23 01:42:49 PM PDT 24 99096991 ps
T306 /workspace/coverage/default/27.rom_ctrl_kmac_err_chk.4284792407 May 23 01:42:57 PM PDT 24 May 23 01:43:20 PM PDT 24 1930927192 ps
T307 /workspace/coverage/default/32.rom_ctrl_corrupt_sig_fatal_chk.1544342468 May 23 01:43:15 PM PDT 24 May 23 01:47:22 PM PDT 24 22547584689 ps
T308 /workspace/coverage/default/6.rom_ctrl_kmac_err_chk.119121253 May 23 01:42:23 PM PDT 24 May 23 01:43:00 PM PDT 24 17815584108 ps
T309 /workspace/coverage/default/4.rom_ctrl_corrupt_sig_fatal_chk.1334486490 May 23 01:42:23 PM PDT 24 May 23 01:47:49 PM PDT 24 129135123566 ps
T310 /workspace/coverage/default/4.rom_ctrl_smoke.3224832440 May 23 01:42:23 PM PDT 24 May 23 01:42:52 PM PDT 24 4655527083 ps
T311 /workspace/coverage/default/29.rom_ctrl_smoke.1793192662 May 23 01:43:16 PM PDT 24 May 23 01:43:50 PM PDT 24 14652195102 ps
T312 /workspace/coverage/default/35.rom_ctrl_kmac_err_chk.1195997564 May 23 01:43:17 PM PDT 24 May 23 01:43:31 PM PDT 24 692570606 ps
T313 /workspace/coverage/default/0.rom_ctrl_stress_all.2653127382 May 23 01:42:15 PM PDT 24 May 23 01:42:41 PM PDT 24 6399747753 ps
T314 /workspace/coverage/default/3.rom_ctrl_max_throughput_chk.1947234522 May 23 01:42:22 PM PDT 24 May 23 01:42:32 PM PDT 24 3125922028 ps
T315 /workspace/coverage/default/29.rom_ctrl_corrupt_sig_fatal_chk.3098983142 May 23 01:43:17 PM PDT 24 May 23 01:46:43 PM PDT 24 161461696987 ps
T316 /workspace/coverage/default/29.rom_ctrl_kmac_err_chk.2266223804 May 23 01:43:15 PM PDT 24 May 23 01:43:48 PM PDT 24 12506578537 ps
T317 /workspace/coverage/default/23.rom_ctrl_max_throughput_chk.2705107534 May 23 01:42:58 PM PDT 24 May 23 01:43:06 PM PDT 24 379674693 ps
T318 /workspace/coverage/default/20.rom_ctrl_kmac_err_chk.2312154107 May 23 01:42:54 PM PDT 24 May 23 01:43:09 PM PDT 24 2048901188 ps
T319 /workspace/coverage/default/8.rom_ctrl_stress_all.4162117027 May 23 01:42:36 PM PDT 24 May 23 01:42:58 PM PDT 24 1542742913 ps
T320 /workspace/coverage/default/36.rom_ctrl_corrupt_sig_fatal_chk.1781208180 May 23 01:43:12 PM PDT 24 May 23 01:47:27 PM PDT 24 28424906767 ps
T321 /workspace/coverage/default/30.rom_ctrl_corrupt_sig_fatal_chk.2269900792 May 23 01:43:15 PM PDT 24 May 23 01:45:43 PM PDT 24 44196856496 ps
T322 /workspace/coverage/default/44.rom_ctrl_max_throughput_chk.4249412802 May 23 01:43:23 PM PDT 24 May 23 01:43:36 PM PDT 24 3952597460 ps
T323 /workspace/coverage/default/20.rom_ctrl_stress_all.3087032285 May 23 01:42:55 PM PDT 24 May 23 01:44:28 PM PDT 24 31189643624 ps
T324 /workspace/coverage/default/23.rom_ctrl_stress_all.1254721682 May 23 01:42:54 PM PDT 24 May 23 01:43:27 PM PDT 24 6616045981 ps
T325 /workspace/coverage/default/20.rom_ctrl_corrupt_sig_fatal_chk.2754167379 May 23 01:42:53 PM PDT 24 May 23 01:47:03 PM PDT 24 82510233916 ps
T326 /workspace/coverage/default/32.rom_ctrl_max_throughput_chk.3730645247 May 23 01:43:16 PM PDT 24 May 23 01:43:26 PM PDT 24 97574196 ps
T327 /workspace/coverage/default/18.rom_ctrl_max_throughput_chk.3557067518 May 23 01:42:38 PM PDT 24 May 23 01:42:45 PM PDT 24 193392629 ps
T328 /workspace/coverage/default/26.rom_ctrl_kmac_err_chk.3067407100 May 23 01:42:58 PM PDT 24 May 23 01:43:31 PM PDT 24 13726523353 ps
T329 /workspace/coverage/default/27.rom_ctrl_alert_test.940810240 May 23 01:42:58 PM PDT 24 May 23 01:43:05 PM PDT 24 88150543 ps
T330 /workspace/coverage/default/17.rom_ctrl_max_throughput_chk.3391919450 May 23 01:42:39 PM PDT 24 May 23 01:42:55 PM PDT 24 6929890477 ps
T331 /workspace/coverage/default/13.rom_ctrl_max_throughput_chk.3758171757 May 23 01:42:39 PM PDT 24 May 23 01:42:46 PM PDT 24 189916283 ps
T332 /workspace/coverage/default/24.rom_ctrl_stress_all.3285975586 May 23 01:42:56 PM PDT 24 May 23 01:43:26 PM PDT 24 404756750 ps
T333 /workspace/coverage/default/13.rom_ctrl_corrupt_sig_fatal_chk.1447919137 May 23 01:42:40 PM PDT 24 May 23 01:46:20 PM PDT 24 46158091902 ps
T334 /workspace/coverage/default/13.rom_ctrl_stress_all.1038606431 May 23 01:42:38 PM PDT 24 May 23 01:43:40 PM PDT 24 35118849354 ps
T335 /workspace/coverage/default/14.rom_ctrl_corrupt_sig_fatal_chk.3370357203 May 23 01:42:40 PM PDT 24 May 23 01:47:27 PM PDT 24 27515221289 ps
T336 /workspace/coverage/default/2.rom_ctrl_max_throughput_chk.2692652403 May 23 01:42:14 PM PDT 24 May 23 01:42:29 PM PDT 24 3769760296 ps
T337 /workspace/coverage/default/23.rom_ctrl_alert_test.2633124345 May 23 01:42:57 PM PDT 24 May 23 01:43:11 PM PDT 24 2615890627 ps
T338 /workspace/coverage/default/19.rom_ctrl_max_throughput_chk.294174883 May 23 01:42:55 PM PDT 24 May 23 01:43:06 PM PDT 24 2511679696 ps
T339 /workspace/coverage/default/41.rom_ctrl_stress_all.710078194 May 23 01:43:20 PM PDT 24 May 23 01:44:39 PM PDT 24 32477609313 ps
T340 /workspace/coverage/default/39.rom_ctrl_smoke.3874111786 May 23 01:43:21 PM PDT 24 May 23 01:43:34 PM PDT 24 184895097 ps
T341 /workspace/coverage/default/45.rom_ctrl_smoke.2288227752 May 23 01:43:26 PM PDT 24 May 23 01:43:55 PM PDT 24 11225063643 ps
T342 /workspace/coverage/default/45.rom_ctrl_alert_test.124162703 May 23 01:43:32 PM PDT 24 May 23 01:43:44 PM PDT 24 2138695726 ps
T343 /workspace/coverage/default/38.rom_ctrl_max_throughput_chk.2767476628 May 23 01:43:20 PM PDT 24 May 23 01:43:32 PM PDT 24 500953832 ps
T344 /workspace/coverage/default/48.rom_ctrl_smoke.3553886721 May 23 01:43:29 PM PDT 24 May 23 01:43:46 PM PDT 24 7270997298 ps
T345 /workspace/coverage/default/7.rom_ctrl_stress_all.82119925 May 23 01:42:25 PM PDT 24 May 23 01:43:11 PM PDT 24 4802141044 ps
T346 /workspace/coverage/default/26.rom_ctrl_max_throughput_chk.3481922205 May 23 01:43:00 PM PDT 24 May 23 01:43:20 PM PDT 24 8504017488 ps
T347 /workspace/coverage/default/0.rom_ctrl_kmac_err_chk.1385758507 May 23 01:42:17 PM PDT 24 May 23 01:42:29 PM PDT 24 177218968 ps
T348 /workspace/coverage/default/25.rom_ctrl_stress_all_with_rand_reset.3825985760 May 23 01:42:55 PM PDT 24 May 23 01:53:43 PM PDT 24 34279086307 ps
T349 /workspace/coverage/default/12.rom_ctrl_smoke.78966923 May 23 01:42:39 PM PDT 24 May 23 01:42:50 PM PDT 24 717648081 ps
T350 /workspace/coverage/default/44.rom_ctrl_kmac_err_chk.886665052 May 23 01:43:34 PM PDT 24 May 23 01:43:55 PM PDT 24 2640225888 ps
T351 /workspace/coverage/default/34.rom_ctrl_alert_test.1636834397 May 23 01:43:17 PM PDT 24 May 23 01:43:38 PM PDT 24 2118213092 ps
T352 /workspace/coverage/default/42.rom_ctrl_smoke.3950177872 May 23 01:43:35 PM PDT 24 May 23 01:43:46 PM PDT 24 185254161 ps
T353 /workspace/coverage/default/32.rom_ctrl_stress_all.3338800790 May 23 01:43:18 PM PDT 24 May 23 01:43:58 PM PDT 24 4916417119 ps
T354 /workspace/coverage/default/44.rom_ctrl_corrupt_sig_fatal_chk.2835772936 May 23 01:43:27 PM PDT 24 May 23 01:46:31 PM PDT 24 21666955262 ps
T355 /workspace/coverage/default/38.rom_ctrl_kmac_err_chk.1953064180 May 23 01:43:20 PM PDT 24 May 23 01:43:33 PM PDT 24 169197308 ps
T356 /workspace/coverage/default/37.rom_ctrl_smoke.1527205148 May 23 01:43:14 PM PDT 24 May 23 01:43:44 PM PDT 24 2652849859 ps
T357 /workspace/coverage/default/25.rom_ctrl_alert_test.62607412 May 23 01:42:55 PM PDT 24 May 23 01:43:08 PM PDT 24 4378873149 ps
T358 /workspace/coverage/default/2.rom_ctrl_alert_test.3607708647 May 23 01:42:24 PM PDT 24 May 23 01:42:36 PM PDT 24 3774250666 ps
T359 /workspace/coverage/default/3.rom_ctrl_kmac_err_chk.4137465970 May 23 01:42:22 PM PDT 24 May 23 01:42:46 PM PDT 24 2377483765 ps
T360 /workspace/coverage/default/46.rom_ctrl_alert_test.3432554517 May 23 01:43:22 PM PDT 24 May 23 01:43:37 PM PDT 24 2756208852 ps
T361 /workspace/coverage/default/34.rom_ctrl_max_throughput_chk.3298212731 May 23 01:43:14 PM PDT 24 May 23 01:43:34 PM PDT 24 10113765185 ps
T362 /workspace/coverage/default/15.rom_ctrl_alert_test.2748422560 May 23 01:42:41 PM PDT 24 May 23 01:42:50 PM PDT 24 579455637 ps
T363 /workspace/coverage/default/35.rom_ctrl_stress_all.3608567210 May 23 01:43:12 PM PDT 24 May 23 01:44:02 PM PDT 24 13169259828 ps
T102 /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_errors.1330480061 May 23 01:42:02 PM PDT 24 May 23 01:42:16 PM PDT 24 786563535 ps
T62 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_rw.1185838269 May 23 01:41:57 PM PDT 24 May 23 01:42:09 PM PDT 24 3673499131 ps
T63 /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_rw.4107408770 May 23 01:42:14 PM PDT 24 May 23 01:42:28 PM PDT 24 1060741609 ps
T64 /workspace/coverage/cover_reg_top/2.rom_ctrl_passthru_mem_tl_intg_err.2729390446 May 23 01:42:00 PM PDT 24 May 23 01:42:59 PM PDT 24 6270265563 ps
T59 /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_intg_err.3771856377 May 23 01:42:11 PM PDT 24 May 23 01:42:52 PM PDT 24 330787202 ps
T364 /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_walk.3569610758 May 23 01:42:02 PM PDT 24 May 23 01:42:15 PM PDT 24 3823856817 ps
T365 /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_errors.3385533453 May 23 01:42:01 PM PDT 24 May 23 01:42:20 PM PDT 24 2042668760 ps
T366 /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_errors.3910102545 May 23 01:42:11 PM PDT 24 May 23 01:42:26 PM PDT 24 642802171 ps
T367 /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_errors.1029386115 May 23 01:42:00 PM PDT 24 May 23 01:42:15 PM PDT 24 165987223 ps
T98 /workspace/coverage/cover_reg_top/11.rom_ctrl_passthru_mem_tl_intg_err.595009076 May 23 01:42:13 PM PDT 24 May 23 01:42:44 PM PDT 24 2248485027 ps
T368 /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_mem_rw_with_rand_reset.496071585 May 23 01:42:00 PM PDT 24 May 23 01:42:16 PM PDT 24 2770584357 ps
T68 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_aliasing.1321425354 May 23 01:42:00 PM PDT 24 May 23 01:42:16 PM PDT 24 3321955651 ps
T369 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_mem_rw_with_rand_reset.298554670 May 23 01:41:59 PM PDT 24 May 23 01:42:11 PM PDT 24 1554060200 ps
T60 /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_intg_err.3745323797 May 23 01:42:05 PM PDT 24 May 23 01:42:50 PM PDT 24 1050594703 ps
T370 /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_rw.2952998822 May 23 01:42:11 PM PDT 24 May 23 01:42:20 PM PDT 24 611975117 ps
T69 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_hw_reset.1611171975 May 23 01:42:05 PM PDT 24 May 23 01:42:26 PM PDT 24 3376245433 ps
T70 /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_rw.2576454510 May 23 01:42:00 PM PDT 24 May 23 01:42:17 PM PDT 24 5354082383 ps
T71 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_hw_reset.1553142420 May 23 01:42:00 PM PDT 24 May 23 01:42:21 PM PDT 24 1555101733 ps
T93 /workspace/coverage/cover_reg_top/14.rom_ctrl_same_csr_outstanding.3816553060 May 23 01:42:17 PM PDT 24 May 23 01:42:24 PM PDT 24 333990683 ps
T61 /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_intg_err.2937991454 May 23 01:42:16 PM PDT 24 May 23 01:43:32 PM PDT 24 1386537724 ps
T371 /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_partial_access.2911624895 May 23 01:41:58 PM PDT 24 May 23 01:42:08 PM PDT 24 1130729576 ps
T72 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_rw.2083343800 May 23 01:42:02 PM PDT 24 May 23 01:42:12 PM PDT 24 255638437 ps
T73 /workspace/coverage/cover_reg_top/3.rom_ctrl_same_csr_outstanding.2965683284 May 23 01:42:05 PM PDT 24 May 23 01:42:23 PM PDT 24 1613476461 ps
T372 /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_errors.1148360892 May 23 01:42:10 PM PDT 24 May 23 01:42:22 PM PDT 24 703275828 ps
T103 /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_intg_err.1643915317 May 23 01:42:21 PM PDT 24 May 23 01:43:00 PM PDT 24 463798557 ps
T74 /workspace/coverage/cover_reg_top/5.rom_ctrl_same_csr_outstanding.3604988490 May 23 01:41:59 PM PDT 24 May 23 01:42:10 PM PDT 24 363395727 ps
T75 /workspace/coverage/cover_reg_top/8.rom_ctrl_same_csr_outstanding.526762027 May 23 01:42:05 PM PDT 24 May 23 01:42:25 PM PDT 24 8077569984 ps
T373 /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_walk.3007914819 May 23 01:42:00 PM PDT 24 May 23 01:42:13 PM PDT 24 2916018172 ps
T374 /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_errors.924142076 May 23 01:42:16 PM PDT 24 May 23 01:42:32 PM PDT 24 1794513639 ps
T375 /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_partial_access.289059364 May 23 01:42:02 PM PDT 24 May 23 01:42:20 PM PDT 24 6644624155 ps
T376 /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_errors.3808772421 May 23 01:42:02 PM PDT 24 May 23 01:42:20 PM PDT 24 1805715836 ps
T377 /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_rw.1913268056 May 23 01:42:11 PM PDT 24 May 23 01:42:25 PM PDT 24 1038957949 ps
T107 /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_intg_err.766974961 May 23 01:42:00 PM PDT 24 May 23 01:42:40 PM PDT 24 310186606 ps
T378 /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_errors.1803529404 May 23 01:42:03 PM PDT 24 May 23 01:42:26 PM PDT 24 2470885435 ps
T379 /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_mem_rw_with_rand_reset.1206374760 May 23 01:42:13 PM PDT 24 May 23 01:42:28 PM PDT 24 1393848075 ps
T76 /workspace/coverage/cover_reg_top/4.rom_ctrl_passthru_mem_tl_intg_err.927926810 May 23 01:41:59 PM PDT 24 May 23 01:43:04 PM PDT 24 94857157708 ps
T380 /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_rw.3972325209 May 23 01:42:12 PM PDT 24 May 23 01:42:32 PM PDT 24 5901832468 ps
T100 /workspace/coverage/cover_reg_top/17.rom_ctrl_passthru_mem_tl_intg_err.1528331168 May 23 01:42:16 PM PDT 24 May 23 01:43:17 PM PDT 24 4872467469 ps
T381 /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_mem_rw_with_rand_reset.2345533731 May 23 01:42:11 PM PDT 24 May 23 01:42:28 PM PDT 24 2991184932 ps
T111 /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_intg_err.166364281 May 23 01:41:59 PM PDT 24 May 23 01:43:15 PM PDT 24 1713350015 ps
T94 /workspace/coverage/cover_reg_top/16.rom_ctrl_same_csr_outstanding.2566809015 May 23 01:42:10 PM PDT 24 May 23 01:42:28 PM PDT 24 6919181471 ps
T95 /workspace/coverage/cover_reg_top/15.rom_ctrl_same_csr_outstanding.1620846141 May 23 01:42:17 PM PDT 24 May 23 01:42:34 PM PDT 24 7478261140 ps
T382 /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_errors.1732493196 May 23 01:42:14 PM PDT 24 May 23 01:42:34 PM PDT 24 1279181757 ps
T383 /workspace/coverage/cover_reg_top/7.rom_ctrl_passthru_mem_tl_intg_err.2792878367 May 23 01:42:04 PM PDT 24 May 23 01:42:53 PM PDT 24 4224467324 ps
T96 /workspace/coverage/cover_reg_top/19.rom_ctrl_same_csr_outstanding.220244548 May 23 01:42:14 PM PDT 24 May 23 01:42:22 PM PDT 24 89138193 ps
T384 /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_mem_rw_with_rand_reset.3039684351 May 23 01:42:16 PM PDT 24 May 23 01:42:26 PM PDT 24 588441595 ps
T82 /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_rw.1006412833 May 23 01:42:13 PM PDT 24 May 23 01:42:29 PM PDT 24 4457693859 ps
T385 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_rw.3673174099 May 23 01:42:06 PM PDT 24 May 23 01:42:25 PM PDT 24 8578558280 ps
T386 /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_mem_rw_with_rand_reset.2111598271 May 23 01:42:11 PM PDT 24 May 23 01:42:31 PM PDT 24 7478999784 ps
T387 /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_mem_rw_with_rand_reset.2621231693 May 23 01:42:00 PM PDT 24 May 23 01:42:10 PM PDT 24 95020935 ps
T97 /workspace/coverage/cover_reg_top/11.rom_ctrl_same_csr_outstanding.3154422761 May 23 01:42:11 PM PDT 24 May 23 01:42:21 PM PDT 24 341965250 ps
T388 /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_mem_rw_with_rand_reset.3366749338 May 23 01:42:01 PM PDT 24 May 23 01:42:15 PM PDT 24 3476289853 ps
T389 /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_rw.4148541161 May 23 01:42:10 PM PDT 24 May 23 01:42:28 PM PDT 24 1684922607 ps
T390 /workspace/coverage/cover_reg_top/8.rom_ctrl_passthru_mem_tl_intg_err.1262477629 May 23 01:42:03 PM PDT 24 May 23 01:42:25 PM PDT 24 376989728 ps
T391 /workspace/coverage/cover_reg_top/4.rom_ctrl_same_csr_outstanding.1491775735 May 23 01:41:57 PM PDT 24 May 23 01:42:08 PM PDT 24 454671175 ps
T392 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_mem_rw_with_rand_reset.4199848964 May 23 01:42:03 PM PDT 24 May 23 01:42:21 PM PDT 24 1301915939 ps
T393 /workspace/coverage/cover_reg_top/0.rom_ctrl_same_csr_outstanding.1265695228 May 23 01:41:58 PM PDT 24 May 23 01:42:17 PM PDT 24 1842951345 ps
T394 /workspace/coverage/cover_reg_top/17.rom_ctrl_same_csr_outstanding.4173982386 May 23 01:42:11 PM PDT 24 May 23 01:42:30 PM PDT 24 20236756172 ps
T104 /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_intg_err.1744748931 May 23 01:42:10 PM PDT 24 May 23 01:42:59 PM PDT 24 1917371696 ps
T395 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_rw.3203844001 May 23 01:41:59 PM PDT 24 May 23 01:42:07 PM PDT 24 85620504 ps
T396 /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_mem_rw_with_rand_reset.471287801 May 23 01:42:02 PM PDT 24 May 23 01:42:21 PM PDT 24 13308842557 ps
T83 /workspace/coverage/cover_reg_top/12.rom_ctrl_passthru_mem_tl_intg_err.4062396575 May 23 01:42:11 PM PDT 24 May 23 01:42:43 PM PDT 24 1747925336 ps
T113 /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_intg_err.3146813198 May 23 01:42:01 PM PDT 24 May 23 01:42:43 PM PDT 24 1255536441 ps
T397 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_bit_bash.710910172 May 23 01:41:59 PM PDT 24 May 23 01:42:12 PM PDT 24 1671223153 ps
T398 /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_errors.719619717 May 23 01:41:58 PM PDT 24 May 23 01:42:23 PM PDT 24 2208368438 ps
T399 /workspace/coverage/cover_reg_top/6.rom_ctrl_same_csr_outstanding.2658796917 May 23 01:42:04 PM PDT 24 May 23 01:42:13 PM PDT 24 85484555 ps
T400 /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_walk.3637122383 May 23 01:42:01 PM PDT 24 May 23 01:42:22 PM PDT 24 2448134549 ps
T112 /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_intg_err.4267329128 May 23 01:42:13 PM PDT 24 May 23 01:42:54 PM PDT 24 698073176 ps
T401 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_aliasing.1432067036 May 23 01:42:03 PM PDT 24 May 23 01:42:21 PM PDT 24 6651756865 ps
T402 /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_partial_access.832851774 May 23 01:42:04 PM PDT 24 May 23 01:42:17 PM PDT 24 2905222065 ps
T403 /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_errors.705851808 May 23 01:42:02 PM PDT 24 May 23 01:42:20 PM PDT 24 3078823135 ps
T84 /workspace/coverage/cover_reg_top/16.rom_ctrl_passthru_mem_tl_intg_err.935465588 May 23 01:42:13 PM PDT 24 May 23 01:43:15 PM PDT 24 5066280584 ps
T85 /workspace/coverage/cover_reg_top/9.rom_ctrl_passthru_mem_tl_intg_err.2472537776 May 23 01:42:02 PM PDT 24 May 23 01:43:23 PM PDT 24 72156492853 ps
T90 /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_rw.160080668 May 23 01:42:11 PM PDT 24 May 23 01:42:32 PM PDT 24 4360512140 ps
T404 /workspace/coverage/cover_reg_top/18.rom_ctrl_same_csr_outstanding.802786876 May 23 01:42:14 PM PDT 24 May 23 01:42:32 PM PDT 24 2685975183 ps
T405 /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_partial_access.487208864 May 23 01:41:57 PM PDT 24 May 23 01:42:16 PM PDT 24 2168506211 ps
T406 /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_partial_access.2892728112 May 23 01:42:02 PM PDT 24 May 23 01:42:19 PM PDT 24 1443430663 ps
T407 /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_errors.2310246721 May 23 01:42:02 PM PDT 24 May 23 01:42:22 PM PDT 24 1270131394 ps
T408 /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_rw.3682804327 May 23 01:41:59 PM PDT 24 May 23 01:42:11 PM PDT 24 2598552071 ps
T106 /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_intg_err.1164150252 May 23 01:41:57 PM PDT 24 May 23 01:43:18 PM PDT 24 11360632086 ps
T409 /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_mem_rw_with_rand_reset.3260446374 May 23 01:42:14 PM PDT 24 May 23 01:42:26 PM PDT 24 433452530 ps
T108 /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_intg_err.3212340714 May 23 01:42:01 PM PDT 24 May 23 01:43:14 PM PDT 24 352556683 ps
T410 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_hw_reset.3018490001 May 23 01:41:58 PM PDT 24 May 23 01:42:12 PM PDT 24 517004833 ps
T411 /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_intg_err.3062909411 May 23 01:42:10 PM PDT 24 May 23 01:42:54 PM PDT 24 1728079933 ps
T412 /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_walk.3915545838 May 23 01:42:01 PM PDT 24 May 23 01:42:16 PM PDT 24 1034722372 ps
T413 /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_walk.1490383349 May 23 01:41:59 PM PDT 24 May 23 01:42:15 PM PDT 24 6099429686 ps
T414 /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_mem_rw_with_rand_reset.1973769919 May 23 01:42:15 PM PDT 24 May 23 01:42:36 PM PDT 24 13773543041 ps
T415 /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_mem_rw_with_rand_reset.99324937 May 23 01:42:11 PM PDT 24 May 23 01:42:19 PM PDT 24 94745869 ps
T416 /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_intg_err.1975470648 May 23 01:42:13 PM PDT 24 May 23 01:43:32 PM PDT 24 1512387634 ps
T417 /workspace/coverage/cover_reg_top/10.rom_ctrl_same_csr_outstanding.557853303 May 23 01:42:13 PM PDT 24 May 23 01:42:31 PM PDT 24 6170798714 ps
T418 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_bit_bash.2210873267 May 23 01:41:59 PM PDT 24 May 23 01:42:15 PM PDT 24 5155930529 ps
T419 /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_errors.633712683 May 23 01:42:11 PM PDT 24 May 23 01:42:29 PM PDT 24 967027897 ps
T105 /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_intg_err.1594676269 May 23 01:42:02 PM PDT 24 May 23 01:43:18 PM PDT 24 1439156164 ps
T420 /workspace/coverage/cover_reg_top/2.rom_ctrl_same_csr_outstanding.3005736147 May 23 01:42:01 PM PDT 24 May 23 01:42:19 PM PDT 24 6701732479 ps
T421 /workspace/coverage/cover_reg_top/7.rom_ctrl_same_csr_outstanding.3239679035 May 23 01:42:02 PM PDT 24 May 23 01:42:14 PM PDT 24 429286731 ps
T422 /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_mem_rw_with_rand_reset.121964553 May 23 01:42:16 PM PDT 24 May 23 01:42:24 PM PDT 24 419023143 ps
T423 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_bit_bash.3599692809 May 23 01:41:58 PM PDT 24 May 23 01:42:18 PM PDT 24 8142490338 ps
T86 /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_rw.1808847607 May 23 01:42:02 PM PDT 24 May 23 01:42:17 PM PDT 24 1098687698 ps
T424 /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_intg_err.4176608499 May 23 01:42:03 PM PDT 24 May 23 01:43:17 PM PDT 24 287278759 ps
T425 /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_errors.3004013096 May 23 01:42:12 PM PDT 24 May 23 01:42:29 PM PDT 24 4049517457 ps
T426 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_rw.3226668567 May 23 01:42:01 PM PDT 24 May 23 01:42:17 PM PDT 24 1119114430 ps
T427 /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_errors.1390534352 May 23 01:42:10 PM PDT 24 May 23 01:42:25 PM PDT 24 333020967 ps
T428 /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_rw.3378046442 May 23 01:42:12 PM PDT 24 May 23 01:42:25 PM PDT 24 1092441875 ps
T429 /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_intg_err.2443923188 May 23 01:42:16 PM PDT 24 May 23 01:43:30 PM PDT 24 895182705 ps
T101 /workspace/coverage/cover_reg_top/15.rom_ctrl_passthru_mem_tl_intg_err.1065082533 May 23 01:42:11 PM PDT 24 May 23 01:43:17 PM PDT 24 103728868092 ps
T430 /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_rw.938175754 May 23 01:42:02 PM PDT 24 May 23 01:42:11 PM PDT 24 395807377 ps
T431 /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_rw.3410932770 May 23 01:42:10 PM PDT 24 May 23 01:42:25 PM PDT 24 2461661758 ps
T432 /workspace/coverage/cover_reg_top/3.rom_ctrl_passthru_mem_tl_intg_err.225020816 May 23 01:42:04 PM PDT 24 May 23 01:42:41 PM PDT 24 9309542350 ps
T91 /workspace/coverage/cover_reg_top/13.rom_ctrl_passthru_mem_tl_intg_err.2265588236 May 23 01:42:11 PM PDT 24 May 23 01:42:54 PM PDT 24 1879560875 ps
T433 /workspace/coverage/cover_reg_top/5.rom_ctrl_passthru_mem_tl_intg_err.2305209407 May 23 01:42:00 PM PDT 24 May 23 01:43:04 PM PDT 24 20298812616 ps
T109 /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_intg_err.3011277695 May 23 01:42:04 PM PDT 24 May 23 01:42:54 PM PDT 24 3794354414 ps
T434 /workspace/coverage/cover_reg_top/13.rom_ctrl_same_csr_outstanding.368326887 May 23 01:42:10 PM PDT 24 May 23 01:42:22 PM PDT 24 788304351 ps
T435 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_mem_rw_with_rand_reset.403535143 May 23 01:41:57 PM PDT 24 May 23 01:42:09 PM PDT 24 409799083 ps
T436 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_aliasing.1147116630 May 23 01:42:04 PM PDT 24 May 23 01:42:21 PM PDT 24 6037445544 ps
T437 /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_intg_err.65672193 May 23 01:42:12 PM PDT 24 May 23 01:43:33 PM PDT 24 2027172877 ps
T438 /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_mem_rw_with_rand_reset.2814450263 May 23 01:42:17 PM PDT 24 May 23 01:42:36 PM PDT 24 8358621485 ps
T439 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_mem_rw_with_rand_reset.561274941 May 23 01:42:00 PM PDT 24 May 23 01:42:18 PM PDT 24 6389589406 ps
T440 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_bit_bash.2371836839 May 23 01:42:00 PM PDT 24 May 23 01:42:16 PM PDT 24 2348738821 ps
T441 /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_errors.1792041842 May 23 01:42:13 PM PDT 24 May 23 01:42:35 PM PDT 24 6741456736 ps
T442 /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_rw.3115831212 May 23 01:42:12 PM PDT 24 May 23 01:42:31 PM PDT 24 2015939490 ps
T87 /workspace/coverage/cover_reg_top/18.rom_ctrl_passthru_mem_tl_intg_err.4082733515 May 23 01:42:10 PM PDT 24 May 23 01:43:05 PM PDT 24 5657509873 ps
T443 /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_errors.670985980 May 23 01:42:11 PM PDT 24 May 23 01:42:21 PM PDT 24 332607744 ps
T92 /workspace/coverage/cover_reg_top/1.rom_ctrl_passthru_mem_tl_intg_err.2478284796 May 23 01:42:00 PM PDT 24 May 23 01:42:32 PM PDT 24 1097924399 ps
T444 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_aliasing.2580600198 May 23 01:42:02 PM PDT 24 May 23 01:42:11 PM PDT 24 256512936 ps
T445 /workspace/coverage/cover_reg_top/14.rom_ctrl_passthru_mem_tl_intg_err.3485998884 May 23 01:42:10 PM PDT 24 May 23 01:42:58 PM PDT 24 11745793658 ps
T446 /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_rw.3494936267 May 23 01:42:05 PM PDT 24 May 23 01:42:15 PM PDT 24 412739265 ps
T447 /workspace/coverage/cover_reg_top/19.rom_ctrl_passthru_mem_tl_intg_err.3381398931 May 23 01:42:15 PM PDT 24 May 23 01:43:13 PM PDT 24 13674913587 ps
T110 /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_intg_err.3394466079 May 23 01:41:47 PM PDT 24 May 23 01:42:33 PM PDT 24 776870232 ps
T448 /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_mem_rw_with_rand_reset.1292133828 May 23 01:42:12 PM PDT 24 May 23 01:42:21 PM PDT 24 400759005 ps
T449 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_hw_reset.3845251041 May 23 01:41:58 PM PDT 24 May 23 01:42:17 PM PDT 24 1603521730 ps
T88 /workspace/coverage/cover_reg_top/10.rom_ctrl_passthru_mem_tl_intg_err.3483864266 May 23 01:42:05 PM PDT 24 May 23 01:42:59 PM PDT 24 21379450939 ps
T450 /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_errors.3857628937 May 23 01:42:02 PM PDT 24 May 23 01:42:20 PM PDT 24 7181802828 ps
T451 /workspace/coverage/cover_reg_top/12.rom_ctrl_same_csr_outstanding.153078791 May 23 01:42:14 PM PDT 24 May 23 01:42:22 PM PDT 24 168676732 ps
T452 /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_errors.1500362974 May 23 01:41:48 PM PDT 24 May 23 01:42:11 PM PDT 24 1825671649 ps
T453 /workspace/coverage/cover_reg_top/1.rom_ctrl_same_csr_outstanding.1026986993 May 23 01:41:57 PM PDT 24 May 23 01:42:05 PM PDT 24 89248655 ps
T454 /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_intg_err.1424329057 May 23 01:42:00 PM PDT 24 May 23 01:42:49 PM PDT 24 3220710010 ps
T455 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_mem_rw_with_rand_reset.3422511549 May 23 01:42:05 PM PDT 24 May 23 01:42:23 PM PDT 24 5938247224 ps
T456 /workspace/coverage/cover_reg_top/9.rom_ctrl_same_csr_outstanding.3966154563 May 23 01:42:04 PM PDT 24 May 23 01:42:23 PM PDT 24 1380928704 ps
T457 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_hw_reset.3421082110 May 23 01:41:57 PM PDT 24 May 23 01:42:08 PM PDT 24 698414466 ps
T458 /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_mem_rw_with_rand_reset.1492565924 May 23 01:42:03 PM PDT 24 May 23 01:42:21 PM PDT 24 1632541680 ps
T459 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_bit_bash.2954746700 May 23 01:42:04 PM PDT 24 May 23 01:42:19 PM PDT 24 2093446593 ps
T460 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_aliasing.854787078 May 23 01:41:59 PM PDT 24 May 23 01:42:11 PM PDT 24 860046356 ps
T89 /workspace/coverage/cover_reg_top/6.rom_ctrl_passthru_mem_tl_intg_err.3328566748 May 23 01:42:02 PM PDT 24 May 23 01:42:25 PM PDT 24 2111959728 ps
T461 /workspace/coverage/cover_reg_top/0.rom_ctrl_passthru_mem_tl_intg_err.4146881414 May 23 01:41:46 PM PDT 24 May 23 01:43:12 PM PDT 24 9451354040 ps
T462 /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_errors.3728719251 May 23 01:42:02 PM PDT 24 May 23 01:42:15 PM PDT 24 87545893 ps

Test location /workspace/coverage/default/45.rom_ctrl_stress_all.2506664991
Short name T2
Test name
Test status
Simulation time 6039659442 ps
CPU time 73.56 seconds
Started May 23 01:43:33 PM PDT 24
Finished May 23 01:44:48 PM PDT 24
Peak memory 217560 kb
Host smart-e163b41c-a6e9-44f5-acf7-9ed2afea2ef2
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2506664991 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 45.rom_ctrl_stress_all.2506664991
Directory /workspace/45.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/2.rom_ctrl_stress_all_with_rand_reset.3689428055
Short name T13
Test name
Test status
Simulation time 140946699112 ps
CPU time 1460.48 seconds
Started May 23 01:42:30 PM PDT 24
Finished May 23 02:06:52 PM PDT 24
Peak memory 235952 kb
Host smart-d32c3bec-7730-4a81-b3b6-63893c3c6982
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3689428055 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_stress_all_with_rand_reset.3689428055
Directory /workspace/2.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.rom_ctrl_corrupt_sig_fatal_chk.2124081714
Short name T21
Test name
Test status
Simulation time 49607495127 ps
CPU time 312.46 seconds
Started May 23 01:42:24 PM PDT 24
Finished May 23 01:47:37 PM PDT 24
Peak memory 225300 kb
Host smart-a29046c6-e455-41db-9478-4b55870cf372
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2124081714 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_c
orrupt_sig_fatal_chk.2124081714
Directory /workspace/6.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_intg_err.2937991454
Short name T61
Test name
Test status
Simulation time 1386537724 ps
CPU time 73.42 seconds
Started May 23 01:42:16 PM PDT 24
Finished May 23 01:43:32 PM PDT 24
Peak memory 211328 kb
Host smart-e77e9459-0190-4e07-a3d8-ed22786eb0df
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2937991454 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_tl_i
ntg_err.2937991454
Directory /workspace/19.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/46.rom_ctrl_corrupt_sig_fatal_chk.3428887587
Short name T25
Test name
Test status
Simulation time 19217314787 ps
CPU time 208.67 seconds
Started May 23 01:43:25 PM PDT 24
Finished May 23 01:46:56 PM PDT 24
Peak memory 228664 kb
Host smart-83287447-03f4-454a-8010-21787d4c5f51
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3428887587 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_
corrupt_sig_fatal_chk.3428887587
Directory /workspace/46.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/30.rom_ctrl_stress_all.1995380908
Short name T11
Test name
Test status
Simulation time 5819146298 ps
CPU time 56.11 seconds
Started May 23 01:43:13 PM PDT 24
Finished May 23 01:44:12 PM PDT 24
Peak memory 214032 kb
Host smart-d759c739-1628-4b2b-ae9c-5129335228c8
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1995380908 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 30.rom_ctrl_stress_all.1995380908
Directory /workspace/30.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/40.rom_ctrl_alert_test.1195406922
Short name T1
Test name
Test status
Simulation time 1474519377 ps
CPU time 6.95 seconds
Started May 23 01:43:21 PM PDT 24
Finished May 23 01:43:31 PM PDT 24
Peak memory 211260 kb
Host smart-7a1999b2-8ad2-4910-8cf8-1b8895093a8e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1195406922 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_alert_test.1195406922
Directory /workspace/40.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/0.rom_ctrl_sec_cm.2436249958
Short name T31
Test name
Test status
Simulation time 531379995 ps
CPU time 99.19 seconds
Started May 23 01:42:21 PM PDT 24
Finished May 23 01:44:02 PM PDT 24
Peak memory 230488 kb
Host smart-954a68c8-ef87-4447-b619-036805ae0f1a
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2436249958 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_sec_cm.2436249958
Directory /workspace/0.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_passthru_mem_tl_intg_err.4062396575
Short name T83
Test name
Test status
Simulation time 1747925336 ps
CPU time 29.21 seconds
Started May 23 01:42:11 PM PDT 24
Finished May 23 01:42:43 PM PDT 24
Peak memory 211324 kb
Host smart-be76d604-2ac6-4f7f-8e3e-b9a06da39b91
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4062396575 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_p
assthru_mem_tl_intg_err.4062396575
Directory /workspace/12.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_intg_err.1164150252
Short name T106
Test name
Test status
Simulation time 11360632086 ps
CPU time 77.31 seconds
Started May 23 01:41:57 PM PDT 24
Finished May 23 01:43:18 PM PDT 24
Peak memory 219504 kb
Host smart-c929bd15-d2ab-48da-bb5d-db5f329619f7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1164150252 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_tl_in
tg_err.1164150252
Directory /workspace/1.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/24.rom_ctrl_stress_all_with_rand_reset.1936539211
Short name T57
Test name
Test status
Simulation time 26101180417 ps
CPU time 356.57 seconds
Started May 23 01:42:59 PM PDT 24
Finished May 23 01:48:58 PM PDT 24
Peak memory 224640 kb
Host smart-293b2661-f93a-46fd-a614-32f27d5fc012
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1936539211 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_stress_all_with_rand_reset.1936539211
Directory /workspace/24.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/11.rom_ctrl_kmac_err_chk.16724735
Short name T19
Test name
Test status
Simulation time 694507730 ps
CPU time 9.43 seconds
Started May 23 01:42:31 PM PDT 24
Finished May 23 01:42:42 PM PDT 24
Peak memory 211340 kb
Host smart-079791fb-c3e1-472e-b8a0-2084bb433575
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=16724735 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_kmac_err_chk.16724735
Directory /workspace/11.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/16.rom_ctrl_kmac_err_chk.2054907050
Short name T118
Test name
Test status
Simulation time 11044811545 ps
CPU time 21.66 seconds
Started May 23 01:42:38 PM PDT 24
Finished May 23 01:43:01 PM PDT 24
Peak memory 211740 kb
Host smart-5812783d-0784-4180-be4f-e05a8e522c46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2054907050 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_kmac_err_chk.2054907050
Directory /workspace/16.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_intg_err.1594676269
Short name T105
Test name
Test status
Simulation time 1439156164 ps
CPU time 71.92 seconds
Started May 23 01:42:02 PM PDT 24
Finished May 23 01:43:18 PM PDT 24
Peak memory 213096 kb
Host smart-1214d99c-33a8-4a6e-b3c2-d476999957f8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1594676269 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_tl_i
ntg_err.1594676269
Directory /workspace/10.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_rw.2083343800
Short name T72
Test name
Test status
Simulation time 255638437 ps
CPU time 5.99 seconds
Started May 23 01:42:02 PM PDT 24
Finished May 23 01:42:12 PM PDT 24
Peak memory 211280 kb
Host smart-41c6d57c-7372-4e91-81b3-4d67e454f906
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2083343800 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_rw.2083343800
Directory /workspace/2.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_passthru_mem_tl_intg_err.4146881414
Short name T461
Test name
Test status
Simulation time 9451354040 ps
CPU time 79.62 seconds
Started May 23 01:41:46 PM PDT 24
Finished May 23 01:43:12 PM PDT 24
Peak memory 211396 kb
Host smart-a777a901-dd6c-46fa-b57d-774505f4a138
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4146881414 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_pa
ssthru_mem_tl_intg_err.4146881414
Directory /workspace/0.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_intg_err.3394466079
Short name T110
Test name
Test status
Simulation time 776870232 ps
CPU time 39.95 seconds
Started May 23 01:41:47 PM PDT 24
Finished May 23 01:42:33 PM PDT 24
Peak memory 212228 kb
Host smart-cde4726c-1035-42eb-b08f-b2cafc13a7f5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3394466079 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_tl_in
tg_err.3394466079
Directory /workspace/0.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/14.rom_ctrl_stress_all.2558553340
Short name T50
Test name
Test status
Simulation time 14134328150 ps
CPU time 54.82 seconds
Started May 23 01:42:41 PM PDT 24
Finished May 23 01:43:37 PM PDT 24
Peak memory 219468 kb
Host smart-1b13cfa9-93d9-44e8-8adb-f75fb718a860
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2558553340 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 14.rom_ctrl_stress_all.2558553340
Directory /workspace/14.rom_ctrl_stress_all/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_mem_rw_with_rand_reset.298554670
Short name T369
Test name
Test status
Simulation time 1554060200 ps
CPU time 6.96 seconds
Started May 23 01:41:59 PM PDT 24
Finished May 23 01:42:11 PM PDT 24
Peak memory 219532 kb
Host smart-5c96a275-5d72-4c8b-881d-adae0a69283f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=298554670 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 1.rom_ctrl_csr_mem_rw_with_rand_reset.298554670
Directory /workspace/1.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/default/1.rom_ctrl_corrupt_sig_fatal_chk.1596090496
Short name T248
Test name
Test status
Simulation time 72558755259 ps
CPU time 242.4 seconds
Started May 23 01:42:21 PM PDT 24
Finished May 23 01:46:26 PM PDT 24
Peak memory 237912 kb
Host smart-adaf762e-a0d9-4ee3-9cc2-e6af85a8e9ab
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1596090496 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_c
orrupt_sig_fatal_chk.1596090496
Directory /workspace/1.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_aliasing.1432067036
Short name T401
Test name
Test status
Simulation time 6651756865 ps
CPU time 13.89 seconds
Started May 23 01:42:03 PM PDT 24
Finished May 23 01:42:21 PM PDT 24
Peak memory 211352 kb
Host smart-34bad8ed-786d-4d75-9ade-c332717d2b52
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1432067036 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_alia
sing.1432067036
Directory /workspace/0.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_bit_bash.2210873267
Short name T418
Test name
Test status
Simulation time 5155930529 ps
CPU time 12 seconds
Started May 23 01:41:59 PM PDT 24
Finished May 23 01:42:15 PM PDT 24
Peak memory 211308 kb
Host smart-83b5f583-4bea-456b-95c3-7eedd1201829
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2210873267 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_bit_
bash.2210873267
Directory /workspace/0.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_hw_reset.3421082110
Short name T457
Test name
Test status
Simulation time 698414466 ps
CPU time 6.99 seconds
Started May 23 01:41:57 PM PDT 24
Finished May 23 01:42:08 PM PDT 24
Peak memory 211284 kb
Host smart-86cb01a2-7024-41a6-b40f-19c72ae609c9
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3421082110 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_hw_r
eset.3421082110
Directory /workspace/0.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_mem_rw_with_rand_reset.403535143
Short name T435
Test name
Test status
Simulation time 409799083 ps
CPU time 7.7 seconds
Started May 23 01:41:57 PM PDT 24
Finished May 23 01:42:09 PM PDT 24
Peak memory 219552 kb
Host smart-33f61fb4-f5d5-4eed-906c-7ca380faa2eb
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=403535143 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 0.rom_ctrl_csr_mem_rw_with_rand_reset.403535143
Directory /workspace/0.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_rw.3203844001
Short name T395
Test name
Test status
Simulation time 85620504 ps
CPU time 4.33 seconds
Started May 23 01:41:59 PM PDT 24
Finished May 23 01:42:07 PM PDT 24
Peak memory 211240 kb
Host smart-0a2d53a8-8fbe-4042-8c94-db452c7f2efe
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3203844001 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_rw.3203844001
Directory /workspace/0.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_partial_access.487208864
Short name T405
Test name
Test status
Simulation time 2168506211 ps
CPU time 15.51 seconds
Started May 23 01:41:57 PM PDT 24
Finished May 23 01:42:16 PM PDT 24
Peak memory 211216 kb
Host smart-28f4c76c-a7e4-4509-9d52-e44a8be2f404
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=487208864 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl
_mem_partial_access.487208864
Directory /workspace/0.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_walk.1490383349
Short name T413
Test name
Test status
Simulation time 6099429686 ps
CPU time 10.8 seconds
Started May 23 01:41:59 PM PDT 24
Finished May 23 01:42:15 PM PDT 24
Peak memory 211292 kb
Host smart-3d053811-b641-495d-8464-bb32213baa8e
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1490383349 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_mem_walk
.1490383349
Directory /workspace/0.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_same_csr_outstanding.1265695228
Short name T393
Test name
Test status
Simulation time 1842951345 ps
CPU time 15.39 seconds
Started May 23 01:41:58 PM PDT 24
Finished May 23 01:42:17 PM PDT 24
Peak memory 211236 kb
Host smart-90a36da7-1026-4f7f-b300-76b4dbe0a7f3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1265695228 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_c
trl_same_csr_outstanding.1265695228
Directory /workspace/0.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_errors.1500362974
Short name T452
Test name
Test status
Simulation time 1825671649 ps
CPU time 17.13 seconds
Started May 23 01:41:48 PM PDT 24
Finished May 23 01:42:11 PM PDT 24
Peak memory 219548 kb
Host smart-a77b4b5f-6990-43f4-bb36-23b80414db01
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1500362974 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_tl_errors.1500362974
Directory /workspace/0.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_aliasing.1147116630
Short name T436
Test name
Test status
Simulation time 6037445544 ps
CPU time 13.42 seconds
Started May 23 01:42:04 PM PDT 24
Finished May 23 01:42:21 PM PDT 24
Peak memory 211372 kb
Host smart-01533454-64bc-4fab-988d-580bc2604851
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1147116630 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_alia
sing.1147116630
Directory /workspace/1.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_bit_bash.710910172
Short name T397
Test name
Test status
Simulation time 1671223153 ps
CPU time 9.3 seconds
Started May 23 01:41:59 PM PDT 24
Finished May 23 01:42:12 PM PDT 24
Peak memory 211272 kb
Host smart-620f4021-fde1-4099-91d6-4626cb05b6f4
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=710910172 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_bit_b
ash.710910172
Directory /workspace/1.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_hw_reset.3845251041
Short name T449
Test name
Test status
Simulation time 1603521730 ps
CPU time 15.15 seconds
Started May 23 01:41:58 PM PDT 24
Finished May 23 01:42:17 PM PDT 24
Peak memory 211368 kb
Host smart-22f3dc2b-f23f-40ef-8466-2d757b5f87ac
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3845251041 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_hw_r
eset.3845251041
Directory /workspace/1.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_rw.1185838269
Short name T62
Test name
Test status
Simulation time 3673499131 ps
CPU time 8.12 seconds
Started May 23 01:41:57 PM PDT 24
Finished May 23 01:42:09 PM PDT 24
Peak memory 211364 kb
Host smart-82b263bc-8768-4ead-a695-11a4047fe95c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1185838269 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_rw.1185838269
Directory /workspace/1.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_partial_access.2911624895
Short name T371
Test name
Test status
Simulation time 1130729576 ps
CPU time 5.86 seconds
Started May 23 01:41:58 PM PDT 24
Finished May 23 01:42:08 PM PDT 24
Peak memory 211132 kb
Host smart-030a08dd-1bfb-4201-9a3a-5ecbdf5c2ad4
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2911624895 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctr
l_mem_partial_access.2911624895
Directory /workspace/1.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_walk.3007914819
Short name T373
Test name
Test status
Simulation time 2916018172 ps
CPU time 8.74 seconds
Started May 23 01:42:00 PM PDT 24
Finished May 23 01:42:13 PM PDT 24
Peak memory 211300 kb
Host smart-54185e36-a932-4315-aea9-61010a3fc50e
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3007914819 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_mem_walk
.3007914819
Directory /workspace/1.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_passthru_mem_tl_intg_err.2478284796
Short name T92
Test name
Test status
Simulation time 1097924399 ps
CPU time 27.87 seconds
Started May 23 01:42:00 PM PDT 24
Finished May 23 01:42:32 PM PDT 24
Peak memory 211392 kb
Host smart-f739135e-4c57-4089-8a77-19e09e2c1c22
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2478284796 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_pa
ssthru_mem_tl_intg_err.2478284796
Directory /workspace/1.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_same_csr_outstanding.1026986993
Short name T453
Test name
Test status
Simulation time 89248655 ps
CPU time 4.32 seconds
Started May 23 01:41:57 PM PDT 24
Finished May 23 01:42:05 PM PDT 24
Peak memory 211284 kb
Host smart-759666b2-72ed-491c-b015-eb926f542913
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1026986993 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_c
trl_same_csr_outstanding.1026986993
Directory /workspace/1.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_errors.719619717
Short name T398
Test name
Test status
Simulation time 2208368438 ps
CPU time 20.42 seconds
Started May 23 01:41:58 PM PDT 24
Finished May 23 01:42:23 PM PDT 24
Peak memory 219608 kb
Host smart-26d296a6-6fb3-486d-9d73-96fcc1ca938b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=719619717 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_tl_errors.719619717
Directory /workspace/1.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_mem_rw_with_rand_reset.121964553
Short name T422
Test name
Test status
Simulation time 419023143 ps
CPU time 5.25 seconds
Started May 23 01:42:16 PM PDT 24
Finished May 23 01:42:24 PM PDT 24
Peak memory 219476 kb
Host smart-d616db65-8236-4332-9668-b6cfdfa8152d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=121964553 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 10.rom_ctrl_csr_mem_rw_with_rand_reset.121964553
Directory /workspace/10.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_rw.4148541161
Short name T389
Test name
Test status
Simulation time 1684922607 ps
CPU time 14.01 seconds
Started May 23 01:42:10 PM PDT 24
Finished May 23 01:42:28 PM PDT 24
Peak memory 211360 kb
Host smart-13944c2c-ba7b-46a2-8e63-8d85534990e8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4148541161 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_csr_rw.4148541161
Directory /workspace/10.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_passthru_mem_tl_intg_err.3483864266
Short name T88
Test name
Test status
Simulation time 21379450939 ps
CPU time 50.07 seconds
Started May 23 01:42:05 PM PDT 24
Finished May 23 01:42:59 PM PDT 24
Peak memory 211424 kb
Host smart-63097088-bc59-4c07-a9fd-e5b8ee4a3cb3
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3483864266 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_p
assthru_mem_tl_intg_err.3483864266
Directory /workspace/10.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_same_csr_outstanding.557853303
Short name T417
Test name
Test status
Simulation time 6170798714 ps
CPU time 14.68 seconds
Started May 23 01:42:13 PM PDT 24
Finished May 23 01:42:31 PM PDT 24
Peak memory 211320 kb
Host smart-73aad110-8ca4-4f2b-9ddf-446bc99db90f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=557853303 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_c
trl_same_csr_outstanding.557853303
Directory /workspace/10.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_errors.2310246721
Short name T407
Test name
Test status
Simulation time 1270131394 ps
CPU time 15.95 seconds
Started May 23 01:42:02 PM PDT 24
Finished May 23 01:42:22 PM PDT 24
Peak memory 219544 kb
Host smart-f7b57ca2-85a8-4a1c-bfc7-3d2e282790b3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2310246721 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_tl_errors.2310246721
Directory /workspace/10.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_mem_rw_with_rand_reset.1206374760
Short name T379
Test name
Test status
Simulation time 1393848075 ps
CPU time 11.32 seconds
Started May 23 01:42:13 PM PDT 24
Finished May 23 01:42:28 PM PDT 24
Peak memory 219528 kb
Host smart-7de9681a-afa3-41a5-906c-5b6308da6bfc
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1206374760 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 11.rom_ctrl_csr_mem_rw_with_rand_reset.1206374760
Directory /workspace/11.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_rw.3115831212
Short name T442
Test name
Test status
Simulation time 2015939490 ps
CPU time 14.83 seconds
Started May 23 01:42:12 PM PDT 24
Finished May 23 01:42:31 PM PDT 24
Peak memory 211328 kb
Host smart-77b8c636-bd22-46b2-af39-85ec99b5b8a4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3115831212 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_csr_rw.3115831212
Directory /workspace/11.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_passthru_mem_tl_intg_err.595009076
Short name T98
Test name
Test status
Simulation time 2248485027 ps
CPU time 27.71 seconds
Started May 23 01:42:13 PM PDT 24
Finished May 23 01:42:44 PM PDT 24
Peak memory 211356 kb
Host smart-5948118d-04c4-4842-876f-f2fafeac5ca4
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=595009076 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_pa
ssthru_mem_tl_intg_err.595009076
Directory /workspace/11.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_same_csr_outstanding.3154422761
Short name T97
Test name
Test status
Simulation time 341965250 ps
CPU time 6.24 seconds
Started May 23 01:42:11 PM PDT 24
Finished May 23 01:42:21 PM PDT 24
Peak memory 211280 kb
Host smart-61a25a95-63b5-4b05-92d7-e93caef46ebd
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3154422761 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_
ctrl_same_csr_outstanding.3154422761
Directory /workspace/11.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_errors.1792041842
Short name T441
Test name
Test status
Simulation time 6741456736 ps
CPU time 18.56 seconds
Started May 23 01:42:13 PM PDT 24
Finished May 23 01:42:35 PM PDT 24
Peak memory 219600 kb
Host smart-521b013d-ebef-410e-bba2-df2143336de2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1792041842 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_tl_errors.1792041842
Directory /workspace/11.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_intg_err.4267329128
Short name T112
Test name
Test status
Simulation time 698073176 ps
CPU time 36.22 seconds
Started May 23 01:42:13 PM PDT 24
Finished May 23 01:42:54 PM PDT 24
Peak memory 211336 kb
Host smart-ad83ce3a-1d69-41ba-975c-88852b3201e8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4267329128 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_tl_i
ntg_err.4267329128
Directory /workspace/11.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_mem_rw_with_rand_reset.2345533731
Short name T381
Test name
Test status
Simulation time 2991184932 ps
CPU time 13.54 seconds
Started May 23 01:42:11 PM PDT 24
Finished May 23 01:42:28 PM PDT 24
Peak memory 219552 kb
Host smart-8c85141f-471e-4a08-8f52-612e608864c7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2345533731 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 12.rom_ctrl_csr_mem_rw_with_rand_reset.2345533731
Directory /workspace/12.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_rw.2952998822
Short name T370
Test name
Test status
Simulation time 611975117 ps
CPU time 6.11 seconds
Started May 23 01:42:11 PM PDT 24
Finished May 23 01:42:20 PM PDT 24
Peak memory 211304 kb
Host smart-8ea874ab-d846-4a9b-bfe6-951630728abb
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2952998822 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_csr_rw.2952998822
Directory /workspace/12.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_same_csr_outstanding.153078791
Short name T451
Test name
Test status
Simulation time 168676732 ps
CPU time 4.26 seconds
Started May 23 01:42:14 PM PDT 24
Finished May 23 01:42:22 PM PDT 24
Peak memory 211280 kb
Host smart-f2e8d741-e4e0-4a7e-8687-bc62617a1e6f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=153078791 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_c
trl_same_csr_outstanding.153078791
Directory /workspace/12.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_errors.1732493196
Short name T382
Test name
Test status
Simulation time 1279181757 ps
CPU time 16.4 seconds
Started May 23 01:42:14 PM PDT 24
Finished May 23 01:42:34 PM PDT 24
Peak memory 219572 kb
Host smart-4687a1df-28c4-40c4-8c7b-c84a534e1270
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1732493196 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_tl_errors.1732493196
Directory /workspace/12.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_intg_err.1975470648
Short name T416
Test name
Test status
Simulation time 1512387634 ps
CPU time 74.93 seconds
Started May 23 01:42:13 PM PDT 24
Finished May 23 01:43:32 PM PDT 24
Peak memory 212284 kb
Host smart-637fbf78-f58e-4f9d-b630-36aaac856976
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1975470648 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_tl_i
ntg_err.1975470648
Directory /workspace/12.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_mem_rw_with_rand_reset.1292133828
Short name T448
Test name
Test status
Simulation time 400759005 ps
CPU time 5.21 seconds
Started May 23 01:42:12 PM PDT 24
Finished May 23 01:42:21 PM PDT 24
Peak memory 219404 kb
Host smart-2a90095b-1962-44ba-a9b2-51eb172699cd
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1292133828 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 13.rom_ctrl_csr_mem_rw_with_rand_reset.1292133828
Directory /workspace/13.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_rw.3410932770
Short name T431
Test name
Test status
Simulation time 2461661758 ps
CPU time 11.74 seconds
Started May 23 01:42:10 PM PDT 24
Finished May 23 01:42:25 PM PDT 24
Peak memory 211356 kb
Host smart-37a21fae-43bb-4934-a7b5-4ce81f3fff60
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3410932770 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_csr_rw.3410932770
Directory /workspace/13.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_passthru_mem_tl_intg_err.2265588236
Short name T91
Test name
Test status
Simulation time 1879560875 ps
CPU time 39.85 seconds
Started May 23 01:42:11 PM PDT 24
Finished May 23 01:42:54 PM PDT 24
Peak memory 211356 kb
Host smart-a80f1e46-4191-4821-9be4-489e9ec6ae9b
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2265588236 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_p
assthru_mem_tl_intg_err.2265588236
Directory /workspace/13.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_same_csr_outstanding.368326887
Short name T434
Test name
Test status
Simulation time 788304351 ps
CPU time 8.46 seconds
Started May 23 01:42:10 PM PDT 24
Finished May 23 01:42:22 PM PDT 24
Peak memory 211296 kb
Host smart-05c72ee6-98d2-463a-aa02-4bd029d7be60
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=368326887 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_c
trl_same_csr_outstanding.368326887
Directory /workspace/13.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_errors.3910102545
Short name T366
Test name
Test status
Simulation time 642802171 ps
CPU time 11.49 seconds
Started May 23 01:42:11 PM PDT 24
Finished May 23 01:42:26 PM PDT 24
Peak memory 219560 kb
Host smart-66a2e855-039a-4ae8-af28-3572ae69cfef
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3910102545 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_tl_errors.3910102545
Directory /workspace/13.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_intg_err.65672193
Short name T437
Test name
Test status
Simulation time 2027172877 ps
CPU time 77.26 seconds
Started May 23 01:42:12 PM PDT 24
Finished May 23 01:43:33 PM PDT 24
Peak memory 213052 kb
Host smart-6b5c76a5-1c12-4fef-860a-fee83f0e3b07
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=65672193 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_tl_int
g_err.65672193
Directory /workspace/13.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_mem_rw_with_rand_reset.99324937
Short name T415
Test name
Test status
Simulation time 94745869 ps
CPU time 4.69 seconds
Started May 23 01:42:11 PM PDT 24
Finished May 23 01:42:19 PM PDT 24
Peak memory 213564 kb
Host smart-87f34bf5-574b-4acf-9379-a507b526ac6e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99324937 -assert nopostproc +UVM_TESTNAME=r
om_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 14.rom_ctrl_csr_mem_rw_with_rand_reset.99324937
Directory /workspace/14.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_rw.1006412833
Short name T82
Test name
Test status
Simulation time 4457693859 ps
CPU time 11.42 seconds
Started May 23 01:42:13 PM PDT 24
Finished May 23 01:42:29 PM PDT 24
Peak memory 211360 kb
Host smart-9d0ecce4-1912-4832-a01c-e32d2cc86ef7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1006412833 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_csr_rw.1006412833
Directory /workspace/14.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_passthru_mem_tl_intg_err.3485998884
Short name T445
Test name
Test status
Simulation time 11745793658 ps
CPU time 45.17 seconds
Started May 23 01:42:10 PM PDT 24
Finished May 23 01:42:58 PM PDT 24
Peak memory 211412 kb
Host smart-2eb0e6c7-fb72-4a9b-a189-f2df8e154802
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3485998884 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_p
assthru_mem_tl_intg_err.3485998884
Directory /workspace/14.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_same_csr_outstanding.3816553060
Short name T93
Test name
Test status
Simulation time 333990683 ps
CPU time 4.24 seconds
Started May 23 01:42:17 PM PDT 24
Finished May 23 01:42:24 PM PDT 24
Peak memory 211224 kb
Host smart-f0ba7c32-daf3-47e8-8d1d-cdfb8380e87a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3816553060 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_
ctrl_same_csr_outstanding.3816553060
Directory /workspace/14.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_errors.3004013096
Short name T425
Test name
Test status
Simulation time 4049517457 ps
CPU time 12.81 seconds
Started May 23 01:42:12 PM PDT 24
Finished May 23 01:42:29 PM PDT 24
Peak memory 219584 kb
Host smart-64192055-3aa7-432c-837a-efdf06004a08
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3004013096 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_tl_errors.3004013096
Directory /workspace/14.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_intg_err.2443923188
Short name T429
Test name
Test status
Simulation time 895182705 ps
CPU time 71.15 seconds
Started May 23 01:42:16 PM PDT 24
Finished May 23 01:43:30 PM PDT 24
Peak memory 212300 kb
Host smart-fbd83ec3-0f2a-45a5-88ec-843f172d1405
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2443923188 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_tl_i
ntg_err.2443923188
Directory /workspace/14.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_mem_rw_with_rand_reset.1973769919
Short name T414
Test name
Test status
Simulation time 13773543041 ps
CPU time 17.28 seconds
Started May 23 01:42:15 PM PDT 24
Finished May 23 01:42:36 PM PDT 24
Peak memory 219600 kb
Host smart-dba47d88-cbc1-471a-ba5c-09b409b6397a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1973769919 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 15.rom_ctrl_csr_mem_rw_with_rand_reset.1973769919
Directory /workspace/15.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_rw.3972325209
Short name T380
Test name
Test status
Simulation time 5901832468 ps
CPU time 16.06 seconds
Started May 23 01:42:12 PM PDT 24
Finished May 23 01:42:32 PM PDT 24
Peak memory 211360 kb
Host smart-f04c0361-b3f4-4e32-bd3f-9c9076c3464a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3972325209 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_csr_rw.3972325209
Directory /workspace/15.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_passthru_mem_tl_intg_err.1065082533
Short name T101
Test name
Test status
Simulation time 103728868092 ps
CPU time 62.53 seconds
Started May 23 01:42:11 PM PDT 24
Finished May 23 01:43:17 PM PDT 24
Peak memory 211380 kb
Host smart-15dd6491-88c6-49a3-8099-fcc26d459238
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1065082533 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_p
assthru_mem_tl_intg_err.1065082533
Directory /workspace/15.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_same_csr_outstanding.1620846141
Short name T95
Test name
Test status
Simulation time 7478261140 ps
CPU time 15.05 seconds
Started May 23 01:42:17 PM PDT 24
Finished May 23 01:42:34 PM PDT 24
Peak memory 211316 kb
Host smart-c8ef383d-a8cf-439a-a531-4e48749cf066
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1620846141 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_
ctrl_same_csr_outstanding.1620846141
Directory /workspace/15.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_errors.670985980
Short name T443
Test name
Test status
Simulation time 332607744 ps
CPU time 6.63 seconds
Started May 23 01:42:11 PM PDT 24
Finished May 23 01:42:21 PM PDT 24
Peak memory 215608 kb
Host smart-130f12d7-4647-4413-a444-857c3a954781
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=670985980 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_tl_errors.670985980
Directory /workspace/15.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_intg_err.3771856377
Short name T59
Test name
Test status
Simulation time 330787202 ps
CPU time 36.63 seconds
Started May 23 01:42:11 PM PDT 24
Finished May 23 01:42:52 PM PDT 24
Peak memory 212332 kb
Host smart-a5da8414-c39b-416f-b899-fb634dfa629b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3771856377 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_tl_i
ntg_err.3771856377
Directory /workspace/15.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_mem_rw_with_rand_reset.3039684351
Short name T384
Test name
Test status
Simulation time 588441595 ps
CPU time 7.51 seconds
Started May 23 01:42:16 PM PDT 24
Finished May 23 01:42:26 PM PDT 24
Peak memory 211588 kb
Host smart-42ed3b1c-a01c-498b-8724-db07ec4bfeac
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3039684351 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 16.rom_ctrl_csr_mem_rw_with_rand_reset.3039684351
Directory /workspace/16.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_rw.3378046442
Short name T428
Test name
Test status
Simulation time 1092441875 ps
CPU time 9.79 seconds
Started May 23 01:42:12 PM PDT 24
Finished May 23 01:42:25 PM PDT 24
Peak memory 211208 kb
Host smart-00e69eef-a52a-44e7-9b08-6c646c656f83
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3378046442 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_csr_rw.3378046442
Directory /workspace/16.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_passthru_mem_tl_intg_err.935465588
Short name T84
Test name
Test status
Simulation time 5066280584 ps
CPU time 58.25 seconds
Started May 23 01:42:13 PM PDT 24
Finished May 23 01:43:15 PM PDT 24
Peak memory 211416 kb
Host smart-dd65d0e9-c09e-49f4-a80d-b7f4a70bd164
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=935465588 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_pa
ssthru_mem_tl_intg_err.935465588
Directory /workspace/16.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_same_csr_outstanding.2566809015
Short name T94
Test name
Test status
Simulation time 6919181471 ps
CPU time 14.96 seconds
Started May 23 01:42:10 PM PDT 24
Finished May 23 01:42:28 PM PDT 24
Peak memory 211360 kb
Host smart-ed280077-fe2e-42b8-bdcd-d6255b70de0b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2566809015 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_
ctrl_same_csr_outstanding.2566809015
Directory /workspace/16.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_errors.633712683
Short name T419
Test name
Test status
Simulation time 967027897 ps
CPU time 14.57 seconds
Started May 23 01:42:11 PM PDT 24
Finished May 23 01:42:29 PM PDT 24
Peak memory 219560 kb
Host smart-42135677-d831-45e4-bcf5-6d9a092a7a40
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=633712683 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_tl_errors.633712683
Directory /workspace/16.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_intg_err.1643915317
Short name T103
Test name
Test status
Simulation time 463798557 ps
CPU time 37.74 seconds
Started May 23 01:42:21 PM PDT 24
Finished May 23 01:43:00 PM PDT 24
Peak memory 211832 kb
Host smart-f8b6d6aa-3865-4a1d-9ad0-b57037bb26dc
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1643915317 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_tl_i
ntg_err.1643915317
Directory /workspace/16.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_mem_rw_with_rand_reset.3260446374
Short name T409
Test name
Test status
Simulation time 433452530 ps
CPU time 8.57 seconds
Started May 23 01:42:14 PM PDT 24
Finished May 23 01:42:26 PM PDT 24
Peak memory 219540 kb
Host smart-678537be-939e-4851-bd0c-f49a2238a5cb
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3260446374 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 17.rom_ctrl_csr_mem_rw_with_rand_reset.3260446374
Directory /workspace/17.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_rw.160080668
Short name T90
Test name
Test status
Simulation time 4360512140 ps
CPU time 16.77 seconds
Started May 23 01:42:11 PM PDT 24
Finished May 23 01:42:32 PM PDT 24
Peak memory 211344 kb
Host smart-0f9fe43e-4165-4246-88b2-295a52b369b3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=160080668 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_csr_rw.160080668
Directory /workspace/17.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_passthru_mem_tl_intg_err.1528331168
Short name T100
Test name
Test status
Simulation time 4872467469 ps
CPU time 57.67 seconds
Started May 23 01:42:16 PM PDT 24
Finished May 23 01:43:17 PM PDT 24
Peak memory 211404 kb
Host smart-d858aa8e-8cfc-45bc-9547-d6eae2101780
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1528331168 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_p
assthru_mem_tl_intg_err.1528331168
Directory /workspace/17.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_same_csr_outstanding.4173982386
Short name T394
Test name
Test status
Simulation time 20236756172 ps
CPU time 16.01 seconds
Started May 23 01:42:11 PM PDT 24
Finished May 23 01:42:30 PM PDT 24
Peak memory 211336 kb
Host smart-05acc246-da06-4fc5-90e7-600178f71850
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4173982386 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_
ctrl_same_csr_outstanding.4173982386
Directory /workspace/17.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_errors.1390534352
Short name T427
Test name
Test status
Simulation time 333020967 ps
CPU time 10.79 seconds
Started May 23 01:42:10 PM PDT 24
Finished May 23 01:42:25 PM PDT 24
Peak memory 219500 kb
Host smart-63de1eed-d8e1-42f6-b6ea-36e3d03ae458
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1390534352 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_tl_errors.1390534352
Directory /workspace/17.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_intg_err.3062909411
Short name T411
Test name
Test status
Simulation time 1728079933 ps
CPU time 40.4 seconds
Started May 23 01:42:10 PM PDT 24
Finished May 23 01:42:54 PM PDT 24
Peak memory 211864 kb
Host smart-791b6e59-459b-47ac-9127-3e1088fa5575
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3062909411 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_tl_i
ntg_err.3062909411
Directory /workspace/17.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_mem_rw_with_rand_reset.2111598271
Short name T386
Test name
Test status
Simulation time 7478999784 ps
CPU time 15.59 seconds
Started May 23 01:42:11 PM PDT 24
Finished May 23 01:42:31 PM PDT 24
Peak memory 219588 kb
Host smart-07329a7d-39b7-48c4-8fc3-982055af3da8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2111598271 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 18.rom_ctrl_csr_mem_rw_with_rand_reset.2111598271
Directory /workspace/18.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_rw.1913268056
Short name T377
Test name
Test status
Simulation time 1038957949 ps
CPU time 10.5 seconds
Started May 23 01:42:11 PM PDT 24
Finished May 23 01:42:25 PM PDT 24
Peak memory 211284 kb
Host smart-bcfb113c-707c-48a8-8760-0f59d89cefde
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1913268056 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_csr_rw.1913268056
Directory /workspace/18.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_passthru_mem_tl_intg_err.4082733515
Short name T87
Test name
Test status
Simulation time 5657509873 ps
CPU time 51.76 seconds
Started May 23 01:42:10 PM PDT 24
Finished May 23 01:43:05 PM PDT 24
Peak memory 211404 kb
Host smart-ea6feff4-6323-43e9-a860-44767e8ceb15
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4082733515 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_p
assthru_mem_tl_intg_err.4082733515
Directory /workspace/18.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_same_csr_outstanding.802786876
Short name T404
Test name
Test status
Simulation time 2685975183 ps
CPU time 13.83 seconds
Started May 23 01:42:14 PM PDT 24
Finished May 23 01:42:32 PM PDT 24
Peak memory 211340 kb
Host smart-8510f449-b73b-4283-8d85-46984c0b4075
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=802786876 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_c
trl_same_csr_outstanding.802786876
Directory /workspace/18.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_errors.1148360892
Short name T372
Test name
Test status
Simulation time 703275828 ps
CPU time 8.58 seconds
Started May 23 01:42:10 PM PDT 24
Finished May 23 01:42:22 PM PDT 24
Peak memory 219568 kb
Host smart-8895656e-3d61-4f6e-bbb5-f8a771397fb2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1148360892 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_tl_errors.1148360892
Directory /workspace/18.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_intg_err.1744748931
Short name T104
Test name
Test status
Simulation time 1917371696 ps
CPU time 46.23 seconds
Started May 23 01:42:10 PM PDT 24
Finished May 23 01:42:59 PM PDT 24
Peak memory 211256 kb
Host smart-5e972cab-49a4-4075-9357-9562dc32a643
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1744748931 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_tl_i
ntg_err.1744748931
Directory /workspace/18.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_mem_rw_with_rand_reset.2814450263
Short name T438
Test name
Test status
Simulation time 8358621485 ps
CPU time 16.55 seconds
Started May 23 01:42:17 PM PDT 24
Finished May 23 01:42:36 PM PDT 24
Peak memory 219560 kb
Host smart-1d6b4771-a61f-46b8-bbe0-f096f9cd43e5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2814450263 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 19.rom_ctrl_csr_mem_rw_with_rand_reset.2814450263
Directory /workspace/19.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_rw.4107408770
Short name T63
Test name
Test status
Simulation time 1060741609 ps
CPU time 10.28 seconds
Started May 23 01:42:14 PM PDT 24
Finished May 23 01:42:28 PM PDT 24
Peak memory 211272 kb
Host smart-1772422d-afce-4951-acf2-101d1e456bc0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4107408770 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_csr_rw.4107408770
Directory /workspace/19.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_passthru_mem_tl_intg_err.3381398931
Short name T447
Test name
Test status
Simulation time 13674913587 ps
CPU time 54.57 seconds
Started May 23 01:42:15 PM PDT 24
Finished May 23 01:43:13 PM PDT 24
Peak memory 211388 kb
Host smart-3b24bdda-da5e-4b7d-92e8-b984ea4455f4
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3381398931 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_p
assthru_mem_tl_intg_err.3381398931
Directory /workspace/19.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_same_csr_outstanding.220244548
Short name T96
Test name
Test status
Simulation time 89138193 ps
CPU time 4.36 seconds
Started May 23 01:42:14 PM PDT 24
Finished May 23 01:42:22 PM PDT 24
Peak memory 211244 kb
Host smart-f970df3f-86a7-4ebc-9b30-292b3aeb7930
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=220244548 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_c
trl_same_csr_outstanding.220244548
Directory /workspace/19.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_errors.924142076
Short name T374
Test name
Test status
Simulation time 1794513639 ps
CPU time 13.05 seconds
Started May 23 01:42:16 PM PDT 24
Finished May 23 01:42:32 PM PDT 24
Peak memory 219544 kb
Host smart-452be598-b637-450f-af94-6ce1573cd791
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=924142076 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_tl_errors.924142076
Directory /workspace/19.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_aliasing.2580600198
Short name T444
Test name
Test status
Simulation time 256512936 ps
CPU time 5.08 seconds
Started May 23 01:42:02 PM PDT 24
Finished May 23 01:42:11 PM PDT 24
Peak memory 211316 kb
Host smart-73fe84da-6ee1-4678-a956-3b24b95822e5
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2580600198 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_alia
sing.2580600198
Directory /workspace/2.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_bit_bash.2954746700
Short name T459
Test name
Test status
Simulation time 2093446593 ps
CPU time 10.69 seconds
Started May 23 01:42:04 PM PDT 24
Finished May 23 01:42:19 PM PDT 24
Peak memory 211300 kb
Host smart-d4f946d1-f0ee-4663-bd66-eeabc1aebc9d
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2954746700 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_bit_
bash.2954746700
Directory /workspace/2.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_hw_reset.3018490001
Short name T410
Test name
Test status
Simulation time 517004833 ps
CPU time 9.2 seconds
Started May 23 01:41:58 PM PDT 24
Finished May 23 01:42:12 PM PDT 24
Peak memory 211308 kb
Host smart-174bddff-04d7-461d-abe6-3e2509232bff
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3018490001 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_hw_r
eset.3018490001
Directory /workspace/2.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_mem_rw_with_rand_reset.4199848964
Short name T392
Test name
Test status
Simulation time 1301915939 ps
CPU time 13.11 seconds
Started May 23 01:42:03 PM PDT 24
Finished May 23 01:42:21 PM PDT 24
Peak memory 219520 kb
Host smart-d207a83d-5134-489b-a946-6bf5a69f4941
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4199848964 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 2.rom_ctrl_csr_mem_rw_with_rand_reset.4199848964
Directory /workspace/2.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_partial_access.289059364
Short name T375
Test name
Test status
Simulation time 6644624155 ps
CPU time 13.57 seconds
Started May 23 01:42:02 PM PDT 24
Finished May 23 01:42:20 PM PDT 24
Peak memory 211232 kb
Host smart-638a487b-6857-4875-8f29-ac57a6b5f799
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=289059364 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl
_mem_partial_access.289059364
Directory /workspace/2.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_walk.3569610758
Short name T364
Test name
Test status
Simulation time 3823856817 ps
CPU time 8.15 seconds
Started May 23 01:42:02 PM PDT 24
Finished May 23 01:42:15 PM PDT 24
Peak memory 211300 kb
Host smart-f29b0284-decf-4331-8664-ab1bd0d97ced
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3569610758 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_mem_walk
.3569610758
Directory /workspace/2.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_passthru_mem_tl_intg_err.2729390446
Short name T64
Test name
Test status
Simulation time 6270265563 ps
CPU time 54.93 seconds
Started May 23 01:42:00 PM PDT 24
Finished May 23 01:42:59 PM PDT 24
Peak memory 211376 kb
Host smart-9324b692-096a-461e-9280-e4ed91941cfb
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2729390446 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_pa
ssthru_mem_tl_intg_err.2729390446
Directory /workspace/2.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_same_csr_outstanding.3005736147
Short name T420
Test name
Test status
Simulation time 6701732479 ps
CPU time 14.1 seconds
Started May 23 01:42:01 PM PDT 24
Finished May 23 01:42:19 PM PDT 24
Peak memory 211364 kb
Host smart-153f2ba9-315b-4fe5-a208-86b6bdb4f8eb
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3005736147 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_c
trl_same_csr_outstanding.3005736147
Directory /workspace/2.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_errors.3728719251
Short name T462
Test name
Test status
Simulation time 87545893 ps
CPU time 8.17 seconds
Started May 23 01:42:02 PM PDT 24
Finished May 23 01:42:15 PM PDT 24
Peak memory 215992 kb
Host smart-9d31c5d7-d63d-4817-af2c-4ac0c13c6f71
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3728719251 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_tl_errors.3728719251
Directory /workspace/2.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_intg_err.166364281
Short name T111
Test name
Test status
Simulation time 1713350015 ps
CPU time 70.89 seconds
Started May 23 01:41:59 PM PDT 24
Finished May 23 01:43:15 PM PDT 24
Peak memory 212192 kb
Host smart-6ca4b07c-c40f-4ffb-a5a8-9b708976e212
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=166364281 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_tl_int
g_err.166364281
Directory /workspace/2.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_aliasing.1321425354
Short name T68
Test name
Test status
Simulation time 3321955651 ps
CPU time 11.85 seconds
Started May 23 01:42:00 PM PDT 24
Finished May 23 01:42:16 PM PDT 24
Peak memory 211372 kb
Host smart-a7803359-ac2a-4bf9-ba98-23836af07b8d
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1321425354 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_alia
sing.1321425354
Directory /workspace/3.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_bit_bash.2371836839
Short name T440
Test name
Test status
Simulation time 2348738821 ps
CPU time 11.41 seconds
Started May 23 01:42:00 PM PDT 24
Finished May 23 01:42:16 PM PDT 24
Peak memory 211384 kb
Host smart-4fd6eda4-b9c2-4801-9022-c20b36b17874
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2371836839 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_bit_
bash.2371836839
Directory /workspace/3.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_hw_reset.1611171975
Short name T69
Test name
Test status
Simulation time 3376245433 ps
CPU time 17.28 seconds
Started May 23 01:42:05 PM PDT 24
Finished May 23 01:42:26 PM PDT 24
Peak memory 211400 kb
Host smart-c8bb7ad3-7c6b-49f5-a056-b46835f11a25
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1611171975 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_hw_r
eset.1611171975
Directory /workspace/3.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_mem_rw_with_rand_reset.3422511549
Short name T455
Test name
Test status
Simulation time 5938247224 ps
CPU time 13.14 seconds
Started May 23 01:42:05 PM PDT 24
Finished May 23 01:42:23 PM PDT 24
Peak memory 213312 kb
Host smart-b1d35595-b0c9-47a3-94b1-43065035ca69
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3422511549 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 3.rom_ctrl_csr_mem_rw_with_rand_reset.3422511549
Directory /workspace/3.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_rw.3673174099
Short name T385
Test name
Test status
Simulation time 8578558280 ps
CPU time 15.21 seconds
Started May 23 01:42:06 PM PDT 24
Finished May 23 01:42:25 PM PDT 24
Peak memory 211396 kb
Host smart-1f4a22a5-ed03-45b4-a381-c0a18f6c4a43
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3673174099 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_rw.3673174099
Directory /workspace/3.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_partial_access.832851774
Short name T402
Test name
Test status
Simulation time 2905222065 ps
CPU time 8.59 seconds
Started May 23 01:42:04 PM PDT 24
Finished May 23 01:42:17 PM PDT 24
Peak memory 211228 kb
Host smart-125f7cf5-a87b-46e0-9ee4-fc5d14332a9b
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=832851774 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl
_mem_partial_access.832851774
Directory /workspace/3.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_walk.3637122383
Short name T400
Test name
Test status
Simulation time 2448134549 ps
CPU time 16.41 seconds
Started May 23 01:42:01 PM PDT 24
Finished May 23 01:42:22 PM PDT 24
Peak memory 211280 kb
Host smart-2658b045-2805-4d7d-88f1-2db6904a4ad2
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3637122383 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_mem_walk
.3637122383
Directory /workspace/3.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_passthru_mem_tl_intg_err.225020816
Short name T432
Test name
Test status
Simulation time 9309542350 ps
CPU time 33.41 seconds
Started May 23 01:42:04 PM PDT 24
Finished May 23 01:42:41 PM PDT 24
Peak memory 211404 kb
Host smart-088c0ce2-b8ad-4011-be6e-b79a35d3b904
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=225020816 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_pas
sthru_mem_tl_intg_err.225020816
Directory /workspace/3.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_same_csr_outstanding.2965683284
Short name T73
Test name
Test status
Simulation time 1613476461 ps
CPU time 13.88 seconds
Started May 23 01:42:05 PM PDT 24
Finished May 23 01:42:23 PM PDT 24
Peak memory 211352 kb
Host smart-6fbb1c56-1270-4367-9e48-1ccbe8c44c94
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2965683284 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_c
trl_same_csr_outstanding.2965683284
Directory /workspace/3.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_errors.1029386115
Short name T367
Test name
Test status
Simulation time 165987223 ps
CPU time 10.49 seconds
Started May 23 01:42:00 PM PDT 24
Finished May 23 01:42:15 PM PDT 24
Peak memory 219568 kb
Host smart-01d4347e-77f6-4966-b183-c52b4546fce4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1029386115 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_tl_errors.1029386115
Directory /workspace/3.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_intg_err.3146813198
Short name T113
Test name
Test status
Simulation time 1255536441 ps
CPU time 38.15 seconds
Started May 23 01:42:01 PM PDT 24
Finished May 23 01:42:43 PM PDT 24
Peak memory 213196 kb
Host smart-ed1ac554-d8fc-4247-b86e-6669b6b90de8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3146813198 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_tl_in
tg_err.3146813198
Directory /workspace/3.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_aliasing.854787078
Short name T460
Test name
Test status
Simulation time 860046356 ps
CPU time 7.12 seconds
Started May 23 01:41:59 PM PDT 24
Finished May 23 01:42:11 PM PDT 24
Peak memory 211292 kb
Host smart-805b22fb-31be-48c6-ab57-da687f849661
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=854787078 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_alias
ing.854787078
Directory /workspace/4.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_bit_bash.3599692809
Short name T423
Test name
Test status
Simulation time 8142490338 ps
CPU time 15.96 seconds
Started May 23 01:41:58 PM PDT 24
Finished May 23 01:42:18 PM PDT 24
Peak memory 211384 kb
Host smart-20ffe179-a7f8-4020-9c96-9b9ed4eec421
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3599692809 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_bit_
bash.3599692809
Directory /workspace/4.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_hw_reset.1553142420
Short name T71
Test name
Test status
Simulation time 1555101733 ps
CPU time 16.37 seconds
Started May 23 01:42:00 PM PDT 24
Finished May 23 01:42:21 PM PDT 24
Peak memory 211316 kb
Host smart-391f22cf-371b-4cb4-a9e9-24b469121751
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1553142420 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_hw_r
eset.1553142420
Directory /workspace/4.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_mem_rw_with_rand_reset.561274941
Short name T439
Test name
Test status
Simulation time 6389589406 ps
CPU time 12.73 seconds
Started May 23 01:42:00 PM PDT 24
Finished May 23 01:42:18 PM PDT 24
Peak memory 219632 kb
Host smart-01c00b00-2bdb-4bd9-9366-983eb3d48194
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=561274941 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 4.rom_ctrl_csr_mem_rw_with_rand_reset.561274941
Directory /workspace/4.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_rw.3226668567
Short name T426
Test name
Test status
Simulation time 1119114430 ps
CPU time 11.17 seconds
Started May 23 01:42:01 PM PDT 24
Finished May 23 01:42:17 PM PDT 24
Peak memory 211288 kb
Host smart-adcd70c6-2b0d-4473-b68d-1a4ba5092ab8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3226668567 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_rw.3226668567
Directory /workspace/4.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_partial_access.2892728112
Short name T406
Test name
Test status
Simulation time 1443430663 ps
CPU time 12.21 seconds
Started May 23 01:42:02 PM PDT 24
Finished May 23 01:42:19 PM PDT 24
Peak memory 211196 kb
Host smart-2193422e-5c3a-4b80-8865-d826a86ed2e2
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2892728112 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctr
l_mem_partial_access.2892728112
Directory /workspace/4.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_walk.3915545838
Short name T412
Test name
Test status
Simulation time 1034722372 ps
CPU time 10.23 seconds
Started May 23 01:42:01 PM PDT 24
Finished May 23 01:42:16 PM PDT 24
Peak memory 211260 kb
Host smart-635ea025-609f-49d0-b1ad-a85ceed1d343
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3915545838 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_mem_walk
.3915545838
Directory /workspace/4.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_passthru_mem_tl_intg_err.927926810
Short name T76
Test name
Test status
Simulation time 94857157708 ps
CPU time 60.61 seconds
Started May 23 01:41:59 PM PDT 24
Finished May 23 01:43:04 PM PDT 24
Peak memory 211368 kb
Host smart-2456d758-5253-47c1-b5f1-455ab14d05ba
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=927926810 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_pas
sthru_mem_tl_intg_err.927926810
Directory /workspace/4.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_same_csr_outstanding.1491775735
Short name T391
Test name
Test status
Simulation time 454671175 ps
CPU time 7.13 seconds
Started May 23 01:41:57 PM PDT 24
Finished May 23 01:42:08 PM PDT 24
Peak memory 211296 kb
Host smart-6b82b1fb-9680-43f0-82f3-ce7c5d76f178
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1491775735 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_c
trl_same_csr_outstanding.1491775735
Directory /workspace/4.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_errors.3857628937
Short name T450
Test name
Test status
Simulation time 7181802828 ps
CPU time 13.66 seconds
Started May 23 01:42:02 PM PDT 24
Finished May 23 01:42:20 PM PDT 24
Peak memory 215712 kb
Host smart-9783ffef-7a34-4e2a-8239-dd7422fd5eef
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3857628937 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_tl_errors.3857628937
Directory /workspace/4.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_intg_err.3745323797
Short name T60
Test name
Test status
Simulation time 1050594703 ps
CPU time 40.85 seconds
Started May 23 01:42:05 PM PDT 24
Finished May 23 01:42:50 PM PDT 24
Peak memory 211908 kb
Host smart-d378c59d-e746-4d00-ab2c-6246007b2c5b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3745323797 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_tl_in
tg_err.3745323797
Directory /workspace/4.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_mem_rw_with_rand_reset.3366749338
Short name T388
Test name
Test status
Simulation time 3476289853 ps
CPU time 10.04 seconds
Started May 23 01:42:01 PM PDT 24
Finished May 23 01:42:15 PM PDT 24
Peak memory 214092 kb
Host smart-777bf780-a662-4e6d-9691-23b85d70aff0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3366749338 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 5.rom_ctrl_csr_mem_rw_with_rand_reset.3366749338
Directory /workspace/5.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_rw.2576454510
Short name T70
Test name
Test status
Simulation time 5354082383 ps
CPU time 12.05 seconds
Started May 23 01:42:00 PM PDT 24
Finished May 23 01:42:17 PM PDT 24
Peak memory 211428 kb
Host smart-7cb69eea-c322-434b-a3f9-42bbd58f0727
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2576454510 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_csr_rw.2576454510
Directory /workspace/5.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_passthru_mem_tl_intg_err.2305209407
Short name T433
Test name
Test status
Simulation time 20298812616 ps
CPU time 59.68 seconds
Started May 23 01:42:00 PM PDT 24
Finished May 23 01:43:04 PM PDT 24
Peak memory 211416 kb
Host smart-a94135e3-5155-4681-9ef0-541f0716a8be
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2305209407 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_pa
ssthru_mem_tl_intg_err.2305209407
Directory /workspace/5.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_same_csr_outstanding.3604988490
Short name T74
Test name
Test status
Simulation time 363395727 ps
CPU time 6.17 seconds
Started May 23 01:41:59 PM PDT 24
Finished May 23 01:42:10 PM PDT 24
Peak memory 211280 kb
Host smart-b36896a8-6563-4e48-8f5c-3bdfb3ca093d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3604988490 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_c
trl_same_csr_outstanding.3604988490
Directory /workspace/5.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_errors.3808772421
Short name T376
Test name
Test status
Simulation time 1805715836 ps
CPU time 13.32 seconds
Started May 23 01:42:02 PM PDT 24
Finished May 23 01:42:20 PM PDT 24
Peak memory 219552 kb
Host smart-62bb35ff-e3df-4b54-8748-742273bf0dd4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3808772421 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_tl_errors.3808772421
Directory /workspace/5.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_intg_err.1424329057
Short name T454
Test name
Test status
Simulation time 3220710010 ps
CPU time 44.37 seconds
Started May 23 01:42:00 PM PDT 24
Finished May 23 01:42:49 PM PDT 24
Peak memory 213276 kb
Host smart-4a1fdc57-b872-4f88-a429-5977f6919952
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1424329057 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_tl_in
tg_err.1424329057
Directory /workspace/5.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_mem_rw_with_rand_reset.471287801
Short name T396
Test name
Test status
Simulation time 13308842557 ps
CPU time 14.96 seconds
Started May 23 01:42:02 PM PDT 24
Finished May 23 01:42:21 PM PDT 24
Peak memory 219612 kb
Host smart-61371f2c-6ebb-4c5f-b073-ad905e0a6d56
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=471287801 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 6.rom_ctrl_csr_mem_rw_with_rand_reset.471287801
Directory /workspace/6.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_rw.3682804327
Short name T408
Test name
Test status
Simulation time 2598552071 ps
CPU time 8.46 seconds
Started May 23 01:41:59 PM PDT 24
Finished May 23 01:42:11 PM PDT 24
Peak memory 211300 kb
Host smart-8ea41206-b277-4223-bcbb-2a23ece25bed
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3682804327 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_csr_rw.3682804327
Directory /workspace/6.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_passthru_mem_tl_intg_err.3328566748
Short name T89
Test name
Test status
Simulation time 2111959728 ps
CPU time 18.31 seconds
Started May 23 01:42:02 PM PDT 24
Finished May 23 01:42:25 PM PDT 24
Peak memory 211324 kb
Host smart-8d0547dd-7c42-4866-a212-0ffb634b59e0
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3328566748 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_pa
ssthru_mem_tl_intg_err.3328566748
Directory /workspace/6.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_same_csr_outstanding.2658796917
Short name T399
Test name
Test status
Simulation time 85484555 ps
CPU time 4.31 seconds
Started May 23 01:42:04 PM PDT 24
Finished May 23 01:42:13 PM PDT 24
Peak memory 211296 kb
Host smart-16e4b68c-530f-492e-9b21-6b9d4460d589
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2658796917 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_c
trl_same_csr_outstanding.2658796917
Directory /workspace/6.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_errors.3385533453
Short name T365
Test name
Test status
Simulation time 2042668760 ps
CPU time 13.92 seconds
Started May 23 01:42:01 PM PDT 24
Finished May 23 01:42:20 PM PDT 24
Peak memory 219532 kb
Host smart-16e2083e-10e2-4a94-b078-e0c8c79ac18d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3385533453 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_tl_errors.3385533453
Directory /workspace/6.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_intg_err.3212340714
Short name T108
Test name
Test status
Simulation time 352556683 ps
CPU time 68.49 seconds
Started May 23 01:42:01 PM PDT 24
Finished May 23 01:43:14 PM PDT 24
Peak memory 212156 kb
Host smart-5de03325-0648-428a-9994-641cd29e0889
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3212340714 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_tl_in
tg_err.3212340714
Directory /workspace/6.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_mem_rw_with_rand_reset.1492565924
Short name T458
Test name
Test status
Simulation time 1632541680 ps
CPU time 13.81 seconds
Started May 23 01:42:03 PM PDT 24
Finished May 23 01:42:21 PM PDT 24
Peak memory 219532 kb
Host smart-b21b88d4-6ee0-4154-9f51-9595b504a694
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1492565924 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 7.rom_ctrl_csr_mem_rw_with_rand_reset.1492565924
Directory /workspace/7.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_rw.3494936267
Short name T446
Test name
Test status
Simulation time 412739265 ps
CPU time 5.59 seconds
Started May 23 01:42:05 PM PDT 24
Finished May 23 01:42:15 PM PDT 24
Peak memory 211300 kb
Host smart-3c6428fc-9eac-4c67-9c10-c60cf0e4999e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3494936267 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_csr_rw.3494936267
Directory /workspace/7.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_passthru_mem_tl_intg_err.2792878367
Short name T383
Test name
Test status
Simulation time 4224467324 ps
CPU time 43.76 seconds
Started May 23 01:42:04 PM PDT 24
Finished May 23 01:42:53 PM PDT 24
Peak memory 211384 kb
Host smart-e405538f-107c-450b-88c1-f3c0e26da8b7
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2792878367 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_pa
ssthru_mem_tl_intg_err.2792878367
Directory /workspace/7.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_same_csr_outstanding.3239679035
Short name T421
Test name
Test status
Simulation time 429286731 ps
CPU time 7.04 seconds
Started May 23 01:42:02 PM PDT 24
Finished May 23 01:42:14 PM PDT 24
Peak memory 211304 kb
Host smart-64b07911-0900-4faa-93b9-0ccba7cbeef5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3239679035 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_c
trl_same_csr_outstanding.3239679035
Directory /workspace/7.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_errors.705851808
Short name T403
Test name
Test status
Simulation time 3078823135 ps
CPU time 13.88 seconds
Started May 23 01:42:02 PM PDT 24
Finished May 23 01:42:20 PM PDT 24
Peak memory 215900 kb
Host smart-6123aa2e-fb14-4af2-ba4b-b9de5a642ae0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=705851808 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_tl_errors.705851808
Directory /workspace/7.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_intg_err.3011277695
Short name T109
Test name
Test status
Simulation time 3794354414 ps
CPU time 46.39 seconds
Started May 23 01:42:04 PM PDT 24
Finished May 23 01:42:54 PM PDT 24
Peak memory 212244 kb
Host smart-3076c73b-9f88-43dd-8fe6-a423b53b0f07
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3011277695 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_tl_in
tg_err.3011277695
Directory /workspace/7.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_mem_rw_with_rand_reset.2621231693
Short name T387
Test name
Test status
Simulation time 95020935 ps
CPU time 5.01 seconds
Started May 23 01:42:00 PM PDT 24
Finished May 23 01:42:10 PM PDT 24
Peak memory 219544 kb
Host smart-66e9ca8e-3e76-46ee-841e-a1fdc97b51c6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2621231693 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 8.rom_ctrl_csr_mem_rw_with_rand_reset.2621231693
Directory /workspace/8.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_rw.938175754
Short name T430
Test name
Test status
Simulation time 395807377 ps
CPU time 4.18 seconds
Started May 23 01:42:02 PM PDT 24
Finished May 23 01:42:11 PM PDT 24
Peak memory 211312 kb
Host smart-98a31ae0-1814-4946-a3a4-35582b1e2138
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=938175754 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_csr_rw.938175754
Directory /workspace/8.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_passthru_mem_tl_intg_err.1262477629
Short name T390
Test name
Test status
Simulation time 376989728 ps
CPU time 18.57 seconds
Started May 23 01:42:03 PM PDT 24
Finished May 23 01:42:25 PM PDT 24
Peak memory 211360 kb
Host smart-96918b16-18f8-4ceb-85d4-311a5a577427
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1262477629 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_pa
ssthru_mem_tl_intg_err.1262477629
Directory /workspace/8.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_same_csr_outstanding.526762027
Short name T75
Test name
Test status
Simulation time 8077569984 ps
CPU time 15.8 seconds
Started May 23 01:42:05 PM PDT 24
Finished May 23 01:42:25 PM PDT 24
Peak memory 211392 kb
Host smart-0ddafe0f-91dd-4eef-96b4-38a68494e1dc
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=526762027 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ct
rl_same_csr_outstanding.526762027
Directory /workspace/8.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_errors.1803529404
Short name T378
Test name
Test status
Simulation time 2470885435 ps
CPU time 18.67 seconds
Started May 23 01:42:03 PM PDT 24
Finished May 23 01:42:26 PM PDT 24
Peak memory 219592 kb
Host smart-24239903-edf0-4439-8b4c-a9b66bf011fe
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1803529404 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_tl_errors.1803529404
Directory /workspace/8.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_intg_err.4176608499
Short name T424
Test name
Test status
Simulation time 287278759 ps
CPU time 69.14 seconds
Started May 23 01:42:03 PM PDT 24
Finished May 23 01:43:17 PM PDT 24
Peak memory 212388 kb
Host smart-30c2eef3-aaea-4fc2-8469-8a95ef6c77f7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4176608499 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_tl_in
tg_err.4176608499
Directory /workspace/8.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_mem_rw_with_rand_reset.496071585
Short name T368
Test name
Test status
Simulation time 2770584357 ps
CPU time 11.44 seconds
Started May 23 01:42:00 PM PDT 24
Finished May 23 01:42:16 PM PDT 24
Peak memory 219632 kb
Host smart-d17f8f8c-25fb-41d7-9ab5-6f7c15936d58
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=496071585 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 9.rom_ctrl_csr_mem_rw_with_rand_reset.496071585
Directory /workspace/9.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_rw.1808847607
Short name T86
Test name
Test status
Simulation time 1098687698 ps
CPU time 10.65 seconds
Started May 23 01:42:02 PM PDT 24
Finished May 23 01:42:17 PM PDT 24
Peak memory 211300 kb
Host smart-567f9da9-3957-41d1-8bbb-fb1d4193f31e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1808847607 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_csr_rw.1808847607
Directory /workspace/9.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_passthru_mem_tl_intg_err.2472537776
Short name T85
Test name
Test status
Simulation time 72156492853 ps
CPU time 76.88 seconds
Started May 23 01:42:02 PM PDT 24
Finished May 23 01:43:23 PM PDT 24
Peak memory 211384 kb
Host smart-e245e31a-ea5c-4782-88d4-fb29fa6802c4
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2472537776 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_pa
ssthru_mem_tl_intg_err.2472537776
Directory /workspace/9.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_same_csr_outstanding.3966154563
Short name T456
Test name
Test status
Simulation time 1380928704 ps
CPU time 13.69 seconds
Started May 23 01:42:04 PM PDT 24
Finished May 23 01:42:23 PM PDT 24
Peak memory 211304 kb
Host smart-400f1cbb-4b7f-4409-870b-164d6a13f1b3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3966154563 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_c
trl_same_csr_outstanding.3966154563
Directory /workspace/9.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_errors.1330480061
Short name T102
Test name
Test status
Simulation time 786563535 ps
CPU time 9.7 seconds
Started May 23 01:42:02 PM PDT 24
Finished May 23 01:42:16 PM PDT 24
Peak memory 219572 kb
Host smart-ec34bdc2-7077-48a8-91cc-03c9e925dd18
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1330480061 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_tl_errors.1330480061
Directory /workspace/9.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_intg_err.766974961
Short name T107
Test name
Test status
Simulation time 310186606 ps
CPU time 36.17 seconds
Started May 23 01:42:00 PM PDT 24
Finished May 23 01:42:40 PM PDT 24
Peak memory 211284 kb
Host smart-de3e1d14-8d32-4ad1-9ef2-d8eaf80c1ef1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=766974961 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_tl_int
g_err.766974961
Directory /workspace/9.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/0.rom_ctrl_alert_test.2764563271
Short name T66
Test name
Test status
Simulation time 85637109 ps
CPU time 4.36 seconds
Started May 23 01:42:21 PM PDT 24
Finished May 23 01:42:28 PM PDT 24
Peak memory 210916 kb
Host smart-96434fcf-d0dc-494e-9fd3-24fb1ba3a258
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2764563271 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_alert_test.2764563271
Directory /workspace/0.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/0.rom_ctrl_corrupt_sig_fatal_chk.685358213
Short name T51
Test name
Test status
Simulation time 74426234174 ps
CPU time 189.9 seconds
Started May 23 01:42:16 PM PDT 24
Finished May 23 01:45:29 PM PDT 24
Peak memory 230832 kb
Host smart-f43814d9-8702-435a-adcd-716cad820010
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=685358213 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_co
rrupt_sig_fatal_chk.685358213
Directory /workspace/0.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/0.rom_ctrl_kmac_err_chk.1385758507
Short name T347
Test name
Test status
Simulation time 177218968 ps
CPU time 9.5 seconds
Started May 23 01:42:17 PM PDT 24
Finished May 23 01:42:29 PM PDT 24
Peak memory 211996 kb
Host smart-ebb73ced-77b6-439d-b81f-72d190ce9e40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1385758507 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_kmac_err_chk.1385758507
Directory /workspace/0.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/0.rom_ctrl_max_throughput_chk.299111998
Short name T132
Test name
Test status
Simulation time 2266407181 ps
CPU time 8.72 seconds
Started May 23 01:42:17 PM PDT 24
Finished May 23 01:42:28 PM PDT 24
Peak memory 211156 kb
Host smart-da955142-ce34-497b-bf5b-ce58ea9527ac
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=299111998 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_max_throughput_chk.299111998
Directory /workspace/0.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/0.rom_ctrl_smoke.4259685501
Short name T153
Test name
Test status
Simulation time 7666483244 ps
CPU time 22.99 seconds
Started May 23 01:42:16 PM PDT 24
Finished May 23 01:42:42 PM PDT 24
Peak memory 219388 kb
Host smart-7a4a96c4-7eb7-4ef8-8492-a8fc1fe5f1b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4259685501 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_smoke.4259685501
Directory /workspace/0.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/0.rom_ctrl_stress_all.2653127382
Short name T313
Test name
Test status
Simulation time 6399747753 ps
CPU time 22.86 seconds
Started May 23 01:42:15 PM PDT 24
Finished May 23 01:42:41 PM PDT 24
Peak memory 212380 kb
Host smart-a02d0d9b-9c76-4478-978d-c34906c837bf
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2653127382 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 0.rom_ctrl_stress_all.2653127382
Directory /workspace/0.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/0.rom_ctrl_stress_all_with_rand_reset.1793399140
Short name T16
Test name
Test status
Simulation time 13721384996 ps
CPU time 39.03 seconds
Started May 23 01:42:21 PM PDT 24
Finished May 23 01:43:03 PM PDT 24
Peak memory 221136 kb
Host smart-d48442c7-c174-4d0d-ba67-fdfe3ed5dcbd
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1793399140 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_stress_all_with_rand_reset.1793399140
Directory /workspace/0.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.rom_ctrl_alert_test.239877875
Short name T233
Test name
Test status
Simulation time 1168737939 ps
CPU time 11.54 seconds
Started May 23 01:42:10 PM PDT 24
Finished May 23 01:42:24 PM PDT 24
Peak memory 211264 kb
Host smart-882b86ce-550d-43ee-8111-074ea386a4a2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=239877875 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_alert_test.239877875
Directory /workspace/1.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/1.rom_ctrl_kmac_err_chk.3961942185
Short name T226
Test name
Test status
Simulation time 1660597777 ps
CPU time 9.51 seconds
Started May 23 01:42:21 PM PDT 24
Finished May 23 01:42:32 PM PDT 24
Peak memory 211888 kb
Host smart-72c5c8fb-ac32-446e-b4ac-788a5b645549
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3961942185 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_kmac_err_chk.3961942185
Directory /workspace/1.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/1.rom_ctrl_max_throughput_chk.482191118
Short name T192
Test name
Test status
Simulation time 374907732 ps
CPU time 5.76 seconds
Started May 23 01:42:21 PM PDT 24
Finished May 23 01:42:29 PM PDT 24
Peak memory 211092 kb
Host smart-478fecfb-6d7f-4b76-beaf-9ee5f4f921a2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=482191118 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_max_throughput_chk.482191118
Directory /workspace/1.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/1.rom_ctrl_sec_cm.551942843
Short name T30
Test name
Test status
Simulation time 1284102850 ps
CPU time 58.84 seconds
Started May 23 01:42:21 PM PDT 24
Finished May 23 01:43:22 PM PDT 24
Peak memory 235828 kb
Host smart-32f98388-1c12-452b-a252-4e44f1ba8c9e
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=551942843 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_sec_cm.551942843
Directory /workspace/1.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/1.rom_ctrl_smoke.1934851373
Short name T156
Test name
Test status
Simulation time 2949929029 ps
CPU time 28.73 seconds
Started May 23 01:42:14 PM PDT 24
Finished May 23 01:42:46 PM PDT 24
Peak memory 219456 kb
Host smart-f08f32f7-a47a-428a-ba19-9600e63b72ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1934851373 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_smoke.1934851373
Directory /workspace/1.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/1.rom_ctrl_stress_all.1962081724
Short name T266
Test name
Test status
Simulation time 23134554484 ps
CPU time 48.45 seconds
Started May 23 01:42:21 PM PDT 24
Finished May 23 01:43:11 PM PDT 24
Peak memory 219420 kb
Host smart-1a7b4144-96be-4d0e-88b2-b0fdc41f19e9
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1962081724 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 1.rom_ctrl_stress_all.1962081724
Directory /workspace/1.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/1.rom_ctrl_stress_all_with_rand_reset.3531857578
Short name T54
Test name
Test status
Simulation time 10182346826 ps
CPU time 386.84 seconds
Started May 23 01:42:21 PM PDT 24
Finished May 23 01:48:50 PM PDT 24
Peak memory 231792 kb
Host smart-1781f467-6cf1-4fd3-80ca-f5d96859ecb4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3531857578 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_stress_all_with_rand_reset.3531857578
Directory /workspace/1.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.rom_ctrl_alert_test.3608090913
Short name T303
Test name
Test status
Simulation time 347353978 ps
CPU time 4.3 seconds
Started May 23 01:42:29 PM PDT 24
Finished May 23 01:42:35 PM PDT 24
Peak memory 211252 kb
Host smart-a4383062-d5c3-45a6-bd33-e1d2ef563d2c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3608090913 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_alert_test.3608090913
Directory /workspace/10.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/10.rom_ctrl_corrupt_sig_fatal_chk.796274954
Short name T287
Test name
Test status
Simulation time 301911530863 ps
CPU time 353.48 seconds
Started May 23 01:42:33 PM PDT 24
Finished May 23 01:48:28 PM PDT 24
Peak memory 229800 kb
Host smart-8176fae7-4c8a-406b-8ec8-737d281ce354
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=796274954 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_c
orrupt_sig_fatal_chk.796274954
Directory /workspace/10.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/10.rom_ctrl_kmac_err_chk.2261147613
Short name T295
Test name
Test status
Simulation time 11605508608 ps
CPU time 33.25 seconds
Started May 23 01:42:31 PM PDT 24
Finished May 23 01:43:06 PM PDT 24
Peak memory 212228 kb
Host smart-d8fd2c53-3829-4583-b8a8-7a101b38daf8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2261147613 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_kmac_err_chk.2261147613
Directory /workspace/10.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/10.rom_ctrl_max_throughput_chk.3905084637
Short name T275
Test name
Test status
Simulation time 1882425608 ps
CPU time 5.83 seconds
Started May 23 01:42:31 PM PDT 24
Finished May 23 01:42:39 PM PDT 24
Peak memory 211060 kb
Host smart-c053fccb-b9cc-482b-8092-d2a2b52f394e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3905084637 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_max_throughput_chk.3905084637
Directory /workspace/10.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/10.rom_ctrl_smoke.1185398225
Short name T290
Test name
Test status
Simulation time 191380838 ps
CPU time 10.4 seconds
Started May 23 01:42:30 PM PDT 24
Finished May 23 01:42:42 PM PDT 24
Peak memory 212776 kb
Host smart-bfd24807-4268-44a7-87f9-e6636083c81d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1185398225 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_smoke.1185398225
Directory /workspace/10.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/10.rom_ctrl_stress_all.1404707483
Short name T79
Test name
Test status
Simulation time 6473593679 ps
CPU time 57.34 seconds
Started May 23 01:42:30 PM PDT 24
Finished May 23 01:43:29 PM PDT 24
Peak memory 216220 kb
Host smart-90c4ab55-0925-4af7-961a-e5bcc0881ff2
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1404707483 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 10.rom_ctrl_stress_all.1404707483
Directory /workspace/10.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/11.rom_ctrl_alert_test.3269743522
Short name T154
Test name
Test status
Simulation time 378057143 ps
CPU time 4.19 seconds
Started May 23 01:42:45 PM PDT 24
Finished May 23 01:42:50 PM PDT 24
Peak memory 211220 kb
Host smart-d4281450-4c6b-4681-bfab-d0c39dd4aefb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3269743522 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_alert_test.3269743522
Directory /workspace/11.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/11.rom_ctrl_corrupt_sig_fatal_chk.2558485898
Short name T167
Test name
Test status
Simulation time 228764431035 ps
CPU time 533.22 seconds
Started May 23 01:42:30 PM PDT 24
Finished May 23 01:51:24 PM PDT 24
Peak memory 234984 kb
Host smart-096d819d-f45c-45f5-8e48-d5ece987155c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2558485898 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_
corrupt_sig_fatal_chk.2558485898
Directory /workspace/11.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/11.rom_ctrl_max_throughput_chk.3607983151
Short name T191
Test name
Test status
Simulation time 369828777 ps
CPU time 5.17 seconds
Started May 23 01:42:32 PM PDT 24
Finished May 23 01:42:39 PM PDT 24
Peak memory 211092 kb
Host smart-060002be-7af2-40d4-a0f5-00a5a7e9a33c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3607983151 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_max_throughput_chk.3607983151
Directory /workspace/11.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/11.rom_ctrl_smoke.982004475
Short name T210
Test name
Test status
Simulation time 3609414209 ps
CPU time 24.59 seconds
Started May 23 01:42:29 PM PDT 24
Finished May 23 01:42:55 PM PDT 24
Peak memory 213072 kb
Host smart-638aafeb-a5db-4ceb-b32f-4f2da4f98cd9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=982004475 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_smoke.982004475
Directory /workspace/11.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/11.rom_ctrl_stress_all.2283866408
Short name T177
Test name
Test status
Simulation time 1595185769 ps
CPU time 18.6 seconds
Started May 23 01:42:32 PM PDT 24
Finished May 23 01:42:52 PM PDT 24
Peak memory 219300 kb
Host smart-0edee597-3ad2-4e63-a455-40fdbe6e2c82
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2283866408 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 11.rom_ctrl_stress_all.2283866408
Directory /workspace/11.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/12.rom_ctrl_alert_test.4040292793
Short name T235
Test name
Test status
Simulation time 1476837550 ps
CPU time 12.98 seconds
Started May 23 01:42:39 PM PDT 24
Finished May 23 01:42:53 PM PDT 24
Peak memory 211184 kb
Host smart-07d9acfb-bb91-4883-9e78-f23af9707545
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4040292793 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_alert_test.4040292793
Directory /workspace/12.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/12.rom_ctrl_corrupt_sig_fatal_chk.3432005268
Short name T276
Test name
Test status
Simulation time 73921546584 ps
CPU time 479.5 seconds
Started May 23 01:42:38 PM PDT 24
Finished May 23 01:50:39 PM PDT 24
Peak memory 228212 kb
Host smart-1f4a2218-82cf-4b18-b306-a0f0787029f2
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3432005268 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_
corrupt_sig_fatal_chk.3432005268
Directory /workspace/12.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/12.rom_ctrl_kmac_err_chk.2213411492
Short name T256
Test name
Test status
Simulation time 11596339626 ps
CPU time 26.29 seconds
Started May 23 01:42:40 PM PDT 24
Finished May 23 01:43:07 PM PDT 24
Peak memory 217900 kb
Host smart-00f23768-5a4b-454d-a2cd-1a0176666ab0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2213411492 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_kmac_err_chk.2213411492
Directory /workspace/12.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/12.rom_ctrl_max_throughput_chk.2225525701
Short name T181
Test name
Test status
Simulation time 1820221156 ps
CPU time 15.26 seconds
Started May 23 01:42:36 PM PDT 24
Finished May 23 01:42:52 PM PDT 24
Peak memory 211112 kb
Host smart-22c36667-32eb-4cc0-b64f-1992733efa7a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2225525701 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_max_throughput_chk.2225525701
Directory /workspace/12.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/12.rom_ctrl_smoke.78966923
Short name T349
Test name
Test status
Simulation time 717648081 ps
CPU time 10.26 seconds
Started May 23 01:42:39 PM PDT 24
Finished May 23 01:42:50 PM PDT 24
Peak memory 213568 kb
Host smart-5bbac4e3-138f-4f01-a550-8fc5184d50da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=78966923 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_smoke.78966923
Directory /workspace/12.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/12.rom_ctrl_stress_all.4202295976
Short name T142
Test name
Test status
Simulation time 5341445012 ps
CPU time 47.91 seconds
Started May 23 01:42:43 PM PDT 24
Finished May 23 01:43:32 PM PDT 24
Peak memory 216704 kb
Host smart-451714db-0b10-4824-87d1-a34b3f224fc7
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4202295976 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 12.rom_ctrl_stress_all.4202295976
Directory /workspace/12.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/13.rom_ctrl_alert_test.3871872473
Short name T249
Test name
Test status
Simulation time 1848250507 ps
CPU time 14.81 seconds
Started May 23 01:42:41 PM PDT 24
Finished May 23 01:42:57 PM PDT 24
Peak memory 211204 kb
Host smart-2fd399a0-ed6c-4c5e-aa76-907427f33136
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3871872473 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_alert_test.3871872473
Directory /workspace/13.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/13.rom_ctrl_corrupt_sig_fatal_chk.1447919137
Short name T333
Test name
Test status
Simulation time 46158091902 ps
CPU time 219.23 seconds
Started May 23 01:42:40 PM PDT 24
Finished May 23 01:46:20 PM PDT 24
Peak memory 232912 kb
Host smart-7c602790-b83b-4631-98d2-3fc53746b3f3
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1447919137 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_
corrupt_sig_fatal_chk.1447919137
Directory /workspace/13.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/13.rom_ctrl_kmac_err_chk.3126076429
Short name T282
Test name
Test status
Simulation time 14600693433 ps
CPU time 31.73 seconds
Started May 23 01:42:39 PM PDT 24
Finished May 23 01:43:12 PM PDT 24
Peak memory 212552 kb
Host smart-cd7a62c4-56ab-4fbe-bf10-572b664fc686
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3126076429 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_kmac_err_chk.3126076429
Directory /workspace/13.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/13.rom_ctrl_max_throughput_chk.3758171757
Short name T331
Test name
Test status
Simulation time 189916283 ps
CPU time 5.64 seconds
Started May 23 01:42:39 PM PDT 24
Finished May 23 01:42:46 PM PDT 24
Peak memory 211060 kb
Host smart-0f6911a1-e594-44d3-b7bb-0d2c59756cb2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3758171757 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_max_throughput_chk.3758171757
Directory /workspace/13.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/13.rom_ctrl_smoke.898735690
Short name T162
Test name
Test status
Simulation time 1283448176 ps
CPU time 10.05 seconds
Started May 23 01:42:42 PM PDT 24
Finished May 23 01:42:53 PM PDT 24
Peak memory 219328 kb
Host smart-abb3e0dc-5213-4bd7-a5be-5bd7a3da85f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=898735690 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_smoke.898735690
Directory /workspace/13.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/13.rom_ctrl_stress_all.1038606431
Short name T334
Test name
Test status
Simulation time 35118849354 ps
CPU time 61.05 seconds
Started May 23 01:42:38 PM PDT 24
Finished May 23 01:43:40 PM PDT 24
Peak memory 219420 kb
Host smart-73e55ddc-be70-4d00-97d9-5fc01d93fae1
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1038606431 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 13.rom_ctrl_stress_all.1038606431
Directory /workspace/13.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/14.rom_ctrl_alert_test.3923466016
Short name T294
Test name
Test status
Simulation time 2433566705 ps
CPU time 11.67 seconds
Started May 23 01:42:39 PM PDT 24
Finished May 23 01:42:52 PM PDT 24
Peak memory 211344 kb
Host smart-4424b20e-2af9-4124-b2be-31769a361a6c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3923466016 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_alert_test.3923466016
Directory /workspace/14.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/14.rom_ctrl_corrupt_sig_fatal_chk.3370357203
Short name T335
Test name
Test status
Simulation time 27515221289 ps
CPU time 285.08 seconds
Started May 23 01:42:40 PM PDT 24
Finished May 23 01:47:27 PM PDT 24
Peak memory 233828 kb
Host smart-eeff23b5-53f2-444d-ad31-7e5a25a56f04
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3370357203 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_
corrupt_sig_fatal_chk.3370357203
Directory /workspace/14.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/14.rom_ctrl_kmac_err_chk.381324352
Short name T8
Test name
Test status
Simulation time 170028808 ps
CPU time 9.45 seconds
Started May 23 01:42:38 PM PDT 24
Finished May 23 01:42:49 PM PDT 24
Peak memory 211756 kb
Host smart-d7c5dcc8-1635-4c40-b066-92a4fda4e299
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=381324352 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_kmac_err_chk.381324352
Directory /workspace/14.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/14.rom_ctrl_max_throughput_chk.1029783382
Short name T305
Test name
Test status
Simulation time 99096991 ps
CPU time 5.54 seconds
Started May 23 01:42:42 PM PDT 24
Finished May 23 01:42:49 PM PDT 24
Peak memory 211092 kb
Host smart-3d594587-7580-4bca-819e-301ae4e1918d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1029783382 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_max_throughput_chk.1029783382
Directory /workspace/14.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/14.rom_ctrl_smoke.3634673179
Short name T222
Test name
Test status
Simulation time 2792028622 ps
CPU time 24.12 seconds
Started May 23 01:42:37 PM PDT 24
Finished May 23 01:43:03 PM PDT 24
Peak memory 219408 kb
Host smart-94279f92-754e-4885-ab16-3f9a803fd168
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3634673179 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_smoke.3634673179
Directory /workspace/14.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/14.rom_ctrl_stress_all_with_rand_reset.1034647208
Short name T55
Test name
Test status
Simulation time 104758124707 ps
CPU time 2066.21 seconds
Started May 23 01:42:38 PM PDT 24
Finished May 23 02:17:06 PM PDT 24
Peak memory 235716 kb
Host smart-2ba80e07-7307-46ef-a649-624737ccb763
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1034647208 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_stress_all_with_rand_reset.1034647208
Directory /workspace/14.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/15.rom_ctrl_alert_test.2748422560
Short name T362
Test name
Test status
Simulation time 579455637 ps
CPU time 7.91 seconds
Started May 23 01:42:41 PM PDT 24
Finished May 23 01:42:50 PM PDT 24
Peak memory 211260 kb
Host smart-c3d59503-c2db-45f6-b0e5-b346d965d1a1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2748422560 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_alert_test.2748422560
Directory /workspace/15.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/15.rom_ctrl_corrupt_sig_fatal_chk.357913903
Short name T219
Test name
Test status
Simulation time 3754636728 ps
CPU time 87.32 seconds
Started May 23 01:42:38 PM PDT 24
Finished May 23 01:44:07 PM PDT 24
Peak memory 239144 kb
Host smart-05a808da-76b4-4046-bdad-cebe646e9dbe
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=357913903 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_c
orrupt_sig_fatal_chk.357913903
Directory /workspace/15.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/15.rom_ctrl_kmac_err_chk.3642749748
Short name T125
Test name
Test status
Simulation time 175357603 ps
CPU time 9.44 seconds
Started May 23 01:42:44 PM PDT 24
Finished May 23 01:42:54 PM PDT 24
Peak memory 211916 kb
Host smart-596f1ee4-e30a-4a61-9db7-113d263317f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3642749748 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_kmac_err_chk.3642749748
Directory /workspace/15.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/15.rom_ctrl_max_throughput_chk.1627871495
Short name T178
Test name
Test status
Simulation time 7208530932 ps
CPU time 16.91 seconds
Started May 23 01:42:46 PM PDT 24
Finished May 23 01:43:04 PM PDT 24
Peak memory 211192 kb
Host smart-6f583ac1-a441-4b23-b4f7-4963449da45d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1627871495 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_max_throughput_chk.1627871495
Directory /workspace/15.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/15.rom_ctrl_smoke.2690456031
Short name T120
Test name
Test status
Simulation time 740148705 ps
CPU time 9.93 seconds
Started May 23 01:42:40 PM PDT 24
Finished May 23 01:42:51 PM PDT 24
Peak memory 219320 kb
Host smart-b58a6334-3ad1-4f40-a998-c50e28c2182e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2690456031 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_smoke.2690456031
Directory /workspace/15.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/15.rom_ctrl_stress_all.667950684
Short name T136
Test name
Test status
Simulation time 5319069934 ps
CPU time 53.1 seconds
Started May 23 01:42:40 PM PDT 24
Finished May 23 01:43:34 PM PDT 24
Peak memory 216640 kb
Host smart-c39e2339-8803-4c5e-bc03-e6fb3b2c89b9
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=667950684 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 15.rom_ctrl_stress_all.667950684
Directory /workspace/15.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/16.rom_ctrl_alert_test.2240770664
Short name T147
Test name
Test status
Simulation time 86410019 ps
CPU time 4.37 seconds
Started May 23 01:42:44 PM PDT 24
Finished May 23 01:42:49 PM PDT 24
Peak memory 211248 kb
Host smart-05156581-6775-44d8-900d-185151b16fed
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2240770664 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_alert_test.2240770664
Directory /workspace/16.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/16.rom_ctrl_corrupt_sig_fatal_chk.472421926
Short name T176
Test name
Test status
Simulation time 143223622759 ps
CPU time 379.45 seconds
Started May 23 01:42:40 PM PDT 24
Finished May 23 01:49:00 PM PDT 24
Peak memory 237960 kb
Host smart-1cea48db-b024-406c-bd02-3ffcd9fa6bc5
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=472421926 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_c
orrupt_sig_fatal_chk.472421926
Directory /workspace/16.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/16.rom_ctrl_max_throughput_chk.768254905
Short name T251
Test name
Test status
Simulation time 3754761759 ps
CPU time 16.58 seconds
Started May 23 01:42:37 PM PDT 24
Finished May 23 01:42:55 PM PDT 24
Peak memory 211268 kb
Host smart-d350cd6f-86af-4177-87dc-d285ae71eb7a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=768254905 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_max_throughput_chk.768254905
Directory /workspace/16.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/16.rom_ctrl_smoke.2705013540
Short name T77
Test name
Test status
Simulation time 187564595 ps
CPU time 10.34 seconds
Started May 23 01:42:37 PM PDT 24
Finished May 23 01:42:49 PM PDT 24
Peak memory 213164 kb
Host smart-935c5357-761e-448e-91be-bba33d6b46ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2705013540 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_smoke.2705013540
Directory /workspace/16.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/16.rom_ctrl_stress_all.9841643
Short name T17
Test name
Test status
Simulation time 2187048919 ps
CPU time 19.04 seconds
Started May 23 01:42:40 PM PDT 24
Finished May 23 01:43:01 PM PDT 24
Peak memory 216388 kb
Host smart-53facc61-bb1d-4105-9466-d304355f247b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=9841643 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UV
M_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 16.rom_ctrl_stress_all.9841643
Directory /workspace/16.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/17.rom_ctrl_alert_test.3352059657
Short name T175
Test name
Test status
Simulation time 2596813112 ps
CPU time 12.23 seconds
Started May 23 01:42:46 PM PDT 24
Finished May 23 01:42:59 PM PDT 24
Peak memory 211344 kb
Host smart-830d962b-03e7-4305-a89d-61798db3cc0c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3352059657 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_alert_test.3352059657
Directory /workspace/17.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/17.rom_ctrl_corrupt_sig_fatal_chk.3103341259
Short name T217
Test name
Test status
Simulation time 584152242061 ps
CPU time 298.24 seconds
Started May 23 01:42:37 PM PDT 24
Finished May 23 01:47:37 PM PDT 24
Peak memory 230556 kb
Host smart-e0b85d80-4174-4309-a829-c413488a282f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3103341259 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_
corrupt_sig_fatal_chk.3103341259
Directory /workspace/17.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/17.rom_ctrl_kmac_err_chk.3066835281
Short name T49
Test name
Test status
Simulation time 4264296619 ps
CPU time 34.43 seconds
Started May 23 01:42:36 PM PDT 24
Finished May 23 01:43:11 PM PDT 24
Peak memory 212020 kb
Host smart-271ecf0c-f81f-40f6-9ebc-37c1f1b61564
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3066835281 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_kmac_err_chk.3066835281
Directory /workspace/17.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/17.rom_ctrl_max_throughput_chk.3391919450
Short name T330
Test name
Test status
Simulation time 6929890477 ps
CPU time 14.83 seconds
Started May 23 01:42:39 PM PDT 24
Finished May 23 01:42:55 PM PDT 24
Peak memory 211208 kb
Host smart-acb78cfa-20df-4703-9d79-222b5b1da4c6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3391919450 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_max_throughput_chk.3391919450
Directory /workspace/17.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/17.rom_ctrl_smoke.3315951769
Short name T150
Test name
Test status
Simulation time 37998458658 ps
CPU time 33.84 seconds
Started May 23 01:42:45 PM PDT 24
Finished May 23 01:43:20 PM PDT 24
Peak memory 219428 kb
Host smart-8aefbe65-4dcf-4e77-94a7-cd0d09130208
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3315951769 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_smoke.3315951769
Directory /workspace/17.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/17.rom_ctrl_stress_all.3338409100
Short name T297
Test name
Test status
Simulation time 1517492348 ps
CPU time 21.67 seconds
Started May 23 01:42:42 PM PDT 24
Finished May 23 01:43:04 PM PDT 24
Peak memory 216624 kb
Host smart-c1b27905-3f31-4ffa-93d5-f0cc68bd7403
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3338409100 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 17.rom_ctrl_stress_all.3338409100
Directory /workspace/17.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/18.rom_ctrl_alert_test.4157138168
Short name T65
Test name
Test status
Simulation time 1339106671 ps
CPU time 12.45 seconds
Started May 23 01:42:41 PM PDT 24
Finished May 23 01:42:55 PM PDT 24
Peak memory 211204 kb
Host smart-83cc5cc8-a6e5-4303-b5f8-8ec9a4eb1448
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4157138168 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_alert_test.4157138168
Directory /workspace/18.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/18.rom_ctrl_corrupt_sig_fatal_chk.2179852911
Short name T43
Test name
Test status
Simulation time 55629795804 ps
CPU time 276.32 seconds
Started May 23 01:42:39 PM PDT 24
Finished May 23 01:47:17 PM PDT 24
Peak memory 228688 kb
Host smart-e8757912-44cf-4e8d-958b-a874ce767087
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2179852911 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_
corrupt_sig_fatal_chk.2179852911
Directory /workspace/18.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/18.rom_ctrl_kmac_err_chk.1316397531
Short name T152
Test name
Test status
Simulation time 1328126267 ps
CPU time 11.86 seconds
Started May 23 01:42:37 PM PDT 24
Finished May 23 01:42:50 PM PDT 24
Peak memory 211816 kb
Host smart-bd24d6b0-17ec-42ce-899d-f3e6f2344ac9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1316397531 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_kmac_err_chk.1316397531
Directory /workspace/18.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/18.rom_ctrl_max_throughput_chk.3557067518
Short name T327
Test name
Test status
Simulation time 193392629 ps
CPU time 5.4 seconds
Started May 23 01:42:38 PM PDT 24
Finished May 23 01:42:45 PM PDT 24
Peak memory 211072 kb
Host smart-e2e90147-35f6-47bf-b948-e332ea501a69
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3557067518 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_max_throughput_chk.3557067518
Directory /workspace/18.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/18.rom_ctrl_smoke.1814073840
Short name T143
Test name
Test status
Simulation time 3769438072 ps
CPU time 37.28 seconds
Started May 23 01:42:40 PM PDT 24
Finished May 23 01:43:18 PM PDT 24
Peak memory 219436 kb
Host smart-11ddce22-9d0a-49f4-9546-c6330d59afa8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1814073840 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_smoke.1814073840
Directory /workspace/18.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/18.rom_ctrl_stress_all.1839703942
Short name T304
Test name
Test status
Simulation time 2258850372 ps
CPU time 7.18 seconds
Started May 23 01:42:41 PM PDT 24
Finished May 23 01:42:50 PM PDT 24
Peak memory 211296 kb
Host smart-32ad848d-a118-4934-a03a-a16418d6130c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1839703942 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 18.rom_ctrl_stress_all.1839703942
Directory /workspace/18.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/19.rom_ctrl_alert_test.3801580234
Short name T164
Test name
Test status
Simulation time 21009752050 ps
CPU time 13.96 seconds
Started May 23 01:42:59 PM PDT 24
Finished May 23 01:43:15 PM PDT 24
Peak memory 211352 kb
Host smart-2f689983-bc13-4c79-8fa8-e61894d35e73
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3801580234 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_alert_test.3801580234
Directory /workspace/19.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/19.rom_ctrl_corrupt_sig_fatal_chk.1716701803
Short name T183
Test name
Test status
Simulation time 206087163076 ps
CPU time 470.67 seconds
Started May 23 01:42:56 PM PDT 24
Finished May 23 01:50:48 PM PDT 24
Peak memory 212540 kb
Host smart-ce6544d6-e9e8-447f-b280-0db88f6c4ab3
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1716701803 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_
corrupt_sig_fatal_chk.1716701803
Directory /workspace/19.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/19.rom_ctrl_kmac_err_chk.3529344980
Short name T124
Test name
Test status
Simulation time 10815558530 ps
CPU time 26.26 seconds
Started May 23 01:42:55 PM PDT 24
Finished May 23 01:43:22 PM PDT 24
Peak memory 211368 kb
Host smart-8a5a8051-f9b8-45f2-9fd1-c4b2a71d5d34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3529344980 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_kmac_err_chk.3529344980
Directory /workspace/19.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/19.rom_ctrl_max_throughput_chk.294174883
Short name T338
Test name
Test status
Simulation time 2511679696 ps
CPU time 9.36 seconds
Started May 23 01:42:55 PM PDT 24
Finished May 23 01:43:06 PM PDT 24
Peak memory 211180 kb
Host smart-9dd956c8-df81-416c-be5e-b676cf4c0f86
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=294174883 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_max_throughput_chk.294174883
Directory /workspace/19.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/19.rom_ctrl_smoke.44337252
Short name T122
Test name
Test status
Simulation time 1913872259 ps
CPU time 21.29 seconds
Started May 23 01:42:45 PM PDT 24
Finished May 23 01:43:07 PM PDT 24
Peak memory 219304 kb
Host smart-2ae6ddf2-119d-4681-baf1-48929e8dad0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=44337252 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_smoke.44337252
Directory /workspace/19.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/19.rom_ctrl_stress_all.2008731640
Short name T237
Test name
Test status
Simulation time 2714897520 ps
CPU time 30.35 seconds
Started May 23 01:42:56 PM PDT 24
Finished May 23 01:43:28 PM PDT 24
Peak memory 216212 kb
Host smart-d34589b1-b23b-4f63-bf9b-7aebcd6b0253
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2008731640 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 19.rom_ctrl_stress_all.2008731640
Directory /workspace/19.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/2.rom_ctrl_alert_test.3607708647
Short name T358
Test name
Test status
Simulation time 3774250666 ps
CPU time 10.22 seconds
Started May 23 01:42:24 PM PDT 24
Finished May 23 01:42:36 PM PDT 24
Peak memory 211356 kb
Host smart-2906b3fb-78ed-4ac0-a3bb-b60627f62d1a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3607708647 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_alert_test.3607708647
Directory /workspace/2.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/2.rom_ctrl_corrupt_sig_fatal_chk.3948128731
Short name T196
Test name
Test status
Simulation time 59730904184 ps
CPU time 586.59 seconds
Started May 23 01:42:21 PM PDT 24
Finished May 23 01:52:10 PM PDT 24
Peak memory 228816 kb
Host smart-1f905123-89f5-4e4f-ae81-344ba32ebd00
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3948128731 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_c
orrupt_sig_fatal_chk.3948128731
Directory /workspace/2.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/2.rom_ctrl_kmac_err_chk.3358275354
Short name T37
Test name
Test status
Simulation time 3816101156 ps
CPU time 31.29 seconds
Started May 23 01:42:22 PM PDT 24
Finished May 23 01:42:55 PM PDT 24
Peak memory 211968 kb
Host smart-a34e38cd-92f4-4d12-89c3-b98efc38cf05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3358275354 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_kmac_err_chk.3358275354
Directory /workspace/2.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/2.rom_ctrl_max_throughput_chk.2692652403
Short name T336
Test name
Test status
Simulation time 3769760296 ps
CPU time 10.84 seconds
Started May 23 01:42:14 PM PDT 24
Finished May 23 01:42:29 PM PDT 24
Peak memory 211192 kb
Host smart-25489db9-7eb4-4020-9b80-56b16d5bfb67
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2692652403 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_max_throughput_chk.2692652403
Directory /workspace/2.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/2.rom_ctrl_sec_cm.2685430147
Short name T32
Test name
Test status
Simulation time 2146674832 ps
CPU time 63.17 seconds
Started May 23 01:42:21 PM PDT 24
Finished May 23 01:43:27 PM PDT 24
Peak memory 229164 kb
Host smart-16558188-c94b-4aff-bbd0-80b036d298fa
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2685430147 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_sec_cm.2685430147
Directory /workspace/2.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/2.rom_ctrl_smoke.3933530241
Short name T78
Test name
Test status
Simulation time 1765285396 ps
CPU time 22.14 seconds
Started May 23 01:42:13 PM PDT 24
Finished May 23 01:42:39 PM PDT 24
Peak memory 219300 kb
Host smart-f21ef126-3d32-4dba-828d-1653f9e8d8f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3933530241 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_smoke.3933530241
Directory /workspace/2.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/2.rom_ctrl_stress_all.4218274063
Short name T133
Test name
Test status
Simulation time 17583900379 ps
CPU time 52.38 seconds
Started May 23 01:42:21 PM PDT 24
Finished May 23 01:43:15 PM PDT 24
Peak memory 214184 kb
Host smart-294a8d0b-e976-4156-b307-4e446a9e4501
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4218274063 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 2.rom_ctrl_stress_all.4218274063
Directory /workspace/2.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/20.rom_ctrl_alert_test.3977854055
Short name T255
Test name
Test status
Simulation time 1488320712 ps
CPU time 12.86 seconds
Started May 23 01:42:58 PM PDT 24
Finished May 23 01:43:13 PM PDT 24
Peak memory 211256 kb
Host smart-748edb7e-0d38-489a-b350-69e7cd702c28
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3977854055 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_alert_test.3977854055
Directory /workspace/20.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/20.rom_ctrl_corrupt_sig_fatal_chk.2754167379
Short name T325
Test name
Test status
Simulation time 82510233916 ps
CPU time 249.52 seconds
Started May 23 01:42:53 PM PDT 24
Finished May 23 01:47:03 PM PDT 24
Peak memory 229720 kb
Host smart-a844b4d7-fdba-42b4-b682-18d1274ba8a5
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2754167379 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_
corrupt_sig_fatal_chk.2754167379
Directory /workspace/20.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/20.rom_ctrl_kmac_err_chk.2312154107
Short name T318
Test name
Test status
Simulation time 2048901188 ps
CPU time 13.04 seconds
Started May 23 01:42:54 PM PDT 24
Finished May 23 01:43:09 PM PDT 24
Peak memory 211956 kb
Host smart-f64ee69a-4ee9-4f90-a51b-3d747c6fa2a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2312154107 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_kmac_err_chk.2312154107
Directory /workspace/20.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/20.rom_ctrl_max_throughput_chk.1604869602
Short name T208
Test name
Test status
Simulation time 94244976 ps
CPU time 5.44 seconds
Started May 23 01:43:00 PM PDT 24
Finished May 23 01:43:08 PM PDT 24
Peak memory 211076 kb
Host smart-79482e8c-8765-4410-8bee-137a71a4065f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1604869602 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_max_throughput_chk.1604869602
Directory /workspace/20.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/20.rom_ctrl_smoke.1912275096
Short name T169
Test name
Test status
Simulation time 3128510658 ps
CPU time 38.81 seconds
Started May 23 01:42:58 PM PDT 24
Finished May 23 01:43:39 PM PDT 24
Peak memory 213672 kb
Host smart-76b6c174-3961-420e-bda2-5422719b4380
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1912275096 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_smoke.1912275096
Directory /workspace/20.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/20.rom_ctrl_stress_all.3087032285
Short name T323
Test name
Test status
Simulation time 31189643624 ps
CPU time 92.29 seconds
Started May 23 01:42:55 PM PDT 24
Finished May 23 01:44:28 PM PDT 24
Peak memory 219460 kb
Host smart-d180bc83-a531-423b-8f7d-450423fec4dd
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3087032285 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 20.rom_ctrl_stress_all.3087032285
Directory /workspace/20.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/21.rom_ctrl_alert_test.852824857
Short name T207
Test name
Test status
Simulation time 1485226017 ps
CPU time 6.9 seconds
Started May 23 01:42:58 PM PDT 24
Finished May 23 01:43:07 PM PDT 24
Peak memory 211144 kb
Host smart-b49bb973-1690-4390-bde9-4c4848898b0d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=852824857 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_alert_test.852824857
Directory /workspace/21.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/21.rom_ctrl_corrupt_sig_fatal_chk.1287190730
Short name T220
Test name
Test status
Simulation time 6419359746 ps
CPU time 105.98 seconds
Started May 23 01:42:56 PM PDT 24
Finished May 23 01:44:43 PM PDT 24
Peak memory 239128 kb
Host smart-50330cee-b026-4b8a-b131-4c418c2894a3
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1287190730 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_
corrupt_sig_fatal_chk.1287190730
Directory /workspace/21.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/21.rom_ctrl_kmac_err_chk.3594964087
Short name T225
Test name
Test status
Simulation time 341394749 ps
CPU time 9.39 seconds
Started May 23 01:42:55 PM PDT 24
Finished May 23 01:43:06 PM PDT 24
Peak memory 212104 kb
Host smart-6c4a11b4-1fda-4099-bbb5-a0512d490a64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3594964087 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_kmac_err_chk.3594964087
Directory /workspace/21.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/21.rom_ctrl_max_throughput_chk.3347136920
Short name T6
Test name
Test status
Simulation time 1609799967 ps
CPU time 10.13 seconds
Started May 23 01:42:57 PM PDT 24
Finished May 23 01:43:09 PM PDT 24
Peak memory 211100 kb
Host smart-72d43285-f419-4c52-97d1-1c5c8b2eb194
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3347136920 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_max_throughput_chk.3347136920
Directory /workspace/21.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/21.rom_ctrl_smoke.3992842246
Short name T286
Test name
Test status
Simulation time 3603382174 ps
CPU time 34.72 seconds
Started May 23 01:42:59 PM PDT 24
Finished May 23 01:43:36 PM PDT 24
Peak memory 219432 kb
Host smart-25ab070d-14b7-489a-9369-4679c5229477
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3992842246 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_smoke.3992842246
Directory /workspace/21.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/21.rom_ctrl_stress_all.2699379488
Short name T41
Test name
Test status
Simulation time 20415551616 ps
CPU time 53.86 seconds
Started May 23 01:42:58 PM PDT 24
Finished May 23 01:43:54 PM PDT 24
Peak memory 219436 kb
Host smart-814d53e3-0ba5-4d65-8a1a-12e9f4dda652
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2699379488 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 21.rom_ctrl_stress_all.2699379488
Directory /workspace/21.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/22.rom_ctrl_alert_test.445215764
Short name T258
Test name
Test status
Simulation time 3539981073 ps
CPU time 15.05 seconds
Started May 23 01:42:57 PM PDT 24
Finished May 23 01:43:14 PM PDT 24
Peak memory 211356 kb
Host smart-29a3ada1-4f15-48cb-b171-df716f307f45
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=445215764 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_alert_test.445215764
Directory /workspace/22.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/22.rom_ctrl_corrupt_sig_fatal_chk.2823131862
Short name T283
Test name
Test status
Simulation time 1288592426 ps
CPU time 85.48 seconds
Started May 23 01:42:58 PM PDT 24
Finished May 23 01:44:26 PM PDT 24
Peak memory 224688 kb
Host smart-67001d64-e6bf-4bdd-87d2-39e15dbaebf2
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2823131862 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_
corrupt_sig_fatal_chk.2823131862
Directory /workspace/22.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/22.rom_ctrl_kmac_err_chk.3888139413
Short name T209
Test name
Test status
Simulation time 55164770281 ps
CPU time 33.81 seconds
Started May 23 01:42:59 PM PDT 24
Finished May 23 01:43:35 PM PDT 24
Peak memory 212296 kb
Host smart-b5b6d020-c5b5-47bf-bea5-c4703f875511
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3888139413 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_kmac_err_chk.3888139413
Directory /workspace/22.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/22.rom_ctrl_max_throughput_chk.2560829709
Short name T211
Test name
Test status
Simulation time 5325817160 ps
CPU time 13.32 seconds
Started May 23 01:42:54 PM PDT 24
Finished May 23 01:43:08 PM PDT 24
Peak memory 211176 kb
Host smart-fdd35275-8329-47b4-8760-65827912f278
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2560829709 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_max_throughput_chk.2560829709
Directory /workspace/22.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/22.rom_ctrl_smoke.966403021
Short name T229
Test name
Test status
Simulation time 1812705180 ps
CPU time 26.88 seconds
Started May 23 01:42:54 PM PDT 24
Finished May 23 01:43:22 PM PDT 24
Peak memory 213680 kb
Host smart-41eb2801-cb65-4a06-aeb6-dadf5baafd0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=966403021 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_smoke.966403021
Directory /workspace/22.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/22.rom_ctrl_stress_all.2551255164
Short name T38
Test name
Test status
Simulation time 32311039350 ps
CPU time 143.38 seconds
Started May 23 01:42:54 PM PDT 24
Finished May 23 01:45:19 PM PDT 24
Peak memory 219444 kb
Host smart-e6d0ba9a-5f8d-4a43-826a-9c0ccf6d6a2b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2551255164 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 22.rom_ctrl_stress_all.2551255164
Directory /workspace/22.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/23.rom_ctrl_alert_test.2633124345
Short name T337
Test name
Test status
Simulation time 2615890627 ps
CPU time 11.85 seconds
Started May 23 01:42:57 PM PDT 24
Finished May 23 01:43:11 PM PDT 24
Peak memory 211376 kb
Host smart-ae3ec377-f777-486c-97b5-acb08f42d248
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2633124345 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_alert_test.2633124345
Directory /workspace/23.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/23.rom_ctrl_corrupt_sig_fatal_chk.2629064995
Short name T259
Test name
Test status
Simulation time 6843560168 ps
CPU time 146.95 seconds
Started May 23 01:42:54 PM PDT 24
Finished May 23 01:45:22 PM PDT 24
Peak memory 213528 kb
Host smart-6ca29aa2-0d2f-4fff-9488-50ca7ee8a52d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2629064995 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_
corrupt_sig_fatal_chk.2629064995
Directory /workspace/23.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/23.rom_ctrl_kmac_err_chk.347800919
Short name T267
Test name
Test status
Simulation time 29641920955 ps
CPU time 25.36 seconds
Started May 23 01:42:57 PM PDT 24
Finished May 23 01:43:24 PM PDT 24
Peak memory 211412 kb
Host smart-f49e9413-879c-41b0-89a7-060ed940b433
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=347800919 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_kmac_err_chk.347800919
Directory /workspace/23.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/23.rom_ctrl_max_throughput_chk.2705107534
Short name T317
Test name
Test status
Simulation time 379674693 ps
CPU time 5.78 seconds
Started May 23 01:42:58 PM PDT 24
Finished May 23 01:43:06 PM PDT 24
Peak memory 211072 kb
Host smart-024b64ce-5f31-4ac8-a981-95628a9710b7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2705107534 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_max_throughput_chk.2705107534
Directory /workspace/23.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/23.rom_ctrl_smoke.3484593070
Short name T261
Test name
Test status
Simulation time 9721912191 ps
CPU time 28.51 seconds
Started May 23 01:42:57 PM PDT 24
Finished May 23 01:43:27 PM PDT 24
Peak memory 219440 kb
Host smart-5b7f3959-c26c-4f5d-a93c-180d21fd2d2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3484593070 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_smoke.3484593070
Directory /workspace/23.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/23.rom_ctrl_stress_all.1254721682
Short name T324
Test name
Test status
Simulation time 6616045981 ps
CPU time 31.33 seconds
Started May 23 01:42:54 PM PDT 24
Finished May 23 01:43:27 PM PDT 24
Peak memory 219484 kb
Host smart-c72b65a9-b460-470f-9a5f-cbcc260f60b4
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1254721682 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 23.rom_ctrl_stress_all.1254721682
Directory /workspace/23.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/24.rom_ctrl_alert_test.321980128
Short name T67
Test name
Test status
Simulation time 8392375083 ps
CPU time 16.32 seconds
Started May 23 01:42:57 PM PDT 24
Finished May 23 01:43:15 PM PDT 24
Peak memory 211328 kb
Host smart-e8342bf3-2df0-448c-8b3d-2987b7d6a109
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=321980128 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_alert_test.321980128
Directory /workspace/24.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/24.rom_ctrl_corrupt_sig_fatal_chk.740888959
Short name T234
Test name
Test status
Simulation time 5737550005 ps
CPU time 117.52 seconds
Started May 23 01:42:58 PM PDT 24
Finished May 23 01:44:58 PM PDT 24
Peak memory 230296 kb
Host smart-104b94dc-4737-4b6d-854e-cb5ff19870dc
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=740888959 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_c
orrupt_sig_fatal_chk.740888959
Directory /workspace/24.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/24.rom_ctrl_kmac_err_chk.2969828317
Short name T23
Test name
Test status
Simulation time 2207263533 ps
CPU time 22.99 seconds
Started May 23 01:43:00 PM PDT 24
Finished May 23 01:43:25 PM PDT 24
Peak memory 211936 kb
Host smart-6c9501ab-25c3-40bb-9b5a-486e3604192a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2969828317 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_kmac_err_chk.2969828317
Directory /workspace/24.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/24.rom_ctrl_max_throughput_chk.3256951268
Short name T39
Test name
Test status
Simulation time 1273500419 ps
CPU time 12.7 seconds
Started May 23 01:42:59 PM PDT 24
Finished May 23 01:43:14 PM PDT 24
Peak memory 211104 kb
Host smart-9b681765-e2dd-4087-baa0-abc18fe0c2ed
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3256951268 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_max_throughput_chk.3256951268
Directory /workspace/24.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/24.rom_ctrl_smoke.2127180034
Short name T116
Test name
Test status
Simulation time 956155779 ps
CPU time 10.59 seconds
Started May 23 01:42:57 PM PDT 24
Finished May 23 01:43:09 PM PDT 24
Peak memory 213960 kb
Host smart-e83d3b36-9962-4af4-83fb-6ed88803e980
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2127180034 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_smoke.2127180034
Directory /workspace/24.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/24.rom_ctrl_stress_all.3285975586
Short name T332
Test name
Test status
Simulation time 404756750 ps
CPU time 28.41 seconds
Started May 23 01:42:56 PM PDT 24
Finished May 23 01:43:26 PM PDT 24
Peak memory 214096 kb
Host smart-4d65f137-5892-4f99-bff2-72b04b224bed
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3285975586 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 24.rom_ctrl_stress_all.3285975586
Directory /workspace/24.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/25.rom_ctrl_alert_test.62607412
Short name T357
Test name
Test status
Simulation time 4378873149 ps
CPU time 11.07 seconds
Started May 23 01:42:55 PM PDT 24
Finished May 23 01:43:08 PM PDT 24
Peak memory 211356 kb
Host smart-324c805b-b422-4a24-9bef-d9808d95f113
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=62607412 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_alert_test.62607412
Directory /workspace/25.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/25.rom_ctrl_corrupt_sig_fatal_chk.1244783178
Short name T291
Test name
Test status
Simulation time 21670083634 ps
CPU time 194.07 seconds
Started May 23 01:42:55 PM PDT 24
Finished May 23 01:46:10 PM PDT 24
Peak memory 237900 kb
Host smart-5ac71022-9806-475e-a39e-6c8e0be51b5a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1244783178 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_
corrupt_sig_fatal_chk.1244783178
Directory /workspace/25.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/25.rom_ctrl_kmac_err_chk.1313894161
Short name T187
Test name
Test status
Simulation time 15380407467 ps
CPU time 32.5 seconds
Started May 23 01:42:53 PM PDT 24
Finished May 23 01:43:27 PM PDT 24
Peak memory 212016 kb
Host smart-8d14a7c5-6c98-4531-8161-3d9e1ff6f94d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1313894161 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_kmac_err_chk.1313894161
Directory /workspace/25.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/25.rom_ctrl_max_throughput_chk.881239043
Short name T301
Test name
Test status
Simulation time 2381526714 ps
CPU time 12.41 seconds
Started May 23 01:42:56 PM PDT 24
Finished May 23 01:43:11 PM PDT 24
Peak memory 211144 kb
Host smart-f136a590-5c22-44e7-a4f2-d4d0494883ec
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=881239043 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_max_throughput_chk.881239043
Directory /workspace/25.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/25.rom_ctrl_smoke.1008828107
Short name T232
Test name
Test status
Simulation time 1133309180 ps
CPU time 13.17 seconds
Started May 23 01:43:00 PM PDT 24
Finished May 23 01:43:15 PM PDT 24
Peak memory 213508 kb
Host smart-463aa1dd-811f-4601-b49b-25a498a5bc7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1008828107 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_smoke.1008828107
Directory /workspace/25.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/25.rom_ctrl_stress_all.3984685100
Short name T289
Test name
Test status
Simulation time 19663195979 ps
CPU time 39.88 seconds
Started May 23 01:43:01 PM PDT 24
Finished May 23 01:43:43 PM PDT 24
Peak memory 216960 kb
Host smart-74e935b7-1ad9-46d0-8c12-bca22b306eb4
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3984685100 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 25.rom_ctrl_stress_all.3984685100
Directory /workspace/25.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/25.rom_ctrl_stress_all_with_rand_reset.3825985760
Short name T348
Test name
Test status
Simulation time 34279086307 ps
CPU time 646.7 seconds
Started May 23 01:42:55 PM PDT 24
Finished May 23 01:53:43 PM PDT 24
Peak memory 226580 kb
Host smart-0cb2da23-1759-4b8c-823f-91d3128ad131
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3825985760 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_stress_all_with_rand_reset.3825985760
Directory /workspace/25.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/26.rom_ctrl_alert_test.348397822
Short name T271
Test name
Test status
Simulation time 2681404953 ps
CPU time 7.61 seconds
Started May 23 01:42:58 PM PDT 24
Finished May 23 01:43:08 PM PDT 24
Peak memory 211380 kb
Host smart-99554847-2666-40d5-8962-0d005fdae61a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=348397822 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_alert_test.348397822
Directory /workspace/26.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/26.rom_ctrl_corrupt_sig_fatal_chk.3320378683
Short name T161
Test name
Test status
Simulation time 6234173238 ps
CPU time 142.31 seconds
Started May 23 01:43:01 PM PDT 24
Finished May 23 01:45:25 PM PDT 24
Peak memory 231584 kb
Host smart-85064b0f-48b9-4b58-9acf-a45da1a0efc7
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3320378683 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_
corrupt_sig_fatal_chk.3320378683
Directory /workspace/26.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/26.rom_ctrl_kmac_err_chk.3067407100
Short name T328
Test name
Test status
Simulation time 13726523353 ps
CPU time 30.32 seconds
Started May 23 01:42:58 PM PDT 24
Finished May 23 01:43:31 PM PDT 24
Peak memory 212240 kb
Host smart-342908b7-8139-4afd-a1a4-23675ac22429
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3067407100 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_kmac_err_chk.3067407100
Directory /workspace/26.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/26.rom_ctrl_max_throughput_chk.3481922205
Short name T346
Test name
Test status
Simulation time 8504017488 ps
CPU time 17.61 seconds
Started May 23 01:43:00 PM PDT 24
Finished May 23 01:43:20 PM PDT 24
Peak memory 211188 kb
Host smart-96e2d6b5-41de-414f-9377-163ba8dea6ff
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3481922205 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_max_throughput_chk.3481922205
Directory /workspace/26.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/26.rom_ctrl_smoke.1753970859
Short name T292
Test name
Test status
Simulation time 525926346 ps
CPU time 13.19 seconds
Started May 23 01:42:55 PM PDT 24
Finished May 23 01:43:09 PM PDT 24
Peak memory 212820 kb
Host smart-b3bb156f-6b33-4849-9528-00db54d309b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1753970859 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_smoke.1753970859
Directory /workspace/26.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/26.rom_ctrl_stress_all.4221748416
Short name T22
Test name
Test status
Simulation time 2498301173 ps
CPU time 26.91 seconds
Started May 23 01:42:56 PM PDT 24
Finished May 23 01:43:25 PM PDT 24
Peak memory 214228 kb
Host smart-40f6f9a2-e8d5-478e-adbc-32bac1d0527c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4221748416 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 26.rom_ctrl_stress_all.4221748416
Directory /workspace/26.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/26.rom_ctrl_stress_all_with_rand_reset.325726721
Short name T18
Test name
Test status
Simulation time 178835774038 ps
CPU time 4113.41 seconds
Started May 23 01:42:59 PM PDT 24
Finished May 23 02:51:35 PM PDT 24
Peak memory 235964 kb
Host smart-fe9fc5ec-2476-44ef-bb02-3c57eea0446d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=325726721 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_stress_all_with_rand_reset.325726721
Directory /workspace/26.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/27.rom_ctrl_alert_test.940810240
Short name T329
Test name
Test status
Simulation time 88150543 ps
CPU time 4.42 seconds
Started May 23 01:42:58 PM PDT 24
Finished May 23 01:43:05 PM PDT 24
Peak memory 211180 kb
Host smart-f7ca59b2-3e30-4dbe-afc8-72fb020cdb90
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=940810240 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_alert_test.940810240
Directory /workspace/27.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/27.rom_ctrl_corrupt_sig_fatal_chk.550229526
Short name T45
Test name
Test status
Simulation time 870003060791 ps
CPU time 476.1 seconds
Started May 23 01:43:03 PM PDT 24
Finished May 23 01:51:00 PM PDT 24
Peak memory 237884 kb
Host smart-ee5ec3ce-e70b-4ff8-963b-0c131b74fa2b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=550229526 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_c
orrupt_sig_fatal_chk.550229526
Directory /workspace/27.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/27.rom_ctrl_kmac_err_chk.4284792407
Short name T306
Test name
Test status
Simulation time 1930927192 ps
CPU time 21 seconds
Started May 23 01:42:57 PM PDT 24
Finished May 23 01:43:20 PM PDT 24
Peak memory 211904 kb
Host smart-aeb95185-dcdd-4399-956a-64c560339fe9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4284792407 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_kmac_err_chk.4284792407
Directory /workspace/27.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/27.rom_ctrl_max_throughput_chk.104308717
Short name T119
Test name
Test status
Simulation time 440906330 ps
CPU time 8.21 seconds
Started May 23 01:42:58 PM PDT 24
Finished May 23 01:43:09 PM PDT 24
Peak memory 211020 kb
Host smart-0cbd51c8-d4bb-4939-a8e7-cb0582a7a87d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=104308717 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_max_throughput_chk.104308717
Directory /workspace/27.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/27.rom_ctrl_smoke.3163556366
Short name T270
Test name
Test status
Simulation time 27727329824 ps
CPU time 29.94 seconds
Started May 23 01:42:59 PM PDT 24
Finished May 23 01:43:31 PM PDT 24
Peak memory 214052 kb
Host smart-1d98d9ff-efea-4913-b59d-b3590cc8b4eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3163556366 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_smoke.3163556366
Directory /workspace/27.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/27.rom_ctrl_stress_all.3172621549
Short name T117
Test name
Test status
Simulation time 18108126692 ps
CPU time 51.33 seconds
Started May 23 01:42:56 PM PDT 24
Finished May 23 01:43:49 PM PDT 24
Peak memory 218560 kb
Host smart-40dc5b3b-1d62-4556-9fb7-a4570fe30970
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3172621549 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 27.rom_ctrl_stress_all.3172621549
Directory /workspace/27.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/28.rom_ctrl_alert_test.2474392626
Short name T42
Test name
Test status
Simulation time 1071262156 ps
CPU time 11.27 seconds
Started May 23 01:43:14 PM PDT 24
Finished May 23 01:43:28 PM PDT 24
Peak memory 211248 kb
Host smart-751cb736-c4f6-4de1-934b-47c41a1395b6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2474392626 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_alert_test.2474392626
Directory /workspace/28.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/28.rom_ctrl_corrupt_sig_fatal_chk.598936866
Short name T230
Test name
Test status
Simulation time 25361316540 ps
CPU time 155.21 seconds
Started May 23 01:43:15 PM PDT 24
Finished May 23 01:45:54 PM PDT 24
Peak memory 229468 kb
Host smart-7c12f8c0-daba-4b29-a694-defbf1d7a401
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=598936866 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_c
orrupt_sig_fatal_chk.598936866
Directory /workspace/28.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/28.rom_ctrl_kmac_err_chk.1443377389
Short name T135
Test name
Test status
Simulation time 3278411060 ps
CPU time 29.19 seconds
Started May 23 01:43:12 PM PDT 24
Finished May 23 01:43:43 PM PDT 24
Peak memory 211884 kb
Host smart-3971fb26-8073-4765-8fa6-57a0733dc029
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1443377389 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_kmac_err_chk.1443377389
Directory /workspace/28.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/28.rom_ctrl_max_throughput_chk.622236682
Short name T205
Test name
Test status
Simulation time 103946324 ps
CPU time 5.88 seconds
Started May 23 01:43:17 PM PDT 24
Finished May 23 01:43:27 PM PDT 24
Peak memory 211092 kb
Host smart-29fd7064-f38a-463e-9d36-b590f9636aac
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=622236682 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_max_throughput_chk.622236682
Directory /workspace/28.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/28.rom_ctrl_smoke.2310519045
Short name T227
Test name
Test status
Simulation time 219113301 ps
CPU time 9.63 seconds
Started May 23 01:42:57 PM PDT 24
Finished May 23 01:43:08 PM PDT 24
Peak memory 219320 kb
Host smart-688efbe7-042b-4e03-9bb1-ff6a70368131
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2310519045 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_smoke.2310519045
Directory /workspace/28.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/28.rom_ctrl_stress_all.3397855381
Short name T129
Test name
Test status
Simulation time 1854464052 ps
CPU time 17.05 seconds
Started May 23 01:43:13 PM PDT 24
Finished May 23 01:43:32 PM PDT 24
Peak memory 211032 kb
Host smart-179c325a-0ee3-445a-b092-dac3af1327e9
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3397855381 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 28.rom_ctrl_stress_all.3397855381
Directory /workspace/28.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/28.rom_ctrl_stress_all_with_rand_reset.1468064567
Short name T299
Test name
Test status
Simulation time 102727162170 ps
CPU time 1050.76 seconds
Started May 23 01:43:14 PM PDT 24
Finished May 23 02:00:49 PM PDT 24
Peak memory 231732 kb
Host smart-a4fc87cc-de89-4b59-abfb-13abf401df1e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1468064567 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_stress_all_with_rand_reset.1468064567
Directory /workspace/28.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/29.rom_ctrl_alert_test.2724971349
Short name T254
Test name
Test status
Simulation time 7969453500 ps
CPU time 12.04 seconds
Started May 23 01:43:20 PM PDT 24
Finished May 23 01:43:36 PM PDT 24
Peak memory 211328 kb
Host smart-f2b83fa0-88b1-40a2-b907-168210ec65d2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2724971349 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_alert_test.2724971349
Directory /workspace/29.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/29.rom_ctrl_corrupt_sig_fatal_chk.3098983142
Short name T315
Test name
Test status
Simulation time 161461696987 ps
CPU time 201.77 seconds
Started May 23 01:43:17 PM PDT 24
Finished May 23 01:46:43 PM PDT 24
Peak memory 224992 kb
Host smart-0e45953f-6ad8-407d-ae5d-97e6d58b45df
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3098983142 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_
corrupt_sig_fatal_chk.3098983142
Directory /workspace/29.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/29.rom_ctrl_kmac_err_chk.2266223804
Short name T316
Test name
Test status
Simulation time 12506578537 ps
CPU time 28.45 seconds
Started May 23 01:43:15 PM PDT 24
Finished May 23 01:43:48 PM PDT 24
Peak memory 212160 kb
Host smart-71e2002e-6c5d-49f0-a431-e42c4cee9b9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2266223804 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_kmac_err_chk.2266223804
Directory /workspace/29.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/29.rom_ctrl_max_throughput_chk.2875587476
Short name T121
Test name
Test status
Simulation time 5686878925 ps
CPU time 17.38 seconds
Started May 23 01:43:18 PM PDT 24
Finished May 23 01:43:39 PM PDT 24
Peak memory 211188 kb
Host smart-51db831e-60cf-47bd-aede-ddeaab8c70ab
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2875587476 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_max_throughput_chk.2875587476
Directory /workspace/29.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/29.rom_ctrl_smoke.1793192662
Short name T311
Test name
Test status
Simulation time 14652195102 ps
CPU time 30.43 seconds
Started May 23 01:43:16 PM PDT 24
Finished May 23 01:43:50 PM PDT 24
Peak memory 219448 kb
Host smart-766594ec-5a3c-4194-85c6-81701cd4e261
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1793192662 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_smoke.1793192662
Directory /workspace/29.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/29.rom_ctrl_stress_all.2523781938
Short name T252
Test name
Test status
Simulation time 2167907907 ps
CPU time 20.75 seconds
Started May 23 01:43:15 PM PDT 24
Finished May 23 01:43:40 PM PDT 24
Peak memory 215116 kb
Host smart-ff558b47-a487-4cc2-aa29-222b0036e96c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2523781938 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 29.rom_ctrl_stress_all.2523781938
Directory /workspace/29.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/3.rom_ctrl_alert_test.4012481023
Short name T200
Test name
Test status
Simulation time 379213540 ps
CPU time 4.23 seconds
Started May 23 01:42:22 PM PDT 24
Finished May 23 01:42:28 PM PDT 24
Peak memory 211184 kb
Host smart-434f9e97-601d-41c2-aaf4-5c86a5e5f69c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4012481023 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_alert_test.4012481023
Directory /workspace/3.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/3.rom_ctrl_corrupt_sig_fatal_chk.1107711927
Short name T193
Test name
Test status
Simulation time 128463609712 ps
CPU time 356.35 seconds
Started May 23 01:42:23 PM PDT 24
Finished May 23 01:48:21 PM PDT 24
Peak memory 228536 kb
Host smart-8ac2d812-dd64-440e-a23b-2ea7ab6243e5
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1107711927 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_c
orrupt_sig_fatal_chk.1107711927
Directory /workspace/3.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/3.rom_ctrl_kmac_err_chk.4137465970
Short name T359
Test name
Test status
Simulation time 2377483765 ps
CPU time 22.27 seconds
Started May 23 01:42:22 PM PDT 24
Finished May 23 01:42:46 PM PDT 24
Peak memory 211900 kb
Host smart-505eb716-a069-4b18-a1c9-ee62ceb3b666
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4137465970 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_kmac_err_chk.4137465970
Directory /workspace/3.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/3.rom_ctrl_max_throughput_chk.1947234522
Short name T314
Test name
Test status
Simulation time 3125922028 ps
CPU time 7.98 seconds
Started May 23 01:42:22 PM PDT 24
Finished May 23 01:42:32 PM PDT 24
Peak memory 211168 kb
Host smart-160ca624-bf58-4fac-bd21-102dc04e4098
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1947234522 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_max_throughput_chk.1947234522
Directory /workspace/3.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/3.rom_ctrl_sec_cm.3194073283
Short name T35
Test name
Test status
Simulation time 3500259884 ps
CPU time 106.81 seconds
Started May 23 01:42:28 PM PDT 24
Finished May 23 01:44:17 PM PDT 24
Peak memory 230804 kb
Host smart-6ab5ac03-90ca-44f4-bbe4-efabe1708d6a
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3194073283 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_sec_cm.3194073283
Directory /workspace/3.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/3.rom_ctrl_smoke.3715838452
Short name T9
Test name
Test status
Simulation time 4263420434 ps
CPU time 33.94 seconds
Started May 23 01:42:28 PM PDT 24
Finished May 23 01:43:04 PM PDT 24
Peak memory 213132 kb
Host smart-7af19550-398e-4f7e-9fa4-27efb2e15843
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3715838452 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_smoke.3715838452
Directory /workspace/3.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/3.rom_ctrl_stress_all.75231109
Short name T204
Test name
Test status
Simulation time 29636847412 ps
CPU time 102.29 seconds
Started May 23 01:42:22 PM PDT 24
Finished May 23 01:44:06 PM PDT 24
Peak memory 219444 kb
Host smart-907a08d7-9a78-45f9-a84c-3b7107225e8d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75231109 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +U
VM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n
ame 3.rom_ctrl_stress_all.75231109
Directory /workspace/3.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/30.rom_ctrl_alert_test.1228245508
Short name T246
Test name
Test status
Simulation time 1018610862 ps
CPU time 10.58 seconds
Started May 23 01:43:14 PM PDT 24
Finished May 23 01:43:29 PM PDT 24
Peak memory 211220 kb
Host smart-679f1231-2a5f-43a3-8ed7-ad410442e423
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1228245508 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_alert_test.1228245508
Directory /workspace/30.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/30.rom_ctrl_corrupt_sig_fatal_chk.2269900792
Short name T321
Test name
Test status
Simulation time 44196856496 ps
CPU time 143.36 seconds
Started May 23 01:43:15 PM PDT 24
Finished May 23 01:45:43 PM PDT 24
Peak memory 237848 kb
Host smart-a6c95518-b963-4a7d-a638-be5f44651e7c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2269900792 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_
corrupt_sig_fatal_chk.2269900792
Directory /workspace/30.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/30.rom_ctrl_kmac_err_chk.1553733488
Short name T293
Test name
Test status
Simulation time 168736843 ps
CPU time 9.87 seconds
Started May 23 01:43:15 PM PDT 24
Finished May 23 01:43:29 PM PDT 24
Peak memory 211224 kb
Host smart-7c74e327-1972-4107-b573-285f66275851
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1553733488 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_kmac_err_chk.1553733488
Directory /workspace/30.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/30.rom_ctrl_max_throughput_chk.658847921
Short name T272
Test name
Test status
Simulation time 98161438 ps
CPU time 5.75 seconds
Started May 23 01:43:13 PM PDT 24
Finished May 23 01:43:21 PM PDT 24
Peak memory 211092 kb
Host smart-ab6178bb-e99d-4a9c-8eba-31c08cd2f171
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=658847921 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_max_throughput_chk.658847921
Directory /workspace/30.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/30.rom_ctrl_smoke.1473028519
Short name T203
Test name
Test status
Simulation time 9734666338 ps
CPU time 23.85 seconds
Started May 23 01:43:18 PM PDT 24
Finished May 23 01:43:46 PM PDT 24
Peak memory 219476 kb
Host smart-3f99fb5d-6f0b-4f56-ba86-23b4d0d59020
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1473028519 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_smoke.1473028519
Directory /workspace/30.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/31.rom_ctrl_alert_test.768820879
Short name T180
Test name
Test status
Simulation time 209865211 ps
CPU time 4.42 seconds
Started May 23 01:43:17 PM PDT 24
Finished May 23 01:43:25 PM PDT 24
Peak memory 211228 kb
Host smart-4807cd5c-c6ee-4028-be5f-088898c8fc31
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=768820879 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_alert_test.768820879
Directory /workspace/31.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/31.rom_ctrl_corrupt_sig_fatal_chk.4018979856
Short name T202
Test name
Test status
Simulation time 44494777651 ps
CPU time 433.7 seconds
Started May 23 01:43:15 PM PDT 24
Finished May 23 01:50:33 PM PDT 24
Peak memory 229224 kb
Host smart-43acba88-daf9-43af-be32-efc0f3857703
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4018979856 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_
corrupt_sig_fatal_chk.4018979856
Directory /workspace/31.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/31.rom_ctrl_kmac_err_chk.1338362968
Short name T20
Test name
Test status
Simulation time 4546072473 ps
CPU time 23.46 seconds
Started May 23 01:43:16 PM PDT 24
Finished May 23 01:43:44 PM PDT 24
Peak memory 212312 kb
Host smart-0465d890-fdc1-4e47-9091-560f3449b74c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1338362968 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_kmac_err_chk.1338362968
Directory /workspace/31.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/31.rom_ctrl_max_throughput_chk.1433435266
Short name T138
Test name
Test status
Simulation time 14482628993 ps
CPU time 17.61 seconds
Started May 23 01:43:15 PM PDT 24
Finished May 23 01:43:36 PM PDT 24
Peak memory 211188 kb
Host smart-de689171-6f30-42fa-87e0-24c5736d6023
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1433435266 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_max_throughput_chk.1433435266
Directory /workspace/31.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/31.rom_ctrl_smoke.2016049830
Short name T186
Test name
Test status
Simulation time 3028775857 ps
CPU time 15.11 seconds
Started May 23 01:43:15 PM PDT 24
Finished May 23 01:43:34 PM PDT 24
Peak memory 213832 kb
Host smart-66cb9ea1-db65-4868-919e-fbab4f627f68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2016049830 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_smoke.2016049830
Directory /workspace/31.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/31.rom_ctrl_stress_all.1067108778
Short name T201
Test name
Test status
Simulation time 946706778 ps
CPU time 16.64 seconds
Started May 23 01:43:20 PM PDT 24
Finished May 23 01:43:40 PM PDT 24
Peak memory 219284 kb
Host smart-1e6853b1-e5a4-4765-a0a1-62e4ecc04bea
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1067108778 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 31.rom_ctrl_stress_all.1067108778
Directory /workspace/31.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/32.rom_ctrl_alert_test.1567940104
Short name T155
Test name
Test status
Simulation time 3393769094 ps
CPU time 10.24 seconds
Started May 23 01:43:14 PM PDT 24
Finished May 23 01:43:27 PM PDT 24
Peak memory 211376 kb
Host smart-0d6c95f1-3907-41dc-8e3e-55ad5af21e26
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1567940104 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_alert_test.1567940104
Directory /workspace/32.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/32.rom_ctrl_corrupt_sig_fatal_chk.1544342468
Short name T307
Test name
Test status
Simulation time 22547584689 ps
CPU time 242.15 seconds
Started May 23 01:43:15 PM PDT 24
Finished May 23 01:47:22 PM PDT 24
Peak memory 237000 kb
Host smart-893743e4-d6f1-43b4-89b7-08ba63182baf
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1544342468 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_
corrupt_sig_fatal_chk.1544342468
Directory /workspace/32.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/32.rom_ctrl_kmac_err_chk.3396091756
Short name T240
Test name
Test status
Simulation time 10052133012 ps
CPU time 25.66 seconds
Started May 23 01:43:16 PM PDT 24
Finished May 23 01:43:46 PM PDT 24
Peak memory 212124 kb
Host smart-7379f83f-cfd5-43c2-ad10-c50915adc29d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3396091756 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_kmac_err_chk.3396091756
Directory /workspace/32.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/32.rom_ctrl_max_throughput_chk.3730645247
Short name T326
Test name
Test status
Simulation time 97574196 ps
CPU time 5.35 seconds
Started May 23 01:43:16 PM PDT 24
Finished May 23 01:43:26 PM PDT 24
Peak memory 211072 kb
Host smart-2279541e-22da-45fa-ac7f-dbb31b77ea62
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3730645247 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_max_throughput_chk.3730645247
Directory /workspace/32.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/32.rom_ctrl_smoke.2827636834
Short name T12
Test name
Test status
Simulation time 1496845745 ps
CPU time 19.7 seconds
Started May 23 01:43:13 PM PDT 24
Finished May 23 01:43:35 PM PDT 24
Peak memory 213420 kb
Host smart-f65ee968-a18e-42be-ad8e-9fa6e245b2f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2827636834 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_smoke.2827636834
Directory /workspace/32.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/32.rom_ctrl_stress_all.3338800790
Short name T353
Test name
Test status
Simulation time 4916417119 ps
CPU time 35.74 seconds
Started May 23 01:43:18 PM PDT 24
Finished May 23 01:43:58 PM PDT 24
Peak memory 213188 kb
Host smart-697cbfe5-89bf-45c7-90a5-89be9147e00c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3338800790 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 32.rom_ctrl_stress_all.3338800790
Directory /workspace/32.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/33.rom_ctrl_alert_test.2861564512
Short name T238
Test name
Test status
Simulation time 10397265546 ps
CPU time 10.4 seconds
Started May 23 01:43:16 PM PDT 24
Finished May 23 01:43:30 PM PDT 24
Peak memory 211344 kb
Host smart-9e1896b6-578a-41b4-b0a1-7ed9a3b9c0f6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2861564512 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_alert_test.2861564512
Directory /workspace/33.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/33.rom_ctrl_corrupt_sig_fatal_chk.676273661
Short name T298
Test name
Test status
Simulation time 98922371400 ps
CPU time 196.6 seconds
Started May 23 01:43:14 PM PDT 24
Finished May 23 01:46:34 PM PDT 24
Peak memory 238064 kb
Host smart-5ee52792-c2d2-40b2-b973-e9a82c628ef5
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=676273661 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_c
orrupt_sig_fatal_chk.676273661
Directory /workspace/33.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/33.rom_ctrl_kmac_err_chk.1669044150
Short name T231
Test name
Test status
Simulation time 4405579012 ps
CPU time 22.43 seconds
Started May 23 01:43:15 PM PDT 24
Finished May 23 01:43:42 PM PDT 24
Peak memory 211416 kb
Host smart-3d959da4-fedd-4f56-ae15-8b7ad8b91d27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1669044150 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_kmac_err_chk.1669044150
Directory /workspace/33.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/33.rom_ctrl_max_throughput_chk.283761996
Short name T40
Test name
Test status
Simulation time 2486658290 ps
CPU time 12.04 seconds
Started May 23 01:43:12 PM PDT 24
Finished May 23 01:43:24 PM PDT 24
Peak memory 211188 kb
Host smart-4fd20abe-695b-43ed-b9ab-f4649d0f7264
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=283761996 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_max_throughput_chk.283761996
Directory /workspace/33.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/33.rom_ctrl_smoke.979339969
Short name T274
Test name
Test status
Simulation time 3557794537 ps
CPU time 20.9 seconds
Started May 23 01:43:15 PM PDT 24
Finished May 23 01:43:40 PM PDT 24
Peak memory 219348 kb
Host smart-733190d5-5e9d-4071-bef3-0339c3055b8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=979339969 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_smoke.979339969
Directory /workspace/33.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/33.rom_ctrl_stress_all.2286925513
Short name T264
Test name
Test status
Simulation time 9071254665 ps
CPU time 86.2 seconds
Started May 23 01:43:14 PM PDT 24
Finished May 23 01:44:45 PM PDT 24
Peak memory 216252 kb
Host smart-4d87de36-ae57-4b29-877f-9b2601ba564d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2286925513 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 33.rom_ctrl_stress_all.2286925513
Directory /workspace/33.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/34.rom_ctrl_alert_test.1636834397
Short name T351
Test name
Test status
Simulation time 2118213092 ps
CPU time 16.36 seconds
Started May 23 01:43:17 PM PDT 24
Finished May 23 01:43:38 PM PDT 24
Peak memory 211232 kb
Host smart-4e09a1e6-005b-4e16-a74a-11cb68dff6b1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1636834397 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_alert_test.1636834397
Directory /workspace/34.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/34.rom_ctrl_corrupt_sig_fatal_chk.970434914
Short name T44
Test name
Test status
Simulation time 66806032087 ps
CPU time 326.99 seconds
Started May 23 01:43:15 PM PDT 24
Finished May 23 01:48:45 PM PDT 24
Peak memory 224712 kb
Host smart-4e45cb92-32e7-4b3a-a93b-a37b60cb97ad
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=970434914 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_c
orrupt_sig_fatal_chk.970434914
Directory /workspace/34.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/34.rom_ctrl_kmac_err_chk.2808577243
Short name T184
Test name
Test status
Simulation time 8510855261 ps
CPU time 32.96 seconds
Started May 23 01:43:16 PM PDT 24
Finished May 23 01:43:53 PM PDT 24
Peak memory 212680 kb
Host smart-11c371f1-3ae5-43a9-892f-784ed960a87c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2808577243 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_kmac_err_chk.2808577243
Directory /workspace/34.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/34.rom_ctrl_max_throughput_chk.3298212731
Short name T361
Test name
Test status
Simulation time 10113765185 ps
CPU time 15.77 seconds
Started May 23 01:43:14 PM PDT 24
Finished May 23 01:43:34 PM PDT 24
Peak memory 211196 kb
Host smart-beb7ec45-b7b0-460f-a323-580c5a1110be
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3298212731 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_max_throughput_chk.3298212731
Directory /workspace/34.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/34.rom_ctrl_smoke.3950403154
Short name T4
Test name
Test status
Simulation time 4187621002 ps
CPU time 34.6 seconds
Started May 23 01:43:17 PM PDT 24
Finished May 23 01:43:55 PM PDT 24
Peak memory 213540 kb
Host smart-6a1db2ac-cfdb-4b13-9da3-83ffef75546f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3950403154 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_smoke.3950403154
Directory /workspace/34.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/34.rom_ctrl_stress_all.3693475733
Short name T221
Test name
Test status
Simulation time 4396208176 ps
CPU time 28.24 seconds
Started May 23 01:43:13 PM PDT 24
Finished May 23 01:43:44 PM PDT 24
Peak memory 219484 kb
Host smart-019f3c8e-5d95-4048-9878-46d84d4ec06e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3693475733 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 34.rom_ctrl_stress_all.3693475733
Directory /workspace/34.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/34.rom_ctrl_stress_all_with_rand_reset.2463979537
Short name T56
Test name
Test status
Simulation time 145379212615 ps
CPU time 4990.21 seconds
Started May 23 01:43:17 PM PDT 24
Finished May 23 03:06:32 PM PDT 24
Peak memory 235932 kb
Host smart-f2435a53-4c8c-4748-b24a-bbf3739ce78f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2463979537 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_stress_all_with_rand_reset.2463979537
Directory /workspace/34.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.rom_ctrl_alert_test.2102075256
Short name T277
Test name
Test status
Simulation time 5958780322 ps
CPU time 12.93 seconds
Started May 23 01:43:16 PM PDT 24
Finished May 23 01:43:33 PM PDT 24
Peak memory 211288 kb
Host smart-32ecab7a-4416-4261-b2c4-dc7b9448dd6f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2102075256 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_alert_test.2102075256
Directory /workspace/35.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/35.rom_ctrl_corrupt_sig_fatal_chk.440751644
Short name T28
Test name
Test status
Simulation time 8341953658 ps
CPU time 52.06 seconds
Started May 23 01:43:15 PM PDT 24
Finished May 23 01:44:11 PM PDT 24
Peak memory 212564 kb
Host smart-588bb5f3-ab08-4594-9c41-da812e5eb31a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=440751644 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_c
orrupt_sig_fatal_chk.440751644
Directory /workspace/35.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/35.rom_ctrl_kmac_err_chk.1195997564
Short name T312
Test name
Test status
Simulation time 692570606 ps
CPU time 9.3 seconds
Started May 23 01:43:17 PM PDT 24
Finished May 23 01:43:31 PM PDT 24
Peak memory 211788 kb
Host smart-27d880ec-5362-4a36-8220-34453980a4af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1195997564 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_kmac_err_chk.1195997564
Directory /workspace/35.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/35.rom_ctrl_max_throughput_chk.1806040387
Short name T302
Test name
Test status
Simulation time 2060087089 ps
CPU time 17.54 seconds
Started May 23 01:43:14 PM PDT 24
Finished May 23 01:43:36 PM PDT 24
Peak memory 211068 kb
Host smart-73c6363e-cd5d-425f-bbb5-494a3766e27c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1806040387 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_max_throughput_chk.1806040387
Directory /workspace/35.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/35.rom_ctrl_smoke.50541145
Short name T284
Test name
Test status
Simulation time 370535034 ps
CPU time 10.08 seconds
Started May 23 01:43:17 PM PDT 24
Finished May 23 01:43:32 PM PDT 24
Peak memory 219288 kb
Host smart-06b22b98-6c62-41bc-825a-5e46e6111dd1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=50541145 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_smoke.50541145
Directory /workspace/35.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/35.rom_ctrl_stress_all.3608567210
Short name T363
Test name
Test status
Simulation time 13169259828 ps
CPU time 48.26 seconds
Started May 23 01:43:12 PM PDT 24
Finished May 23 01:44:02 PM PDT 24
Peak memory 219440 kb
Host smart-6975060f-83b8-4f6c-8762-02e57a274fe3
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3608567210 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 35.rom_ctrl_stress_all.3608567210
Directory /workspace/35.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/36.rom_ctrl_alert_test.721234318
Short name T185
Test name
Test status
Simulation time 4741180486 ps
CPU time 11.38 seconds
Started May 23 01:43:17 PM PDT 24
Finished May 23 01:43:32 PM PDT 24
Peak memory 211340 kb
Host smart-50c13987-28a1-4d91-aab9-f4470207175c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=721234318 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_alert_test.721234318
Directory /workspace/36.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/36.rom_ctrl_corrupt_sig_fatal_chk.1781208180
Short name T320
Test name
Test status
Simulation time 28424906767 ps
CPU time 252.76 seconds
Started May 23 01:43:12 PM PDT 24
Finished May 23 01:47:27 PM PDT 24
Peak memory 212564 kb
Host smart-6ad29c99-ce8c-46ad-93d0-579be041fe59
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1781208180 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_
corrupt_sig_fatal_chk.1781208180
Directory /workspace/36.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/36.rom_ctrl_kmac_err_chk.359140409
Short name T236
Test name
Test status
Simulation time 19086022041 ps
CPU time 29.47 seconds
Started May 23 01:43:17 PM PDT 24
Finished May 23 01:43:51 PM PDT 24
Peak memory 212364 kb
Host smart-6dc7dac6-f45d-49f2-b66b-2ae06885bbf0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=359140409 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_kmac_err_chk.359140409
Directory /workspace/36.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/36.rom_ctrl_max_throughput_chk.1530153670
Short name T250
Test name
Test status
Simulation time 1987682947 ps
CPU time 15.91 seconds
Started May 23 01:43:15 PM PDT 24
Finished May 23 01:43:35 PM PDT 24
Peak memory 211096 kb
Host smart-ba8cd449-56c8-4538-99d5-db4c0e3994dd
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1530153670 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_max_throughput_chk.1530153670
Directory /workspace/36.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/36.rom_ctrl_smoke.695334130
Short name T170
Test name
Test status
Simulation time 9176745384 ps
CPU time 26.55 seconds
Started May 23 01:43:15 PM PDT 24
Finished May 23 01:43:46 PM PDT 24
Peak memory 219420 kb
Host smart-bd78a983-1e16-4873-a110-f9affb0eda05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=695334130 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_smoke.695334130
Directory /workspace/36.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/36.rom_ctrl_stress_all.3303158468
Short name T5
Test name
Test status
Simulation time 5081267599 ps
CPU time 19.57 seconds
Started May 23 01:43:16 PM PDT 24
Finished May 23 01:43:40 PM PDT 24
Peak memory 219344 kb
Host smart-43b81b7c-d82f-49ba-b041-8beaae769cfc
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3303158468 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 36.rom_ctrl_stress_all.3303158468
Directory /workspace/36.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/37.rom_ctrl_alert_test.1778082315
Short name T247
Test name
Test status
Simulation time 15297742835 ps
CPU time 16.04 seconds
Started May 23 01:43:17 PM PDT 24
Finished May 23 01:43:37 PM PDT 24
Peak memory 211324 kb
Host smart-c3e55141-a7a2-4990-b379-8b3ec87bdb58
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1778082315 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_alert_test.1778082315
Directory /workspace/37.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/37.rom_ctrl_corrupt_sig_fatal_chk.155151935
Short name T26
Test name
Test status
Simulation time 4721250492 ps
CPU time 149.67 seconds
Started May 23 01:43:17 PM PDT 24
Finished May 23 01:45:50 PM PDT 24
Peak memory 222092 kb
Host smart-75c07c5d-b6d2-493c-96ce-67943fcead17
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=155151935 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_c
orrupt_sig_fatal_chk.155151935
Directory /workspace/37.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/37.rom_ctrl_kmac_err_chk.1830090292
Short name T134
Test name
Test status
Simulation time 41630001184 ps
CPU time 32.54 seconds
Started May 23 01:43:17 PM PDT 24
Finished May 23 01:43:54 PM PDT 24
Peak memory 212180 kb
Host smart-da3d1851-4cf5-44cb-a163-8f9234e22d89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1830090292 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_kmac_err_chk.1830090292
Directory /workspace/37.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/37.rom_ctrl_max_throughput_chk.3622873609
Short name T198
Test name
Test status
Simulation time 1111351631 ps
CPU time 11.98 seconds
Started May 23 01:43:17 PM PDT 24
Finished May 23 01:43:33 PM PDT 24
Peak memory 211048 kb
Host smart-b1036342-af18-4c20-90a8-8add65a2e826
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3622873609 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_max_throughput_chk.3622873609
Directory /workspace/37.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/37.rom_ctrl_smoke.1527205148
Short name T356
Test name
Test status
Simulation time 2652849859 ps
CPU time 26.45 seconds
Started May 23 01:43:14 PM PDT 24
Finished May 23 01:43:44 PM PDT 24
Peak memory 212880 kb
Host smart-9a1be7ac-0cf0-48e4-a8c7-2c13db732e7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1527205148 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_smoke.1527205148
Directory /workspace/37.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/37.rom_ctrl_stress_all.1002216895
Short name T10
Test name
Test status
Simulation time 404436789 ps
CPU time 11.77 seconds
Started May 23 01:43:18 PM PDT 24
Finished May 23 01:43:34 PM PDT 24
Peak memory 214152 kb
Host smart-7018c265-349a-4c3a-b377-8f2b02eea849
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1002216895 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 37.rom_ctrl_stress_all.1002216895
Directory /workspace/37.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/38.rom_ctrl_alert_test.1619777424
Short name T145
Test name
Test status
Simulation time 2187232622 ps
CPU time 17.19 seconds
Started May 23 01:43:20 PM PDT 24
Finished May 23 01:43:41 PM PDT 24
Peak memory 211376 kb
Host smart-d1e1b502-7dfc-4d10-a1a5-bd1795cbdcae
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1619777424 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_alert_test.1619777424
Directory /workspace/38.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/38.rom_ctrl_corrupt_sig_fatal_chk.718138581
Short name T141
Test name
Test status
Simulation time 93217932614 ps
CPU time 223.03 seconds
Started May 23 01:43:20 PM PDT 24
Finished May 23 01:47:06 PM PDT 24
Peak memory 236912 kb
Host smart-abc8746f-d3d9-4f76-b93d-265297f583cc
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=718138581 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_c
orrupt_sig_fatal_chk.718138581
Directory /workspace/38.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/38.rom_ctrl_kmac_err_chk.1953064180
Short name T355
Test name
Test status
Simulation time 169197308 ps
CPU time 9.52 seconds
Started May 23 01:43:20 PM PDT 24
Finished May 23 01:43:33 PM PDT 24
Peak memory 212680 kb
Host smart-4440fee5-52e0-4d07-90be-e8e0c474d33c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1953064180 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_kmac_err_chk.1953064180
Directory /workspace/38.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/38.rom_ctrl_max_throughput_chk.2767476628
Short name T343
Test name
Test status
Simulation time 500953832 ps
CPU time 8.67 seconds
Started May 23 01:43:20 PM PDT 24
Finished May 23 01:43:32 PM PDT 24
Peak memory 211100 kb
Host smart-3da1e6a4-a312-4768-946a-bdae256d72e3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2767476628 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_max_throughput_chk.2767476628
Directory /workspace/38.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/38.rom_ctrl_smoke.3132409762
Short name T151
Test name
Test status
Simulation time 876669071 ps
CPU time 16.21 seconds
Started May 23 01:43:18 PM PDT 24
Finished May 23 01:43:38 PM PDT 24
Peak memory 219096 kb
Host smart-a02ef119-d6e1-45f8-86b4-8e93544022da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3132409762 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_smoke.3132409762
Directory /workspace/38.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/38.rom_ctrl_stress_all.1016102225
Short name T190
Test name
Test status
Simulation time 1608081097 ps
CPU time 22.86 seconds
Started May 23 01:43:17 PM PDT 24
Finished May 23 01:43:44 PM PDT 24
Peak memory 214548 kb
Host smart-77619aa1-0cda-4601-9791-524b8d9a813c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1016102225 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 38.rom_ctrl_stress_all.1016102225
Directory /workspace/38.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/38.rom_ctrl_stress_all_with_rand_reset.3284946536
Short name T53
Test name
Test status
Simulation time 159620891050 ps
CPU time 5140.89 seconds
Started May 23 01:43:15 PM PDT 24
Finished May 23 03:09:00 PM PDT 24
Peak memory 235916 kb
Host smart-b84adb09-6748-4eab-916a-2f6d5877f09b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3284946536 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_stress_all_with_rand_reset.3284946536
Directory /workspace/38.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.rom_ctrl_alert_test.4038942215
Short name T128
Test name
Test status
Simulation time 246392343 ps
CPU time 4.25 seconds
Started May 23 01:43:21 PM PDT 24
Finished May 23 01:43:28 PM PDT 24
Peak memory 211232 kb
Host smart-995685b3-1a3a-4ab9-a678-0d9f57baec49
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4038942215 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_alert_test.4038942215
Directory /workspace/39.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/39.rom_ctrl_corrupt_sig_fatal_chk.3851470182
Short name T263
Test name
Test status
Simulation time 63363729688 ps
CPU time 163.11 seconds
Started May 23 01:43:17 PM PDT 24
Finished May 23 01:46:04 PM PDT 24
Peak memory 236804 kb
Host smart-948de3f2-736d-4caf-bca4-c0bac019d31f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3851470182 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_
corrupt_sig_fatal_chk.3851470182
Directory /workspace/39.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/39.rom_ctrl_kmac_err_chk.851671427
Short name T288
Test name
Test status
Simulation time 13955715328 ps
CPU time 30.64 seconds
Started May 23 01:43:14 PM PDT 24
Finished May 23 01:43:49 PM PDT 24
Peak memory 212128 kb
Host smart-e49ed7db-e649-451c-a592-6061f7cebcb2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=851671427 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_kmac_err_chk.851671427
Directory /workspace/39.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/39.rom_ctrl_max_throughput_chk.3814289413
Short name T3
Test name
Test status
Simulation time 861543265 ps
CPU time 8.6 seconds
Started May 23 01:43:16 PM PDT 24
Finished May 23 01:43:29 PM PDT 24
Peak memory 211052 kb
Host smart-a219ad2c-62b1-4a50-ad8f-3051c3baab6c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3814289413 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_max_throughput_chk.3814289413
Directory /workspace/39.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/39.rom_ctrl_smoke.3874111786
Short name T340
Test name
Test status
Simulation time 184895097 ps
CPU time 10.43 seconds
Started May 23 01:43:21 PM PDT 24
Finished May 23 01:43:34 PM PDT 24
Peak memory 219316 kb
Host smart-91bb29b5-aa8d-48bf-9f0a-9b1e132c141d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3874111786 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_smoke.3874111786
Directory /workspace/39.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/39.rom_ctrl_stress_all.26958163
Short name T80
Test name
Test status
Simulation time 4144237498 ps
CPU time 51.5 seconds
Started May 23 01:43:17 PM PDT 24
Finished May 23 01:44:12 PM PDT 24
Peak memory 215524 kb
Host smart-56ca0e44-3f01-4a7a-a0e9-2dcbdc2fe5a5
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26958163 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +U
VM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n
ame 39.rom_ctrl_stress_all.26958163
Directory /workspace/39.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/4.rom_ctrl_alert_test.4246527181
Short name T243
Test name
Test status
Simulation time 7891602561 ps
CPU time 16.09 seconds
Started May 23 01:42:27 PM PDT 24
Finished May 23 01:42:45 PM PDT 24
Peak memory 211348 kb
Host smart-2fd7c442-a0aa-46fe-9c7a-bd973305df6c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4246527181 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_alert_test.4246527181
Directory /workspace/4.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/4.rom_ctrl_corrupt_sig_fatal_chk.1334486490
Short name T309
Test name
Test status
Simulation time 129135123566 ps
CPU time 324.94 seconds
Started May 23 01:42:23 PM PDT 24
Finished May 23 01:47:49 PM PDT 24
Peak memory 228700 kb
Host smart-c5cb37ed-9af4-4527-a768-b5b61b8ed3f5
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1334486490 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_c
orrupt_sig_fatal_chk.1334486490
Directory /workspace/4.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/4.rom_ctrl_kmac_err_chk.2374253272
Short name T127
Test name
Test status
Simulation time 4447557933 ps
CPU time 16.54 seconds
Started May 23 01:42:29 PM PDT 24
Finished May 23 01:42:47 PM PDT 24
Peak memory 212436 kb
Host smart-bbc97007-4d07-4a58-88e7-f41ee8f1a905
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2374253272 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_kmac_err_chk.2374253272
Directory /workspace/4.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/4.rom_ctrl_max_throughput_chk.1503440388
Short name T14
Test name
Test status
Simulation time 475615006 ps
CPU time 5.45 seconds
Started May 23 01:42:26 PM PDT 24
Finished May 23 01:42:33 PM PDT 24
Peak memory 211008 kb
Host smart-dab488be-f40d-4d7a-b8f5-08ada4f6ee18
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1503440388 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_max_throughput_chk.1503440388
Directory /workspace/4.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/4.rom_ctrl_sec_cm.3886495282
Short name T36
Test name
Test status
Simulation time 5475473664 ps
CPU time 108.87 seconds
Started May 23 01:42:22 PM PDT 24
Finished May 23 01:44:13 PM PDT 24
Peak memory 236848 kb
Host smart-71375ac7-55b7-4558-97f6-e2ff27a881b5
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3886495282 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_sec_cm.3886495282
Directory /workspace/4.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/4.rom_ctrl_smoke.3224832440
Short name T310
Test name
Test status
Simulation time 4655527083 ps
CPU time 27.67 seconds
Started May 23 01:42:23 PM PDT 24
Finished May 23 01:42:52 PM PDT 24
Peak memory 219448 kb
Host smart-9d487ef7-06f6-4f5d-a6a1-8514762b80aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3224832440 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_smoke.3224832440
Directory /workspace/4.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/4.rom_ctrl_stress_all.3202884887
Short name T99
Test name
Test status
Simulation time 3937531325 ps
CPU time 18.72 seconds
Started May 23 01:42:26 PM PDT 24
Finished May 23 01:42:46 PM PDT 24
Peak memory 212076 kb
Host smart-45c03c9f-308c-4618-b0f6-653edab1fd45
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3202884887 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 4.rom_ctrl_stress_all.3202884887
Directory /workspace/4.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/40.rom_ctrl_corrupt_sig_fatal_chk.4237061905
Short name T29
Test name
Test status
Simulation time 86917324826 ps
CPU time 238.07 seconds
Started May 23 01:43:21 PM PDT 24
Finished May 23 01:47:22 PM PDT 24
Peak memory 236812 kb
Host smart-7dd98f3a-1f0a-4b0c-87d7-0be29dcb64b7
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4237061905 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_
corrupt_sig_fatal_chk.4237061905
Directory /workspace/40.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/40.rom_ctrl_kmac_err_chk.2048251789
Short name T24
Test name
Test status
Simulation time 2970433713 ps
CPU time 26.95 seconds
Started May 23 01:43:20 PM PDT 24
Finished May 23 01:43:51 PM PDT 24
Peak memory 212084 kb
Host smart-53a2f292-d041-44b5-8383-69d2848f7a7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2048251789 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_kmac_err_chk.2048251789
Directory /workspace/40.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/40.rom_ctrl_max_throughput_chk.917272400
Short name T273
Test name
Test status
Simulation time 13139790531 ps
CPU time 11.55 seconds
Started May 23 01:43:22 PM PDT 24
Finished May 23 01:43:36 PM PDT 24
Peak memory 211196 kb
Host smart-5fb62883-31e9-47f1-b2b4-c8ab3f847c7f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=917272400 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_max_throughput_chk.917272400
Directory /workspace/40.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/40.rom_ctrl_smoke.237890582
Short name T146
Test name
Test status
Simulation time 1683316709 ps
CPU time 20.83 seconds
Started May 23 01:43:16 PM PDT 24
Finished May 23 01:43:41 PM PDT 24
Peak memory 213236 kb
Host smart-17cee8cd-3a17-4d6f-a0e9-0fa219bc522f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=237890582 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_smoke.237890582
Directory /workspace/40.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/40.rom_ctrl_stress_all.3341074937
Short name T140
Test name
Test status
Simulation time 402447475 ps
CPU time 22.73 seconds
Started May 23 01:43:18 PM PDT 24
Finished May 23 01:43:45 PM PDT 24
Peak memory 215848 kb
Host smart-c0ad26eb-7844-4f2c-bc15-ba79cd593a15
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3341074937 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 40.rom_ctrl_stress_all.3341074937
Directory /workspace/40.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/41.rom_ctrl_alert_test.1875711441
Short name T265
Test name
Test status
Simulation time 2634519046 ps
CPU time 11.43 seconds
Started May 23 01:43:22 PM PDT 24
Finished May 23 01:43:36 PM PDT 24
Peak memory 211316 kb
Host smart-dc276803-9827-46a5-b561-4cd165a17008
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1875711441 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_alert_test.1875711441
Directory /workspace/41.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/41.rom_ctrl_corrupt_sig_fatal_chk.3032076144
Short name T168
Test name
Test status
Simulation time 22367198018 ps
CPU time 120.43 seconds
Started May 23 01:43:23 PM PDT 24
Finished May 23 01:45:26 PM PDT 24
Peak memory 212624 kb
Host smart-e673b174-f87e-4d29-a647-29fcd3bfa4f6
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3032076144 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_
corrupt_sig_fatal_chk.3032076144
Directory /workspace/41.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/41.rom_ctrl_kmac_err_chk.4050440367
Short name T262
Test name
Test status
Simulation time 3687692140 ps
CPU time 20.32 seconds
Started May 23 01:43:15 PM PDT 24
Finished May 23 01:43:40 PM PDT 24
Peak memory 211988 kb
Host smart-74a98c08-0ee6-447c-afd9-86cf7cb0b4e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4050440367 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_kmac_err_chk.4050440367
Directory /workspace/41.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/41.rom_ctrl_max_throughput_chk.1822768531
Short name T123
Test name
Test status
Simulation time 102536513 ps
CPU time 5.63 seconds
Started May 23 01:43:20 PM PDT 24
Finished May 23 01:43:29 PM PDT 24
Peak memory 211108 kb
Host smart-a6aebe69-14e4-428c-9e0e-60e9a979b069
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1822768531 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_max_throughput_chk.1822768531
Directory /workspace/41.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/41.rom_ctrl_smoke.2384236096
Short name T197
Test name
Test status
Simulation time 3197000135 ps
CPU time 30.52 seconds
Started May 23 01:43:23 PM PDT 24
Finished May 23 01:43:56 PM PDT 24
Peak memory 219456 kb
Host smart-19eb0efb-42cc-4cdb-836b-c855492c3f9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2384236096 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_smoke.2384236096
Directory /workspace/41.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/41.rom_ctrl_stress_all.710078194
Short name T339
Test name
Test status
Simulation time 32477609313 ps
CPU time 75.12 seconds
Started May 23 01:43:20 PM PDT 24
Finished May 23 01:44:39 PM PDT 24
Peak memory 219440 kb
Host smart-a652503f-301a-4d41-8b4c-2bc25c28dede
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=710078194 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 41.rom_ctrl_stress_all.710078194
Directory /workspace/41.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/41.rom_ctrl_stress_all_with_rand_reset.2284076319
Short name T52
Test name
Test status
Simulation time 25671192696 ps
CPU time 1920.72 seconds
Started May 23 01:43:24 PM PDT 24
Finished May 23 02:15:27 PM PDT 24
Peak memory 227528 kb
Host smart-2f0e5951-3d3c-4248-b7bc-bb1bc42b4fb9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2284076319 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_stress_all_with_rand_reset.2284076319
Directory /workspace/41.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.rom_ctrl_alert_test.3046279519
Short name T33
Test name
Test status
Simulation time 1877446843 ps
CPU time 14.49 seconds
Started May 23 01:43:33 PM PDT 24
Finished May 23 01:43:49 PM PDT 24
Peak memory 211244 kb
Host smart-e0f3363e-4710-467a-a5e6-bbf65d8ad2d6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3046279519 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_alert_test.3046279519
Directory /workspace/42.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/42.rom_ctrl_corrupt_sig_fatal_chk.3794126189
Short name T215
Test name
Test status
Simulation time 23947717219 ps
CPU time 246.76 seconds
Started May 23 01:43:23 PM PDT 24
Finished May 23 01:47:32 PM PDT 24
Peak memory 230904 kb
Host smart-a9acb019-bd4f-4d93-b8c1-87cfacb03b69
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3794126189 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_
corrupt_sig_fatal_chk.3794126189
Directory /workspace/42.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/42.rom_ctrl_kmac_err_chk.3324631224
Short name T188
Test name
Test status
Simulation time 4597003967 ps
CPU time 16.99 seconds
Started May 23 01:43:22 PM PDT 24
Finished May 23 01:43:41 PM PDT 24
Peak memory 212388 kb
Host smart-05498fd4-d1a3-44a1-95e0-b6b187fe1e4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3324631224 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_kmac_err_chk.3324631224
Directory /workspace/42.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/42.rom_ctrl_max_throughput_chk.346541646
Short name T245
Test name
Test status
Simulation time 572021575 ps
CPU time 8.51 seconds
Started May 23 01:43:22 PM PDT 24
Finished May 23 01:43:33 PM PDT 24
Peak memory 211092 kb
Host smart-943a16c6-b99d-45bc-9a5e-eeea4f89f1a4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=346541646 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_max_throughput_chk.346541646
Directory /workspace/42.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/42.rom_ctrl_smoke.3950177872
Short name T352
Test name
Test status
Simulation time 185254161 ps
CPU time 10.07 seconds
Started May 23 01:43:35 PM PDT 24
Finished May 23 01:43:46 PM PDT 24
Peak memory 219328 kb
Host smart-67ba9b28-bac7-4f2e-9971-8ad7306d1ea6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3950177872 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_smoke.3950177872
Directory /workspace/42.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/42.rom_ctrl_stress_all.448363523
Short name T244
Test name
Test status
Simulation time 18244926612 ps
CPU time 31.17 seconds
Started May 23 01:43:27 PM PDT 24
Finished May 23 01:44:00 PM PDT 24
Peak memory 219440 kb
Host smart-e5b9347d-720f-4fa6-94cc-49b2ffdeced4
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=448363523 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 42.rom_ctrl_stress_all.448363523
Directory /workspace/42.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/43.rom_ctrl_alert_test.3310723185
Short name T223
Test name
Test status
Simulation time 2009185408 ps
CPU time 15.89 seconds
Started May 23 01:43:35 PM PDT 24
Finished May 23 01:43:52 PM PDT 24
Peak memory 211244 kb
Host smart-4b3c2943-f518-4ec2-820c-393aa9e8b625
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3310723185 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_alert_test.3310723185
Directory /workspace/43.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/43.rom_ctrl_corrupt_sig_fatal_chk.1729549392
Short name T171
Test name
Test status
Simulation time 1779851735 ps
CPU time 74.1 seconds
Started May 23 01:43:28 PM PDT 24
Finished May 23 01:44:44 PM PDT 24
Peak memory 233720 kb
Host smart-e10e6ca8-b798-4662-9457-fb9bce8fd2a1
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1729549392 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_
corrupt_sig_fatal_chk.1729549392
Directory /workspace/43.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/43.rom_ctrl_kmac_err_chk.1670051847
Short name T157
Test name
Test status
Simulation time 1718379006 ps
CPU time 12.49 seconds
Started May 23 01:43:26 PM PDT 24
Finished May 23 01:43:41 PM PDT 24
Peak memory 211744 kb
Host smart-6f31b1d4-51e0-43f4-9ae8-3367a4c07d11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1670051847 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_kmac_err_chk.1670051847
Directory /workspace/43.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/43.rom_ctrl_max_throughput_chk.2365931104
Short name T216
Test name
Test status
Simulation time 1685536944 ps
CPU time 14.88 seconds
Started May 23 01:43:28 PM PDT 24
Finished May 23 01:43:46 PM PDT 24
Peak memory 211096 kb
Host smart-fbb4d872-791c-41cb-81f8-571eed5adad3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2365931104 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_max_throughput_chk.2365931104
Directory /workspace/43.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/43.rom_ctrl_smoke.2552395415
Short name T268
Test name
Test status
Simulation time 647660906 ps
CPU time 10.29 seconds
Started May 23 01:43:35 PM PDT 24
Finished May 23 01:43:46 PM PDT 24
Peak memory 213336 kb
Host smart-e12193c6-504e-4f37-b9e6-9982d958125e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2552395415 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_smoke.2552395415
Directory /workspace/43.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/43.rom_ctrl_stress_all.3385028527
Short name T172
Test name
Test status
Simulation time 139335781 ps
CPU time 6.71 seconds
Started May 23 01:43:28 PM PDT 24
Finished May 23 01:43:37 PM PDT 24
Peak memory 211160 kb
Host smart-a10dc689-311f-4eb4-9f4b-7dda6cfafcf6
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3385028527 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 43.rom_ctrl_stress_all.3385028527
Directory /workspace/43.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/44.rom_ctrl_alert_test.655310606
Short name T260
Test name
Test status
Simulation time 431687383 ps
CPU time 7.06 seconds
Started May 23 01:43:23 PM PDT 24
Finished May 23 01:43:33 PM PDT 24
Peak memory 211212 kb
Host smart-6c1609ae-d5ae-4e09-acb2-9199bfa8105e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=655310606 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_alert_test.655310606
Directory /workspace/44.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/44.rom_ctrl_corrupt_sig_fatal_chk.2835772936
Short name T354
Test name
Test status
Simulation time 21666955262 ps
CPU time 181.37 seconds
Started May 23 01:43:27 PM PDT 24
Finished May 23 01:46:31 PM PDT 24
Peak memory 212504 kb
Host smart-3c4d3f18-2b5f-48a0-ac51-d4c6e5eecbdf
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2835772936 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_
corrupt_sig_fatal_chk.2835772936
Directory /workspace/44.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/44.rom_ctrl_kmac_err_chk.886665052
Short name T350
Test name
Test status
Simulation time 2640225888 ps
CPU time 20 seconds
Started May 23 01:43:34 PM PDT 24
Finished May 23 01:43:55 PM PDT 24
Peak memory 211820 kb
Host smart-f8a0b96d-3ba4-4ab2-9344-e1ce0f7d8667
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=886665052 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_kmac_err_chk.886665052
Directory /workspace/44.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/44.rom_ctrl_max_throughput_chk.4249412802
Short name T322
Test name
Test status
Simulation time 3952597460 ps
CPU time 11.15 seconds
Started May 23 01:43:23 PM PDT 24
Finished May 23 01:43:36 PM PDT 24
Peak memory 211200 kb
Host smart-6082c552-bf2b-4ece-aed2-4fb0bd3e61c0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4249412802 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_max_throughput_chk.4249412802
Directory /workspace/44.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/44.rom_ctrl_smoke.3821458295
Short name T257
Test name
Test status
Simulation time 3677173091 ps
CPU time 28.82 seconds
Started May 23 01:43:29 PM PDT 24
Finished May 23 01:44:00 PM PDT 24
Peak memory 219444 kb
Host smart-3433f3f0-b334-4ce1-9b9b-b4db70d61b24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3821458295 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_smoke.3821458295
Directory /workspace/44.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/44.rom_ctrl_stress_all.1845321832
Short name T15
Test name
Test status
Simulation time 320449937 ps
CPU time 11.86 seconds
Started May 23 01:43:26 PM PDT 24
Finished May 23 01:43:40 PM PDT 24
Peak memory 211028 kb
Host smart-46a25d49-cf7d-4a24-b36e-e01d4bd6779c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1845321832 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 44.rom_ctrl_stress_all.1845321832
Directory /workspace/44.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/45.rom_ctrl_alert_test.124162703
Short name T342
Test name
Test status
Simulation time 2138695726 ps
CPU time 10.42 seconds
Started May 23 01:43:32 PM PDT 24
Finished May 23 01:43:44 PM PDT 24
Peak memory 211244 kb
Host smart-6e87e81e-2f17-4cc3-8384-2860c4b82d73
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=124162703 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_alert_test.124162703
Directory /workspace/45.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/45.rom_ctrl_corrupt_sig_fatal_chk.3717125870
Short name T224
Test name
Test status
Simulation time 1306210095 ps
CPU time 84.97 seconds
Started May 23 01:43:34 PM PDT 24
Finished May 23 01:45:00 PM PDT 24
Peak memory 229088 kb
Host smart-81b15262-8619-464a-81f8-cebf730a0c71
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3717125870 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_
corrupt_sig_fatal_chk.3717125870
Directory /workspace/45.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/45.rom_ctrl_kmac_err_chk.3313223638
Short name T149
Test name
Test status
Simulation time 3528881313 ps
CPU time 32.35 seconds
Started May 23 01:43:23 PM PDT 24
Finished May 23 01:43:57 PM PDT 24
Peak memory 212068 kb
Host smart-5f5aad65-f0fc-424a-bab4-37a1f27f4ad5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3313223638 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_kmac_err_chk.3313223638
Directory /workspace/45.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/45.rom_ctrl_max_throughput_chk.3663809632
Short name T242
Test name
Test status
Simulation time 915904442 ps
CPU time 10.89 seconds
Started May 23 01:43:35 PM PDT 24
Finished May 23 01:43:47 PM PDT 24
Peak memory 211092 kb
Host smart-2bb56bc7-4807-4a1b-859e-25e7b148afc3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3663809632 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_max_throughput_chk.3663809632
Directory /workspace/45.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/45.rom_ctrl_smoke.2288227752
Short name T341
Test name
Test status
Simulation time 11225063643 ps
CPU time 27.09 seconds
Started May 23 01:43:26 PM PDT 24
Finished May 23 01:43:55 PM PDT 24
Peak memory 219460 kb
Host smart-9b84b463-b61d-4dc1-816b-390093fd7137
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2288227752 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_smoke.2288227752
Directory /workspace/45.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/46.rom_ctrl_alert_test.3432554517
Short name T360
Test name
Test status
Simulation time 2756208852 ps
CPU time 12.27 seconds
Started May 23 01:43:22 PM PDT 24
Finished May 23 01:43:37 PM PDT 24
Peak memory 211376 kb
Host smart-ef53e35c-51bd-44f0-8cf7-a80bb22b9824
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3432554517 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_alert_test.3432554517
Directory /workspace/46.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/46.rom_ctrl_kmac_err_chk.4123299334
Short name T214
Test name
Test status
Simulation time 3741077724 ps
CPU time 31.3 seconds
Started May 23 01:43:23 PM PDT 24
Finished May 23 01:43:56 PM PDT 24
Peak memory 211800 kb
Host smart-56dc5925-cf19-4b1f-94e9-b4ec479deada
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4123299334 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_kmac_err_chk.4123299334
Directory /workspace/46.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/46.rom_ctrl_max_throughput_chk.1328669684
Short name T285
Test name
Test status
Simulation time 143274540 ps
CPU time 6.62 seconds
Started May 23 01:43:30 PM PDT 24
Finished May 23 01:43:39 PM PDT 24
Peak memory 211100 kb
Host smart-6e74ad40-595d-487e-a865-b7939304527e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1328669684 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_max_throughput_chk.1328669684
Directory /workspace/46.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/46.rom_ctrl_smoke.1223937471
Short name T253
Test name
Test status
Simulation time 725998863 ps
CPU time 9.88 seconds
Started May 23 01:43:34 PM PDT 24
Finished May 23 01:43:46 PM PDT 24
Peak memory 213008 kb
Host smart-f6c88eef-efb2-44ee-be5f-4768c8369df7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1223937471 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_smoke.1223937471
Directory /workspace/46.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/46.rom_ctrl_stress_all.932037906
Short name T300
Test name
Test status
Simulation time 6976688665 ps
CPU time 58.21 seconds
Started May 23 01:43:29 PM PDT 24
Finished May 23 01:44:29 PM PDT 24
Peak memory 216896 kb
Host smart-bbe5b3f1-b7f3-4a56-973e-a0882a847a21
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=932037906 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 46.rom_ctrl_stress_all.932037906
Directory /workspace/46.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/47.rom_ctrl_alert_test.529909150
Short name T148
Test name
Test status
Simulation time 7714535428 ps
CPU time 16.11 seconds
Started May 23 01:43:27 PM PDT 24
Finished May 23 01:43:45 PM PDT 24
Peak memory 211376 kb
Host smart-3c9f4ab1-afcc-422f-923e-4b6a5f4354b0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=529909150 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_alert_test.529909150
Directory /workspace/47.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/47.rom_ctrl_corrupt_sig_fatal_chk.2244314791
Short name T182
Test name
Test status
Simulation time 38870909195 ps
CPU time 403.64 seconds
Started May 23 01:43:35 PM PDT 24
Finished May 23 01:50:20 PM PDT 24
Peak memory 237872 kb
Host smart-9e2a285e-05cc-4f4e-a9ae-a696fae4e2e8
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2244314791 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_
corrupt_sig_fatal_chk.2244314791
Directory /workspace/47.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/47.rom_ctrl_kmac_err_chk.966094352
Short name T7
Test name
Test status
Simulation time 4591106027 ps
CPU time 31.6 seconds
Started May 23 01:43:25 PM PDT 24
Finished May 23 01:43:59 PM PDT 24
Peak memory 212264 kb
Host smart-132b71b5-1726-4f6c-a32b-8b78f19c627d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=966094352 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_kmac_err_chk.966094352
Directory /workspace/47.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/47.rom_ctrl_max_throughput_chk.2023203536
Short name T144
Test name
Test status
Simulation time 2056717326 ps
CPU time 17.58 seconds
Started May 23 01:43:25 PM PDT 24
Finished May 23 01:43:44 PM PDT 24
Peak memory 211096 kb
Host smart-5b256d94-2865-4cb6-bb77-7e88321b1863
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2023203536 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_max_throughput_chk.2023203536
Directory /workspace/47.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/47.rom_ctrl_smoke.3804969812
Short name T166
Test name
Test status
Simulation time 352339679 ps
CPU time 12.12 seconds
Started May 23 01:43:30 PM PDT 24
Finished May 23 01:43:44 PM PDT 24
Peak memory 212800 kb
Host smart-4e206e14-87bb-4f98-bf0b-32b51d3c0e28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3804969812 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_smoke.3804969812
Directory /workspace/47.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/47.rom_ctrl_stress_all.1209815252
Short name T115
Test name
Test status
Simulation time 592975283 ps
CPU time 14.73 seconds
Started May 23 01:43:34 PM PDT 24
Finished May 23 01:43:50 PM PDT 24
Peak memory 214916 kb
Host smart-ef54f7b6-2c2b-4d12-ae8c-3cb363b13b35
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1209815252 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 47.rom_ctrl_stress_all.1209815252
Directory /workspace/47.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/48.rom_ctrl_alert_test.2070663362
Short name T195
Test name
Test status
Simulation time 1527545255 ps
CPU time 13.87 seconds
Started May 23 01:43:18 PM PDT 24
Finished May 23 01:43:36 PM PDT 24
Peak memory 211256 kb
Host smart-089972b1-a037-47da-8d96-abd21e34d1d6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2070663362 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_alert_test.2070663362
Directory /workspace/48.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/48.rom_ctrl_corrupt_sig_fatal_chk.3113604821
Short name T281
Test name
Test status
Simulation time 24578770358 ps
CPU time 280.85 seconds
Started May 23 01:43:29 PM PDT 24
Finished May 23 01:48:13 PM PDT 24
Peak memory 237860 kb
Host smart-def220c1-671a-4ac0-9ce3-112c812d5254
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3113604821 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_
corrupt_sig_fatal_chk.3113604821
Directory /workspace/48.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/48.rom_ctrl_kmac_err_chk.3306737457
Short name T199
Test name
Test status
Simulation time 9041216439 ps
CPU time 32.63 seconds
Started May 23 01:43:24 PM PDT 24
Finished May 23 01:43:59 PM PDT 24
Peak memory 211388 kb
Host smart-1edbe863-67ee-4712-9c67-0bbf88c736c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3306737457 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_kmac_err_chk.3306737457
Directory /workspace/48.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/48.rom_ctrl_max_throughput_chk.2148727892
Short name T213
Test name
Test status
Simulation time 3369999970 ps
CPU time 15.21 seconds
Started May 23 01:43:29 PM PDT 24
Finished May 23 01:43:46 PM PDT 24
Peak memory 211184 kb
Host smart-90c4c266-fc50-4bdb-aecd-aeb0fe5afe64
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2148727892 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_max_throughput_chk.2148727892
Directory /workspace/48.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/48.rom_ctrl_smoke.3553886721
Short name T344
Test name
Test status
Simulation time 7270997298 ps
CPU time 13.92 seconds
Started May 23 01:43:29 PM PDT 24
Finished May 23 01:43:46 PM PDT 24
Peak memory 214488 kb
Host smart-0768ed8b-41db-44f7-af7a-d7f422052d2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3553886721 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_smoke.3553886721
Directory /workspace/48.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/48.rom_ctrl_stress_all.4181814622
Short name T189
Test name
Test status
Simulation time 43309075078 ps
CPU time 74.07 seconds
Started May 23 01:43:30 PM PDT 24
Finished May 23 01:44:46 PM PDT 24
Peak memory 217432 kb
Host smart-b4bc28e5-4466-4cf2-bb75-d20b8764cd9a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4181814622 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 48.rom_ctrl_stress_all.4181814622
Directory /workspace/48.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/49.rom_ctrl_alert_test.3481961652
Short name T34
Test name
Test status
Simulation time 1798807187 ps
CPU time 10.14 seconds
Started May 23 01:43:40 PM PDT 24
Finished May 23 01:43:51 PM PDT 24
Peak memory 211220 kb
Host smart-21ce4b82-7943-4377-a2f0-269a82c3e2c7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3481961652 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_alert_test.3481961652
Directory /workspace/49.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/49.rom_ctrl_corrupt_sig_fatal_chk.3715778263
Short name T114
Test name
Test status
Simulation time 5154779816 ps
CPU time 92.75 seconds
Started May 23 01:43:35 PM PDT 24
Finished May 23 01:45:09 PM PDT 24
Peak memory 232808 kb
Host smart-e9a53c94-bd61-4d68-9cc2-b6cace77c570
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3715778263 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_
corrupt_sig_fatal_chk.3715778263
Directory /workspace/49.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/49.rom_ctrl_kmac_err_chk.2187448896
Short name T173
Test name
Test status
Simulation time 3062807376 ps
CPU time 15.27 seconds
Started May 23 01:43:24 PM PDT 24
Finished May 23 01:43:41 PM PDT 24
Peak memory 212092 kb
Host smart-3633a6e3-31ee-4d60-8fad-fea88f888482
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2187448896 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_kmac_err_chk.2187448896
Directory /workspace/49.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/49.rom_ctrl_max_throughput_chk.2322886442
Short name T160
Test name
Test status
Simulation time 23076335393 ps
CPU time 12.55 seconds
Started May 23 01:43:21 PM PDT 24
Finished May 23 01:43:36 PM PDT 24
Peak memory 211224 kb
Host smart-963b7ccc-1861-4992-8e98-a2ce11b9df82
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2322886442 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_max_throughput_chk.2322886442
Directory /workspace/49.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/49.rom_ctrl_smoke.2364709897
Short name T194
Test name
Test status
Simulation time 12180289850 ps
CPU time 26.96 seconds
Started May 23 01:43:34 PM PDT 24
Finished May 23 01:44:02 PM PDT 24
Peak memory 214108 kb
Host smart-0e85ff51-1534-4a5d-834f-72c8e135f48b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2364709897 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_smoke.2364709897
Directory /workspace/49.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/49.rom_ctrl_stress_all.4004812363
Short name T139
Test name
Test status
Simulation time 9153949763 ps
CPU time 80.73 seconds
Started May 23 01:43:27 PM PDT 24
Finished May 23 01:44:50 PM PDT 24
Peak memory 217292 kb
Host smart-8b730543-48bc-4e4f-845a-a2a9e937f783
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4004812363 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 49.rom_ctrl_stress_all.4004812363
Directory /workspace/49.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/5.rom_ctrl_alert_test.1177872514
Short name T269
Test name
Test status
Simulation time 87536112 ps
CPU time 4.24 seconds
Started May 23 01:42:25 PM PDT 24
Finished May 23 01:42:31 PM PDT 24
Peak memory 211228 kb
Host smart-b6a4f650-e82d-41ff-8914-ec1089965620
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1177872514 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_alert_test.1177872514
Directory /workspace/5.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/5.rom_ctrl_corrupt_sig_fatal_chk.4045211289
Short name T46
Test name
Test status
Simulation time 95388361373 ps
CPU time 222.7 seconds
Started May 23 01:42:21 PM PDT 24
Finished May 23 01:46:06 PM PDT 24
Peak memory 236172 kb
Host smart-91d4af1a-4ab0-4730-a2fe-dd2ff7255503
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4045211289 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_c
orrupt_sig_fatal_chk.4045211289
Directory /workspace/5.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/5.rom_ctrl_kmac_err_chk.2754078463
Short name T130
Test name
Test status
Simulation time 11824339870 ps
CPU time 27.18 seconds
Started May 23 01:42:23 PM PDT 24
Finished May 23 01:42:51 PM PDT 24
Peak memory 212264 kb
Host smart-4c87e96a-427b-4573-8013-6a146563e9a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2754078463 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_kmac_err_chk.2754078463
Directory /workspace/5.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/5.rom_ctrl_max_throughput_chk.1309470473
Short name T137
Test name
Test status
Simulation time 1418055551 ps
CPU time 9.87 seconds
Started May 23 01:42:26 PM PDT 24
Finished May 23 01:42:37 PM PDT 24
Peak memory 211096 kb
Host smart-1c486ab4-a180-4024-a88e-37f16c33b93f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1309470473 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_max_throughput_chk.1309470473
Directory /workspace/5.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/5.rom_ctrl_smoke.4099651516
Short name T278
Test name
Test status
Simulation time 745080064 ps
CPU time 10.4 seconds
Started May 23 01:42:24 PM PDT 24
Finished May 23 01:42:36 PM PDT 24
Peak memory 213216 kb
Host smart-04815af4-718f-4407-aeb2-35e1d00393f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4099651516 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_smoke.4099651516
Directory /workspace/5.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/5.rom_ctrl_stress_all.52782577
Short name T126
Test name
Test status
Simulation time 8201340140 ps
CPU time 19.65 seconds
Started May 23 01:42:23 PM PDT 24
Finished May 23 01:42:44 PM PDT 24
Peak memory 212516 kb
Host smart-4b8458c8-47bc-4303-a76c-2719bbb98c25
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52782577 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +U
VM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n
ame 5.rom_ctrl_stress_all.52782577
Directory /workspace/5.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/6.rom_ctrl_alert_test.2156401465
Short name T163
Test name
Test status
Simulation time 347607591 ps
CPU time 4.37 seconds
Started May 23 01:42:23 PM PDT 24
Finished May 23 01:42:29 PM PDT 24
Peak memory 211308 kb
Host smart-6ff3beff-fbb7-44fb-b4d0-b13cc2845d79
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2156401465 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_alert_test.2156401465
Directory /workspace/6.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/6.rom_ctrl_kmac_err_chk.119121253
Short name T308
Test name
Test status
Simulation time 17815584108 ps
CPU time 35.25 seconds
Started May 23 01:42:23 PM PDT 24
Finished May 23 01:43:00 PM PDT 24
Peak memory 212116 kb
Host smart-bce6d476-e15e-422d-970c-1012edb21dd2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=119121253 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_kmac_err_chk.119121253
Directory /workspace/6.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/6.rom_ctrl_max_throughput_chk.576072718
Short name T174
Test name
Test status
Simulation time 1542545868 ps
CPU time 14.43 seconds
Started May 23 01:42:21 PM PDT 24
Finished May 23 01:42:37 PM PDT 24
Peak memory 211052 kb
Host smart-223bc8eb-bc3d-49cf-a37b-4a5050ff8507
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=576072718 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_max_throughput_chk.576072718
Directory /workspace/6.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/6.rom_ctrl_smoke.1849150592
Short name T239
Test name
Test status
Simulation time 18713684070 ps
CPU time 34.7 seconds
Started May 23 01:42:22 PM PDT 24
Finished May 23 01:42:59 PM PDT 24
Peak memory 219428 kb
Host smart-2d35005d-973f-4579-b5d2-7eb7296f59c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1849150592 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_smoke.1849150592
Directory /workspace/6.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/6.rom_ctrl_stress_all.2190583912
Short name T296
Test name
Test status
Simulation time 4153835186 ps
CPU time 36.79 seconds
Started May 23 01:42:29 PM PDT 24
Finished May 23 01:43:07 PM PDT 24
Peak memory 219508 kb
Host smart-075e4fc0-b86d-4a75-b91a-7bf1139d2966
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2190583912 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 6.rom_ctrl_stress_all.2190583912
Directory /workspace/6.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/7.rom_ctrl_alert_test.3335666870
Short name T158
Test name
Test status
Simulation time 346273476 ps
CPU time 4.27 seconds
Started May 23 01:42:27 PM PDT 24
Finished May 23 01:42:34 PM PDT 24
Peak memory 211164 kb
Host smart-227bfc06-cb42-4fb8-829d-04309a467167
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3335666870 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_alert_test.3335666870
Directory /workspace/7.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/7.rom_ctrl_corrupt_sig_fatal_chk.4200935451
Short name T228
Test name
Test status
Simulation time 20599055459 ps
CPU time 217.86 seconds
Started May 23 01:42:29 PM PDT 24
Finished May 23 01:46:08 PM PDT 24
Peak memory 237888 kb
Host smart-5520f702-a7a7-4b9f-9195-71f333d72e50
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4200935451 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_c
orrupt_sig_fatal_chk.4200935451
Directory /workspace/7.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/7.rom_ctrl_kmac_err_chk.913641932
Short name T47
Test name
Test status
Simulation time 14618604854 ps
CPU time 29.52 seconds
Started May 23 01:42:27 PM PDT 24
Finished May 23 01:42:58 PM PDT 24
Peak memory 212628 kb
Host smart-e17d1614-dcd4-4b62-a084-1f1763b41005
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=913641932 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_kmac_err_chk.913641932
Directory /workspace/7.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/7.rom_ctrl_max_throughput_chk.1577772463
Short name T241
Test name
Test status
Simulation time 4040085724 ps
CPU time 16.71 seconds
Started May 23 01:42:24 PM PDT 24
Finished May 23 01:42:42 PM PDT 24
Peak memory 211208 kb
Host smart-09481766-6390-4d4d-992e-844edcf6246d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1577772463 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_max_throughput_chk.1577772463
Directory /workspace/7.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/7.rom_ctrl_smoke.2650427557
Short name T131
Test name
Test status
Simulation time 188813842 ps
CPU time 9.9 seconds
Started May 23 01:42:30 PM PDT 24
Finished May 23 01:42:41 PM PDT 24
Peak memory 213272 kb
Host smart-72627521-0917-4960-8a8e-5ff7393db123
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2650427557 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_smoke.2650427557
Directory /workspace/7.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/7.rom_ctrl_stress_all.82119925
Short name T345
Test name
Test status
Simulation time 4802141044 ps
CPU time 44.24 seconds
Started May 23 01:42:25 PM PDT 24
Finished May 23 01:43:11 PM PDT 24
Peak memory 216144 kb
Host smart-c32b94e8-9267-4ca8-bc89-a795a27f3761
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82119925 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +U
VM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n
ame 7.rom_ctrl_stress_all.82119925
Directory /workspace/7.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/7.rom_ctrl_stress_all_with_rand_reset.236823322
Short name T58
Test name
Test status
Simulation time 183752035392 ps
CPU time 1909.31 seconds
Started May 23 01:42:30 PM PDT 24
Finished May 23 02:14:21 PM PDT 24
Peak memory 238012 kb
Host smart-3360525a-f79c-4a2b-9829-57db44c187ff
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=236823322 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_stress_all_with_rand_reset.236823322
Directory /workspace/7.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.rom_ctrl_alert_test.2459841358
Short name T206
Test name
Test status
Simulation time 1262089483 ps
CPU time 11.8 seconds
Started May 23 01:42:33 PM PDT 24
Finished May 23 01:42:46 PM PDT 24
Peak memory 211208 kb
Host smart-f228d163-57a3-448f-acc2-817d9912fc99
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2459841358 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_alert_test.2459841358
Directory /workspace/8.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/8.rom_ctrl_corrupt_sig_fatal_chk.2084176172
Short name T27
Test name
Test status
Simulation time 82205590571 ps
CPU time 383.98 seconds
Started May 23 01:42:27 PM PDT 24
Finished May 23 01:48:53 PM PDT 24
Peak memory 218628 kb
Host smart-e9557add-b9e3-484e-b44f-9aab2e46ae2a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2084176172 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_c
orrupt_sig_fatal_chk.2084176172
Directory /workspace/8.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/8.rom_ctrl_kmac_err_chk.2444371505
Short name T165
Test name
Test status
Simulation time 15315884955 ps
CPU time 33.26 seconds
Started May 23 01:42:32 PM PDT 24
Finished May 23 01:43:07 PM PDT 24
Peak memory 212204 kb
Host smart-5f8457f8-d770-4bca-9520-a3d4d3320c2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2444371505 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_kmac_err_chk.2444371505
Directory /workspace/8.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/8.rom_ctrl_max_throughput_chk.1723223413
Short name T218
Test name
Test status
Simulation time 96156512 ps
CPU time 5.77 seconds
Started May 23 01:42:32 PM PDT 24
Finished May 23 01:42:39 PM PDT 24
Peak memory 211044 kb
Host smart-d16ed787-0eb4-46d8-bc12-0952ec3de68f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1723223413 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_max_throughput_chk.1723223413
Directory /workspace/8.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/8.rom_ctrl_smoke.641100825
Short name T81
Test name
Test status
Simulation time 13406587544 ps
CPU time 33.2 seconds
Started May 23 01:42:30 PM PDT 24
Finished May 23 01:43:05 PM PDT 24
Peak memory 219424 kb
Host smart-b180c10a-fcc9-4356-a344-62e1213b4f89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=641100825 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_smoke.641100825
Directory /workspace/8.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/8.rom_ctrl_stress_all.4162117027
Short name T319
Test name
Test status
Simulation time 1542742913 ps
CPU time 21.25 seconds
Started May 23 01:42:36 PM PDT 24
Finished May 23 01:42:58 PM PDT 24
Peak memory 216304 kb
Host smart-c9b486bb-a275-4a98-8ad3-6b12cb4a898b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4162117027 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 8.rom_ctrl_stress_all.4162117027
Directory /workspace/8.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/9.rom_ctrl_alert_test.2069053886
Short name T280
Test name
Test status
Simulation time 1954492898 ps
CPU time 15.84 seconds
Started May 23 01:42:29 PM PDT 24
Finished May 23 01:42:47 PM PDT 24
Peak memory 211256 kb
Host smart-e563ac5b-4d0f-46d0-ab96-2a292e3c3a64
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2069053886 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_alert_test.2069053886
Directory /workspace/9.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/9.rom_ctrl_corrupt_sig_fatal_chk.2276484956
Short name T212
Test name
Test status
Simulation time 38509804396 ps
CPU time 372.42 seconds
Started May 23 01:42:32 PM PDT 24
Finished May 23 01:48:46 PM PDT 24
Peak memory 237832 kb
Host smart-d7124125-9156-4a03-9d20-43eff6c70b6f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2276484956 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_c
orrupt_sig_fatal_chk.2276484956
Directory /workspace/9.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/9.rom_ctrl_kmac_err_chk.4012050279
Short name T48
Test name
Test status
Simulation time 2131713577 ps
CPU time 22.59 seconds
Started May 23 01:42:31 PM PDT 24
Finished May 23 01:42:55 PM PDT 24
Peak memory 212016 kb
Host smart-8c92647e-5e39-4feb-b704-dffda4c120f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4012050279 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_kmac_err_chk.4012050279
Directory /workspace/9.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/9.rom_ctrl_max_throughput_chk.1849802165
Short name T179
Test name
Test status
Simulation time 1193258250 ps
CPU time 12.38 seconds
Started May 23 01:42:36 PM PDT 24
Finished May 23 01:42:50 PM PDT 24
Peak memory 211068 kb
Host smart-6c1343b2-875c-42ad-b16b-6891307ed352
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1849802165 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_max_throughput_chk.1849802165
Directory /workspace/9.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/9.rom_ctrl_smoke.1239802597
Short name T279
Test name
Test status
Simulation time 1988913245 ps
CPU time 17.04 seconds
Started May 23 01:42:30 PM PDT 24
Finished May 23 01:42:49 PM PDT 24
Peak memory 213196 kb
Host smart-a403b019-e1fd-4a6e-a8ba-41d168d6cf08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1239802597 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_smoke.1239802597
Directory /workspace/9.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/9.rom_ctrl_stress_all.1948825382
Short name T159
Test name
Test status
Simulation time 6993420937 ps
CPU time 40.81 seconds
Started May 23 01:42:26 PM PDT 24
Finished May 23 01:43:09 PM PDT 24
Peak memory 212492 kb
Host smart-4f2cbcfe-b85b-42ec-bcbe-724fdadb2bc8
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1948825382 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 9.rom_ctrl_stress_all.1948825382
Directory /workspace/9.rom_ctrl_stress_all/latest
0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%